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authorArnd Bergmann <arnd@arndb.de>2013-06-21 08:57:38 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-21 08:57:38 -0400
commit30e544612c4c64eb992244607ac16aea79f824b7 (patch)
tree73bca9413c09dec2ed5d61091b97d257198e3295 /arch
parentc20e459fcc7d5d86a359b19f54362fb6fb77c6aa (diff)
parent53332005bfde9d2e3c9a66030c0e8c2598eaa1d5 (diff)
Merge tag 'renesas-cleanup-boot-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman: Renesas ARM based SoC boot cleanup for v3.11 Work by Magnus Damm and others to clean up the boot of and move things closer to supporting multi-arch. As a side effect of this work it was decided to remove support for two boards, Bonito and AP4EVB. Those patches are included in this series as they depend on earlier patches in the series. * tag 'renesas-cleanup-boot-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Remove Bonito board support ARM: shmobile: Remove AP4EVB board support ARM: shmobile: Remove mach/memory.h ARM: shmobile: Remove MEMORY_START/SIZE ARM: shmobile: Enable ARM_PATCH_PHYS_VIRT ARM: shmobile: Remove old SCU boot code ARM: shmobile: EMEV2 SMP with SCU boot fn and args ARM: shmobile: sh73a0 SMP with SCU boot fn and args ARM: shmobile: r8a7779 SMP with SCU boot fn and args ARM: shmobile: Add SCU boot function using argument ARM: shmobile: Add SMP boot function and argument ARM: shmobile: Rework sh7372 sleep code to use virt_to_phys() ARM: shmobile: Remove romImage CONFIG_MEMORY_START ARM: shmobile: Let romImage rely on default ATAGS ARM: shmobile: uImage load address rework Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/boot/compressed/head-shmobile.S21
-rw-r--r--arch/arm/configs/ap4evb_defconfig56
-rw-r--r--arch/arm/configs/bonito_defconfig72
-rw-r--r--arch/arm/mach-shmobile/Kconfig58
-rw-r--r--arch/arm/mach-shmobile/Makefile2
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot18
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c1310
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c502
-rw-r--r--arch/arm/mach-shmobile/headsmp-scu.S29
-rw-r--r--arch/arm/mach-shmobile/headsmp.S13
-rw-r--r--arch/arm/mach-shmobile/include/mach/common.h6
-rw-r--r--arch/arm/mach-shmobile/include/mach/head-ap4evb.txt93
-rw-r--r--arch/arm/mach-shmobile/include/mach/memory.h7
-rw-r--r--arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h29
-rw-r--r--arch/arm/mach-shmobile/include/mach/mmc.h4
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h2
-rw-r--r--arch/arm/mach-shmobile/include/mach/zboot.h6
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c3
-rw-r--r--arch/arm/mach-shmobile/sleep-sh7372.S5
-rw-r--r--arch/arm/mach-shmobile/smp-emev2.c6
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c6
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c6
23 files changed, 68 insertions, 2188 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ccd78c912cbf..db5aa5f2d1de 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -636,6 +636,7 @@ config ARCH_MSM
636 636
637config ARCH_SHMOBILE 637config ARCH_SHMOBILE
638 bool "Renesas SH-Mobile / R-Mobile" 638 bool "Renesas SH-Mobile / R-Mobile"
639 select ARM_PATCH_PHYS_VIRT
639 select CLKDEV_LOOKUP 640 select CLKDEV_LOOKUP
640 select GENERIC_CLOCKEVENTS 641 select GENERIC_CLOCKEVENTS
641 select HAVE_ARM_SCU if SMP 642 select HAVE_ARM_SCU if SMP
@@ -645,7 +646,6 @@ config ARCH_SHMOBILE
645 select HAVE_SMP 646 select HAVE_SMP
646 select MIGHT_HAVE_CACHE_L2X0 647 select MIGHT_HAVE_CACHE_L2X0
647 select MULTI_IRQ_HANDLER 648 select MULTI_IRQ_HANDLER
648 select NEED_MACH_MEMORY_H
649 select NO_IOPORT 649 select NO_IOPORT
650 select PINCTRL 650 select PINCTRL
651 select PM_GENERIC_DOMAINS if PM 651 select PM_GENERIC_DOMAINS if PM
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index fe3719b516fd..e2d636336b7c 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -46,7 +46,7 @@ __image_start:
46__image_end: 46__image_end:
47 .long _got_end 47 .long _got_end
48__load_base: 48__load_base:
49 .long CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM 49 .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
50__loaded: 50__loaded:
51 .long __continue 51 .long __continue
52 .align 52 .align
@@ -55,26 +55,9 @@ __tmp_stack:
55__continue: 55__continue:
56#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */ 56#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
57 57
58 b 1f
59__atags:@ tag #1
60 .long 12 @ tag->hdr.size = tag_size(tag_core);
61 .long 0x54410001 @ tag->hdr.tag = ATAG_CORE;
62 .long 0 @ tag->u.core.flags = 0;
63 .long 0 @ tag->u.core.pagesize = 0;
64 .long 0 @ tag->u.core.rootdev = 0;
65 @ tag #2
66 .long 8 @ tag->hdr.size = tag_size(tag_mem32);
67 .long 0x54410002 @ tag->hdr.tag = ATAG_MEM;
68 .long CONFIG_MEMORY_SIZE @ tag->u.mem.size = CONFIG_MEMORY_SIZE;
69 .long CONFIG_MEMORY_START @ @ tag->u.mem.start = CONFIG_MEMORY_START;
70 @ tag #3
71 .long 0 @ tag->hdr.size = 0
72 .long 0 @ tag->hdr.tag = ATAG_NONE;
731:
74
75 /* Set board ID necessary for boot */ 58 /* Set board ID necessary for boot */
76 ldr r7, 1f @ Set machine type register 59 ldr r7, 1f @ Set machine type register
77 adr r8, __atags @ Set atag register 60 mov r8, #0 @ pass null pointer as atag
78 b 2f 61 b 2f
79 62
801 : .long MACH_TYPE 631 : .long MACH_TYPE
diff --git a/arch/arm/configs/ap4evb_defconfig b/arch/arm/configs/ap4evb_defconfig
deleted file mode 100644
index 66894f736d04..000000000000
--- a/arch/arm/configs/ap4evb_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6CONFIG_BLK_DEV_INITRD=y
7CONFIG_SLAB=y
8# CONFIG_BLK_DEV_BSG is not set
9# CONFIG_IOSCHED_DEADLINE is not set
10# CONFIG_IOSCHED_CFQ is not set
11CONFIG_ARCH_SHMOBILE=y
12CONFIG_ARCH_SH7372=y
13CONFIG_MACH_AP4EVB=y
14CONFIG_AEABI=y
15# CONFIG_OABI_COMPAT is not set
16CONFIG_ZBOOT_ROM_TEXT=0x0
17CONFIG_ZBOOT_ROM_BSS=0x0
18CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200"
19CONFIG_KEXEC=y
20CONFIG_PM=y
21# CONFIG_SUSPEND is not set
22CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
23# CONFIG_FIRMWARE_IN_KERNEL is not set
24CONFIG_MTD=y
25CONFIG_MTD_CONCAT=y
26CONFIG_MTD_PARTITIONS=y
27CONFIG_MTD_CHAR=y
28CONFIG_MTD_BLOCK=y
29CONFIG_MTD_CFI=y
30CONFIG_MTD_CFI_INTELEXT=y
31CONFIG_MTD_PHYSMAP=y
32CONFIG_MTD_NAND=y
33# CONFIG_BLK_DEV is not set
34# CONFIG_MISC_DEVICES is not set
35# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
36# CONFIG_INPUT_KEYBOARD is not set
37# CONFIG_INPUT_MOUSE is not set
38# CONFIG_SERIO is not set
39CONFIG_SERIAL_SH_SCI=y
40CONFIG_SERIAL_SH_SCI_NR_UARTS=8
41CONFIG_SERIAL_SH_SCI_CONSOLE=y
42# CONFIG_LEGACY_PTYS is not set
43# CONFIG_HW_RANDOM is not set
44# CONFIG_HWMON is not set
45# CONFIG_VGA_CONSOLE is not set
46# CONFIG_HID_SUPPORT is not set
47# CONFIG_USB_SUPPORT is not set
48# CONFIG_DNOTIFY is not set
49CONFIG_TMPFS=y
50# CONFIG_MISC_FILESYSTEMS is not set
51CONFIG_MAGIC_SYSRQ=y
52CONFIG_DEBUG_KERNEL=y
53# CONFIG_DETECT_SOFTLOCKUP is not set
54# CONFIG_RCU_CPU_STALL_DETECTOR is not set
55# CONFIG_FTRACE is not set
56# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/bonito_defconfig b/arch/arm/configs/bonito_defconfig
deleted file mode 100644
index 54571082d920..000000000000
--- a/arch/arm/configs/bonito_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6# CONFIG_UTS_NS is not set
7# CONFIG_IPC_NS is not set
8# CONFIG_USER_NS is not set
9# CONFIG_PID_NS is not set
10CONFIG_BLK_DEV_INITRD=y
11CONFIG_INITRAMFS_SOURCE=""
12CONFIG_CC_OPTIMIZE_FOR_SIZE=y
13CONFIG_SLAB=y
14CONFIG_MODULES=y
15CONFIG_MODULE_UNLOAD=y
16CONFIG_MODULE_FORCE_UNLOAD=y
17# CONFIG_BLK_DEV_BSG is not set
18# CONFIG_IOSCHED_DEADLINE is not set
19# CONFIG_IOSCHED_CFQ is not set
20CONFIG_ARCH_SHMOBILE=y
21CONFIG_ARCH_R8A7740=y
22CONFIG_MACH_BONITO=y
23# CONFIG_SH_TIMER_TMU is not set
24CONFIG_AEABI=y
25# CONFIG_OABI_COMPAT is not set
26CONFIG_FORCE_MAX_ZONEORDER=12
27CONFIG_ZBOOT_ROM_TEXT=0x0
28CONFIG_ZBOOT_ROM_BSS=0x0
29CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
30CONFIG_KEXEC=y
31# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
32# CONFIG_SUSPEND is not set
33CONFIG_PM_RUNTIME=y
34CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
35# CONFIG_FIRMWARE_IN_KERNEL is not set
36CONFIG_MTD=y
37CONFIG_MTD_CHAR=y
38CONFIG_MTD_BLOCK=y
39CONFIG_MTD_CFI=y
40CONFIG_MTD_CFI_ADV_OPTIONS=y
41CONFIG_MTD_CFI_INTELEXT=y
42CONFIG_MTD_PHYSMAP=y
43CONFIG_MTD_ARM_INTEGRATOR=y
44CONFIG_MTD_BLOCK2MTD=y
45CONFIG_SCSI=y
46CONFIG_BLK_DEV_SD=y
47# CONFIG_SCSI_LOWLEVEL is not set
48# CONFIG_INPUT_KEYBOARD is not set
49# CONFIG_INPUT_MOUSE is not set
50# CONFIG_LEGACY_PTYS is not set
51CONFIG_SERIAL_SH_SCI=y
52CONFIG_SERIAL_SH_SCI_NR_UARTS=9
53CONFIG_SERIAL_SH_SCI_CONSOLE=y
54# CONFIG_HW_RANDOM is not set
55CONFIG_I2C=y
56CONFIG_I2C_CHARDEV=y
57CONFIG_I2C_SH_MOBILE=y
58CONFIG_GPIO_SYSFS=y
59# CONFIG_HWMON is not set
60# CONFIG_MFD_SUPPORT is not set
61# CONFIG_HID_SUPPORT is not set
62# CONFIG_USB_SUPPORT is not set
63CONFIG_UIO=y
64CONFIG_UIO_PDRV=y
65CONFIG_UIO_PDRV_GENIRQ=y
66# CONFIG_DNOTIFY is not set
67# CONFIG_INOTIFY_USER is not set
68CONFIG_TMPFS=y
69# CONFIG_MISC_FILESYSTEMS is not set
70# CONFIG_ENABLE_WARN_DEPRECATED is not set
71# CONFIG_ENABLE_MUST_CHECK is not set
72# CONFIG_ARM_UNWIND is not set
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 757c4e97375f..65e1547678b0 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -71,27 +71,6 @@ config ARCH_EMEV2
71 71
72comment "SH-Mobile Board Type" 72comment "SH-Mobile Board Type"
73 73
74config MACH_AP4EVB
75 bool "AP4EVB board"
76 depends on ARCH_SH7372
77 select ARCH_REQUIRE_GPIOLIB
78 select REGULATOR_FIXED_VOLTAGE if REGULATOR
79 select SH_LCD_MIPI_DSI
80 select SND_SOC_AK4642 if SND_SIMPLE_CARD
81
82choice
83 prompt "AP4EVB LCD panel selection"
84 default AP4EVB_QHD
85 depends on MACH_AP4EVB
86
87config AP4EVB_QHD
88 bool "MIPI-DSI QHD (960x540)"
89
90config AP4EVB_WVGA
91 bool "Parallel WVGA (800x480)"
92
93endchoice
94
95config MACH_AG5EVM 74config MACH_AG5EVM
96 bool "AG5EVM board" 75 bool "AG5EVM board"
97 depends on ARCH_SH73A0 76 depends on ARCH_SH73A0
@@ -118,12 +97,6 @@ config MACH_KOTA2
118 select ARCH_REQUIRE_GPIOLIB 97 select ARCH_REQUIRE_GPIOLIB
119 select REGULATOR_FIXED_VOLTAGE if REGULATOR 98 select REGULATOR_FIXED_VOLTAGE if REGULATOR
120 99
121config MACH_BONITO
122 bool "bonito board"
123 depends on ARCH_R8A7740
124 select ARCH_REQUIRE_GPIOLIB
125 select REGULATOR_FIXED_VOLTAGE if REGULATOR
126
127config MACH_ARMADILLO800EVA 100config MACH_ARMADILLO800EVA
128 bool "Armadillo-800 EVA board" 101 bool "Armadillo-800 EVA board"
129 depends on ARCH_R8A7740 102 depends on ARCH_R8A7740
@@ -199,37 +172,6 @@ config CPU_HAS_INTEVT
199 bool 172 bool
200 default y 173 default y
201 174
202menu "Memory configuration"
203
204config MEMORY_START
205 hex "Physical memory start address"
206 default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
207 MACH_MACKEREL || MACH_BONITO || \
208 MACH_ARMADILLO800EVA || MACH_APE6EVM || \
209 MACH_LAGER
210 default "0x41000000" if MACH_KOTA2
211 default "0x00000000"
212 ---help---
213 Tweak this only when porting to a new machine which does not
214 already have a defconfig. Changing it from the known correct
215 value on any of the known systems will only lead to disaster.
216
217config MEMORY_SIZE
218 hex "Physical memory size"
219 default "0x80000000" if MACH_LAGER
220 default "0x40000000" if MACH_APE6EVM
221 default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
222 MACH_ARMADILLO800EVA
223 default "0x1e000000" if MACH_KOTA2
224 default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
225 default "0x04000000"
226 help
227 This sets the default memory size assumed by your kernel. It can
228 be overridden as normal by the 'mem=' argument on the kernel command
229 line.
230
231endmenu
232
233menu "Timer and clock configuration" 175menu "Timer and clock configuration"
234 176
235config SHMOBILE_TIMER_HZ 177config SHMOBILE_TIMER_HZ
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 068f1dadc46b..76f1639c5945 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -35,12 +35,10 @@ obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
35obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o 35obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
36 36
37# Board objects 37# Board objects
38obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
39obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o 38obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
40obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o 39obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
41obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o 40obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
42obj-$(CONFIG_MACH_KOTA2) += board-kota2.o 41obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
43obj-$(CONFIG_MACH_BONITO) += board-bonito.o
44obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 42obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
45obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 43obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
46obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o 44obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index 498efd99338d..84c6868580f0 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -1,6 +1,20 @@
1__ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \ 1# per-board load address for uImage
2 $$[$(CONFIG_MEMORY_START) + 0x8000]') 2loadaddr-y :=
3loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000
4loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
5loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
6loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
7loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
8loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000
9loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
10loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
11loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
12loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
13loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
14loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
15loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
3 16
17__ZRELADDR := $(sort $(loadaddr-y))
4 zreladdr-y += $(__ZRELADDR) 18 zreladdr-y += $(__ZRELADDR)
5 19
6# Unsupported legacy stuff 20# Unsupported legacy stuff
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
deleted file mode 100644
index 297bf5eec5ab..000000000000
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ /dev/null
@@ -1,1310 +0,0 @@
1/*
2 * AP4EVB board support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/clk.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/delay.h>
27#include <linux/mfd/tmio.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/sh_mobile_sdhi.h>
30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h>
33#include <linux/mmc/sh_mmcif.h>
34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h>
36#include <linux/io.h>
37#include <linux/pinctrl/machine.h>
38#include <linux/regulator/fixed.h>
39#include <linux/regulator/machine.h>
40#include <linux/smsc911x.h>
41#include <linux/sh_intc.h>
42#include <linux/sh_clk.h>
43#include <linux/gpio.h>
44#include <linux/input.h>
45#include <linux/leds.h>
46#include <linux/input/sh_keysc.h>
47#include <linux/usb/r8a66597.h>
48#include <linux/pm_clock.h>
49#include <linux/dma-mapping.h>
50
51#include <media/sh_mobile_ceu.h>
52#include <media/sh_mobile_csi2.h>
53#include <media/soc_camera.h>
54
55#include <sound/sh_fsi.h>
56#include <sound/simple_card.h>
57
58#include <video/sh_mobile_hdmi.h>
59#include <video/sh_mobile_lcdc.h>
60#include <video/sh_mipi_dsi.h>
61
62#include <mach/common.h>
63#include <mach/irqs.h>
64#include <mach/sh7372.h>
65
66#include <asm/mach-types.h>
67#include <asm/mach/arch.h>
68#include <asm/setup.h>
69
70#include "sh-gpio.h"
71
72/*
73 * Address Interface BusWidth note
74 * ------------------------------------------------------------------
75 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
76 * 0x0800_0000 user area -
77 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
78 * 0x1400_0000 Ether (LAN9220) 16bit
79 * 0x1600_0000 user area - cannot use with NAND
80 * 0x1800_0000 user area -
81 * 0x1A00_0000 -
82 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
83 */
84
85/*
86 * NOR Flash ROM
87 *
88 * SW1 | SW2 | SW7 | NOR Flash ROM
89 * bit1 | bit1 bit2 | bit1 | Memory allocation
90 * ------+------------+------+------------------
91 * OFF | ON OFF | ON | Area 0
92 * OFF | ON OFF | OFF | Area 4
93 */
94
95/*
96 * NAND Flash ROM
97 *
98 * SW1 | SW2 | SW7 | NAND Flash ROM
99 * bit1 | bit1 bit2 | bit2 | Memory allocation
100 * ------+------------+------+------------------
101 * OFF | ON OFF | ON | FCE 0
102 * OFF | ON OFF | OFF | FCE 1
103 */
104
105/*
106 * SMSC 9220
107 *
108 * SW1 SMSC 9220
109 * -----------------------
110 * ON access disable
111 * OFF access enable
112 */
113
114/*
115 * LCD / IRQ / KEYSC / IrDA
116 *
117 * IRQ = IRQ26 (TS), IRQ27 (VIO), IRQ28 (QHD-TouchScreen)
118 * LCD = 2nd LCDC (WVGA)
119 *
120 * | SW43 |
121 * SW3 | ON | OFF |
122 * -------------+-----------------------+---------------+
123 * ON | KEY / IrDA | LCD |
124 * OFF | KEY / IrDA / IRQ | IRQ |
125 *
126 *
127 * QHD / WVGA display
128 *
129 * You can choice display type on menuconfig.
130 * Then, check above dip-switch.
131 */
132
133/*
134 * USB
135 *
136 * J7 : 1-2 MAX3355E VBUS
137 * 2-3 DC 5.0V
138 *
139 * S39: bit2: off
140 */
141
142/*
143 * FSI/FSMI
144 *
145 * SW41 : ON : SH-Mobile AP4 Audio Mode
146 * : OFF : Bluetooth Audio Mode
147 *
148 * it needs amixer settings for playing
149 *
150 * amixer set "Headphone Enable" on
151 */
152
153/*
154 * MMC0/SDHI1 (CN7)
155 *
156 * J22 : select card voltage
157 * 1-2 pin : 1.8v
158 * 2-3 pin : 3.3v
159 *
160 * SW1 | SW33
161 * | bit1 | bit2 | bit3 | bit4
162 * ------------+------+------+------+-------
163 * MMC0 OFF | OFF | ON | ON | X
164 * SDHI1 OFF | ON | X | OFF | ON
165 *
166 * voltage lebel
167 * CN7 : 1.8v
168 * CN12: 3.3v
169 */
170
171/* Dummy supplies, where voltage doesn't matter */
172static struct regulator_consumer_supply fixed1v8_power_consumers[] =
173{
174 /* J22 default position: 1.8V */
175 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
176 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
177 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
178 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
179};
180
181static struct regulator_consumer_supply fixed3v3_power_consumers[] =
182{
183 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
184 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
185};
186
187static struct regulator_consumer_supply dummy_supplies[] = {
188 REGULATOR_SUPPLY("vddvario", "smsc911x"),
189 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
190};
191
192/* MTD */
193static struct mtd_partition nor_flash_partitions[] = {
194 {
195 .name = "loader",
196 .offset = 0x00000000,
197 .size = 512 * 1024,
198 .mask_flags = MTD_WRITEABLE,
199 },
200 {
201 .name = "bootenv",
202 .offset = MTDPART_OFS_APPEND,
203 .size = 512 * 1024,
204 .mask_flags = MTD_WRITEABLE,
205 },
206 {
207 .name = "kernel_ro",
208 .offset = MTDPART_OFS_APPEND,
209 .size = 8 * 1024 * 1024,
210 .mask_flags = MTD_WRITEABLE,
211 },
212 {
213 .name = "kernel",
214 .offset = MTDPART_OFS_APPEND,
215 .size = 8 * 1024 * 1024,
216 },
217 {
218 .name = "data",
219 .offset = MTDPART_OFS_APPEND,
220 .size = MTDPART_SIZ_FULL,
221 },
222};
223
224static struct physmap_flash_data nor_flash_data = {
225 .width = 2,
226 .parts = nor_flash_partitions,
227 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
228};
229
230static struct resource nor_flash_resources[] = {
231 [0] = {
232 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
233 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
234 .flags = IORESOURCE_MEM,
235 }
236};
237
238static struct platform_device nor_flash_device = {
239 .name = "physmap-flash",
240 .dev = {
241 .platform_data = &nor_flash_data,
242 },
243 .num_resources = ARRAY_SIZE(nor_flash_resources),
244 .resource = nor_flash_resources,
245};
246
247/* SMSC 9220 */
248static struct resource smc911x_resources[] = {
249 {
250 .start = 0x14000000,
251 .end = 0x16000000 - 1,
252 .flags = IORESOURCE_MEM,
253 }, {
254 .start = evt2irq(0x02c0) /* IRQ6A */,
255 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
256 },
257};
258
259static struct smsc911x_platform_config smsc911x_info = {
260 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
261 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
262 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
263};
264
265static struct platform_device smc911x_device = {
266 .name = "smsc911x",
267 .id = -1,
268 .num_resources = ARRAY_SIZE(smc911x_resources),
269 .resource = smc911x_resources,
270 .dev = {
271 .platform_data = &smsc911x_info,
272 },
273};
274
275/*
276 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
277 * connected to GPIO A22 of SH7372 (GPIO 41).
278 */
279static int slot_cn7_get_cd(struct platform_device *pdev)
280{
281 return !gpio_get_value(41);
282}
283/* MERAM */
284static struct sh_mobile_meram_info meram_info = {
285 .addr_mode = SH_MOBILE_MERAM_MODE1,
286};
287
288static struct resource meram_resources[] = {
289 [0] = {
290 .name = "regs",
291 .start = 0xe8000000,
292 .end = 0xe807ffff,
293 .flags = IORESOURCE_MEM,
294 },
295 [1] = {
296 .name = "meram",
297 .start = 0xe8080000,
298 .end = 0xe81fffff,
299 .flags = IORESOURCE_MEM,
300 },
301};
302
303static struct platform_device meram_device = {
304 .name = "sh_mobile_meram",
305 .id = 0,
306 .num_resources = ARRAY_SIZE(meram_resources),
307 .resource = meram_resources,
308 .dev = {
309 .platform_data = &meram_info,
310 },
311};
312
313/* SH_MMCIF */
314static struct resource sh_mmcif_resources[] = {
315 [0] = {
316 .name = "MMCIF",
317 .start = 0xE6BD0000,
318 .end = 0xE6BD00FF,
319 .flags = IORESOURCE_MEM,
320 },
321 [1] = {
322 /* MMC ERR */
323 .start = evt2irq(0x1ac0),
324 .flags = IORESOURCE_IRQ,
325 },
326 [2] = {
327 /* MMC NOR */
328 .start = evt2irq(0x1ae0),
329 .flags = IORESOURCE_IRQ,
330 },
331};
332
333static struct sh_mmcif_plat_data sh_mmcif_plat = {
334 .sup_pclk = 0,
335 .ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
336 .caps = MMC_CAP_4_BIT_DATA |
337 MMC_CAP_8_BIT_DATA |
338 MMC_CAP_NEEDS_POLL,
339 .get_cd = slot_cn7_get_cd,
340 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
341 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
342};
343
344static struct platform_device sh_mmcif_device = {
345 .name = "sh_mmcif",
346 .id = 0,
347 .dev = {
348 .dma_mask = NULL,
349 .coherent_dma_mask = 0xffffffff,
350 .platform_data = &sh_mmcif_plat,
351 },
352 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
353 .resource = sh_mmcif_resources,
354};
355
356/* SDHI0 */
357static struct sh_mobile_sdhi_info sdhi0_info = {
358 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
359 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
360 .tmio_caps = MMC_CAP_SDIO_IRQ,
361};
362
363static struct resource sdhi0_resources[] = {
364 [0] = {
365 .name = "SDHI0",
366 .start = 0xe6850000,
367 .end = 0xe68500ff,
368 .flags = IORESOURCE_MEM,
369 },
370 [1] = {
371 .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
372 .flags = IORESOURCE_IRQ,
373 },
374 [2] = {
375 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
376 .flags = IORESOURCE_IRQ,
377 },
378 [3] = {
379 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
380 .flags = IORESOURCE_IRQ,
381 },
382};
383
384static struct platform_device sdhi0_device = {
385 .name = "sh_mobile_sdhi",
386 .num_resources = ARRAY_SIZE(sdhi0_resources),
387 .resource = sdhi0_resources,
388 .id = 0,
389 .dev = {
390 .platform_data = &sdhi0_info,
391 },
392};
393
394/* SDHI1 */
395static struct sh_mobile_sdhi_info sdhi1_info = {
396 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
397 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
398 .tmio_ocr_mask = MMC_VDD_165_195,
399 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
400 .tmio_caps = MMC_CAP_NEEDS_POLL | MMC_CAP_SDIO_IRQ,
401 .get_cd = slot_cn7_get_cd,
402};
403
404static struct resource sdhi1_resources[] = {
405 [0] = {
406 .name = "SDHI1",
407 .start = 0xe6860000,
408 .end = 0xe68600ff,
409 .flags = IORESOURCE_MEM,
410 },
411 [1] = {
412 .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
413 .flags = IORESOURCE_IRQ,
414 },
415 [2] = {
416 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
417 .flags = IORESOURCE_IRQ,
418 },
419 [3] = {
420 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
421 .flags = IORESOURCE_IRQ,
422 },
423};
424
425static struct platform_device sdhi1_device = {
426 .name = "sh_mobile_sdhi",
427 .num_resources = ARRAY_SIZE(sdhi1_resources),
428 .resource = sdhi1_resources,
429 .id = 1,
430 .dev = {
431 .platform_data = &sdhi1_info,
432 },
433};
434
435/* USB1 */
436static void usb1_host_port_power(int port, int power)
437{
438 if (!power) /* only power-on supported for now */
439 return;
440
441 /* set VBOUT/PWEN and EXTLP1 in DVSTCTR */
442 __raw_writew(__raw_readw(IOMEM(0xE68B0008)) | 0x600, IOMEM(0xE68B0008));
443}
444
445static struct r8a66597_platdata usb1_host_data = {
446 .on_chip = 1,
447 .port_power = usb1_host_port_power,
448};
449
450static struct resource usb1_host_resources[] = {
451 [0] = {
452 .name = "USBHS",
453 .start = 0xE68B0000,
454 .end = 0xE68B00E6 - 1,
455 .flags = IORESOURCE_MEM,
456 },
457 [1] = {
458 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
459 .flags = IORESOURCE_IRQ,
460 },
461};
462
463static struct platform_device usb1_host_device = {
464 .name = "r8a66597_hcd",
465 .id = 1,
466 .dev = {
467 .dma_mask = NULL, /* not use dma */
468 .coherent_dma_mask = 0xffffffff,
469 .platform_data = &usb1_host_data,
470 },
471 .num_resources = ARRAY_SIZE(usb1_host_resources),
472 .resource = usb1_host_resources,
473};
474
475/*
476 * QHD display
477 */
478#ifdef CONFIG_AP4EVB_QHD
479
480/* KEYSC (Needs SW43 set to ON) */
481static struct sh_keysc_info keysc_info = {
482 .mode = SH_KEYSC_MODE_1,
483 .scan_timing = 3,
484 .delay = 2500,
485 .keycodes = {
486 KEY_0, KEY_1, KEY_2, KEY_3, KEY_4,
487 KEY_5, KEY_6, KEY_7, KEY_8, KEY_9,
488 KEY_A, KEY_B, KEY_C, KEY_D, KEY_E,
489 KEY_F, KEY_G, KEY_H, KEY_I, KEY_J,
490 KEY_K, KEY_L, KEY_M, KEY_N, KEY_O,
491 },
492};
493
494static struct resource keysc_resources[] = {
495 [0] = {
496 .name = "KEYSC",
497 .start = 0xe61b0000,
498 .end = 0xe61b0063,
499 .flags = IORESOURCE_MEM,
500 },
501 [1] = {
502 .start = evt2irq(0x0be0), /* KEYSC_KEY */
503 .flags = IORESOURCE_IRQ,
504 },
505};
506
507static struct platform_device keysc_device = {
508 .name = "sh_keysc",
509 .id = 0, /* "keysc0" clock */
510 .num_resources = ARRAY_SIZE(keysc_resources),
511 .resource = keysc_resources,
512 .dev = {
513 .platform_data = &keysc_info,
514 },
515};
516
517/* MIPI-DSI */
518static int sh_mipi_set_dot_clock(struct platform_device *pdev,
519 void __iomem *base,
520 int enable)
521{
522 struct clk *pck = clk_get(&pdev->dev, "dsip_clk");
523
524 if (IS_ERR(pck))
525 return PTR_ERR(pck);
526
527 if (enable) {
528 /*
529 * DSIPCLK = 24MHz
530 * D-PHY = DSIPCLK * ((0x6*2)+1) = 312MHz (see .phyctrl)
531 * HsByteCLK = D-PHY/8 = 39MHz
532 *
533 * X * Y * FPS =
534 * (544+72+600+16) * (961+8+8+2) * 30 = 36.1MHz
535 */
536 clk_set_rate(pck, clk_round_rate(pck, 24000000));
537 clk_enable(pck);
538 } else {
539 clk_disable(pck);
540 }
541
542 clk_put(pck);
543
544 return 0;
545}
546
547static struct resource mipidsi0_resources[] = {
548 [0] = {
549 .start = 0xffc60000,
550 .end = 0xffc63073,
551 .flags = IORESOURCE_MEM,
552 },
553 [1] = {
554 .start = 0xffc68000,
555 .end = 0xffc680ef,
556 .flags = IORESOURCE_MEM,
557 },
558};
559
560static struct sh_mipi_dsi_info mipidsi0_info = {
561 .data_format = MIPI_RGB888,
562 .channel = LCDC_CHAN_MAINLCD,
563 .lane = 2,
564 .vsynw_offset = 17,
565 .phyctrl = 0x6 << 8,
566 .flags = SH_MIPI_DSI_SYNC_PULSES_MODE |
567 SH_MIPI_DSI_HSbyteCLK,
568 .set_dot_clock = sh_mipi_set_dot_clock,
569};
570
571static struct platform_device mipidsi0_device = {
572 .name = "sh-mipi-dsi",
573 .num_resources = ARRAY_SIZE(mipidsi0_resources),
574 .resource = mipidsi0_resources,
575 .id = 0,
576 .dev = {
577 .platform_data = &mipidsi0_info,
578 },
579};
580
581static struct platform_device *qhd_devices[] __initdata = {
582 &mipidsi0_device,
583 &keysc_device,
584};
585#endif /* CONFIG_AP4EVB_QHD */
586
587/* LCDC0 */
588static const struct fb_videomode ap4evb_lcdc_modes[] = {
589 {
590#ifdef CONFIG_AP4EVB_QHD
591 .name = "R63302(QHD)",
592 .xres = 544,
593 .yres = 961,
594 .left_margin = 72,
595 .right_margin = 600,
596 .hsync_len = 16,
597 .upper_margin = 8,
598 .lower_margin = 8,
599 .vsync_len = 2,
600 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
601#else
602 .name = "WVGA Panel",
603 .xres = 800,
604 .yres = 480,
605 .left_margin = 220,
606 .right_margin = 110,
607 .hsync_len = 70,
608 .upper_margin = 20,
609 .lower_margin = 5,
610 .vsync_len = 5,
611 .sync = 0,
612#endif
613 },
614};
615
616static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
617 .icb[0] = {
618 .meram_size = 0x40,
619 },
620 .icb[1] = {
621 .meram_size = 0x40,
622 },
623};
624
625static struct sh_mobile_lcdc_info lcdc_info = {
626 .meram_dev = &meram_info,
627 .ch[0] = {
628 .chan = LCDC_CHAN_MAINLCD,
629 .fourcc = V4L2_PIX_FMT_RGB565,
630 .lcd_modes = ap4evb_lcdc_modes,
631 .num_modes = ARRAY_SIZE(ap4evb_lcdc_modes),
632 .meram_cfg = &lcd_meram_cfg,
633#ifdef CONFIG_AP4EVB_QHD
634 .tx_dev = &mipidsi0_device,
635#endif
636 }
637};
638
639static struct resource lcdc_resources[] = {
640 [0] = {
641 .name = "LCDC",
642 .start = 0xfe940000, /* P4-only space */
643 .end = 0xfe943fff,
644 .flags = IORESOURCE_MEM,
645 },
646 [1] = {
647 .start = intcs_evt2irq(0x580),
648 .flags = IORESOURCE_IRQ,
649 },
650};
651
652static struct platform_device lcdc_device = {
653 .name = "sh_mobile_lcdc_fb",
654 .num_resources = ARRAY_SIZE(lcdc_resources),
655 .resource = lcdc_resources,
656 .dev = {
657 .platform_data = &lcdc_info,
658 .coherent_dma_mask = ~0,
659 },
660};
661
662/* FSI */
663#define IRQ_FSI evt2irq(0x1840)
664static struct sh_fsi_platform_info fsi_info = {
665 .port_b = {
666 .flags = SH_FSI_CLK_CPG |
667 SH_FSI_FMT_SPDIF,
668 },
669};
670
671static struct resource fsi_resources[] = {
672 [0] = {
673 .name = "FSI",
674 .start = 0xFE3C0000,
675 .end = 0xFE3C0400 - 1,
676 .flags = IORESOURCE_MEM,
677 },
678 [1] = {
679 .start = IRQ_FSI,
680 .flags = IORESOURCE_IRQ,
681 },
682};
683
684static struct platform_device fsi_device = {
685 .name = "sh_fsi2",
686 .id = -1,
687 .num_resources = ARRAY_SIZE(fsi_resources),
688 .resource = fsi_resources,
689 .dev = {
690 .platform_data = &fsi_info,
691 },
692};
693
694static struct asoc_simple_card_info fsi2_ak4643_info = {
695 .name = "AK4643",
696 .card = "FSI2A-AK4643",
697 .codec = "ak4642-codec.0-0013",
698 .platform = "sh_fsi2",
699 .daifmt = SND_SOC_DAIFMT_LEFT_J,
700 .cpu_dai = {
701 .name = "fsia-dai",
702 .fmt = SND_SOC_DAIFMT_CBS_CFS,
703 },
704 .codec_dai = {
705 .name = "ak4642-hifi",
706 .fmt = SND_SOC_DAIFMT_CBM_CFM,
707 .sysclk = 11289600,
708 },
709};
710
711static struct platform_device fsi_ak4643_device = {
712 .name = "asoc-simple-card",
713 .dev = {
714 .platform_data = &fsi2_ak4643_info,
715 },
716};
717
718/* LCDC1 */
719static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
720 unsigned long *parent_freq);
721
722static struct sh_mobile_hdmi_info hdmi_info = {
723 .flags = HDMI_SND_SRC_SPDIF,
724 .clk_optimize_parent = ap4evb_clk_optimize,
725};
726
727static struct resource hdmi_resources[] = {
728 [0] = {
729 .name = "HDMI",
730 .start = 0xe6be0000,
731 .end = 0xe6be00ff,
732 .flags = IORESOURCE_MEM,
733 },
734 [1] = {
735 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
736 .start = evt2irq(0x17e0),
737 .flags = IORESOURCE_IRQ,
738 },
739};
740
741static struct platform_device hdmi_device = {
742 .name = "sh-mobile-hdmi",
743 .num_resources = ARRAY_SIZE(hdmi_resources),
744 .resource = hdmi_resources,
745 .id = -1,
746 .dev = {
747 .platform_data = &hdmi_info,
748 },
749};
750
751static long ap4evb_clk_optimize(unsigned long target, unsigned long *best_freq,
752 unsigned long *parent_freq)
753{
754 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
755 long error;
756
757 if (IS_ERR(hdmi_ick)) {
758 int ret = PTR_ERR(hdmi_ick);
759 pr_err("Cannot get HDMI ICK: %d\n", ret);
760 return ret;
761 }
762
763 error = clk_round_parent(hdmi_ick, target, best_freq, parent_freq, 1, 64);
764
765 clk_put(hdmi_ick);
766
767 return error;
768}
769
770static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
771 .icb[0] = {
772 .meram_size = 0x100,
773 },
774 .icb[1] = {
775 .meram_size = 0x100,
776 },
777};
778
779static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
780 .clock_source = LCDC_CLK_EXTERNAL,
781 .meram_dev = &meram_info,
782 .ch[0] = {
783 .chan = LCDC_CHAN_MAINLCD,
784 .fourcc = V4L2_PIX_FMT_RGB565,
785 .interface_type = RGB24,
786 .clock_divider = 1,
787 .flags = LCDC_FLAGS_DWPOL,
788 .meram_cfg = &hdmi_meram_cfg,
789 .tx_dev = &hdmi_device,
790 }
791};
792
793static struct resource lcdc1_resources[] = {
794 [0] = {
795 .name = "LCDC1",
796 .start = 0xfe944000,
797 .end = 0xfe947fff,
798 .flags = IORESOURCE_MEM,
799 },
800 [1] = {
801 .start = intcs_evt2irq(0x1780),
802 .flags = IORESOURCE_IRQ,
803 },
804};
805
806static struct platform_device lcdc1_device = {
807 .name = "sh_mobile_lcdc_fb",
808 .num_resources = ARRAY_SIZE(lcdc1_resources),
809 .resource = lcdc1_resources,
810 .id = 1,
811 .dev = {
812 .platform_data = &sh_mobile_lcdc1_info,
813 .coherent_dma_mask = ~0,
814 },
815};
816
817static struct asoc_simple_card_info fsi2_hdmi_info = {
818 .name = "HDMI",
819 .card = "FSI2B-HDMI",
820 .codec = "sh-mobile-hdmi",
821 .platform = "sh_fsi2",
822 .cpu_dai = {
823 .name = "fsib-dai",
824 .fmt = SND_SOC_DAIFMT_CBM_CFM | SND_SOC_DAIFMT_IB_NF,
825 },
826 .codec_dai = {
827 .name = "sh_mobile_hdmi-hifi",
828 },
829};
830
831static struct platform_device fsi_hdmi_device = {
832 .name = "asoc-simple-card",
833 .id = 1,
834 .dev = {
835 .platform_data = &fsi2_hdmi_info,
836 },
837};
838
839static struct gpio_led ap4evb_leds[] = {
840 {
841 .name = "led4",
842 .gpio = 185,
843 .default_state = LEDS_GPIO_DEFSTATE_ON,
844 },
845 {
846 .name = "led2",
847 .gpio = 186,
848 .default_state = LEDS_GPIO_DEFSTATE_ON,
849 },
850 {
851 .name = "led3",
852 .gpio = 187,
853 .default_state = LEDS_GPIO_DEFSTATE_ON,
854 },
855 {
856 .name = "led1",
857 .gpio = 188,
858 .default_state = LEDS_GPIO_DEFSTATE_ON,
859 }
860};
861
862static struct gpio_led_platform_data ap4evb_leds_pdata = {
863 .num_leds = ARRAY_SIZE(ap4evb_leds),
864 .leds = ap4evb_leds,
865};
866
867static struct platform_device leds_device = {
868 .name = "leds-gpio",
869 .id = 0,
870 .dev = {
871 .platform_data = &ap4evb_leds_pdata,
872 },
873};
874
875static struct i2c_board_info imx074_info = {
876 I2C_BOARD_INFO("imx074", 0x1a),
877};
878
879static struct soc_camera_link imx074_link = {
880 .bus_id = 0,
881 .board_info = &imx074_info,
882 .i2c_adapter_id = 0,
883 .module_name = "imx074",
884};
885
886static struct platform_device ap4evb_camera = {
887 .name = "soc-camera-pdrv",
888 .id = 0,
889 .dev = {
890 .platform_data = &imx074_link,
891 },
892};
893
894static struct sh_csi2_client_config csi2_clients[] = {
895 {
896 .phy = SH_CSI2_PHY_MAIN,
897 .lanes = 0, /* default: 2 lanes */
898 .channel = 0,
899 .pdev = &ap4evb_camera,
900 },
901};
902
903static struct sh_csi2_pdata csi2_info = {
904 .type = SH_CSI2C,
905 .clients = csi2_clients,
906 .num_clients = ARRAY_SIZE(csi2_clients),
907 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
908};
909
910static struct resource csi2_resources[] = {
911 [0] = {
912 .name = "CSI2",
913 .start = 0xffc90000,
914 .end = 0xffc90fff,
915 .flags = IORESOURCE_MEM,
916 },
917 [1] = {
918 .start = intcs_evt2irq(0x17a0),
919 .flags = IORESOURCE_IRQ,
920 },
921};
922
923static struct sh_mobile_ceu_companion csi2 = {
924 .id = 0,
925 .num_resources = ARRAY_SIZE(csi2_resources),
926 .resource = csi2_resources,
927 .platform_data = &csi2_info,
928};
929
930static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
931 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
932 .max_width = 8188,
933 .max_height = 8188,
934 .csi2 = &csi2,
935};
936
937static struct resource ceu_resources[] = {
938 [0] = {
939 .name = "CEU",
940 .start = 0xfe910000,
941 .end = 0xfe91009f,
942 .flags = IORESOURCE_MEM,
943 },
944 [1] = {
945 .start = intcs_evt2irq(0x880),
946 .flags = IORESOURCE_IRQ,
947 },
948 [2] = {
949 /* place holder for contiguous memory */
950 },
951};
952
953static struct platform_device ceu_device = {
954 .name = "sh_mobile_ceu",
955 .id = 0, /* "ceu0" clock */
956 .num_resources = ARRAY_SIZE(ceu_resources),
957 .resource = ceu_resources,
958 .dev = {
959 .platform_data = &sh_mobile_ceu_info,
960 .coherent_dma_mask = 0xffffffff,
961 },
962};
963
964static struct platform_device *ap4evb_devices[] __initdata = {
965 &leds_device,
966 &nor_flash_device,
967 &smc911x_device,
968 &sdhi0_device,
969 &sdhi1_device,
970 &usb1_host_device,
971 &fsi_device,
972 &fsi_ak4643_device,
973 &fsi_hdmi_device,
974 &sh_mmcif_device,
975 &hdmi_device,
976 &lcdc_device,
977 &lcdc1_device,
978 &ceu_device,
979 &ap4evb_camera,
980 &meram_device,
981};
982
983static void __init hdmi_init_pm_clock(void)
984{
985 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
986 int ret;
987 long rate;
988
989 if (IS_ERR(hdmi_ick)) {
990 ret = PTR_ERR(hdmi_ick);
991 pr_err("Cannot get HDMI ICK: %d\n", ret);
992 goto out;
993 }
994
995 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
996 if (ret < 0) {
997 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
998 goto out;
999 }
1000
1001 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
1002
1003 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
1004 if (rate < 0) {
1005 pr_err("Cannot get suitable rate: %ld\n", rate);
1006 ret = rate;
1007 goto out;
1008 }
1009
1010 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
1011 if (ret < 0) {
1012 pr_err("Cannot set rate %ld: %d\n", rate, ret);
1013 goto out;
1014 }
1015
1016 pr_debug("PLLC2 set frequency %lu\n", rate);
1017
1018 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
1019 if (ret < 0)
1020 pr_err("Cannot set HDMI parent: %d\n", ret);
1021
1022out:
1023 if (!IS_ERR(hdmi_ick))
1024 clk_put(hdmi_ick);
1025}
1026
1027/* TouchScreen */
1028#ifdef CONFIG_AP4EVB_QHD
1029# define GPIO_TSC_PORT 123
1030#else /* WVGA */
1031# define GPIO_TSC_PORT 40
1032#endif
1033
1034#define IRQ28 evt2irq(0x3380) /* IRQ28A */
1035#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
1036static int ts_get_pendown_state(void)
1037{
1038 return !gpio_get_value(GPIO_TSC_PORT);
1039}
1040
1041static int ts_init(void)
1042{
1043 gpio_request_one(GPIO_TSC_PORT, GPIOF_IN, NULL);
1044
1045 return 0;
1046}
1047
1048static struct tsc2007_platform_data tsc2007_info = {
1049 .model = 2007,
1050 .x_plate_ohms = 180,
1051 .get_pendown_state = ts_get_pendown_state,
1052 .init_platform_hw = ts_init,
1053};
1054
1055static struct i2c_board_info tsc_device = {
1056 I2C_BOARD_INFO("tsc2007", 0x48),
1057 .type = "tsc2007",
1058 .platform_data = &tsc2007_info,
1059 /*.irq is selected on ap4evb_init */
1060};
1061
1062/* I2C */
1063static struct i2c_board_info i2c0_devices[] = {
1064 {
1065 I2C_BOARD_INFO("ak4643", 0x13),
1066 },
1067};
1068
1069static struct i2c_board_info i2c1_devices[] = {
1070 {
1071 I2C_BOARD_INFO("r2025sd", 0x32),
1072 },
1073};
1074
1075
1076static const struct pinctrl_map ap4evb_pinctrl_map[] = {
1077 /* CEU */
1078 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
1079 "ceu_clk_0", "ceu"),
1080 /* FSIA (AK4643) */
1081 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1082 "fsia_sclk_in", "fsia"),
1083 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1084 "fsia_data_in", "fsia"),
1085 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1086 "fsia_data_out", "fsia"),
1087 /* FSIB (HDMI) */
1088 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
1089 "fsib_mclk_in", "fsib"),
1090 /* HDMI */
1091 PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
1092 "hdmi", "hdmi"),
1093 /* KEYSC */
1094 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
1095 "keysc_in04_0", "keysc"),
1096 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc", "pfc-sh7372",
1097 "keysc_out5", "keysc"),
1098#ifndef CONFIG_AP4EVB_QHD
1099 /* LCDC */
1100 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
1101 "lcd_data18", "lcd"),
1102 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
1103 "lcd_sync", "lcd"),
1104#endif
1105 /* MMCIF */
1106 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1107 "mmc0_data8_0", "mmc0"),
1108 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1109 "mmc0_ctrl_0", "mmc0"),
1110 /* SCIFA0 */
1111 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
1112 "scifa0_data", "scifa0"),
1113 /* SDHI0 */
1114 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1115 "sdhi0_data4", "sdhi0"),
1116 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1117 "sdhi0_ctrl", "sdhi0"),
1118 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1119 "sdhi0_cd", "sdhi0"),
1120 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1121 "sdhi0_wp", "sdhi0"),
1122 /* SDHI1 */
1123 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1124 "sdhi1_data4", "sdhi1"),
1125 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1126 "sdhi1_ctrl", "sdhi1"),
1127 /* SMSC911X */
1128 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
1129 "bsc_cs5a", "bsc"),
1130 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
1131 "intc_irq6_0", "intc"),
1132 /* TSC2007 */
1133#ifdef CONFIG_AP4EVB_QHD
1134 PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
1135 "intc_irq28_0", "intc"),
1136#else /* WVGA */
1137 PIN_MAP_MUX_GROUP_DEFAULT("1-0048", "pfc-sh7372",
1138 "intc_irq7_0", "intc"),
1139#endif
1140 /* USBHS1 */
1141 PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
1142 "usb1_vbus", "usb1"),
1143 PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
1144 "usb1_otg_id_0", "usb1"),
1145 PIN_MAP_MUX_GROUP_DEFAULT("r8a66597_hcd.1", "pfc-sh7372",
1146 "usb1_otg_ctrl_0", "usb1"),
1147};
1148
1149#define GPIO_PORT9CR IOMEM(0xE6051009)
1150#define GPIO_PORT10CR IOMEM(0xE605100A)
1151#define USCCR1 IOMEM(0xE6058144)
1152static void __init ap4evb_init(void)
1153{
1154 struct pm_domain_device domain_devices[] = {
1155 { "A4LC", &lcdc1_device, },
1156 { "A4LC", &lcdc_device, },
1157 { "A4MP", &fsi_device, },
1158 { "A3SP", &sh_mmcif_device, },
1159 { "A3SP", &sdhi0_device, },
1160 { "A3SP", &sdhi1_device, },
1161 { "A4R", &ceu_device, },
1162 };
1163 u32 srcr4;
1164 struct clk *clk;
1165
1166 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
1167 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
1168 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
1169 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
1170 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1171
1172 /* External clock source */
1173 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1174
1175 pinctrl_register_mappings(ap4evb_pinctrl_map,
1176 ARRAY_SIZE(ap4evb_pinctrl_map));
1177 sh7372_pinmux_init();
1178
1179 /* enable Debug switch (S6) */
1180 gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
1181 gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
1182 gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
1183 gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
1184
1185 /* setup USB phy */
1186 __raw_writew(0x8a0a, IOMEM(0xE6058130)); /* USBCR4 */
1187
1188 /* FSI2 port A (ak4643) */
1189 gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
1190
1191 gpio_request(9, NULL);
1192 gpio_request(10, NULL);
1193 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1194 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1195
1196 /* card detect pin for MMC slot (CN7) */
1197 gpio_request_one(41, GPIOF_IN, NULL);
1198
1199 /* FSI2 port B (HDMI) */
1200 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1201
1202 /* set SPU2 clock to 119.6 MHz */
1203 clk = clk_get(NULL, "spu_clk");
1204 if (!IS_ERR(clk)) {
1205 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1206 clk_put(clk);
1207 }
1208
1209 /*
1210 * set irq priority, to avoid sound chopping
1211 * when NFS rootfs is used
1212 * FSI(3) > SMSC911X(2)
1213 */
1214 intc_set_priority(IRQ_FSI, 3);
1215
1216 i2c_register_board_info(0, i2c0_devices,
1217 ARRAY_SIZE(i2c0_devices));
1218
1219 i2c_register_board_info(1, i2c1_devices,
1220 ARRAY_SIZE(i2c1_devices));
1221
1222#ifdef CONFIG_AP4EVB_QHD
1223
1224 /*
1225 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1226 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
1227 */
1228
1229 /* enable TouchScreen */
1230 irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
1231
1232 tsc_device.irq = IRQ28;
1233 i2c_register_board_info(1, &tsc_device, 1);
1234
1235 /* LCDC0 */
1236 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1237 lcdc_info.ch[0].interface_type = RGB24;
1238 lcdc_info.ch[0].clock_divider = 1;
1239 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
1240 lcdc_info.ch[0].panel_cfg.width = 44;
1241 lcdc_info.ch[0].panel_cfg.height = 79;
1242
1243 platform_add_devices(qhd_devices, ARRAY_SIZE(qhd_devices));
1244
1245#else
1246 /*
1247 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1248 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
1249 */
1250 gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
1251 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1252
1253 lcdc_info.clock_source = LCDC_CLK_BUS;
1254 lcdc_info.ch[0].interface_type = RGB18;
1255 lcdc_info.ch[0].clock_divider = 3;
1256 lcdc_info.ch[0].flags = 0;
1257 lcdc_info.ch[0].panel_cfg.width = 152;
1258 lcdc_info.ch[0].panel_cfg.height = 91;
1259
1260 /* enable TouchScreen */
1261 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1262
1263 tsc_device.irq = IRQ7;
1264 i2c_register_board_info(0, &tsc_device, 1);
1265#endif /* CONFIG_AP4EVB_QHD */
1266
1267 /* CEU */
1268
1269 /*
1270 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1271 * becomes available
1272 */
1273
1274 /* MIPI-CSI stuff */
1275 clk = clk_get(NULL, "vck1_clk");
1276 if (!IS_ERR(clk)) {
1277 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1278 clk_enable(clk);
1279 clk_put(clk);
1280 }
1281
1282 sh7372_add_standard_devices();
1283
1284 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1285#define SRCR4 IOMEM(0xe61580bc)
1286 srcr4 = __raw_readl(SRCR4);
1287 __raw_writel(srcr4 | (1 << 13), SRCR4);
1288 udelay(50);
1289 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1290
1291 platform_add_devices(ap4evb_devices, ARRAY_SIZE(ap4evb_devices));
1292
1293 rmobile_add_devices_to_domains(domain_devices,
1294 ARRAY_SIZE(domain_devices));
1295
1296 hdmi_init_pm_clock();
1297 sh7372_pm_init();
1298 pm_clk_add(&fsi_device.dev, "spu2");
1299 pm_clk_add(&lcdc1_device.dev, "hdmi");
1300}
1301
1302MACHINE_START(AP4EVB, "ap4evb")
1303 .map_io = sh7372_map_io,
1304 .init_early = sh7372_add_early_devices,
1305 .init_irq = sh7372_init_irq,
1306 .handle_irq = shmobile_handle_irq_intc,
1307 .init_machine = ap4evb_init,
1308 .init_late = sh7372_pm_init_late,
1309 .init_time = sh7372_earlytimer_init,
1310MACHINE_END
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
deleted file mode 100644
index b373e9ced573..000000000000
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ /dev/null
@@ -1,502 +0,0 @@
1/*
2 * bonito board support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/i2c.h>
24#include <linux/init.h>
25#include <linux/interrupt.h>
26#include <linux/irq.h>
27#include <linux/pinctrl/machine.h>
28#include <linux/platform_device.h>
29#include <linux/gpio.h>
30#include <linux/regulator/fixed.h>
31#include <linux/regulator/machine.h>
32#include <linux/smsc911x.h>
33#include <linux/videodev2.h>
34#include <mach/common.h>
35#include <asm/mach-types.h>
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/time.h>
39#include <asm/hardware/cache-l2x0.h>
40#include <mach/r8a7740.h>
41#include <mach/irqs.h>
42#include <video/sh_mobile_lcdc.h>
43
44/*
45 * CS Address device note
46 *----------------------------------------------------------------
47 * 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
48 * 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
49 * 4 -
50 * 5A -
51 * 5B 0x1600_0000 SRAM (8MB)
52 * 6 0x1800_0000 FPGA (64K)
53 * 0x1801_0000 Ether (4KB)
54 * 0x1801_1000 USB (4KB)
55 */
56
57/*
58 * SW12
59 *
60 * bit1 bit2 bit3
61 *----------------------------------------------------------------------------
62 * ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
63 * OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
64 */
65
66/*
67 * SCIFA5 (CN42)
68 *
69 * S38.3 = ON
70 * S39.6 = ON
71 * S43.1 = ON
72 */
73
74/*
75 * LCDC0 (CN3/CN4/CN7)
76 *
77 * S38.1 = OFF
78 * S38.2 = OFF
79 */
80
81/* Dummy supplies, where voltage doesn't matter */
82static struct regulator_consumer_supply dummy_supplies[] = {
83 REGULATOR_SUPPLY("vddvario", "smsc911x"),
84 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
85};
86
87/*
88 * FPGA
89 */
90#define IRQSR0 0x0020
91#define IRQSR1 0x0022
92#define IRQMR0 0x0030
93#define IRQMR1 0x0032
94#define BUSSWMR1 0x0070
95#define BUSSWMR2 0x0072
96#define BUSSWMR3 0x0074
97#define BUSSWMR4 0x0076
98
99#define LCDCR 0x10B4
100#define DEVRSTCR1 0x10D0
101#define DEVRSTCR2 0x10D2
102#define A1MDSR 0x10E0
103#define BVERR 0x1100
104
105/* FPGA IRQ */
106#define FPGA_IRQ_BASE (512)
107#define FPGA_IRQ0 (FPGA_IRQ_BASE)
108#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
109#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
110static u16 bonito_fpga_read(u32 offset)
111{
112 return __raw_readw(IOMEM(0xf0003000) + offset);
113}
114
115static void bonito_fpga_write(u32 offset, u16 val)
116{
117 __raw_writew(val, IOMEM(0xf0003000) + offset);
118}
119
120static void bonito_fpga_irq_disable(struct irq_data *data)
121{
122 unsigned int irq = data->irq;
123 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
124 int shift = irq % 16;
125
126 bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
127}
128
129static void bonito_fpga_irq_enable(struct irq_data *data)
130{
131 unsigned int irq = data->irq;
132 u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
133 int shift = irq % 16;
134
135 bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
136}
137
138static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
139 .name = "bonito FPGA",
140 .irq_mask = bonito_fpga_irq_disable,
141 .irq_unmask = bonito_fpga_irq_enable,
142};
143
144static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
145{
146 u32 val = bonito_fpga_read(IRQSR1) << 16 |
147 bonito_fpga_read(IRQSR0);
148 u32 mask = bonito_fpga_read(IRQMR1) << 16 |
149 bonito_fpga_read(IRQMR0);
150
151 int i;
152
153 val &= ~mask;
154
155 for (i = 0; i < 32; i++) {
156 if (!(val & (1 << i)))
157 continue;
158
159 generic_handle_irq(FPGA_IRQ_BASE + i);
160 }
161}
162
163static void bonito_fpga_init(void)
164{
165 int i;
166
167 bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
168 bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
169
170 /* Device reset */
171 bonito_fpga_write(DEVRSTCR1,
172 (1 << 2)); /* Eth */
173
174 /* FPGA irq require special handling */
175 for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
176 irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
177 handle_level_irq, "level");
178 set_irq_flags(i, IRQF_VALID); /* yuck */
179 }
180
181 irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
182 irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
183}
184
185/*
186* PMIC settings
187*
188* FIXME
189*
190* bonito board needs some settings by pmic which use i2c access.
191* pmic settings use device_initcall() here for use it.
192*/
193static __u8 *pmic_settings = NULL;
194static __u8 pmic_do_2A[] = {
195 0x1C, 0x09,
196 0x1A, 0x80,
197 0xff, 0xff,
198};
199
200static int __init pmic_init(void)
201{
202 struct i2c_adapter *a = i2c_get_adapter(0);
203 struct i2c_msg msg;
204 __u8 buf[2];
205 int i, ret;
206
207 if (!pmic_settings)
208 return 0;
209 if (!a)
210 return 0;
211
212 msg.addr = 0x46;
213 msg.buf = buf;
214 msg.len = 2;
215 msg.flags = 0;
216
217 for (i = 0; ; i += 2) {
218 buf[0] = pmic_settings[i + 0];
219 buf[1] = pmic_settings[i + 1];
220
221 if ((0xff == buf[0]) && (0xff == buf[1]))
222 break;
223
224 ret = i2c_transfer(a, &msg, 1);
225 if (ret < 0) {
226 pr_err("i2c transfer fail\n");
227 break;
228 }
229 }
230
231 return 0;
232}
233device_initcall(pmic_init);
234
235/*
236 * LCDC0
237 */
238static const struct fb_videomode lcdc0_mode = {
239 .name = "WVGA Panel",
240 .xres = 800,
241 .yres = 480,
242 .left_margin = 88,
243 .right_margin = 40,
244 .hsync_len = 128,
245 .upper_margin = 20,
246 .lower_margin = 5,
247 .vsync_len = 5,
248 .sync = 0,
249};
250
251static struct sh_mobile_lcdc_info lcdc0_info = {
252 .clock_source = LCDC_CLK_BUS,
253 .ch[0] = {
254 .chan = LCDC_CHAN_MAINLCD,
255 .fourcc = V4L2_PIX_FMT_RGB565,
256 .interface_type = RGB24,
257 .clock_divider = 5,
258 .flags = 0,
259 .lcd_modes = &lcdc0_mode,
260 .num_modes = 1,
261 .panel_cfg = {
262 .width = 152,
263 .height = 91,
264 },
265 },
266};
267
268static struct resource lcdc0_resources[] = {
269 [0] = {
270 .name = "LCDC0",
271 .start = 0xfe940000,
272 .end = 0xfe943fff,
273 .flags = IORESOURCE_MEM,
274 },
275 [1] = {
276 .start = intcs_evt2irq(0x0580),
277 .flags = IORESOURCE_IRQ,
278 },
279};
280
281static struct platform_device lcdc0_device = {
282 .name = "sh_mobile_lcdc_fb",
283 .id = 0,
284 .resource = lcdc0_resources,
285 .num_resources = ARRAY_SIZE(lcdc0_resources),
286 .dev = {
287 .platform_data = &lcdc0_info,
288 .coherent_dma_mask = ~0,
289 },
290};
291
292static const struct pinctrl_map lcdc0_pinctrl_map[] = {
293 /* LCD0 */
294 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
295 "lcd0_data24_1", "lcd0"),
296 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
297 "lcd0_lclk_1", "lcd0"),
298 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
299 "lcd0_sync", "lcd0"),
300};
301
302/*
303 * SMSC 9221
304 */
305static struct resource smsc_resources[] = {
306 [0] = {
307 .start = 0x18010000,
308 .end = 0x18011000 - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = FPGA_ETH_IRQ,
313 .flags = IORESOURCE_IRQ,
314 },
315};
316
317static struct smsc911x_platform_config smsc_platdata = {
318 .flags = SMSC911X_USE_16BIT,
319 .phy_interface = PHY_INTERFACE_MODE_MII,
320 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
321 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
322};
323
324static struct platform_device smsc_device = {
325 .name = "smsc911x",
326 .dev = {
327 .platform_data = &smsc_platdata,
328 },
329 .resource = smsc_resources,
330 .num_resources = ARRAY_SIZE(smsc_resources),
331};
332
333/*
334 * base board devices
335 */
336static struct platform_device *bonito_base_devices[] __initdata = {
337 &lcdc0_device,
338 &smsc_device,
339};
340
341/*
342 * map I/O
343 */
344static struct map_desc bonito_io_desc[] __initdata = {
345 /*
346 * for FPGA (0x1800000-0x19ffffff)
347 * 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
348 */
349 {
350 .virtual = 0xf0003000,
351 .pfn = __phys_to_pfn(0x18000000),
352 .length = PAGE_SIZE * 2,
353 .type = MT_DEVICE_NONSHARED
354 }
355};
356
357static void __init bonito_map_io(void)
358{
359 r8a7740_map_io();
360 iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
361}
362
363/*
364 * board init
365 */
366#define BIT_ON(sw, bit) (sw & (1 << bit))
367#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
368
369#define VCCQ1CR IOMEM(0xE6058140)
370#define VCCQ1LCDCR IOMEM(0xE6058186)
371
372/*
373 * HACK: The FPGA mappings should be associated with the FPGA device, but we
374 * don't have one at the moment. Associate them with the PFC device to make
375 * sure they will be applied.
376 */
377static const struct pinctrl_map fpga_pinctrl_map[] = {
378 /* FPGA */
379 PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
380 "bsc_cs5a_0", "bsc"),
381 PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
382 "bsc_cs5b", "bsc"),
383 PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
384 "bsc_cs6a", "bsc"),
385 PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
386 "intc_irq10", "intc"),
387};
388
389static const struct pinctrl_map scifa5_pinctrl_map[] = {
390 /* SCIFA5 */
391 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
392 "scifa5_data_2", "scifa5"),
393};
394
395static void __init bonito_init(void)
396{
397 u16 val;
398
399 regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
400
401 pinctrl_register_mappings(fpga_pinctrl_map,
402 ARRAY_SIZE(fpga_pinctrl_map));
403 r8a7740_pinmux_init();
404 bonito_fpga_init();
405
406 pmic_settings = pmic_do_2A;
407
408 /*
409 * core board settings
410 */
411
412#ifdef CONFIG_CACHE_L2X0
413 /* Early BRESP enable, Shared attribute override enable, 32K*8way */
414 l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
415#endif
416
417 r8a7740_add_standard_devices();
418
419 /*
420 * base board settings
421 */
422 gpio_request_one(176, GPIOF_IN, NULL);
423 if (!gpio_get_value(176)) {
424 u16 bsw2;
425 u16 bsw3;
426 u16 bsw4;
427
428 val = bonito_fpga_read(BVERR);
429 pr_info("bonito version: cpu %02x, base %02x\n",
430 ((val >> 8) & 0xFF),
431 ((val >> 0) & 0xFF));
432
433 bsw2 = bonito_fpga_read(BUSSWMR2);
434 bsw3 = bonito_fpga_read(BUSSWMR3);
435 bsw4 = bonito_fpga_read(BUSSWMR4);
436
437 /*
438 * SCIFA5 (CN42)
439 */
440 if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
441 BIT_OFF(bsw3, 9) && /* S39.6 = ON */
442 BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
443 pinctrl_register_mappings(scifa5_pinctrl_map,
444 ARRAY_SIZE(scifa5_pinctrl_map));
445 }
446
447 /*
448 * LCDC0 (CN3)
449 */
450 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
451 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
452 pinctrl_register_mappings(lcdc0_pinctrl_map,
453 ARRAY_SIZE(lcdc0_pinctrl_map));
454
455 gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
456 NULL); /* LCDDON */
457
458 /* backlight on */
459 bonito_fpga_write(LCDCR, 1);
460
461 /* drivability Max */
462 __raw_writew(0x00FF , VCCQ1LCDCR);
463 __raw_writew(0xFFFF , VCCQ1CR);
464 }
465
466 platform_add_devices(bonito_base_devices,
467 ARRAY_SIZE(bonito_base_devices));
468 }
469}
470
471static void __init bonito_earlytimer_init(void)
472{
473 u16 val;
474 u8 md_ck = 0;
475
476 /* read MD_CK value */
477 val = bonito_fpga_read(A1MDSR);
478 if (val & (1 << 10))
479 md_ck |= MD_CK2;
480 if (val & (1 << 9))
481 md_ck |= MD_CK1;
482 if (val & (1 << 8))
483 md_ck |= MD_CK0;
484
485 r8a7740_clock_init(md_ck);
486 shmobile_earlytimer_init();
487}
488
489static void __init bonito_add_early_devices(void)
490{
491 r8a7740_add_early_devices();
492}
493
494MACHINE_START(BONITO, "bonito")
495 .map_io = bonito_map_io,
496 .init_early = bonito_add_early_devices,
497 .init_irq = r8a7740_init_irq,
498 .handle_irq = shmobile_handle_irq_intc,
499 .init_machine = bonito_init,
500 .init_late = shmobile_init_late,
501 .init_time = bonito_earlytimer_init,
502MACHINE_END
diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S
index 7d113f898e7f..6f9865467258 100644
--- a/arch/arm/mach-shmobile/headsmp-scu.S
+++ b/arch/arm/mach-shmobile/headsmp-scu.S
@@ -25,31 +25,24 @@
25 25
26 __CPUINIT 26 __CPUINIT
27/* 27/*
28 * Reset vector for secondary CPUs. 28 * Boot code for secondary CPUs.
29 * 29 *
30 * First we turn on L1 cache coherency for our CPU. Then we jump to 30 * First we turn on L1 cache coherency for our CPU. Then we jump to
31 * shmobile_invalidate_start that invalidates the cache and hands over control 31 * shmobile_invalidate_start that invalidates the cache and hands over control
32 * to the common ARM startup code. 32 * to the common ARM startup code.
33 * This function will be mapped to address 0 by the SBAR register.
34 * A normal branch is out of range here so we need a long jump. We jump to
35 * the physical address as the MMU is still turned off.
36 */ 33 */
37 .align 12 34ENTRY(shmobile_boot_scu)
38ENTRY(shmobile_secondary_vector_scu) 35 @ r0 = SCU base address
39 mrc p15, 0, r0, c0, c0, 5 @ read MIPDR 36 mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
40 and r0, r0, #3 @ mask out cpu ID 37 and r1, r1, #3 @ mask out cpu ID
41 lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits 38 lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
42 ldr r1, 2f 39 ldr r2, [r0, #8] @ SCU Power Status Register
43 ldr r1, [r1] @ SCU base address
44 ldr r2, [r1, #8] @ SCU Power Status Register
45 mov r3, #3 40 mov r3, #3
46 bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode) 41 bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode)
47 str r2, [r1, #8] @ write back 42 str r2, [r0, #8] @ write back
48 43
49 ldr pc, 1f 44 b shmobile_invalidate_start
501: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET 45ENDPROC(shmobile_boot_scu)
512: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
52ENDPROC(shmobile_secondary_vector_scu)
53 46
54 .text 47 .text
55 .globl shmobile_scu_base 48 .globl shmobile_scu_base
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index 96001fd49b6c..559d1ce5f57e 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -27,7 +27,14 @@ ENDPROC(shmobile_invalidate_start)
27 * We need _long_ jump to the physical address. 27 * We need _long_ jump to the physical address.
28 */ 28 */
29 .align 12 29 .align 12
30ENTRY(shmobile_secondary_vector) 30ENTRY(shmobile_boot_vector)
31 ldr r0, 2f
31 ldr pc, 1f 32 ldr pc, 1f
321: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET 33ENDPROC(shmobile_boot_vector)
33ENDPROC(shmobile_secondary_vector) 34
35 .globl shmobile_boot_fn
36shmobile_boot_fn:
371: .space 4
38 .globl shmobile_boot_arg
39shmobile_boot_arg:
402: .space 4
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 4634a5d4b63f..e818f029d8e3 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -7,8 +7,10 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
7 unsigned int mult, unsigned int div); 7 unsigned int mult, unsigned int div);
8struct twd_local_timer; 8struct twd_local_timer;
9extern void shmobile_setup_console(void); 9extern void shmobile_setup_console(void);
10extern void shmobile_secondary_vector(void); 10extern void shmobile_boot_vector(void);
11extern void shmobile_secondary_vector_scu(void); 11extern unsigned long shmobile_boot_fn;
12extern unsigned long shmobile_boot_arg;
13extern void shmobile_boot_scu(void);
12struct clk; 14struct clk;
13extern int shmobile_clk_init(void); 15extern int shmobile_clk_init(void);
14extern void shmobile_handle_irq_intc(struct pt_regs *); 16extern void shmobile_handle_irq_intc(struct pt_regs *);
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
deleted file mode 100644
index 9f134dfeffdc..000000000000
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ /dev/null
@@ -1,93 +0,0 @@
1LIST "partner-jet-setup.txt"
2LIST "(C) Copyright 2010 Renesas Solutions Corp"
3LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
4
5LIST "RWT Setting"
6EW 0xE6020004, 0xA500
7EW 0xE6030004, 0xA500
8
9LIST "GPIO Setting"
10EB 0xE6051013, 0xA2
11
12LIST "CPG"
13ED 0xE61500C0, 0x00000002
14
15WAIT 1, 0xFE40009C
16
17LIST "FRQCR"
18ED 0xE6150000, 0x2D1305C3
19ED 0xE61500E0, 0x9E40358E
20ED 0xE6150004, 0x80331050
21
22WAIT 1, 0xFE40009C
23
24ED 0xE61500E4, 0x00002000
25
26WAIT 1, 0xFE40009C
27
28LIST "PLL"
29ED 0xE6150028, 0x00004000
30
31WAIT 1, 0xFE40009C
32
33ED 0xE615002C, 0x93000040
34
35WAIT 1, 0xFE40009C
36
37LIST "SUB/USBClk"
38ED 0xE6150080, 0x00000180
39
40LIST "BSC"
41ED 0xFEC10000, 0x00E0001B
42
43LIST "SBSC1"
44ED 0xFE400354, 0x01AD8000
45ED 0xFE400354, 0x01AD8001
46
47WAIT 5, 0xFE40009C
48
49ED 0xFE400008, 0xBCC90151
50ED 0xFE400040, 0x41774113
51ED 0xFE400044, 0x2712E229
52ED 0xFE400048, 0x20C18505
53ED 0xFE40004C, 0x00110209
54ED 0xFE400010, 0x00000087
55
56WAIT 30, 0xFE40009C
57
58ED 0xFE400084, 0x0000003F
59EB 0xFE500000, 0x00
60
61WAIT 5, 0xFE40009C
62
63ED 0xFE400084, 0x0000FF0A
64EB 0xFE500000, 0x00
65
66WAIT 1, 0xFE40009C
67
68ED 0xFE400084, 0x00002201
69EB 0xFE500000, 0x00
70ED 0xFE400084, 0x00000302
71EB 0xFE500000, 0x00
72EB 0xFE5C0000, 0x00
73ED 0xFE400008, 0xBCC90159
74ED 0xFE40008C, 0x88800004
75ED 0xFE400094, 0x00000004
76ED 0xFE400028, 0xA55A0032
77ED 0xFE40002C, 0xA55A000C
78ED 0xFE400020, 0xA55A2048
79ED 0xFE400008, 0xBCC90959
80
81LIST "Change CPGA setting"
82ED 0xE61500E0, 0x9E40352E
83ED 0xE6150004, 0x80331050
84
85WAIT 1, 0xFE40009C
86
87ED 0xFE400354, 0x01AD8002
88
89LIST "SCIF0 - Serial port for earlyprintk"
90EB 0xE6053098, 0xe1
91EW 0xE6C40000, 0x0000
92EB 0xE6C40004, 0x19
93EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
deleted file mode 100644
index 0ffbe8155c76..000000000000
--- a/arch/arm/mach-shmobile/include/mach/memory.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_MACH_MEMORY_H
2#define __ASM_MACH_MEMORY_H
3
4#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START)
5#define MEM_SIZE UL(CONFIG_MEMORY_SIZE)
6
7#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h b/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h
deleted file mode 100644
index db59fdbda860..000000000000
--- a/arch/arm/mach-shmobile/include/mach/mmc-ap4eb.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef MMC_AP4EB_H
2#define MMC_AP4EB_H
3
4#define PORT185CR (void __iomem *)0xe60520b9
5#define PORT186CR (void __iomem *)0xe60520ba
6#define PORT187CR (void __iomem *)0xe60520bb
7#define PORT188CR (void __iomem *)0xe60520bc
8
9#define PORTR191_160DR (void __iomem *)0xe6056014
10
11static inline void mmc_init_progress(void)
12{
13 /* Initialise LEDS1-4
14 * registers: PORT185CR-PORT188CR (LED1-LED4 Control)
15 * value: 0x10 - enable output
16 */
17 __raw_writeb(0x10, PORT185CR);
18 __raw_writeb(0x10, PORT186CR);
19 __raw_writeb(0x10, PORT187CR);
20 __raw_writeb(0x10, PORT188CR);
21}
22
23static inline void mmc_update_progress(int n)
24{
25 __raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) |
26 (1 << (25 + n)), PORTR191_160DR);
27}
28
29#endif /* MMC_AP4EB_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h
index 21a59db638bb..e979b8fc1da2 100644
--- a/arch/arm/mach-shmobile/include/mach/mmc.h
+++ b/arch/arm/mach-shmobile/include/mach/mmc.h
@@ -7,9 +7,7 @@
7 * 7 *
8 **************************************************/ 8 **************************************************/
9 9
10#ifdef CONFIG_MACH_AP4EVB 10#ifdef CONFIG_MACH_MACKEREL
11#include "mach/mmc-ap4eb.h"
12#elif defined(CONFIG_MACH_MACKEREL)
13#include "mach/mmc-mackerel.h" 11#include "mach/mmc-mackerel.h"
14#else 12#else
15#error "unsupported board." 13#error "unsupported board."
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index e882717ca97f..854a9f0ca040 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -75,6 +75,8 @@ extern void sh7372_intcs_resume(void);
75extern void sh7372_intca_suspend(void); 75extern void sh7372_intca_suspend(void);
76extern void sh7372_intca_resume(void); 76extern void sh7372_intca_resume(void);
77 77
78extern unsigned long sh7372_cpu_resume;
79
78#ifdef CONFIG_PM 80#ifdef CONFIG_PM
79extern void __init sh7372_init_pm_domains(void); 81extern void __init sh7372_init_pm_domains(void);
80#else 82#else
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index 9320aff0a20f..f2d8744c1f14 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -10,11 +10,9 @@
10 * 10 *
11 **************************************************/ 11 **************************************************/
12 12
13#ifdef CONFIG_MACH_AP4EVB 13#ifdef CONFIG_MACH_MACKEREL
14#define MACH_TYPE MACH_TYPE_AP4EVB
15#include "mach/head-ap4evb.txt"
16#elif defined(CONFIG_MACH_MACKEREL)
17#define MACH_TYPE MACH_TYPE_MACKEREL 14#define MACH_TYPE MACH_TYPE_MACKEREL
15#define MEMORY_START 0x40000000
18#include "mach/head-mackerel.txt" 16#include "mach/head-mackerel.txt"
19#else 17#else
20#error "unsupported board." 18#error "unsupported board."
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index dec9293bb90d..0de75fd394b9 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -351,6 +351,9 @@ static void sh7372_enter_a4s_common(int pllc0_on)
351 351
352static void sh7372_pm_setup_smfram(void) 352static void sh7372_pm_setup_smfram(void)
353{ 353{
354 /* pass physical address of cpu_resume() to assembly resume code */
355 sh7372_cpu_resume = virt_to_phys(cpu_resume);
356
354 memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100); 357 memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
355} 358}
356#else 359#else
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
index a9df53b69ab8..53f4840e4949 100644
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -40,7 +40,10 @@
40 .global sh7372_resume_core_standby_sysc 40 .global sh7372_resume_core_standby_sysc
41sh7372_resume_core_standby_sysc: 41sh7372_resume_core_standby_sysc:
42 ldr pc, 1f 42 ldr pc, 1f
431: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET 43
44 .globl sh7372_cpu_resume
45sh7372_cpu_resume:
461: .space 4
44 47
45#define SPDCR 0xe6180008 48#define SPDCR 0xe6180008
46 49
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index e38691b4d0dd..80991b35f4ac 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -40,8 +40,10 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
40{ 40{
41 scu_enable(shmobile_scu_base); 41 scu_enable(shmobile_scu_base);
42 42
43 /* Tell ROM loader about our vector (in headsmp-scu.S) */ 43 /* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
44 emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu)); 44 emev2_set_boot_vector(__pa(shmobile_boot_vector));
45 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
46 shmobile_boot_arg = (unsigned long)shmobile_scu_base;
45 47
46 /* enable cache coherency on booting CPU */ 48 /* enable cache coherency on booting CPU */
47 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); 49 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index a853bf182ed5..526cfaae81c1 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -101,8 +101,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
101{ 101{
102 scu_enable(shmobile_scu_base); 102 scu_enable(shmobile_scu_base);
103 103
104 /* Map the reset vector (in headsmp-scu.S) */ 104 /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
105 __raw_writel(__pa(shmobile_secondary_vector_scu), AVECR); 105 __raw_writel(__pa(shmobile_boot_vector), AVECR);
106 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
107 shmobile_boot_arg = (unsigned long)shmobile_scu_base;
106 108
107 /* enable cache coherency on booting CPU */ 109 /* enable cache coherency on booting CPU */
108 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); 110 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 496592b6c763..d613113a04bd 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -64,9 +64,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
64{ 64{
65 scu_enable(shmobile_scu_base); 65 scu_enable(shmobile_scu_base);
66 66
67 /* Map the reset vector (in headsmp-scu.S) */ 67 /* Map the reset vector (in headsmp-scu.S, headsmp.S) */
68 __raw_writel(0, APARMBAREA); /* 4k */ 68 __raw_writel(0, APARMBAREA); /* 4k */
69 __raw_writel(__pa(shmobile_secondary_vector_scu), SBAR); 69 __raw_writel(__pa(shmobile_boot_vector), SBAR);
70 shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
71 shmobile_boot_arg = (unsigned long)shmobile_scu_base;
70 72
71 /* enable cache coherency on booting CPU */ 73 /* enable cache coherency on booting CPU */
72 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL); 74 scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-29 12:34:50 -0500