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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-06-26 07:47:08 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-07-02 05:56:12 -0400
commit30891c90d81133179cc47eb77c30764a3b5dad5c (patch)
tree4af470a3f2d999ec8feefce84b6d502c28cdfbb4 /arch
parent40f0b90a2f16f433f9afbfef4b7c312efb54e933 (diff)
ARM: entry: no need to reload the SPSR value from struct pt_regs
The SVC IRQ, prefetch and data abort handlers preserve the SPSR value via r5 across the exception. Rather than re-loading it from pt_regs, use the preserved value instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/kernel/entry-armv.S10
1 files changed, 1 insertions, 9 deletions
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index bbdd443b8055..fa02a22a4c4b 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -195,10 +195,6 @@ __dabt_svc:
195 @ 195 @
196 disable_irq_notrace 196 disable_irq_notrace
197 197
198 @
199 @ restore SPSR and restart the instruction
200 @
201 ldr r5, [sp, #S_PSR]
202#ifdef CONFIG_TRACE_IRQFLAGS 198#ifdef CONFIG_TRACE_IRQFLAGS
203 tst r5, #PSR_I_BIT 199 tst r5, #PSR_I_BIT
204 bleq trace_hardirqs_on 200 bleq trace_hardirqs_on
@@ -223,7 +219,7 @@ __irq_svc:
223 tst r0, #_TIF_NEED_RESCHED 219 tst r0, #_TIF_NEED_RESCHED
224 blne svc_preempt 220 blne svc_preempt
225#endif 221#endif
226 ldr r5, [sp, #S_PSR] 222
227#ifdef CONFIG_TRACE_IRQFLAGS 223#ifdef CONFIG_TRACE_IRQFLAGS
228 @ The parent context IRQs must have been enabled to get here in 224 @ The parent context IRQs must have been enabled to get here in
229 @ the first place, so there's no point checking the PSR I bit. 225 @ the first place, so there's no point checking the PSR I bit.
@@ -308,10 +304,6 @@ __pabt_svc:
308 @ 304 @
309 disable_irq_notrace 305 disable_irq_notrace
310 306
311 @
312 @ restore SPSR and restart the instruction
313 @
314 ldr r5, [sp, #S_PSR]
315#ifdef CONFIG_TRACE_IRQFLAGS 307#ifdef CONFIG_TRACE_IRQFLAGS
316 tst r5, #PSR_I_BIT 308 tst r5, #PSR_I_BIT
317 bleq trace_hardirqs_on 309 bleq trace_hardirqs_on