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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-10-29 19:26:23 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-10-29 19:26:23 -0400
commit2f29e3a561017b95f5c3e40b7d66ec8bbd632d2d (patch)
treeb54979117db6804ad3c8c88ef341c0dd1e30779f /arch
parentbcd77ffc5d8ff3c9056927fb7aa855164b982053 (diff)
parenta3821b2af185b64e3382c45fbdaa2cbc91ce14b8 (diff)
Merge remote-tracking branch 'scott/next' into next
Highlights include corenet board file consolidation, the ability to run userspaces with lwsync on e500v1/v2, some cleanup patches that other KVM patches will build on, support for stripped-down e6500 emulation targets, and some fixes of minor longstanding issues.
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/boot/dts/b4860emu.dts218
-rw-r--r--arch/powerpc/boot/dts/b4qds.dtsi51
-rw-r--r--arch/powerpc/boot/dts/c293pcie.dts1
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi3
-rw-r--r--arch/powerpc/boot/dts/t4240emu.dts268
-rw-r--r--arch/powerpc/boot/dts/t4240qds.dts73
-rw-r--r--arch/powerpc/configs/corenet32_smp_defconfig7
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig5
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig1
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig1
-rw-r--r--arch/powerpc/configs/ppc64e_defconfig2
-rw-r--r--arch/powerpc/configs/ppc6xx_defconfig2
-rw-r--r--arch/powerpc/include/asm/emulated_ops.h1
-rw-r--r--arch/powerpc/include/asm/ppc-opcode.h2
-rw-r--r--arch/powerpc/include/asm/processor.h34
-rw-r--r--arch/powerpc/include/asm/reg_booke.h8
-rw-r--r--arch/powerpc/include/asm/switch_to.h1
-rw-r--r--arch/powerpc/kernel/asm-offsets.c2
-rw-r--r--arch/powerpc/kernel/exceptions-64e.S5
-rw-r--r--arch/powerpc/kernel/head_8xx.S3
-rw-r--r--arch/powerpc/kernel/head_fsl_booke.S10
-rw-r--r--arch/powerpc/kernel/kgdb.c6
-rw-r--r--arch/powerpc/kernel/process.c45
-rw-r--r--arch/powerpc/kernel/ptrace.c156
-rw-r--r--arch/powerpc/kernel/ptrace32.c2
-rw-r--r--arch/powerpc/kernel/signal_32.c6
-rw-r--r--arch/powerpc/kernel/traps.c46
-rw-r--r--arch/powerpc/mm/init_32.c5
-rw-r--r--arch/powerpc/mm/pgtable.c19
-rw-r--r--arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c1
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig101
-rw-r--r--arch/powerpc/platforms/85xx/Makefile8
-rw-r--r--arch/powerpc/platforms/85xx/b4_qds.c102
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.c96
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.h19
-rw-r--r--arch/powerpc/platforms/85xx/corenet_generic.c182
-rw-r--r--arch/powerpc/platforms/85xx/p1010rdb.c2
-rw-r--r--arch/powerpc/platforms/85xx/p2041_rdb.c87
-rw-r--r--arch/powerpc/platforms/85xx/p3041_ds.c89
-rw-r--r--arch/powerpc/platforms/85xx/p4080_ds.c87
-rw-r--r--arch/powerpc/platforms/85xx/p5020_ds.c93
-rw-r--r--arch/powerpc/platforms/85xx/p5040_ds.c84
-rw-r--r--arch/powerpc/platforms/85xx/t4240_qds.c93
-rw-r--r--arch/powerpc/platforms/embedded6xx/hlwd-pic.c1
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c5
-rw-r--r--arch/powerpc/sysdev/mv64x60_dev.c2
51 files changed, 964 insertions, 1081 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 875d815a8e7f..5f15468300bf 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -420,7 +420,7 @@ config FA_DUMP
420 420
421config IRQ_ALL_CPUS 421config IRQ_ALL_CPUS
422 bool "Distribute interrupts on all CPUs by default" 422 bool "Distribute interrupts on all CPUs by default"
423 depends on SMP && !MV64360 423 depends on SMP
424 help 424 help
425 This option gives the kernel permission to distribute IRQs across 425 This option gives the kernel permission to distribute IRQs across
426 multiple CPUs. Saying N here will route all IRQs to the first 426 multiple CPUs. Saying N here will route all IRQs to the first
diff --git a/arch/powerpc/boot/dts/b4860emu.dts b/arch/powerpc/boot/dts/b4860emu.dts
new file mode 100644
index 000000000000..7290021f2dfc
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860emu.dts
@@ -0,0 +1,218 @@
1/*
2 * B4860 emulator Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/dts-v1/;
36
37/include/ "fsl/e6500_power_isa.dtsi"
38
39/ {
40 compatible = "fsl,B4860";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47
48 serial0 = &serial0;
49 serial1 = &serial1;
50 serial2 = &serial2;
51 serial3 = &serial3;
52 dma0 = &dma0;
53 dma1 = &dma1;
54 };
55
56 cpus {
57 #address-cells = <1>;
58 #size-cells = <0>;
59
60 cpu0: PowerPC,e6500@0 {
61 device_type = "cpu";
62 reg = <0 1>;
63 next-level-cache = <&L2>;
64 };
65 cpu1: PowerPC,e6500@2 {
66 device_type = "cpu";
67 reg = <2 3>;
68 next-level-cache = <&L2>;
69 };
70 cpu2: PowerPC,e6500@4 {
71 device_type = "cpu";
72 reg = <4 5>;
73 next-level-cache = <&L2>;
74 };
75 cpu3: PowerPC,e6500@6 {
76 device_type = "cpu";
77 reg = <6 7>;
78 next-level-cache = <&L2>;
79 };
80 };
81};
82
83/ {
84 model = "fsl,B4860QDS";
85 compatible = "fsl,B4860EMU", "fsl,B4860QDS";
86 #address-cells = <2>;
87 #size-cells = <2>;
88 interrupt-parent = <&mpic>;
89
90 ifc: localbus@ffe124000 {
91 reg = <0xf 0xfe124000 0 0x2000>;
92 ranges = <0 0 0xf 0xe8000000 0x08000000
93 2 0 0xf 0xff800000 0x00010000
94 3 0 0xf 0xffdf0000 0x00008000>;
95
96 nor@0,0 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "cfi-flash";
100 reg = <0x0 0x0 0x8000000>;
101 bank-width = <2>;
102 device-width = <1>;
103 };
104 };
105
106 memory {
107 device_type = "memory";
108 };
109
110 soc: soc@ffe000000 {
111 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
112 reg = <0xf 0xfe000000 0 0x00001000>;
113 };
114};
115
116&ifc {
117 #address-cells = <2>;
118 #size-cells = <1>;
119 compatible = "fsl,ifc", "simple-bus";
120 interrupts = <25 2 0 0>;
121};
122
123&soc {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 device_type = "soc";
127 compatible = "simple-bus";
128
129 soc-sram-error {
130 compatible = "fsl,soc-sram-error";
131 interrupts = <16 2 1 2>;
132 };
133
134 corenet-law@0 {
135 compatible = "fsl,corenet-law";
136 reg = <0x0 0x1000>;
137 fsl,num-laws = <32>;
138 };
139
140 ddr1: memory-controller@8000 {
141 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
142 reg = <0x8000 0x1000>;
143 interrupts = <16 2 1 8>;
144 };
145
146 ddr2: memory-controller@9000 {
147 compatible = "fsl,qoriq-memory-controller-v4.5","fsl,qoriq-memory-controller";
148 reg = <0x9000 0x1000>;
149 interrupts = <16 2 1 9>;
150 };
151
152 cpc: l3-cache-controller@10000 {
153 compatible = "fsl,b4-l3-cache-controller", "cache";
154 reg = <0x10000 0x1000
155 0x11000 0x1000>;
156 interrupts = <16 2 1 4>;
157 };
158
159 corenet-cf@18000 {
160 compatible = "fsl,b4-corenet-cf";
161 reg = <0x18000 0x1000>;
162 interrupts = <16 2 1 0>;
163 fsl,ccf-num-csdids = <32>;
164 fsl,ccf-num-snoopids = <32>;
165 };
166
167 iommu@20000 {
168 compatible = "fsl,pamu-v1.0", "fsl,pamu";
169 reg = <0x20000 0x4000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 interrupts = <
173 24 2 0 0
174 16 2 1 1>;
175 pamu0: pamu@0 {
176 reg = <0 0x1000>;
177 fsl,primary-cache-geometry = <8 1>;
178 fsl,secondary-cache-geometry = <32 2>;
179 };
180 };
181
182/include/ "fsl/qoriq-mpic.dtsi"
183
184 guts: global-utilities@e0000 {
185 compatible = "fsl,b4-device-config";
186 reg = <0xe0000 0xe00>;
187 fsl,has-rstcr;
188 fsl,liodn-bits = <12>;
189 };
190
191 clockgen: global-utilities@e1000 {
192 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
193 reg = <0xe1000 0x1000>;
194 };
195
196/include/ "fsl/qoriq-dma-0.dtsi"
197 dma@100300 {
198 fsl,iommu-parent = <&pamu0>;
199 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
200 };
201
202/include/ "fsl/qoriq-dma-1.dtsi"
203 dma@101300 {
204 fsl,iommu-parent = <&pamu0>;
205 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
206 };
207
208/include/ "fsl/qoriq-i2c-0.dtsi"
209/include/ "fsl/qoriq-i2c-1.dtsi"
210/include/ "fsl/qoriq-duart-0.dtsi"
211/include/ "fsl/qoriq-duart-1.dtsi"
212
213 L2: l2-cache-controller@c20000 {
214 compatible = "fsl,b4-l2-cache-controller";
215 reg = <0xc20000 0x1000>;
216 next-level-cache = <&cpc>;
217 };
218};
diff --git a/arch/powerpc/boot/dts/b4qds.dtsi b/arch/powerpc/boot/dts/b4qds.dtsi
index e6d2f8f90544..8b47edcfabf0 100644
--- a/arch/powerpc/boot/dts/b4qds.dtsi
+++ b/arch/powerpc/boot/dts/b4qds.dtsi
@@ -120,25 +120,38 @@
120 }; 120 };
121 121
122 i2c@118000 { 122 i2c@118000 {
123 eeprom@50 { 123 mux@77 {
124 compatible = "at24,24c64"; 124 compatible = "nxp,pca9547";
125 reg = <0x50>; 125 reg = <0x77>;
126 }; 126 #address-cells = <1>;
127 eeprom@51 { 127 #size-cells = <0>;
128 compatible = "at24,24c256"; 128
129 reg = <0x51>; 129 i2c@0 {
130 }; 130 #address-cells = <1>;
131 eeprom@53 { 131 #size-cells = <0>;
132 compatible = "at24,24c256"; 132 reg = <0>;
133 reg = <0x53>; 133
134 }; 134 eeprom@50 {
135 eeprom@57 { 135 compatible = "at24,24c64";
136 compatible = "at24,24c256"; 136 reg = <0x50>;
137 reg = <0x57>; 137 };
138 }; 138 eeprom@51 {
139 rtc@68 { 139 compatible = "at24,24c256";
140 compatible = "dallas,ds3232"; 140 reg = <0x51>;
141 reg = <0x68>; 141 };
142 eeprom@53 {
143 compatible = "at24,24c256";
144 reg = <0x53>;
145 };
146 eeprom@57 {
147 compatible = "at24,24c256";
148 reg = <0x57>;
149 };
150 rtc@68 {
151 compatible = "dallas,ds3232";
152 reg = <0x68>;
153 };
154 };
142 }; 155 };
143 }; 156 };
144 157
diff --git a/arch/powerpc/boot/dts/c293pcie.dts b/arch/powerpc/boot/dts/c293pcie.dts
index 1238bda8901f..6681cc21030b 100644
--- a/arch/powerpc/boot/dts/c293pcie.dts
+++ b/arch/powerpc/boot/dts/c293pcie.dts
@@ -45,6 +45,7 @@
45 ifc: ifc@fffe1e000 { 45 ifc: ifc@fffe1e000 {
46 reg = <0xf 0xffe1e000 0 0x2000>; 46 reg = <0xf 0xffe1e000 0 0x2000>;
47 ranges = <0x0 0x0 0xf 0xec000000 0x04000000 47 ranges = <0x0 0x0 0xf 0xec000000 0x04000000
48 0x1 0x0 0xf 0xff800000 0x00010000
48 0x2 0x0 0xf 0xffdf0000 0x00010000>; 49 0x2 0x0 0xf 0xffdf0000 0x00010000>;
49 50
50 }; 51 };
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
index 7b4426e0a5a5..c6e451affb05 100644
--- a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -34,6 +34,8 @@
34 34
35/dts-v1/; 35/dts-v1/;
36 36
37/include/ "e6500_power_isa.dtsi"
38
37/ { 39/ {
38 compatible = "fsl,B4420"; 40 compatible = "fsl,B4420";
39 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
index e5cf6c81dd66..981397518fc6 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -41,7 +41,7 @@
41 41
42&rio { 42&rio {
43 compatible = "fsl,srio"; 43 compatible = "fsl,srio";
44 interrupts = <16 2 1 11>; 44 interrupts = <16 2 1 20>;
45 #address-cells = <2>; 45 #address-cells = <2>;
46 #size-cells = <2>; 46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>; 47 fsl,iommu-parent = <&pamu0>;
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
index 5263fa46a3fb..9bc26b147900 100644
--- a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -34,6 +34,8 @@
34 34
35/dts-v1/; 35/dts-v1/;
36 36
37/include/ "e6500_power_isa.dtsi"
38
37/ { 39/ {
38 compatible = "fsl,B4860"; 40 compatible = "fsl,B4860";
39 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
index 5180d9d37989..0c0efa94cfb4 100644
--- a/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi
@@ -130,7 +130,7 @@ usb@22000 {
130 130
131/include/ "pq3-esdhc-0.dtsi" 131/include/ "pq3-esdhc-0.dtsi"
132 sdhc@2e000 { 132 sdhc@2e000 {
133 fsl,sdhci-auto-cmd12; 133 sdhci,auto-cmd12;
134 interrupts = <41 0x2 0 0>; 134 interrupts = <41 0x2 0 0>;
135 }; 135 };
136 136
diff --git a/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi b/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
index 743e4aeda349..f6ec4a67560c 100644
--- a/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
+++ b/arch/powerpc/boot/dts/fsl/bsc9131si-pre.dtsi
@@ -33,6 +33,9 @@
33 */ 33 */
34 34
35/dts-v1/; 35/dts-v1/;
36
37/include/ "e500v2_power_isa.dtsi"
38
36/ { 39/ {
37 compatible = "fsl,BSC9131"; 40 compatible = "fsl,BSC9131";
38 #address-cells = <2>; 41 #address-cells = <2>;
diff --git a/arch/powerpc/boot/dts/t4240emu.dts b/arch/powerpc/boot/dts/t4240emu.dts
new file mode 100644
index 000000000000..ee24ab335598
--- /dev/null
+++ b/arch/powerpc/boot/dts/t4240emu.dts
@@ -0,0 +1,268 @@
1/*
2 * T4240 emulator Device Tree Source
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "fsl/e6500_power_isa.dtsi"
38/ {
39 compatible = "fsl,T4240";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 aliases {
45 ccsr = &soc;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 dma0 = &dma0;
52 dma1 = &dma1;
53 };
54
55 cpus {
56 #address-cells = <1>;
57 #size-cells = <0>;
58
59 cpu0: PowerPC,e6500@0 {
60 device_type = "cpu";
61 reg = <0 1>;
62 next-level-cache = <&L2_1>;
63 };
64 cpu1: PowerPC,e6500@2 {
65 device_type = "cpu";
66 reg = <2 3>;
67 next-level-cache = <&L2_1>;
68 };
69 cpu2: PowerPC,e6500@4 {
70 device_type = "cpu";
71 reg = <4 5>;
72 next-level-cache = <&L2_1>;
73 };
74 cpu3: PowerPC,e6500@6 {
75 device_type = "cpu";
76 reg = <6 7>;
77 next-level-cache = <&L2_1>;
78 };
79
80 cpu4: PowerPC,e6500@8 {
81 device_type = "cpu";
82 reg = <8 9>;
83 next-level-cache = <&L2_2>;
84 };
85 cpu5: PowerPC,e6500@10 {
86 device_type = "cpu";
87 reg = <10 11>;
88 next-level-cache = <&L2_2>;
89 };
90 cpu6: PowerPC,e6500@12 {
91 device_type = "cpu";
92 reg = <12 13>;
93 next-level-cache = <&L2_2>;
94 };
95 cpu7: PowerPC,e6500@14 {
96 device_type = "cpu";
97 reg = <14 15>;
98 next-level-cache = <&L2_2>;
99 };
100
101 cpu8: PowerPC,e6500@16 {
102 device_type = "cpu";
103 reg = <16 17>;
104 next-level-cache = <&L2_3>;
105 };
106 cpu9: PowerPC,e6500@18 {
107 device_type = "cpu";
108 reg = <18 19>;
109 next-level-cache = <&L2_3>;
110 };
111 cpu10: PowerPC,e6500@20 {
112 device_type = "cpu";
113 reg = <20 21>;
114 next-level-cache = <&L2_3>;
115 };
116 cpu11: PowerPC,e6500@22 {
117 device_type = "cpu";
118 reg = <22 23>;
119 next-level-cache = <&L2_3>;
120 };
121 };
122};
123
124/ {
125 model = "fsl,T4240QDS";
126 compatible = "fsl,T4240EMU", "fsl,T4240QDS";
127 #address-cells = <2>;
128 #size-cells = <2>;
129 interrupt-parent = <&mpic>;
130
131 ifc: localbus@ffe124000 {
132 reg = <0xf 0xfe124000 0 0x2000>;
133 ranges = <0 0 0xf 0xe8000000 0x08000000
134 2 0 0xf 0xff800000 0x00010000
135 3 0 0xf 0xffdf0000 0x00008000>;
136
137 nor@0,0 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "cfi-flash";
141 reg = <0x0 0x0 0x8000000>;
142
143 bank-width = <2>;
144 device-width = <1>;
145 };
146
147 };
148
149 memory {
150 device_type = "memory";
151 };
152
153 soc: soc@ffe000000 {
154 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
155 reg = <0xf 0xfe000000 0 0x00001000>;
156
157 };
158};
159
160&ifc {
161 #address-cells = <2>;
162 #size-cells = <1>;
163 compatible = "fsl,ifc", "simple-bus";
164 interrupts = <25 2 0 0>;
165};
166
167&soc {
168 #address-cells = <1>;
169 #size-cells = <1>;
170 device_type = "soc";
171 compatible = "simple-bus";
172
173 soc-sram-error {
174 compatible = "fsl,soc-sram-error";
175 interrupts = <16 2 1 29>;
176 };
177
178 corenet-law@0 {
179 compatible = "fsl,corenet-law";
180 reg = <0x0 0x1000>;
181 fsl,num-laws = <32>;
182 };
183
184 ddr1: memory-controller@8000 {
185 compatible = "fsl,qoriq-memory-controller-v4.7",
186 "fsl,qoriq-memory-controller";
187 reg = <0x8000 0x1000>;
188 interrupts = <16 2 1 23>;
189 };
190
191 ddr2: memory-controller@9000 {
192 compatible = "fsl,qoriq-memory-controller-v4.7",
193 "fsl,qoriq-memory-controller";
194 reg = <0x9000 0x1000>;
195 interrupts = <16 2 1 22>;
196 };
197
198 ddr3: memory-controller@a000 {
199 compatible = "fsl,qoriq-memory-controller-v4.7",
200 "fsl,qoriq-memory-controller";
201 reg = <0xa000 0x1000>;
202 interrupts = <16 2 1 21>;
203 };
204
205 cpc: l3-cache-controller@10000 {
206 compatible = "fsl,t4240-l3-cache-controller", "cache";
207 reg = <0x10000 0x1000
208 0x11000 0x1000
209 0x12000 0x1000>;
210 interrupts = <16 2 1 27
211 16 2 1 26
212 16 2 1 25>;
213 };
214
215 corenet-cf@18000 {
216 compatible = "fsl,corenet-cf";
217 reg = <0x18000 0x1000>;
218 interrupts = <16 2 1 31>;
219 fsl,ccf-num-csdids = <32>;
220 fsl,ccf-num-snoopids = <32>;
221 };
222
223 iommu@20000 {
224 compatible = "fsl,pamu-v1.0", "fsl,pamu";
225 reg = <0x20000 0x6000>;
226 interrupts = <
227 24 2 0 0
228 16 2 1 30>;
229 };
230
231/include/ "fsl/qoriq-mpic.dtsi"
232
233 guts: global-utilities@e0000 {
234 compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
235 reg = <0xe0000 0xe00>;
236 fsl,has-rstcr;
237 fsl,liodn-bits = <12>;
238 };
239
240 clockgen: global-utilities@e1000 {
241 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
242 reg = <0xe1000 0x1000>;
243 };
244
245/include/ "fsl/qoriq-dma-0.dtsi"
246/include/ "fsl/qoriq-dma-1.dtsi"
247
248/include/ "fsl/qoriq-i2c-0.dtsi"
249/include/ "fsl/qoriq-i2c-1.dtsi"
250/include/ "fsl/qoriq-duart-0.dtsi"
251/include/ "fsl/qoriq-duart-1.dtsi"
252
253 L2_1: l2-cache-controller@c20000 {
254 compatible = "fsl,t4240-l2-cache-controller";
255 reg = <0xc20000 0x40000>;
256 next-level-cache = <&cpc>;
257 };
258 L2_2: l2-cache-controller@c60000 {
259 compatible = "fsl,t4240-l2-cache-controller";
260 reg = <0xc60000 0x40000>;
261 next-level-cache = <&cpc>;
262 };
263 L2_3: l2-cache-controller@ca0000 {
264 compatible = "fsl,t4240-l2-cache-controller";
265 reg = <0xca0000 0x40000>;
266 next-level-cache = <&cpc>;
267 };
268};
diff --git a/arch/powerpc/boot/dts/t4240qds.dts b/arch/powerpc/boot/dts/t4240qds.dts
index 0555976dd0f3..63e81b010804 100644
--- a/arch/powerpc/boot/dts/t4240qds.dts
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -118,36 +118,53 @@
118 }; 118 };
119 119
120 i2c@118000 { 120 i2c@118000 {
121 eeprom@51 { 121 mux@77 {
122 compatible = "at24,24c256"; 122 compatible = "nxp,pca9547";
123 reg = <0x51>; 123 reg = <0x77>;
124 }; 124 #address-cells = <1>;
125 eeprom@52 { 125 #size-cells = <0>;
126 compatible = "at24,24c256"; 126
127 reg = <0x52>; 127 i2c@0 {
128 }; 128 #address-cells = <1>;
129 eeprom@53 { 129 #size-cells = <0>;
130 compatible = "at24,24c256"; 130 reg = <0>;
131 reg = <0x53>; 131
132 }; 132 eeprom@51 {
133 eeprom@54 { 133 compatible = "at24,24c256";
134 compatible = "at24,24c256"; 134 reg = <0x51>;
135 reg = <0x54>; 135 };
136 }; 136 eeprom@52 {
137 eeprom@55 { 137 compatible = "at24,24c256";
138 compatible = "at24,24c256"; 138 reg = <0x52>;
139 reg = <0x55>; 139 };
140 }; 140 eeprom@53 {
141 eeprom@56 { 141 compatible = "at24,24c256";
142 compatible = "at24,24c256"; 142 reg = <0x53>;
143 reg = <0x56>; 143 };
144 }; 144 eeprom@54 {
145 rtc@68 { 145 compatible = "at24,24c256";
146 compatible = "dallas,ds3232"; 146 reg = <0x54>;
147 reg = <0x68>; 147 };
148 interrupts = <0x1 0x1 0 0>; 148 eeprom@55 {
149 compatible = "at24,24c256";
150 reg = <0x55>;
151 };
152 eeprom@56 {
153 compatible = "at24,24c256";
154 reg = <0x56>;
155 };
156 rtc@68 {
157 compatible = "dallas,ds3232";
158 reg = <0x68>;
159 interrupts = <0x1 0x1 0 0>;
160 };
161 };
149 }; 162 };
150 }; 163 };
164
165 sdhc@114000 {
166 voltage-ranges = <1800 1800 3300 3300>;
167 };
151 }; 168 };
152 169
153 pci0: pcie@ffe240000 { 170 pci0: pcie@ffe240000 {
diff --git a/arch/powerpc/configs/corenet32_smp_defconfig b/arch/powerpc/configs/corenet32_smp_defconfig
index 3dfab4c40c76..bbd794deb6eb 100644
--- a/arch/powerpc/configs/corenet32_smp_defconfig
+++ b/arch/powerpc/configs/corenet32_smp_defconfig
@@ -23,11 +23,7 @@ CONFIG_MODVERSIONS=y
23# CONFIG_BLK_DEV_BSG is not set 23# CONFIG_BLK_DEV_BSG is not set
24CONFIG_PARTITION_ADVANCED=y 24CONFIG_PARTITION_ADVANCED=y
25CONFIG_MAC_PARTITION=y 25CONFIG_MAC_PARTITION=y
26CONFIG_P2041_RDB=y 26CONFIG_CORENET_GENERIC=y
27CONFIG_P3041_DS=y
28CONFIG_P4080_DS=y
29CONFIG_P5020_DS=y
30CONFIG_P5040_DS=y
31CONFIG_HIGHMEM=y 27CONFIG_HIGHMEM=y
32# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set 28# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
33CONFIG_BINFMT_MISC=m 29CONFIG_BINFMT_MISC=m
@@ -104,6 +100,7 @@ CONFIG_FSL_PQ_MDIO=y
104CONFIG_E1000=y 100CONFIG_E1000=y
105CONFIG_E1000E=y 101CONFIG_E1000E=y
106CONFIG_VITESSE_PHY=y 102CONFIG_VITESSE_PHY=y
103CONFIG_AT803X_PHY=y
107CONFIG_FIXED_PHY=y 104CONFIG_FIXED_PHY=y
108# CONFIG_INPUT_MOUSEDEV is not set 105# CONFIG_INPUT_MOUSEDEV is not set
109# CONFIG_INPUT_KEYBOARD is not set 106# CONFIG_INPUT_KEYBOARD is not set
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index fa94fb3bb44d..63508ddee11c 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -21,10 +21,7 @@ CONFIG_MODVERSIONS=y
21# CONFIG_BLK_DEV_BSG is not set 21# CONFIG_BLK_DEV_BSG is not set
22CONFIG_PARTITION_ADVANCED=y 22CONFIG_PARTITION_ADVANCED=y
23CONFIG_MAC_PARTITION=y 23CONFIG_MAC_PARTITION=y
24CONFIG_B4_QDS=y 24CONFIG_CORENET_GENERIC=y
25CONFIG_P5020_DS=y
26CONFIG_P5040_DS=y
27CONFIG_T4240_QDS=y
28# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set 25# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
29CONFIG_BINFMT_MISC=m 26CONFIG_BINFMT_MISC=m
30CONFIG_MATH_EMULATION=y 27CONFIG_MATH_EMULATION=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index dc098d988211..d2e0fab5ee5b 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -138,6 +138,7 @@ CONFIG_MARVELL_PHY=y
138CONFIG_DAVICOM_PHY=y 138CONFIG_DAVICOM_PHY=y
139CONFIG_CICADA_PHY=y 139CONFIG_CICADA_PHY=y
140CONFIG_VITESSE_PHY=y 140CONFIG_VITESSE_PHY=y
141CONFIG_AT803X_PHY=y
141CONFIG_FIXED_PHY=y 142CONFIG_FIXED_PHY=y
142CONFIG_INPUT_FF_MEMLESS=m 143CONFIG_INPUT_FF_MEMLESS=m
143# CONFIG_INPUT_MOUSEDEV is not set 144# CONFIG_INPUT_MOUSEDEV is not set
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 5bca60161bb3..4cb7b59e98bd 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -138,6 +138,7 @@ CONFIG_MARVELL_PHY=y
138CONFIG_DAVICOM_PHY=y 138CONFIG_DAVICOM_PHY=y
139CONFIG_CICADA_PHY=y 139CONFIG_CICADA_PHY=y
140CONFIG_VITESSE_PHY=y 140CONFIG_VITESSE_PHY=y
141CONFIG_AT803X_PHY=y
141CONFIG_FIXED_PHY=y 142CONFIG_FIXED_PHY=y
142CONFIG_INPUT_FF_MEMLESS=m 143CONFIG_INPUT_FF_MEMLESS=m
143# CONFIG_INPUT_MOUSEDEV is not set 144# CONFIG_INPUT_MOUSEDEV is not set
diff --git a/arch/powerpc/configs/ppc64e_defconfig b/arch/powerpc/configs/ppc64e_defconfig
index 0085dc4642c5..0a6be6dd6003 100644
--- a/arch/powerpc/configs/ppc64e_defconfig
+++ b/arch/powerpc/configs/ppc64e_defconfig
@@ -23,7 +23,7 @@ CONFIG_MODULE_SRCVERSION_ALL=y
23CONFIG_PARTITION_ADVANCED=y 23CONFIG_PARTITION_ADVANCED=y
24CONFIG_MAC_PARTITION=y 24CONFIG_MAC_PARTITION=y
25CONFIG_EFI_PARTITION=y 25CONFIG_EFI_PARTITION=y
26CONFIG_P5020_DS=y 26CONFIG_CORENET_GENERIC=y
27CONFIG_CPU_FREQ=y 27CONFIG_CPU_FREQ=y
28CONFIG_CPU_FREQ_GOV_POWERSAVE=y 28CONFIG_CPU_FREQ_GOV_POWERSAVE=y
29CONFIG_CPU_FREQ_GOV_USERSPACE=y 29CONFIG_CPU_FREQ_GOV_USERSPACE=y
diff --git a/arch/powerpc/configs/ppc6xx_defconfig b/arch/powerpc/configs/ppc6xx_defconfig
index 20ebfaf7234b..c2353bf059fd 100644
--- a/arch/powerpc/configs/ppc6xx_defconfig
+++ b/arch/powerpc/configs/ppc6xx_defconfig
@@ -71,7 +71,7 @@ CONFIG_QUICC_ENGINE=y
71CONFIG_QE_GPIO=y 71CONFIG_QE_GPIO=y
72CONFIG_PPC_BESTCOMM=y 72CONFIG_PPC_BESTCOMM=y
73CONFIG_GPIO_MPC8XXX=y 73CONFIG_GPIO_MPC8XXX=y
74CONFIG_MCU_MPC8349EMITX=m 74CONFIG_MCU_MPC8349EMITX=y
75CONFIG_HIGHMEM=y 75CONFIG_HIGHMEM=y
76CONFIG_NO_HZ=y 76CONFIG_NO_HZ=y
77CONFIG_HIGH_RES_TIMERS=y 77CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/powerpc/include/asm/emulated_ops.h b/arch/powerpc/include/asm/emulated_ops.h
index 5a8b82aa7241..4358e3002f35 100644
--- a/arch/powerpc/include/asm/emulated_ops.h
+++ b/arch/powerpc/include/asm/emulated_ops.h
@@ -43,6 +43,7 @@ extern struct ppc_emulated {
43 struct ppc_emulated_entry popcntb; 43 struct ppc_emulated_entry popcntb;
44 struct ppc_emulated_entry spe; 44 struct ppc_emulated_entry spe;
45 struct ppc_emulated_entry string; 45 struct ppc_emulated_entry string;
46 struct ppc_emulated_entry sync;
46 struct ppc_emulated_entry unaligned; 47 struct ppc_emulated_entry unaligned;
47#ifdef CONFIG_MATH_EMULATION 48#ifdef CONFIG_MATH_EMULATION
48 struct ppc_emulated_entry math; 49 struct ppc_emulated_entry math;
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index ad5fcf51b252..442edee4b6aa 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -143,6 +143,8 @@
143#define PPC_INST_LSWX 0x7c00042a 143#define PPC_INST_LSWX 0x7c00042a
144#define PPC_INST_LWARX 0x7c000028 144#define PPC_INST_LWARX 0x7c000028
145#define PPC_INST_LWSYNC 0x7c2004ac 145#define PPC_INST_LWSYNC 0x7c2004ac
146#define PPC_INST_SYNC 0x7c0004ac
147#define PPC_INST_SYNC_MASK 0xfc0007fe
146#define PPC_INST_LXVD2X 0x7c000698 148#define PPC_INST_LXVD2X 0x7c000698
147#define PPC_INST_MCRXR 0x7c000400 149#define PPC_INST_MCRXR 0x7c000400
148#define PPC_INST_MCRXR_MASK 0xfc0007fe 150#define PPC_INST_MCRXR_MASK 0xfc0007fe
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index c1583070937d..7794b2b04eb2 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -167,21 +167,7 @@ struct thread_vr_state {
167 vector128 vscr __attribute__((aligned(16))); 167 vector128 vscr __attribute__((aligned(16)));
168}; 168};
169 169
170struct thread_struct { 170struct debug_reg {
171 unsigned long ksp; /* Kernel stack pointer */
172#ifdef CONFIG_PPC64
173 unsigned long ksp_vsid;
174#endif
175 struct pt_regs *regs; /* Pointer to saved register state */
176 mm_segment_t fs; /* for get_fs() validation */
177#ifdef CONFIG_BOOKE
178 /* BookE base exception scratch space; align on cacheline */
179 unsigned long normsave[8] ____cacheline_aligned;
180#endif
181#ifdef CONFIG_PPC32
182 void *pgdir; /* root of page-table tree */
183 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
184#endif
185#ifdef CONFIG_PPC_ADV_DEBUG_REGS 171#ifdef CONFIG_PPC_ADV_DEBUG_REGS
186 /* 172 /*
187 * The following help to manage the use of Debug Control Registers 173 * The following help to manage the use of Debug Control Registers
@@ -218,6 +204,24 @@ struct thread_struct {
218 unsigned long dvc2; 204 unsigned long dvc2;
219#endif 205#endif
220#endif 206#endif
207};
208
209struct thread_struct {
210 unsigned long ksp; /* Kernel stack pointer */
211#ifdef CONFIG_PPC64
212 unsigned long ksp_vsid;
213#endif
214 struct pt_regs *regs; /* Pointer to saved register state */
215 mm_segment_t fs; /* for get_fs() validation */
216#ifdef CONFIG_BOOKE
217 /* BookE base exception scratch space; align on cacheline */
218 unsigned long normsave[8] ____cacheline_aligned;
219#endif
220#ifdef CONFIG_PPC32
221 void *pgdir; /* root of page-table tree */
222 unsigned long ksp_limit; /* if ksp <= ksp_limit stack overflow */
223#endif
224 struct debug_reg debug;
221 struct thread_fp_state fp_state; 225 struct thread_fp_state fp_state;
222 struct thread_fp_state *fp_save_area; 226 struct thread_fp_state *fp_save_area;
223 int fpexc_mode; /* floating-point exception mode */ 227 int fpexc_mode; /* floating-point exception mode */
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index ed8f836da094..2e31aacd8acc 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -381,7 +381,7 @@
381#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ 381#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
382#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 382#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
383 383
384#define dbcr_iac_range(task) ((task)->thread.dbcr0) 384#define dbcr_iac_range(task) ((task)->thread.debug.dbcr0)
385#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */ 385#define DBCR_IAC12I DBCR0_IA12 /* Range Inclusive */
386#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */ 386#define DBCR_IAC12X (DBCR0_IA12 | DBCR0_IA12X) /* Range Exclusive */
387#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */ 387#define DBCR_IAC12MODE (DBCR0_IA12 | DBCR0_IA12X) /* IAC 1-2 Mode Bits */
@@ -395,7 +395,7 @@
395#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */ 395#define DBCR1_DAC1W 0x20000000 /* DAC1 Write Debug Event */
396#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */ 396#define DBCR1_DAC2W 0x10000000 /* DAC2 Write Debug Event */
397 397
398#define dbcr_dac(task) ((task)->thread.dbcr1) 398#define dbcr_dac(task) ((task)->thread.debug.dbcr1)
399#define DBCR_DAC1R DBCR1_DAC1R 399#define DBCR_DAC1R DBCR1_DAC1R
400#define DBCR_DAC1W DBCR1_DAC1W 400#define DBCR_DAC1W DBCR1_DAC1W
401#define DBCR_DAC2R DBCR1_DAC2R 401#define DBCR_DAC2R DBCR1_DAC2R
@@ -441,7 +441,7 @@
441#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */ 441#define DBCR0_CRET 0x00000020 /* Critical Return Debug Event */
442#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 442#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
443 443
444#define dbcr_dac(task) ((task)->thread.dbcr0) 444#define dbcr_dac(task) ((task)->thread.debug.dbcr0)
445#define DBCR_DAC1R DBCR0_DAC1R 445#define DBCR_DAC1R DBCR0_DAC1R
446#define DBCR_DAC1W DBCR0_DAC1W 446#define DBCR_DAC1W DBCR0_DAC1W
447#define DBCR_DAC2R DBCR0_DAC2R 447#define DBCR_DAC2R DBCR0_DAC2R
@@ -475,7 +475,7 @@
475#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */ 475#define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
476#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */ 476#define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
477 477
478#define dbcr_iac_range(task) ((task)->thread.dbcr1) 478#define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
479#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */ 479#define DBCR_IAC12I DBCR1_IAC12M /* Range Inclusive */
480#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */ 480#define DBCR_IAC12X DBCR1_IAC12MX /* Range Exclusive */
481#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */ 481#define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
diff --git a/arch/powerpc/include/asm/switch_to.h b/arch/powerpc/include/asm/switch_to.h
index 2be5618cdec6..9ee12610af02 100644
--- a/arch/powerpc/include/asm/switch_to.h
+++ b/arch/powerpc/include/asm/switch_to.h
@@ -35,6 +35,7 @@ extern void giveup_vsx(struct task_struct *);
35extern void enable_kernel_spe(void); 35extern void enable_kernel_spe(void);
36extern void giveup_spe(struct task_struct *); 36extern void giveup_spe(struct task_struct *);
37extern void load_up_spe(struct task_struct *); 37extern void load_up_spe(struct task_struct *);
38extern void switch_booke_debug_regs(struct thread_struct *new_thread);
38 39
39#ifndef CONFIG_SMP 40#ifndef CONFIG_SMP
40extern void discard_lazy_cpu_state(void); 41extern void discard_lazy_cpu_state(void);
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 6278edddc3f8..e60a3697932c 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -115,7 +115,7 @@ int main(void)
115#endif /* CONFIG_SPE */ 115#endif /* CONFIG_SPE */
116#endif /* CONFIG_PPC64 */ 116#endif /* CONFIG_PPC64 */
117#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE) 117#if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
118 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, dbcr0)); 118 DEFINE(THREAD_DBCR0, offsetof(struct thread_struct, debug.dbcr0));
119#endif 119#endif
120#ifdef CONFIG_KVM_BOOK3S_32_HANDLER 120#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
121 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu)); 121 DEFINE(THREAD_KVM_SVCPU, offsetof(struct thread_struct, kvm_shadow_vcpu));
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index 68d74b45232d..e7751561fd1d 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -399,7 +399,7 @@ interrupt_end_book3e:
399 399
400/* Altivec Unavailable Interrupt */ 400/* Altivec Unavailable Interrupt */
401 START_EXCEPTION(altivec_unavailable); 401 START_EXCEPTION(altivec_unavailable);
402 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, 402 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_SPE_ALTIVEC_UNAVAIL,
403 PROLOG_ADDITION_NONE) 403 PROLOG_ADDITION_NONE)
404 /* we can probably do a shorter exception entry for that one... */ 404 /* we can probably do a shorter exception entry for that one... */
405 EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP) 405 EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP)
@@ -421,7 +421,8 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
421 421
422/* AltiVec Assist */ 422/* AltiVec Assist */
423 START_EXCEPTION(altivec_assist); 423 START_EXCEPTION(altivec_assist);
424 NORMAL_EXCEPTION_PROLOG(0x220, BOOKE_INTERRUPT_ALTIVEC_ASSIST, 424 NORMAL_EXCEPTION_PROLOG(0x220,
425 BOOKE_INTERRUPT_SPE_FP_DATA_ALTIVEC_ASSIST,
425 PROLOG_ADDITION_NONE) 426 PROLOG_ADDITION_NONE)
426 EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE) 427 EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE)
427 bl .save_nvgprs 428 bl .save_nvgprs
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 1b92a97b1b04..7ee876d2adb5 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -858,6 +858,9 @@ initial_mmu:
858 addis r11, r11, 0x0080 /* Add 8M */ 858 addis r11, r11, 0x0080 /* Add 8M */
859 mtspr SPRN_MD_RPN, r11 859 mtspr SPRN_MD_RPN, r11
860 860
861 addi r10, r10, 0x0100
862 mtspr SPRN_MD_CTR, r10
863
861 addis r8, r8, 0x0080 /* Add 8M */ 864 addis r8, r8, 0x0080 /* Add 8M */
862 mtspr SPRN_MD_EPN, r8 865 mtspr SPRN_MD_EPN, r8
863 mtspr SPRN_MD_TWC, r9 866 mtspr SPRN_MD_TWC, r9
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S
index 289afaffbbb5..f45726a1d963 100644
--- a/arch/powerpc/kernel/head_fsl_booke.S
+++ b/arch/powerpc/kernel/head_fsl_booke.S
@@ -555,27 +555,27 @@ END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
555#ifdef CONFIG_SPE 555#ifdef CONFIG_SPE
556 /* SPE Unavailable */ 556 /* SPE Unavailable */
557 START_EXCEPTION(SPEUnavailable) 557 START_EXCEPTION(SPEUnavailable)
558 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL) 558 NORMAL_EXCEPTION_PROLOG(SPE_ALTIVEC_UNAVAIL)
559 beq 1f 559 beq 1f
560 bl load_up_spe 560 bl load_up_spe
561 b fast_exception_return 561 b fast_exception_return
5621: addi r3,r1,STACK_FRAME_OVERHEAD 5621: addi r3,r1,STACK_FRAME_OVERHEAD
563 EXC_XFER_EE_LITE(0x2010, KernelSPE) 563 EXC_XFER_EE_LITE(0x2010, KernelSPE)
564#else 564#else
565 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \ 565 EXCEPTION(0x2020, SPE_ALTIVEC_UNAVAIL, SPEUnavailable, \
566 unknown_exception, EXC_XFER_EE) 566 unknown_exception, EXC_XFER_EE)
567#endif /* CONFIG_SPE */ 567#endif /* CONFIG_SPE */
568 568
569 /* SPE Floating Point Data */ 569 /* SPE Floating Point Data */
570#ifdef CONFIG_SPE 570#ifdef CONFIG_SPE
571 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData, \ 571 EXCEPTION(0x2030, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
572 SPEFloatingPointException, EXC_XFER_EE); 572 SPEFloatingPointException, EXC_XFER_EE)
573 573
574 /* SPE Floating Point Round */ 574 /* SPE Floating Point Round */
575 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ 575 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
576 SPEFloatingPointRoundException, EXC_XFER_EE) 576 SPEFloatingPointRoundException, EXC_XFER_EE)
577#else 577#else
578 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData, \ 578 EXCEPTION(0x2040, SPE_FP_DATA_ALTIVEC_ASSIST, SPEFloatingPointData,
579 unknown_exception, EXC_XFER_EE) 579 unknown_exception, EXC_XFER_EE)
580 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \ 580 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
581 unknown_exception, EXC_XFER_EE) 581 unknown_exception, EXC_XFER_EE)
diff --git a/arch/powerpc/kernel/kgdb.c b/arch/powerpc/kernel/kgdb.c
index c1eef241017a..83e89d310734 100644
--- a/arch/powerpc/kernel/kgdb.c
+++ b/arch/powerpc/kernel/kgdb.c
@@ -151,15 +151,16 @@ static int kgdb_handle_breakpoint(struct pt_regs *regs)
151 return 1; 151 return 1;
152} 152}
153 153
154static DEFINE_PER_CPU(struct thread_info, kgdb_thread_info);
154static int kgdb_singlestep(struct pt_regs *regs) 155static int kgdb_singlestep(struct pt_regs *regs)
155{ 156{
156 struct thread_info *thread_info, *exception_thread_info; 157 struct thread_info *thread_info, *exception_thread_info;
157 struct thread_info *backup_current_thread_info; 158 struct thread_info *backup_current_thread_info =
159 &__get_cpu_var(kgdb_thread_info);
158 160
159 if (user_mode(regs)) 161 if (user_mode(regs))
160 return 0; 162 return 0;
161 163
162 backup_current_thread_info = kmalloc(sizeof(struct thread_info), GFP_KERNEL);
163 /* 164 /*
164 * On Book E and perhaps other processors, singlestep is handled on 165 * On Book E and perhaps other processors, singlestep is handled on
165 * the critical exception stack. This causes current_thread_info() 166 * the critical exception stack. This causes current_thread_info()
@@ -185,7 +186,6 @@ static int kgdb_singlestep(struct pt_regs *regs)
185 /* Restore current_thread_info lastly. */ 186 /* Restore current_thread_info lastly. */
186 memcpy(exception_thread_info, backup_current_thread_info, sizeof *thread_info); 187 memcpy(exception_thread_info, backup_current_thread_info, sizeof *thread_info);
187 188
188 kfree(backup_current_thread_info);
189 return 1; 189 return 1;
190} 190}
191 191
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 8649a3d629e1..4d42c4de8b9b 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -314,28 +314,28 @@ static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
314 */ 314 */
315static void set_debug_reg_defaults(struct thread_struct *thread) 315static void set_debug_reg_defaults(struct thread_struct *thread)
316{ 316{
317 thread->iac1 = thread->iac2 = 0; 317 thread->debug.iac1 = thread->debug.iac2 = 0;
318#if CONFIG_PPC_ADV_DEBUG_IACS > 2 318#if CONFIG_PPC_ADV_DEBUG_IACS > 2
319 thread->iac3 = thread->iac4 = 0; 319 thread->debug.iac3 = thread->debug.iac4 = 0;
320#endif 320#endif
321 thread->dac1 = thread->dac2 = 0; 321 thread->debug.dac1 = thread->debug.dac2 = 0;
322#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 322#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
323 thread->dvc1 = thread->dvc2 = 0; 323 thread->debug.dvc1 = thread->debug.dvc2 = 0;
324#endif 324#endif
325 thread->dbcr0 = 0; 325 thread->debug.dbcr0 = 0;
326#ifdef CONFIG_BOOKE 326#ifdef CONFIG_BOOKE
327 /* 327 /*
328 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1) 328 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
329 */ 329 */
330 thread->dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US | \ 330 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
331 DBCR1_IAC3US | DBCR1_IAC4US; 331 DBCR1_IAC3US | DBCR1_IAC4US;
332 /* 332 /*
333 * Force Data Address Compare User/Supervisor bits to be User-only 333 * Force Data Address Compare User/Supervisor bits to be User-only
334 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0. 334 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
335 */ 335 */
336 thread->dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US; 336 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
337#else 337#else
338 thread->dbcr1 = 0; 338 thread->debug.dbcr1 = 0;
339#endif 339#endif
340} 340}
341 341
@@ -348,22 +348,22 @@ static void prime_debug_regs(struct thread_struct *thread)
348 */ 348 */
349 mtmsr(mfmsr() & ~MSR_DE); 349 mtmsr(mfmsr() & ~MSR_DE);
350 350
351 mtspr(SPRN_IAC1, thread->iac1); 351 mtspr(SPRN_IAC1, thread->debug.iac1);
352 mtspr(SPRN_IAC2, thread->iac2); 352 mtspr(SPRN_IAC2, thread->debug.iac2);
353#if CONFIG_PPC_ADV_DEBUG_IACS > 2 353#if CONFIG_PPC_ADV_DEBUG_IACS > 2
354 mtspr(SPRN_IAC3, thread->iac3); 354 mtspr(SPRN_IAC3, thread->debug.iac3);
355 mtspr(SPRN_IAC4, thread->iac4); 355 mtspr(SPRN_IAC4, thread->debug.iac4);
356#endif 356#endif
357 mtspr(SPRN_DAC1, thread->dac1); 357 mtspr(SPRN_DAC1, thread->debug.dac1);
358 mtspr(SPRN_DAC2, thread->dac2); 358 mtspr(SPRN_DAC2, thread->debug.dac2);
359#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 359#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
360 mtspr(SPRN_DVC1, thread->dvc1); 360 mtspr(SPRN_DVC1, thread->debug.dvc1);
361 mtspr(SPRN_DVC2, thread->dvc2); 361 mtspr(SPRN_DVC2, thread->debug.dvc2);
362#endif 362#endif
363 mtspr(SPRN_DBCR0, thread->dbcr0); 363 mtspr(SPRN_DBCR0, thread->debug.dbcr0);
364 mtspr(SPRN_DBCR1, thread->dbcr1); 364 mtspr(SPRN_DBCR1, thread->debug.dbcr1);
365#ifdef CONFIG_BOOKE 365#ifdef CONFIG_BOOKE
366 mtspr(SPRN_DBCR2, thread->dbcr2); 366 mtspr(SPRN_DBCR2, thread->debug.dbcr2);
367#endif 367#endif
368} 368}
369/* 369/*
@@ -371,12 +371,13 @@ static void prime_debug_regs(struct thread_struct *thread)
371 * debug registers, set the debug registers from the values 371 * debug registers, set the debug registers from the values
372 * stored in the new thread. 372 * stored in the new thread.
373 */ 373 */
374static void switch_booke_debug_regs(struct thread_struct *new_thread) 374void switch_booke_debug_regs(struct thread_struct *new_thread)
375{ 375{
376 if ((current->thread.dbcr0 & DBCR0_IDM) 376 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
377 || (new_thread->dbcr0 & DBCR0_IDM)) 377 || (new_thread->debug.dbcr0 & DBCR0_IDM))
378 prime_debug_regs(new_thread); 378 prime_debug_regs(new_thread);
379} 379}
380EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
380#else /* !CONFIG_PPC_ADV_DEBUG_REGS */ 381#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
381#ifndef CONFIG_HAVE_HW_BREAKPOINT 382#ifndef CONFIG_HAVE_HW_BREAKPOINT
382static void set_debug_reg_defaults(struct thread_struct *thread) 383static void set_debug_reg_defaults(struct thread_struct *thread)
diff --git a/arch/powerpc/kernel/ptrace.c b/arch/powerpc/kernel/ptrace.c
index 1ca589c9ec6d..75fb40498b41 100644
--- a/arch/powerpc/kernel/ptrace.c
+++ b/arch/powerpc/kernel/ptrace.c
@@ -658,7 +658,7 @@ static const struct user_regset native_regsets[] = {
658#endif 658#endif
659#ifdef CONFIG_SPE 659#ifdef CONFIG_SPE
660 [REGSET_SPE] = { 660 [REGSET_SPE] = {
661 .n = 35, 661 .core_note_type = NT_PPC_SPE, .n = 35,
662 .size = sizeof(u32), .align = sizeof(u32), 662 .size = sizeof(u32), .align = sizeof(u32),
663 .active = evr_active, .get = evr_get, .set = evr_set 663 .active = evr_active, .get = evr_get, .set = evr_set
664 }, 664 },
@@ -855,8 +855,8 @@ void user_enable_single_step(struct task_struct *task)
855 855
856 if (regs != NULL) { 856 if (regs != NULL) {
857#ifdef CONFIG_PPC_ADV_DEBUG_REGS 857#ifdef CONFIG_PPC_ADV_DEBUG_REGS
858 task->thread.dbcr0 &= ~DBCR0_BT; 858 task->thread.debug.dbcr0 &= ~DBCR0_BT;
859 task->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 859 task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
860 regs->msr |= MSR_DE; 860 regs->msr |= MSR_DE;
861#else 861#else
862 regs->msr &= ~MSR_BE; 862 regs->msr &= ~MSR_BE;
@@ -872,8 +872,8 @@ void user_enable_block_step(struct task_struct *task)
872 872
873 if (regs != NULL) { 873 if (regs != NULL) {
874#ifdef CONFIG_PPC_ADV_DEBUG_REGS 874#ifdef CONFIG_PPC_ADV_DEBUG_REGS
875 task->thread.dbcr0 &= ~DBCR0_IC; 875 task->thread.debug.dbcr0 &= ~DBCR0_IC;
876 task->thread.dbcr0 = DBCR0_IDM | DBCR0_BT; 876 task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
877 regs->msr |= MSR_DE; 877 regs->msr |= MSR_DE;
878#else 878#else
879 regs->msr &= ~MSR_SE; 879 regs->msr &= ~MSR_SE;
@@ -895,16 +895,16 @@ void user_disable_single_step(struct task_struct *task)
895 * And, after doing so, if all debug flags are off, turn 895 * And, after doing so, if all debug flags are off, turn
896 * off DBCR0(IDM) and MSR(DE) .... Torez 896 * off DBCR0(IDM) and MSR(DE) .... Torez
897 */ 897 */
898 task->thread.dbcr0 &= ~DBCR0_IC; 898 task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
899 /* 899 /*
900 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set. 900 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
901 */ 901 */
902 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, 902 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
903 task->thread.dbcr1)) { 903 task->thread.debug.dbcr1)) {
904 /* 904 /*
905 * All debug events were off..... 905 * All debug events were off.....
906 */ 906 */
907 task->thread.dbcr0 &= ~DBCR0_IDM; 907 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
908 regs->msr &= ~MSR_DE; 908 regs->msr &= ~MSR_DE;
909 } 909 }
910#else 910#else
@@ -1023,14 +1023,14 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
1023 */ 1023 */
1024 1024
1025 /* DAC's hold the whole address without any mode flags */ 1025 /* DAC's hold the whole address without any mode flags */
1026 task->thread.dac1 = data & ~0x3UL; 1026 task->thread.debug.dac1 = data & ~0x3UL;
1027 1027
1028 if (task->thread.dac1 == 0) { 1028 if (task->thread.debug.dac1 == 0) {
1029 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1029 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1030 if (!DBCR_ACTIVE_EVENTS(task->thread.dbcr0, 1030 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
1031 task->thread.dbcr1)) { 1031 task->thread.debug.dbcr1)) {
1032 task->thread.regs->msr &= ~MSR_DE; 1032 task->thread.regs->msr &= ~MSR_DE;
1033 task->thread.dbcr0 &= ~DBCR0_IDM; 1033 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
1034 } 1034 }
1035 return 0; 1035 return 0;
1036 } 1036 }
@@ -1042,7 +1042,7 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
1042 1042
1043 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0 1043 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
1044 register */ 1044 register */
1045 task->thread.dbcr0 |= DBCR0_IDM; 1045 task->thread.debug.dbcr0 |= DBCR0_IDM;
1046 1046
1047 /* Check for write and read flags and set DBCR0 1047 /* Check for write and read flags and set DBCR0
1048 accordingly */ 1048 accordingly */
@@ -1072,10 +1072,10 @@ static long set_instruction_bp(struct task_struct *child,
1072 struct ppc_hw_breakpoint *bp_info) 1072 struct ppc_hw_breakpoint *bp_info)
1073{ 1073{
1074 int slot; 1074 int slot;
1075 int slot1_in_use = ((child->thread.dbcr0 & DBCR0_IAC1) != 0); 1075 int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
1076 int slot2_in_use = ((child->thread.dbcr0 & DBCR0_IAC2) != 0); 1076 int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
1077 int slot3_in_use = ((child->thread.dbcr0 & DBCR0_IAC3) != 0); 1077 int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
1078 int slot4_in_use = ((child->thread.dbcr0 & DBCR0_IAC4) != 0); 1078 int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
1079 1079
1080 if (dbcr_iac_range(child) & DBCR_IAC12MODE) 1080 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1081 slot2_in_use = 1; 1081 slot2_in_use = 1;
@@ -1094,9 +1094,9 @@ static long set_instruction_bp(struct task_struct *child,
1094 /* We need a pair of IAC regsisters */ 1094 /* We need a pair of IAC regsisters */
1095 if ((!slot1_in_use) && (!slot2_in_use)) { 1095 if ((!slot1_in_use) && (!slot2_in_use)) {
1096 slot = 1; 1096 slot = 1;
1097 child->thread.iac1 = bp_info->addr; 1097 child->thread.debug.iac1 = bp_info->addr;
1098 child->thread.iac2 = bp_info->addr2; 1098 child->thread.debug.iac2 = bp_info->addr2;
1099 child->thread.dbcr0 |= DBCR0_IAC1; 1099 child->thread.debug.dbcr0 |= DBCR0_IAC1;
1100 if (bp_info->addr_mode == 1100 if (bp_info->addr_mode ==
1101 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) 1101 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1102 dbcr_iac_range(child) |= DBCR_IAC12X; 1102 dbcr_iac_range(child) |= DBCR_IAC12X;
@@ -1105,9 +1105,9 @@ static long set_instruction_bp(struct task_struct *child,
1105#if CONFIG_PPC_ADV_DEBUG_IACS > 2 1105#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1106 } else if ((!slot3_in_use) && (!slot4_in_use)) { 1106 } else if ((!slot3_in_use) && (!slot4_in_use)) {
1107 slot = 3; 1107 slot = 3;
1108 child->thread.iac3 = bp_info->addr; 1108 child->thread.debug.iac3 = bp_info->addr;
1109 child->thread.iac4 = bp_info->addr2; 1109 child->thread.debug.iac4 = bp_info->addr2;
1110 child->thread.dbcr0 |= DBCR0_IAC3; 1110 child->thread.debug.dbcr0 |= DBCR0_IAC3;
1111 if (bp_info->addr_mode == 1111 if (bp_info->addr_mode ==
1112 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) 1112 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1113 dbcr_iac_range(child) |= DBCR_IAC34X; 1113 dbcr_iac_range(child) |= DBCR_IAC34X;
@@ -1127,30 +1127,30 @@ static long set_instruction_bp(struct task_struct *child,
1127 */ 1127 */
1128 if (slot2_in_use || (slot3_in_use == slot4_in_use)) { 1128 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
1129 slot = 1; 1129 slot = 1;
1130 child->thread.iac1 = bp_info->addr; 1130 child->thread.debug.iac1 = bp_info->addr;
1131 child->thread.dbcr0 |= DBCR0_IAC1; 1131 child->thread.debug.dbcr0 |= DBCR0_IAC1;
1132 goto out; 1132 goto out;
1133 } 1133 }
1134 } 1134 }
1135 if (!slot2_in_use) { 1135 if (!slot2_in_use) {
1136 slot = 2; 1136 slot = 2;
1137 child->thread.iac2 = bp_info->addr; 1137 child->thread.debug.iac2 = bp_info->addr;
1138 child->thread.dbcr0 |= DBCR0_IAC2; 1138 child->thread.debug.dbcr0 |= DBCR0_IAC2;
1139#if CONFIG_PPC_ADV_DEBUG_IACS > 2 1139#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1140 } else if (!slot3_in_use) { 1140 } else if (!slot3_in_use) {
1141 slot = 3; 1141 slot = 3;
1142 child->thread.iac3 = bp_info->addr; 1142 child->thread.debug.iac3 = bp_info->addr;
1143 child->thread.dbcr0 |= DBCR0_IAC3; 1143 child->thread.debug.dbcr0 |= DBCR0_IAC3;
1144 } else if (!slot4_in_use) { 1144 } else if (!slot4_in_use) {
1145 slot = 4; 1145 slot = 4;
1146 child->thread.iac4 = bp_info->addr; 1146 child->thread.debug.iac4 = bp_info->addr;
1147 child->thread.dbcr0 |= DBCR0_IAC4; 1147 child->thread.debug.dbcr0 |= DBCR0_IAC4;
1148#endif 1148#endif
1149 } else 1149 } else
1150 return -ENOSPC; 1150 return -ENOSPC;
1151 } 1151 }
1152out: 1152out:
1153 child->thread.dbcr0 |= DBCR0_IDM; 1153 child->thread.debug.dbcr0 |= DBCR0_IDM;
1154 child->thread.regs->msr |= MSR_DE; 1154 child->thread.regs->msr |= MSR_DE;
1155 1155
1156 return slot; 1156 return slot;
@@ -1160,49 +1160,49 @@ static int del_instruction_bp(struct task_struct *child, int slot)
1160{ 1160{
1161 switch (slot) { 1161 switch (slot) {
1162 case 1: 1162 case 1:
1163 if ((child->thread.dbcr0 & DBCR0_IAC1) == 0) 1163 if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
1164 return -ENOENT; 1164 return -ENOENT;
1165 1165
1166 if (dbcr_iac_range(child) & DBCR_IAC12MODE) { 1166 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
1167 /* address range - clear slots 1 & 2 */ 1167 /* address range - clear slots 1 & 2 */
1168 child->thread.iac2 = 0; 1168 child->thread.debug.iac2 = 0;
1169 dbcr_iac_range(child) &= ~DBCR_IAC12MODE; 1169 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
1170 } 1170 }
1171 child->thread.iac1 = 0; 1171 child->thread.debug.iac1 = 0;
1172 child->thread.dbcr0 &= ~DBCR0_IAC1; 1172 child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1173 break; 1173 break;
1174 case 2: 1174 case 2:
1175 if ((child->thread.dbcr0 & DBCR0_IAC2) == 0) 1175 if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
1176 return -ENOENT; 1176 return -ENOENT;
1177 1177
1178 if (dbcr_iac_range(child) & DBCR_IAC12MODE) 1178 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1179 /* used in a range */ 1179 /* used in a range */
1180 return -EINVAL; 1180 return -EINVAL;
1181 child->thread.iac2 = 0; 1181 child->thread.debug.iac2 = 0;
1182 child->thread.dbcr0 &= ~DBCR0_IAC2; 1182 child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1183 break; 1183 break;
1184#if CONFIG_PPC_ADV_DEBUG_IACS > 2 1184#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1185 case 3: 1185 case 3:
1186 if ((child->thread.dbcr0 & DBCR0_IAC3) == 0) 1186 if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
1187 return -ENOENT; 1187 return -ENOENT;
1188 1188
1189 if (dbcr_iac_range(child) & DBCR_IAC34MODE) { 1189 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
1190 /* address range - clear slots 3 & 4 */ 1190 /* address range - clear slots 3 & 4 */
1191 child->thread.iac4 = 0; 1191 child->thread.debug.iac4 = 0;
1192 dbcr_iac_range(child) &= ~DBCR_IAC34MODE; 1192 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
1193 } 1193 }
1194 child->thread.iac3 = 0; 1194 child->thread.debug.iac3 = 0;
1195 child->thread.dbcr0 &= ~DBCR0_IAC3; 1195 child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1196 break; 1196 break;
1197 case 4: 1197 case 4:
1198 if ((child->thread.dbcr0 & DBCR0_IAC4) == 0) 1198 if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
1199 return -ENOENT; 1199 return -ENOENT;
1200 1200
1201 if (dbcr_iac_range(child) & DBCR_IAC34MODE) 1201 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1202 /* Used in a range */ 1202 /* Used in a range */
1203 return -EINVAL; 1203 return -EINVAL;
1204 child->thread.iac4 = 0; 1204 child->thread.debug.iac4 = 0;
1205 child->thread.dbcr0 &= ~DBCR0_IAC4; 1205 child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1206 break; 1206 break;
1207#endif 1207#endif
1208 default: 1208 default:
@@ -1232,18 +1232,18 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1232 dbcr_dac(child) |= DBCR_DAC1R; 1232 dbcr_dac(child) |= DBCR_DAC1R;
1233 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) 1233 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1234 dbcr_dac(child) |= DBCR_DAC1W; 1234 dbcr_dac(child) |= DBCR_DAC1W;
1235 child->thread.dac1 = (unsigned long)bp_info->addr; 1235 child->thread.debug.dac1 = (unsigned long)bp_info->addr;
1236#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1236#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1237 if (byte_enable) { 1237 if (byte_enable) {
1238 child->thread.dvc1 = 1238 child->thread.debug.dvc1 =
1239 (unsigned long)bp_info->condition_value; 1239 (unsigned long)bp_info->condition_value;
1240 child->thread.dbcr2 |= 1240 child->thread.debug.dbcr2 |=
1241 ((byte_enable << DBCR2_DVC1BE_SHIFT) | 1241 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
1242 (condition_mode << DBCR2_DVC1M_SHIFT)); 1242 (condition_mode << DBCR2_DVC1M_SHIFT));
1243 } 1243 }
1244#endif 1244#endif
1245#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1245#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1246 } else if (child->thread.dbcr2 & DBCR2_DAC12MODE) { 1246 } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
1247 /* Both dac1 and dac2 are part of a range */ 1247 /* Both dac1 and dac2 are part of a range */
1248 return -ENOSPC; 1248 return -ENOSPC;
1249#endif 1249#endif
@@ -1253,19 +1253,19 @@ static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1253 dbcr_dac(child) |= DBCR_DAC2R; 1253 dbcr_dac(child) |= DBCR_DAC2R;
1254 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) 1254 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1255 dbcr_dac(child) |= DBCR_DAC2W; 1255 dbcr_dac(child) |= DBCR_DAC2W;
1256 child->thread.dac2 = (unsigned long)bp_info->addr; 1256 child->thread.debug.dac2 = (unsigned long)bp_info->addr;
1257#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1257#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1258 if (byte_enable) { 1258 if (byte_enable) {
1259 child->thread.dvc2 = 1259 child->thread.debug.dvc2 =
1260 (unsigned long)bp_info->condition_value; 1260 (unsigned long)bp_info->condition_value;
1261 child->thread.dbcr2 |= 1261 child->thread.debug.dbcr2 |=
1262 ((byte_enable << DBCR2_DVC2BE_SHIFT) | 1262 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
1263 (condition_mode << DBCR2_DVC2M_SHIFT)); 1263 (condition_mode << DBCR2_DVC2M_SHIFT));
1264 } 1264 }
1265#endif 1265#endif
1266 } else 1266 } else
1267 return -ENOSPC; 1267 return -ENOSPC;
1268 child->thread.dbcr0 |= DBCR0_IDM; 1268 child->thread.debug.dbcr0 |= DBCR0_IDM;
1269 child->thread.regs->msr |= MSR_DE; 1269 child->thread.regs->msr |= MSR_DE;
1270 1270
1271 return slot + 4; 1271 return slot + 4;
@@ -1277,32 +1277,32 @@ static int del_dac(struct task_struct *child, int slot)
1277 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) 1277 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
1278 return -ENOENT; 1278 return -ENOENT;
1279 1279
1280 child->thread.dac1 = 0; 1280 child->thread.debug.dac1 = 0;
1281 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1281 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1282#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1282#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1283 if (child->thread.dbcr2 & DBCR2_DAC12MODE) { 1283 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
1284 child->thread.dac2 = 0; 1284 child->thread.debug.dac2 = 0;
1285 child->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1285 child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1286 } 1286 }
1287 child->thread.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE); 1287 child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
1288#endif 1288#endif
1289#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1289#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1290 child->thread.dvc1 = 0; 1290 child->thread.debug.dvc1 = 0;
1291#endif 1291#endif
1292 } else if (slot == 2) { 1292 } else if (slot == 2) {
1293 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) 1293 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
1294 return -ENOENT; 1294 return -ENOENT;
1295 1295
1296#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1296#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1297 if (child->thread.dbcr2 & DBCR2_DAC12MODE) 1297 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
1298 /* Part of a range */ 1298 /* Part of a range */
1299 return -EINVAL; 1299 return -EINVAL;
1300 child->thread.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE); 1300 child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
1301#endif 1301#endif
1302#if CONFIG_PPC_ADV_DEBUG_DVCS > 0 1302#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1303 child->thread.dvc2 = 0; 1303 child->thread.debug.dvc2 = 0;
1304#endif 1304#endif
1305 child->thread.dac2 = 0; 1305 child->thread.debug.dac2 = 0;
1306 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W); 1306 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1307 } else 1307 } else
1308 return -EINVAL; 1308 return -EINVAL;
@@ -1344,22 +1344,22 @@ static int set_dac_range(struct task_struct *child,
1344 return -EIO; 1344 return -EIO;
1345 } 1345 }
1346 1346
1347 if (child->thread.dbcr0 & 1347 if (child->thread.debug.dbcr0 &
1348 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W)) 1348 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
1349 return -ENOSPC; 1349 return -ENOSPC;
1350 1350
1351 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ) 1351 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1352 child->thread.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM); 1352 child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
1353 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE) 1353 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1354 child->thread.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM); 1354 child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
1355 child->thread.dac1 = bp_info->addr; 1355 child->thread.debug.dac1 = bp_info->addr;
1356 child->thread.dac2 = bp_info->addr2; 1356 child->thread.debug.dac2 = bp_info->addr2;
1357 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE) 1357 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1358 child->thread.dbcr2 |= DBCR2_DAC12M; 1358 child->thread.debug.dbcr2 |= DBCR2_DAC12M;
1359 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE) 1359 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1360 child->thread.dbcr2 |= DBCR2_DAC12MX; 1360 child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
1361 else /* PPC_BREAKPOINT_MODE_MASK */ 1361 else /* PPC_BREAKPOINT_MODE_MASK */
1362 child->thread.dbcr2 |= DBCR2_DAC12MM; 1362 child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
1363 child->thread.regs->msr |= MSR_DE; 1363 child->thread.regs->msr |= MSR_DE;
1364 1364
1365 return 5; 1365 return 5;
@@ -1490,9 +1490,9 @@ static long ppc_del_hwdebug(struct task_struct *child, long data)
1490 rc = del_dac(child, (int)data - 4); 1490 rc = del_dac(child, (int)data - 4);
1491 1491
1492 if (!rc) { 1492 if (!rc) {
1493 if (!DBCR_ACTIVE_EVENTS(child->thread.dbcr0, 1493 if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
1494 child->thread.dbcr1)) { 1494 child->thread.debug.dbcr1)) {
1495 child->thread.dbcr0 &= ~DBCR0_IDM; 1495 child->thread.debug.dbcr0 &= ~DBCR0_IDM;
1496 child->thread.regs->msr &= ~MSR_DE; 1496 child->thread.regs->msr &= ~MSR_DE;
1497 } 1497 }
1498 } 1498 }
@@ -1670,7 +1670,7 @@ long arch_ptrace(struct task_struct *child, long request,
1670 if (addr > 0) 1670 if (addr > 0)
1671 break; 1671 break;
1672#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1672#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1673 ret = put_user(child->thread.dac1, datalp); 1673 ret = put_user(child->thread.debug.dac1, datalp);
1674#else 1674#else
1675 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | 1675 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
1676 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR)); 1676 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
diff --git a/arch/powerpc/kernel/ptrace32.c b/arch/powerpc/kernel/ptrace32.c
index 097f8dc426a0..f52b7db327c8 100644
--- a/arch/powerpc/kernel/ptrace32.c
+++ b/arch/powerpc/kernel/ptrace32.c
@@ -266,7 +266,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
266 if (addr > 0) 266 if (addr > 0)
267 break; 267 break;
268#ifdef CONFIG_PPC_ADV_DEBUG_REGS 268#ifdef CONFIG_PPC_ADV_DEBUG_REGS
269 ret = put_user(child->thread.dac1, (u32 __user *)data); 269 ret = put_user(child->thread.debug.dac1, (u32 __user *)data);
270#else 270#else
271 dabr_fake = ( 271 dabr_fake = (
272 (child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) | 272 (child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
diff --git a/arch/powerpc/kernel/signal_32.c b/arch/powerpc/kernel/signal_32.c
index c094e28b3f10..1a410aa57fb7 100644
--- a/arch/powerpc/kernel/signal_32.c
+++ b/arch/powerpc/kernel/signal_32.c
@@ -1312,7 +1312,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
1312 unsigned char tmp; 1312 unsigned char tmp;
1313 unsigned long new_msr = regs->msr; 1313 unsigned long new_msr = regs->msr;
1314#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1314#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1315 unsigned long new_dbcr0 = current->thread.dbcr0; 1315 unsigned long new_dbcr0 = current->thread.debug.dbcr0;
1316#endif 1316#endif
1317 1317
1318 for (i=0; i<ndbg; i++) { 1318 for (i=0; i<ndbg; i++) {
@@ -1327,7 +1327,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
1327 } else { 1327 } else {
1328 new_dbcr0 &= ~DBCR0_IC; 1328 new_dbcr0 &= ~DBCR0_IC;
1329 if (!DBCR_ACTIVE_EVENTS(new_dbcr0, 1329 if (!DBCR_ACTIVE_EVENTS(new_dbcr0,
1330 current->thread.dbcr1)) { 1330 current->thread.debug.dbcr1)) {
1331 new_msr &= ~MSR_DE; 1331 new_msr &= ~MSR_DE;
1332 new_dbcr0 &= ~DBCR0_IDM; 1332 new_dbcr0 &= ~DBCR0_IDM;
1333 } 1333 }
@@ -1362,7 +1362,7 @@ int sys_debug_setcontext(struct ucontext __user *ctx,
1362 the user is really doing something wrong. */ 1362 the user is really doing something wrong. */
1363 regs->msr = new_msr; 1363 regs->msr = new_msr;
1364#ifdef CONFIG_PPC_ADV_DEBUG_REGS 1364#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1365 current->thread.dbcr0 = new_dbcr0; 1365 current->thread.debug.dbcr0 = new_dbcr0;
1366#endif 1366#endif
1367 1367
1368 if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx)) 1368 if (!access_ok(VERIFY_READ, ctx, sizeof(*ctx))
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f0a6814007a5..62c3dd8c69f2 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -351,8 +351,8 @@ static inline int check_io_access(struct pt_regs *regs)
351#define REASON_TRAP ESR_PTR 351#define REASON_TRAP ESR_PTR
352 352
353/* single-step stuff */ 353/* single-step stuff */
354#define single_stepping(regs) (current->thread.dbcr0 & DBCR0_IC) 354#define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
355#define clear_single_step(regs) (current->thread.dbcr0 &= ~DBCR0_IC) 355#define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
356 356
357#else 357#else
358/* On non-4xx, the reason for the machine check or program 358/* On non-4xx, the reason for the machine check or program
@@ -1018,6 +1018,13 @@ static int emulate_instruction(struct pt_regs *regs)
1018 return emulate_isel(regs, instword); 1018 return emulate_isel(regs, instword);
1019 } 1019 }
1020 1020
1021 /* Emulate sync instruction variants */
1022 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1023 PPC_WARN_EMULATED(sync, regs);
1024 asm volatile("sync");
1025 return 0;
1026 }
1027
1021#ifdef CONFIG_PPC64 1028#ifdef CONFIG_PPC64
1022 /* Emulate the mfspr rD, DSCR. */ 1029 /* Emulate the mfspr rD, DSCR. */
1023 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) == 1030 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
@@ -1461,7 +1468,8 @@ void SoftwareEmulation(struct pt_regs *regs)
1461 1468
1462 if (!user_mode(regs)) { 1469 if (!user_mode(regs)) {
1463 debugger(regs); 1470 debugger(regs);
1464 die("Kernel Mode Software FPU Emulation", regs, SIGFPE); 1471 die("Kernel Mode Unimplemented Instruction or SW FPU Emulation",
1472 regs, SIGFPE);
1465 } 1473 }
1466 1474
1467 if (!emulate_math(regs)) 1475 if (!emulate_math(regs))
@@ -1482,7 +1490,7 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1482 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) { 1490 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1483 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W); 1491 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1484#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE 1492#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1485 current->thread.dbcr2 &= ~DBCR2_DAC12MODE; 1493 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1486#endif 1494#endif
1487 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT, 1495 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1488 5); 1496 5);
@@ -1493,24 +1501,24 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1493 6); 1501 6);
1494 changed |= 0x01; 1502 changed |= 0x01;
1495 } else if (debug_status & DBSR_IAC1) { 1503 } else if (debug_status & DBSR_IAC1) {
1496 current->thread.dbcr0 &= ~DBCR0_IAC1; 1504 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1497 dbcr_iac_range(current) &= ~DBCR_IAC12MODE; 1505 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1498 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT, 1506 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1499 1); 1507 1);
1500 changed |= 0x01; 1508 changed |= 0x01;
1501 } else if (debug_status & DBSR_IAC2) { 1509 } else if (debug_status & DBSR_IAC2) {
1502 current->thread.dbcr0 &= ~DBCR0_IAC2; 1510 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1503 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT, 1511 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1504 2); 1512 2);
1505 changed |= 0x01; 1513 changed |= 0x01;
1506 } else if (debug_status & DBSR_IAC3) { 1514 } else if (debug_status & DBSR_IAC3) {
1507 current->thread.dbcr0 &= ~DBCR0_IAC3; 1515 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1508 dbcr_iac_range(current) &= ~DBCR_IAC34MODE; 1516 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1509 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT, 1517 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1510 3); 1518 3);
1511 changed |= 0x01; 1519 changed |= 0x01;
1512 } else if (debug_status & DBSR_IAC4) { 1520 } else if (debug_status & DBSR_IAC4) {
1513 current->thread.dbcr0 &= ~DBCR0_IAC4; 1521 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1514 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT, 1522 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1515 4); 1523 4);
1516 changed |= 0x01; 1524 changed |= 0x01;
@@ -1520,19 +1528,20 @@ static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1520 * Check all other debug flags and see if that bit needs to be turned 1528 * Check all other debug flags and see if that bit needs to be turned
1521 * back on or not. 1529 * back on or not.
1522 */ 1530 */
1523 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, current->thread.dbcr1)) 1531 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1532 current->thread.debug.dbcr1))
1524 regs->msr |= MSR_DE; 1533 regs->msr |= MSR_DE;
1525 else 1534 else
1526 /* Make sure the IDM flag is off */ 1535 /* Make sure the IDM flag is off */
1527 current->thread.dbcr0 &= ~DBCR0_IDM; 1536 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1528 1537
1529 if (changed & 0x01) 1538 if (changed & 0x01)
1530 mtspr(SPRN_DBCR0, current->thread.dbcr0); 1539 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1531} 1540}
1532 1541
1533void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status) 1542void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1534{ 1543{
1535 current->thread.dbsr = debug_status; 1544 current->thread.debug.dbsr = debug_status;
1536 1545
1537 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while 1546 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1538 * on server, it stops on the target of the branch. In order to simulate 1547 * on server, it stops on the target of the branch. In order to simulate
@@ -1549,8 +1558,8 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1549 1558
1550 /* Do the single step trick only when coming from userspace */ 1559 /* Do the single step trick only when coming from userspace */
1551 if (user_mode(regs)) { 1560 if (user_mode(regs)) {
1552 current->thread.dbcr0 &= ~DBCR0_BT; 1561 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1553 current->thread.dbcr0 |= DBCR0_IDM | DBCR0_IC; 1562 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1554 regs->msr |= MSR_DE; 1563 regs->msr |= MSR_DE;
1555 return; 1564 return;
1556 } 1565 }
@@ -1578,13 +1587,13 @@ void __kprobes DebugException(struct pt_regs *regs, unsigned long debug_status)
1578 return; 1587 return;
1579 1588
1580 if (user_mode(regs)) { 1589 if (user_mode(regs)) {
1581 current->thread.dbcr0 &= ~DBCR0_IC; 1590 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1582 if (DBCR_ACTIVE_EVENTS(current->thread.dbcr0, 1591 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1583 current->thread.dbcr1)) 1592 current->thread.debug.dbcr1))
1584 regs->msr |= MSR_DE; 1593 regs->msr |= MSR_DE;
1585 else 1594 else
1586 /* Make sure the IDM bit is off */ 1595 /* Make sure the IDM bit is off */
1587 current->thread.dbcr0 &= ~DBCR0_IDM; 1596 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1588 } 1597 }
1589 1598
1590 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip); 1599 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
@@ -1811,6 +1820,7 @@ struct ppc_emulated ppc_emulated = {
1811 WARN_EMULATED_SETUP(popcntb), 1820 WARN_EMULATED_SETUP(popcntb),
1812 WARN_EMULATED_SETUP(spe), 1821 WARN_EMULATED_SETUP(spe),
1813 WARN_EMULATED_SETUP(string), 1822 WARN_EMULATED_SETUP(string),
1823 WARN_EMULATED_SETUP(sync),
1814 WARN_EMULATED_SETUP(unaligned), 1824 WARN_EMULATED_SETUP(unaligned),
1815#ifdef CONFIG_MATH_EMULATION 1825#ifdef CONFIG_MATH_EMULATION
1816 WARN_EMULATED_SETUP(math), 1826 WARN_EMULATED_SETUP(math),
diff --git a/arch/powerpc/mm/init_32.c b/arch/powerpc/mm/init_32.c
index d47d3dab4870..cff59f1bec23 100644
--- a/arch/powerpc/mm/init_32.c
+++ b/arch/powerpc/mm/init_32.c
@@ -213,7 +213,12 @@ void setup_initial_memory_limit(phys_addr_t first_memblock_base,
213 */ 213 */
214 BUG_ON(first_memblock_base != 0); 214 BUG_ON(first_memblock_base != 0);
215 215
216#ifdef CONFIG_PIN_TLB
217 /* 8xx can only access 24MB at the moment */
218 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x01800000));
219#else
216 /* 8xx can only access 8MB at the moment */ 220 /* 8xx can only access 8MB at the moment */
217 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000)); 221 memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
222#endif
218} 223}
219#endif /* CONFIG_8xx */ 224#endif /* CONFIG_8xx */
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index edda589795c3..841e0d00863c 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -32,8 +32,6 @@
32#include <asm/tlbflush.h> 32#include <asm/tlbflush.h>
33#include <asm/tlb.h> 33#include <asm/tlb.h>
34 34
35#include "mmu_decl.h"
36
37static inline int is_exec_fault(void) 35static inline int is_exec_fault(void)
38{ 36{
39 return current->thread.regs && TRAP(current->thread.regs) == 0x400; 37 return current->thread.regs && TRAP(current->thread.regs) == 0x400;
@@ -72,7 +70,7 @@ struct page * maybe_pte_to_page(pte_t pte)
72 * support falls into the same category. 70 * support falls into the same category.
73 */ 71 */
74 72
75static pte_t set_pte_filter(pte_t pte, unsigned long addr) 73static pte_t set_pte_filter(pte_t pte)
76{ 74{
77 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS); 75 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
78 if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) || 76 if (pte_looks_normal(pte) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
@@ -81,17 +79,6 @@ static pte_t set_pte_filter(pte_t pte, unsigned long addr)
81 if (!pg) 79 if (!pg)
82 return pte; 80 return pte;
83 if (!test_bit(PG_arch_1, &pg->flags)) { 81 if (!test_bit(PG_arch_1, &pg->flags)) {
84#ifdef CONFIG_8xx
85 /* On 8xx, cache control instructions (particularly
86 * "dcbst" from flush_dcache_icache) fault as write
87 * operation if there is an unpopulated TLB entry
88 * for the address in question. To workaround that,
89 * we invalidate the TLB here, thus avoiding dcbst
90 * misbehaviour.
91 */
92 /* 8xx doesn't care about PID, size or ind args */
93 _tlbil_va(addr, 0, 0, 0);
94#endif /* CONFIG_8xx */
95 flush_dcache_icache_page(pg); 82 flush_dcache_icache_page(pg);
96 set_bit(PG_arch_1, &pg->flags); 83 set_bit(PG_arch_1, &pg->flags);
97 } 84 }
@@ -111,7 +98,7 @@ static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
111 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so 98 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
112 * instead we "filter out" the exec permission for non clean pages. 99 * instead we "filter out" the exec permission for non clean pages.
113 */ 100 */
114static pte_t set_pte_filter(pte_t pte, unsigned long addr) 101static pte_t set_pte_filter(pte_t pte)
115{ 102{
116 struct page *pg; 103 struct page *pg;
117 104
@@ -193,7 +180,7 @@ void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
193 * this context might not have been activated yet when this 180 * this context might not have been activated yet when this
194 * is called. 181 * is called.
195 */ 182 */
196 pte = set_pte_filter(pte, addr); 183 pte = set_pte_filter(pte);
197 184
198 /* Perform the setting of the PTE */ 185 /* Perform the setting of the PTE */
199 __set_pte_at(mm, addr, ptep, pte, 0); 186 __set_pte_at(mm, addr, ptep, pte, 0);
diff --git a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
index 7bc315822935..fd71cfdf2380 100644
--- a/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
+++ b/arch/powerpc/platforms/83xx/mcu_mpc8349emitx.c
@@ -204,7 +204,6 @@ static int mcu_remove(struct i2c_client *client)
204 ret = mcu_gpiochip_remove(mcu); 204 ret = mcu_gpiochip_remove(mcu);
205 if (ret) 205 if (ret)
206 return ret; 206 return ret;
207 i2c_set_clientdata(client, NULL);
208 kfree(mcu); 207 kfree(mcu);
209 return 0; 208 return 0;
210} 209}
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index de2eb9320993..4d4634958cfb 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -218,83 +218,16 @@ config GE_IMP3A
218 This board is a 3U CompactPCI Single Board Computer with a Freescale 218 This board is a 3U CompactPCI Single Board Computer with a Freescale
219 P2020 processor. 219 P2020 processor.
220 220
221config P2041_RDB
222 bool "Freescale P2041 RDB"
223 select DEFAULT_UIMAGE
224 select PPC_E500MC
225 select PHYS_64BIT
226 select SWIOTLB
227 select ARCH_REQUIRE_GPIOLIB
228 select GPIO_MPC8XXX
229 select HAS_RAPIDIO
230 select PPC_EPAPR_HV_PIC
231 help
232 This option enables support for the P2041 RDB board
233
234config P3041_DS
235 bool "Freescale P3041 DS"
236 select DEFAULT_UIMAGE
237 select PPC_E500MC
238 select PHYS_64BIT
239 select SWIOTLB
240 select ARCH_REQUIRE_GPIOLIB
241 select GPIO_MPC8XXX
242 select HAS_RAPIDIO
243 select PPC_EPAPR_HV_PIC
244 help
245 This option enables support for the P3041 DS board
246
247config P4080_DS
248 bool "Freescale P4080 DS"
249 select DEFAULT_UIMAGE
250 select PPC_E500MC
251 select PHYS_64BIT
252 select SWIOTLB
253 select ARCH_REQUIRE_GPIOLIB
254 select GPIO_MPC8XXX
255 select HAS_RAPIDIO
256 select PPC_EPAPR_HV_PIC
257 help
258 This option enables support for the P4080 DS board
259
260config SGY_CTS1000 221config SGY_CTS1000
261 tristate "Servergy CTS-1000 support" 222 tristate "Servergy CTS-1000 support"
262 select GPIOLIB 223 select GPIOLIB
263 select OF_GPIO 224 select OF_GPIO
264 depends on P4080_DS 225 depends on CORENET_GENERIC
265 help 226 help
266 Enable this to support functionality in Servergy's CTS-1000 systems. 227 Enable this to support functionality in Servergy's CTS-1000 systems.
267 228
268endif # PPC32 229endif # PPC32
269 230
270config P5020_DS
271 bool "Freescale P5020 DS"
272 select DEFAULT_UIMAGE
273 select E500
274 select PPC_E500MC
275 select PHYS_64BIT
276 select SWIOTLB
277 select ARCH_REQUIRE_GPIOLIB
278 select GPIO_MPC8XXX
279 select HAS_RAPIDIO
280 select PPC_EPAPR_HV_PIC
281 help
282 This option enables support for the P5020 DS board
283
284config P5040_DS
285 bool "Freescale P5040 DS"
286 select DEFAULT_UIMAGE
287 select E500
288 select PPC_E500MC
289 select PHYS_64BIT
290 select SWIOTLB
291 select ARCH_REQUIRE_GPIOLIB
292 select GPIO_MPC8XXX
293 select HAS_RAPIDIO
294 select PPC_EPAPR_HV_PIC
295 help
296 This option enables support for the P5040 DS board
297
298config PPC_QEMU_E500 231config PPC_QEMU_E500
299 bool "QEMU generic e500 platform" 232 bool "QEMU generic e500 platform"
300 select DEFAULT_UIMAGE 233 select DEFAULT_UIMAGE
@@ -310,10 +243,8 @@ config PPC_QEMU_E500
310 unset based on the emulated CPU (or actual host CPU in the case 243 unset based on the emulated CPU (or actual host CPU in the case
311 of KVM). 244 of KVM).
312 245
313if PPC64 246config CORENET_GENERIC
314 247 bool "Freescale CoreNet Generic"
315config T4240_QDS
316 bool "Freescale T4240 QDS"
317 select DEFAULT_UIMAGE 248 select DEFAULT_UIMAGE
318 select E500 249 select E500
319 select PPC_E500MC 250 select PPC_E500MC
@@ -324,26 +255,14 @@ config T4240_QDS
324 select HAS_RAPIDIO 255 select HAS_RAPIDIO
325 select PPC_EPAPR_HV_PIC 256 select PPC_EPAPR_HV_PIC
326 help 257 help
327 This option enables support for the T4240 QDS board 258 This option enables support for the FSL CoreNet based boards.
328 259 For 32bit kernel, the following boards are supported:
329config B4_QDS 260 P2041 RDB, P3041 DS and P4080 DS
330 bool "Freescale B4 QDS" 261 For 64bit kernel, the following boards are supported:
331 select DEFAULT_UIMAGE 262 T4240 QDS and B4 QDS
332 select E500 263 The following boards are supported for both 32bit and 64bit kernel:
333 select PPC_E500MC 264 P5020 DS and P5040 DS
334 select PHYS_64BIT
335 select SWIOTLB
336 select GPIOLIB
337 select ARCH_REQUIRE_GPIOLIB
338 select HAS_RAPIDIO
339 select PPC_EPAPR_HV_PIC
340 help
341 This option enables support for the B4 QDS board
342 The B4 application development system B4 QDS is a complete
343 debugging environment intended for engineers developing
344 applications for the B4.
345 265
346endif
347endif # FSL_SOC_BOOKE 266endif # FSL_SOC_BOOKE
348 267
349config TQM85xx 268config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 53c9f75a6907..dd4c0b59577b 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -18,13 +18,7 @@ obj-$(CONFIG_P1010_RDB) += p1010rdb.o
18obj-$(CONFIG_P1022_DS) += p1022_ds.o 18obj-$(CONFIG_P1022_DS) += p1022_ds.o
19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o 19obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
20obj-$(CONFIG_P1023_RDS) += p1023_rds.o 20obj-$(CONFIG_P1023_RDS) += p1023_rds.o
21obj-$(CONFIG_P2041_RDB) += p2041_rdb.o corenet_ds.o 21obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
22obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
23obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
24obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
25obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
26obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o
27obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o
28obj-$(CONFIG_STX_GP3) += stx_gp3.o 22obj-$(CONFIG_STX_GP3) += stx_gp3.o
29obj-$(CONFIG_TQM85xx) += tqm85xx.o 23obj-$(CONFIG_TQM85xx) += tqm85xx.o
30obj-$(CONFIG_SBC8548) += sbc8548.o 24obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
deleted file mode 100644
index 0c6702f8b88e..000000000000
--- a/arch/powerpc/platforms/85xx/b4_qds.c
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * B4 QDS Setup
3 * Should apply for QDS platform of B4860 and it's personalities.
4 * viz B4860/B4420/B4220QDS
5 *
6 * Copyright 2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init b4_qds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
47 (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
48 (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
49 return 1;
50
51 /* Check if we're running under the Freescale hypervisor */
52 if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
53 (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
54 (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
55 ppc_md.init_IRQ = ehv_pic_init;
56 ppc_md.get_irq = ehv_pic_get_irq;
57 ppc_md.restart = fsl_hv_restart;
58 ppc_md.power_off = fsl_hv_halt;
59 ppc_md.halt = fsl_hv_halt;
60#ifdef CONFIG_SMP
61 /*
62 * Disable the timebase sync operations because we can't write
63 * to the timebase registers under the hypervisor.
64 */
65 smp_85xx_ops.give_timebase = NULL;
66 smp_85xx_ops.take_timebase = NULL;
67#endif
68 return 1;
69 }
70
71 return 0;
72}
73
74define_machine(b4_qds) {
75 .name = "B4 QDS",
76 .probe = b4_qds_probe,
77 .setup_arch = corenet_ds_setup_arch,
78 .init_IRQ = corenet_ds_pic_init,
79#ifdef CONFIG_PCI
80 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
81#endif
82/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
83#ifdef CONFIG_PPC64
84 .get_irq = mpic_get_irq,
85#else
86 .get_irq = mpic_get_coreint_irq,
87#endif
88 .restart = fsl_rstcr_restart,
89 .calibrate_decr = generic_calibrate_decr,
90 .progress = udbg_progress,
91#ifdef CONFIG_PPC64
92 .power_save = book3e_idle,
93#else
94 .power_save = e500_idle,
95#endif
96};
97
98machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
99
100#ifdef CONFIG_SWIOTLB
101machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
102#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
deleted file mode 100644
index aa3690bae415..000000000000
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * Corenet based SoC DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2011 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <asm/ppc-pci.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include "smp.h"
33
34void __init corenet_ds_pic_init(void)
35{
36 struct mpic *mpic;
37 unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
38 MPIC_NO_RESET;
39
40 if (ppc_md.get_irq == mpic_get_coreint_irq)
41 flags |= MPIC_ENABLE_COREINT;
42
43 mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
44 BUG_ON(mpic == NULL);
45
46 mpic_init(mpic);
47}
48
49/*
50 * Setup the architecture
51 */
52void __init corenet_ds_setup_arch(void)
53{
54 mpc85xx_smp_init();
55
56 swiotlb_detect_4g();
57
58 pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
59}
60
61static const struct of_device_id of_device_ids[] = {
62 {
63 .compatible = "simple-bus"
64 },
65 {
66 .compatible = "fsl,srio",
67 },
68 {
69 .compatible = "fsl,p4080-pcie",
70 },
71 {
72 .compatible = "fsl,qoriq-pcie-v2.2",
73 },
74 {
75 .compatible = "fsl,qoriq-pcie-v2.3",
76 },
77 {
78 .compatible = "fsl,qoriq-pcie-v2.4",
79 },
80 {
81 .compatible = "fsl,qoriq-pcie-v3.0",
82 },
83 /* The following two are for the Freescale hypervisor */
84 {
85 .name = "hypervisor",
86 },
87 {
88 .name = "handles",
89 },
90 {}
91};
92
93int __init corenet_ds_publish_devices(void)
94{
95 return of_platform_bus_probe(NULL, of_device_ids, NULL);
96}
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.h b/arch/powerpc/platforms/85xx/corenet_ds.h
deleted file mode 100644
index ddd700b23031..000000000000
--- a/arch/powerpc/platforms/85xx/corenet_ds.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Corenet based SoC DS Setup
3 *
4 * Copyright 2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#ifndef CORENET_DS_H
13#define CORENET_DS_H
14
15extern void __init corenet_ds_pic_init(void);
16extern void __init corenet_ds_setup_arch(void);
17extern int __init corenet_ds_publish_devices(void);
18
19#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
new file mode 100644
index 000000000000..fbd871e69754
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -0,0 +1,182 @@
1/*
2 * Corenet based SoC DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2011 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <asm/ppc-pci.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28#include <asm/ehv_pic.h>
29
30#include <linux/of_platform.h>
31#include <sysdev/fsl_soc.h>
32#include <sysdev/fsl_pci.h>
33#include "smp.h"
34
35void __init corenet_gen_pic_init(void)
36{
37 struct mpic *mpic;
38 unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
39 MPIC_NO_RESET;
40
41 if (ppc_md.get_irq == mpic_get_coreint_irq)
42 flags |= MPIC_ENABLE_COREINT;
43
44 mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
45 BUG_ON(mpic == NULL);
46
47 mpic_init(mpic);
48}
49
50/*
51 * Setup the architecture
52 */
53void __init corenet_gen_setup_arch(void)
54{
55 mpc85xx_smp_init();
56
57 swiotlb_detect_4g();
58
59 pr_info("%s board from Freescale Semiconductor\n", ppc_md.name);
60}
61
62static const struct of_device_id of_device_ids[] = {
63 {
64 .compatible = "simple-bus"
65 },
66 {
67 .compatible = "fsl,srio",
68 },
69 {
70 .compatible = "fsl,p4080-pcie",
71 },
72 {
73 .compatible = "fsl,qoriq-pcie-v2.2",
74 },
75 {
76 .compatible = "fsl,qoriq-pcie-v2.3",
77 },
78 {
79 .compatible = "fsl,qoriq-pcie-v2.4",
80 },
81 {
82 .compatible = "fsl,qoriq-pcie-v3.0",
83 },
84 /* The following two are for the Freescale hypervisor */
85 {
86 .name = "hypervisor",
87 },
88 {
89 .name = "handles",
90 },
91 {}
92};
93
94int __init corenet_gen_publish_devices(void)
95{
96 return of_platform_bus_probe(NULL, of_device_ids, NULL);
97}
98
99static const char * const boards[] __initconst = {
100 "fsl,P2041RDB",
101 "fsl,P3041DS",
102 "fsl,P4080DS",
103 "fsl,P5020DS",
104 "fsl,P5040DS",
105 "fsl,T4240QDS",
106 "fsl,B4860QDS",
107 "fsl,B4420QDS",
108 "fsl,B4220QDS",
109 NULL
110};
111
112static const char * const hv_boards[] __initconst = {
113 "fsl,P2041RDB-hv",
114 "fsl,P3041DS-hv",
115 "fsl,P4080DS-hv",
116 "fsl,P5020DS-hv",
117 "fsl,P5040DS-hv",
118 "fsl,T4240QDS-hv",
119 "fsl,B4860QDS-hv",
120 "fsl,B4420QDS-hv",
121 "fsl,B4220QDS-hv",
122 NULL
123};
124
125/*
126 * Called very early, device-tree isn't unflattened
127 */
128static int __init corenet_generic_probe(void)
129{
130 unsigned long root = of_get_flat_dt_root();
131#ifdef CONFIG_SMP
132 extern struct smp_ops_t smp_85xx_ops;
133#endif
134
135 if (of_flat_dt_match(root, boards))
136 return 1;
137
138 /* Check if we're running under the Freescale hypervisor */
139 if (of_flat_dt_match(root, hv_boards)) {
140 ppc_md.init_IRQ = ehv_pic_init;
141 ppc_md.get_irq = ehv_pic_get_irq;
142 ppc_md.restart = fsl_hv_restart;
143 ppc_md.power_off = fsl_hv_halt;
144 ppc_md.halt = fsl_hv_halt;
145#ifdef CONFIG_SMP
146 /*
147 * Disable the timebase sync operations because we can't write
148 * to the timebase registers under the hypervisor.
149 */
150 smp_85xx_ops.give_timebase = NULL;
151 smp_85xx_ops.take_timebase = NULL;
152#endif
153 return 1;
154 }
155
156 return 0;
157}
158
159define_machine(corenet_generic) {
160 .name = "CoreNet Generic",
161 .probe = corenet_generic_probe,
162 .setup_arch = corenet_gen_setup_arch,
163 .init_IRQ = corenet_gen_pic_init,
164#ifdef CONFIG_PCI
165 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
166#endif
167 .get_irq = mpic_get_coreint_irq,
168 .restart = fsl_rstcr_restart,
169 .calibrate_decr = generic_calibrate_decr,
170 .progress = udbg_progress,
171#ifdef CONFIG_PPC64
172 .power_save = book3e_idle,
173#else
174 .power_save = e500_idle,
175#endif
176};
177
178machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
179
180#ifdef CONFIG_SWIOTLB
181machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
182#endif
diff --git a/arch/powerpc/platforms/85xx/p1010rdb.c b/arch/powerpc/platforms/85xx/p1010rdb.c
index 0252961392d5..d6a3dd311494 100644
--- a/arch/powerpc/platforms/85xx/p1010rdb.c
+++ b/arch/powerpc/platforms/85xx/p1010rdb.c
@@ -66,6 +66,8 @@ static int __init p1010_rdb_probe(void)
66 66
67 if (of_flat_dt_is_compatible(root, "fsl,P1010RDB")) 67 if (of_flat_dt_is_compatible(root, "fsl,P1010RDB"))
68 return 1; 68 return 1;
69 if (of_flat_dt_is_compatible(root, "fsl,P1010RDB-PB"))
70 return 1;
69 return 0; 71 return 0;
70} 72}
71 73
diff --git a/arch/powerpc/platforms/85xx/p2041_rdb.c b/arch/powerpc/platforms/85xx/p2041_rdb.c
deleted file mode 100644
index 000c0892fc40..000000000000
--- a/arch/powerpc/platforms/85xx/p2041_rdb.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * P2041 RDB Setup
3 *
4 * Copyright 2011 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/kdev_t.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/phy.h>
18
19#include <asm/time.h>
20#include <asm/machdep.h>
21#include <asm/pci-bridge.h>
22#include <mm/mmu_decl.h>
23#include <asm/prom.h>
24#include <asm/udbg.h>
25#include <asm/mpic.h>
26
27#include <linux/of_platform.h>
28#include <sysdev/fsl_soc.h>
29#include <sysdev/fsl_pci.h>
30#include <asm/ehv_pic.h>
31
32#include "corenet_ds.h"
33
34/*
35 * Called very early, device-tree isn't unflattened
36 */
37static int __init p2041_rdb_probe(void)
38{
39 unsigned long root = of_get_flat_dt_root();
40#ifdef CONFIG_SMP
41 extern struct smp_ops_t smp_85xx_ops;
42#endif
43
44 if (of_flat_dt_is_compatible(root, "fsl,P2041RDB"))
45 return 1;
46
47 /* Check if we're running under the Freescale hypervisor */
48 if (of_flat_dt_is_compatible(root, "fsl,P2041RDB-hv")) {
49 ppc_md.init_IRQ = ehv_pic_init;
50 ppc_md.get_irq = ehv_pic_get_irq;
51 ppc_md.restart = fsl_hv_restart;
52 ppc_md.power_off = fsl_hv_halt;
53 ppc_md.halt = fsl_hv_halt;
54#ifdef CONFIG_SMP
55 /*
56 * Disable the timebase sync operations because we can't write
57 * to the timebase registers under the hypervisor.
58 */
59 smp_85xx_ops.give_timebase = NULL;
60 smp_85xx_ops.take_timebase = NULL;
61#endif
62 return 1;
63 }
64
65 return 0;
66}
67
68define_machine(p2041_rdb) {
69 .name = "P2041 RDB",
70 .probe = p2041_rdb_probe,
71 .setup_arch = corenet_ds_setup_arch,
72 .init_IRQ = corenet_ds_pic_init,
73#ifdef CONFIG_PCI
74 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
75#endif
76 .get_irq = mpic_get_coreint_irq,
77 .restart = fsl_rstcr_restart,
78 .calibrate_decr = generic_calibrate_decr,
79 .progress = udbg_progress,
80 .power_save = e500_idle,
81};
82
83machine_arch_initcall(p2041_rdb, corenet_ds_publish_devices);
84
85#ifdef CONFIG_SWIOTLB
86machine_arch_initcall(p2041_rdb, swiotlb_setup_bus_notifier);
87#endif
diff --git a/arch/powerpc/platforms/85xx/p3041_ds.c b/arch/powerpc/platforms/85xx/p3041_ds.c
deleted file mode 100644
index b3edc205daa9..000000000000
--- a/arch/powerpc/platforms/85xx/p3041_ds.c
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * P3041 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2010 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init p3041_ds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if (of_flat_dt_is_compatible(root, "fsl,P3041DS"))
47 return 1;
48
49 /* Check if we're running under the Freescale hypervisor */
50 if (of_flat_dt_is_compatible(root, "fsl,P3041DS-hv")) {
51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
63#endif
64 return 1;
65 }
66
67 return 0;
68}
69
70define_machine(p3041_ds) {
71 .name = "P3041 DS",
72 .probe = p3041_ds_probe,
73 .setup_arch = corenet_ds_setup_arch,
74 .init_IRQ = corenet_ds_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77#endif
78 .get_irq = mpic_get_coreint_irq,
79 .restart = fsl_rstcr_restart,
80 .calibrate_decr = generic_calibrate_decr,
81 .progress = udbg_progress,
82 .power_save = e500_idle,
83};
84
85machine_arch_initcall(p3041_ds, corenet_ds_publish_devices);
86
87#ifdef CONFIG_SWIOTLB
88machine_arch_initcall(p3041_ds, swiotlb_setup_bus_notifier);
89#endif
diff --git a/arch/powerpc/platforms/85xx/p4080_ds.c b/arch/powerpc/platforms/85xx/p4080_ds.c
deleted file mode 100644
index 54df10632aea..000000000000
--- a/arch/powerpc/platforms/85xx/p4080_ds.c
+++ /dev/null
@@ -1,87 +0,0 @@
1/*
2 * P4080 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19
20#include <asm/time.h>
21#include <asm/machdep.h>
22#include <asm/pci-bridge.h>
23#include <mm/mmu_decl.h>
24#include <asm/prom.h>
25#include <asm/udbg.h>
26#include <asm/mpic.h>
27
28#include <linux/of_platform.h>
29#include <sysdev/fsl_soc.h>
30#include <sysdev/fsl_pci.h>
31#include <asm/ehv_pic.h>
32
33#include "corenet_ds.h"
34
35/*
36 * Called very early, device-tree isn't unflattened
37 */
38static int __init p4080_ds_probe(void)
39{
40 unsigned long root = of_get_flat_dt_root();
41#ifdef CONFIG_SMP
42 extern struct smp_ops_t smp_85xx_ops;
43#endif
44
45 if (of_flat_dt_is_compatible(root, "fsl,P4080DS"))
46 return 1;
47
48 /* Check if we're running under the Freescale hypervisor */
49 if (of_flat_dt_is_compatible(root, "fsl,P4080DS-hv")) {
50 ppc_md.init_IRQ = ehv_pic_init;
51 ppc_md.get_irq = ehv_pic_get_irq;
52 ppc_md.restart = fsl_hv_restart;
53 ppc_md.power_off = fsl_hv_halt;
54 ppc_md.halt = fsl_hv_halt;
55#ifdef CONFIG_SMP
56 /*
57 * Disable the timebase sync operations because we can't write
58 * to the timebase registers under the hypervisor.
59 */
60 smp_85xx_ops.give_timebase = NULL;
61 smp_85xx_ops.take_timebase = NULL;
62#endif
63 return 1;
64 }
65
66 return 0;
67}
68
69define_machine(p4080_ds) {
70 .name = "P4080 DS",
71 .probe = p4080_ds_probe,
72 .setup_arch = corenet_ds_setup_arch,
73 .init_IRQ = corenet_ds_pic_init,
74#ifdef CONFIG_PCI
75 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
76#endif
77 .get_irq = mpic_get_coreint_irq,
78 .restart = fsl_rstcr_restart,
79 .calibrate_decr = generic_calibrate_decr,
80 .progress = udbg_progress,
81 .power_save = e500_idle,
82};
83
84machine_arch_initcall(p4080_ds, corenet_ds_publish_devices);
85#ifdef CONFIG_SWIOTLB
86machine_arch_initcall(p4080_ds, swiotlb_setup_bus_notifier);
87#endif
diff --git a/arch/powerpc/platforms/85xx/p5020_ds.c b/arch/powerpc/platforms/85xx/p5020_ds.c
deleted file mode 100644
index 39cfa4044e6c..000000000000
--- a/arch/powerpc/platforms/85xx/p5020_ds.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * P5020 DS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2009-2010 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init p5020_ds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if (of_flat_dt_is_compatible(root, "fsl,P5020DS"))
47 return 1;
48
49 /* Check if we're running under the Freescale hypervisor */
50 if (of_flat_dt_is_compatible(root, "fsl,P5020DS-hv")) {
51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
63#endif
64 return 1;
65 }
66
67 return 0;
68}
69
70define_machine(p5020_ds) {
71 .name = "P5020 DS",
72 .probe = p5020_ds_probe,
73 .setup_arch = corenet_ds_setup_arch,
74 .init_IRQ = corenet_ds_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77#endif
78 .get_irq = mpic_get_coreint_irq,
79 .restart = fsl_rstcr_restart,
80 .calibrate_decr = generic_calibrate_decr,
81 .progress = udbg_progress,
82#ifdef CONFIG_PPC64
83 .power_save = book3e_idle,
84#else
85 .power_save = e500_idle,
86#endif
87};
88
89machine_arch_initcall(p5020_ds, corenet_ds_publish_devices);
90
91#ifdef CONFIG_SWIOTLB
92machine_arch_initcall(p5020_ds, swiotlb_setup_bus_notifier);
93#endif
diff --git a/arch/powerpc/platforms/85xx/p5040_ds.c b/arch/powerpc/platforms/85xx/p5040_ds.c
deleted file mode 100644
index f70e74cddf97..000000000000
--- a/arch/powerpc/platforms/85xx/p5040_ds.c
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * P5040 DS Setup
3 *
4 * Copyright 2009-2010 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#include <linux/kernel.h>
13#include <linux/pci.h>
14
15#include <asm/machdep.h>
16#include <asm/udbg.h>
17#include <asm/mpic.h>
18
19#include <linux/of_fdt.h>
20
21#include <sysdev/fsl_soc.h>
22#include <sysdev/fsl_pci.h>
23#include <asm/ehv_pic.h>
24
25#include "corenet_ds.h"
26
27/*
28 * Called very early, device-tree isn't unflattened
29 */
30static int __init p5040_ds_probe(void)
31{
32 unsigned long root = of_get_flat_dt_root();
33#ifdef CONFIG_SMP
34 extern struct smp_ops_t smp_85xx_ops;
35#endif
36
37 if (of_flat_dt_is_compatible(root, "fsl,P5040DS"))
38 return 1;
39
40 /* Check if we're running under the Freescale hypervisor */
41 if (of_flat_dt_is_compatible(root, "fsl,P5040DS-hv")) {
42 ppc_md.init_IRQ = ehv_pic_init;
43 ppc_md.get_irq = ehv_pic_get_irq;
44 ppc_md.restart = fsl_hv_restart;
45 ppc_md.power_off = fsl_hv_halt;
46 ppc_md.halt = fsl_hv_halt;
47#ifdef CONFIG_SMP
48 /*
49 * Disable the timebase sync operations because we can't write
50 * to the timebase registers under the hypervisor.
51 */
52 smp_85xx_ops.give_timebase = NULL;
53 smp_85xx_ops.take_timebase = NULL;
54#endif
55 return 1;
56 }
57
58 return 0;
59}
60
61define_machine(p5040_ds) {
62 .name = "P5040 DS",
63 .probe = p5040_ds_probe,
64 .setup_arch = corenet_ds_setup_arch,
65 .init_IRQ = corenet_ds_pic_init,
66#ifdef CONFIG_PCI
67 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
68#endif
69 .get_irq = mpic_get_coreint_irq,
70 .restart = fsl_rstcr_restart,
71 .calibrate_decr = generic_calibrate_decr,
72 .progress = udbg_progress,
73#ifdef CONFIG_PPC64
74 .power_save = book3e_idle,
75#else
76 .power_save = e500_idle,
77#endif
78};
79
80machine_arch_initcall(p5040_ds, corenet_ds_publish_devices);
81
82#ifdef CONFIG_SWIOTLB
83machine_arch_initcall(p5040_ds, swiotlb_setup_bus_notifier);
84#endif
diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c
deleted file mode 100644
index 91ead6b1b8af..000000000000
--- a/arch/powerpc/platforms/85xx/t4240_qds.c
+++ /dev/null
@@ -1,93 +0,0 @@
1/*
2 * T4240 QDS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init t4240_qds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
47 return 1;
48
49 /* Check if we're running under the Freescale hypervisor */
50 if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) {
51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
63#endif
64 return 1;
65 }
66
67 return 0;
68}
69
70define_machine(t4240_qds) {
71 .name = "T4240 QDS",
72 .probe = t4240_qds_probe,
73 .setup_arch = corenet_ds_setup_arch,
74 .init_IRQ = corenet_ds_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77#endif
78 .get_irq = mpic_get_coreint_irq,
79 .restart = fsl_rstcr_restart,
80 .calibrate_decr = generic_calibrate_decr,
81 .progress = udbg_progress,
82#ifdef CONFIG_PPC64
83 .power_save = book3e_idle,
84#else
85 .power_save = e500_idle,
86#endif
87};
88
89machine_arch_initcall(t4240_qds, corenet_ds_publish_devices);
90
91#ifdef CONFIG_SWIOTLB
92machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier);
93#endif
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index 3006b5117ec6..6f61e21b3617 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -181,6 +181,7 @@ struct irq_domain *hlwd_pic_init(struct device_node *np)
181 &hlwd_irq_domain_ops, io_base); 181 &hlwd_irq_domain_ops, io_base);
182 if (!irq_domain) { 182 if (!irq_domain) {
183 pr_err("failed to allocate irq_domain\n"); 183 pr_err("failed to allocate irq_domain\n");
184 iounmap(io_base);
184 return NULL; 185 return NULL;
185 } 186 }
186 187
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index ccfb50ddfe38..21039634d1d0 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -40,7 +40,7 @@
40 40
41static int fsl_pcie_bus_fixup, is_mpc83xx_pci; 41static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
42 42
43static void quirk_fsl_pcie_header(struct pci_dev *dev) 43static void quirk_fsl_pcie_early(struct pci_dev *dev)
44{ 44{
45 u8 hdr_type; 45 u8 hdr_type;
46 46
@@ -562,7 +562,8 @@ no_bridge:
562} 562}
563#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */ 563#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
564 564
565DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header); 565DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
566 quirk_fsl_pcie_early);
566 567
567#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x) 568#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
568struct mpc83xx_pcie_priv { 569struct mpc83xx_pcie_priv {
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index 4a25c26f0bf4..a3a8fad8537d 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -228,7 +228,7 @@ static struct platform_device * __init mv64x60_eth_register_shared_pdev(
228 228
229 if (id == 0) { 229 if (id == 0) {
230 pdev = platform_device_register_simple("orion-mdio", -1, &r[1], 1); 230 pdev = platform_device_register_simple("orion-mdio", -1, &r[1], 1);
231 if (!pdev) 231 if (IS_ERR(pdev))
232 return pdev; 232 return pdev;
233 } 233 }
234 234
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-06 20:38:36 -0400