diff options
author | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 05:57:43 -0400 |
---|---|---|
committer | Kukjin Kim <kgene.kim@samsung.com> | 2011-10-04 05:57:43 -0400 |
commit | 22be71ea8bf7e9f907e916bf9f6c2bbea9f42553 (patch) | |
tree | edf517ccf09aec82c6a30e69ef885a785fa77167 /arch | |
parent | 59ca37f74a6e9d3e9367359f2fcbb286df7d9748 (diff) | |
parent | b391f8cf606679e97b02e3b9dca8a1d9956a5301 (diff) |
Merge branch 'next/topic-gpio-samsung' into next-samsung-devel
Diffstat (limited to 'arch')
41 files changed, 251 insertions, 2164 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3146ed3f6eca..bea81d018312 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -724,9 +724,6 @@ config ARCH_S3C64XX | |||
724 | select SAMSUNG_IRQ_VIC_TIMER | 724 | select SAMSUNG_IRQ_VIC_TIMER |
725 | select SAMSUNG_IRQ_UART | 725 | select SAMSUNG_IRQ_UART |
726 | select S3C_GPIO_TRACK | 726 | select S3C_GPIO_TRACK |
727 | select S3C_GPIO_PULL_UPDOWN | ||
728 | select S3C_GPIO_CFG_S3C24XX | ||
729 | select S3C_GPIO_CFG_S3C64XX | ||
730 | select S3C_DEV_NAND | 727 | select S3C_DEV_NAND |
731 | select USB_ARCH_HAS_OHCI | 728 | select USB_ARCH_HAS_OHCI |
732 | select SAMSUNG_GPIOLIB_4BIT | 729 | select SAMSUNG_GPIOLIB_4BIT |
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h index 1df3b81f96e8..3499ec737206 100644 --- a/arch/arm/mach-exynos4/include/mach/pm-core.h +++ b/arch/arm/mach-exynos4/include/mach/pm-core.h | |||
@@ -53,7 +53,7 @@ static inline void s3c_pm_restored_gpios(void) | |||
53 | /* nothing here yet */ | 53 | /* nothing here yet */ |
54 | } | 54 | } |
55 | 55 | ||
56 | static inline void s3c_pm_saved_gpios(void) | 56 | static inline void samsung_pm_saved_gpios(void) |
57 | { | 57 | { |
58 | /* nothing here yet */ | 58 | /* nothing here yet */ |
59 | } | 59 | } |
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig index 7245a55795dc..5261a7ed0999 100644 --- a/arch/arm/mach-s3c2410/Kconfig +++ b/arch/arm/mach-s3c2410/Kconfig | |||
@@ -6,9 +6,7 @@ config CPU_S3C2410 | |||
6 | bool | 6 | bool |
7 | depends on ARCH_S3C2410 | 7 | depends on ARCH_S3C2410 |
8 | select CPU_ARM920T | 8 | select CPU_ARM920T |
9 | select S3C_GPIO_PULL_UP | ||
10 | select S3C2410_CLOCK | 9 | select S3C2410_CLOCK |
11 | select S3C2410_GPIO | ||
12 | select CPU_LLSERIAL_S3C2410 | 10 | select CPU_LLSERIAL_S3C2410 |
13 | select S3C2410_PM if PM | 11 | select S3C2410_PM if PM |
14 | select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX | 12 | select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX |
@@ -28,11 +26,6 @@ config S3C2410_PM | |||
28 | help | 26 | help |
29 | Power Management code common to S3C2410 and better | 27 | Power Management code common to S3C2410 and better |
30 | 28 | ||
31 | config S3C2410_GPIO | ||
32 | bool | ||
33 | help | ||
34 | GPIO code for S3C2410 and similar processors | ||
35 | |||
36 | config SIMTEC_NOR | 29 | config SIMTEC_NOR |
37 | bool | 30 | bool |
38 | help | 31 | help |
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile index 81695353d8f4..782fd81144e9 100644 --- a/arch/arm/mach-s3c2410/Makefile +++ b/arch/arm/mach-s3c2410/Makefile | |||
@@ -13,7 +13,6 @@ obj-$(CONFIG_CPU_S3C2410) += s3c2410.o | |||
13 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o | 13 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o |
14 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o | 14 | obj-$(CONFIG_CPU_S3C2410_DMA) += dma.o |
15 | obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o | 15 | obj-$(CONFIG_S3C2410_PM) += pm.o sleep.o |
16 | obj-$(CONFIG_S3C2410_GPIO) += gpio.o | ||
17 | obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o | 16 | obj-$(CONFIG_S3C2410_CPUFREQ) += cpu-freq.o |
18 | obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o | 17 | obj-$(CONFIG_S3C2410_PLLTABLE) += pll.o |
19 | 18 | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h index bab139201761..c53ad34c6579 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h | |||
@@ -1,98 +1 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/gpio-fns.h | #include <plat/gpio-fns.h> | |
2 | * | ||
3 | * Copyright (c) 2003-2009 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - hardware | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __MACH_GPIO_FNS_H | ||
14 | #define __MACH_GPIO_FNS_H __FILE__ | ||
15 | |||
16 | /* These functions are in the to-be-removed category and it is strongly | ||
17 | * encouraged not to use these in new code. They will be marked deprecated | ||
18 | * very soon. | ||
19 | * | ||
20 | * Most of the functionality can be either replaced by the gpiocfg calls | ||
21 | * for the s3c platform or by the generic GPIOlib API. | ||
22 | * | ||
23 | * As of 2.6.35-rc, these will be removed, with the few drivers using them | ||
24 | * either replaced or given a wrapper until the calls can be removed. | ||
25 | */ | ||
26 | |||
27 | #include <plat/gpio-cfg.h> | ||
28 | |||
29 | static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg) | ||
30 | { | ||
31 | /* 1:1 mapping between cfgpin and setcfg calls at the moment */ | ||
32 | s3c_gpio_cfgpin(pin, cfg); | ||
33 | } | ||
34 | |||
35 | /* external functions for GPIO support | ||
36 | * | ||
37 | * These allow various different clients to access the same GPIO | ||
38 | * registers without conflicting. If your driver only owns the entire | ||
39 | * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. | ||
40 | */ | ||
41 | |||
42 | extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); | ||
43 | |||
44 | /* s3c2410_gpio_getirq | ||
45 | * | ||
46 | * turn the given pin number into the corresponding IRQ number | ||
47 | * | ||
48 | * returns: | ||
49 | * < 0 = no interrupt for this pin | ||
50 | * >=0 = interrupt number for the pin | ||
51 | */ | ||
52 | |||
53 | extern int s3c2410_gpio_getirq(unsigned int pin); | ||
54 | |||
55 | /* s3c2410_gpio_irqfilter | ||
56 | * | ||
57 | * set the irq filtering on the given pin | ||
58 | * | ||
59 | * on = 0 => disable filtering | ||
60 | * 1 => enable filtering | ||
61 | * | ||
62 | * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with | ||
63 | * width of filter (0 through 63) | ||
64 | * | ||
65 | * | ||
66 | */ | ||
67 | |||
68 | extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, | ||
69 | unsigned int config); | ||
70 | |||
71 | /* s3c2410_gpio_pullup | ||
72 | * | ||
73 | * This call should be replaced with s3c_gpio_setpull(). | ||
74 | * | ||
75 | * As a note, there is currently no distinction between pull-up and pull-down | ||
76 | * in the s3c24xx series devices with only an on/off configuration. | ||
77 | */ | ||
78 | |||
79 | /* s3c2410_gpio_pullup | ||
80 | * | ||
81 | * configure the pull-up control on the given pin | ||
82 | * | ||
83 | * to = 1 => disable the pull-up | ||
84 | * 0 => enable the pull-up | ||
85 | * | ||
86 | * eg; | ||
87 | * | ||
88 | * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); | ||
89 | * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); | ||
90 | */ | ||
91 | |||
92 | extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); | ||
93 | |||
94 | extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); | ||
95 | |||
96 | extern unsigned int s3c2410_gpio_getpin(unsigned int pin); | ||
97 | |||
98 | #endif /* __MACH_GPIO_FNS_H */ | ||
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-track.h b/arch/arm/mach-s3c2410/include/mach/gpio-track.h index d67819dde42a..c410a078622c 100644 --- a/arch/arm/mach-s3c2410/include/mach/gpio-track.h +++ b/arch/arm/mach-s3c2410/include/mach/gpio-track.h | |||
@@ -17,11 +17,11 @@ | |||
17 | 17 | ||
18 | #include <mach/regs-gpio.h> | 18 | #include <mach/regs-gpio.h> |
19 | 19 | ||
20 | extern struct s3c_gpio_chip s3c24xx_gpios[]; | 20 | extern struct samsung_gpio_chip s3c24xx_gpios[]; |
21 | 21 | ||
22 | static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) | 22 | static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int pin) |
23 | { | 23 | { |
24 | struct s3c_gpio_chip *chip; | 24 | struct samsung_gpio_chip *chip; |
25 | 25 | ||
26 | if (pin > S3C_GPIO_END) | 26 | if (pin > S3C_GPIO_END) |
27 | return NULL; | 27 | return NULL; |
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h index 45eea5210c87..2eef7e6f7675 100644 --- a/arch/arm/mach-s3c2410/include/mach/pm-core.h +++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h | |||
@@ -64,4 +64,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, | |||
64 | } | 64 | } |
65 | 65 | ||
66 | static inline void s3c_pm_restored_gpios(void) { } | 66 | static inline void s3c_pm_restored_gpios(void) { } |
67 | static inline void s3c_pm_saved_gpios(void) { } | 67 | static inline void samsung_pm_saved_gpios(void) { } |
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c index f1d3bd8f6f17..a99c2f4a523f 100644 --- a/arch/arm/mach-s3c2410/s3c2410.c +++ b/arch/arm/mach-s3c2410/s3c2410.c | |||
@@ -72,8 +72,8 @@ void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |||
72 | 72 | ||
73 | void __init s3c2410_map_io(void) | 73 | void __init s3c2410_map_io(void) |
74 | { | 74 | { |
75 | s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up; | 75 | s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; |
76 | s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up; | 76 | s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; |
77 | 77 | ||
78 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); | 78 | iotable_init(s3c2410_iodesc, ARRAY_SIZE(s3c2410_iodesc)); |
79 | } | 79 | } |
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig index c2cf4e569989..b8b9029e9f2d 100644 --- a/arch/arm/mach-s3c2412/Kconfig +++ b/arch/arm/mach-s3c2412/Kconfig | |||
@@ -9,7 +9,6 @@ config CPU_S3C2412 | |||
9 | select CPU_LLSERIAL_S3C2440 | 9 | select CPU_LLSERIAL_S3C2440 |
10 | select S3C2412_PM if PM | 10 | select S3C2412_PM if PM |
11 | select S3C2412_DMA if S3C2410_DMA | 11 | select S3C2412_DMA if S3C2410_DMA |
12 | select S3C2410_GPIO | ||
13 | help | 12 | help |
14 | Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line | 13 | Support for the S3C2412 and S3C2413 SoCs from the S3C24XX line |
15 | 14 | ||
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile index 6c48a91ea39e..7e4d95fa8a97 100644 --- a/arch/arm/mach-s3c2412/Makefile +++ b/arch/arm/mach-s3c2412/Makefile | |||
@@ -12,7 +12,6 @@ obj- := | |||
12 | obj-$(CONFIG_CPU_S3C2412) += s3c2412.o | 12 | obj-$(CONFIG_CPU_S3C2412) += s3c2412.o |
13 | obj-$(CONFIG_CPU_S3C2412) += irq.o | 13 | obj-$(CONFIG_CPU_S3C2412) += irq.o |
14 | obj-$(CONFIG_CPU_S3C2412) += clock.o | 14 | obj-$(CONFIG_CPU_S3C2412) += clock.o |
15 | obj-$(CONFIG_CPU_S3C2412) += gpio.o | ||
16 | obj-$(CONFIG_S3C2412_DMA) += dma.o | 15 | obj-$(CONFIG_S3C2412_DMA) += dma.o |
17 | obj-$(CONFIG_S3C2412_PM) += pm.o | 16 | obj-$(CONFIG_S3C2412_PM) += pm.o |
18 | obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o | 17 | obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep.o |
diff --git a/arch/arm/mach-s3c2412/gpio.c b/arch/arm/mach-s3c2412/gpio.c index 3404a876b33e..4526f6ba31a8 100644 --- a/arch/arm/mach-s3c2412/gpio.c +++ b/arch/arm/mach-s3c2412/gpio.c | |||
@@ -28,7 +28,7 @@ | |||
28 | 28 | ||
29 | int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) | 29 | int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) |
30 | { | 30 | { |
31 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | 31 | struct samsung_gpio_chip *chip = samsung_gpiolib_getchip(pin); |
32 | unsigned long offs = pin - chip->chip.base; | 32 | unsigned long offs = pin - chip->chip.base; |
33 | unsigned long flags; | 33 | unsigned long flags; |
34 | unsigned long slpcon; | 34 | unsigned long slpcon; |
diff --git a/arch/arm/mach-s3c2416/Kconfig b/arch/arm/mach-s3c2416/Kconfig index 69b48a7d1dbd..84c7b03e5a30 100644 --- a/arch/arm/mach-s3c2416/Kconfig +++ b/arch/arm/mach-s3c2416/Kconfig | |||
@@ -13,7 +13,6 @@ config CPU_S3C2416 | |||
13 | select CPU_ARM926T | 13 | select CPU_ARM926T |
14 | select S3C2416_DMA if S3C2410_DMA | 14 | select S3C2416_DMA if S3C2410_DMA |
15 | select CPU_LLSERIAL_S3C2440 | 15 | select CPU_LLSERIAL_S3C2440 |
16 | select S3C_GPIO_PULL_UPDOWN | ||
17 | select SAMSUNG_CLKSRC | 16 | select SAMSUNG_CLKSRC |
18 | select S3C2443_CLOCK | 17 | select S3C2443_CLOCK |
19 | help | 18 | help |
diff --git a/arch/arm/mach-s3c2416/s3c2416.c b/arch/arm/mach-s3c2416/s3c2416.c index 494ce913dc95..3156b7a71371 100644 --- a/arch/arm/mach-s3c2416/s3c2416.c +++ b/arch/arm/mach-s3c2416/s3c2416.c | |||
@@ -118,8 +118,8 @@ void __init s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |||
118 | 118 | ||
119 | void __init s3c2416_map_io(void) | 119 | void __init s3c2416_map_io(void) |
120 | { | 120 | { |
121 | s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_updown; | 121 | s3c24xx_gpiocfg_default.set_pull = samsung_gpio_setpull_updown; |
122 | s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_updown; | 122 | s3c24xx_gpiocfg_default.get_pull = samsung_gpio_getpull_updown; |
123 | 123 | ||
124 | /* initialize device information early */ | 124 | /* initialize device information early */ |
125 | s3c2416_default_sdhci0(); | 125 | s3c2416_default_sdhci0(); |
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig index 50825a3f91cc..914e620f1257 100644 --- a/arch/arm/mach-s3c2440/Kconfig +++ b/arch/arm/mach-s3c2440/Kconfig | |||
@@ -5,10 +5,8 @@ | |||
5 | config CPU_S3C2440 | 5 | config CPU_S3C2440 |
6 | bool | 6 | bool |
7 | select CPU_ARM920T | 7 | select CPU_ARM920T |
8 | select S3C_GPIO_PULL_UP | ||
9 | select S3C2410_CLOCK | 8 | select S3C2410_CLOCK |
10 | select S3C2410_PM if PM | 9 | select S3C2410_PM if PM |
11 | select S3C2410_GPIO | ||
12 | select S3C2440_DMA if S3C2410_DMA | 10 | select S3C2440_DMA if S3C2410_DMA |
13 | select CPU_S3C244X | 11 | select CPU_S3C244X |
14 | select CPU_LLSERIAL_S3C2440 | 12 | select CPU_LLSERIAL_S3C2440 |
@@ -18,9 +16,7 @@ config CPU_S3C2440 | |||
18 | config CPU_S3C2442 | 16 | config CPU_S3C2442 |
19 | bool | 17 | bool |
20 | select CPU_ARM920T | 18 | select CPU_ARM920T |
21 | select S3C_GPIO_PULL_DOWN | ||
22 | select S3C2410_CLOCK | 19 | select S3C2410_CLOCK |
23 | select S3C2410_GPIO | ||
24 | select S3C2410_PM if PM | 20 | select S3C2410_PM if PM |
25 | select CPU_S3C244X | 21 | select CPU_S3C244X |
26 | select CPU_LLSERIAL_S3C2440 | 22 | select CPU_LLSERIAL_S3C2440 |
diff --git a/arch/arm/mach-s3c2440/s3c2440.c b/arch/arm/mach-s3c2440/s3c2440.c index ce99ff72838d..fc84e481efcf 100644 --- a/arch/arm/mach-s3c2440/s3c2440.c +++ b/arch/arm/mach-s3c2440/s3c2440.c | |||
@@ -68,6 +68,6 @@ void __init s3c2440_map_io(void) | |||
68 | { | 68 | { |
69 | s3c244x_map_io(); | 69 | s3c244x_map_io(); |
70 | 70 | ||
71 | s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1up; | 71 | s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1up; |
72 | s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1up; | 72 | s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1up; |
73 | } | 73 | } |
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c index 9ad99f8016a1..48e273ce9f9a 100644 --- a/arch/arm/mach-s3c2440/s3c2442.c +++ b/arch/arm/mach-s3c2440/s3c2442.c | |||
@@ -180,6 +180,6 @@ void __init s3c2442_map_io(void) | |||
180 | { | 180 | { |
181 | s3c244x_map_io(); | 181 | s3c244x_map_io(); |
182 | 182 | ||
183 | s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_1down; | 183 | s3c24xx_gpiocfg_default.set_pull = s3c24xx_gpio_setpull_1down; |
184 | s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_1down; | 184 | s3c24xx_gpiocfg_default.get_pull = s3c24xx_gpio_getpull_1down; |
185 | } | 185 | } |
diff --git a/arch/arm/mach-s3c2443/Kconfig b/arch/arm/mach-s3c2443/Kconfig index d8eb86823df7..8814031516ce 100644 --- a/arch/arm/mach-s3c2443/Kconfig +++ b/arch/arm/mach-s3c2443/Kconfig | |||
@@ -10,7 +10,6 @@ config CPU_S3C2443 | |||
10 | select CPU_LLSERIAL_S3C2440 | 10 | select CPU_LLSERIAL_S3C2440 |
11 | select SAMSUNG_CLKSRC | 11 | select SAMSUNG_CLKSRC |
12 | select S3C2443_CLOCK | 12 | select S3C2443_CLOCK |
13 | select S3C_GPIO_PULL_S3C2443 | ||
14 | help | 13 | help |
15 | Support for the S3C2443 SoC from the S3C24XX line | 14 | Support for the S3C2443 SoC from the S3C24XX line |
16 | 15 | ||
diff --git a/arch/arm/mach-s3c2443/s3c2443.c b/arch/arm/mach-s3c2443/s3c2443.c index e6a28ba52c7d..5df6458ddd42 100644 --- a/arch/arm/mach-s3c2443/s3c2443.c +++ b/arch/arm/mach-s3c2443/s3c2443.c | |||
@@ -90,8 +90,8 @@ void __init s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no) | |||
90 | 90 | ||
91 | void __init s3c2443_map_io(void) | 91 | void __init s3c2443_map_io(void) |
92 | { | 92 | { |
93 | s3c24xx_gpiocfg_default.set_pull = s3c_gpio_setpull_s3c2443; | 93 | s3c24xx_gpiocfg_default.set_pull = s3c2443_gpio_setpull; |
94 | s3c24xx_gpiocfg_default.get_pull = s3c_gpio_getpull_s3c2443; | 94 | s3c24xx_gpiocfg_default.get_pull = s3c2443_gpio_getpull; |
95 | 95 | ||
96 | iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); | 96 | iotable_init(s3c2443_iodesc, ARRAY_SIZE(s3c2443_iodesc)); |
97 | } | 97 | } |
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile index 5fdea6aa50d4..902ab9ace93b 100644 --- a/arch/arm/mach-s3c64xx/Makefile +++ b/arch/arm/mach-s3c64xx/Makefile | |||
@@ -13,7 +13,6 @@ obj- := | |||
13 | # Core files | 13 | # Core files |
14 | obj-y += cpu.o | 14 | obj-y += cpu.o |
15 | obj-y += clock.o | 15 | obj-y += clock.o |
16 | obj-y += gpiolib.o | ||
17 | 16 | ||
18 | # Core support for S3C6400 system | 17 | # Core support for S3C6400 system |
19 | 18 | ||
diff --git a/arch/arm/mach-s3c64xx/gpiolib.c b/arch/arm/mach-s3c64xx/gpiolib.c deleted file mode 100644 index 92b09085caaa..000000000000 --- a/arch/arm/mach-s3c64xx/gpiolib.c +++ /dev/null | |||
@@ -1,290 +0,0 @@ | |||
1 | /* arch/arm/plat-s3c64xx/gpiolib.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C64XX - GPIOlib support | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/irq.h> | ||
17 | #include <linux/io.h> | ||
18 | #include <linux/gpio.h> | ||
19 | |||
20 | #include <mach/map.h> | ||
21 | |||
22 | #include <plat/gpio-core.h> | ||
23 | #include <plat/gpio-cfg.h> | ||
24 | #include <plat/gpio-cfg-helpers.h> | ||
25 | #include <mach/regs-gpio.h> | ||
26 | |||
27 | /* GPIO bank summary: | ||
28 | * | ||
29 | * Bank GPIOs Style SlpCon ExtInt Group | ||
30 | * A 8 4Bit Yes 1 | ||
31 | * B 7 4Bit Yes 1 | ||
32 | * C 8 4Bit Yes 2 | ||
33 | * D 5 4Bit Yes 3 | ||
34 | * E 5 4Bit Yes None | ||
35 | * F 16 2Bit Yes 4 [1] | ||
36 | * G 7 4Bit Yes 5 | ||
37 | * H 10 4Bit[2] Yes 6 | ||
38 | * I 16 2Bit Yes None | ||
39 | * J 12 2Bit Yes None | ||
40 | * K 16 4Bit[2] No None | ||
41 | * L 15 4Bit[2] No None | ||
42 | * M 6 4Bit No IRQ_EINT | ||
43 | * N 16 2Bit No IRQ_EINT | ||
44 | * O 16 2Bit Yes 7 | ||
45 | * P 15 2Bit Yes 8 | ||
46 | * Q 9 2Bit Yes 9 | ||
47 | * | ||
48 | * [1] BANKF pins 14,15 do not form part of the external interrupt sources | ||
49 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | ||
50 | */ | ||
51 | |||
52 | static struct s3c_gpio_cfg gpio_4bit_cfg_noint = { | ||
53 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
54 | .get_config = s3c_gpio_getcfg_s3c64xx_4bit, | ||
55 | .set_pull = s3c_gpio_setpull_updown, | ||
56 | .get_pull = s3c_gpio_getpull_updown, | ||
57 | }; | ||
58 | |||
59 | static struct s3c_gpio_cfg gpio_4bit_cfg_eint0111 = { | ||
60 | .cfg_eint = 7, | ||
61 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
62 | .get_config = s3c_gpio_getcfg_s3c64xx_4bit, | ||
63 | .set_pull = s3c_gpio_setpull_updown, | ||
64 | .get_pull = s3c_gpio_getpull_updown, | ||
65 | }; | ||
66 | |||
67 | static struct s3c_gpio_cfg gpio_4bit_cfg_eint0011 = { | ||
68 | .cfg_eint = 3, | ||
69 | .get_config = s3c_gpio_getcfg_s3c64xx_4bit, | ||
70 | .set_config = s3c_gpio_setcfg_s3c64xx_4bit, | ||
71 | .set_pull = s3c_gpio_setpull_updown, | ||
72 | .get_pull = s3c_gpio_getpull_updown, | ||
73 | }; | ||
74 | |||
75 | static int s3c64xx_gpio2int_gpm(struct gpio_chip *chip, unsigned pin) | ||
76 | { | ||
77 | return pin < 5 ? IRQ_EINT(23) + pin : -ENXIO; | ||
78 | } | ||
79 | |||
80 | static struct s3c_gpio_chip gpio_4bit[] = { | ||
81 | { | ||
82 | .base = S3C64XX_GPA_BASE, | ||
83 | .config = &gpio_4bit_cfg_eint0111, | ||
84 | .chip = { | ||
85 | .base = S3C64XX_GPA(0), | ||
86 | .ngpio = S3C64XX_GPIO_A_NR, | ||
87 | .label = "GPA", | ||
88 | }, | ||
89 | }, { | ||
90 | .base = S3C64XX_GPB_BASE, | ||
91 | .config = &gpio_4bit_cfg_eint0111, | ||
92 | .chip = { | ||
93 | .base = S3C64XX_GPB(0), | ||
94 | .ngpio = S3C64XX_GPIO_B_NR, | ||
95 | .label = "GPB", | ||
96 | }, | ||
97 | }, { | ||
98 | .base = S3C64XX_GPC_BASE, | ||
99 | .config = &gpio_4bit_cfg_eint0111, | ||
100 | .chip = { | ||
101 | .base = S3C64XX_GPC(0), | ||
102 | .ngpio = S3C64XX_GPIO_C_NR, | ||
103 | .label = "GPC", | ||
104 | }, | ||
105 | }, { | ||
106 | .base = S3C64XX_GPD_BASE, | ||
107 | .config = &gpio_4bit_cfg_eint0111, | ||
108 | .chip = { | ||
109 | .base = S3C64XX_GPD(0), | ||
110 | .ngpio = S3C64XX_GPIO_D_NR, | ||
111 | .label = "GPD", | ||
112 | }, | ||
113 | }, { | ||
114 | .base = S3C64XX_GPE_BASE, | ||
115 | .config = &gpio_4bit_cfg_noint, | ||
116 | .chip = { | ||
117 | .base = S3C64XX_GPE(0), | ||
118 | .ngpio = S3C64XX_GPIO_E_NR, | ||
119 | .label = "GPE", | ||
120 | }, | ||
121 | }, { | ||
122 | .base = S3C64XX_GPG_BASE, | ||
123 | .config = &gpio_4bit_cfg_eint0111, | ||
124 | .chip = { | ||
125 | .base = S3C64XX_GPG(0), | ||
126 | .ngpio = S3C64XX_GPIO_G_NR, | ||
127 | .label = "GPG", | ||
128 | }, | ||
129 | }, { | ||
130 | .base = S3C64XX_GPM_BASE, | ||
131 | .config = &gpio_4bit_cfg_eint0011, | ||
132 | .chip = { | ||
133 | .base = S3C64XX_GPM(0), | ||
134 | .ngpio = S3C64XX_GPIO_M_NR, | ||
135 | .label = "GPM", | ||
136 | .to_irq = s3c64xx_gpio2int_gpm, | ||
137 | }, | ||
138 | }, | ||
139 | }; | ||
140 | |||
141 | static int s3c64xx_gpio2int_gpl(struct gpio_chip *chip, unsigned pin) | ||
142 | { | ||
143 | return pin >= 8 ? IRQ_EINT(16) + pin - 8 : -ENXIO; | ||
144 | } | ||
145 | |||
146 | static struct s3c_gpio_chip gpio_4bit2[] = { | ||
147 | { | ||
148 | .base = S3C64XX_GPH_BASE + 0x4, | ||
149 | .config = &gpio_4bit_cfg_eint0111, | ||
150 | .chip = { | ||
151 | .base = S3C64XX_GPH(0), | ||
152 | .ngpio = S3C64XX_GPIO_H_NR, | ||
153 | .label = "GPH", | ||
154 | }, | ||
155 | }, { | ||
156 | .base = S3C64XX_GPK_BASE + 0x4, | ||
157 | .config = &gpio_4bit_cfg_noint, | ||
158 | .chip = { | ||
159 | .base = S3C64XX_GPK(0), | ||
160 | .ngpio = S3C64XX_GPIO_K_NR, | ||
161 | .label = "GPK", | ||
162 | }, | ||
163 | }, { | ||
164 | .base = S3C64XX_GPL_BASE + 0x4, | ||
165 | .config = &gpio_4bit_cfg_eint0011, | ||
166 | .chip = { | ||
167 | .base = S3C64XX_GPL(0), | ||
168 | .ngpio = S3C64XX_GPIO_L_NR, | ||
169 | .label = "GPL", | ||
170 | .to_irq = s3c64xx_gpio2int_gpl, | ||
171 | }, | ||
172 | }, | ||
173 | }; | ||
174 | |||
175 | static struct s3c_gpio_cfg gpio_2bit_cfg_noint = { | ||
176 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
177 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
178 | .set_pull = s3c_gpio_setpull_updown, | ||
179 | .get_pull = s3c_gpio_getpull_updown, | ||
180 | }; | ||
181 | |||
182 | static struct s3c_gpio_cfg gpio_2bit_cfg_eint10 = { | ||
183 | .cfg_eint = 2, | ||
184 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
185 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
186 | .set_pull = s3c_gpio_setpull_updown, | ||
187 | .get_pull = s3c_gpio_getpull_updown, | ||
188 | }; | ||
189 | |||
190 | static struct s3c_gpio_cfg gpio_2bit_cfg_eint11 = { | ||
191 | .cfg_eint = 3, | ||
192 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
193 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
194 | .set_pull = s3c_gpio_setpull_updown, | ||
195 | .get_pull = s3c_gpio_getpull_updown, | ||
196 | }; | ||
197 | |||
198 | static struct s3c_gpio_chip gpio_2bit[] = { | ||
199 | { | ||
200 | .base = S3C64XX_GPF_BASE, | ||
201 | .config = &gpio_2bit_cfg_eint11, | ||
202 | .chip = { | ||
203 | .base = S3C64XX_GPF(0), | ||
204 | .ngpio = S3C64XX_GPIO_F_NR, | ||
205 | .label = "GPF", | ||
206 | }, | ||
207 | }, { | ||
208 | .base = S3C64XX_GPI_BASE, | ||
209 | .config = &gpio_2bit_cfg_noint, | ||
210 | .chip = { | ||
211 | .base = S3C64XX_GPI(0), | ||
212 | .ngpio = S3C64XX_GPIO_I_NR, | ||
213 | .label = "GPI", | ||
214 | }, | ||
215 | }, { | ||
216 | .base = S3C64XX_GPJ_BASE, | ||
217 | .config = &gpio_2bit_cfg_noint, | ||
218 | .chip = { | ||
219 | .base = S3C64XX_GPJ(0), | ||
220 | .ngpio = S3C64XX_GPIO_J_NR, | ||
221 | .label = "GPJ", | ||
222 | }, | ||
223 | }, { | ||
224 | .base = S3C64XX_GPN_BASE, | ||
225 | .irq_base = IRQ_EINT(0), | ||
226 | .config = &gpio_2bit_cfg_eint10, | ||
227 | .chip = { | ||
228 | .base = S3C64XX_GPN(0), | ||
229 | .ngpio = S3C64XX_GPIO_N_NR, | ||
230 | .label = "GPN", | ||
231 | .to_irq = samsung_gpiolib_to_irq, | ||
232 | }, | ||
233 | }, { | ||
234 | .base = S3C64XX_GPO_BASE, | ||
235 | .config = &gpio_2bit_cfg_eint11, | ||
236 | .chip = { | ||
237 | .base = S3C64XX_GPO(0), | ||
238 | .ngpio = S3C64XX_GPIO_O_NR, | ||
239 | .label = "GPO", | ||
240 | }, | ||
241 | }, { | ||
242 | .base = S3C64XX_GPP_BASE, | ||
243 | .config = &gpio_2bit_cfg_eint11, | ||
244 | .chip = { | ||
245 | .base = S3C64XX_GPP(0), | ||
246 | .ngpio = S3C64XX_GPIO_P_NR, | ||
247 | .label = "GPP", | ||
248 | }, | ||
249 | }, { | ||
250 | .base = S3C64XX_GPQ_BASE, | ||
251 | .config = &gpio_2bit_cfg_eint11, | ||
252 | .chip = { | ||
253 | .base = S3C64XX_GPQ(0), | ||
254 | .ngpio = S3C64XX_GPIO_Q_NR, | ||
255 | .label = "GPQ", | ||
256 | }, | ||
257 | }, | ||
258 | }; | ||
259 | |||
260 | static __init void s3c64xx_gpiolib_add_2bit(struct s3c_gpio_chip *chip) | ||
261 | { | ||
262 | chip->pm = __gpio_pm(&s3c_gpio_pm_2bit); | ||
263 | } | ||
264 | |||
265 | static __init void s3c64xx_gpiolib_add(struct s3c_gpio_chip *chips, | ||
266 | int nr_chips, | ||
267 | void (*fn)(struct s3c_gpio_chip *)) | ||
268 | { | ||
269 | for (; nr_chips > 0; nr_chips--, chips++) { | ||
270 | if (fn) | ||
271 | (fn)(chips); | ||
272 | s3c_gpiolib_add(chips); | ||
273 | } | ||
274 | } | ||
275 | |||
276 | static __init int s3c64xx_gpiolib_init(void) | ||
277 | { | ||
278 | s3c64xx_gpiolib_add(gpio_4bit, ARRAY_SIZE(gpio_4bit), | ||
279 | samsung_gpiolib_add_4bit); | ||
280 | |||
281 | s3c64xx_gpiolib_add(gpio_4bit2, ARRAY_SIZE(gpio_4bit2), | ||
282 | samsung_gpiolib_add_4bit2); | ||
283 | |||
284 | s3c64xx_gpiolib_add(gpio_2bit, ARRAY_SIZE(gpio_2bit), | ||
285 | s3c64xx_gpiolib_add_2bit); | ||
286 | |||
287 | return 0; | ||
288 | } | ||
289 | |||
290 | core_initcall(s3c64xx_gpiolib_init); | ||
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h index 38659bebe4b1..fcf3dcabb694 100644 --- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h +++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h | |||
@@ -104,7 +104,7 @@ static inline void s3c_pm_restored_gpios(void) | |||
104 | __raw_writel(0, S3C64XX_SLPEN); | 104 | __raw_writel(0, S3C64XX_SLPEN); |
105 | } | 105 | } |
106 | 106 | ||
107 | static inline void s3c_pm_saved_gpios(void) | 107 | static inline void samsung_pm_saved_gpios(void) |
108 | { | 108 | { |
109 | /* turn on the sleep mode and keep it there, as it seems that during | 109 | /* turn on the sleep mode and keep it there, as it seems that during |
110 | * suspend the xCON registers get re-set and thus you can end up with | 110 | * suspend the xCON registers get re-set and thus you can end up with |
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile index 5f6afdf067ed..5b9495538839 100644 --- a/arch/arm/mach-s5p64x0/Makefile +++ b/arch/arm/mach-s5p64x0/Makefile | |||
@@ -12,7 +12,7 @@ obj- := | |||
12 | 12 | ||
13 | # Core support for S5P64X0 system | 13 | # Core support for S5P64X0 system |
14 | 14 | ||
15 | obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o | 15 | obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o |
16 | obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o | 16 | obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o |
17 | obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o | 17 | obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o |
18 | obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o | 18 | obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o |
diff --git a/arch/arm/mach-s5p64x0/gpiolib.c b/arch/arm/mach-s5p64x0/gpiolib.c deleted file mode 100644 index e7fb3b004e77..000000000000 --- a/arch/arm/mach-s5p64x0/gpiolib.c +++ /dev/null | |||
@@ -1,511 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/gpiolib.c | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - GPIOlib support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/irq.h> | ||
15 | #include <linux/io.h> | ||
16 | #include <linux/gpio.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <mach/regs-gpio.h> | ||
20 | #include <mach/regs-clock.h> | ||
21 | |||
22 | #include <plat/gpio-core.h> | ||
23 | #include <plat/gpio-cfg.h> | ||
24 | #include <plat/gpio-cfg-helpers.h> | ||
25 | |||
26 | /* | ||
27 | * S5P6440 GPIO bank summary: | ||
28 | * | ||
29 | * Bank GPIOs Style SlpCon ExtInt Group | ||
30 | * A 6 4Bit Yes 1 | ||
31 | * B 7 4Bit Yes 1 | ||
32 | * C 8 4Bit Yes 2 | ||
33 | * F 2 2Bit Yes 4 [1] | ||
34 | * G 7 4Bit Yes 5 | ||
35 | * H 10 4Bit[2] Yes 6 | ||
36 | * I 16 2Bit Yes None | ||
37 | * J 12 2Bit Yes None | ||
38 | * N 16 2Bit No IRQ_EINT | ||
39 | * P 8 2Bit Yes 8 | ||
40 | * R 15 4Bit[2] Yes 8 | ||
41 | * | ||
42 | * S5P6450 GPIO bank summary: | ||
43 | * | ||
44 | * Bank GPIOs Style SlpCon ExtInt Group | ||
45 | * A 6 4Bit Yes 1 | ||
46 | * B 7 4Bit Yes 1 | ||
47 | * C 8 4Bit Yes 2 | ||
48 | * D 8 4Bit Yes None | ||
49 | * F 2 2Bit Yes None | ||
50 | * G 14 4Bit[2] Yes 5 | ||
51 | * H 10 4Bit[2] Yes 6 | ||
52 | * I 16 2Bit Yes None | ||
53 | * J 12 2Bit Yes None | ||
54 | * K 5 4Bit Yes None | ||
55 | * N 16 2Bit No IRQ_EINT | ||
56 | * P 11 2Bit Yes 8 | ||
57 | * Q 14 2Bit Yes None | ||
58 | * R 15 4Bit[2] Yes None | ||
59 | * S 8 2Bit Yes None | ||
60 | * | ||
61 | * [1] BANKF pins 14,15 do not form part of the external interrupt sources | ||
62 | * [2] BANK has two control registers, GPxCON0 and GPxCON1 | ||
63 | */ | ||
64 | |||
65 | static int s5p64x0_gpiolib_rbank_4bit2_input(struct gpio_chip *chip, | ||
66 | unsigned int offset) | ||
67 | { | ||
68 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
69 | void __iomem *base = ourchip->base; | ||
70 | void __iomem *regcon = base; | ||
71 | unsigned long con; | ||
72 | unsigned long flags; | ||
73 | |||
74 | switch (offset) { | ||
75 | case 6: | ||
76 | offset += 1; | ||
77 | case 0: | ||
78 | case 1: | ||
79 | case 2: | ||
80 | case 3: | ||
81 | case 4: | ||
82 | case 5: | ||
83 | regcon -= 4; | ||
84 | break; | ||
85 | default: | ||
86 | offset -= 7; | ||
87 | break; | ||
88 | } | ||
89 | |||
90 | s3c_gpio_lock(ourchip, flags); | ||
91 | |||
92 | con = __raw_readl(regcon); | ||
93 | con &= ~(0xf << con_4bit_shift(offset)); | ||
94 | __raw_writel(con, regcon); | ||
95 | |||
96 | s3c_gpio_unlock(ourchip, flags); | ||
97 | |||
98 | return 0; | ||
99 | } | ||
100 | |||
101 | static int s5p64x0_gpiolib_rbank_4bit2_output(struct gpio_chip *chip, | ||
102 | unsigned int offset, int value) | ||
103 | { | ||
104 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
105 | void __iomem *base = ourchip->base; | ||
106 | void __iomem *regcon = base; | ||
107 | unsigned long con; | ||
108 | unsigned long dat; | ||
109 | unsigned long flags; | ||
110 | unsigned con_offset = offset; | ||
111 | |||
112 | switch (con_offset) { | ||
113 | case 6: | ||
114 | con_offset += 1; | ||
115 | case 0: | ||
116 | case 1: | ||
117 | case 2: | ||
118 | case 3: | ||
119 | case 4: | ||
120 | case 5: | ||
121 | regcon -= 4; | ||
122 | break; | ||
123 | default: | ||
124 | con_offset -= 7; | ||
125 | break; | ||
126 | } | ||
127 | |||
128 | s3c_gpio_lock(ourchip, flags); | ||
129 | |||
130 | con = __raw_readl(regcon); | ||
131 | con &= ~(0xf << con_4bit_shift(con_offset)); | ||
132 | con |= 0x1 << con_4bit_shift(con_offset); | ||
133 | |||
134 | dat = __raw_readl(base + GPIODAT_OFF); | ||
135 | if (value) | ||
136 | dat |= 1 << offset; | ||
137 | else | ||
138 | dat &= ~(1 << offset); | ||
139 | |||
140 | __raw_writel(con, regcon); | ||
141 | __raw_writel(dat, base + GPIODAT_OFF); | ||
142 | |||
143 | s3c_gpio_unlock(ourchip, flags); | ||
144 | |||
145 | return 0; | ||
146 | } | ||
147 | |||
148 | int s5p64x0_gpio_setcfg_4bit_rbank(struct s3c_gpio_chip *chip, | ||
149 | unsigned int off, unsigned int cfg) | ||
150 | { | ||
151 | void __iomem *reg = chip->base; | ||
152 | unsigned int shift; | ||
153 | u32 con; | ||
154 | |||
155 | switch (off) { | ||
156 | case 0: | ||
157 | case 1: | ||
158 | case 2: | ||
159 | case 3: | ||
160 | case 4: | ||
161 | case 5: | ||
162 | shift = (off & 7) * 4; | ||
163 | reg -= 4; | ||
164 | break; | ||
165 | case 6: | ||
166 | shift = ((off + 1) & 7) * 4; | ||
167 | reg -= 4; | ||
168 | default: | ||
169 | shift = ((off + 1) & 7) * 4; | ||
170 | break; | ||
171 | } | ||
172 | |||
173 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
174 | cfg &= 0xf; | ||
175 | cfg <<= shift; | ||
176 | } | ||
177 | |||
178 | con = __raw_readl(reg); | ||
179 | con &= ~(0xf << shift); | ||
180 | con |= cfg; | ||
181 | __raw_writel(con, reg); | ||
182 | |||
183 | return 0; | ||
184 | } | ||
185 | |||
186 | static struct s3c_gpio_cfg s5p64x0_gpio_cfgs[] = { | ||
187 | { | ||
188 | .cfg_eint = 0, | ||
189 | }, { | ||
190 | .cfg_eint = 7, | ||
191 | }, { | ||
192 | .cfg_eint = 3, | ||
193 | .set_config = s5p64x0_gpio_setcfg_4bit_rbank, | ||
194 | }, { | ||
195 | .cfg_eint = 0, | ||
196 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
197 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
198 | }, { | ||
199 | .cfg_eint = 2, | ||
200 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
201 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
202 | }, { | ||
203 | .cfg_eint = 3, | ||
204 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
205 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
206 | }, | ||
207 | }; | ||
208 | |||
209 | static struct s3c_gpio_chip s5p6440_gpio_4bit[] = { | ||
210 | { | ||
211 | .base = S5P64X0_GPA_BASE, | ||
212 | .config = &s5p64x0_gpio_cfgs[1], | ||
213 | .chip = { | ||
214 | .base = S5P6440_GPA(0), | ||
215 | .ngpio = S5P6440_GPIO_A_NR, | ||
216 | .label = "GPA", | ||
217 | }, | ||
218 | }, { | ||
219 | .base = S5P64X0_GPB_BASE, | ||
220 | .config = &s5p64x0_gpio_cfgs[1], | ||
221 | .chip = { | ||
222 | .base = S5P6440_GPB(0), | ||
223 | .ngpio = S5P6440_GPIO_B_NR, | ||
224 | .label = "GPB", | ||
225 | }, | ||
226 | }, { | ||
227 | .base = S5P64X0_GPC_BASE, | ||
228 | .config = &s5p64x0_gpio_cfgs[1], | ||
229 | .chip = { | ||
230 | .base = S5P6440_GPC(0), | ||
231 | .ngpio = S5P6440_GPIO_C_NR, | ||
232 | .label = "GPC", | ||
233 | }, | ||
234 | }, { | ||
235 | .base = S5P64X0_GPG_BASE, | ||
236 | .config = &s5p64x0_gpio_cfgs[1], | ||
237 | .chip = { | ||
238 | .base = S5P6440_GPG(0), | ||
239 | .ngpio = S5P6440_GPIO_G_NR, | ||
240 | .label = "GPG", | ||
241 | }, | ||
242 | }, | ||
243 | }; | ||
244 | |||
245 | static struct s3c_gpio_chip s5p6440_gpio_4bit2[] = { | ||
246 | { | ||
247 | .base = S5P64X0_GPH_BASE + 0x4, | ||
248 | .config = &s5p64x0_gpio_cfgs[1], | ||
249 | .chip = { | ||
250 | .base = S5P6440_GPH(0), | ||
251 | .ngpio = S5P6440_GPIO_H_NR, | ||
252 | .label = "GPH", | ||
253 | }, | ||
254 | }, | ||
255 | }; | ||
256 | |||
257 | static struct s3c_gpio_chip s5p6440_gpio_rbank_4bit2[] = { | ||
258 | { | ||
259 | .base = S5P64X0_GPR_BASE + 0x4, | ||
260 | .config = &s5p64x0_gpio_cfgs[2], | ||
261 | .chip = { | ||
262 | .base = S5P6440_GPR(0), | ||
263 | .ngpio = S5P6440_GPIO_R_NR, | ||
264 | .label = "GPR", | ||
265 | }, | ||
266 | }, | ||
267 | }; | ||
268 | |||
269 | static struct s3c_gpio_chip s5p6440_gpio_2bit[] = { | ||
270 | { | ||
271 | .base = S5P64X0_GPF_BASE, | ||
272 | .config = &s5p64x0_gpio_cfgs[5], | ||
273 | .chip = { | ||
274 | .base = S5P6440_GPF(0), | ||
275 | .ngpio = S5P6440_GPIO_F_NR, | ||
276 | .label = "GPF", | ||
277 | }, | ||
278 | }, { | ||
279 | .base = S5P64X0_GPI_BASE, | ||
280 | .config = &s5p64x0_gpio_cfgs[3], | ||
281 | .chip = { | ||
282 | .base = S5P6440_GPI(0), | ||
283 | .ngpio = S5P6440_GPIO_I_NR, | ||
284 | .label = "GPI", | ||
285 | }, | ||
286 | }, { | ||
287 | .base = S5P64X0_GPJ_BASE, | ||
288 | .config = &s5p64x0_gpio_cfgs[3], | ||
289 | .chip = { | ||
290 | .base = S5P6440_GPJ(0), | ||
291 | .ngpio = S5P6440_GPIO_J_NR, | ||
292 | .label = "GPJ", | ||
293 | }, | ||
294 | }, { | ||
295 | .base = S5P64X0_GPN_BASE, | ||
296 | .config = &s5p64x0_gpio_cfgs[4], | ||
297 | .chip = { | ||
298 | .base = S5P6440_GPN(0), | ||
299 | .ngpio = S5P6440_GPIO_N_NR, | ||
300 | .label = "GPN", | ||
301 | }, | ||
302 | }, { | ||
303 | .base = S5P64X0_GPP_BASE, | ||
304 | .config = &s5p64x0_gpio_cfgs[5], | ||
305 | .chip = { | ||
306 | .base = S5P6440_GPP(0), | ||
307 | .ngpio = S5P6440_GPIO_P_NR, | ||
308 | .label = "GPP", | ||
309 | }, | ||
310 | }, | ||
311 | }; | ||
312 | |||
313 | static struct s3c_gpio_chip s5p6450_gpio_4bit[] = { | ||
314 | { | ||
315 | .base = S5P64X0_GPA_BASE, | ||
316 | .config = &s5p64x0_gpio_cfgs[1], | ||
317 | .chip = { | ||
318 | .base = S5P6450_GPA(0), | ||
319 | .ngpio = S5P6450_GPIO_A_NR, | ||
320 | .label = "GPA", | ||
321 | }, | ||
322 | }, { | ||
323 | .base = S5P64X0_GPB_BASE, | ||
324 | .config = &s5p64x0_gpio_cfgs[1], | ||
325 | .chip = { | ||
326 | .base = S5P6450_GPB(0), | ||
327 | .ngpio = S5P6450_GPIO_B_NR, | ||
328 | .label = "GPB", | ||
329 | }, | ||
330 | }, { | ||
331 | .base = S5P64X0_GPC_BASE, | ||
332 | .config = &s5p64x0_gpio_cfgs[1], | ||
333 | .chip = { | ||
334 | .base = S5P6450_GPC(0), | ||
335 | .ngpio = S5P6450_GPIO_C_NR, | ||
336 | .label = "GPC", | ||
337 | }, | ||
338 | }, { | ||
339 | .base = S5P6450_GPD_BASE, | ||
340 | .config = &s5p64x0_gpio_cfgs[1], | ||
341 | .chip = { | ||
342 | .base = S5P6450_GPD(0), | ||
343 | .ngpio = S5P6450_GPIO_D_NR, | ||
344 | .label = "GPD", | ||
345 | }, | ||
346 | }, { | ||
347 | .base = S5P6450_GPK_BASE, | ||
348 | .config = &s5p64x0_gpio_cfgs[1], | ||
349 | .chip = { | ||
350 | .base = S5P6450_GPK(0), | ||
351 | .ngpio = S5P6450_GPIO_K_NR, | ||
352 | .label = "GPK", | ||
353 | }, | ||
354 | }, | ||
355 | }; | ||
356 | |||
357 | static struct s3c_gpio_chip s5p6450_gpio_4bit2[] = { | ||
358 | { | ||
359 | .base = S5P64X0_GPG_BASE + 0x4, | ||
360 | .config = &s5p64x0_gpio_cfgs[1], | ||
361 | .chip = { | ||
362 | .base = S5P6450_GPG(0), | ||
363 | .ngpio = S5P6450_GPIO_G_NR, | ||
364 | .label = "GPG", | ||
365 | }, | ||
366 | }, { | ||
367 | .base = S5P64X0_GPH_BASE + 0x4, | ||
368 | .config = &s5p64x0_gpio_cfgs[1], | ||
369 | .chip = { | ||
370 | .base = S5P6450_GPH(0), | ||
371 | .ngpio = S5P6450_GPIO_H_NR, | ||
372 | .label = "GPH", | ||
373 | }, | ||
374 | }, | ||
375 | }; | ||
376 | |||
377 | static struct s3c_gpio_chip s5p6450_gpio_rbank_4bit2[] = { | ||
378 | { | ||
379 | .base = S5P64X0_GPR_BASE + 0x4, | ||
380 | .config = &s5p64x0_gpio_cfgs[2], | ||
381 | .chip = { | ||
382 | .base = S5P6450_GPR(0), | ||
383 | .ngpio = S5P6450_GPIO_R_NR, | ||
384 | .label = "GPR", | ||
385 | }, | ||
386 | }, | ||
387 | }; | ||
388 | |||
389 | static struct s3c_gpio_chip s5p6450_gpio_2bit[] = { | ||
390 | { | ||
391 | .base = S5P64X0_GPF_BASE, | ||
392 | .config = &s5p64x0_gpio_cfgs[5], | ||
393 | .chip = { | ||
394 | .base = S5P6450_GPF(0), | ||
395 | .ngpio = S5P6450_GPIO_F_NR, | ||
396 | .label = "GPF", | ||
397 | }, | ||
398 | }, { | ||
399 | .base = S5P64X0_GPI_BASE, | ||
400 | .config = &s5p64x0_gpio_cfgs[3], | ||
401 | .chip = { | ||
402 | .base = S5P6450_GPI(0), | ||
403 | .ngpio = S5P6450_GPIO_I_NR, | ||
404 | .label = "GPI", | ||
405 | }, | ||
406 | }, { | ||
407 | .base = S5P64X0_GPJ_BASE, | ||
408 | .config = &s5p64x0_gpio_cfgs[3], | ||
409 | .chip = { | ||
410 | .base = S5P6450_GPJ(0), | ||
411 | .ngpio = S5P6450_GPIO_J_NR, | ||
412 | .label = "GPJ", | ||
413 | }, | ||
414 | }, { | ||
415 | .base = S5P64X0_GPN_BASE, | ||
416 | .config = &s5p64x0_gpio_cfgs[4], | ||
417 | .chip = { | ||
418 | .base = S5P6450_GPN(0), | ||
419 | .ngpio = S5P6450_GPIO_N_NR, | ||
420 | .label = "GPN", | ||
421 | }, | ||
422 | }, { | ||
423 | .base = S5P64X0_GPP_BASE, | ||
424 | .config = &s5p64x0_gpio_cfgs[5], | ||
425 | .chip = { | ||
426 | .base = S5P6450_GPP(0), | ||
427 | .ngpio = S5P6450_GPIO_P_NR, | ||
428 | .label = "GPP", | ||
429 | }, | ||
430 | }, { | ||
431 | .base = S5P6450_GPQ_BASE, | ||
432 | .config = &s5p64x0_gpio_cfgs[4], | ||
433 | .chip = { | ||
434 | .base = S5P6450_GPQ(0), | ||
435 | .ngpio = S5P6450_GPIO_Q_NR, | ||
436 | .label = "GPQ", | ||
437 | }, | ||
438 | }, { | ||
439 | .base = S5P6450_GPS_BASE, | ||
440 | .config = &s5p64x0_gpio_cfgs[5], | ||
441 | .chip = { | ||
442 | .base = S5P6450_GPS(0), | ||
443 | .ngpio = S5P6450_GPIO_S_NR, | ||
444 | .label = "GPS", | ||
445 | }, | ||
446 | }, | ||
447 | }; | ||
448 | |||
449 | void __init s5p64x0_gpiolib_set_cfg(struct s3c_gpio_cfg *chipcfg, int nr_chips) | ||
450 | { | ||
451 | for (; nr_chips > 0; nr_chips--, chipcfg++) { | ||
452 | if (!chipcfg->set_config) | ||
453 | chipcfg->set_config = s3c_gpio_setcfg_s3c64xx_4bit; | ||
454 | if (!chipcfg->get_config) | ||
455 | chipcfg->get_config = s3c_gpio_getcfg_s3c64xx_4bit; | ||
456 | if (!chipcfg->set_pull) | ||
457 | chipcfg->set_pull = s3c_gpio_setpull_updown; | ||
458 | if (!chipcfg->get_pull) | ||
459 | chipcfg->get_pull = s3c_gpio_getpull_updown; | ||
460 | } | ||
461 | } | ||
462 | |||
463 | static void __init s5p64x0_gpio_add_rbank_4bit2(struct s3c_gpio_chip *chip, | ||
464 | int nr_chips) | ||
465 | { | ||
466 | for (; nr_chips > 0; nr_chips--, chip++) { | ||
467 | chip->chip.direction_input = s5p64x0_gpiolib_rbank_4bit2_input; | ||
468 | chip->chip.direction_output = | ||
469 | s5p64x0_gpiolib_rbank_4bit2_output; | ||
470 | s3c_gpiolib_add(chip); | ||
471 | } | ||
472 | } | ||
473 | |||
474 | static int __init s5p64x0_gpiolib_init(void) | ||
475 | { | ||
476 | unsigned int chipid; | ||
477 | |||
478 | chipid = __raw_readl(S5P64X0_SYS_ID); | ||
479 | |||
480 | s5p64x0_gpiolib_set_cfg(s5p64x0_gpio_cfgs, | ||
481 | ARRAY_SIZE(s5p64x0_gpio_cfgs)); | ||
482 | |||
483 | if ((chipid & 0xff000) == 0x50000) { | ||
484 | samsung_gpiolib_add_2bit_chips(s5p6450_gpio_2bit, | ||
485 | ARRAY_SIZE(s5p6450_gpio_2bit)); | ||
486 | |||
487 | samsung_gpiolib_add_4bit_chips(s5p6450_gpio_4bit, | ||
488 | ARRAY_SIZE(s5p6450_gpio_4bit)); | ||
489 | |||
490 | samsung_gpiolib_add_4bit2_chips(s5p6450_gpio_4bit2, | ||
491 | ARRAY_SIZE(s5p6450_gpio_4bit2)); | ||
492 | |||
493 | s5p64x0_gpio_add_rbank_4bit2(s5p6450_gpio_rbank_4bit2, | ||
494 | ARRAY_SIZE(s5p6450_gpio_rbank_4bit2)); | ||
495 | } else { | ||
496 | samsung_gpiolib_add_2bit_chips(s5p6440_gpio_2bit, | ||
497 | ARRAY_SIZE(s5p6440_gpio_2bit)); | ||
498 | |||
499 | samsung_gpiolib_add_4bit_chips(s5p6440_gpio_4bit, | ||
500 | ARRAY_SIZE(s5p6440_gpio_4bit)); | ||
501 | |||
502 | samsung_gpiolib_add_4bit2_chips(s5p6440_gpio_4bit2, | ||
503 | ARRAY_SIZE(s5p6440_gpio_4bit2)); | ||
504 | |||
505 | s5p64x0_gpio_add_rbank_4bit2(s5p6440_gpio_rbank_4bit2, | ||
506 | ARRAY_SIZE(s5p6440_gpio_rbank_4bit2)); | ||
507 | } | ||
508 | |||
509 | return 0; | ||
510 | } | ||
511 | core_initcall(s5p64x0_gpiolib_init); | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h index 3e22109e1b7b..eba8aea63ed8 100644 --- a/arch/arm/mach-s5pv210/include/mach/pm-core.h +++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h | |||
@@ -43,4 +43,4 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs, | |||
43 | } | 43 | } |
44 | 44 | ||
45 | static inline void s3c_pm_restored_gpios(void) { } | 45 | static inline void s3c_pm_restored_gpios(void) { } |
46 | static inline void s3c_pm_saved_gpios(void) { } | 46 | static inline void samsung_pm_saved_gpios(void) { } |
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig index 8c5b3029b39f..d8973ac46bc4 100644 --- a/arch/arm/plat-s3c24xx/Kconfig +++ b/arch/arm/plat-s3c24xx/Kconfig | |||
@@ -9,7 +9,6 @@ config PLAT_S3C24XX | |||
9 | select NO_IOPORT | 9 | select NO_IOPORT |
10 | select ARCH_REQUIRE_GPIOLIB | 10 | select ARCH_REQUIRE_GPIOLIB |
11 | select S3C_DEV_NAND | 11 | select S3C_DEV_NAND |
12 | select S3C_GPIO_CFG_S3C24XX | ||
13 | help | 12 | help |
14 | Base platform code for any Samsung S3C24XX device | 13 | Base platform code for any Samsung S3C24XX device |
15 | 14 | ||
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile index 0291bd6e236e..e4f46495ed30 100644 --- a/arch/arm/plat-s3c24xx/Makefile +++ b/arch/arm/plat-s3c24xx/Makefile | |||
@@ -15,8 +15,6 @@ obj- := | |||
15 | obj-y += cpu.o | 15 | obj-y += cpu.o |
16 | obj-y += irq.o | 16 | obj-y += irq.o |
17 | obj-y += devs.o | 17 | obj-y += devs.o |
18 | obj-y += gpio.o | ||
19 | obj-y += gpiolib.o | ||
20 | obj-y += clock.o | 18 | obj-y += clock.o |
21 | obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o | 19 | obj-$(CONFIG_S3C24XX_DCLK) += clock-dclk.o |
22 | 20 | ||
diff --git a/arch/arm/plat-s3c24xx/gpio.c b/arch/arm/plat-s3c24xx/gpio.c deleted file mode 100644 index 2f3d7c089dfa..000000000000 --- a/arch/arm/plat-s3c24xx/gpio.c +++ /dev/null | |||
@@ -1,96 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/gpio.c | ||
2 | * | ||
3 | * Copyright (c) 2004-2010 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C24XX GPIO support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | */ | ||
22 | |||
23 | #include <linux/kernel.h> | ||
24 | #include <linux/init.h> | ||
25 | #include <linux/module.h> | ||
26 | #include <linux/interrupt.h> | ||
27 | #include <linux/ioport.h> | ||
28 | #include <linux/gpio.h> | ||
29 | #include <linux/io.h> | ||
30 | |||
31 | #include <mach/hardware.h> | ||
32 | #include <mach/gpio-fns.h> | ||
33 | #include <asm/irq.h> | ||
34 | |||
35 | #include <mach/regs-gpio.h> | ||
36 | |||
37 | #include <plat/gpio-core.h> | ||
38 | |||
39 | /* gpiolib wrappers until these are totally eliminated */ | ||
40 | |||
41 | void s3c2410_gpio_pullup(unsigned int pin, unsigned int to) | ||
42 | { | ||
43 | int ret; | ||
44 | |||
45 | WARN_ON(to); /* should be none of these left */ | ||
46 | |||
47 | if (!to) { | ||
48 | /* if pull is enabled, try first with up, and if that | ||
49 | * fails, try using down */ | ||
50 | |||
51 | ret = s3c_gpio_setpull(pin, S3C_GPIO_PULL_UP); | ||
52 | if (ret) | ||
53 | s3c_gpio_setpull(pin, S3C_GPIO_PULL_DOWN); | ||
54 | } else { | ||
55 | s3c_gpio_setpull(pin, S3C_GPIO_PULL_NONE); | ||
56 | } | ||
57 | } | ||
58 | EXPORT_SYMBOL(s3c2410_gpio_pullup); | ||
59 | |||
60 | void s3c2410_gpio_setpin(unsigned int pin, unsigned int to) | ||
61 | { | ||
62 | /* do this via gpiolib until all users removed */ | ||
63 | |||
64 | gpio_request(pin, "temporary"); | ||
65 | gpio_set_value(pin, to); | ||
66 | gpio_free(pin); | ||
67 | } | ||
68 | |||
69 | EXPORT_SYMBOL(s3c2410_gpio_setpin); | ||
70 | |||
71 | unsigned int s3c2410_gpio_getpin(unsigned int pin) | ||
72 | { | ||
73 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
74 | unsigned long offs = pin - chip->chip.base; | ||
75 | |||
76 | return __raw_readl(chip->base + 0x04) & (1<< offs); | ||
77 | } | ||
78 | |||
79 | EXPORT_SYMBOL(s3c2410_gpio_getpin); | ||
80 | |||
81 | unsigned int s3c2410_modify_misccr(unsigned int clear, unsigned int change) | ||
82 | { | ||
83 | unsigned long flags; | ||
84 | unsigned long misccr; | ||
85 | |||
86 | local_irq_save(flags); | ||
87 | misccr = __raw_readl(S3C24XX_MISCCR); | ||
88 | misccr &= ~clear; | ||
89 | misccr ^= change; | ||
90 | __raw_writel(misccr, S3C24XX_MISCCR); | ||
91 | local_irq_restore(flags); | ||
92 | |||
93 | return misccr; | ||
94 | } | ||
95 | |||
96 | EXPORT_SYMBOL(s3c2410_modify_misccr); | ||
diff --git a/arch/arm/plat-s3c24xx/gpiolib.c b/arch/arm/plat-s3c24xx/gpiolib.c deleted file mode 100644 index 243b6411050d..000000000000 --- a/arch/arm/plat-s3c24xx/gpiolib.c +++ /dev/null | |||
@@ -1,229 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s3c24xx/gpiolib.c | ||
2 | * | ||
3 | * Copyright (c) 2008-2010 Simtec Electronics | ||
4 | * http://armlinux.simtec.co.uk/ | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * | ||
7 | * S3C24XX GPIOlib support | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/sysdev.h> | ||
19 | #include <linux/ioport.h> | ||
20 | #include <linux/io.h> | ||
21 | #include <linux/gpio.h> | ||
22 | |||
23 | #include <plat/gpio-core.h> | ||
24 | #include <plat/gpio-cfg.h> | ||
25 | #include <plat/gpio-cfg-helpers.h> | ||
26 | #include <mach/hardware.h> | ||
27 | #include <asm/irq.h> | ||
28 | #include <plat/pm.h> | ||
29 | |||
30 | #include <mach/regs-gpio.h> | ||
31 | |||
32 | static int s3c24xx_gpiolib_banka_input(struct gpio_chip *chip, unsigned offset) | ||
33 | { | ||
34 | return -EINVAL; | ||
35 | } | ||
36 | |||
37 | static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip, | ||
38 | unsigned offset, int value) | ||
39 | { | ||
40 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
41 | void __iomem *base = ourchip->base; | ||
42 | unsigned long flags; | ||
43 | unsigned long dat; | ||
44 | unsigned long con; | ||
45 | |||
46 | local_irq_save(flags); | ||
47 | |||
48 | con = __raw_readl(base + 0x00); | ||
49 | dat = __raw_readl(base + 0x04); | ||
50 | |||
51 | dat &= ~(1 << offset); | ||
52 | if (value) | ||
53 | dat |= 1 << offset; | ||
54 | |||
55 | __raw_writel(dat, base + 0x04); | ||
56 | |||
57 | con &= ~(1 << offset); | ||
58 | |||
59 | __raw_writel(con, base + 0x00); | ||
60 | __raw_writel(dat, base + 0x04); | ||
61 | |||
62 | local_irq_restore(flags); | ||
63 | return 0; | ||
64 | } | ||
65 | |||
66 | static int s3c24xx_gpiolib_bankf_toirq(struct gpio_chip *chip, unsigned offset) | ||
67 | { | ||
68 | if (offset < 4) | ||
69 | return IRQ_EINT0 + offset; | ||
70 | |||
71 | if (offset < 8) | ||
72 | return IRQ_EINT4 + offset - 4; | ||
73 | |||
74 | return -EINVAL; | ||
75 | } | ||
76 | |||
77 | static struct s3c_gpio_cfg s3c24xx_gpiocfg_banka = { | ||
78 | .set_config = s3c_gpio_setcfg_s3c24xx_a, | ||
79 | .get_config = s3c_gpio_getcfg_s3c24xx_a, | ||
80 | }; | ||
81 | |||
82 | struct s3c_gpio_cfg s3c24xx_gpiocfg_default = { | ||
83 | .set_config = s3c_gpio_setcfg_s3c24xx, | ||
84 | .get_config = s3c_gpio_getcfg_s3c24xx, | ||
85 | }; | ||
86 | |||
87 | struct s3c_gpio_chip s3c24xx_gpios[] = { | ||
88 | [0] = { | ||
89 | .base = S3C2410_GPACON, | ||
90 | .pm = __gpio_pm(&s3c_gpio_pm_1bit), | ||
91 | .config = &s3c24xx_gpiocfg_banka, | ||
92 | .chip = { | ||
93 | .base = S3C2410_GPA(0), | ||
94 | .owner = THIS_MODULE, | ||
95 | .label = "GPIOA", | ||
96 | .ngpio = 24, | ||
97 | .direction_input = s3c24xx_gpiolib_banka_input, | ||
98 | .direction_output = s3c24xx_gpiolib_banka_output, | ||
99 | }, | ||
100 | }, | ||
101 | [1] = { | ||
102 | .base = S3C2410_GPBCON, | ||
103 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
104 | .chip = { | ||
105 | .base = S3C2410_GPB(0), | ||
106 | .owner = THIS_MODULE, | ||
107 | .label = "GPIOB", | ||
108 | .ngpio = 16, | ||
109 | }, | ||
110 | }, | ||
111 | [2] = { | ||
112 | .base = S3C2410_GPCCON, | ||
113 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
114 | .chip = { | ||
115 | .base = S3C2410_GPC(0), | ||
116 | .owner = THIS_MODULE, | ||
117 | .label = "GPIOC", | ||
118 | .ngpio = 16, | ||
119 | }, | ||
120 | }, | ||
121 | [3] = { | ||
122 | .base = S3C2410_GPDCON, | ||
123 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
124 | .chip = { | ||
125 | .base = S3C2410_GPD(0), | ||
126 | .owner = THIS_MODULE, | ||
127 | .label = "GPIOD", | ||
128 | .ngpio = 16, | ||
129 | }, | ||
130 | }, | ||
131 | [4] = { | ||
132 | .base = S3C2410_GPECON, | ||
133 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
134 | .chip = { | ||
135 | .base = S3C2410_GPE(0), | ||
136 | .label = "GPIOE", | ||
137 | .owner = THIS_MODULE, | ||
138 | .ngpio = 16, | ||
139 | }, | ||
140 | }, | ||
141 | [5] = { | ||
142 | .base = S3C2410_GPFCON, | ||
143 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
144 | .chip = { | ||
145 | .base = S3C2410_GPF(0), | ||
146 | .owner = THIS_MODULE, | ||
147 | .label = "GPIOF", | ||
148 | .ngpio = 8, | ||
149 | .to_irq = s3c24xx_gpiolib_bankf_toirq, | ||
150 | }, | ||
151 | }, | ||
152 | [6] = { | ||
153 | .base = S3C2410_GPGCON, | ||
154 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
155 | .irq_base = IRQ_EINT8, | ||
156 | .chip = { | ||
157 | .base = S3C2410_GPG(0), | ||
158 | .owner = THIS_MODULE, | ||
159 | .label = "GPIOG", | ||
160 | .ngpio = 16, | ||
161 | .to_irq = samsung_gpiolib_to_irq, | ||
162 | }, | ||
163 | }, { | ||
164 | .base = S3C2410_GPHCON, | ||
165 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
166 | .chip = { | ||
167 | .base = S3C2410_GPH(0), | ||
168 | .owner = THIS_MODULE, | ||
169 | .label = "GPIOH", | ||
170 | .ngpio = 11, | ||
171 | }, | ||
172 | }, | ||
173 | /* GPIOS for the S3C2443 and later devices. */ | ||
174 | { | ||
175 | .base = S3C2440_GPJCON, | ||
176 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
177 | .chip = { | ||
178 | .base = S3C2410_GPJ(0), | ||
179 | .owner = THIS_MODULE, | ||
180 | .label = "GPIOJ", | ||
181 | .ngpio = 16, | ||
182 | }, | ||
183 | }, { | ||
184 | .base = S3C2443_GPKCON, | ||
185 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
186 | .chip = { | ||
187 | .base = S3C2410_GPK(0), | ||
188 | .owner = THIS_MODULE, | ||
189 | .label = "GPIOK", | ||
190 | .ngpio = 16, | ||
191 | }, | ||
192 | }, { | ||
193 | .base = S3C2443_GPLCON, | ||
194 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
195 | .chip = { | ||
196 | .base = S3C2410_GPL(0), | ||
197 | .owner = THIS_MODULE, | ||
198 | .label = "GPIOL", | ||
199 | .ngpio = 15, | ||
200 | }, | ||
201 | }, { | ||
202 | .base = S3C2443_GPMCON, | ||
203 | .pm = __gpio_pm(&s3c_gpio_pm_2bit), | ||
204 | .chip = { | ||
205 | .base = S3C2410_GPM(0), | ||
206 | .owner = THIS_MODULE, | ||
207 | .label = "GPIOM", | ||
208 | .ngpio = 2, | ||
209 | }, | ||
210 | }, | ||
211 | }; | ||
212 | |||
213 | |||
214 | static __init int s3c24xx_gpiolib_init(void) | ||
215 | { | ||
216 | struct s3c_gpio_chip *chip = s3c24xx_gpios; | ||
217 | int gpn; | ||
218 | |||
219 | for (gpn = 0; gpn < ARRAY_SIZE(s3c24xx_gpios); gpn++, chip++) { | ||
220 | if (!chip->config) | ||
221 | chip->config = &s3c24xx_gpiocfg_default; | ||
222 | |||
223 | s3c_gpiolib_add(chip); | ||
224 | } | ||
225 | |||
226 | return 0; | ||
227 | } | ||
228 | |||
229 | core_initcall(s3c24xx_gpiolib_init); | ||
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig index 9843c954c042..ac610bee2cb3 100644 --- a/arch/arm/plat-s5p/Kconfig +++ b/arch/arm/plat-s5p/Kconfig | |||
@@ -16,9 +16,6 @@ config PLAT_S5P | |||
16 | select S3C_GPIO_TRACK | 16 | select S3C_GPIO_TRACK |
17 | select S5P_GPIO_DRVSTR | 17 | select S5P_GPIO_DRVSTR |
18 | select SAMSUNG_GPIOLIB_4BIT | 18 | select SAMSUNG_GPIOLIB_4BIT |
19 | select S3C_GPIO_CFG_S3C64XX | ||
20 | select S3C_GPIO_PULL_UPDOWN | ||
21 | select S3C_GPIO_CFG_S3C24XX | ||
22 | select PLAT_SAMSUNG | 19 | select PLAT_SAMSUNG |
23 | select SAMSUNG_CLKSRC | 20 | select SAMSUNG_CLKSRC |
24 | select SAMSUNG_IRQ_VIC_TIMER | 21 | select SAMSUNG_IRQ_VIC_TIMER |
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c index f88216d23991..a566523d34ec 100644 --- a/arch/arm/plat-s5p/irq-gpioint.c +++ b/arch/arm/plat-s5p/irq-gpioint.c | |||
@@ -37,7 +37,7 @@ struct s5p_gpioint_bank { | |||
37 | int start; | 37 | int start; |
38 | int nr_groups; | 38 | int nr_groups; |
39 | int irq; | 39 | int irq; |
40 | struct s3c_gpio_chip **chips; | 40 | struct samsung_gpio_chip **chips; |
41 | void (*handler)(unsigned int, struct irq_desc *); | 41 | void (*handler)(unsigned int, struct irq_desc *); |
42 | }; | 42 | }; |
43 | 43 | ||
@@ -87,7 +87,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) | |||
87 | chained_irq_enter(chip, desc); | 87 | chained_irq_enter(chip, desc); |
88 | 88 | ||
89 | for (group = 0; group < bank->nr_groups; group++) { | 89 | for (group = 0; group < bank->nr_groups; group++) { |
90 | struct s3c_gpio_chip *chip = bank->chips[group]; | 90 | struct samsung_gpio_chip *chip = bank->chips[group]; |
91 | if (!chip) | 91 | if (!chip) |
92 | continue; | 92 | continue; |
93 | 93 | ||
@@ -110,7 +110,7 @@ static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc) | |||
110 | chained_irq_exit(chip, desc); | 110 | chained_irq_exit(chip, desc); |
111 | } | 111 | } |
112 | 112 | ||
113 | static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) | 113 | static __init int s5p_gpioint_add(struct samsung_gpio_chip *chip) |
114 | { | 114 | { |
115 | static int used_gpioint_groups = 0; | 115 | static int used_gpioint_groups = 0; |
116 | int group = chip->group; | 116 | int group = chip->group; |
@@ -131,7 +131,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) | |||
131 | return -EINVAL; | 131 | return -EINVAL; |
132 | 132 | ||
133 | if (!bank->handler) { | 133 | if (!bank->handler) { |
134 | bank->chips = kzalloc(sizeof(struct s3c_gpio_chip *) * | 134 | bank->chips = kzalloc(sizeof(struct samsung_gpio_chip *) * |
135 | bank->nr_groups, GFP_KERNEL); | 135 | bank->nr_groups, GFP_KERNEL); |
136 | if (!bank->chips) | 136 | if (!bank->chips) |
137 | return -ENOMEM; | 137 | return -ENOMEM; |
@@ -174,7 +174,7 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip) | |||
174 | 174 | ||
175 | int __init s5p_register_gpio_interrupt(int pin) | 175 | int __init s5p_register_gpio_interrupt(int pin) |
176 | { | 176 | { |
177 | struct s3c_gpio_chip *my_chip = s3c_gpiolib_getchip(pin); | 177 | struct samsung_gpio_chip *my_chip = samsung_gpiolib_getchip(pin); |
178 | int offset, group; | 178 | int offset, group; |
179 | int ret; | 179 | int ret; |
180 | 180 | ||
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 0a3eec616d61..74714c155e14 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
@@ -79,39 +79,12 @@ config SAMSUNG_GPIOLIB_4BIT | |||
79 | configuration. GPIOlib shall be compiled only for S3C64XX and S5P | 79 | configuration. GPIOlib shall be compiled only for S3C64XX and S5P |
80 | series of processors. | 80 | series of processors. |
81 | 81 | ||
82 | config S3C_GPIO_CFG_S3C24XX | ||
83 | bool | ||
84 | help | ||
85 | Internal configuration to enable S3C24XX style GPIO configuration | ||
86 | functions. | ||
87 | |||
88 | config S3C_GPIO_CFG_S3C64XX | 82 | config S3C_GPIO_CFG_S3C64XX |
89 | bool | 83 | bool |
90 | help | 84 | help |
91 | Internal configuration to enable S3C64XX style GPIO configuration | 85 | Internal configuration to enable S3C64XX style GPIO configuration |
92 | functions. | 86 | functions. |
93 | 87 | ||
94 | config S3C_GPIO_PULL_UPDOWN | ||
95 | bool | ||
96 | help | ||
97 | Internal configuration to enable the correct GPIO pull helper | ||
98 | |||
99 | config S3C_GPIO_PULL_S3C2443 | ||
100 | bool | ||
101 | select S3C_GPIO_PULL_UPDOWN | ||
102 | help | ||
103 | Internal configuration to enable the correct GPIO pull helper for S3C2443-style GPIO | ||
104 | |||
105 | config S3C_GPIO_PULL_DOWN | ||
106 | bool | ||
107 | help | ||
108 | Internal configuration to enable the correct GPIO pull helper | ||
109 | |||
110 | config S3C_GPIO_PULL_UP | ||
111 | bool | ||
112 | help | ||
113 | Internal configuration to enable the correct GPIO pull helper | ||
114 | |||
115 | config S5P_GPIO_DRVSTR | 88 | config S5P_GPIO_DRVSTR |
116 | bool | 89 | bool |
117 | help | 90 | help |
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile index 90758494cad8..5ed2b2be0c7e 100644 --- a/arch/arm/plat-samsung/Makefile +++ b/arch/arm/plat-samsung/Makefile | |||
@@ -15,8 +15,6 @@ obj-y += init.o | |||
15 | obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o | 15 | obj-$(CONFIG_ARCH_USES_GETTIMEOFFSET) += time.o |
16 | obj-y += clock.o | 16 | obj-y += clock.o |
17 | obj-y += pwm-clock.o | 17 | obj-y += pwm-clock.o |
18 | obj-y += gpio.o | ||
19 | obj-y += gpio-config.o | ||
20 | obj-y += dev-asocdma.o | 18 | obj-y += dev-asocdma.o |
21 | 19 | ||
22 | obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o | 20 | obj-$(CONFIG_SAMSUNG_CLKSRC) += clock-clksrc.o |
diff --git a/arch/arm/plat-samsung/gpio-config.c b/arch/arm/plat-samsung/gpio-config.c deleted file mode 100644 index 1c0b0401594b..000000000000 --- a/arch/arm/plat-samsung/gpio-config.c +++ /dev/null | |||
@@ -1,431 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s3c/gpio-config.c | ||
2 | * | ||
3 | * Copyright 2008 Openmoko, Inc. | ||
4 | * Copyright 2008-2010 Simtec Electronics | ||
5 | * Ben Dooks <ben@simtec.co.uk> | ||
6 | * http://armlinux.simtec.co.uk/ | ||
7 | * | ||
8 | * S3C series GPIO configuration core | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/gpio.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include <plat/gpio-core.h> | ||
21 | #include <plat/gpio-cfg.h> | ||
22 | #include <plat/gpio-cfg-helpers.h> | ||
23 | |||
24 | int s3c_gpio_cfgpin(unsigned int pin, unsigned int config) | ||
25 | { | ||
26 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
27 | unsigned long flags; | ||
28 | int offset; | ||
29 | int ret; | ||
30 | |||
31 | if (!chip) | ||
32 | return -EINVAL; | ||
33 | |||
34 | offset = pin - chip->chip.base; | ||
35 | |||
36 | s3c_gpio_lock(chip, flags); | ||
37 | ret = s3c_gpio_do_setcfg(chip, offset, config); | ||
38 | s3c_gpio_unlock(chip, flags); | ||
39 | |||
40 | return ret; | ||
41 | } | ||
42 | EXPORT_SYMBOL(s3c_gpio_cfgpin); | ||
43 | |||
44 | int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, | ||
45 | unsigned int cfg) | ||
46 | { | ||
47 | int ret; | ||
48 | |||
49 | for (; nr > 0; nr--, start++) { | ||
50 | ret = s3c_gpio_cfgpin(start, cfg); | ||
51 | if (ret != 0) | ||
52 | return ret; | ||
53 | } | ||
54 | |||
55 | return 0; | ||
56 | } | ||
57 | EXPORT_SYMBOL_GPL(s3c_gpio_cfgpin_range); | ||
58 | |||
59 | int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, | ||
60 | unsigned int cfg, s3c_gpio_pull_t pull) | ||
61 | { | ||
62 | int ret; | ||
63 | |||
64 | for (; nr > 0; nr--, start++) { | ||
65 | s3c_gpio_setpull(start, pull); | ||
66 | ret = s3c_gpio_cfgpin(start, cfg); | ||
67 | if (ret != 0) | ||
68 | return ret; | ||
69 | } | ||
70 | |||
71 | return 0; | ||
72 | } | ||
73 | EXPORT_SYMBOL_GPL(s3c_gpio_cfgall_range); | ||
74 | |||
75 | unsigned s3c_gpio_getcfg(unsigned int pin) | ||
76 | { | ||
77 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
78 | unsigned long flags; | ||
79 | unsigned ret = 0; | ||
80 | int offset; | ||
81 | |||
82 | if (chip) { | ||
83 | offset = pin - chip->chip.base; | ||
84 | |||
85 | s3c_gpio_lock(chip, flags); | ||
86 | ret = s3c_gpio_do_getcfg(chip, offset); | ||
87 | s3c_gpio_unlock(chip, flags); | ||
88 | } | ||
89 | |||
90 | return ret; | ||
91 | } | ||
92 | EXPORT_SYMBOL(s3c_gpio_getcfg); | ||
93 | |||
94 | |||
95 | int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull) | ||
96 | { | ||
97 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
98 | unsigned long flags; | ||
99 | int offset, ret; | ||
100 | |||
101 | if (!chip) | ||
102 | return -EINVAL; | ||
103 | |||
104 | offset = pin - chip->chip.base; | ||
105 | |||
106 | s3c_gpio_lock(chip, flags); | ||
107 | ret = s3c_gpio_do_setpull(chip, offset, pull); | ||
108 | s3c_gpio_unlock(chip, flags); | ||
109 | |||
110 | return ret; | ||
111 | } | ||
112 | EXPORT_SYMBOL(s3c_gpio_setpull); | ||
113 | |||
114 | s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin) | ||
115 | { | ||
116 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
117 | unsigned long flags; | ||
118 | int offset; | ||
119 | u32 pup = 0; | ||
120 | |||
121 | if (chip) { | ||
122 | offset = pin - chip->chip.base; | ||
123 | |||
124 | s3c_gpio_lock(chip, flags); | ||
125 | pup = s3c_gpio_do_getpull(chip, offset); | ||
126 | s3c_gpio_unlock(chip, flags); | ||
127 | } | ||
128 | |||
129 | return (__force s3c_gpio_pull_t)pup; | ||
130 | } | ||
131 | EXPORT_SYMBOL(s3c_gpio_getpull); | ||
132 | |||
133 | #ifdef CONFIG_S3C_GPIO_CFG_S3C24XX | ||
134 | int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, | ||
135 | unsigned int off, unsigned int cfg) | ||
136 | { | ||
137 | void __iomem *reg = chip->base; | ||
138 | unsigned int shift = off; | ||
139 | u32 con; | ||
140 | |||
141 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
142 | cfg &= 0xf; | ||
143 | |||
144 | /* Map output to 0, and SFN2 to 1 */ | ||
145 | cfg -= 1; | ||
146 | if (cfg > 1) | ||
147 | return -EINVAL; | ||
148 | |||
149 | cfg <<= shift; | ||
150 | } | ||
151 | |||
152 | con = __raw_readl(reg); | ||
153 | con &= ~(0x1 << shift); | ||
154 | con |= cfg; | ||
155 | __raw_writel(con, reg); | ||
156 | |||
157 | return 0; | ||
158 | } | ||
159 | |||
160 | unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, | ||
161 | unsigned int off) | ||
162 | { | ||
163 | u32 con; | ||
164 | |||
165 | con = __raw_readl(chip->base); | ||
166 | con >>= off; | ||
167 | con &= 1; | ||
168 | con++; | ||
169 | |||
170 | return S3C_GPIO_SFN(con); | ||
171 | } | ||
172 | |||
173 | int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, | ||
174 | unsigned int off, unsigned int cfg) | ||
175 | { | ||
176 | void __iomem *reg = chip->base; | ||
177 | unsigned int shift = off * 2; | ||
178 | u32 con; | ||
179 | |||
180 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
181 | cfg &= 0xf; | ||
182 | if (cfg > 3) | ||
183 | return -EINVAL; | ||
184 | |||
185 | cfg <<= shift; | ||
186 | } | ||
187 | |||
188 | con = __raw_readl(reg); | ||
189 | con &= ~(0x3 << shift); | ||
190 | con |= cfg; | ||
191 | __raw_writel(con, reg); | ||
192 | |||
193 | return 0; | ||
194 | } | ||
195 | |||
196 | unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip, | ||
197 | unsigned int off) | ||
198 | { | ||
199 | u32 con; | ||
200 | |||
201 | con = __raw_readl(chip->base); | ||
202 | con >>= off * 2; | ||
203 | con &= 3; | ||
204 | |||
205 | /* this conversion works for IN and OUT as well as special mode */ | ||
206 | return S3C_GPIO_SPECIAL(con); | ||
207 | } | ||
208 | #endif | ||
209 | |||
210 | #ifdef CONFIG_S3C_GPIO_CFG_S3C64XX | ||
211 | int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | ||
212 | unsigned int off, unsigned int cfg) | ||
213 | { | ||
214 | void __iomem *reg = chip->base; | ||
215 | unsigned int shift = (off & 7) * 4; | ||
216 | u32 con; | ||
217 | |||
218 | if (off < 8 && chip->chip.ngpio > 8) | ||
219 | reg -= 4; | ||
220 | |||
221 | if (s3c_gpio_is_cfg_special(cfg)) { | ||
222 | cfg &= 0xf; | ||
223 | cfg <<= shift; | ||
224 | } | ||
225 | |||
226 | con = __raw_readl(reg); | ||
227 | con &= ~(0xf << shift); | ||
228 | con |= cfg; | ||
229 | __raw_writel(con, reg); | ||
230 | |||
231 | return 0; | ||
232 | } | ||
233 | |||
234 | unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | ||
235 | unsigned int off) | ||
236 | { | ||
237 | void __iomem *reg = chip->base; | ||
238 | unsigned int shift = (off & 7) * 4; | ||
239 | u32 con; | ||
240 | |||
241 | if (off < 8 && chip->chip.ngpio > 8) | ||
242 | reg -= 4; | ||
243 | |||
244 | con = __raw_readl(reg); | ||
245 | con >>= shift; | ||
246 | con &= 0xf; | ||
247 | |||
248 | /* this conversion works for IN and OUT as well as special mode */ | ||
249 | return S3C_GPIO_SPECIAL(con); | ||
250 | } | ||
251 | |||
252 | #endif /* CONFIG_S3C_GPIO_CFG_S3C64XX */ | ||
253 | |||
254 | #ifdef CONFIG_S3C_GPIO_PULL_UPDOWN | ||
255 | int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, | ||
256 | unsigned int off, s3c_gpio_pull_t pull) | ||
257 | { | ||
258 | void __iomem *reg = chip->base + 0x08; | ||
259 | int shift = off * 2; | ||
260 | u32 pup; | ||
261 | |||
262 | pup = __raw_readl(reg); | ||
263 | pup &= ~(3 << shift); | ||
264 | pup |= pull << shift; | ||
265 | __raw_writel(pup, reg); | ||
266 | |||
267 | return 0; | ||
268 | } | ||
269 | |||
270 | s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, | ||
271 | unsigned int off) | ||
272 | { | ||
273 | void __iomem *reg = chip->base + 0x08; | ||
274 | int shift = off * 2; | ||
275 | u32 pup = __raw_readl(reg); | ||
276 | |||
277 | pup >>= shift; | ||
278 | pup &= 0x3; | ||
279 | return (__force s3c_gpio_pull_t)pup; | ||
280 | } | ||
281 | |||
282 | #ifdef CONFIG_S3C_GPIO_PULL_S3C2443 | ||
283 | int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, | ||
284 | unsigned int off, s3c_gpio_pull_t pull) | ||
285 | { | ||
286 | switch (pull) { | ||
287 | case S3C_GPIO_PULL_NONE: | ||
288 | pull = 0x01; | ||
289 | break; | ||
290 | case S3C_GPIO_PULL_UP: | ||
291 | pull = 0x00; | ||
292 | break; | ||
293 | case S3C_GPIO_PULL_DOWN: | ||
294 | pull = 0x02; | ||
295 | break; | ||
296 | } | ||
297 | return s3c_gpio_setpull_updown(chip, off, pull); | ||
298 | } | ||
299 | |||
300 | s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, | ||
301 | unsigned int off) | ||
302 | { | ||
303 | s3c_gpio_pull_t pull; | ||
304 | |||
305 | pull = s3c_gpio_getpull_updown(chip, off); | ||
306 | |||
307 | switch (pull) { | ||
308 | case 0x00: | ||
309 | pull = S3C_GPIO_PULL_UP; | ||
310 | break; | ||
311 | case 0x01: | ||
312 | case 0x03: | ||
313 | pull = S3C_GPIO_PULL_NONE; | ||
314 | break; | ||
315 | case 0x02: | ||
316 | pull = S3C_GPIO_PULL_DOWN; | ||
317 | break; | ||
318 | } | ||
319 | |||
320 | return pull; | ||
321 | } | ||
322 | #endif | ||
323 | #endif | ||
324 | |||
325 | #if defined(CONFIG_S3C_GPIO_PULL_UP) || defined(CONFIG_S3C_GPIO_PULL_DOWN) | ||
326 | static int s3c_gpio_setpull_1(struct s3c_gpio_chip *chip, | ||
327 | unsigned int off, s3c_gpio_pull_t pull, | ||
328 | s3c_gpio_pull_t updown) | ||
329 | { | ||
330 | void __iomem *reg = chip->base + 0x08; | ||
331 | u32 pup = __raw_readl(reg); | ||
332 | |||
333 | if (pull == updown) | ||
334 | pup &= ~(1 << off); | ||
335 | else if (pull == S3C_GPIO_PULL_NONE) | ||
336 | pup |= (1 << off); | ||
337 | else | ||
338 | return -EINVAL; | ||
339 | |||
340 | __raw_writel(pup, reg); | ||
341 | return 0; | ||
342 | } | ||
343 | |||
344 | static s3c_gpio_pull_t s3c_gpio_getpull_1(struct s3c_gpio_chip *chip, | ||
345 | unsigned int off, s3c_gpio_pull_t updown) | ||
346 | { | ||
347 | void __iomem *reg = chip->base + 0x08; | ||
348 | u32 pup = __raw_readl(reg); | ||
349 | |||
350 | pup &= (1 << off); | ||
351 | return pup ? S3C_GPIO_PULL_NONE : updown; | ||
352 | } | ||
353 | #endif /* CONFIG_S3C_GPIO_PULL_UP || CONFIG_S3C_GPIO_PULL_DOWN */ | ||
354 | |||
355 | #ifdef CONFIG_S3C_GPIO_PULL_UP | ||
356 | s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, | ||
357 | unsigned int off) | ||
358 | { | ||
359 | return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_UP); | ||
360 | } | ||
361 | |||
362 | int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, | ||
363 | unsigned int off, s3c_gpio_pull_t pull) | ||
364 | { | ||
365 | return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_UP); | ||
366 | } | ||
367 | #endif /* CONFIG_S3C_GPIO_PULL_UP */ | ||
368 | |||
369 | #ifdef CONFIG_S3C_GPIO_PULL_DOWN | ||
370 | s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, | ||
371 | unsigned int off) | ||
372 | { | ||
373 | return s3c_gpio_getpull_1(chip, off, S3C_GPIO_PULL_DOWN); | ||
374 | } | ||
375 | |||
376 | int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, | ||
377 | unsigned int off, s3c_gpio_pull_t pull) | ||
378 | { | ||
379 | return s3c_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); | ||
380 | } | ||
381 | #endif /* CONFIG_S3C_GPIO_PULL_DOWN */ | ||
382 | |||
383 | #ifdef CONFIG_S5P_GPIO_DRVSTR | ||
384 | s5p_gpio_drvstr_t s5p_gpio_get_drvstr(unsigned int pin) | ||
385 | { | ||
386 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
387 | unsigned int off; | ||
388 | void __iomem *reg; | ||
389 | int shift; | ||
390 | u32 drvstr; | ||
391 | |||
392 | if (!chip) | ||
393 | return -EINVAL; | ||
394 | |||
395 | off = pin - chip->chip.base; | ||
396 | shift = off * 2; | ||
397 | reg = chip->base + 0x0C; | ||
398 | |||
399 | drvstr = __raw_readl(reg); | ||
400 | drvstr = drvstr >> shift; | ||
401 | drvstr &= 0x3; | ||
402 | |||
403 | return (__force s5p_gpio_drvstr_t)drvstr; | ||
404 | } | ||
405 | EXPORT_SYMBOL(s5p_gpio_get_drvstr); | ||
406 | |||
407 | int s5p_gpio_set_drvstr(unsigned int pin, s5p_gpio_drvstr_t drvstr) | ||
408 | { | ||
409 | struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin); | ||
410 | unsigned int off; | ||
411 | void __iomem *reg; | ||
412 | int shift; | ||
413 | u32 tmp; | ||
414 | |||
415 | if (!chip) | ||
416 | return -EINVAL; | ||
417 | |||
418 | off = pin - chip->chip.base; | ||
419 | shift = off * 2; | ||
420 | reg = chip->base + 0x0C; | ||
421 | |||
422 | tmp = __raw_readl(reg); | ||
423 | tmp &= ~(0x3 << shift); | ||
424 | tmp |= drvstr << shift; | ||
425 | |||
426 | __raw_writel(tmp, reg); | ||
427 | |||
428 | return 0; | ||
429 | } | ||
430 | EXPORT_SYMBOL(s5p_gpio_set_drvstr); | ||
431 | #endif /* CONFIG_S5P_GPIO_DRVSTR */ | ||
diff --git a/arch/arm/plat-samsung/gpio.c b/arch/arm/plat-samsung/gpio.c deleted file mode 100644 index 7743c4b8b2fb..000000000000 --- a/arch/arm/plat-samsung/gpio.c +++ /dev/null | |||
@@ -1,167 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s3c/gpio.c | ||
2 | * | ||
3 | * Copyright 2008 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * http://armlinux.simtec.co.uk/ | ||
6 | * | ||
7 | * S3C series GPIO core | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | #include <linux/kernel.h> | ||
15 | #include <linux/init.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/gpio.h> | ||
18 | #include <linux/spinlock.h> | ||
19 | |||
20 | #include <plat/gpio-core.h> | ||
21 | |||
22 | #ifdef CONFIG_S3C_GPIO_TRACK | ||
23 | struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; | ||
24 | |||
25 | static __init void s3c_gpiolib_track(struct s3c_gpio_chip *chip) | ||
26 | { | ||
27 | unsigned int gpn; | ||
28 | int i; | ||
29 | |||
30 | gpn = chip->chip.base; | ||
31 | for (i = 0; i < chip->chip.ngpio; i++, gpn++) { | ||
32 | BUG_ON(gpn >= ARRAY_SIZE(s3c_gpios)); | ||
33 | s3c_gpios[gpn] = chip; | ||
34 | } | ||
35 | } | ||
36 | #endif /* CONFIG_S3C_GPIO_TRACK */ | ||
37 | |||
38 | /* Default routines for controlling GPIO, based on the original S3C24XX | ||
39 | * GPIO functions which deal with the case where each gpio bank of the | ||
40 | * chip is as following: | ||
41 | * | ||
42 | * base + 0x00: Control register, 2 bits per gpio | ||
43 | * gpio n: 2 bits starting at (2*n) | ||
44 | * 00 = input, 01 = output, others mean special-function | ||
45 | * base + 0x04: Data register, 1 bit per gpio | ||
46 | * bit n: data bit n | ||
47 | */ | ||
48 | |||
49 | static int s3c_gpiolib_input(struct gpio_chip *chip, unsigned offset) | ||
50 | { | ||
51 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
52 | void __iomem *base = ourchip->base; | ||
53 | unsigned long flags; | ||
54 | unsigned long con; | ||
55 | |||
56 | s3c_gpio_lock(ourchip, flags); | ||
57 | |||
58 | con = __raw_readl(base + 0x00); | ||
59 | con &= ~(3 << (offset * 2)); | ||
60 | |||
61 | __raw_writel(con, base + 0x00); | ||
62 | |||
63 | s3c_gpio_unlock(ourchip, flags); | ||
64 | return 0; | ||
65 | } | ||
66 | |||
67 | static int s3c_gpiolib_output(struct gpio_chip *chip, | ||
68 | unsigned offset, int value) | ||
69 | { | ||
70 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
71 | void __iomem *base = ourchip->base; | ||
72 | unsigned long flags; | ||
73 | unsigned long dat; | ||
74 | unsigned long con; | ||
75 | |||
76 | s3c_gpio_lock(ourchip, flags); | ||
77 | |||
78 | dat = __raw_readl(base + 0x04); | ||
79 | dat &= ~(1 << offset); | ||
80 | if (value) | ||
81 | dat |= 1 << offset; | ||
82 | __raw_writel(dat, base + 0x04); | ||
83 | |||
84 | con = __raw_readl(base + 0x00); | ||
85 | con &= ~(3 << (offset * 2)); | ||
86 | con |= 1 << (offset * 2); | ||
87 | |||
88 | __raw_writel(con, base + 0x00); | ||
89 | __raw_writel(dat, base + 0x04); | ||
90 | |||
91 | s3c_gpio_unlock(ourchip, flags); | ||
92 | return 0; | ||
93 | } | ||
94 | |||
95 | static void s3c_gpiolib_set(struct gpio_chip *chip, | ||
96 | unsigned offset, int value) | ||
97 | { | ||
98 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
99 | void __iomem *base = ourchip->base; | ||
100 | unsigned long flags; | ||
101 | unsigned long dat; | ||
102 | |||
103 | s3c_gpio_lock(ourchip, flags); | ||
104 | |||
105 | dat = __raw_readl(base + 0x04); | ||
106 | dat &= ~(1 << offset); | ||
107 | if (value) | ||
108 | dat |= 1 << offset; | ||
109 | __raw_writel(dat, base + 0x04); | ||
110 | |||
111 | s3c_gpio_unlock(ourchip, flags); | ||
112 | } | ||
113 | |||
114 | static int s3c_gpiolib_get(struct gpio_chip *chip, unsigned offset) | ||
115 | { | ||
116 | struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip); | ||
117 | unsigned long val; | ||
118 | |||
119 | val = __raw_readl(ourchip->base + 0x04); | ||
120 | val >>= offset; | ||
121 | val &= 1; | ||
122 | |||
123 | return val; | ||
124 | } | ||
125 | |||
126 | __init void s3c_gpiolib_add(struct s3c_gpio_chip *chip) | ||
127 | { | ||
128 | struct gpio_chip *gc = &chip->chip; | ||
129 | int ret; | ||
130 | |||
131 | BUG_ON(!chip->base); | ||
132 | BUG_ON(!gc->label); | ||
133 | BUG_ON(!gc->ngpio); | ||
134 | |||
135 | spin_lock_init(&chip->lock); | ||
136 | |||
137 | if (!gc->direction_input) | ||
138 | gc->direction_input = s3c_gpiolib_input; | ||
139 | if (!gc->direction_output) | ||
140 | gc->direction_output = s3c_gpiolib_output; | ||
141 | if (!gc->set) | ||
142 | gc->set = s3c_gpiolib_set; | ||
143 | if (!gc->get) | ||
144 | gc->get = s3c_gpiolib_get; | ||
145 | |||
146 | #ifdef CONFIG_PM | ||
147 | if (chip->pm != NULL) { | ||
148 | if (!chip->pm->save || !chip->pm->resume) | ||
149 | printk(KERN_ERR "gpio: %s has missing PM functions\n", | ||
150 | gc->label); | ||
151 | } else | ||
152 | printk(KERN_ERR "gpio: %s has no PM function\n", gc->label); | ||
153 | #endif | ||
154 | |||
155 | /* gpiochip_add() prints own failure message on error. */ | ||
156 | ret = gpiochip_add(gc); | ||
157 | if (ret >= 0) | ||
158 | s3c_gpiolib_track(chip); | ||
159 | } | ||
160 | |||
161 | int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) | ||
162 | { | ||
163 | struct s3c_gpio_chip *s3c_chip = container_of(chip, | ||
164 | struct s3c_gpio_chip, chip); | ||
165 | |||
166 | return s3c_chip->irq_base + offset; | ||
167 | } | ||
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h index 9a4e53d52967..a181d7ce81cf 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h | |||
@@ -1,11 +1,11 @@ | |||
1 | /* linux/arch/arm/plat-s3c/include/plat/gpio-cfg-helper.h | 1 | /* linux/arch/arm/plat-samsung/include/plat/gpio-cfg-helper.h |
2 | * | 2 | * |
3 | * Copyright 2008 Openmoko, Inc. | 3 | * Copyright 2008 Openmoko, Inc. |
4 | * Copyright 2008 Simtec Electronics | 4 | * Copyright 2008 Simtec Electronics |
5 | * http://armlinux.simtec.co.uk/ | 5 | * http://armlinux.simtec.co.uk/ |
6 | * Ben Dooks <ben@simtec.co.uk> | 6 | * Ben Dooks <ben@simtec.co.uk> |
7 | * | 7 | * |
8 | * S3C Platform - GPIO pin configuration helper definitions | 8 | * Samsung Platform - GPIO pin configuration helper definitions |
9 | * | 9 | * |
10 | * This program is free software; you can redistribute it and/or modify | 10 | * This program is free software; you can redistribute it and/or modify |
11 | * it under the terms of the GNU General Public License version 2 as | 11 | * it under the terms of the GNU General Public License version 2 as |
@@ -24,120 +24,30 @@ | |||
24 | * by disabling interrupts. | 24 | * by disabling interrupts. |
25 | */ | 25 | */ |
26 | 26 | ||
27 | static inline int s3c_gpio_do_setcfg(struct s3c_gpio_chip *chip, | 27 | static inline int samsung_gpio_do_setcfg(struct samsung_gpio_chip *chip, |
28 | unsigned int off, unsigned int config) | 28 | unsigned int off, unsigned int config) |
29 | { | 29 | { |
30 | return (chip->config->set_config)(chip, off, config); | 30 | return (chip->config->set_config)(chip, off, config); |
31 | } | 31 | } |
32 | 32 | ||
33 | static inline unsigned s3c_gpio_do_getcfg(struct s3c_gpio_chip *chip, | 33 | static inline unsigned samsung_gpio_do_getcfg(struct samsung_gpio_chip *chip, |
34 | unsigned int off) | 34 | unsigned int off) |
35 | { | 35 | { |
36 | return (chip->config->get_config)(chip, off); | 36 | return (chip->config->get_config)(chip, off); |
37 | } | 37 | } |
38 | 38 | ||
39 | static inline int s3c_gpio_do_setpull(struct s3c_gpio_chip *chip, | 39 | static inline int samsung_gpio_do_setpull(struct samsung_gpio_chip *chip, |
40 | unsigned int off, s3c_gpio_pull_t pull) | 40 | unsigned int off, samsung_gpio_pull_t pull) |
41 | { | 41 | { |
42 | return (chip->config->set_pull)(chip, off, pull); | 42 | return (chip->config->set_pull)(chip, off, pull); |
43 | } | 43 | } |
44 | 44 | ||
45 | static inline s3c_gpio_pull_t s3c_gpio_do_getpull(struct s3c_gpio_chip *chip, | 45 | static inline samsung_gpio_pull_t samsung_gpio_do_getpull(struct samsung_gpio_chip *chip, |
46 | unsigned int off) | 46 | unsigned int off) |
47 | { | 47 | { |
48 | return chip->config->get_pull(chip, off); | 48 | return chip->config->get_pull(chip, off); |
49 | } | 49 | } |
50 | 50 | ||
51 | /** | ||
52 | * s3c_gpio_setcfg_s3c24xx - S3C24XX style GPIO configuration. | ||
53 | * @chip: The gpio chip that is being configured. | ||
54 | * @off: The offset for the GPIO being configured. | ||
55 | * @cfg: The configuration value to set. | ||
56 | * | ||
57 | * This helper deal with the GPIO cases where the control register | ||
58 | * has two bits of configuration per gpio, which have the following | ||
59 | * functions: | ||
60 | * 00 = input | ||
61 | * 01 = output | ||
62 | * 1x = special function | ||
63 | */ | ||
64 | extern int s3c_gpio_setcfg_s3c24xx(struct s3c_gpio_chip *chip, | ||
65 | unsigned int off, unsigned int cfg); | ||
66 | |||
67 | /** | ||
68 | * s3c_gpio_getcfg_s3c24xx - S3C24XX style GPIO configuration read. | ||
69 | * @chip: The gpio chip that is being configured. | ||
70 | * @off: The offset for the GPIO being configured. | ||
71 | * | ||
72 | * The reverse of s3c_gpio_setcfg_s3c24xx(). Will return a value whicg | ||
73 | * could be directly passed back to s3c_gpio_setcfg_s3c24xx(), from the | ||
74 | * S3C_GPIO_SPECIAL() macro. | ||
75 | */ | ||
76 | unsigned int s3c_gpio_getcfg_s3c24xx(struct s3c_gpio_chip *chip, | ||
77 | unsigned int off); | ||
78 | |||
79 | /** | ||
80 | * s3c_gpio_setcfg_s3c24xx_a - S3C24XX style GPIO configuration (Bank A) | ||
81 | * @chip: The gpio chip that is being configured. | ||
82 | * @off: The offset for the GPIO being configured. | ||
83 | * @cfg: The configuration value to set. | ||
84 | * | ||
85 | * This helper deal with the GPIO cases where the control register | ||
86 | * has one bit of configuration for the gpio, where setting the bit | ||
87 | * means the pin is in special function mode and unset means output. | ||
88 | */ | ||
89 | extern int s3c_gpio_setcfg_s3c24xx_a(struct s3c_gpio_chip *chip, | ||
90 | unsigned int off, unsigned int cfg); | ||
91 | |||
92 | |||
93 | /** | ||
94 | * s3c_gpio_getcfg_s3c24xx_a - S3C24XX style GPIO configuration read (Bank A) | ||
95 | * @chip: The gpio chip that is being configured. | ||
96 | * @off: The offset for the GPIO being configured. | ||
97 | * | ||
98 | * The reverse of s3c_gpio_setcfg_s3c24xx_a() turning an GPIO into a usable | ||
99 | * GPIO configuration value. | ||
100 | * | ||
101 | * @sa s3c_gpio_getcfg_s3c24xx | ||
102 | * @sa s3c_gpio_getcfg_s3c64xx_4bit | ||
103 | */ | ||
104 | extern unsigned s3c_gpio_getcfg_s3c24xx_a(struct s3c_gpio_chip *chip, | ||
105 | unsigned int off); | ||
106 | |||
107 | /** | ||
108 | * s3c_gpio_setcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config. | ||
109 | * @chip: The gpio chip that is being configured. | ||
110 | * @off: The offset for the GPIO being configured. | ||
111 | * @cfg: The configuration value to set. | ||
112 | * | ||
113 | * This helper deal with the GPIO cases where the control register has 4 bits | ||
114 | * of control per GPIO, generally in the form of: | ||
115 | * 0000 = Input | ||
116 | * 0001 = Output | ||
117 | * others = Special functions (dependent on bank) | ||
118 | * | ||
119 | * Note, since the code to deal with the case where there are two control | ||
120 | * registers instead of one, we do not have a separate set of functions for | ||
121 | * each case. | ||
122 | */ | ||
123 | extern int s3c_gpio_setcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | ||
124 | unsigned int off, unsigned int cfg); | ||
125 | |||
126 | |||
127 | /** | ||
128 | * s3c_gpio_getcfg_s3c64xx_4bit - S3C64XX 4bit single register GPIO config read. | ||
129 | * @chip: The gpio chip that is being configured. | ||
130 | * @off: The offset for the GPIO being configured. | ||
131 | * | ||
132 | * The reverse of s3c_gpio_setcfg_s3c64xx_4bit(), turning a gpio configuration | ||
133 | * register setting into a value the software can use, such as could be passed | ||
134 | * to s3c_gpio_setcfg_s3c64xx_4bit(). | ||
135 | * | ||
136 | * @sa s3c_gpio_getcfg_s3c24xx | ||
137 | */ | ||
138 | extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | ||
139 | unsigned int off); | ||
140 | |||
141 | /* Pull-{up,down} resistor controls. | 51 | /* Pull-{up,down} resistor controls. |
142 | * | 52 | * |
143 | * S3C2410,S3C2440 = Pull-UP, | 53 | * S3C2410,S3C2440 = Pull-UP, |
@@ -147,7 +57,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | |||
147 | */ | 57 | */ |
148 | 58 | ||
149 | /** | 59 | /** |
150 | * s3c_gpio_setpull_1up() - Pull configuration for choice of up or none. | 60 | * s3c24xx_gpio_setpull_1up() - Pull configuration for choice of up or none. |
151 | * @chip: The gpio chip that is being configured. | 61 | * @chip: The gpio chip that is being configured. |
152 | * @off: The offset for the GPIO being configured. | 62 | * @off: The offset for the GPIO being configured. |
153 | * @param: pull: The pull mode being requested. | 63 | * @param: pull: The pull mode being requested. |
@@ -155,11 +65,11 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip, | |||
155 | * This is a helper function for the case where we have GPIOs with one | 65 | * This is a helper function for the case where we have GPIOs with one |
156 | * bit configuring the presence of a pull-up resistor. | 66 | * bit configuring the presence of a pull-up resistor. |
157 | */ | 67 | */ |
158 | extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, | 68 | extern int s3c24xx_gpio_setpull_1up(struct samsung_gpio_chip *chip, |
159 | unsigned int off, s3c_gpio_pull_t pull); | 69 | unsigned int off, samsung_gpio_pull_t pull); |
160 | 70 | ||
161 | /** | 71 | /** |
162 | * s3c_gpio_setpull_1down() - Pull configuration for choice of down or none | 72 | * s3c24xx_gpio_setpull_1down() - Pull configuration for choice of down or none |
163 | * @chip: The gpio chip that is being configured | 73 | * @chip: The gpio chip that is being configured |
164 | * @off: The offset for the GPIO being configured | 74 | * @off: The offset for the GPIO being configured |
165 | * @param: pull: The pull mode being requested | 75 | * @param: pull: The pull mode being requested |
@@ -167,11 +77,13 @@ extern int s3c_gpio_setpull_1up(struct s3c_gpio_chip *chip, | |||
167 | * This is a helper function for the case where we have GPIOs with one | 77 | * This is a helper function for the case where we have GPIOs with one |
168 | * bit configuring the presence of a pull-down resistor. | 78 | * bit configuring the presence of a pull-down resistor. |
169 | */ | 79 | */ |
170 | extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, | 80 | extern int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip, |
171 | unsigned int off, s3c_gpio_pull_t pull); | 81 | unsigned int off, samsung_gpio_pull_t pull); |
172 | 82 | ||
173 | /** | 83 | /** |
174 | * s3c_gpio_setpull_upown() - Pull configuration for choice of up, down or none | 84 | * samsung_gpio_setpull_upown() - Pull configuration for choice of up, |
85 | * down or none | ||
86 | * | ||
175 | * @chip: The gpio chip that is being configured. | 87 | * @chip: The gpio chip that is being configured. |
176 | * @off: The offset for the GPIO being configured. | 88 | * @off: The offset for the GPIO being configured. |
177 | * @param: pull: The pull mode being requested. | 89 | * @param: pull: The pull mode being requested. |
@@ -183,45 +95,46 @@ extern int s3c_gpio_setpull_1down(struct s3c_gpio_chip *chip, | |||
183 | * 01 = Pull-up resistor connected | 95 | * 01 = Pull-up resistor connected |
184 | * 10 = Pull-down resistor connected | 96 | * 10 = Pull-down resistor connected |
185 | */ | 97 | */ |
186 | extern int s3c_gpio_setpull_updown(struct s3c_gpio_chip *chip, | 98 | extern int samsung_gpio_setpull_updown(struct samsung_gpio_chip *chip, |
187 | unsigned int off, s3c_gpio_pull_t pull); | 99 | unsigned int off, samsung_gpio_pull_t pull); |
188 | |||
189 | 100 | ||
190 | /** | 101 | /** |
191 | * s3c_gpio_getpull_updown() - Get configuration for choice of up, down or none | 102 | * samsung_gpio_getpull_updown() - Get configuration for choice of up, |
103 | * down or none | ||
104 | * | ||
192 | * @chip: The gpio chip that the GPIO pin belongs to | 105 | * @chip: The gpio chip that the GPIO pin belongs to |
193 | * @off: The offset to the pin to get the configuration of. | 106 | * @off: The offset to the pin to get the configuration of. |
194 | * | 107 | * |
195 | * This helper function reads the state of the pull-{up,down} resistor for the | 108 | * This helper function reads the state of the pull-{up,down} resistor |
196 | * given GPIO in the same case as s3c_gpio_setpull_upown. | 109 | * for the given GPIO in the same case as samsung_gpio_setpull_upown. |
197 | */ | 110 | */ |
198 | extern s3c_gpio_pull_t s3c_gpio_getpull_updown(struct s3c_gpio_chip *chip, | 111 | extern samsung_gpio_pull_t samsung_gpio_getpull_updown(struct samsung_gpio_chip *chip, |
199 | unsigned int off); | 112 | unsigned int off); |
200 | 113 | ||
201 | /** | 114 | /** |
202 | * s3c_gpio_getpull_1up() - Get configuration for choice of up or none | 115 | * s3c24xx_gpio_getpull_1up() - Get configuration for choice of up or none |
203 | * @chip: The gpio chip that the GPIO pin belongs to | 116 | * @chip: The gpio chip that the GPIO pin belongs to |
204 | * @off: The offset to the pin to get the configuration of. | 117 | * @off: The offset to the pin to get the configuration of. |
205 | * | 118 | * |
206 | * This helper function reads the state of the pull-up resistor for the | 119 | * This helper function reads the state of the pull-up resistor for the |
207 | * given GPIO in the same case as s3c_gpio_setpull_1up. | 120 | * given GPIO in the same case as s3c24xx_gpio_setpull_1up. |
208 | */ | 121 | */ |
209 | extern s3c_gpio_pull_t s3c_gpio_getpull_1up(struct s3c_gpio_chip *chip, | 122 | extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1up(struct samsung_gpio_chip *chip, |
210 | unsigned int off); | 123 | unsigned int off); |
211 | 124 | ||
212 | /** | 125 | /** |
213 | * s3c_gpio_getpull_1down() - Get configuration for choice of down or none | 126 | * s3c24xx_gpio_getpull_1down() - Get configuration for choice of down or none |
214 | * @chip: The gpio chip that the GPIO pin belongs to | 127 | * @chip: The gpio chip that the GPIO pin belongs to |
215 | * @off: The offset to the pin to get the configuration of. | 128 | * @off: The offset to the pin to get the configuration of. |
216 | * | 129 | * |
217 | * This helper function reads the state of the pull-down resistor for the | 130 | * This helper function reads the state of the pull-down resistor for the |
218 | * given GPIO in the same case as s3c_gpio_setpull_1down. | 131 | * given GPIO in the same case as s3c24xx_gpio_setpull_1down. |
219 | */ | 132 | */ |
220 | extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, | 133 | extern samsung_gpio_pull_t s3c24xx_gpio_getpull_1down(struct samsung_gpio_chip *chip, |
221 | unsigned int off); | 134 | unsigned int off); |
222 | 135 | ||
223 | /** | 136 | /** |
224 | * s3c_gpio_setpull_s3c2443() - Pull configuration for s3c2443. | 137 | * s3c2443_gpio_setpull() - Pull configuration for s3c2443. |
225 | * @chip: The gpio chip that is being configured. | 138 | * @chip: The gpio chip that is being configured. |
226 | * @off: The offset for the GPIO being configured. | 139 | * @off: The offset for the GPIO being configured. |
227 | * @param: pull: The pull mode being requested. | 140 | * @param: pull: The pull mode being requested. |
@@ -233,19 +146,18 @@ extern s3c_gpio_pull_t s3c_gpio_getpull_1down(struct s3c_gpio_chip *chip, | |||
233 | * 10 = Pull-down resistor connected | 146 | * 10 = Pull-down resistor connected |
234 | * x1 = No pull up resistor | 147 | * x1 = No pull up resistor |
235 | */ | 148 | */ |
236 | extern int s3c_gpio_setpull_s3c2443(struct s3c_gpio_chip *chip, | 149 | extern int s3c2443_gpio_setpull(struct samsung_gpio_chip *chip, |
237 | unsigned int off, s3c_gpio_pull_t pull); | 150 | unsigned int off, samsung_gpio_pull_t pull); |
238 | 151 | ||
239 | /** | 152 | /** |
240 | * s3c_gpio_getpull_s3c2443() - Get configuration for s3c2443 pull resistors | 153 | * s3c2443_gpio_getpull() - Get configuration for s3c2443 pull resistors |
241 | * @chip: The gpio chip that the GPIO pin belongs to. | 154 | * @chip: The gpio chip that the GPIO pin belongs to. |
242 | * @off: The offset to the pin to get the configuration of. | 155 | * @off: The offset to the pin to get the configuration of. |
243 | * | 156 | * |
244 | * This helper function reads the state of the pull-{up,down} resistor for the | 157 | * This helper function reads the state of the pull-{up,down} resistor for the |
245 | * given GPIO in the same case as s3c_gpio_setpull_upown. | 158 | * given GPIO in the same case as samsung_gpio_setpull_upown. |
246 | */ | 159 | */ |
247 | extern s3c_gpio_pull_t s3c_gpio_getpull_s3c2443(struct s3c_gpio_chip *chip, | 160 | extern samsung_gpio_pull_t s3c2443_gpio_getpull(struct samsung_gpio_chip *chip, |
248 | unsigned int off); | 161 | unsigned int off); |
249 | 162 | ||
250 | #endif /* __PLAT_GPIO_CFG_HELPERS_H */ | 163 | #endif /* __PLAT_GPIO_CFG_HELPERS_H */ |
251 | |||
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg.h b/arch/arm/plat-samsung/include/plat/gpio-cfg.h index 1762dcb4cb9e..d48245bb02b3 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-cfg.h +++ b/arch/arm/plat-samsung/include/plat/gpio-cfg.h | |||
@@ -24,14 +24,14 @@ | |||
24 | #ifndef __PLAT_GPIO_CFG_H | 24 | #ifndef __PLAT_GPIO_CFG_H |
25 | #define __PLAT_GPIO_CFG_H __FILE__ | 25 | #define __PLAT_GPIO_CFG_H __FILE__ |
26 | 26 | ||
27 | typedef unsigned int __bitwise__ s3c_gpio_pull_t; | 27 | typedef unsigned int __bitwise__ samsung_gpio_pull_t; |
28 | typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; | 28 | typedef unsigned int __bitwise__ s5p_gpio_drvstr_t; |
29 | 29 | ||
30 | /* forward declaration if gpio-core.h hasn't been included */ | 30 | /* forward declaration if gpio-core.h hasn't been included */ |
31 | struct s3c_gpio_chip; | 31 | struct samsung_gpio_chip; |
32 | 32 | ||
33 | /** | 33 | /** |
34 | * struct s3c_gpio_cfg GPIO configuration | 34 | * struct samsung_gpio_cfg GPIO configuration |
35 | * @cfg_eint: Configuration setting when used for external interrupt source | 35 | * @cfg_eint: Configuration setting when used for external interrupt source |
36 | * @get_pull: Read the current pull configuration for the GPIO | 36 | * @get_pull: Read the current pull configuration for the GPIO |
37 | * @set_pull: Set the current pull configuraiton for the GPIO | 37 | * @set_pull: Set the current pull configuraiton for the GPIO |
@@ -44,20 +44,20 @@ struct s3c_gpio_chip; | |||
44 | * per-bank configuration information that other systems such as the | 44 | * per-bank configuration information that other systems such as the |
45 | * external interrupt code will need. | 45 | * external interrupt code will need. |
46 | * | 46 | * |
47 | * @sa s3c_gpio_cfgpin | 47 | * @sa samsung_gpio_cfgpin |
48 | * @sa s3c_gpio_getcfg | 48 | * @sa s3c_gpio_getcfg |
49 | * @sa s3c_gpio_setpull | 49 | * @sa s3c_gpio_setpull |
50 | * @sa s3c_gpio_getpull | 50 | * @sa s3c_gpio_getpull |
51 | */ | 51 | */ |
52 | struct s3c_gpio_cfg { | 52 | struct samsung_gpio_cfg { |
53 | unsigned int cfg_eint; | 53 | unsigned int cfg_eint; |
54 | 54 | ||
55 | s3c_gpio_pull_t (*get_pull)(struct s3c_gpio_chip *chip, unsigned offs); | 55 | samsung_gpio_pull_t (*get_pull)(struct samsung_gpio_chip *chip, unsigned offs); |
56 | int (*set_pull)(struct s3c_gpio_chip *chip, unsigned offs, | 56 | int (*set_pull)(struct samsung_gpio_chip *chip, unsigned offs, |
57 | s3c_gpio_pull_t pull); | 57 | samsung_gpio_pull_t pull); |
58 | 58 | ||
59 | unsigned (*get_config)(struct s3c_gpio_chip *chip, unsigned offs); | 59 | unsigned (*get_config)(struct samsung_gpio_chip *chip, unsigned offs); |
60 | int (*set_config)(struct s3c_gpio_chip *chip, unsigned offs, | 60 | int (*set_config)(struct samsung_gpio_chip *chip, unsigned offs, |
61 | unsigned config); | 61 | unsigned config); |
62 | }; | 62 | }; |
63 | 63 | ||
@@ -69,7 +69,7 @@ struct s3c_gpio_cfg { | |||
69 | #define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) | 69 | #define S3C_GPIO_OUTPUT (S3C_GPIO_SPECIAL(1)) |
70 | #define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) | 70 | #define S3C_GPIO_SFN(x) (S3C_GPIO_SPECIAL(x)) |
71 | 71 | ||
72 | #define s3c_gpio_is_cfg_special(_cfg) \ | 72 | #define samsung_gpio_is_cfg_special(_cfg) \ |
73 | (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) | 73 | (((_cfg) & S3C_GPIO_SPECIAL_MARK) == S3C_GPIO_SPECIAL_MARK) |
74 | 74 | ||
75 | /** | 75 | /** |
@@ -128,9 +128,9 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, | |||
128 | * up or down settings, and it may be dependent on the chip that is being | 128 | * up or down settings, and it may be dependent on the chip that is being |
129 | * used to whether the particular mode is available. | 129 | * used to whether the particular mode is available. |
130 | */ | 130 | */ |
131 | #define S3C_GPIO_PULL_NONE ((__force s3c_gpio_pull_t)0x00) | 131 | #define S3C_GPIO_PULL_NONE ((__force samsung_gpio_pull_t)0x00) |
132 | #define S3C_GPIO_PULL_DOWN ((__force s3c_gpio_pull_t)0x01) | 132 | #define S3C_GPIO_PULL_DOWN ((__force samsung_gpio_pull_t)0x01) |
133 | #define S3C_GPIO_PULL_UP ((__force s3c_gpio_pull_t)0x02) | 133 | #define S3C_GPIO_PULL_UP ((__force samsung_gpio_pull_t)0x02) |
134 | 134 | ||
135 | /** | 135 | /** |
136 | * s3c_gpio_setpull() - set the state of a gpio pin pull resistor | 136 | * s3c_gpio_setpull() - set the state of a gpio pin pull resistor |
@@ -143,7 +143,7 @@ extern int s3c_gpio_cfgpin_range(unsigned int start, unsigned int nr, | |||
143 | * | 143 | * |
144 | * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. | 144 | * @pull is one of S3C_GPIO_PULL_NONE, S3C_GPIO_PULL_DOWN or S3C_GPIO_PULL_UP. |
145 | */ | 145 | */ |
146 | extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); | 146 | extern int s3c_gpio_setpull(unsigned int pin, samsung_gpio_pull_t pull); |
147 | 147 | ||
148 | /** | 148 | /** |
149 | * s3c_gpio_getpull() - get the pull resistor state of a gpio pin | 149 | * s3c_gpio_getpull() - get the pull resistor state of a gpio pin |
@@ -151,7 +151,7 @@ extern int s3c_gpio_setpull(unsigned int pin, s3c_gpio_pull_t pull); | |||
151 | * | 151 | * |
152 | * Read the pull resistor value for the specified pin. | 152 | * Read the pull resistor value for the specified pin. |
153 | */ | 153 | */ |
154 | extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); | 154 | extern samsung_gpio_pull_t s3c_gpio_getpull(unsigned int pin); |
155 | 155 | ||
156 | /* configure `all` aspects of an gpio */ | 156 | /* configure `all` aspects of an gpio */ |
157 | 157 | ||
@@ -170,7 +170,7 @@ extern s3c_gpio_pull_t s3c_gpio_getpull(unsigned int pin); | |||
170 | * @sa s3c_gpio_cfgpin_range | 170 | * @sa s3c_gpio_cfgpin_range |
171 | */ | 171 | */ |
172 | extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, | 172 | extern int s3c_gpio_cfgall_range(unsigned int start, unsigned int nr, |
173 | unsigned int cfg, s3c_gpio_pull_t pull); | 173 | unsigned int cfg, samsung_gpio_pull_t pull); |
174 | 174 | ||
175 | static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, | 175 | static inline int s3c_gpio_cfgrange_nopull(unsigned int pin, unsigned int size, |
176 | unsigned int cfg) | 176 | unsigned int cfg) |
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index 8cad4cf19c3c..1fe6917f6a2a 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h | |||
@@ -25,22 +25,22 @@ | |||
25 | * specific code. | 25 | * specific code. |
26 | */ | 26 | */ |
27 | 27 | ||
28 | struct s3c_gpio_chip; | 28 | struct samsung_gpio_chip; |
29 | 29 | ||
30 | /** | 30 | /** |
31 | * struct s3c_gpio_pm - power management (suspend/resume) information | 31 | * struct samsung_gpio_pm - power management (suspend/resume) information |
32 | * @save: Routine to save the state of the GPIO block | 32 | * @save: Routine to save the state of the GPIO block |
33 | * @resume: Routine to resume the GPIO block. | 33 | * @resume: Routine to resume the GPIO block. |
34 | */ | 34 | */ |
35 | struct s3c_gpio_pm { | 35 | struct samsung_gpio_pm { |
36 | void (*save)(struct s3c_gpio_chip *chip); | 36 | void (*save)(struct samsung_gpio_chip *chip); |
37 | void (*resume)(struct s3c_gpio_chip *chip); | 37 | void (*resume)(struct samsung_gpio_chip *chip); |
38 | }; | 38 | }; |
39 | 39 | ||
40 | struct s3c_gpio_cfg; | 40 | struct samsung_gpio_cfg; |
41 | 41 | ||
42 | /** | 42 | /** |
43 | * struct s3c_gpio_chip - wrapper for specific implementation of gpio | 43 | * struct samsung_gpio_chip - wrapper for specific implementation of gpio |
44 | * @chip: The chip structure to be exported via gpiolib. | 44 | * @chip: The chip structure to be exported via gpiolib. |
45 | * @base: The base pointer to the gpio configuration registers. | 45 | * @base: The base pointer to the gpio configuration registers. |
46 | * @group: The group register number for gpio interrupt support. | 46 | * @group: The group register number for gpio interrupt support. |
@@ -60,10 +60,10 @@ struct s3c_gpio_cfg; | |||
60 | * CPU cores trying to get one lock for different GPIO banks, where each | 60 | * CPU cores trying to get one lock for different GPIO banks, where each |
61 | * bank of GPIO has its own register space and configuration registers. | 61 | * bank of GPIO has its own register space and configuration registers. |
62 | */ | 62 | */ |
63 | struct s3c_gpio_chip { | 63 | struct samsung_gpio_chip { |
64 | struct gpio_chip chip; | 64 | struct gpio_chip chip; |
65 | struct s3c_gpio_cfg *config; | 65 | struct samsung_gpio_cfg *config; |
66 | struct s3c_gpio_pm *pm; | 66 | struct samsung_gpio_pm *pm; |
67 | void __iomem *base; | 67 | void __iomem *base; |
68 | int irq_base; | 68 | int irq_base; |
69 | int group; | 69 | int group; |
@@ -73,58 +73,11 @@ struct s3c_gpio_chip { | |||
73 | #endif | 73 | #endif |
74 | }; | 74 | }; |
75 | 75 | ||
76 | static inline struct s3c_gpio_chip *to_s3c_gpio(struct gpio_chip *gpc) | 76 | static inline struct samsung_gpio_chip *to_samsung_gpio(struct gpio_chip *gpc) |
77 | { | 77 | { |
78 | return container_of(gpc, struct s3c_gpio_chip, chip); | 78 | return container_of(gpc, struct samsung_gpio_chip, chip); |
79 | } | 79 | } |
80 | 80 | ||
81 | /** s3c_gpiolib_add() - add the s3c specific version of a gpio_chip. | ||
82 | * @chip: The chip to register | ||
83 | * | ||
84 | * This is a wrapper to gpiochip_add() that takes our specific gpio chip | ||
85 | * information and makes the necessary alterations for the platform and | ||
86 | * notes the information for use with the configuration systems and any | ||
87 | * other parts of the system. | ||
88 | */ | ||
89 | extern void s3c_gpiolib_add(struct s3c_gpio_chip *chip); | ||
90 | |||
91 | /* CONFIG_S3C_GPIO_TRACK enables the tracking of the s3c specific gpios | ||
92 | * for use with the configuration calls, and other parts of the s3c gpiolib | ||
93 | * support code. | ||
94 | * | ||
95 | * Not all s3c support code will need this, as some configurations of cpu | ||
96 | * may only support one or two different configuration options and have an | ||
97 | * easy gpio to s3c_gpio_chip mapping function. If this is the case, then | ||
98 | * the machine support file should provide its own s3c_gpiolib_getchip() | ||
99 | * and any other necessary functions. | ||
100 | */ | ||
101 | |||
102 | /** | ||
103 | * samsung_gpiolib_add_4bit_chips - 4bit single register GPIO config. | ||
104 | * @chip: The gpio chip that is being configured. | ||
105 | * @nr_chips: The no of chips (gpio ports) for the GPIO being configured. | ||
106 | * | ||
107 | * This helper deal with the GPIO cases where the control register has 4 bits | ||
108 | * of control per GPIO, generally in the form of: | ||
109 | * 0000 = Input | ||
110 | * 0001 = Output | ||
111 | * others = Special functions (dependent on bank) | ||
112 | * | ||
113 | * Note, since the code to deal with the case where there are two control | ||
114 | * registers instead of one, we do not have a separate set of function | ||
115 | * (samsung_gpiolib_add_4bit2_chips)for each case. | ||
116 | */ | ||
117 | extern void samsung_gpiolib_add_4bit_chips(struct s3c_gpio_chip *chip, | ||
118 | int nr_chips); | ||
119 | extern void samsung_gpiolib_add_4bit2_chips(struct s3c_gpio_chip *chip, | ||
120 | int nr_chips); | ||
121 | extern void samsung_gpiolib_add_2bit_chips(struct s3c_gpio_chip *chip, | ||
122 | int nr_chips); | ||
123 | |||
124 | extern void samsung_gpiolib_add_4bit(struct s3c_gpio_chip *chip); | ||
125 | extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); | ||
126 | |||
127 | |||
128 | /** | 81 | /** |
129 | * samsung_gpiolib_to_irq - convert gpio pin to irq number | 82 | * samsung_gpiolib_to_irq - convert gpio pin to irq number |
130 | * @chip: The gpio chip that the pin belongs to. | 83 | * @chip: The gpio chip that the pin belongs to. |
@@ -136,36 +89,36 @@ extern void samsung_gpiolib_add_4bit2(struct s3c_gpio_chip *chip); | |||
136 | extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); | 89 | extern int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset); |
137 | 90 | ||
138 | /* exported for core SoC support to change */ | 91 | /* exported for core SoC support to change */ |
139 | extern struct s3c_gpio_cfg s3c24xx_gpiocfg_default; | 92 | extern struct samsung_gpio_cfg s3c24xx_gpiocfg_default; |
140 | 93 | ||
141 | #ifdef CONFIG_S3C_GPIO_TRACK | 94 | #ifdef CONFIG_S3C_GPIO_TRACK |
142 | extern struct s3c_gpio_chip *s3c_gpios[S3C_GPIO_END]; | 95 | extern struct samsung_gpio_chip *s3c_gpios[S3C_GPIO_END]; |
143 | 96 | ||
144 | static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int chip) | 97 | static inline struct samsung_gpio_chip *samsung_gpiolib_getchip(unsigned int chip) |
145 | { | 98 | { |
146 | return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; | 99 | return (chip < S3C_GPIO_END) ? s3c_gpios[chip] : NULL; |
147 | } | 100 | } |
148 | #else | 101 | #else |
149 | /* machine specific code should provide s3c_gpiolib_getchip */ | 102 | /* machine specific code should provide samsung_gpiolib_getchip */ |
150 | 103 | ||
151 | #include <mach/gpio-track.h> | 104 | #include <mach/gpio-track.h> |
152 | 105 | ||
153 | static inline void s3c_gpiolib_track(struct s3c_gpio_chip *chip) { } | 106 | static inline void s3c_gpiolib_track(struct samsung_gpio_chip *chip) { } |
154 | #endif | 107 | #endif |
155 | 108 | ||
156 | #ifdef CONFIG_PM | 109 | #ifdef CONFIG_PM |
157 | extern struct s3c_gpio_pm s3c_gpio_pm_1bit; | 110 | extern struct samsung_gpio_pm samsung_gpio_pm_1bit; |
158 | extern struct s3c_gpio_pm s3c_gpio_pm_2bit; | 111 | extern struct samsung_gpio_pm samsung_gpio_pm_2bit; |
159 | extern struct s3c_gpio_pm s3c_gpio_pm_4bit; | 112 | extern struct samsung_gpio_pm samsung_gpio_pm_4bit; |
160 | #define __gpio_pm(x) x | 113 | #define __gpio_pm(x) x |
161 | #else | 114 | #else |
162 | #define s3c_gpio_pm_1bit NULL | 115 | #define samsung_gpio_pm_1bit NULL |
163 | #define s3c_gpio_pm_2bit NULL | 116 | #define samsung_gpio_pm_2bit NULL |
164 | #define s3c_gpio_pm_4bit NULL | 117 | #define samsung_gpio_pm_4bit NULL |
165 | #define __gpio_pm(x) NULL | 118 | #define __gpio_pm(x) NULL |
166 | 119 | ||
167 | #endif /* CONFIG_PM */ | 120 | #endif /* CONFIG_PM */ |
168 | 121 | ||
169 | /* locking wrappers to deal with multiple access to the same gpio bank */ | 122 | /* locking wrappers to deal with multiple access to the same gpio bank */ |
170 | #define s3c_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) | 123 | #define samsung_gpio_lock(_oc, _fl) spin_lock_irqsave(&(_oc)->lock, _fl) |
171 | #define s3c_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) | 124 | #define samsung_gpio_unlock(_oc, _fl) spin_unlock_irqrestore(&(_oc)->lock, _fl) |
diff --git a/arch/arm/plat-samsung/include/plat/gpio-fns.h b/arch/arm/plat-samsung/include/plat/gpio-fns.h new file mode 100644 index 000000000000..bab139201761 --- /dev/null +++ b/arch/arm/plat-samsung/include/plat/gpio-fns.h | |||
@@ -0,0 +1,98 @@ | |||
1 | /* arch/arm/mach-s3c2410/include/mach/gpio-fns.h | ||
2 | * | ||
3 | * Copyright (c) 2003-2009 Simtec Electronics | ||
4 | * Ben Dooks <ben@simtec.co.uk> | ||
5 | * | ||
6 | * S3C2410 - hardware | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __MACH_GPIO_FNS_H | ||
14 | #define __MACH_GPIO_FNS_H __FILE__ | ||
15 | |||
16 | /* These functions are in the to-be-removed category and it is strongly | ||
17 | * encouraged not to use these in new code. They will be marked deprecated | ||
18 | * very soon. | ||
19 | * | ||
20 | * Most of the functionality can be either replaced by the gpiocfg calls | ||
21 | * for the s3c platform or by the generic GPIOlib API. | ||
22 | * | ||
23 | * As of 2.6.35-rc, these will be removed, with the few drivers using them | ||
24 | * either replaced or given a wrapper until the calls can be removed. | ||
25 | */ | ||
26 | |||
27 | #include <plat/gpio-cfg.h> | ||
28 | |||
29 | static inline void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int cfg) | ||
30 | { | ||
31 | /* 1:1 mapping between cfgpin and setcfg calls at the moment */ | ||
32 | s3c_gpio_cfgpin(pin, cfg); | ||
33 | } | ||
34 | |||
35 | /* external functions for GPIO support | ||
36 | * | ||
37 | * These allow various different clients to access the same GPIO | ||
38 | * registers without conflicting. If your driver only owns the entire | ||
39 | * GPIO register, then it is safe to ioremap/__raw_{read|write} to it. | ||
40 | */ | ||
41 | |||
42 | extern unsigned int s3c2410_gpio_getcfg(unsigned int pin); | ||
43 | |||
44 | /* s3c2410_gpio_getirq | ||
45 | * | ||
46 | * turn the given pin number into the corresponding IRQ number | ||
47 | * | ||
48 | * returns: | ||
49 | * < 0 = no interrupt for this pin | ||
50 | * >=0 = interrupt number for the pin | ||
51 | */ | ||
52 | |||
53 | extern int s3c2410_gpio_getirq(unsigned int pin); | ||
54 | |||
55 | /* s3c2410_gpio_irqfilter | ||
56 | * | ||
57 | * set the irq filtering on the given pin | ||
58 | * | ||
59 | * on = 0 => disable filtering | ||
60 | * 1 => enable filtering | ||
61 | * | ||
62 | * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with | ||
63 | * width of filter (0 through 63) | ||
64 | * | ||
65 | * | ||
66 | */ | ||
67 | |||
68 | extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on, | ||
69 | unsigned int config); | ||
70 | |||
71 | /* s3c2410_gpio_pullup | ||
72 | * | ||
73 | * This call should be replaced with s3c_gpio_setpull(). | ||
74 | * | ||
75 | * As a note, there is currently no distinction between pull-up and pull-down | ||
76 | * in the s3c24xx series devices with only an on/off configuration. | ||
77 | */ | ||
78 | |||
79 | /* s3c2410_gpio_pullup | ||
80 | * | ||
81 | * configure the pull-up control on the given pin | ||
82 | * | ||
83 | * to = 1 => disable the pull-up | ||
84 | * 0 => enable the pull-up | ||
85 | * | ||
86 | * eg; | ||
87 | * | ||
88 | * s3c2410_gpio_pullup(S3C2410_GPB(0), 0); | ||
89 | * s3c2410_gpio_pullup(S3C2410_GPE(8), 0); | ||
90 | */ | ||
91 | |||
92 | extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to); | ||
93 | |||
94 | extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to); | ||
95 | |||
96 | extern unsigned int s3c2410_gpio_getpin(unsigned int pin); | ||
97 | |||
98 | #endif /* __MACH_GPIO_FNS_H */ | ||
diff --git a/arch/arm/plat-samsung/include/plat/pm.h b/arch/arm/plat-samsung/include/plat/pm.h index f6749916d194..dcf68709f9cf 100644 --- a/arch/arm/plat-samsung/include/plat/pm.h +++ b/arch/arm/plat-samsung/include/plat/pm.h | |||
@@ -165,20 +165,20 @@ extern void s3c_pm_check_store(void); | |||
165 | extern void s3c_pm_configure_extint(void); | 165 | extern void s3c_pm_configure_extint(void); |
166 | 166 | ||
167 | /** | 167 | /** |
168 | * s3c_pm_restore_gpios() - restore the state of the gpios after sleep. | 168 | * samsung_pm_restore_gpios() - restore the state of the gpios after sleep. |
169 | * | 169 | * |
170 | * Restore the state of the GPIO pins after sleep, which may involve ensuring | 170 | * Restore the state of the GPIO pins after sleep, which may involve ensuring |
171 | * that we do not glitch the state of the pins from that the bootloader's | 171 | * that we do not glitch the state of the pins from that the bootloader's |
172 | * resume code has done. | 172 | * resume code has done. |
173 | */ | 173 | */ |
174 | extern void s3c_pm_restore_gpios(void); | 174 | extern void samsung_pm_restore_gpios(void); |
175 | 175 | ||
176 | /** | 176 | /** |
177 | * s3c_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. | 177 | * samsung_pm_save_gpios() - save the state of the GPIOs for restoring after sleep. |
178 | * | 178 | * |
179 | * Save the GPIO states for resotration on resume. See s3c_pm_restore_gpios(). | 179 | * Save the GPIO states for resotration on resume. See samsung_pm_restore_gpios(). |
180 | */ | 180 | */ |
181 | extern void s3c_pm_save_gpios(void); | 181 | extern void samsung_pm_save_gpios(void); |
182 | 182 | ||
183 | extern void s3c_pm_save_core(void); | 183 | extern void s3c_pm_save_core(void); |
184 | extern void s3c_pm_restore_core(void); | 184 | extern void s3c_pm_restore_core(void); |
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index 96528200eb79..4be016eaa6db 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c | |||
@@ -28,13 +28,13 @@ | |||
28 | #define OFFS_DAT (0x04) | 28 | #define OFFS_DAT (0x04) |
29 | #define OFFS_UP (0x08) | 29 | #define OFFS_UP (0x08) |
30 | 30 | ||
31 | static void s3c_gpio_pm_1bit_save(struct s3c_gpio_chip *chip) | 31 | static void samsung_gpio_pm_1bit_save(struct samsung_gpio_chip *chip) |
32 | { | 32 | { |
33 | chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); | 33 | chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); |
34 | chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); | 34 | chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); |
35 | } | 35 | } |
36 | 36 | ||
37 | static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip) | 37 | static void samsung_gpio_pm_1bit_resume(struct samsung_gpio_chip *chip) |
38 | { | 38 | { |
39 | void __iomem *base = chip->base; | 39 | void __iomem *base = chip->base; |
40 | u32 old_gpcon = __raw_readl(base + OFFS_CON); | 40 | u32 old_gpcon = __raw_readl(base + OFFS_CON); |
@@ -60,12 +60,12 @@ static void s3c_gpio_pm_1bit_resume(struct s3c_gpio_chip *chip) | |||
60 | chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); | 60 | chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); |
61 | } | 61 | } |
62 | 62 | ||
63 | struct s3c_gpio_pm s3c_gpio_pm_1bit = { | 63 | struct samsung_gpio_pm samsung_gpio_pm_1bit = { |
64 | .save = s3c_gpio_pm_1bit_save, | 64 | .save = samsung_gpio_pm_1bit_save, |
65 | .resume = s3c_gpio_pm_1bit_resume, | 65 | .resume = samsung_gpio_pm_1bit_resume, |
66 | }; | 66 | }; |
67 | 67 | ||
68 | static void s3c_gpio_pm_2bit_save(struct s3c_gpio_chip *chip) | 68 | static void samsung_gpio_pm_2bit_save(struct samsung_gpio_chip *chip) |
69 | { | 69 | { |
70 | chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); | 70 | chip->pm_save[0] = __raw_readl(chip->base + OFFS_CON); |
71 | chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); | 71 | chip->pm_save[1] = __raw_readl(chip->base + OFFS_DAT); |
@@ -95,7 +95,7 @@ static inline int is_out(unsigned long con) | |||
95 | } | 95 | } |
96 | 96 | ||
97 | /** | 97 | /** |
98 | * s3c_gpio_pm_2bit_resume() - restore the given GPIO bank | 98 | * samsung_gpio_pm_2bit_resume() - restore the given GPIO bank |
99 | * @chip: The chip information to resume. | 99 | * @chip: The chip information to resume. |
100 | * | 100 | * |
101 | * Restore one of the GPIO banks that was saved during suspend. This is | 101 | * Restore one of the GPIO banks that was saved during suspend. This is |
@@ -121,7 +121,7 @@ static inline int is_out(unsigned long con) | |||
121 | * [1] this assumes that writing to a pin DAT whilst in SFN will set the | 121 | * [1] this assumes that writing to a pin DAT whilst in SFN will set the |
122 | * state for when it is next output. | 122 | * state for when it is next output. |
123 | */ | 123 | */ |
124 | static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip) | 124 | static void samsung_gpio_pm_2bit_resume(struct samsung_gpio_chip *chip) |
125 | { | 125 | { |
126 | void __iomem *base = chip->base; | 126 | void __iomem *base = chip->base; |
127 | u32 old_gpcon = __raw_readl(base + OFFS_CON); | 127 | u32 old_gpcon = __raw_readl(base + OFFS_CON); |
@@ -187,13 +187,13 @@ static void s3c_gpio_pm_2bit_resume(struct s3c_gpio_chip *chip) | |||
187 | chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); | 187 | chip->chip.label, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat); |
188 | } | 188 | } |
189 | 189 | ||
190 | struct s3c_gpio_pm s3c_gpio_pm_2bit = { | 190 | struct samsung_gpio_pm samsung_gpio_pm_2bit = { |
191 | .save = s3c_gpio_pm_2bit_save, | 191 | .save = samsung_gpio_pm_2bit_save, |
192 | .resume = s3c_gpio_pm_2bit_resume, | 192 | .resume = samsung_gpio_pm_2bit_resume, |
193 | }; | 193 | }; |
194 | 194 | ||
195 | #if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) | 195 | #if defined(CONFIG_ARCH_S3C64XX) || defined(CONFIG_PLAT_S5P) |
196 | static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) | 196 | static void samsung_gpio_pm_4bit_save(struct samsung_gpio_chip *chip) |
197 | { | 197 | { |
198 | chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); | 198 | chip->pm_save[1] = __raw_readl(chip->base + OFFS_CON); |
199 | chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); | 199 | chip->pm_save[2] = __raw_readl(chip->base + OFFS_DAT); |
@@ -203,7 +203,7 @@ static void s3c_gpio_pm_4bit_save(struct s3c_gpio_chip *chip) | |||
203 | chip->pm_save[0] = __raw_readl(chip->base - 4); | 203 | chip->pm_save[0] = __raw_readl(chip->base - 4); |
204 | } | 204 | } |
205 | 205 | ||
206 | static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) | 206 | static u32 samsung_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) |
207 | { | 207 | { |
208 | u32 old, new, mask; | 208 | u32 old, new, mask; |
209 | u32 change_mask = 0x0; | 209 | u32 change_mask = 0x0; |
@@ -242,14 +242,14 @@ static u32 s3c_gpio_pm_4bit_mask(u32 old_gpcon, u32 gps_gpcon) | |||
242 | return change_mask; | 242 | return change_mask; |
243 | } | 243 | } |
244 | 244 | ||
245 | static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index) | 245 | static void samsung_gpio_pm_4bit_con(struct samsung_gpio_chip *chip, int index) |
246 | { | 246 | { |
247 | void __iomem *con = chip->base + (index * 4); | 247 | void __iomem *con = chip->base + (index * 4); |
248 | u32 old_gpcon = __raw_readl(con); | 248 | u32 old_gpcon = __raw_readl(con); |
249 | u32 gps_gpcon = chip->pm_save[index + 1]; | 249 | u32 gps_gpcon = chip->pm_save[index + 1]; |
250 | u32 gpcon, mask; | 250 | u32 gpcon, mask; |
251 | 251 | ||
252 | mask = s3c_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); | 252 | mask = samsung_gpio_pm_4bit_mask(old_gpcon, gps_gpcon); |
253 | 253 | ||
254 | gpcon = old_gpcon & ~mask; | 254 | gpcon = old_gpcon & ~mask; |
255 | gpcon |= gps_gpcon & mask; | 255 | gpcon |= gps_gpcon & mask; |
@@ -257,7 +257,7 @@ static void s3c_gpio_pm_4bit_con(struct s3c_gpio_chip *chip, int index) | |||
257 | __raw_writel(gpcon, con); | 257 | __raw_writel(gpcon, con); |
258 | } | 258 | } |
259 | 259 | ||
260 | static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) | 260 | static void samsung_gpio_pm_4bit_resume(struct samsung_gpio_chip *chip) |
261 | { | 261 | { |
262 | void __iomem *base = chip->base; | 262 | void __iomem *base = chip->base; |
263 | u32 old_gpcon[2]; | 263 | u32 old_gpcon[2]; |
@@ -269,10 +269,10 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) | |||
269 | old_gpcon[0] = 0; | 269 | old_gpcon[0] = 0; |
270 | old_gpcon[1] = __raw_readl(base + OFFS_CON); | 270 | old_gpcon[1] = __raw_readl(base + OFFS_CON); |
271 | 271 | ||
272 | s3c_gpio_pm_4bit_con(chip, 0); | 272 | samsung_gpio_pm_4bit_con(chip, 0); |
273 | if (chip->chip.ngpio > 8) { | 273 | if (chip->chip.ngpio > 8) { |
274 | old_gpcon[0] = __raw_readl(base - 4); | 274 | old_gpcon[0] = __raw_readl(base - 4); |
275 | s3c_gpio_pm_4bit_con(chip, -1); | 275 | samsung_gpio_pm_4bit_con(chip, -1); |
276 | } | 276 | } |
277 | 277 | ||
278 | /* Now change the configurations that require DAT,CON */ | 278 | /* Now change the configurations that require DAT,CON */ |
@@ -298,19 +298,19 @@ static void s3c_gpio_pm_4bit_resume(struct s3c_gpio_chip *chip) | |||
298 | old_gpdat, gps_gpdat); | 298 | old_gpdat, gps_gpdat); |
299 | } | 299 | } |
300 | 300 | ||
301 | struct s3c_gpio_pm s3c_gpio_pm_4bit = { | 301 | struct samsung_gpio_pm samsung_gpio_pm_4bit = { |
302 | .save = s3c_gpio_pm_4bit_save, | 302 | .save = samsung_gpio_pm_4bit_save, |
303 | .resume = s3c_gpio_pm_4bit_resume, | 303 | .resume = samsung_gpio_pm_4bit_resume, |
304 | }; | 304 | }; |
305 | #endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ | 305 | #endif /* CONFIG_ARCH_S3C64XX || CONFIG_PLAT_S5P */ |
306 | 306 | ||
307 | /** | 307 | /** |
308 | * s3c_pm_save_gpio() - save gpio chip data for suspend | 308 | * samsung_pm_save_gpio() - save gpio chip data for suspend |
309 | * @ourchip: The chip for suspend. | 309 | * @ourchip: The chip for suspend. |
310 | */ | 310 | */ |
311 | static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip) | 311 | static void samsung_pm_save_gpio(struct samsung_gpio_chip *ourchip) |
312 | { | 312 | { |
313 | struct s3c_gpio_pm *pm = ourchip->pm; | 313 | struct samsung_gpio_pm *pm = ourchip->pm; |
314 | 314 | ||
315 | if (pm == NULL || pm->save == NULL) | 315 | if (pm == NULL || pm->save == NULL) |
316 | S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); | 316 | S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); |
@@ -319,24 +319,24 @@ static void s3c_pm_save_gpio(struct s3c_gpio_chip *ourchip) | |||
319 | } | 319 | } |
320 | 320 | ||
321 | /** | 321 | /** |
322 | * s3c_pm_save_gpios() - Save the state of the GPIO banks. | 322 | * samsung_pm_save_gpios() - Save the state of the GPIO banks. |
323 | * | 323 | * |
324 | * For all the GPIO banks, save the state of each one ready for going | 324 | * For all the GPIO banks, save the state of each one ready for going |
325 | * into a suspend mode. | 325 | * into a suspend mode. |
326 | */ | 326 | */ |
327 | void s3c_pm_save_gpios(void) | 327 | void samsung_pm_save_gpios(void) |
328 | { | 328 | { |
329 | struct s3c_gpio_chip *ourchip; | 329 | struct samsung_gpio_chip *ourchip; |
330 | unsigned int gpio_nr; | 330 | unsigned int gpio_nr; |
331 | 331 | ||
332 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { | 332 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { |
333 | ourchip = s3c_gpiolib_getchip(gpio_nr); | 333 | ourchip = samsung_gpiolib_getchip(gpio_nr); |
334 | if (!ourchip) { | 334 | if (!ourchip) { |
335 | gpio_nr++; | 335 | gpio_nr++; |
336 | continue; | 336 | continue; |
337 | } | 337 | } |
338 | 338 | ||
339 | s3c_pm_save_gpio(ourchip); | 339 | samsung_pm_save_gpio(ourchip); |
340 | 340 | ||
341 | S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n", | 341 | S3C_PMDBG("%s: save %08x,%08x,%08x,%08x\n", |
342 | ourchip->chip.label, | 342 | ourchip->chip.label, |
@@ -351,12 +351,12 @@ void s3c_pm_save_gpios(void) | |||
351 | } | 351 | } |
352 | 352 | ||
353 | /** | 353 | /** |
354 | * s3c_pm_resume_gpio() - restore gpio chip data after suspend | 354 | * samsung_pm_resume_gpio() - restore gpio chip data after suspend |
355 | * @ourchip: The suspended chip. | 355 | * @ourchip: The suspended chip. |
356 | */ | 356 | */ |
357 | static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip) | 357 | static void samsung_pm_resume_gpio(struct samsung_gpio_chip *ourchip) |
358 | { | 358 | { |
359 | struct s3c_gpio_pm *pm = ourchip->pm; | 359 | struct samsung_gpio_pm *pm = ourchip->pm; |
360 | 360 | ||
361 | if (pm == NULL || pm->resume == NULL) | 361 | if (pm == NULL || pm->resume == NULL) |
362 | S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); | 362 | S3C_PMDBG("%s: no pm for %s\n", __func__, ourchip->chip.label); |
@@ -364,19 +364,19 @@ static void s3c_pm_resume_gpio(struct s3c_gpio_chip *ourchip) | |||
364 | pm->resume(ourchip); | 364 | pm->resume(ourchip); |
365 | } | 365 | } |
366 | 366 | ||
367 | void s3c_pm_restore_gpios(void) | 367 | void samsung_pm_restore_gpios(void) |
368 | { | 368 | { |
369 | struct s3c_gpio_chip *ourchip; | 369 | struct samsung_gpio_chip *ourchip; |
370 | unsigned int gpio_nr; | 370 | unsigned int gpio_nr; |
371 | 371 | ||
372 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { | 372 | for (gpio_nr = 0; gpio_nr < S3C_GPIO_END;) { |
373 | ourchip = s3c_gpiolib_getchip(gpio_nr); | 373 | ourchip = samsung_gpiolib_getchip(gpio_nr); |
374 | if (!ourchip) { | 374 | if (!ourchip) { |
375 | gpio_nr++; | 375 | gpio_nr++; |
376 | continue; | 376 | continue; |
377 | } | 377 | } |
378 | 378 | ||
379 | s3c_pm_resume_gpio(ourchip); | 379 | samsung_pm_resume_gpio(ourchip); |
380 | 380 | ||
381 | gpio_nr += ourchip->chip.ngpio; | 381 | gpio_nr += ourchip->chip.ngpio; |
382 | gpio_nr += CONFIG_S3C_GPIO_SPACE; | 382 | gpio_nr += CONFIG_S3C_GPIO_SPACE; |
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c index ae6f99834cdd..64ab65f0fdbc 100644 --- a/arch/arm/plat-samsung/pm.c +++ b/arch/arm/plat-samsung/pm.c | |||
@@ -268,8 +268,8 @@ static int s3c_pm_enter(suspend_state_t state) | |||
268 | 268 | ||
269 | /* save all necessary core registers not covered by the drivers */ | 269 | /* save all necessary core registers not covered by the drivers */ |
270 | 270 | ||
271 | s3c_pm_save_gpios(); | 271 | samsung_pm_save_gpios(); |
272 | s3c_pm_saved_gpios(); | 272 | samsung_pm_saved_gpios(); |
273 | s3c_pm_save_uarts(); | 273 | s3c_pm_save_uarts(); |
274 | s3c_pm_save_core(); | 274 | s3c_pm_save_core(); |
275 | 275 | ||
@@ -306,7 +306,7 @@ static int s3c_pm_enter(suspend_state_t state) | |||
306 | 306 | ||
307 | s3c_pm_restore_core(); | 307 | s3c_pm_restore_core(); |
308 | s3c_pm_restore_uarts(); | 308 | s3c_pm_restore_uarts(); |
309 | s3c_pm_restore_gpios(); | 309 | samsung_pm_restore_gpios(); |
310 | s3c_pm_restored_gpios(); | 310 | s3c_pm_restored_gpios(); |
311 | 311 | ||
312 | s3c_pm_debug_init(); | 312 | s3c_pm_debug_init(); |