Merge branch 'sh/rsk-updates' into sh-latest

Conflicts:
	arch/sh/Kconfig

Signed-off-by: Paul Mundt <lethal@linux-sh.org>

192 files changed, 4412 insertions, 932 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 56a4df952fb0..22e58a99f38b 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -477,7 +477,7 @@ config ALPHA_BROKEN_IRQ_MASK
 
 config VGA_HOSE
         bool
-        depends on ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI
+        depends on VGA_CONSOLE && (ALPHA_GENERIC || ALPHA_TITAN || ALPHA_MARVEL || ALPHA_TSUNAMI)
         default y
         help
           Support VGA on an arbitrary hose; needed for several platforms
diff --git a/arch/alpha/include/asm/rtc.h b/arch/alpha/include/asm/rtc.h
index 1f7fba671ae6..d70408d36677 100644
--- a/arch/alpha/include/asm/rtc.h
+++ b/arch/alpha/include/asm/rtc.h
@@ -1,14 +1,10 @@
 #ifndef _ALPHA_RTC_H
 #define _ALPHA_RTC_H
 
-#if defined(CONFIG_ALPHA_GENERIC)
+#if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP) \
+ || defined(CONFIG_ALPHA_GENERIC)
 # define get_rtc_time           alpha_mv.rtc_get_time
 # define set_rtc_time           alpha_mv.rtc_set_time
-#else
-# if defined(CONFIG_ALPHA_MARVEL) && defined(CONFIG_SMP)
-#  define get_rtc_time          marvel_get_rtc_time
-#  define set_rtc_time          marvel_set_rtc_time
-# endif
 #endif
 
 #include <asm-generic/rtc.h>
diff --git a/arch/alpha/kernel/core_tsunami.c b/arch/alpha/kernel/core_tsunami.c
index 5e7c28f92f19..61893d7bdda5 100644
--- a/arch/alpha/kernel/core_tsunami.c
+++ b/arch/alpha/kernel/core_tsunami.c
@@ -11,6 +11,7 @@
 #include <asm/core_tsunami.h>
 #undef __EXTERN_INLINE
 
+#include <linux/module.h>
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/sched.h>
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index 14a4b6a7cf59..407accc80877 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -317,7 +317,7 @@ marvel_init_irq(void)
 }
 
 static int 
-marvel_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+marvel_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
         struct pci_controller *hose = dev->sysdata;
         struct io7_port *io7_port = hose->sysdata;
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index cf006d40342c..36586dba6fa6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1186,6 +1186,15 @@ if !MMU
 source "arch/arm/Kconfig-nommu"
 endif
 
+config ARM_ERRATA_326103
+        bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
+        depends on CPU_V6
+        help
+          Executing a SWP instruction to read-only memory does not set bit 11
+          of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
+          treat the access as a read, preventing a COW from occurring and
+          causing the faulting task to livelock.
+
 config ARM_ERRATA_411920
         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
         depends on CPU_V6 || CPU_V6K
diff --git a/arch/arm/boot/dts/msm8660-surf.dts b/arch/arm/boot/dts/msm8660-surf.dts
index 15ded0deaa79..45bc4bb04e57 100644
--- a/arch/arm/boot/dts/msm8660-surf.dts
+++ b/arch/arm/boot/dts/msm8660-surf.dts
@@ -10,7 +10,7 @@
         intc: interrupt-controller@02080000 {
                 compatible = "qcom,msm-8660-qgic";
                 interrupt-controller;
-                #interrupt-cells = <1>;
+                #interrupt-cells = <3>;
                 reg = < 0x02080000 0x1000 >,
                       < 0x02081000 0x1000 >;
         };
@@ -19,6 +19,6 @@
                 compatible = "qcom,msm-hsuart", "qcom,msm-uart";
                 reg = <0x19c40000 0x1000>,
                       <0x19c00000 0x1000>;
-                interrupts = <195>;
+                interrupts = <0 195 0x0>;
         };
 };
diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts
index 0b32925f2147..e2fe3195c0d1 100644
--- a/arch/arm/boot/dts/versatile-ab.dts
+++ b/arch/arm/boot/dts/versatile-ab.dts
@@ -173,7 +173,7 @@
                         mmc@5000 {
                                 compatible = "arm,primecell";
                                 reg = < 0x5000 0x1000>;
-                                interrupts = <22>;
+                                interrupts = <22 34>;
                         };
                         kmi@6000 {
                                 compatible = "arm,pl050", "arm,primecell";
diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts
index 166461073b78..7e8175269064 100644
--- a/arch/arm/boot/dts/versatile-pb.dts
+++ b/arch/arm/boot/dts/versatile-pb.dts
@@ -41,7 +41,7 @@
                         mmc@b000 {
                                 compatible = "arm,primecell";
                                 reg = <0xb000 0x1000>;
-                                interrupts = <23>;
+                                interrupts = <23 34>;
                         };
                 };
         };
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index b5ac644e12af..6b31cb60daab 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -112,6 +112,7 @@ CONFIG_WATCHDOG=y
 CONFIG_IMX2_WDT=y
 CONFIG_MFD_MC13XXX=y
 CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_MC13783=y
 CONFIG_REGULATOR_MC13892=y
 CONFIG_FB=y
diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig
index 42da9183acc8..082175c54e7c 100644
--- a/arch/arm/configs/mini2440_defconfig
+++ b/arch/arm/configs/mini2440_defconfig
@@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_BLK_DEV_INTEGRITY=y
 CONFIG_ARCH_S3C24XX=y
+# CONFIG_CPU_S3C2410 is not set
+CONFIG_CPU_S3C2440=y
 CONFIG_S3C_ADC=y
 CONFIG_S3C24XX_PWM=y
 CONFIG_MACH_MINI2440=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index 889d73ac1ae1..7e84f453e8a6 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -8,8 +8,6 @@ CONFIG_MODULE_UNLOAD=y
 # CONFIG_LBDAF is not set
 # CONFIG_BLK_DEV_BSG is not set
 CONFIG_ARCH_U8500=y
-CONFIG_UX500_SOC_DB5500=y
-CONFIG_UX500_SOC_DB8500=y
 CONFIG_MACH_HREFV60=y
 CONFIG_MACH_SNOWBALL=y
 CONFIG_MACH_U5500=y
@@ -39,7 +37,6 @@ CONFIG_CAIF=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_BLK_DEV_RAM=y
 CONFIG_BLK_DEV_RAM_SIZE=65536
-CONFIG_MISC_DEVICES=y
 CONFIG_AB8500_PWM=y
 CONFIG_SENSORS_BH1780=y
 CONFIG_NETDEVICES=y
@@ -65,16 +62,18 @@ CONFIG_SERIAL_AMBA_PL011=y
 CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_HW_RANDOM=y
 CONFIG_HW_RANDOM_NOMADIK=y
-CONFIG_I2C=y
-CONFIG_I2C_NOMADIK=y
 CONFIG_SPI=y
 CONFIG_SPI_PL022=y
 CONFIG_GPIO_STMPE=y
 CONFIG_GPIO_TC3589X=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_AB8500_BM=y
+CONFIG_AB8500_BATTERY_THERM_ON_BATCTRL=y
 CONFIG_MFD_STMPE=y
 CONFIG_MFD_TC3589X=y
 CONFIG_AB5500_CORE=y
 CONFIG_AB8500_CORE=y
+CONFIG_REGULATOR=y
 CONFIG_REGULATOR_AB8500=y
 # CONFIG_HID_SUPPORT is not set
 CONFIG_USB_GADGET=y
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index d4c24d412a8d..0f04d84582e1 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -118,6 +118,13 @@ extern void iwmmxt_task_switch(struct thread_info *);
 extern void vfp_sync_hwstate(struct thread_info *);
 extern void vfp_flush_hwstate(struct thread_info *);
 
+struct user_vfp;
+struct user_vfp_exc;
+
+extern int vfp_preserve_user_clear_hwstate(struct user_vfp __user *,
+                                           struct user_vfp_exc __user *);
+extern int vfp_restore_user_hwstate(struct user_vfp __user *,
+                                    struct user_vfp_exc __user *);
 #endif
 
 /*
diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
index 60843eb0f61c..73409e6c0251 100644
--- a/arch/arm/include/asm/tls.h
+++ b/arch/arm/include/asm/tls.h
@@ -7,6 +7,8 @@
 
         .macro set_tls_v6k, tp, tmp1, tmp2
         mcr     p15, 0, \tp, c13, c0, 3         @ set TLS register
+        mov     \tmp1, #0
+        mcr     p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         .endm
 
         .macro set_tls_v6, tp, tmp1, tmp2
@@ -15,6 +17,8 @@
         mov     \tmp2, #0xffff0fff
         tst     \tmp1, #HWCAP_TLS               @ hardware TLS available?
         mcrne   p15, 0, \tp, c13, c0, 3         @ yes, set TLS register
+        movne   \tmp1, #0
+        mcrne   p15, 0, \tmp1, c13, c0, 2       @ clear user r/w TLS register
         streq   \tp, [\tmp2, #-15]              @ set TLS value at 0xffff0ff0
         .endm
 
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 71ccdbfed662..8349d4e97e2b 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -155,10 +155,10 @@ static bool migrate_one_irq(struct irq_desc *desc)
         }
 
         c = irq_data_get_irq_chip(d);
-        if (c->irq_set_affinity)
-                c->irq_set_affinity(d, affinity, true);
-        else
+        if (!c->irq_set_affinity)
                 pr_debug("IRQ%u: unable to set affinity\n", d->irq);
+        else if (c->irq_set_affinity(d, affinity, true) == IRQ_SET_MASK_OK && ret)
+                cpumask_copy(d->affinity, affinity);
 
         return ret;
 }
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 80abafb9bf33..9650c143afc1 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -906,27 +906,14 @@ long arch_ptrace(struct task_struct *child, long request,
         return ret;
 }
 
-#ifdef __ARMEB__
-#define AUDIT_ARCH_NR AUDIT_ARCH_ARMEB
-#else
-#define AUDIT_ARCH_NR AUDIT_ARCH_ARM
-#endif
-
 asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 {
         unsigned long ip;
 
-        /*
-         * Save IP.  IP is used to denote syscall entry/exit:
-         *  IP = 0 -> entry, = 1 -> exit
-         */
-        ip = regs->ARM_ip;
-        regs->ARM_ip = why;
-
-        if (!ip)
+        if (why)
                 audit_syscall_exit(regs);
         else
-                audit_syscall_entry(AUDIT_ARCH_NR, scno, regs->ARM_r0,
+                audit_syscall_entry(AUDIT_ARCH_ARM, scno, regs->ARM_r0,
                                     regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
 
         if (!test_thread_flag(TIF_SYSCALL_TRACE))
@@ -936,6 +923,13 @@ asmlinkage int syscall_trace(int why, struct pt_regs *regs, int scno)
 
         current_thread_info()->syscall = scno;
 
+        /*
+         * IP is used to denote syscall entry/exit:
+         * IP = 0 -> entry, =1 -> exit
+         */
+        ip = regs->ARM_ip;
+        regs->ARM_ip = why;
+
         /* the 0x80 provides a way for the tracing parent to distinguish
            between a syscall stop and SIGTRAP delivery */
         ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 7cb532fc8aa4..d68d1b694680 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -180,44 +180,23 @@ static int restore_iwmmxt_context(struct iwmmxt_sigframe *frame)
 
 static int preserve_vfp_context(struct vfp_sigframe __user *frame)
 {
-        struct thread_info *thread = current_thread_info();
-        struct vfp_hard_struct *h = &thread->vfpstate.hard;
         const unsigned long magic = VFP_MAGIC;
         const unsigned long size = VFP_STORAGE_SIZE;
         int err = 0;
 
-        vfp_sync_hwstate(thread);
         __put_user_error(magic, &frame->magic, err);
         __put_user_error(size, &frame->size, err);
 
-        /*
-         * Copy the floating point registers. There can be unused
-         * registers see asm/hwcap.h for details.
-         */
-        err |= __copy_to_user(&frame->ufp.fpregs, &h->fpregs,
-                              sizeof(h->fpregs));
-        /*
-         * Copy the status and control register.
-         */
-        __put_user_error(h->fpscr, &frame->ufp.fpscr, err);
-
-        /*
-         * Copy the exception registers.
-         */
-        __put_user_error(h->fpexc, &frame->ufp_exc.fpexc, err);
-        __put_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-        __put_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
+        if (err)
+                return -EFAULT;
 
-        return err ? -EFAULT : 0;
+        return vfp_preserve_user_clear_hwstate(&frame->ufp, &frame->ufp_exc);
 }
 
 static int restore_vfp_context(struct vfp_sigframe __user *frame)
 {
-        struct thread_info *thread = current_thread_info();
-        struct vfp_hard_struct *h = &thread->vfpstate.hard;
         unsigned long magic;
         unsigned long size;
-        unsigned long fpexc;
         int err = 0;
 
         __get_user_error(magic, &frame->magic, err);
@@ -228,33 +207,7 @@ static int restore_vfp_context(struct vfp_sigframe __user *frame)
         if (magic != VFP_MAGIC || size != VFP_STORAGE_SIZE)
                 return -EINVAL;
 
-        vfp_flush_hwstate(thread);
-
-        /*
-         * Copy the floating point registers. There can be unused
-         * registers see asm/hwcap.h for details.
-         */
-        err |= __copy_from_user(&h->fpregs, &frame->ufp.fpregs,
-                                sizeof(h->fpregs));
-        /*
-         * Copy the status and control register.
-         */
-        __get_user_error(h->fpscr, &frame->ufp.fpscr, err);
-
-        /*
-         * Sanitise and restore the exception registers.
-         */
-        __get_user_error(fpexc, &frame->ufp_exc.fpexc, err);
-        /* Ensure the VFP is enabled. */
-        fpexc |= FPEXC_EN;
-        /* Ensure FPINST2 is invalid and the exception flag is cleared. */
-        fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
-        h->fpexc = fpexc;
-
-        __get_user_error(h->fpinst, &frame->ufp_exc.fpinst, err);
-        __get_user_error(h->fpinst2, &frame->ufp_exc.fpinst2, err);
-
-        return err ? -EFAULT : 0;
+        return vfp_restore_user_hwstate(&frame->ufp, &frame->ufp_exc);
 }
 
 #endif
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index addbbe8028c2..8f4644659777 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -251,8 +251,6 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         struct mm_struct *mm = &init_mm;
         unsigned int cpu = smp_processor_id();
 
-        printk("CPU%u: Booted secondary processor\n", cpu);
-
         /*
          * All kernel threads share the same mm context; grab a
          * reference and switch to it.
@@ -264,6 +262,8 @@ asmlinkage void __cpuinit secondary_start_kernel(void)
         enter_lazy_tlb(mm, current);
         local_flush_tlb_all();
 
+        printk("CPU%u: Booted secondary processor\n", cpu);
+
         cpu_init();
         preempt_disable();
         trace_hardirqs_off();
@@ -510,10 +510,6 @@ static void ipi_cpu_stop(unsigned int cpu)
         local_fiq_disable();
         local_irq_disable();
 
-#ifdef CONFIG_HOTPLUG_CPU
-        platform_cpu_kill(cpu);
-#endif
-
         while (1)
                 cpu_relax();
 }
@@ -576,17 +572,25 @@ void smp_send_reschedule(int cpu)
         smp_cross_call(cpumask_of(cpu), IPI_RESCHEDULE);
 }
 
+#ifdef CONFIG_HOTPLUG_CPU
+static void smp_kill_cpus(cpumask_t *mask)
+{
+        unsigned int cpu;
+        for_each_cpu(cpu, mask)
+                platform_cpu_kill(cpu);
+}
+#else
+static void smp_kill_cpus(cpumask_t *mask) { }
+#endif
+
 void smp_send_stop(void)
 {
         unsigned long timeout;
+        struct cpumask mask;
 
-        if (num_online_cpus() > 1) {
-                struct cpumask mask;
-                cpumask_copy(&mask, cpu_online_mask);
-                cpumask_clear_cpu(smp_processor_id(), &mask);
-
-                smp_cross_call(&mask, IPI_CPU_STOP);
-        }
+        cpumask_copy(&mask, cpu_online_mask);
+        cpumask_clear_cpu(smp_processor_id(), &mask);
+        smp_cross_call(&mask, IPI_CPU_STOP);
 
         /* Wait up to one second for other CPUs to stop */
         timeout = USEC_PER_SEC;
@@ -595,6 +599,8 @@ void smp_send_stop(void)
 
         if (num_online_cpus() > 1)
                 pr_warning("SMP: failed to stop secondary CPUs\n");
+
+        smp_kill_cpus(&mask);
 }
 
 /*
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 5b150afb995b..fef42b21cecb 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
          * The twd clock events must be reprogrammed to account for the new
          * frequency.  The timer is local to a cpu, so cross-call to the
          * changing cpu.
-         *
-         * Only wait for it to finish, if the cpu is active to avoid
-         * deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
-         * booting of that cpu.
          */
         if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
                 smp_call_function_single(freqs->cpu, twd_update_frequency,
-                                         NULL, cpu_active(freqs->cpu));
+                        NULL, 1);
 
         return NOTIFY_OK;
 }
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index d2b177905cdb..76cbb055dd05 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -115,7 +115,7 @@ int kernel_execve(const char *filename,
                   "Ir" (THREAD_START_SP - sizeof(regs)),
                   "r" (&regs),
                   "Ir" (sizeof(regs))
-                : "r0", "r1", "r2", "r3", "ip", "lr", "memory");
+                : "r0", "r1", "r2", "r3", "r8", "r9", "ip", "lr", "memory");
 
  out:
         return ret;
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 99ce5c955e39..05774e5b1cba 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -1173,7 +1173,6 @@ void __init at91_add_device_serial(void)
                 printk(KERN_INFO "AT91: No default serial console defined.\n");
 }
 #else
-void __init __deprecated at91_init_serial(struct at91_uart_config *config) {}
 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
 void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index dd7f782b0b91..104ca40d8d18 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/clockchips.h>
+#include <linux/export.h>
 
 #include <asm/mach/time.h>
 
@@ -176,6 +177,7 @@ static struct clock_event_device clkevt = {
 };
 
 void __iomem *at91_st_base;
+EXPORT_SYMBOL_GPL(at91_st_base);
 
 void __init at91rm9200_ioremap_st(u32 addr)
 {
diff --git a/arch/arm/mach-at91/board-rm9200ek.c b/arch/arm/mach-at91/board-rm9200ek.c
index 11cbaa8946fe..b2e4fe21f346 100644
--- a/arch/arm/mach-at91/board-rm9200ek.c
+++ b/arch/arm/mach-at91/board-rm9200ek.c
@@ -117,7 +117,7 @@ static struct i2c_board_info __initdata ek_i2c_devices[] = {
 };
 
 #define EK_FLASH_BASE   AT91_CHIPSELECT_0
-#define EK_FLASH_SIZE   SZ_2M
+#define EK_FLASH_SIZE   SZ_8M
 
 static struct physmap_flash_data ek_flash_data = {
         .width          = 2,
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index c3f994462864..065fed342424 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -85,8 +85,6 @@ static struct resource dm9000_resource[] = {
                 .flags  = IORESOURCE_MEM
         },
         [2] = {
-                .start  = AT91_PIN_PC11,
-                .end    = AT91_PIN_PC11,
                 .flags  = IORESOURCE_IRQ
                         | IORESOURCE_IRQ_LOWEDGE | IORESOURCE_IRQ_HIGHEDGE,
         }
@@ -130,6 +128,8 @@ static struct sam9_smc_config __initdata dm9000_smc_config = {
 
 static void __init ek_add_device_dm9000(void)
 {
+        struct resource *r = &dm9000_resource[2];
+
         /* Configure chip-select 2 (DM9000) */
         sam9_smc_configure(0, 2, &dm9000_smc_config);
 
@@ -139,6 +139,7 @@ static void __init ek_add_device_dm9000(void)
         /* Configure Interrupt pin as input, no pull-up */
         at91_set_gpio_input(AT91_PIN_PC11, 0);
 
+        r->start = r->end = gpio_to_irq(AT91_PIN_PC11);
         platform_device_register(&dm9000_device);
 }
 #else
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index a0f4d7424cdc..6b692824c988 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -35,6 +35,7 @@
 #include "generic.h"
 
 void __iomem *at91_pmc_base;
+EXPORT_SYMBOL_GPL(at91_pmc_base);
 
 /*
  * There's a lot more which can be done with clocks, including cpufreq
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 36604782a78f..ea2c57a86ca6 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -25,7 +25,7 @@ extern void __iomem *at91_pmc_base;
 #define at91_pmc_write(field, value) \
         __raw_writel(value, at91_pmc_base + field)
 #else
-.extern at91_aic_base
+.extern at91_pmc_base
 #endif
 
 #define AT91_PMC_SCER           0x00                    /* System Clock Enable Register */
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 97cc04dc8073..f44a2e7272e3 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -54,6 +54,7 @@ void __init at91_init_interrupts(unsigned int *priority)
 }
 
 void __iomem *at91_ramc_base[2];
+EXPORT_SYMBOL_GPL(at91_ramc_base);
 
 void __init at91_ioremap_ramc(int id, u32 addr, u32 size)
 {
@@ -292,6 +293,7 @@ void __init at91_ioremap_rstc(u32 base_addr)
 }
 
 void __iomem *at91_matrix_base;
+EXPORT_SYMBOL_GPL(at91_matrix_base);
 
 void __init at91_ioremap_matrix(u32 base_addr)
 {
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 22e4e0a28ad1..adbfb1994582 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -52,8 +52,8 @@
 #include <mach/csp/chipcHw_inline.h>
 #include <mach/csp/tmrHw_reg.h>
 
-static AMBA_APB_DEVICE(uartA, "uarta", MM_ADDR_IO_UARTA, { IRQ_UARTA }, NULL);
-static AMBA_APB_DEVICE(uartB, "uartb", MM_ADDR_IO_UARTB, { IRQ_UARTB }, NULL);
+static AMBA_APB_DEVICE(uartA, "uartA", 0, MM_ADDR_IO_UARTA, {IRQ_UARTA}, NULL);
+static AMBA_APB_DEVICE(uartB, "uartB", 0, MM_ADDR_IO_UARTB, {IRQ_UARTB}, NULL);
 
 static struct clk pll1_clk = {
         .name = "PLL1",
diff --git a/arch/arm/mach-exynos/clock-exynos4.c b/arch/arm/mach-exynos/clock-exynos4.c
index df54c2a92225..6efd1e5919fd 100644
--- a/arch/arm/mach-exynos/clock-exynos4.c
+++ b/arch/arm/mach-exynos/clock-exynos4.c
@@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
                 .ctrlbit        = (1 << 3),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 5),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 6),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 7),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos4_clk_aclk_133.clk,
                 .enable         = exynos4_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos4_clk_dout_mmc0.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 0),
@@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos4_clk_dout_mmc1.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 4),
@@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos4_clk_dout_mmc2.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos4_clk_dout_mmc3.clk,
                 .enable         = exynos4_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
@@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
         CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index d013982d0f8e..5cd7a8b8868c 100644
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
                 .ctrlbit        = (1 << 20),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 13),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 14),
         }, {
                 .name           = "hsmmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos5_clk_aclk_200.clk,
                 .enable         = exynos5_clk_ip_fsys_ctrl,
                 .ctrlbit        = (1 << 15),
@@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.0",
+                .devname        = "exynos4-sdhci.0",
                 .parent         = &exynos5_clk_dout_mmc0.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 0),
@@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.1",
+                .devname        = "exynos4-sdhci.1",
                 .parent         = &exynos5_clk_dout_mmc1.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 4),
@@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.2",
+                .devname        = "exynos4-sdhci.2",
                 .parent         = &exynos5_clk_dout_mmc2.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 8),
@@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
 static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
         .clk    = {
                 .name           = "sclk_mmc",
-                .devname        = "s3c-sdhci.3",
+                .devname        = "exynos4-sdhci.3",
                 .parent         = &exynos5_clk_dout_mmc3.clk,
                 .enable         = exynos5_clksrc_mask_fsys_ctrl,
                 .ctrlbit        = (1 << 12),
@@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
         CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
         CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
         CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
-        CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
-        CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
-        CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
-        CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+        CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+        CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+        CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+        CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
         CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
         CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
         CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 8614aab47cc0..5ccd6e80a607 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
         s3c_fimc_setname(2, "exynos4-fimc");
         s3c_fimc_setname(3, "exynos4-fimc");
 
+        s3c_sdhci_setname(0, "exynos4-sdhci");
+        s3c_sdhci_setname(1, "exynos4-sdhci");
+        s3c_sdhci_setname(2, "exynos4-sdhci");
+        s3c_sdhci_setname(3, "exynos4-sdhci");
+
         /* The I2C bus controllers are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
@@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
         s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
         s3c_device_i2c0.resource[1].end   = EXYNOS5_IRQ_IIC;
 
+        s3c_sdhci_setname(0, "exynos4-sdhci");
+        s3c_sdhci_setname(1, "exynos4-sdhci");
+        s3c_sdhci_setname(2, "exynos4-sdhci");
+        s3c_sdhci_setname(3, "exynos4-sdhci");
+
         /* The I2C bus controllers are directly compatible with s3c2440 */
         s3c_i2c0_setname("s3c2440-i2c");
         s3c_i2c1_setname("s3c2440-i2c");
@@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
 {
         int irq;
 
-        gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+#ifdef CONFIG_OF
+        of_irq_init(exynos4_dt_irq_match);
+#endif
 
         for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
                 combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
diff --git a/arch/arm/mach-exynos/dev-dwmci.c b/arch/arm/mach-exynos/dev-dwmci.c
index b025db4bf602..79035018fb74 100644
--- a/arch/arm/mach-exynos/dev-dwmci.c
+++ b/arch/arm/mach-exynos/dev-dwmci.c
@@ -16,6 +16,7 @@
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
+#include <linux/ioport.h>
 #include <linux/mmc/dw_mmc.h>
 
 #include <plat/devs.h>
@@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
 }
 
 static struct resource exynos4_dwmci_resource[] = {
-        [0] = {
-                .start  = EXYNOS4_PA_DWMCI,
-                .end    = EXYNOS4_PA_DWMCI + SZ_4K - 1,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_DWMCI,
-                .end    = IRQ_DWMCI,
-                .flags  = IORESOURCE_IRQ,
-        }
+        [0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
+        [1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
 };
 
 static struct dw_mci_board exynos4_dwci_pdata = {
diff --git a/arch/arm/mach-exynos/mach-nuri.c b/arch/arm/mach-exynos/mach-nuri.c
index b4f1f902ce6d..ed90aef404c3 100644
--- a/arch/arm/mach-exynos/mach-nuri.c
+++ b/arch/arm/mach-exynos/mach-nuri.c
@@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
         .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
                                 MMC_CAP_ERASE),
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
diff --git a/arch/arm/mach-exynos/mach-universal_c210.c b/arch/arm/mach-exynos/mach-universal_c210.c
index 7ebf79c2ab34..cb2b027f09a6 100644
--- a/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/arch/arm/mach-exynos/mach-universal_c210.c
@@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
         .max_width              = 8,
         .host_caps              = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
                                 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
         .clk_type               = S3C_SDHCI_CLK_DIV_EXTERNAL,
 };
diff --git a/arch/arm/mach-imx/imx27-dt.c b/arch/arm/mach-imx/imx27-dt.c
index 861ceb8232d6..ed38d03c61f2 100644
--- a/arch/arm/mach-imx/imx27-dt.c
+++ b/arch/arm/mach-imx/imx27-dt.c
@@ -35,7 +35,7 @@ static const struct of_dev_auxdata imx27_auxdata_lookup[] __initconst = {
 static int __init imx27_avic_add_irq_domain(struct device_node *np,
                                 struct device_node *interrupt_parent)
 {
-        irq_domain_add_simple(np, 0);
+        irq_domain_add_legacy(np, 64, 0, 0, &irq_domain_simple_ops, NULL);
         return 0;
 }
 
@@ -44,7 +44,9 @@ static int __init imx27_gpio_add_irq_domain(struct device_node *np,
 {
         static int gpio_irq_base = MXC_GPIO_IRQ_START + ARCH_NR_GPIOS;
 
-        irq_domain_add_simple(np, gpio_irq_base);
+        gpio_irq_base -= 32;
+        irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops,
+                                NULL);
 
         return 0;
 }
diff --git a/arch/arm/mach-imx/mm-imx5.c b/arch/arm/mach-imx/mm-imx5.c
index 05250aed61fb..e10f3914fcfe 100644
--- a/arch/arm/mach-imx/mm-imx5.c
+++ b/arch/arm/mach-imx/mm-imx5.c
@@ -35,7 +35,7 @@ static void imx5_idle(void)
         }
         clk_enable(gpc_dvfs_clk);
         mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
-        if (tzic_enable_wake() != 0)
+        if (!tzic_enable_wake())
                 cpu_do_idle();
         clk_disable(gpc_dvfs_clk);
 }
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index 1c672d9e6656..f7fe1b9f3170 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <linux/of.h>
 #include <linux/of_platform.h>
+#include <linux/kexec.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <mach/bridge-regs.h>
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 962e71169750..fb3496a52ef4 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -17,6 +17,7 @@
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/memblock.h>
 
@@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
         msm_map_msm8x60_io();
 }
 
+#ifdef CONFIG_OF
+static struct of_device_id msm_dt_gic_match[] __initdata = {
+        { .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
+        {}
+};
+#endif
+
 static void __init msm8x60_init_irq(void)
 {
-        gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
-                 (void *)MSM_QGIC_CPU_BASE);
+        if (!of_have_populated_dt())
+                gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+                         (void *)MSM_QGIC_CPU_BASE);
+#ifdef CONFIG_OF
+        else
+                of_irq_init(msm_dt_gic_match);
+#endif
 
         /* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
         writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
@@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
         {}
 };
 
-static struct of_device_id msm_dt_gic_match[] __initdata = {
-        { .compatible = "qcom,msm-8660-qgic", },
-        {}
-};
-
 static void __init msm8x60_dt_init(void)
 {
-        irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
-                                GIC_SPI_START);
-
         if (of_machine_is_compatible("qcom,msm8660-surf")) {
                 printk(KERN_INFO "Init surf UART registers\n");
                 msm8x60_init_uart12dm();
diff --git a/arch/arm/mach-omap1/ams-delta-fiq.c b/arch/arm/mach-omap1/ams-delta-fiq.c
index fcce7ff37630..cfd98b186fcc 100644
--- a/arch/arm/mach-omap1/ams-delta-fiq.c
+++ b/arch/arm/mach-omap1/ams-delta-fiq.c
@@ -48,7 +48,7 @@ static irqreturn_t deferred_fiq(int irq, void *dev_id)
         struct irq_chip *irq_chip = NULL;
         int gpio, irq_num, fiq_count;
 
-        irq_desc = irq_to_desc(IH_GPIO_BASE);
+        irq_desc = irq_to_desc(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
         if (irq_desc)
                 irq_chip = irq_desc->irq_data.chip;
 
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index 087dba0df47e..e9cc52d4cb28 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -27,6 +27,7 @@
 #include <linux/io.h>
 #include <linux/spinlock.h>
 
+#include <mach/hardware.h>
 
 #include <plat/mux.h>
 
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 6e90665a7c47..fb202af01d0d 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -47,9 +47,9 @@ static int omap1_dm_timer_set_src(struct platform_device *pdev,
         int n = (pdev->id - 1) << 1;
         u32 l;
 
-        l = __raw_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
+        l = omap_readl(MOD_CONF_CTRL_1) & ~(0x03 << n);
         l |= source << n;
-        __raw_writel(l, MOD_CONF_CTRL_1);
+        omap_writel(l, MOD_CONF_CTRL_1);
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index a39fc4bbd2b8..130ab00c09a2 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -20,6 +20,7 @@
 #include <linux/usb/otg.h>
 #include <linux/spi/spi.h>
 #include <linux/i2c/twl.h>
+#include <linux/mfd/twl6040.h>
 #include <linux/gpio_keys.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
@@ -560,7 +561,7 @@ static struct regulator_init_data sdp4430_vusim = {
         },
 };
 
-static struct twl4030_codec_data twl6040_codec = {
+static struct twl6040_codec_data twl6040_codec = {
         /* single-step ramp for headset and handsfree */
         .hs_left_step   = 0x0f,
         .hs_right_step  = 0x0f,
@@ -568,7 +569,7 @@ static struct twl4030_codec_data twl6040_codec = {
         .hf_right_step  = 0x1d,
 };
 
-static struct twl4030_vibra_data twl6040_vibra = {
+static struct twl6040_vibra_data twl6040_vibra = {
         .vibldrv_res = 8,
         .vibrdrv_res = 3,
         .viblmotor_res = 10,
@@ -577,16 +578,14 @@ static struct twl4030_vibra_data twl6040_vibra = {
         .vddvibr_uV = 0,        /* fixed volt supply - VBAT */
 };
 
-static struct twl4030_audio_data twl6040_audio = {
+static struct twl6040_platform_data twl6040_data = {
         .codec          = &twl6040_codec,
         .vibra          = &twl6040_vibra,
         .audpwron_gpio  = 127,
-        .naudint_irq    = OMAP44XX_IRQ_SYS_2N,
         .irq_base       = TWL6040_CODEC_IRQ_BASE,
 };
 
 static struct twl4030_platform_data sdp4430_twldata = {
-        .audio          = &twl6040_audio,
         /* Regulators */
         .vusim          = &sdp4430_vusim,
         .vaux1          = &sdp4430_vaux1,
@@ -617,7 +616,8 @@ static int __init omap4_i2c_init(void)
                         TWL_COMMON_REGULATOR_VCXIO |
                         TWL_COMMON_REGULATOR_VUSB |
                         TWL_COMMON_REGULATOR_CLK32KG);
-        omap4_pmic_init("twl6030", &sdp4430_twldata);
+        omap4_pmic_init("twl6030", &sdp4430_twldata,
+                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
         omap_register_i2c_bus(2, 400, NULL, 0);
         omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
                                 ARRAY_SIZE(sdp4430_i2c_3_boardinfo));
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 74e1687b5170..098d183a0086 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -137,7 +137,7 @@ static struct twl4030_platform_data sdp4430_twldata = {
 
 static void __init omap4_i2c_init(void)
 {
-        omap4_pmic_init("twl6030", &sdp4430_twldata);
+        omap4_pmic_init("twl6030", &sdp4430_twldata, NULL, 0);
 }
 
 static void __init omap4_init(void)
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 930c0d380435..740cee9369ba 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -641,7 +641,7 @@ static struct regulator_consumer_supply dummy_supplies[] = {
 
 static void __init igep_init(void)
 {
-        regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
+        regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
         omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
 
         /* Get IGEP2 hardware revision */
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index d8c0e89f0126..1b782ba53433 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -25,6 +25,7 @@
 #include <linux/gpio.h>
 #include <linux/usb/otg.h>
 #include <linux/i2c/twl.h>
+#include <linux/mfd/twl6040.h>
 #include <linux/regulator/machine.h>
 #include <linux/regulator/fixed.h>
 #include <linux/wl12xx.h>
@@ -284,7 +285,7 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
         return 0;
 }
 
-static struct twl4030_codec_data twl6040_codec = {
+static struct twl6040_codec_data twl6040_codec = {
         /* single-step ramp for headset and handsfree */
         .hs_left_step   = 0x0f,
         .hs_right_step  = 0x0f,
@@ -292,17 +293,14 @@ static struct twl4030_codec_data twl6040_codec = {
         .hf_right_step  = 0x1d,
 };
 
-static struct twl4030_audio_data twl6040_audio = {
+static struct twl6040_platform_data twl6040_data = {
         .codec          = &twl6040_codec,
         .audpwron_gpio  = 127,
-        .naudint_irq    = OMAP44XX_IRQ_SYS_2N,
         .irq_base       = TWL6040_CODEC_IRQ_BASE,
 };
 
 /* Panda board uses the common PMIC configuration */
-static struct twl4030_platform_data omap4_panda_twldata = {
-        .audio          = &twl6040_audio,
-};
+static struct twl4030_platform_data omap4_panda_twldata;
 
 /*
  * Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -326,7 +324,8 @@ static int __init omap4_panda_i2c_init(void)
                         TWL_COMMON_REGULATOR_VCXIO |
                         TWL_COMMON_REGULATOR_VUSB |
                         TWL_COMMON_REGULATOR_CLK32KG);
-        omap4_pmic_init("twl6030", &omap4_panda_twldata);
+        omap4_pmic_init("twl6030", &omap4_panda_twldata,
+                        &twl6040_data, OMAP44XX_IRQ_SYS_2N);
         omap_register_i2c_bus(2, 400, NULL, 0);
         /*
          * Bus 3 is attached to the DVI port where devices like the pico DLP
diff --git a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
index 1e2d3322f33e..c88420de1151 100644
--- a/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
+++ b/arch/arm/mach-omap2/include/mach/ctrl_module_pad_core_44xx.h
@@ -941,10 +941,10 @@
 #define OMAP4_DSI2_LANEENABLE_MASK                              (0x7 << 29)
 #define OMAP4_DSI1_LANEENABLE_SHIFT                             24
 #define OMAP4_DSI1_LANEENABLE_MASK                              (0x1f << 24)
-#define OMAP4_DSI2_PIPD_SHIFT                                   19
-#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 19)
-#define OMAP4_DSI1_PIPD_SHIFT                                   14
-#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 14)
+#define OMAP4_DSI1_PIPD_SHIFT                                   19
+#define OMAP4_DSI1_PIPD_MASK                                    (0x1f << 19)
+#define OMAP4_DSI2_PIPD_SHIFT                                   14
+#define OMAP4_DSI2_PIPD_MASK                                    (0x1f << 14)
 
 /* CONTROL_MCBSPLP */
 #define OMAP4_ALBCTRLRX_FSX_SHIFT                               31
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2c27fdb61e66..7144ae651d3d 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1422,6 +1422,9 @@ static int _ocp_softreset(struct omap_hwmod *oh)
                 goto dis_opt_clks;
         _write_sysconfig(v, oh);
 
+        if (oh->class->sysc->srst_udelay)
+                udelay(oh->class->sysc->srst_udelay);
+
         if (oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)
                 omap_test_timeout((omap_hwmod_read(oh,
                                                     oh->class->sysc->syss_offs)
@@ -1903,10 +1906,20 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
  */
 int omap_hwmod_softreset(struct omap_hwmod *oh)
 {
-        if (!oh)
+        u32 v;
+        int ret;
+
+        if (!oh || !(oh->_sysc_cache))
                 return -EINVAL;
 
-        return _ocp_softreset(oh);
+        v = oh->_sysc_cache;
+        ret = _set_softreset(oh, &v);
+        if (ret)
+                goto error;
+        _write_sysconfig(v, oh);
+
+error:
+        return ret;
 }
 
 /**
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index a5409ce3f323..a6bde34e443a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1000,7 +1000,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
                         .flags  = OMAP_FIREWALL_L4,
                 }
         },
-        .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index c4f56cb60d7d..04a3885f4475 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1049,7 +1049,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
         .slave          = &omap2430_dss_venc_hwmod,
         .clk            = "dss_ick",
         .addr           = omap2_dss_venc_addrs,
-        .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 34b9766d1d23..db86ce90c69f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1676,7 +1676,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
                         .flags  = OMAP_FIREWALL_L4,
                 }
         },
-        .flags          = OCPIF_SWSUP_IDLE,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index cc9bd106a854..6abc75753e42 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -2594,6 +2594,15 @@ static struct omap_hwmod omap44xx_ipu_hwmod = {
 static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
         .rev_offs       = 0x0000,
         .sysc_offs      = 0x0010,
+        /*
+         * ISS needs 100 OCP clk cycles delay after a softreset before
+         * accessing sysconfig again.
+         * The lowest frequency at the moment for L3 bus is 100 MHz, so
+         * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
+         *
+         * TODO: Indicate errata when available.
+         */
+        .srst_udelay    = 2,
         .sysc_flags     = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
                            SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
         .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index 0cdd359a128e..9fc2f44188cb 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -108,8 +108,14 @@ static void omap_uart_set_noidle(struct platform_device *pdev)
 static void omap_uart_set_smartidle(struct platform_device *pdev)
 {
         struct omap_device *od = to_omap_device(pdev);
+        u8 idlemode;
 
-        omap_hwmod_set_slave_idlemode(od->hwmods[0], HWMOD_IDLEMODE_SMART);
+        if (od->hwmods[0]->class->sysc->idlemodes & SIDLE_SMART_WKUP)
+                idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+        else
+                idlemode = HWMOD_IDLEMODE_SMART;
+
+        omap_hwmod_set_slave_idlemode(od->hwmods[0], idlemode);
 }
 
 #else
@@ -120,124 +126,8 @@ static void omap_uart_set_smartidle(struct platform_device *pdev) {}
 #endif /* CONFIG_PM */
 
 #ifdef CONFIG_OMAP_MUX
-static struct omap_device_pad default_uart1_pads[] __initdata = {
-        {
-                .name   = "uart1_cts.uart1_cts",
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart1_rts.uart1_rts",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart1_tx.uart1_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart1_rx.uart1_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-};
-
-static struct omap_device_pad default_uart2_pads[] __initdata = {
-        {
-                .name   = "uart2_cts.uart2_cts",
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart2_rts.uart2_rts",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart2_tx.uart2_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart2_rx.uart2_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-};
-
-static struct omap_device_pad default_uart3_pads[] __initdata = {
-        {
-                .name   = "uart3_cts_rctx.uart3_cts_rctx",
-                .enable = OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart3_rts_sd.uart3_rts_sd",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart3_tx_irtx.uart3_tx_irtx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart3_rx_irrx.uart3_rx_irrx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-        },
-};
-
-static struct omap_device_pad default_omap36xx_uart4_pads[] __initdata = {
-        {
-                .name   = "gpmc_wait2.uart4_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "gpmc_wait3.uart4_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE2,
-        },
-};
-
-static struct omap_device_pad default_omap4_uart4_pads[] __initdata = {
-        {
-                .name   = "uart4_tx.uart4_tx",
-                .enable = OMAP_PIN_OUTPUT | OMAP_MUX_MODE0,
-        },
-        {
-                .name   = "uart4_rx.uart4_rx",
-                .flags  = OMAP_DEVICE_PAD_REMUX | OMAP_DEVICE_PAD_WAKEUP,
-                .enable = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-                .idle   = OMAP_PIN_INPUT | OMAP_MUX_MODE0,
-        },
-};
-
 static void omap_serial_fill_default_pads(struct omap_board_data *bdata)
 {
-        switch (bdata->id) {
-        case 0:
-                bdata->pads = default_uart1_pads;
-                bdata->pads_cnt = ARRAY_SIZE(default_uart1_pads);
-                break;
-        case 1:
-                bdata->pads = default_uart2_pads;
-                bdata->pads_cnt = ARRAY_SIZE(default_uart2_pads);
-                break;
-        case 2:
-                bdata->pads = default_uart3_pads;
-                bdata->pads_cnt = ARRAY_SIZE(default_uart3_pads);
-                break;
-        case 3:
-                if (cpu_is_omap44xx()) {
-                        bdata->pads = default_omap4_uart4_pads;
-                        bdata->pads_cnt =
-                                ARRAY_SIZE(default_omap4_uart4_pads);
-                } else if (cpu_is_omap3630()) {
-                        bdata->pads = default_omap36xx_uart4_pads;
-                        bdata->pads_cnt =
-                                ARRAY_SIZE(default_omap36xx_uart4_pads);
-                }
-                break;
-        default:
-                break;
-        }
 }
 #else
 static void omap_serial_fill_default_pads(struct omap_board_data *bdata) {}
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
index 4b57757bf9d1..7a7b89304c48 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -37,6 +37,16 @@ static struct i2c_board_info __initdata pmic_i2c_board_info = {
         .flags          = I2C_CLIENT_WAKE,
 };
 
+static struct i2c_board_info __initdata omap4_i2c1_board_info[] = {
+        {
+                .addr           = 0x48,
+                .flags          = I2C_CLIENT_WAKE,
+        },
+        {
+                I2C_BOARD_INFO("twl6040", 0x4b),
+        },
+};
+
 void __init omap_pmic_init(int bus, u32 clkrate,
                            const char *pmic_type, int pmic_irq,
                            struct twl4030_platform_data *pmic_data)
@@ -49,14 +59,31 @@ void __init omap_pmic_init(int bus, u32 clkrate,
         omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
 }
 
+void __init omap4_pmic_init(const char *pmic_type,
+                    struct twl4030_platform_data *pmic_data,
+                    struct twl6040_platform_data *twl6040_data, int twl6040_irq)
+{
+        /* PMIC part*/
+        strncpy(omap4_i2c1_board_info[0].type, pmic_type,
+                sizeof(omap4_i2c1_board_info[0].type));
+        omap4_i2c1_board_info[0].irq = OMAP44XX_IRQ_SYS_1N;
+        omap4_i2c1_board_info[0].platform_data = pmic_data;
+
+        /* TWL6040 audio IC part */
+        omap4_i2c1_board_info[1].irq = twl6040_irq;
+        omap4_i2c1_board_info[1].platform_data = twl6040_data;
+
+        omap_register_i2c_bus(1, 400, omap4_i2c1_board_info, 2);
+
+}
+
 void __init omap_pmic_late_init(void)
 {
         /* Init the OMAP TWL parameters (if PMIC has been registerd) */
-        if (!pmic_i2c_board_info.irq)
-                return;
-
-        omap3_twl_init();
-        omap4_twl_init();
+        if (pmic_i2c_board_info.irq)
+                omap3_twl_init();
+        if (omap4_i2c1_board_info[0].irq)
+                omap4_twl_init();
 }
 
 #if defined(CONFIG_ARCH_OMAP3)
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
index 275dde8cb27a..09627483a57f 100644
--- a/arch/arm/mach-omap2/twl-common.h
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -29,6 +29,7 @@
 
 
 struct twl4030_platform_data;
+struct twl6040_platform_data;
 
 void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
                     struct twl4030_platform_data *pmic_data);
@@ -46,12 +47,9 @@ static inline void omap3_pmic_init(const char *pmic_type,
         omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
 }
 
-static inline void omap4_pmic_init(const char *pmic_type,
-                                   struct twl4030_platform_data *pmic_data)
-{
-        /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
-        omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
-}
+void omap4_pmic_init(const char *pmic_type,
+                    struct twl4030_platform_data *pmic_data,
+                    struct twl6040_platform_data *audio_data, int twl6040_irq);
 
 void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
                            u32 pdata_flags, u32 regulators_flags);
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index eac68978a2c2..db70e79a1198 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -65,8 +65,8 @@
 #define MPP8_GIGE               MPP(8,  0x1, 0, 0, 1,   1,   1)
 
 #define MPP9_UNUSED             MPP(9,  0x0, 0, 0, 1,   1,   1)
-#define MPP9_GPIO               MPP(9,  0x0, 0, 0, 1,   1,   1)
-#define MPP9_GIGE               MPP(9,  0x1, 1, 1, 1,   1,   1)
+#define MPP9_GPIO               MPP(9,  0x0, 1, 1, 1,   1,   1)
+#define MPP9_GIGE               MPP(9,  0x1, 0, 0, 1,   1,   1)
 
 #define MPP10_UNUSED            MPP(10, 0x0, 0, 0, 1,   1,   1)
 #define MPP10_GPIO              MPP(10, 0x0, 1, 1, 1,   1,   1)
diff --git a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
index c54cef25895c..cbf51ae81855 100644
--- a/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
+++ b/arch/arm/mach-pxa/include/mach/mfp-pxa2xx.h
@@ -17,6 +17,7 @@
  *
  * bit     23 - Input/Output (PXA2xx specific)
  * bit     24 - Wakeup Enable(PXA2xx specific)
+ * bit     25 - Keep Output  (PXA2xx specific)
  */
 
 #define MFP_DIR_IN              (0x0 << 23)
@@ -25,6 +26,12 @@
 #define MFP_DIR(x)              (((x) >> 23) & 0x1)
 
 #define MFP_LPM_CAN_WAKEUP      (0x1 << 24)
+
+/*
+ * MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
+ * retain their last output level (low or high).
+ * Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
+ */
 #define MFP_LPM_KEEP_OUTPUT     (0x1 << 25)
 
 #define WAKEUP_ON_EDGE_RISE     (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
diff --git a/arch/arm/mach-pxa/mfp-pxa2xx.c b/arch/arm/mach-pxa/mfp-pxa2xx.c
index b0a842887780..ef0426a159d4 100644
--- a/arch/arm/mach-pxa/mfp-pxa2xx.c
+++ b/arch/arm/mach-pxa/mfp-pxa2xx.c
@@ -33,6 +33,8 @@
 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
 #define GPLR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5))
 #define GPDR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
+#define GPSR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
+#define GPCR(x)         __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
 
 #define PWER_WE35       (1 << 24)
 
@@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
 #ifdef CONFIG_PM
 static unsigned long saved_gafr[2][4];
 static unsigned long saved_gpdr[4];
+static unsigned long saved_gplr[4];
 static unsigned long saved_pgsr[4];
 
 static int pxa2xx_mfp_suspend(void)
@@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
         }
 
         for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
-
                 saved_gafr[0][i] = GAFR_L(i);
                 saved_gafr[1][i] = GAFR_U(i);
                 saved_gpdr[i] = GPDR(i * 32);
+                saved_gplr[i] = GPLR(i * 32);
                 saved_pgsr[i] = PGSR(i);
 
-                GPDR(i * 32) = gpdr_lpm[i];
+                GPSR(i * 32) = PGSR(i);
+                GPCR(i * 32) = ~PGSR(i);
+        }
+
+        /* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
+        for (i = 0; i < pxa_last_gpio; i++) {
+                if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
+                    ((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
+                     (saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
+                        GPDR(i) |= GPIO_bit(i);
+                else
+                        GPDR(i) &= ~GPIO_bit(i);
         }
+
         return 0;
 }
 
@@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
         for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
                 GAFR_L(i) = saved_gafr[0][i];
                 GAFR_U(i) = saved_gafr[1][i];
+                GPSR(i * 32) = saved_gplr[i];
+                GPCR(i * 32) = ~saved_gplr[i];
                 GPDR(i * 32) = saved_gpdr[i];
                 PGSR(i) = saved_pgsr[i];
         }
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c
index 6bce78edce7a..4726c246dcdc 100644
--- a/arch/arm/mach-pxa/pxa27x.c
+++ b/arch/arm/mach-pxa/pxa27x.c
@@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
         pxa_register_device(&pxa27x_device_i2c_power, info);
 }
 
+static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
+        .gpio_set_wake = gpio_set_wake,
+};
+
 static struct platform_device *devices[] __initdata = {
-        &pxa_device_gpio,
         &pxa27x_device_udc,
         &pxa_device_pmu,
         &pxa_device_i2s,
@@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
                 register_syscore_ops(&pxa2xx_mfp_syscore_ops);
                 register_syscore_ops(&pxa2xx_clock_syscore_ops);
 
+                pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
                 ret = platform_add_devices(devices, ARRAY_SIZE(devices));
         }
 
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 0f3a327ebcaa..b34287ab5afd 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
         help
           Compile in platform device definition for Samsung TouchScreen.
 
-# cpu-specific sections
-
-if CPU_S3C2410
-
 config S3C2410_DMA
         bool
         depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
@@ -127,6 +123,10 @@ config S3C2410_PM
         help
           Power Management code common to S3C2410 and better
 
+# cpu-specific sections
+
+if CPU_S3C2410
+
 config S3C24XX_SIMTEC_NOR
         bool
         help
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index a8933de3d627..32395664e879 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -25,6 +25,7 @@
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
 #include <linux/gpio.h>
+#include <linux/mmc/host.h>
 #include <linux/interrupt.h>
 
 #include <asm/hardware/vic.h>
@@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
 /* MoviNAND */
 static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
         .max_width              = 4,
+        .host_caps2             = MMC_CAP2_BROKEN_VOLTAGE,
         .cd_type                = S3C_SDHCI_CD_PERMANENT,
 };
 
diff --git a/arch/arm/mach-sa1100/generic.c b/arch/arm/mach-sa1100/generic.c
index 7c524b4e415d..16be4c56abe3 100644
--- a/arch/arm/mach-sa1100/generic.c
+++ b/arch/arm/mach-sa1100/generic.c
@@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
 }
 
 static struct resource sa1100_rtc_resources[] = {
-        DEFINE_RES_MEM(0x90010000, 0x9001003f),
+        DEFINE_RES_MEM(0x90010000, 0x40),
         DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
         DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
 };
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 1621ad07d284..33339745d432 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
 
         for (i = 0; i < U300_VIC_IRQS_END; i++)
                 set_bit(i, (unsigned long *) &mask[0]);
-        vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
-        vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
+        vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
+                 mask[0], mask[0]);
+        vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
+                 mask[1], mask[1]);
 }
 
 
diff --git a/arch/arm/mach-u300/i2c.c b/arch/arm/mach-u300/i2c.c
index a38f80238ea9..cb04bd6ab3e7 100644
--- a/arch/arm/mach-u300/i2c.c
+++ b/arch/arm/mach-u300/i2c.c
@@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .min_uV = 1800000,
                                 .max_uV = 1800000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
@@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .min_uV = 2500000,
                                 .max_uV = 2500000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
-                                .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
@@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
                                 .max_uV = 1800000,
                                 .valid_modes_mask = REGULATOR_MODE_NORMAL,
                                 .valid_ops_mask =
-                                REGULATOR_CHANGE_VOLTAGE |
-                                REGULATOR_CHANGE_STATUS,
+                                REGULATOR_CHANGE_VOLTAGE,
                                 .always_on = 1,
                                 .boot_on = 1,
                         },
diff --git a/arch/arm/mach-u300/include/mach/irqs.h b/arch/arm/mach-u300/include/mach/irqs.h
index ee78a26707eb..ec09c1e07b1a 100644
--- a/arch/arm/mach-u300/include/mach/irqs.h
+++ b/arch/arm/mach-u300/include/mach/irqs.h
@@ -12,101 +12,101 @@
 #ifndef __MACH_IRQS_H
 #define __MACH_IRQS_H
 
-#define IRQ_U300_INTCON0_START          0
-#define IRQ_U300_INTCON1_START          32
+#define IRQ_U300_INTCON0_START          1
+#define IRQ_U300_INTCON1_START          33
 /* These are on INTCON0 - 30 lines */
-#define IRQ_U300_IRQ0_EXT               0
-#define IRQ_U300_IRQ1_EXT               1
-#define IRQ_U300_DMA                    2
-#define IRQ_U300_VIDEO_ENC_0            3
-#define IRQ_U300_VIDEO_ENC_1            4
-#define IRQ_U300_AAIF_RX                5
-#define IRQ_U300_AAIF_TX                6
-#define IRQ_U300_AAIF_VGPIO             7
-#define IRQ_U300_AAIF_WAKEUP            8
-#define IRQ_U300_PCM_I2S0_FRAME         9
-#define IRQ_U300_PCM_I2S0_FIFO          10
-#define IRQ_U300_PCM_I2S1_FRAME         11
-#define IRQ_U300_PCM_I2S1_FIFO          12
-#define IRQ_U300_XGAM_GAMCON            13
-#define IRQ_U300_XGAM_CDI               14
-#define IRQ_U300_XGAM_CDICON            15
+#define IRQ_U300_IRQ0_EXT               1
+#define IRQ_U300_IRQ1_EXT               2
+#define IRQ_U300_DMA                    3
+#define IRQ_U300_VIDEO_ENC_0            4
+#define IRQ_U300_VIDEO_ENC_1            5
+#define IRQ_U300_AAIF_RX                6
+#define IRQ_U300_AAIF_TX                7
+#define IRQ_U300_AAIF_VGPIO             8
+#define IRQ_U300_AAIF_WAKEUP            9
+#define IRQ_U300_PCM_I2S0_FRAME         10
+#define IRQ_U300_PCM_I2S0_FIFO          11
+#define IRQ_U300_PCM_I2S1_FRAME         12
+#define IRQ_U300_PCM_I2S1_FIFO          13
+#define IRQ_U300_XGAM_GAMCON            14
+#define IRQ_U300_XGAM_CDI               15
+#define IRQ_U300_XGAM_CDICON            16
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
 /* MMIACC not used on the DB3210 or DB3350 chips */
-#define IRQ_U300_XGAM_MMIACC            16
+#define IRQ_U300_XGAM_MMIACC            17
 #endif
-#define IRQ_U300_XGAM_PDI               17
-#define IRQ_U300_XGAM_PDICON            18
-#define IRQ_U300_XGAM_GAMEACC           19
-#define IRQ_U300_XGAM_MCIDCT            20
-#define IRQ_U300_APEX                   21
-#define IRQ_U300_UART0                  22
-#define IRQ_U300_SPI                    23
-#define IRQ_U300_TIMER_APP_OS           24
-#define IRQ_U300_TIMER_APP_DD           25
-#define IRQ_U300_TIMER_APP_GP1          26
-#define IRQ_U300_TIMER_APP_GP2          27
-#define IRQ_U300_TIMER_OS               28
-#define IRQ_U300_TIMER_MS               29
-#define IRQ_U300_KEYPAD_KEYBF           30
-#define IRQ_U300_KEYPAD_KEYBR           31
+#define IRQ_U300_XGAM_PDI               18
+#define IRQ_U300_XGAM_PDICON            19
+#define IRQ_U300_XGAM_GAMEACC           20
+#define IRQ_U300_XGAM_MCIDCT            21
+#define IRQ_U300_APEX                   22
+#define IRQ_U300_UART0                  23
+#define IRQ_U300_SPI                    24
+#define IRQ_U300_TIMER_APP_OS           25
+#define IRQ_U300_TIMER_APP_DD           26
+#define IRQ_U300_TIMER_APP_GP1          27
+#define IRQ_U300_TIMER_APP_GP2          28
+#define IRQ_U300_TIMER_OS               29
+#define IRQ_U300_TIMER_MS               30
+#define IRQ_U300_KEYPAD_KEYBF           31
+#define IRQ_U300_KEYPAD_KEYBR           32
 /* These are on INTCON1 - 32 lines */
-#define IRQ_U300_GPIO_PORT0             32
-#define IRQ_U300_GPIO_PORT1             33
-#define IRQ_U300_GPIO_PORT2             34
+#define IRQ_U300_GPIO_PORT0             33
+#define IRQ_U300_GPIO_PORT1             34
+#define IRQ_U300_GPIO_PORT2             35
 
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
     defined(CONFIG_MACH_U300_BS335)
 /* These are for DB3150, DB3200 and DB3350 */
-#define IRQ_U300_WDOG                   35
-#define IRQ_U300_EVHIST                 36
-#define IRQ_U300_MSPRO                  37
-#define IRQ_U300_MMCSD_MCIINTR0         38
-#define IRQ_U300_MMCSD_MCIINTR1         39
-#define IRQ_U300_I2C0                   40
-#define IRQ_U300_I2C1                   41
-#define IRQ_U300_RTC                    42
-#define IRQ_U300_NFIF                   43
-#define IRQ_U300_NFIF2                  44
+#define IRQ_U300_WDOG                   36
+#define IRQ_U300_EVHIST                 37
+#define IRQ_U300_MSPRO                  38
+#define IRQ_U300_MMCSD_MCIINTR0         39
+#define IRQ_U300_MMCSD_MCIINTR1         40
+#define IRQ_U300_I2C0                   41
+#define IRQ_U300_I2C1                   42
+#define IRQ_U300_RTC                    43
+#define IRQ_U300_NFIF                   44
+#define IRQ_U300_NFIF2                  45
 #endif
 
 /* DB3150 and DB3200 have only 45 IRQs */
 #if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
-#define U300_VIC_IRQS_END               45
+#define U300_VIC_IRQS_END               46
 #endif
 
 /* The DB3350-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS335
-#define IRQ_U300_ISP_F0                 45
-#define IRQ_U300_ISP_F1                 46
-#define IRQ_U300_ISP_F2                 47
-#define IRQ_U300_ISP_F3                 48
-#define IRQ_U300_ISP_F4                 49
-#define IRQ_U300_GPIO_PORT3             50
-#define IRQ_U300_SYSCON_PLL_LOCK        51
-#define IRQ_U300_UART1                  52
-#define IRQ_U300_GPIO_PORT4             53
-#define IRQ_U300_GPIO_PORT5             54
-#define IRQ_U300_GPIO_PORT6             55
-#define U300_VIC_IRQS_END               56
+#define IRQ_U300_ISP_F0                 46
+#define IRQ_U300_ISP_F1                 47
+#define IRQ_U300_ISP_F2                 48
+#define IRQ_U300_ISP_F3                 49
+#define IRQ_U300_ISP_F4                 50
+#define IRQ_U300_GPIO_PORT3             51
+#define IRQ_U300_SYSCON_PLL_LOCK        52
+#define IRQ_U300_UART1                  53
+#define IRQ_U300_GPIO_PORT4             54
+#define IRQ_U300_GPIO_PORT5             55
+#define IRQ_U300_GPIO_PORT6             56
+#define U300_VIC_IRQS_END               57
 #endif
 
 /* The DB3210-specific interrupt lines */
 #ifdef CONFIG_MACH_U300_BS365
-#define IRQ_U300_GPIO_PORT3             35
-#define IRQ_U300_GPIO_PORT4             36
-#define IRQ_U300_WDOG                   37
-#define IRQ_U300_EVHIST                 38
-#define IRQ_U300_MSPRO                  39
-#define IRQ_U300_MMCSD_MCIINTR0         40
-#define IRQ_U300_MMCSD_MCIINTR1         41
-#define IRQ_U300_I2C0                   42
-#define IRQ_U300_I2C1                   43
-#define IRQ_U300_RTC                    44
-#define IRQ_U300_NFIF                   45
-#define IRQ_U300_NFIF2                  46
-#define IRQ_U300_SYSCON_PLL_LOCK        47
-#define U300_VIC_IRQS_END               48
+#define IRQ_U300_GPIO_PORT3             36
+#define IRQ_U300_GPIO_PORT4             37
+#define IRQ_U300_WDOG                   38
+#define IRQ_U300_EVHIST                 39
+#define IRQ_U300_MSPRO                  40
+#define IRQ_U300_MMCSD_MCIINTR0         41
+#define IRQ_U300_MMCSD_MCIINTR1         42
+#define IRQ_U300_I2C0                   43
+#define IRQ_U300_I2C1                   44
+#define IRQ_U300_RTC                    45
+#define IRQ_U300_NFIF                   46
+#define IRQ_U300_NFIF2                  47
+#define IRQ_U300_SYSCON_PLL_LOCK        48
+#define U300_VIC_IRQS_END               49
 #endif
 
 /* Maximum 8*7 GPIO lines */
@@ -117,6 +117,6 @@
 #define IRQ_U300_GPIO_END               (U300_VIC_IRQS_END)
 #endif
 
-#define NR_IRQS                         (IRQ_U300_GPIO_END)
+#define NR_IRQS                         (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
 
 #endif
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 880d02ec89d4..ef7099eea0f2 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -17,6 +17,7 @@ config UX500_SOC_DB5500
 config UX500_SOC_DB8500
         bool
         select MFD_DB8500_PRCMU
+        select REGULATOR
         select REGULATOR_DB8500_PRCMU
         select CPU_FREQ_TABLE if CPU_FREQ
 
diff --git a/arch/arm/mach-ux500/mbox-db5500.c b/arch/arm/mach-ux500/mbox-db5500.c
index 2b2d51caf9d8..0127490218cd 100644
--- a/arch/arm/mach-ux500/mbox-db5500.c
+++ b/arch/arm/mach-ux500/mbox-db5500.c
@@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
         return sprintf(buf, "0x%X\n", mbox_value);
 }
 
-static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
+static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
 
 static int mbox_show(struct seq_file *s, void *data)
 {
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index d2058ef8345f..eff5842f6232 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -99,7 +99,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
          */
         write_pen_release(cpu_logical_map(cpu));
 
-        gic_raise_softirq(cpumask_of(cpu), 1);
+        smp_send_reschedule(cpu);
 
         timeout = jiffies + (1 * HZ);
         while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index ff1f7cc11f87..80741992a9fc 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -26,18 +26,23 @@ ENTRY(v6_early_abort)
         mrc     p15, 0, r1, c5, c0, 0           @ get FSR
         mrc     p15, 0, r0, c6, c0, 0           @ get FAR
 /*
- * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR (erratum 326103).
- * The test below covers all the write situations, including Java bytecodes
+ * Faulty SWP instruction on 1136 doesn't set bit 11 in DFSR.
  */
-        bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+#ifdef CONFIG_ARM_ERRATA_326103
+        ldr     ip, =0x4107b36
+        mrc     p15, 0, r3, c0, c0, 0           @ get processor id
+        teq     ip, r3, lsr #4                  @ r0 ARM1136?
+        bne     do_DataAbort
         tst     r5, #PSR_J_BIT                  @ Java?
+        tsteq   r5, #PSR_T_BIT                  @ Thumb?
         bne     do_DataAbort
-        do_thumb_abort fsr=r1, pc=r4, psr=r5, tmp=r3
-        ldreq   r3, [r4]                        @ read aborted ARM instruction
+        bic     r1, r1, #1 << 11                @ clear bit 11 of FSR
+        ldr     r3, [r4]                        @ read aborted ARM instruction
 #ifdef CONFIG_CPU_ENDIAN_BE8
-        reveq   r3, r3
+        rev     r3, r3
 #endif
         do_ldrd_abort tmp=ip, insn=r3
         tst     r3, #1 << 20                    @ L = 0 -> write
         orreq   r1, r1, #1 << 11                @ yes.
+#endif
         b       do_DataAbort
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index a53fd2aaa2f4..2a8e380501e8 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -32,6 +32,7 @@ static void __iomem *l2x0_base;
 static DEFINE_RAW_SPINLOCK(l2x0_lock);
 static u32 l2x0_way_mask;       /* Bitmask of active ways */
 static u32 l2x0_size;
+static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
 
 struct l2x0_regs l2x0_saved_regs;
 
@@ -61,12 +62,7 @@ static inline void cache_sync(void)
 {
         void __iomem *base = l2x0_base;
 
-#ifdef CONFIG_PL310_ERRATA_753970
-        /* write to an unmmapped register */
-        writel_relaxed(0, base + L2X0_DUMMY_REG);
-#else
-        writel_relaxed(0, base + L2X0_CACHE_SYNC);
-#endif
+        writel_relaxed(0, base + sync_reg_offset);
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
@@ -85,10 +81,13 @@ static inline void l2x0_inv_line(unsigned long addr)
 }
 
 #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
+static inline void debug_writel(unsigned long val)
+{
+        if (outer_cache.set_debug)
+                outer_cache.set_debug(val);
+}
 
-#define debug_writel(val)       outer_cache.set_debug(val)
-
-static void l2x0_set_debug(unsigned long val)
+static void pl310_set_debug(unsigned long val)
 {
         writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
 }
@@ -98,7 +97,7 @@ static inline void debug_writel(unsigned long val)
 {
 }
 
-#define l2x0_set_debug  NULL
+#define pl310_set_debug NULL
 #endif
 
 #ifdef CONFIG_PL310_ERRATA_588369
@@ -331,6 +330,11 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
                 else
                         ways = 8;
                 type = "L310";
+#ifdef CONFIG_PL310_ERRATA_753970
+                /* Unmapped register. */
+                sync_reg_offset = L2X0_DUMMY_REG;
+#endif
+                outer_cache.set_debug = pl310_set_debug;
                 break;
         case L2X0_CACHE_ID_PART_L210:
                 ways = (aux >> 13) & 0xf;
@@ -379,7 +383,6 @@ void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
         outer_cache.flush_all = l2x0_flush_all;
         outer_cache.inv_all = l2x0_inv_all;
         outer_cache.disable = l2x0_disable;
-        outer_cache.set_debug = l2x0_set_debug;
 
         printk(KERN_INFO "%s cache controller enabled\n", type);
         printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 595079fa9d1d..8f5813bbffb5 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -293,11 +293,11 @@ EXPORT_SYMBOL(pfn_valid);
 #endif
 
 #ifndef CONFIG_SPARSEMEM
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
 }
 #else
-static void arm_memory_present(void)
+static void __init arm_memory_present(void)
 {
         struct memblock_region *reg;
 
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index b86f8933ff91..2c7cf2f9c837 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -618,8 +618,8 @@ static void __init alloc_init_section(pud_t *pud, unsigned long addr,
         }
 }
 
-static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end,
-        unsigned long phys, const struct mem_type *type)
+static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
+        unsigned long end, unsigned long phys, const struct mem_type *type)
 {
         pud_t *pud = pud_offset(pgd, addr);
         unsigned long next;
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index ecdb3da0dea9..c58d896cd5c3 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -916,6 +916,13 @@ void omap_start_dma(int lch)
                         l |= OMAP_DMA_CCR_BUFFERING_DISABLE;
         l |= OMAP_DMA_CCR_EN;
 
+        /*
+         * As dma_write() uses IO accessors which are weakly ordered, there
+         * is no guarantee that data in coherent DMA memory will be visible
+         * to the DMA device.  Add a memory barrier here to ensure that any
+         * such data is visible prior to enabling DMA.
+         */
+        mb();
         p->dma_write(l, CCR, lch);
 
         dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
@@ -965,6 +972,13 @@ void omap_stop_dma(int lch)
                 p->dma_write(l, CCR, lch);
         }
 
+        /*
+         * Ensure that data transferred by DMA is visible to any access
+         * after DMA has been disabled.  This is important for coherent
+         * DMA regions.
+         */
+        mb();
+
         if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
                 int next_lch, cur_lch = lch;
                 char dma_chan_link_map[dma_lch_count];
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 8070145ccb98..3f26db4ee8e6 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -305,6 +305,7 @@ struct omap_hwmod_sysc_fields {
  * @rev_offs: IP block revision register offset (from module base addr)
  * @sysc_offs: OCP_SYSCONFIG register offset (from module base addr)
  * @syss_offs: OCP_SYSSTATUS register offset (from module base addr)
+ * @srst_udelay: Delay needed after doing a softreset in usecs
  * @idlemodes: One or more of {SIDLE,MSTANDBY}_{OFF,FORCE,SMART}
  * @sysc_flags: SYS{C,S}_HAS* flags indicating SYSCONFIG bits supported
  * @clockact: the default value of the module CLOCKACTIVITY bits
@@ -330,9 +331,10 @@ struct omap_hwmod_class_sysconfig {
         u16 sysc_offs;
         u16 syss_offs;
         u16 sysc_flags;
+        struct omap_hwmod_sysc_fields *sysc_fields;
+        u8 srst_udelay;
         u8 idlemodes;
         u8 clockact;
-        struct omap_hwmod_sysc_fields *sysc_fields;
 };
 
 /**
diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c
index eec98afa0f83..f9a8c5341ee9 100644
--- a/arch/arm/plat-omap/sram.c
+++ b/arch/arm/plat-omap/sram.c
@@ -348,7 +348,6 @@ u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 }
 
-#ifdef CONFIG_PM
 void omap3_sram_restore_context(void)
 {
         omap_sram_ceil = omap_sram_base + omap_sram_size;
@@ -358,17 +357,18 @@ void omap3_sram_restore_context(void)
                                omap3_sram_configure_core_dpll_sz);
         omap_push_sram_idle();
 }
-#endif /* CONFIG_PM */
-
-#endif /* CONFIG_ARCH_OMAP3 */
 
 static inline int omap34xx_sram_init(void)
 {
-#if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
         omap3_sram_restore_context();
-#endif
         return 0;
 }
+#else
+static inline int omap34xx_sram_init(void)
+{
+        return 0;
+}
+#endif /* CONFIG_ARCH_OMAP3 */
 
 static inline int am33xx_sram_init(void)
 {
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 317e246ffc56..e834c5ef437c 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -18,6 +18,8 @@
 #ifndef __PLAT_S3C_SDHCI_H
 #define __PLAT_S3C_SDHCI_H __FILE__
 
+#include <plat/devs.h>
+
 struct platform_device;
 struct mmc_host;
 struct mmc_card;
@@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
 
 #endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
 
+static inline void s3c_sdhci_setname(int id, char *name)
+{
+        switch (id) {
+#ifdef CONFIG_S3C_DEV_HSMMC
+        case 0:
+                s3c_device_hsmmc0.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC1
+        case 1:
+                s3c_device_hsmmc1.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC2
+        case 2:
+                s3c_device_hsmmc2.name = name;
+                break;
+#endif
+#ifdef CONFIG_S3C_DEV_HSMMC3
+        case 3:
+                s3c_device_hsmmc3.name = name;
+                break;
+#endif
+        }
+}
+
 #endif /* __PLAT_S3C_SDHCI_H */
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 858748eaa144..bc683b8219b5 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -17,6 +17,8 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/init.h>
+#include <linux/uaccess.h>
+#include <linux/user.h>
 
 #include <asm/cp15.h>
 #include <asm/cputype.h>
@@ -529,6 +531,103 @@ void vfp_flush_hwstate(struct thread_info *thread)
 }
 
 /*
+ * Save the current VFP state into the provided structures and prepare
+ * for entry into a new function (signal handler).
+ */
+int vfp_preserve_user_clear_hwstate(struct user_vfp __user *ufp,
+                                    struct user_vfp_exc __user *ufp_exc)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+        int err = 0;
+
+        /* Ensure that the saved hwstate is up-to-date. */
+        vfp_sync_hwstate(thread);
+
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_to_user(&ufp->fpregs, &hwstate->fpregs,
+                              sizeof(hwstate->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __put_user_error(hwstate->fpscr, &ufp->fpscr, err);
+
+        /*
+         * Copy the exception registers.
+         */
+        __put_user_error(hwstate->fpexc, &ufp_exc->fpexc, err);
+        __put_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+        __put_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+
+        if (err)
+                return -EFAULT;
+
+        /* Ensure that VFP is disabled. */
+        vfp_flush_hwstate(thread);
+
+        /*
+         * As per the PCS, clear the length and stride bits for function
+         * entry.
+         */
+        hwstate->fpscr &= ~(FPSCR_LENGTH_MASK | FPSCR_STRIDE_MASK);
+
+        /*
+         * Disable VFP in the hwstate so that we can detect if it gets
+         * used.
+         */
+        hwstate->fpexc &= ~FPEXC_EN;
+        return 0;
+}
+
+/* Sanitise and restore the current VFP state from the provided structures. */
+int vfp_restore_user_hwstate(struct user_vfp __user *ufp,
+                             struct user_vfp_exc __user *ufp_exc)
+{
+        struct thread_info *thread = current_thread_info();
+        struct vfp_hard_struct *hwstate = &thread->vfpstate.hard;
+        unsigned long fpexc;
+        int err = 0;
+
+        /*
+         * If VFP has been used, then disable it to avoid corrupting
+         * the new thread state.
+         */
+        if (hwstate->fpexc & FPEXC_EN)
+                vfp_flush_hwstate(thread);
+
+        /*
+         * Copy the floating point registers. There can be unused
+         * registers see asm/hwcap.h for details.
+         */
+        err |= __copy_from_user(&hwstate->fpregs, &ufp->fpregs,
+                                sizeof(hwstate->fpregs));
+        /*
+         * Copy the status and control register.
+         */
+        __get_user_error(hwstate->fpscr, &ufp->fpscr, err);
+
+        /*
+         * Sanitise and restore the exception registers.
+         */
+        __get_user_error(fpexc, &ufp_exc->fpexc, err);
+
+        /* Ensure the VFP is enabled. */
+        fpexc |= FPEXC_EN;
+
+        /* Ensure FPINST2 is invalid and the exception flag is cleared. */
+        fpexc &= ~(FPEXC_EX | FPEXC_FP2V);
+        hwstate->fpexc = fpexc;
+
+        __get_user_error(hwstate->fpinst, &ufp_exc->fpinst, err);
+        __get_user_error(hwstate->fpinst2, &ufp_exc->fpinst2, err);
+
+        return err ? -EFAULT : 0;
+}
+
+/*
  * VFP hardware can lose all context when a CPU goes offline.
  * As we will be running in SMP mode with CPU hotplug, we will save the
  * hardware state at every thread switch.  We clear our held state when
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index 1633a6f306c0..85038f54354d 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
         .name = "rtc-bfin",
         .id   = -1,
 };
-#endif
+#endif  /* CONFIG_RTC_DRV_BFIN */
 
 #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_UART0
@@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
                 .platform_data = &bfin_uart0_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART0 */
 #ifdef CONFIG_SERIAL_BFIN_UART1
 static struct resource bfin_uart1_resources[] = {
         {
@@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
                 .platform_data = &bfin_uart1_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART1 */
 #ifdef CONFIG_SERIAL_BFIN_UART2
 static struct resource bfin_uart2_resources[] = {
         {
@@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
                 .platform_data = &bfin_uart2_peripherals, /* Passed to driver */
         },
 };
-#endif
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_UART2 */
+#endif  /* CONFIG_SERIAL_BFIN */
 
 #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
 #ifdef CONFIG_BFIN_SIR0
@@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
         .num_resources = ARRAY_SIZE(bfin_sir0_resources),
         .resource = bfin_sir0_resources,
 };
-#endif
+#endif  /* CONFIG_BFIN_SIR0 */
 #ifdef CONFIG_BFIN_SIR1
 static struct resource bfin_sir1_resources[] = {
         {
@@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
         .num_resources = ARRAY_SIZE(bfin_sir1_resources),
         .resource = bfin_sir1_resources,
 };
-#endif
+#endif  /* CONFIG_BFIN_SIR1 */
 #ifdef CONFIG_BFIN_SIR2
 static struct resource bfin_sir2_resources[] = {
         {
@@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
         .num_resources = ARRAY_SIZE(bfin_sir2_resources),
         .resource = bfin_sir2_resources,
 };
-#endif
-#endif
+#endif  /* CONFIG_BFIN_SIR2 */
+#endif  /* CONFIG_BFIN_SIR */
 
 #if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
 #ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
@@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
                 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT0_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
 static struct resource bfin_sport1_uart_resources[] = {
         {
@@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
                 .platform_data = &bfin_sport1_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT1_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
 static struct resource bfin_sport2_uart_resources[] = {
         {
@@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
                 .platform_data = &bfin_sport2_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT2_UART */
 #ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
 static struct resource bfin_sport3_uart_resources[] = {
         {
@@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
                 .platform_data = &bfin_sport3_peripherals, /* Passed to driver */
         },
 };
-#endif
-#endif
+#endif  /* CONFIG_SERIAL_BFIN_SPORT3_UART */
+#endif  /* CONFIG_SERIAL_BFIN_SPORT */
 
 #if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
 static unsigned short bfin_can_peripherals[] = {
@@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
                 .platform_data = &bfin_can_peripherals, /* Passed to driver */
         },
 };
-#endif
+#endif  /* CONFIG_CAN_BFIN */
 
 /*
  *  USB-LAN EzExtender board
@@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
                 .platform_data  = &smc91x_info,
         },
 };
-#endif
+#endif  /* CONFIG_SMC91X */
 
 #if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
 /* all SPI peripherals info goes here */
@@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
 static struct bfin5xx_spi_chip spi_flash_chip_info = {
         .enable_dma = 0,         /* use dma transfer with this chip*/
 };
-#endif
+#endif  /* CONFIG_MTD_M25P80 */
+#endif  /* CONFIG_SPI_BFIN5XX */
 
 #if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
 #include <linux/spi/ad7879.h>
@@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
         .gpio_export            = 1,    /* Export GPIO to gpiolib */
         .gpio_base              = -1,   /* Dynamic allocation */
 };
-#endif
+#endif  /* CONFIG_TOUCHSCREEN_AD7879 */
 
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
 #include <asm/bfin-lq035q1.h>
@@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
                 .platform_data = &bfin_lq035q1_data,
         },
 };
-#endif
+#endif  /* CONFIG_FB_BFIN_LQ035Q1 */
 
 static struct spi_board_info bf538_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
@@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .controller_data = &spi_flash_chip_info,
                 .mode = SPI_MODE_3,
         },
-#endif
+#endif  /* CONFIG_MTD_M25P80 */
 #if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
         {
                 .modalias = "ad7879",
@@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .chip_select = 1,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
-#endif
+#endif  /* CONFIG_TOUCHSCREEN_AD7879_SPI */
 #if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
         {
                 .modalias = "bfin-lq035q1-spi",
@@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .chip_select = 2,
                 .mode = SPI_CPHA | SPI_CPOL,
         },
-#endif
+#endif  /* CONFIG_FB_BFIN_LQ035Q1 */
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
         {
                 .modalias = "spidev",
@@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
                 .bus_num = 0,
                 .chip_select = 1,
         },
-#endif
+#endif  /* CONFIG_SPI_SPIDEV */
 };
 
 /* SPI (0) */
@@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
                 },
 };
 
-#endif  /* spi master and devices */
-
 #if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
 static struct resource bfin_twi0_resource[] = {
         [0] = {
@@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
         .num_resources = ARRAY_SIZE(bfin_twi1_resource),
         .resource = bfin_twi1_resource,
 };
-#endif
-#endif
+#endif  /* CONFIG_BF542 */
+#endif  /* CONFIG_I2C_BLACKFIN_TWI */
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 #include <linux/gpio_keys.h>
diff --git a/arch/hexagon/kernel/dma.c b/arch/hexagon/kernel/dma.c
index 37302218ca4a..0f2367cc5493 100644
--- a/arch/hexagon/kernel/dma.c
+++ b/arch/hexagon/kernel/dma.c
@@ -22,6 +22,7 @@
 #include <linux/bootmem.h>
 #include <linux/genalloc.h>
 #include <asm/dma-mapping.h>
+#include <linux/module.h>
 
 struct dma_map_ops *dma_ops;
 EXPORT_SYMBOL(dma_ops);
diff --git a/arch/hexagon/kernel/process.c b/arch/hexagon/kernel/process.c
index 18c4f0b0f4ba..ff02821bfb7e 100644
--- a/arch/hexagon/kernel/process.c
+++ b/arch/hexagon/kernel/process.c
@@ -1,7 +1,7 @@
 /*
  * Process creation support for Hexagon
  *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
 void cpu_idle(void)
 {
         while (1) {
-                tick_nohz_stop_sched_tick(1);
+                tick_nohz_idle_enter();
                 local_irq_disable();
                 while (!need_resched()) {
                         idle_sleep();
@@ -97,7 +97,7 @@ void cpu_idle(void)
                         local_irq_disable();
                 }
                 local_irq_enable();
-                tick_nohz_restart_sched_tick();
+                tick_nohz_idle_exit();
                 schedule();
         }
 }
diff --git a/arch/hexagon/kernel/ptrace.c b/arch/hexagon/kernel/ptrace.c
index 32342de1a79c..96c3b2c4dbad 100644
--- a/arch/hexagon/kernel/ptrace.c
+++ b/arch/hexagon/kernel/ptrace.c
@@ -28,6 +28,7 @@
 #include <linux/ptrace.h>
 #include <linux/regset.h>
 #include <linux/user.h>
+#include <linux/elf.h>
 
 #include <asm/user.h>
 
diff --git a/arch/hexagon/kernel/smp.c b/arch/hexagon/kernel/smp.c
index 9b44a9e2d05a..1298141874a3 100644
--- a/arch/hexagon/kernel/smp.c
+++ b/arch/hexagon/kernel/smp.c
@@ -1,7 +1,7 @@
 /*
  * SMP support for Hexagon
  *
- * Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and
@@ -28,6 +28,7 @@
 #include <linux/sched.h>
 #include <linux/smp.h>
 #include <linux/spinlock.h>
+#include <linux/cpu.h>
 
 #include <asm/time.h>    /*  timer_interrupt  */
 #include <asm/hexagon_vm.h>
@@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
 
         printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
 
+        notify_cpu_starting(cpu);
+
+        ipi_call_lock();
         set_cpu_online(cpu, true);
+        ipi_call_unlock();
+
         local_irq_enable();
 
         cpu_idle();
diff --git a/arch/hexagon/kernel/time.c b/arch/hexagon/kernel/time.c
index 6bee15c9c113..5d9b33b67935 100644
--- a/arch/hexagon/kernel/time.c
+++ b/arch/hexagon/kernel/time.c
@@ -28,6 +28,7 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/module.h>
 
 #include <asm/timer-regs.h>
 #include <asm/hexagon_vm.h>
diff --git a/arch/hexagon/kernel/vdso.c b/arch/hexagon/kernel/vdso.c
index f212a453b527..5d39f42f7085 100644
--- a/arch/hexagon/kernel/vdso.c
+++ b/arch/hexagon/kernel/vdso.c
@@ -21,6 +21,7 @@
 #include <linux/err.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
+#include <linux/binfmts.h>
 
 #include <asm/vdso.h>
 
diff --git a/arch/ia64/kernel/perfmon.c b/arch/ia64/kernel/perfmon.c
index 9d0fd7d5bb82..f00ba025375d 100644
--- a/arch/ia64/kernel/perfmon.c
+++ b/arch/ia64/kernel/perfmon.c
@@ -604,12 +604,6 @@ pfm_unprotect_ctx_ctxsw(pfm_context_t *x, unsigned long f)
         spin_unlock(&(x)->ctx_lock);
 }
 
-static inline unsigned int
-pfm_do_munmap(struct mm_struct *mm, unsigned long addr, size_t len, int acct)
-{
-        return do_munmap(mm, addr, len);
-}
-
 static inline unsigned long 
 pfm_get_unmapped_area(struct file *file, unsigned long addr, unsigned long len, unsigned long pgoff, unsigned long flags, unsigned long exec)
 {
@@ -1458,8 +1452,9 @@ pfm_unreserve_session(pfm_context_t *ctx, int is_syswide, unsigned int cpu)
  * a PROTECT_CTX() section.
  */
 static int
-pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long size)
+pfm_remove_smpl_mapping(void *vaddr, unsigned long size)
 {
+        struct task_struct *task = current;
         int r;
 
         /* sanity checks */
@@ -1473,13 +1468,8 @@ pfm_remove_smpl_mapping(struct task_struct *task, void *vaddr, unsigned long siz
         /*
          * does the actual unmapping
          */
-        down_write(&task->mm->mmap_sem);
+        r = vm_munmap((unsigned long)vaddr, size);
 
-        DPRINT(("down_write done smpl_vaddr=%p size=%lu\n", vaddr, size));
-
-        r = pfm_do_munmap(task->mm, (unsigned long)vaddr, size, 0);
-
-        up_write(&task->mm->mmap_sem);
         if (r !=0) {
                 printk(KERN_ERR "perfmon: [%d] unable to unmap sampling buffer @%p size=%lu\n", task_pid_nr(task), vaddr, size);
         }
@@ -1945,7 +1935,7 @@ pfm_flush(struct file *filp, fl_owner_t id)
          * because some VM function reenables interrupts.
          *
          */
-        if (smpl_buf_vaddr) pfm_remove_smpl_mapping(current, smpl_buf_vaddr, smpl_buf_size);
+        if (smpl_buf_vaddr) pfm_remove_smpl_mapping(smpl_buf_vaddr, smpl_buf_size);
 
         return 0;
 }
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index f5104b7c52cd..463fb3bbe11e 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -1174,7 +1174,7 @@ out:
 
 bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
 {
-        return irqchip_in_kernel(vcpu->kcm) == (vcpu->arch.apic != NULL);
+        return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
 }
 
 int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
diff --git a/arch/m68k/configs/m5275evb_defconfig b/arch/m68k/configs/m5275evb_defconfig
index 33c32aeca12b..a1230e82bb1e 100644
--- a/arch/m68k/configs/m5275evb_defconfig
+++ b/arch/m68k/configs/m5275evb_defconfig
@@ -49,7 +49,6 @@ CONFIG_BLK_DEV_RAM=y
 CONFIG_NETDEVICES=y
 CONFIG_NET_ETHERNET=y
 CONFIG_FEC=y
-CONFIG_FEC2=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 CONFIG_PPP=y
diff --git a/arch/m68k/platform/527x/config.c b/arch/m68k/platform/527x/config.c
index 7ed848c3b848..f91a53294c35 100644
--- a/arch/m68k/platform/527x/config.c
+++ b/arch/m68k/platform/527x/config.c
@@ -74,9 +74,7 @@ static void __init m527x_fec_init(void)
         writew(par | 0xf00, MCF_IPSBAR + 0x100082);
         v = readb(MCF_IPSBAR + 0x100078);
         writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
-#endif
 
-#ifdef CONFIG_FEC2
         /* Set multi-function pins to ethernet mode for fec1 */
         par = readw(MCF_IPSBAR + 0x100082);
         writew(par | 0xa0, MCF_IPSBAR + 0x100082);
diff --git a/arch/m68k/platform/68EZ328/Makefile b/arch/m68k/platform/68EZ328/Makefile
index ee97735a242c..b44d799b1115 100644
--- a/arch/m68k/platform/68EZ328/Makefile
+++ b/arch/m68k/platform/68EZ328/Makefile
@@ -3,9 +3,3 @@
 #
 
 obj-y := config.o
-
-extra-y := bootlogo.rh
-
-$(obj)/bootlogo.rh: $(src)/bootlogo.h
-        perl $(src)/../68328/bootlogo.pl < $(src)/bootlogo.h \
-                > $(obj)/bootlogo.rh
diff --git a/arch/m68k/platform/68VZ328/Makefile b/arch/m68k/platform/68VZ328/Makefile
index 447ffa0fd7c7..a49d75e65489 100644
--- a/arch/m68k/platform/68VZ328/Makefile
+++ b/arch/m68k/platform/68VZ328/Makefile
@@ -3,14 +3,9 @@
 #
 
 obj-y           := config.o
-logo-$(UCDIMM)  := bootlogo.rh
-logo-$(DRAGEN2) := screen.h
-extra-y         := $(logo-y)
-
-$(obj)/bootlogo.rh: $(src)/../68EZ328/bootlogo.h
-        perl $(src)/bootlogo.pl < $(src)/../68328/bootlogo.h > $(obj)/bootlogo.rh
+extra-$(DRAGEN2):= screen.h
 
 $(obj)/screen.h: $(src)/screen.xbm $(src)/xbm2lcd.pl
         perl $(src)/xbm2lcd.pl < $(src)/screen.xbm > $(obj)/screen.h
 
-clean-files := $(obj)/screen.h $(obj)/bootlogo.rh
+clean-files := $(obj)/screen.h
diff --git a/arch/m68k/platform/68EZ328/bootlogo.h b/arch/m68k/platform/68VZ328/bootlogo.h
index e842bdae5839..b38e2b255142 100644
--- a/arch/m68k/platform/68EZ328/bootlogo.h
+++ b/arch/m68k/platform/68VZ328/bootlogo.h
@@ -1,6 +1,6 @@
 #define splash_width 640
 #define splash_height 480
-static unsigned char splash_bits[] = {
+unsigned char __attribute__ ((aligned(16))) bootlogo_bits[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
diff --git a/arch/m68k/platform/coldfire/device.c b/arch/m68k/platform/coldfire/device.c
index fa50c48292ff..7af97362b95c 100644
--- a/arch/m68k/platform/coldfire/device.c
+++ b/arch/m68k/platform/coldfire/device.c
@@ -114,7 +114,7 @@ static struct resource mcf_fec1_resources[] = {
 
 static struct platform_device mcf_fec1 = {
         .name                   = "fec",
-        .id                     = 0,
+        .id                     = 1,
         .num_resources          = ARRAY_SIZE(mcf_fec1_resources),
         .resource               = mcf_fec1_resources,
 };
diff --git a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
index e21507052066..9c717bf98ffe 100644
--- a/arch/mips/ath79/dev-wmac.c
+++ b/arch/mips/ath79/dev-wmac.c
@@ -58,8 +58,8 @@ static void __init ar913x_wmac_setup(void)
 
 static int ar933x_wmac_reset(void)
 {
-        ath79_device_reset_clear(AR933X_RESET_WMAC);
         ath79_device_reset_set(AR933X_RESET_WMAC);
+        ath79_device_reset_clear(AR933X_RESET_WMAC);
 
         return 0;
 }
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h
index a865c983c70a..5ad1a9c113c6 100644
--- a/arch/mips/include/asm/mach-jz4740/irq.h
+++ b/arch/mips/include/asm/mach-jz4740/irq.h
@@ -45,7 +45,7 @@
 #define JZ4740_IRQ_LCD          JZ4740_IRQ(30)
 
 /* 2nd-level interrupts */
-#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (X))
+#define JZ4740_IRQ_DMA(x)       (JZ4740_IRQ(32) + (x))
 
 #define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x))
 #define JZ4740_IRQ_GPIO(x)      (JZ4740_IRQ(48) + (x))
diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h
index 73c0d45798de..9b02cfba7449 100644
--- a/arch/mips/include/asm/mmu_context.h
+++ b/arch/mips/include/asm/mmu_context.h
@@ -37,12 +37,6 @@ extern void tlbmiss_handler_setup_pgd(unsigned long pgd);
                 write_c0_xcontext((unsigned long) smp_processor_id() << 51); \
         } while (0)
 
-
-static inline unsigned long get_current_pgd(void)
-{
-        return PHYS_TO_XKSEG_CACHED((read_c0_context() >> 11) & ~0xfffUL);
-}
-
 #else /* CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
 
 /*
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 185ca00c4c84..d5a338a1739c 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -257,11 +257,8 @@ asmlinkage int sys_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -286,11 +283,8 @@ asmlinkage int sys_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -362,10 +356,7 @@ asmlinkage void sys_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
 
         sig = restore_sigcontext(&regs, &frame->sf_sc);
         if (sig < 0)
@@ -401,10 +392,7 @@ asmlinkage void sys_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
         if (sig < 0)
@@ -580,12 +568,7 @@ static int handle_signal(unsigned long sig, siginfo_t *info,
         if (ret)
                 return ret;
 
-        spin_lock_irq(&current->sighand->siglock);
-        sigorsets(&current->blocked, &current->blocked, &ka->sa.sa_mask);
-        if (!(ka->sa.sa_flags & SA_NODEFER))
-                sigaddset(&current->blocked, sig);
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        block_sigmask(ka, sig);
 
         return ret;
 }
diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c
index 06b5da392e24..ac3b8d89aae5 100644
--- a/arch/mips/kernel/signal32.c
+++ b/arch/mips/kernel/signal32.c
@@ -290,11 +290,8 @@ asmlinkage int sys32_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -318,11 +315,8 @@ asmlinkage int sys32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
                 return -EFAULT;
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -488,10 +482,7 @@ asmlinkage void sys32_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&blocked, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = blocked;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&blocked);
 
         sig = restore_sigcontext32(&regs, &frame->sf_sc);
         if (sig < 0)
@@ -529,10 +520,7 @@ asmlinkage void sys32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         sig = restore_sigcontext32(&regs, &frame->rs_uc.uc_mcontext);
         if (sig < 0)
diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c
index ae29e894ab8d..86eb4b04631c 100644
--- a/arch/mips/kernel/signal_n32.c
+++ b/arch/mips/kernel/signal_n32.c
@@ -93,11 +93,8 @@ asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs)
         sigset_from_compat(&newset, &uset);
         sigdelsetmask(&newset, ~_BLOCKABLE);
 
-        spin_lock_irq(&current->sighand->siglock);
         current->saved_sigmask = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&newset);
 
         current->state = TASK_INTERRUPTIBLE;
         schedule();
@@ -121,10 +118,7 @@ asmlinkage void sysn32_rt_sigreturn(nabi_no_regargs struct pt_regs regs)
                 goto badframe;
 
         sigdelsetmask(&set, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        current->blocked = set;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
+        set_current_blocked(&set);
 
         sig = restore_sigcontext(&regs, &frame->rs_uc.uc_mcontext);
         if (sig < 0)
diff --git a/arch/parisc/kernel/pdc_cons.c b/arch/parisc/kernel/pdc_cons.c
index 4f004596a6e7..0b3393381a81 100644
--- a/arch/parisc/kernel/pdc_cons.c
+++ b/arch/parisc/kernel/pdc_cons.c
@@ -104,7 +104,7 @@ static int pdc_console_tty_open(struct tty_struct *tty, struct file *filp)
 
 static void pdc_console_tty_close(struct tty_struct *tty, struct file *filp)
 {
-        if (!tty->count) {
+        if (tty->count == 1) {
                 del_timer_sync(&pdc_console_timer);
                 tty_port_tty_set(&tty_port, NULL);
         }
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
new file mode 100644
index 000000000000..1cf0b77b1efe
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
@@ -0,0 +1,43 @@
+/*
+ * PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
+ *
+ * Copyright 2012 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+message@42400 {
+        compatible = "fsl,mpic-v3.1-msgr";
+        reg = <0x42400 0x200>;
+        interrupts = <
+                0xb4 2 0 0
+                0xb5 2 0 0
+                0xb6 2 0 0
+                0xb7 2 0 0>;
+};
diff --git a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
index fdedf7b1fe0f..71c30eb10056 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi
@@ -53,6 +53,16 @@ timer@41100 {
                       3 0 3 0>;
 };
 
+message@41400 {
+        compatible = "fsl,mpic-v3.1-msgr";
+        reg = <0x41400 0x200>;
+        interrupts = <
+                0xb0 2 0 0
+                0xb1 2 0 0
+                0xb2 2 0 0
+                0xb3 2 0 0>;
+};
+
 msi@41600 {
         compatible = "fsl,mpic-msi";
         reg = <0x41600 0x80>;
diff --git a/arch/powerpc/include/asm/exception-64s.h b/arch/powerpc/include/asm/exception-64s.h
index 548da3aa0a30..d58fc4e4149c 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -288,13 +288,6 @@ label##_hv:								\
 /* Exception addition: Hard disable interrupts */
 #define DISABLE_INTS    SOFT_DISABLE_INTS(r10,r11)
 
-/* Exception addition: Keep interrupt state */
-#define ENABLE_INTS                             \
-        ld      r11,PACAKMSR(r13);              \
-        ld      r12,_MSR(r1);                   \
-        rlwimi  r11,r12,0,MSR_EE;               \
-        mtmsrd  r11,1
-
 #define ADD_NVGPRS                              \
         bl      .save_nvgprs
 
diff --git a/arch/powerpc/include/asm/irq.h b/arch/powerpc/include/asm/irq.h
index e648af92ced1..0e40843a1c6e 100644
--- a/arch/powerpc/include/asm/irq.h
+++ b/arch/powerpc/include/asm/irq.h
@@ -18,10 +18,6 @@
 #include <linux/atomic.h>
 
 
-/* Define a way to iterate across irqs. */
-#define for_each_irq(i) \
-        for ((i) = 0; (i) < NR_IRQS; ++(i))
-
 extern atomic_t ppc_n_lost_interrupts;
 
 /* This number is used when no interrupt has been assigned */
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h
index c65b9294376e..c9f698a994be 100644
--- a/arch/powerpc/include/asm/mpic.h
+++ b/arch/powerpc/include/asm/mpic.h
@@ -275,9 +275,6 @@ struct mpic
         unsigned int            isu_mask;
         /* Number of sources */
         unsigned int            num_sources;
-        /* default senses array */
-        unsigned char           *senses;
-        unsigned int            senses_count;
 
         /* vector numbers used for internal sources (ipi/timers) */
         unsigned int            ipi_vecs[4];
@@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                             phys_addr_t phys_addr);
 
-/* Set default sense codes
- *
- * @mpic:       controller
- * @senses:     array of sense codes
- * @count:      size of above array
- *
- * Optionally provide an array (indexed on hardware interrupt numbers
- * for this MPIC) of default sense codes for the chip. Those are linux
- * sense codes IRQ_TYPE_*
- *
- * The driver gets ownership of the pointer, don't dispose of it or
- * anything like that. __init only.
- */
-extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
-
 
 /* Initialize the controller. After this has been called, none of the above
  * should be called again for this mpic
diff --git a/arch/powerpc/include/asm/mpic_msgr.h b/arch/powerpc/include/asm/mpic_msgr.h
index 3ec37dc9003e..326d33ca55cd 100644
--- a/arch/powerpc/include/asm/mpic_msgr.h
+++ b/arch/powerpc/include/asm/mpic_msgr.h
@@ -13,6 +13,7 @@
 
 #include <linux/types.h>
 #include <linux/spinlock.h>
+#include <asm/smp.h>
 
 struct mpic_msgr {
         u32 __iomem *base;
diff --git a/arch/powerpc/include/asm/reg_booke.h b/arch/powerpc/include/asm/reg_booke.h
index b86faa9107da..8a97aa7289d3 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -15,11 +15,6 @@
 #ifndef __ASM_POWERPC_REG_BOOKE_H__
 #define __ASM_POWERPC_REG_BOOKE_H__
 
-#ifdef CONFIG_BOOKE_WDT
-extern u32 booke_wdt_enabled;
-extern u32 booke_wdt_period;
-#endif /* CONFIG_BOOKE_WDT */
-
 /* Machine State Register (MSR) Fields */
 #define MSR_GS          (1<<28) /* Guest state */
 #define MSR_UCLE        (1<<26) /* User-mode cache lock enable */
diff --git a/arch/powerpc/kernel/entry_64.S b/arch/powerpc/kernel/entry_64.S
index f8a7a1a1a9f4..fc6015027a86 100644
--- a/arch/powerpc/kernel/entry_64.S
+++ b/arch/powerpc/kernel/entry_64.S
@@ -767,16 +767,6 @@ do_work:
         SOFT_DISABLE_INTS(r3,r4)
 1:      bl      .preempt_schedule_irq
 
-        /* Hard-disable interrupts again (and update PACA) */
-#ifdef CONFIG_PPC_BOOK3E
-        wrteei  0
-#else
-        ld      r10,PACAKMSR(r13) /* Get kernel MSR without EE */
-        mtmsrd  r10,1
-#endif /* CONFIG_PPC_BOOK3E */
-        li      r0,PACA_IRQ_HARD_DIS
-        stb     r0,PACAIRQHAPPENED(r13)
-
         /* Re-test flags and eventually loop */
         clrrdi  r9,r1,THREAD_SHIFT
         ld      r4,TI_FLAGS(r9)
@@ -787,14 +777,6 @@ do_work:
 user_work:
 #endif /* CONFIG_PREEMPT */
 
-        /* Enable interrupts */
-#ifdef CONFIG_PPC_BOOK3E
-        wrteei  1
-#else
-        ori     r10,r10,MSR_EE
-        mtmsrd  r10,1
-#endif /* CONFIG_PPC_BOOK3E */
-
         andi.   r0,r4,_TIF_NEED_RESCHED
         beq     1f
         bl      .restore_interrupts
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index cb705fdbb458..8f880bc77c56 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -768,8 +768,8 @@ alignment_common:
         std     r3,_DAR(r1)
         std     r4,_DSISR(r1)
         bl      .save_nvgprs
+        DISABLE_INTS
         addi    r3,r1,STACK_FRAME_OVERHEAD
-        ENABLE_INTS
         bl      .alignment_exception
         b       .ret_from_except
 
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 5ec1b2354ca6..c6c6f3b7f8cd 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -260,11 +260,17 @@ EXPORT_SYMBOL(arch_local_irq_restore);
  * if they are currently disabled. This is typically called before
  * schedule() or do_signal() when returning to userspace. We do it
  * in C to avoid the burden of dealing with lockdep etc...
+ *
+ * NOTE: This is called with interrupts hard disabled but not marked
+ * as such in paca->irq_happened, so we need to resync this.
  */
 void restore_interrupts(void)
 {
-        if (irqs_disabled())
+        if (irqs_disabled()) {
+                local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
                 local_irq_enable();
+        } else
+                __hard_irq_enable();
 }
 
 #endif /* CONFIG_PPC64 */
@@ -330,14 +336,10 @@ void migrate_irqs(void)
 
         alloc_cpumask_var(&mask, GFP_KERNEL);
 
-        for_each_irq(irq) {
+        for_each_irq_desc(irq, desc) {
                 struct irq_data *data;
                 struct irq_chip *chip;
 
-                desc = irq_to_desc(irq);
-                if (!desc)
-                        continue;
-
                 data = irq_desc_get_irq_data(desc);
                 if (irqd_is_per_cpu(data))
                         continue;
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index c957b1202bdc..5df777794403 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -23,14 +23,11 @@
 
 void machine_kexec_mask_interrupts(void) {
         unsigned int i;
+        struct irq_desc *desc;
 
-        for_each_irq(i) {
-                struct irq_desc *desc = irq_to_desc(i);
+        for_each_irq_desc(i, desc) {
                 struct irq_chip *chip;
 
-                if (!desc)
-                        continue;
-
                 chip = irq_desc_get_chip(desc);
                 if (!chip)
                         continue;
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c
index 9825f29d1faf..ec8a53fa9e8f 100644
--- a/arch/powerpc/kernel/setup_32.c
+++ b/arch/powerpc/kernel/setup_32.c
@@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr)
 }
 
 #ifdef CONFIG_BOOKE_WDT
+extern u32 booke_wdt_enabled;
+extern u32 booke_wdt_period;
+
 /* Checks wdt=x and wdt_period=xx command-line option */
 notrace int __init early_parse_wdt(char *p)
 {
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 6aa0c663e247..158972341a2d 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -248,7 +248,7 @@ void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
                                    addr, regs->nip, regs->link, code);
         }
 
-        if (!arch_irq_disabled_regs(regs))
+        if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
                 local_irq_enable();
 
         memset(&info, 0, sizeof(info));
@@ -1019,7 +1019,9 @@ void __kprobes program_check_exception(struct pt_regs *regs)
                 return;
         }
 
-        local_irq_enable();
+        /* We restore the interrupt state now */
+        if (!arch_irq_disabled_regs(regs))
+                local_irq_enable();
 
 #ifdef CONFIG_MATH_EMULATION
         /* (reason & REASON_ILLEGAL) would be the obvious thing here,
@@ -1069,6 +1071,10 @@ void alignment_exception(struct pt_regs *regs)
 {
         int sig, code, fixed = 0;
 
+        /* We restore the interrupt state now */
+        if (!arch_irq_disabled_regs(regs))
+                local_irq_enable();
+
         /* we don't implement logging of alignment exceptions */
         if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
                 fixed = fix_alignment(regs);
diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c
index ddc485a529f2..c3beaeef3f60 100644
--- a/arch/powerpc/kvm/book3s_64_mmu_hv.c
+++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c
@@ -258,6 +258,8 @@ static long kvmppc_get_guest_page(struct kvm *kvm, unsigned long gfn,
                             !(memslot->userspace_addr & (s - 1))) {
                                 start &= ~(s - 1);
                                 pgsize = s;
+                                get_page(hpage);
+                                put_page(page);
                                 page = hpage;
                         }
                 }
@@ -281,11 +283,8 @@ static long kvmppc_get_guest_page(struct kvm *kvm, unsigned long gfn,
         err = 0;
 
  out:
-        if (got) {
-                if (PageHuge(page))
-                        page = compound_head(page);
+        if (got)
                 put_page(page);
-        }
         return err;
 
  up_err:
@@ -678,8 +677,15 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu,
                 SetPageDirty(page);
 
  out_put:
-        if (page)
-                put_page(page);
+        if (page) {
+                /*
+                 * We drop pages[0] here, not page because page might
+                 * have been set to the head page of a compound, but
+                 * we have to drop the reference on the correct tail
+                 * page to match the get inside gup()
+                 */
+                put_page(pages[0]);
+        }
         return ret;
 
  out_unlock:
@@ -979,6 +985,7 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
                         pa = *physp;
                 }
                 page = pfn_to_page(pa >> PAGE_SHIFT);
+                get_page(page);
         } else {
                 hva = gfn_to_hva_memslot(memslot, gfn);
                 npages = get_user_pages_fast(hva, 1, 1, pages);
@@ -991,8 +998,6 @@ void *kvmppc_pin_guest_page(struct kvm *kvm, unsigned long gpa,
                 page = compound_head(page);
                 psize <<= compound_order(page);
         }
-        if (!kvm->arch.using_mmu_notifiers)
-                get_page(page);
         offset = gpa & (psize - 1);
         if (nb_ret)
                 *nb_ret = psize - offset;
@@ -1003,7 +1008,6 @@ void kvmppc_unpin_guest_page(struct kvm *kvm, void *va)
 {
         struct page *page = virt_to_page(va);
 
-        page = compound_head(page);
         put_page(page);
 }
 
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 01294a5099dd..108d1f580177 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -1192,8 +1192,6 @@ static void unpin_slot(struct kvm *kvm, int slot_id)
                                 continue;
                         pfn = physp[j] >> PAGE_SHIFT;
                         page = pfn_to_page(pfn);
-                        if (PageHuge(page))
-                                page = compound_head(page);
                         SetPageDirty(page);
                         put_page(page);
                 }
diff --git a/arch/powerpc/net/bpf_jit.h b/arch/powerpc/net/bpf_jit.h
index af1ab5e9a691..5c3cf2d04e41 100644
--- a/arch/powerpc/net/bpf_jit.h
+++ b/arch/powerpc/net/bpf_jit.h
@@ -48,7 +48,13 @@
 /*
  * Assembly helpers from arch/powerpc/net/bpf_jit.S:
  */
-extern u8 sk_load_word[], sk_load_half[], sk_load_byte[], sk_load_byte_msh[];
+#define DECLARE_LOAD_FUNC(func) \
+        extern u8 func[], func##_negative_offset[], func##_positive_offset[]
+
+DECLARE_LOAD_FUNC(sk_load_word);
+DECLARE_LOAD_FUNC(sk_load_half);
+DECLARE_LOAD_FUNC(sk_load_byte);
+DECLARE_LOAD_FUNC(sk_load_byte_msh);
 
 #define FUNCTION_DESCR_SIZE     24
 
diff --git a/arch/powerpc/net/bpf_jit_64.S b/arch/powerpc/net/bpf_jit_64.S
index ff4506e85cce..55ba3855a97f 100644
--- a/arch/powerpc/net/bpf_jit_64.S
+++ b/arch/powerpc/net/bpf_jit_64.S
@@ -31,14 +31,13 @@
  * then branch directly to slow_path_XXX if required.  (In fact, could
  * load a spare GPR with the address of slow_path_generic and pass size
  * as an argument, making the call site a mtlr, li and bllr.)
- *
- * Technically, the "is addr < 0" check is unnecessary & slowing down
- * the ABS path, as it's statically checked on generation.
  */
         .globl  sk_load_word
 sk_load_word:
         cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_word_neg
+        .globl  sk_load_word_positive_offset
+sk_load_word_positive_offset:
         /* Are we accessing past headlen? */
         subi    r_scratch1, r_HL, 4
         cmpd    r_scratch1, r_addr
@@ -51,7 +50,9 @@ sk_load_word:
         .globl  sk_load_half
 sk_load_half:
         cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_half_neg
+        .globl  sk_load_half_positive_offset
+sk_load_half_positive_offset:
         subi    r_scratch1, r_HL, 2
         cmpd    r_scratch1, r_addr
         blt     bpf_slow_path_half
@@ -61,7 +62,9 @@ sk_load_half:
         .globl  sk_load_byte
 sk_load_byte:
         cmpdi   r_addr, 0
-        blt     bpf_error
+        blt     bpf_slow_path_byte_neg
+        .globl  sk_load_byte_positive_offset
+sk_load_byte_positive_offset:
         cmpd    r_HL, r_addr
         ble     bpf_slow_path_byte
         lbzx    r_A, r_D, r_addr
@@ -69,22 +72,20 @@ sk_load_byte:
 
 /*
  * BPF_S_LDX_B_MSH: ldxb  4*([offset]&0xf)
- * r_addr is the offset value, already known positive
+ * r_addr is the offset value
  */
         .globl sk_load_byte_msh
 sk_load_byte_msh:
+        cmpdi   r_addr, 0
+        blt     bpf_slow_path_byte_msh_neg
+        .globl sk_load_byte_msh_positive_offset
+sk_load_byte_msh_positive_offset:
         cmpd    r_HL, r_addr
         ble     bpf_slow_path_byte_msh
         lbzx    r_X, r_D, r_addr
         rlwinm  r_X, r_X, 2, 32-4-2, 31-2
         blr
 
-bpf_error:
-        /* Entered with cr0 = lt */
-        li      r3, 0
-        /* Generated code will 'blt epilogue', returning 0. */
-        blr
-
 /* Call out to skb_copy_bits:
  * We'll need to back up our volatile regs first; we have
  * local variable space at r1+(BPF_PPC_STACK_BASIC).
@@ -136,3 +137,84 @@ bpf_slow_path_byte_msh:
         lbz     r_X, BPF_PPC_STACK_BASIC+(2*8)(r1)
         rlwinm  r_X, r_X, 2, 32-4-2, 31-2
         blr
+
+/* Call out to bpf_internal_load_pointer_neg_helper:
+ * We'll need to back up our volatile regs first; we have
+ * local variable space at r1+(BPF_PPC_STACK_BASIC).
+ * Allocate a new stack frame here to remain ABI-compliant in
+ * stashing LR.
+ */
+#define sk_negative_common(SIZE)                                \
+        mflr    r0;                                             \
+        std     r0, 16(r1);                                     \
+        /* R3 goes in parameter space of caller's frame */      \
+        std     r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        std     r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        std     r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        stdu    r1, -BPF_PPC_SLOWPATH_FRAME(r1);                \
+        /* R3 = r_skb, as passed */                             \
+        mr      r4, r_addr;                                     \
+        li      r5, SIZE;                                       \
+        bl      bpf_internal_load_pointer_neg_helper;           \
+        /* R3 != 0 on success */                                \
+        addi    r1, r1, BPF_PPC_SLOWPATH_FRAME;                 \
+        ld      r0, 16(r1);                                     \
+        ld      r_A, (BPF_PPC_STACK_BASIC+(0*8))(r1);           \
+        ld      r_X, (BPF_PPC_STACK_BASIC+(1*8))(r1);           \
+        mtlr    r0;                                             \
+        cmpldi  r3, 0;                                          \
+        beq     bpf_error_slow; /* cr0 = EQ */                  \
+        mr      r_addr, r3;                                     \
+        ld      r_skb, (BPF_PPC_STACKFRAME+48)(r1);             \
+        /* Great success! */
+
+bpf_slow_path_word_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_word_negative_offset
+sk_load_word_negative_offset:
+        sk_negative_common(4)
+        lwz     r_A, 0(r_addr)
+        blr
+
+bpf_slow_path_half_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_half_negative_offset
+sk_load_half_negative_offset:
+        sk_negative_common(2)
+        lhz     r_A, 0(r_addr)
+        blr
+
+bpf_slow_path_byte_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_byte_negative_offset
+sk_load_byte_negative_offset:
+        sk_negative_common(1)
+        lbz     r_A, 0(r_addr)
+        blr
+
+bpf_slow_path_byte_msh_neg:
+        lis     r_scratch1,-32  /* SKF_LL_OFF */
+        cmpd    r_addr, r_scratch1      /* addr < SKF_* */
+        blt     bpf_error       /* cr0 = LT */
+        .globl  sk_load_byte_msh_negative_offset
+sk_load_byte_msh_negative_offset:
+        sk_negative_common(1)
+        lbz     r_X, 0(r_addr)
+        rlwinm  r_X, r_X, 2, 32-4-2, 31-2
+        blr
+
+bpf_error_slow:
+        /* fabricate a cr0 = lt */
+        li      r_scratch1, -1
+        cmpdi   r_scratch1, 0
+bpf_error:
+        /* Entered with cr0 = lt */
+        li      r3, 0
+        /* Generated code will 'blt epilogue', returning 0. */
+        blr
diff --git a/arch/powerpc/net/bpf_jit_comp.c b/arch/powerpc/net/bpf_jit_comp.c
index 73619d3aeb6c..2dc8b1484845 100644
--- a/arch/powerpc/net/bpf_jit_comp.c
+++ b/arch/powerpc/net/bpf_jit_comp.c
@@ -127,6 +127,9 @@ static void bpf_jit_build_epilogue(u32 *image, struct codegen_context *ctx)
         PPC_BLR();
 }
 
+#define CHOOSE_LOAD_FUNC(K, func) \
+        ((int)K < 0 ? ((int)K >= SKF_LL_OFF ? func##_negative_offset : func) : func##_positive_offset)
+
 /* Assemble the body code between the prologue & epilogue. */
 static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                               struct codegen_context *ctx,
@@ -391,21 +394,16 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
 
                         /*** Absolute loads from packet header/data ***/
                 case BPF_S_LD_W_ABS:
-                        func = sk_load_word;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_word);
                         goto common_load;
                 case BPF_S_LD_H_ABS:
-                        func = sk_load_half;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_half);
                         goto common_load;
                 case BPF_S_LD_B_ABS:
-                        func = sk_load_byte;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_byte);
                 common_load:
-                        /*
-                         * Load from [K].  Reference with the (negative)
-                         * SKF_NET_OFF/SKF_LL_OFF offsets is unsupported.
-                         */
+                        /* Load from [K]. */
                         ctx->seen |= SEEN_DATAREF;
-                        if ((int)K < 0)
-                                return -ENOTSUPP;
                         PPC_LI64(r_scratch1, func);
                         PPC_MTLR(r_scratch1);
                         PPC_LI32(r_addr, K);
@@ -429,7 +427,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                 common_load_ind:
                         /*
                          * Load from [X + K].  Negative offsets are tested for
-                         * in the helper functions, and result in a 'ret 0'.
+                         * in the helper functions.
                          */
                         ctx->seen |= SEEN_DATAREF | SEEN_XREG;
                         PPC_LI64(r_scratch1, func);
@@ -443,13 +441,7 @@ static int bpf_jit_build_body(struct sk_filter *fp, u32 *image,
                         break;
 
                 case BPF_S_LDX_B_MSH:
-                        /*
-                         * x86 version drops packet (RET 0) when K<0, whereas
-                         * interpreter does allow K<0 (__load_pointer, special
-                         * ancillary data).  common_load returns ENOTSUPP if K<0,
-                         * so we fall back to interpreter & filter works.
-                         */
-                        func = sk_load_byte_msh;
+                        func = CHOOSE_LOAD_FUNC(K, sk_load_byte_msh);
                         goto common_load;
                         break;
 
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index 9fef5302adc1..67dac22b4363 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
         { .compatible = "fsl,qe", },
         { .compatible = "fsl,cpm2", },
         { .compatible = "fsl,srio", },
+        /* So that the DMA channel nodes can be probed individually: */
+        { .compatible = "fsl,eloplus-dma", },
+        /* For the PMC driver */
+        { .compatible = "fsl,mpc8548-guts", },
+        /* Probably unnecessary? */
+        { .compatible = "gpio-leds", },
         {},
 };
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 9a6f04406e0d..d208ebccb91c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -399,12 +399,6 @@ static int __init board_fixups(void)
 machine_arch_initcall(mpc8568_mds, board_fixups);
 machine_arch_initcall(mpc8569_mds, board_fixups);
 
-static struct of_device_id mpc85xx_ids[] = {
-        { .compatible = "fsl,mpc8548-guts", },
-        { .compatible = "gpio-leds", },
-        {},
-};
-
 static int __init mpc85xx_publish_devices(void)
 {
         if (machine_is(mpc8568_mds))
@@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void)
         if (machine_is(mpc8569_mds))
                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
 
-        mpc85xx_common_publish_devices();
-        of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
-
-        return 0;
+        return mpc85xx_common_publish_devices();
 }
 
 machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
diff --git a/arch/powerpc/platforms/85xx/p1022_ds.c b/arch/powerpc/platforms/85xx/p1022_ds.c
index e74b7cde9aee..f700c81a1321 100644
--- a/arch/powerpc/platforms/85xx/p1022_ds.c
+++ b/arch/powerpc/platforms/85xx/p1022_ds.c
@@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void)
         pr_info("Freescale P1022 DS reference board\n");
 }
 
-static struct of_device_id __initdata p1022_ds_ids[] = {
-        /* So that the DMA channel nodes can be probed individually: */
-        { .compatible = "fsl,eloplus-dma", },
-        {},
-};
-
-static int __init p1022_ds_publish_devices(void)
-{
-        mpc85xx_common_publish_devices();
-        return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
-}
-machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
+machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
 
 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
 
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index d09f3e8e6867..85825b5401e5 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -114,7 +114,7 @@ static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
                 pr_devel("axon_msi: woff %x roff %x msi %x\n",
                           write_offset, msic->read_offset, msi);
 
-                if (msi < NR_IRQS && irq_get_chip_data(msi) == msic) {
+                if (msi < nr_irqs && irq_get_chip_data(msi) == msic) {
                         generic_handle_irq(msi);
                         msic->fifo_virt[idx] = cpu_to_le32(0xffffffff);
                 } else {
@@ -276,9 +276,6 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
         if (rc)
                 return rc;
 
-        /* We rely on being able to stash a virq in a u16 */
-        BUILD_BUG_ON(NR_IRQS > 65536);
-
         list_for_each_entry(entry, &dev->msi_list, list) {
                 virq = irq_create_direct_mapping(msic->irq_domain);
                 if (virq == NO_IRQ) {
@@ -392,7 +389,8 @@ static int axon_msi_probe(struct platform_device *device)
         }
         memset(msic->fifo_virt, 0xff, MSIC_FIFO_SIZE_BYTES);
 
-        msic->irq_domain = irq_domain_add_nomap(dn, 0, &msic_host_ops, msic);
+        /* We rely on being able to stash a virq in a u16, so limit irqs to < 65536 */
+        msic->irq_domain = irq_domain_add_nomap(dn, 65536, &msic_host_ops, msic);
         if (!msic->irq_domain) {
                 printk(KERN_ERR "axon_msi: couldn't allocate irq_domain for %s\n",
                        dn->full_name);
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
index f9a48af335cb..8c6dc42ecf65 100644
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ b/arch/powerpc/platforms/cell/beat_interrupt.c
@@ -248,6 +248,6 @@ void beatic_deinit_IRQ(void)
 {
         int     i;
 
-        for (i = 1; i < NR_IRQS; i++)
+        for (i = 1; i < nr_irqs; i++)
                 beat_destruct_irq_plug(i);
 }
diff --git a/arch/powerpc/platforms/powermac/low_i2c.c b/arch/powerpc/platforms/powermac/low_i2c.c
index 996c5ff7824b..03685a329d7d 100644
--- a/arch/powerpc/platforms/powermac/low_i2c.c
+++ b/arch/powerpc/platforms/powermac/low_i2c.c
@@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data)
         unsigned long flags;
 
         spin_lock_irqsave(&host->lock, flags);
+
+        /*
+         * If the timer is pending, that means we raced with the
+         * irq, in which case we just return
+         */
+        if (timer_pending(&host->timeout_timer))
+                goto skip;
+
         kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
         if (host->state != state_idle) {
                 host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
                 add_timer(&host->timeout_timer);
         }
+ skip:
         spin_unlock_irqrestore(&host->lock, flags);
 }
 
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index 66ad93de1d55..c4e630576ff2 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -57,9 +57,9 @@ static int max_real_irqs;
 
 static DEFINE_RAW_SPINLOCK(pmac_pic_lock);
 
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+/* The max irq number this driver deals with is 128; see max_irqs */
+static DECLARE_BITMAP(ppc_lost_interrupts, 128);
+static DECLARE_BITMAP(ppc_cached_irq_mask, 128);
 static int pmac_irq_cascade = -1;
 static struct irq_domain *pmac_pic_host;
 
diff --git a/arch/powerpc/platforms/pseries/Kconfig b/arch/powerpc/platforms/pseries/Kconfig
index aadbe4f6d537..178a5f300bc9 100644
--- a/arch/powerpc/platforms/pseries/Kconfig
+++ b/arch/powerpc/platforms/pseries/Kconfig
@@ -30,9 +30,9 @@ config PPC_SPLPAR
           two or more partitions.
 
 config EEH
-        bool "PCI Extended Error Handling (EEH)" if EXPERT
+        bool
         depends on PPC_PSERIES && PCI
-        default y if !EXPERT
+        default y
 
 config PSERIES_MSI
        bool
diff --git a/arch/powerpc/platforms/pseries/eeh.c b/arch/powerpc/platforms/pseries/eeh.c
index 309d38ef7322..a75e37dc41aa 100644
--- a/arch/powerpc/platforms/pseries/eeh.c
+++ b/arch/powerpc/platforms/pseries/eeh.c
@@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
         pr_debug("EEH: Adding device %s\n", pci_name(dev));
 
         dn = pci_device_to_OF_node(dev);
-        edev = pci_dev_to_eeh_dev(dev);
+        edev = of_node_to_eeh_dev(dn);
         if (edev->pdev == dev) {
                 pr_debug("EEH: Already referenced !\n");
                 return;
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index d3be961e2ae7..10386b676d87 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -51,8 +51,7 @@
 static intctl_cpm2_t __iomem *cpm2_intctl;
 
 static struct irq_domain *cpm2_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+static unsigned long ppc_cached_irq_mask[2]; /* 2 32-bit registers */
 
 static const u_char irq_to_siureg[] = {
         1, 1, 1, 1, 1, 1, 1, 1,
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index d5f5416be310..b724622c3a0b 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -18,69 +18,45 @@
 extern int cpm_get_irq(struct pt_regs *regs);
 
 static struct irq_domain *mpc8xx_pic_host;
-#define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
-static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
+static unsigned long mpc8xx_cached_irq_mask;
 static sysconf8xx_t __iomem *siu_reg;
 
-int cpm_get_irq(struct pt_regs *regs);
+static inline unsigned long mpc8xx_irqd_to_bit(struct irq_data *d)
+{
+        return 0x80000000 >> irqd_to_hwirq(d);
+}
 
 static void mpc8xx_unmask_irq(struct irq_data *d)
 {
-        int     bit, word;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-
-        ppc_cached_irq_mask[word] |= (1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+        mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static void mpc8xx_mask_irq(struct irq_data *d)
 {
-        int     bit, word;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-
-        ppc_cached_irq_mask[word] &= ~(1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+        mpc8xx_cached_irq_mask &= ~mpc8xx_irqd_to_bit(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static void mpc8xx_ack(struct irq_data *d)
 {
-        int     bit;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
+        out_be32(&siu_reg->sc_sipend, mpc8xx_irqd_to_bit(d));
 }
 
 static void mpc8xx_end_irq(struct irq_data *d)
 {
-        int bit, word;
-        unsigned int irq_nr = (unsigned int)irqd_to_hwirq(d);
-
-        bit = irq_nr & 0x1f;
-        word = irq_nr >> 5;
-
-        ppc_cached_irq_mask[word] |= (1 << (31-bit));
-        out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
+        mpc8xx_cached_irq_mask |= mpc8xx_irqd_to_bit(d);
+        out_be32(&siu_reg->sc_simask, mpc8xx_cached_irq_mask);
 }
 
 static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        if (flow_type & IRQ_TYPE_EDGE_FALLING) {
-                irq_hw_number_t hw = (unsigned int)irqd_to_hwirq(d);
+        /* only external IRQ senses are programmable */
+        if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !(irqd_to_hwirq(d) & 1)) {
                 unsigned int siel = in_be32(&siu_reg->sc_siel);
-
-                /* only external IRQ senses are programmable */
-                if ((hw & 1) == 0) {
-                        siel |= (0x80000000 >> hw);
-                        out_be32(&siu_reg->sc_siel, siel);
-                        __irq_set_handler_locked(d->irq, handle_edge_irq);
-                }
+                siel |= mpc8xx_irqd_to_bit(d);
+                out_be32(&siu_reg->sc_siel, siel);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
         }
         return 0;
 }
@@ -132,6 +108,9 @@ static int mpc8xx_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
                 IRQ_TYPE_EDGE_FALLING,
         };
 
+        if (intspec[0] > 0x1f)
+                return 0;
+
         *out_hwirq = intspec[0];
         if (intsize > 1 && intspec[1] < 4)
                 *out_flags = map_pic_senses[intspec[1]];
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 9ac71ebd2c40..395af1347749 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq)
 }
 
 /* Determine if the linux irq is an IPI */
-static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
 {
-        unsigned int src = virq_to_hw(irq);
-
         return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
 }
 
 /* Determine if the linux irq is a timer */
-static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
+static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
 {
-        unsigned int src = virq_to_hw(irq);
-
         return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
 }
 
@@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         if (src >= mpic->num_sources)
                 return -EINVAL;
 
+        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
+
+        /* We don't support "none" type */
         if (flow_type == IRQ_TYPE_NONE)
-                if (mpic->senses && src < mpic->senses_count)
-                        flow_type = mpic->senses[src];
-        if (flow_type == IRQ_TYPE_NONE)
-                flow_type = IRQ_TYPE_LEVEL_LOW;
+                flow_type = IRQ_TYPE_DEFAULT;
+
+        /* Default: read HW settings */
+        if (flow_type == IRQ_TYPE_DEFAULT) {
+                switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
+                               MPIC_INFO(VECPRI_SENSE_MASK))) {
+                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                                flow_type = IRQ_TYPE_EDGE_RISING;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_EDGE) |
+                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                                flow_type = IRQ_TYPE_EDGE_FALLING;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                             MPIC_INFO(VECPRI_POLARITY_POSITIVE):
+                                flow_type = IRQ_TYPE_LEVEL_HIGH;
+                                break;
+                        case MPIC_INFO(VECPRI_SENSE_LEVEL) |
+                             MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
+                                flow_type = IRQ_TYPE_LEVEL_LOW;
+                                break;
+                }
+        }
 
+        /* Apply to irq desc */
         irqd_set_trigger_type(d, flow_type);
 
+        /* Apply to HW */
         if (mpic_is_ht_interrupt(mpic, src))
                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
                         MPIC_VECPRI_SENSE_EDGE;
         else
                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
 
-        vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
                         MPIC_INFO(VECPRI_SENSE_MASK));
         vnew |= vecpri;
@@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
         irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
 
         /* Set default irq type */
-        irq_set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
 
         /* If the MPIC was reset, then all vectors have already been
          * initialized.  Otherwise, a per source lazy initialization
@@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                 mpic->num_sources = isu_first + mpic->isu_size;
 }
 
-void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
-{
-        mpic->senses = senses;
-        mpic->senses_count = count;
-}
-
 void __init mpic_init(struct mpic *mpic)
 {
         int i, cpu;
@@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
                 return;
 
         raw_spin_lock_irqsave(&mpic_lock, flags);
-        if (mpic_is_ipi(mpic, irq)) {
+        if (mpic_is_ipi(mpic, src)) {
                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
                         ~MPIC_VECPRI_PRIORITY_MASK;
                 mpic_ipi_write(src - mpic->ipi_vecs[0],
                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
-        } else if (mpic_is_tm(mpic, irq)) {
+        } else if (mpic_is_tm(mpic, src)) {
                 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
                         ~MPIC_VECPRI_PRIORITY_MASK;
                 mpic_tm_write(src - mpic->timer_vecs[0],
diff --git a/arch/powerpc/sysdev/mpic_msgr.c b/arch/powerpc/sysdev/mpic_msgr.c
index 6e7fa386e76a..483d8fa72e8b 100644
--- a/arch/powerpc/sysdev/mpic_msgr.c
+++ b/arch/powerpc/sysdev/mpic_msgr.c
@@ -27,6 +27,7 @@
 
 static struct mpic_msgr **mpic_msgrs;
 static unsigned int mpic_msgr_count;
+static DEFINE_RAW_SPINLOCK(msgrs_lock);
 
 static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
 {
@@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
         if (reg_num >= mpic_msgr_count)
                 return ERR_PTR(-ENODEV);
 
-        raw_spin_lock_irqsave(&msgr->lock, flags);
-        if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
-                msgr = mpic_msgrs[reg_num];
+        raw_spin_lock_irqsave(&msgrs_lock, flags);
+        msgr = mpic_msgrs[reg_num];
+        if (msgr->in_use == MSGR_FREE)
                 msgr->in_use = MSGR_INUSE;
-        }
-        raw_spin_unlock_irqrestore(&msgr->lock, flags);
+        raw_spin_unlock_irqrestore(&msgrs_lock, flags);
 
         return msgr;
 }
@@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev)
 
                 reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
                 msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
-                msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
+                msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
                 msgr->in_use = MSGR_FREE;
                 msgr->num = i;
                 raw_spin_lock_init(&msgr->lock);
diff --git a/arch/powerpc/sysdev/scom.c b/arch/powerpc/sysdev/scom.c
index 49a3ece1c6b3..702256a1ca11 100644
--- a/arch/powerpc/sysdev/scom.c
+++ b/arch/powerpc/sysdev/scom.c
@@ -22,6 +22,7 @@
 #include <linux/debugfs.h>
 #include <linux/slab.h>
 #include <linux/export.h>
+#include <asm/debug.h>
 #include <asm/prom.h>
 #include <asm/scom.h>
 
diff --git a/arch/powerpc/sysdev/xics/xics-common.c b/arch/powerpc/sysdev/xics/xics-common.c
index ea5e204e3450..cd1d18db92c6 100644
--- a/arch/powerpc/sysdev/xics/xics-common.c
+++ b/arch/powerpc/sysdev/xics/xics-common.c
@@ -188,6 +188,7 @@ void xics_migrate_irqs_away(void)
 {
         int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
         unsigned int irq, virq;
+        struct irq_desc *desc;
 
         /* If we used to be the default server, move to the new "boot_cpuid" */
         if (hw_cpu == xics_default_server)
@@ -202,8 +203,7 @@ void xics_migrate_irqs_away(void)
         /* Allow IPIs again... */
         icp_ops->set_priority(DEFAULT_PRIORITY);
 
-        for_each_irq(virq) {
-                struct irq_desc *desc;
+        for_each_irq_desc(virq, desc) {
                 struct irq_chip *chip;
                 long server;
                 unsigned long flags;
@@ -212,9 +212,8 @@ void xics_migrate_irqs_away(void)
                 /* We can't set affinity on ISA interrupts */
                 if (virq < NUM_ISA_INTERRUPTS)
                         continue;
-                desc = irq_to_desc(virq);
                 /* We only need to migrate enabled IRQS */
-                if (!desc || !desc->action)
+                if (!desc->action)
                         continue;
                 if (desc->irq_data.domain != xics_host)
                         continue;
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 98405fa24e81..65bdb5da79c5 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -288,6 +288,13 @@ config CPU_SUBTYPE_SH7263
         select SYS_SUPPORTS_CMT
         select SYS_SUPPORTS_MTU2
 
+config CPU_SUBTYPE_SH7264
+        bool "Support SH7264 processor"
+        select CPU_SH2A
+        select CPU_HAS_FPU
+        select SYS_SUPPORTS_CMT
+        select SYS_SUPPORTS_MTU2
+
 config CPU_SUBTYPE_MXG
         bool "Support MX-G processor"
         select CPU_SH2A
@@ -594,7 +601,8 @@ config SH_CLK_CPG
 config SH_CLK_CPG_LEGACY
         depends on SH_CLK_CPG
         def_bool y if !CPU_SUBTYPE_SH7785 && !ARCH_SHMOBILE && \
-                      !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && !CPU_SUBTYPE_SH7734
+                      !CPU_SHX3 && !CPU_SUBTYPE_SH7757 && \
+                      !CPU_SUBTYPE_SH7734 && !CPU_SUBTYPE_SH7264
 
 source "kernel/time/Kconfig"
 
diff --git a/arch/sh/boards/Kconfig b/arch/sh/boards/Kconfig
index 6c96daab499b..414a797f3be5 100644
--- a/arch/sh/boards/Kconfig
+++ b/arch/sh/boards/Kconfig
@@ -133,7 +133,7 @@ config SH_RTS7751R2D
 
 config SH_RSK
         bool "Renesas Starter Kit"
-        depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203
+        depends on CPU_SUBTYPE_SH7201 || CPU_SUBTYPE_SH7203 || CPU_SUBTYPE_SH7264
         help
          Select this option if configuring for any of the RSK+ MCU
          evaluation platforms.
diff --git a/arch/sh/boards/mach-rsk/Kconfig b/arch/sh/boards/mach-rsk/Kconfig
index aeff3b042205..4315af511649 100644
--- a/arch/sh/boards/mach-rsk/Kconfig
+++ b/arch/sh/boards/mach-rsk/Kconfig
@@ -13,6 +13,11 @@ config SH_RSK7203
         select ARCH_REQUIRE_GPIOLIB
         depends on CPU_SUBTYPE_SH7203
 
+config SH_RSK7264
+        bool "RSK2+SH7264"
+        select ARCH_REQUIRE_GPIOLIB
+        depends on CPU_SUBTYPE_SH7264
+
 endchoice
 
 endif
diff --git a/arch/sh/boards/mach-rsk/Makefile b/arch/sh/boards/mach-rsk/Makefile
index 498da75ce38b..bae6ae45aba8 100644
--- a/arch/sh/boards/mach-rsk/Makefile
+++ b/arch/sh/boards/mach-rsk/Makefile
@@ -1,2 +1,3 @@
 obj-y                           := setup.o
 obj-$(CONFIG_SH_RSK7203)        += devices-rsk7203.o
+obj-$(CONFIG_SH_RSK7264)        += devices-rsk7264.o
diff --git a/arch/sh/boards/mach-rsk/devices-rsk7264.c b/arch/sh/boards/mach-rsk/devices-rsk7264.c
new file mode 100644
index 000000000000..7251e37a842f
--- /dev/null
+++ b/arch/sh/boards/mach-rsk/devices-rsk7264.c
@@ -0,0 +1,58 @@
+/*
+ * RSK+SH7264 Support.
+ *
+ * Copyright (C) 2012 Renesas Electronics Europe
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/smsc911x.h>
+#include <asm/machvec.h>
+#include <asm/io.h>
+
+static struct smsc911x_platform_config smsc911x_config = {
+        .phy_interface  = PHY_INTERFACE_MODE_MII,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+        .irq_type       = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+        .flags          = SMSC911X_USE_16BIT | SMSC911X_SWAP_FIFO,
+};
+
+static struct resource smsc911x_resources[] = {
+        [0] = {
+                .start          = 0x28000000,
+                .end            = 0x280000ff,
+                .flags          = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start          = 65,
+                .end            = 65,
+                .flags          = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device smsc911x_device = {
+        .name           = "smsc911x",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(smsc911x_resources),
+        .resource       = smsc911x_resources,
+        .dev            = {
+                .platform_data = &smsc911x_config,
+        },
+};
+
+static struct platform_device *rsk7264_devices[] __initdata = {
+        &smsc911x_device,
+};
+
+static int __init rsk7264_devices_setup(void)
+{
+        return platform_add_devices(rsk7264_devices,
+                                    ARRAY_SIZE(rsk7264_devices));
+}
+device_initcall(rsk7264_devices_setup);
diff --git a/arch/sh/configs/rsk7264_defconfig b/arch/sh/configs/rsk7264_defconfig
new file mode 100644
index 000000000000..1600426224c2
--- /dev/null
+++ b/arch/sh/configs/rsk7264_defconfig
@@ -0,0 +1,80 @@
+CONFIG_LOCALVERSION="uClinux RSK2+SH7264"
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_IKCONFIG=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_NAMESPACES=y
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_COUNTERS=y
+# CONFIG_VM_EVENT_COUNTERS is not set
+CONFIG_SLAB=y
+CONFIG_MMAP_ALLOW_UNINITIALIZED=y
+CONFIG_PROFILING=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_CPU_SUBTYPE_SH7264=y
+CONFIG_MEMORY_START=0x0c000000
+CONFIG_FLATMEM_MANUAL=y
+CONFIG_CPU_BIG_ENDIAN=y
+CONFIG_SH_RSK=y
+# CONFIG_SH_TIMER_MTU2 is not set
+CONFIG_BINFMT_FLAT=y
+CONFIG_NET=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+# CONFIG_FW_LOADER is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=4
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_SMSC911X=y
+CONFIG_SMSC_PHY=y
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_SH_SCI=y
+CONFIG_SERIAL_SH_SCI_NR_UARTS=8
+CONFIG_SERIAL_SH_SCI_CONSOLE=y
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_DEBUG=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+# CONFIG_USB_DEVICE_CLASS is not set
+CONFIG_USB_R8A66597_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_STORAGE_DEBUG=y
+CONFIG_USB_LIBUSUAL=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_VFAT_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+# CONFIG_FTRACE is not set
diff --git a/arch/sh/include/asm/atomic.h b/arch/sh/include/asm/atomic.h
index 37f2f4a55231..f4c1c20bcdf6 100644
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -11,7 +11,7 @@
 #include <linux/types.h>
 #include <asm/cmpxchg.h>
 
-#define ATOMIC_INIT(i)  ( (atomic_t) { (i) } )
+#define ATOMIC_INIT(i)  { (i) }
 
 #define atomic_read(v)          (*(volatile int *)&(v)->counter)
 #define atomic_set(v,i)         ((v)->counter = (i))
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 26b12fd8fcbd..858b716ca64d 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -18,7 +18,7 @@ enum cpu_type {
         CPU_SH7619,
 
         /* SH-2A types */
-        CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
+        CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_SH7264, CPU_MXG,
 
         /* SH-3 types */
         CPU_SH7705, CPU_SH7706, CPU_SH7707,
diff --git a/arch/sh/include/cpu-sh2a/cpu/sh7264.h b/arch/sh/include/cpu-sh2a/cpu/sh7264.h
new file mode 100644
index 000000000000..4d1ef6d74bd6
--- /dev/null
+++ b/arch/sh/include/cpu-sh2a/cpu/sh7264.h
@@ -0,0 +1,176 @@
+#ifndef __ASM_SH7264_H__
+#define __ASM_SH7264_H__
+
+enum {
+        /* Port A */
+        GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
+
+        /* Port B */
+        GPIO_PB22, GPIO_PB21, GPIO_PB20,
+        GPIO_PB19, GPIO_PB18, GPIO_PB17, GPIO_PB16,
+        GPIO_PB15, GPIO_PB14, GPIO_PB13, GPIO_PB12,
+        GPIO_PB11, GPIO_PB10, GPIO_PB9, GPIO_PB8,
+        GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
+        GPIO_PB3, GPIO_PB2, GPIO_PB1,
+
+        /* Port C */
+        GPIO_PC10, GPIO_PC9, GPIO_PC8,
+        GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
+        GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
+
+        /* Port D */
+        GPIO_PD15, GPIO_PD14, GPIO_PD13, GPIO_PD12,
+        GPIO_PD11, GPIO_PD10, GPIO_PD9, GPIO_PD8,
+        GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
+        GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
+
+        /* Port E */
+        GPIO_PE5, GPIO_PE4,
+        GPIO_PE3, GPIO_PE2, GPIO_PE1, GPIO_PE0,
+
+        /* Port F */
+        GPIO_PF12,
+        GPIO_PF11, GPIO_PF10, GPIO_PF9, GPIO_PF8,
+        GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
+        GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
+
+        /* Port G */
+        GPIO_PG24,
+        GPIO_PG23, GPIO_PG22, GPIO_PG21, GPIO_PG20,
+        GPIO_PG19, GPIO_PG18, GPIO_PG17, GPIO_PG16,
+        GPIO_PG15, GPIO_PG14, GPIO_PG13, GPIO_PG12,
+        GPIO_PG11, GPIO_PG10, GPIO_PG9, GPIO_PG8,
+        GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
+        GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
+
+        /* Port H */
+        GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
+        GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
+
+        /* Port I - not on device */
+
+        /* Port J */
+        GPIO_PJ11, GPIO_PJ10, GPIO_PJ9, GPIO_PJ8,
+        GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
+        GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
+
+        /* Port K */
+        GPIO_PK11, GPIO_PK10, GPIO_PK9, GPIO_PK8,
+        GPIO_PK7, GPIO_PK6, GPIO_PK5, GPIO_PK4,
+        GPIO_PK3, GPIO_PK2, GPIO_PK1, GPIO_PK0,
+
+        /* INTC: IRQ and PINT on PB/PD/PE */
+        GPIO_FN_PINT7_PG, GPIO_FN_PINT6_PG, GPIO_FN_PINT5_PG, GPIO_FN_PINT4_PG,
+        GPIO_FN_PINT3_PG, GPIO_FN_PINT2_PG, GPIO_FN_PINT1_PG,
+
+        GPIO_FN_IRQ7_PC, GPIO_FN_IRQ6_PC, GPIO_FN_IRQ5_PC, GPIO_FN_IRQ4_PC,
+        GPIO_FN_IRQ3_PG, GPIO_FN_IRQ2_PG, GPIO_FN_IRQ1_PJ, GPIO_FN_IRQ0_PJ,
+        GPIO_FN_IRQ3_PE, GPIO_FN_IRQ2_PE, GPIO_FN_IRQ1_PE, GPIO_FN_IRQ0_PE,
+
+        /* WDT */
+        GPIO_FN_WDTOVF,
+
+        /* CAN */
+        GPIO_FN_CTX1, GPIO_FN_CRX1, GPIO_FN_CTX0, GPIO_FN_CTX0_CTX1,
+        GPIO_FN_CRX0, GPIO_FN_CRX0_CRX1,
+
+        /* DMAC */
+        GPIO_FN_TEND0, GPIO_FN_DACK0, GPIO_FN_DREQ0,
+        GPIO_FN_TEND1, GPIO_FN_DACK1, GPIO_FN_DREQ1,
+
+        /* ADC */
+        GPIO_FN_ADTRG,
+
+        /* BSC */
+
+        GPIO_FN_A25, GPIO_FN_A24,
+        GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
+        GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
+        GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
+        GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
+        GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
+        GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
+        GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
+        GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
+        GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
+        GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
+
+        GPIO_FN_BS,
+        GPIO_FN_CS4, GPIO_FN_CS3, GPIO_FN_CS2, GPIO_FN_CS1, GPIO_FN_CS0,
+        GPIO_FN_CS6CE1B, GPIO_FN_CS5CE1A,
+        GPIO_FN_CE2A, GPIO_FN_CE2B,
+        GPIO_FN_RD, GPIO_FN_RDWR,
+        GPIO_FN_ICIOWRAH, GPIO_FN_ICIORD,
+        GPIO_FN_WE1DQMUWE, GPIO_FN_WE0DQML,
+        GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
+        GPIO_FN_WAIT, GPIO_FN_BREQ, GPIO_FN_BACK,
+        GPIO_FN_IOIS16,
+
+        /* TMU */
+        GPIO_FN_TIOC4D, GPIO_FN_TIOC4C, GPIO_FN_TIOC4B, GPIO_FN_TIOC4A,
+        GPIO_FN_TIOC3D, GPIO_FN_TIOC3C, GPIO_FN_TIOC3B, GPIO_FN_TIOC3A,
+        GPIO_FN_TIOC2B, GPIO_FN_TIOC1B, GPIO_FN_TIOC2A, GPIO_FN_TIOC1A,
+        GPIO_FN_TIOC0D, GPIO_FN_TIOC0C, GPIO_FN_TIOC0B, GPIO_FN_TIOC0A,
+        GPIO_FN_TCLKD, GPIO_FN_TCLKC, GPIO_FN_TCLKB, GPIO_FN_TCLKA,
+
+        /* SSU */
+        GPIO_FN_SCS0_PD, GPIO_FN_SSO0_PD, GPIO_FN_SSI0_PD, GPIO_FN_SSCK0_PD,
+        GPIO_FN_SCS0_PF, GPIO_FN_SSO0_PF, GPIO_FN_SSI0_PF, GPIO_FN_SSCK0_PF,
+        GPIO_FN_SCS1_PD, GPIO_FN_SSO1_PD, GPIO_FN_SSI1_PD, GPIO_FN_SSCK1_PD,
+        GPIO_FN_SCS1_PF, GPIO_FN_SSO1_PF, GPIO_FN_SSI1_PF, GPIO_FN_SSCK1_PF,
+
+        /* SCIF */
+        GPIO_FN_SCK0, GPIO_FN_SCK1, GPIO_FN_SCK2, GPIO_FN_SCK3,
+        GPIO_FN_RXD0, GPIO_FN_RXD1, GPIO_FN_RXD2, GPIO_FN_RXD3,
+        GPIO_FN_TXD0, GPIO_FN_TXD1, GPIO_FN_TXD2, GPIO_FN_TXD3,
+        GPIO_FN_RXD4, GPIO_FN_RXD5, GPIO_FN_RXD6, GPIO_FN_RXD7,
+        GPIO_FN_TXD4, GPIO_FN_TXD5, GPIO_FN_TXD6, GPIO_FN_TXD7,
+        GPIO_FN_RTS1, GPIO_FN_RTS3, GPIO_FN_CTS1, GPIO_FN_CTS3,
+
+        /* RSPI */
+        GPIO_FN_RSPCK0, GPIO_FN_MOSI0,
+        GPIO_FN_MISO0_PF12, GPIO_FN_MISO1,
+        GPIO_FN_SSL00,
+        GPIO_FN_RSPCK1, GPIO_FN_MOSI1,
+        GPIO_FN_MISO1_PG19, GPIO_FN_SSL10,
+
+        /* IIC3 */
+        GPIO_FN_SCL0, GPIO_FN_SCL1, GPIO_FN_SCL2,
+        GPIO_FN_SDA2, GPIO_FN_SDA1, GPIO_FN_SDA0,
+
+        /* SSI */
+        GPIO_FN_SSISCK0, GPIO_FN_SSIWS0, GPIO_FN_SSITXD0, GPIO_FN_SSIRXD0,
+        GPIO_FN_SSIWS1, GPIO_FN_SSIWS2, GPIO_FN_SSIWS3,
+        GPIO_FN_SSISCK1, GPIO_FN_SSISCK2, GPIO_FN_SSISCK3,
+        GPIO_FN_SSIDATA1, GPIO_FN_SSIDATA2, GPIO_FN_SSIDATA3,
+        GPIO_FN_AUDIO_CLK,
+
+        /* SIOF */
+        GPIO_FN_SIOFTXD, GPIO_FN_SIOFRXD, GPIO_FN_SIOFSYNC, GPIO_FN_SIOFSCK,
+
+        /* SPDIF */
+        GPIO_FN_SPDIF_IN,
+        GPIO_FN_SPDIF_OUT,
+
+        /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
+        GPIO_FN_FCE,
+        GPIO_FN_FRB,
+
+        /* VDC3 */
+        GPIO_FN_DV_CLK, GPIO_FN_DV_VSYNC, GPIO_FN_DV_HSYNC,
+        GPIO_FN_DV_DATA7, GPIO_FN_DV_DATA6, GPIO_FN_DV_DATA5, GPIO_FN_DV_DATA4,
+        GPIO_FN_DV_DATA3, GPIO_FN_DV_DATA2, GPIO_FN_DV_DATA1, GPIO_FN_DV_DATA0,
+        GPIO_FN_LCD_CLK, GPIO_FN_LCD_EXTCLK,
+        GPIO_FN_LCD_VSYNC, GPIO_FN_LCD_HSYNC, GPIO_FN_LCD_DE,
+        GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
+        GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
+        GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
+        GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
+        GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
+        GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
+        GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
+        GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
+        GPIO_FN_LCD_M_DISP,
+};
+
+#endif /* __ASM_SH7264_H__ */
diff --git a/arch/sh/kernel/cpu/proc.c b/arch/sh/kernel/cpu/proc.c
index e3a16d104528..27dd6f915eae 100644
--- a/arch/sh/kernel/cpu/proc.c
+++ b/arch/sh/kernel/cpu/proc.c
@@ -7,6 +7,7 @@
 static const char *cpu_name[] = {
         [CPU_SH7201]    = "SH7201",
         [CPU_SH7203]    = "SH7203",     [CPU_SH7263]    = "SH7263",
+        [CPU_SH7264]    = "SH7264",
         [CPU_SH7206]    = "SH7206",     [CPU_SH7619]    = "SH7619",
         [CPU_SH7705]    = "SH7705",     [CPU_SH7706]    = "SH7706",
         [CPU_SH7707]    = "SH7707",     [CPU_SH7708]    = "SH7708",
diff --git a/arch/sh/kernel/cpu/sh2a/Makefile b/arch/sh/kernel/cpu/sh2a/Makefile
index 45f85c77ef75..64b0986275b9 100644
--- a/arch/sh/kernel/cpu/sh2a/Makefile
+++ b/arch/sh/kernel/cpu/sh2a/Makefile
@@ -11,10 +11,12 @@ obj-$(CONFIG_SH_FPU)	+= fpu.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7201)        += setup-sh7201.o clock-sh7201.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7203)        += setup-sh7203.o clock-sh7203.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7263)        += setup-sh7203.o clock-sh7203.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7264)        += setup-sh7264.o clock-sh7264.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7206)        += setup-sh7206.o clock-sh7206.o
 obj-$(CONFIG_CPU_SUBTYPE_MXG)           += setup-mxg.o clock-sh7206.o
 
 # Pinmux setup
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7203)     := pinmux-sh7203.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7264)     := pinmux-sh7264.o
 
 obj-$(CONFIG_GENERIC_GPIO)      += $(pinmux-y)
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7264.c b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c
new file mode 100644
index 000000000000..fdf585c95289
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7264.c
@@ -0,0 +1,153 @@
+/*
+ * arch/sh/kernel/cpu/sh2a/clock-sh7264.c
+ *
+ * SH7264 clock framework support
+ *
+ * Copyright (C) 2012  Phil Edworthy
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <asm/clock.h>
+
+/* SH7264 registers */
+#define FRQCR           0xfffe0010
+#define STBCR3          0xfffe0408
+#define STBCR4          0xfffe040c
+#define STBCR5          0xfffe0410
+#define STBCR6          0xfffe0414
+#define STBCR7          0xfffe0418
+#define STBCR8          0xfffe041c
+
+static const unsigned int pll1rate[] = {8, 12};
+
+static unsigned int pll1_div;
+
+/* Fixed 32 KHz root clock for RTC */
+static struct clk r_clk = {
+        .rate           = 32768,
+};
+
+/*
+ * Default rate for the root input clock, reset this with clk_set_rate()
+ * from the platform code.
+ */
+static struct clk extal_clk = {
+        .rate           = 18000000,
+};
+
+static unsigned long pll_recalc(struct clk *clk)
+{
+        unsigned long rate = clk->parent->rate / pll1_div;
+        return rate * pll1rate[(__raw_readw(FRQCR) >> 8) & 1];
+}
+
+static struct sh_clk_ops pll_clk_ops = {
+        .recalc         = pll_recalc,
+};
+
+static struct clk pll_clk = {
+        .ops            = &pll_clk_ops,
+        .parent         = &extal_clk,
+        .flags          = CLK_ENABLE_ON_INIT,
+};
+
+struct clk *main_clks[] = {
+        &r_clk,
+        &extal_clk,
+        &pll_clk,
+};
+
+static int div2[] = { 1, 2, 3, 4, 6, 8, 12 };
+
+static struct clk_div_mult_table div4_div_mult_table = {
+        .divisors = div2,
+        .nr_divisors = ARRAY_SIZE(div2),
+};
+
+static struct clk_div4_table div4_table = {
+        .div_mult_table = &div4_div_mult_table,
+};
+
+enum { DIV4_I, DIV4_P,
+       DIV4_NR };
+
+#define DIV4(_reg, _bit, _mask, _flags) \
+  SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
+
+/* The mask field specifies the div2 entries that are valid */
+struct clk div4_clks[DIV4_NR] = {
+        [DIV4_I] = DIV4(FRQCR, 4, 0x7,  CLK_ENABLE_REG_16BIT
+                                        | CLK_ENABLE_ON_INIT),
+        [DIV4_P] = DIV4(FRQCR, 0, 0x78, CLK_ENABLE_REG_16BIT),
+};
+
+enum {  MSTP77, MSTP74, MSTP72,
+        MSTP60,
+        MSTP35, MSTP34, MSTP33, MSTP32, MSTP30,
+        MSTP_NR };
+
+static struct clk mstp_clks[MSTP_NR] = {
+        [MSTP77] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 7, 0), /* SCIF */
+        [MSTP74] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 4, 0), /* VDC */
+        [MSTP72] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR7, 2, 0), /* CMT */
+        [MSTP60] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR6, 0, 0), /* USB */
+        [MSTP35] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 6, 0), /* MTU2 */
+        [MSTP34] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 4, 0), /* SDHI0 */
+        [MSTP33] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 3, 0), /* SDHI1 */
+        [MSTP32] = SH_CLK_MSTP8(&div4_clks[DIV4_P], STBCR3, 2, 0), /* ADC */
+        [MSTP30] = SH_CLK_MSTP8(&r_clk, STBCR3, 0, 0),  /* RTC */
+};
+
+static struct clk_lookup lookups[] = {
+        /* main clocks */
+        CLKDEV_CON_ID("rclk", &r_clk),
+        CLKDEV_CON_ID("extal", &extal_clk),
+        CLKDEV_CON_ID("pll_clk", &pll_clk),
+
+        /* DIV4 clocks */
+        CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
+        CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
+
+        /* MSTP clocks */
+        CLKDEV_CON_ID("sci_ick", &mstp_clks[MSTP77]),
+        CLKDEV_CON_ID("vdc3", &mstp_clks[MSTP74]),
+        CLKDEV_CON_ID("cmt_fck", &mstp_clks[MSTP72]),
+        CLKDEV_CON_ID("usb0", &mstp_clks[MSTP60]),
+        CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP35]),
+        CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP34]),
+        CLKDEV_CON_ID("sdhi1", &mstp_clks[MSTP33]),
+        CLKDEV_CON_ID("adc0", &mstp_clks[MSTP32]),
+        CLKDEV_CON_ID("rtc0", &mstp_clks[MSTP30]),
+};
+
+int __init arch_clk_init(void)
+{
+        int k, ret = 0;
+
+        if (test_mode_pin(MODE_PIN0)) {
+                if (test_mode_pin(MODE_PIN1))
+                        pll1_div = 3;
+                else
+                        pll1_div = 4;
+        } else
+                pll1_div = 1;
+
+        for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
+                ret = clk_register(main_clks[k]);
+
+        clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+        if (!ret)
+                ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
+
+        if (!ret)
+                ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
+
+        return ret;
+}
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
new file mode 100644
index 000000000000..b055b55d6f27
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -0,0 +1,2136 @@
+/*
+ * SH7264 Pinmux
+ *
+ *  Copyright (C) 2012  Renesas Electronics Europe Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <cpu/sh7264.h>
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        /* Port A */
+        PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
+        /* Port B */
+        PB22_DATA, PB21_DATA, PB20_DATA,
+        PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA,
+        PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
+        PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
+        PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+        PB3_DATA, PB2_DATA, PB1_DATA,
+        /* Port C */
+        PC10_DATA, PC9_DATA, PC8_DATA,
+        PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+        PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
+        /* Port D */
+        PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
+        PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
+        PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+        PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
+        /* Port E */
+        PE5_DATA, PE4_DATA,
+        PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA,
+        /* Port F */
+        PF12_DATA,
+        PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
+        PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+        PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
+        /* Port G */
+        PG24_DATA,
+        PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
+        PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA,
+        PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
+        PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
+        PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
+        PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA,
+        /* Port H */
+        /* NOTE - Port H does not have a Data Register, but PH Data is
+           connected to PH Port Register */
+        PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
+        PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
+        /* Port I - not on device */
+        /* Port J */
+        PJ12_DATA,
+        PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
+        PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
+        PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA,
+        /* Port K */
+        PK12_DATA,
+        PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
+        PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
+        PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA,
+        PINMUX_DATA_END,
+
+        PINMUX_INPUT_BEGIN,
+        FORCE_IN,
+        /* Port A */
+        PA3_IN, PA2_IN, PA1_IN, PA0_IN,
+        /* Port B */
+        PB22_IN, PB21_IN, PB20_IN,
+        PB19_IN, PB18_IN, PB17_IN, PB16_IN,
+        PB15_IN, PB14_IN, PB13_IN, PB12_IN,
+        PB11_IN, PB10_IN, PB9_IN, PB8_IN,
+        PB7_IN, PB6_IN, PB5_IN, PB4_IN,
+        PB3_IN, PB2_IN, PB1_IN,
+        /* Port C */
+        PC10_IN, PC9_IN, PC8_IN,
+        PC7_IN, PC6_IN, PC5_IN, PC4_IN,
+        PC3_IN, PC2_IN, PC1_IN, PC0_IN,
+        /* Port D */
+        PD15_IN, PD14_IN, PD13_IN, PD12_IN,
+        PD11_IN, PD10_IN, PD9_IN, PD8_IN,
+        PD7_IN, PD6_IN, PD5_IN, PD4_IN,
+        PD3_IN, PD2_IN, PD1_IN, PD0_IN,
+        /* Port E */
+        PE5_IN, PE4_IN,
+        PE3_IN, PE2_IN, PE1_IN, PE0_IN,
+        /* Port F */
+        PF12_IN,
+        PF11_IN, PF10_IN, PF9_IN, PF8_IN,
+        PF7_IN, PF6_IN, PF5_IN, PF4_IN,
+        PF3_IN, PF2_IN, PF1_IN, PF0_IN,
+        /* Port G */
+        PG24_IN,
+        PG23_IN, PG22_IN, PG21_IN, PG20_IN,
+        PG19_IN, PG18_IN, PG17_IN, PG16_IN,
+        PG15_IN, PG14_IN, PG13_IN, PG12_IN,
+        PG11_IN, PG10_IN, PG9_IN, PG8_IN,
+        PG7_IN, PG6_IN, PG5_IN, PG4_IN,
+        PG3_IN, PG2_IN, PG1_IN, PG0_IN,
+        /* Port H - Port H does not have a Data Register */
+        /* Port I - not on device */
+        /* Port J */
+        PJ12_IN,
+        PJ11_IN, PJ10_IN, PJ9_IN, PJ8_IN,
+        PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
+        PJ3_IN, PJ2_IN, PJ1_IN, PJ0_IN,
+        /* Port K */
+        PK12_IN,
+        PK11_IN, PK10_IN, PK9_IN, PK8_IN,
+        PK7_IN, PK6_IN, PK5_IN, PK4_IN,
+        PK3_IN, PK2_IN, PK1_IN, PK0_IN,
+        PINMUX_INPUT_END,
+
+        PINMUX_OUTPUT_BEGIN,
+        FORCE_OUT,
+        /* Port A */
+        PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
+        /* Port B */
+        PB22_OUT, PB21_OUT, PB20_OUT,
+        PB19_OUT, PB18_OUT, PB17_OUT, PB16_OUT,
+        PB15_OUT, PB14_OUT, PB13_OUT, PB12_OUT,
+        PB11_OUT, PB10_OUT, PB9_OUT, PB8_OUT,
+        PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
+        PB3_OUT, PB2_OUT, PB1_OUT,
+        /* Port C */
+        PC10_OUT, PC9_OUT, PC8_OUT,
+        PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
+        PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
+        /* Port D */
+        PD15_OUT, PD14_OUT, PD13_OUT, PD12_OUT,
+        PD11_OUT, PD10_OUT, PD9_OUT, PD8_OUT,
+        PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
+        PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
+        /* Port E */
+        PE5_OUT, PE4_OUT,
+        PE3_OUT, PE2_OUT, PE1_OUT, PE0_OUT,
+        /* Port F */
+        PF12_OUT,
+        PF11_OUT, PF10_OUT, PF9_OUT, PF8_OUT,
+        PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
+        PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
+        /* Port G */
+        PG24_OUT,
+        PG23_OUT, PG22_OUT, PG21_OUT, PG20_OUT,
+        PG19_OUT, PG18_OUT, PG17_OUT, PG16_OUT,
+        PG15_OUT, PG14_OUT, PG13_OUT, PG12_OUT,
+        PG11_OUT, PG10_OUT, PG9_OUT, PG8_OUT,
+        PG7_OUT, PG6_OUT, PG5_OUT, PG4_OUT,
+        PG3_OUT, PG2_OUT, PG1_OUT, PG0_OUT,
+        /* Port H - Port H does not have a Data Register */
+        /* Port I - not on device */
+        /* Port J */
+        PJ12_OUT,
+        PJ11_OUT, PJ10_OUT, PJ9_OUT, PJ8_OUT,
+        PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
+        PJ3_OUT, PJ2_OUT, PJ1_OUT, PJ0_OUT,
+        /* Port K */
+        PK12_OUT,
+        PK11_OUT, PK10_OUT, PK9_OUT, PK8_OUT,
+        PK7_OUT, PK6_OUT, PK5_OUT, PK4_OUT,
+        PK3_OUT, PK2_OUT, PK1_OUT, PK0_OUT,
+        PINMUX_OUTPUT_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        /* Port A */
+        PA3_IOR_IN, PA3_IOR_OUT,
+        PA2_IOR_IN, PA2_IOR_OUT,
+        PA1_IOR_IN, PA1_IOR_OUT,
+        PA0_IOR_IN, PA0_IOR_OUT,
+
+        /* Port B */
+        PB11_IOR_IN, PB11_IOR_OUT,
+        PB10_IOR_IN, PB10_IOR_OUT,
+        PB9_IOR_IN, PB9_IOR_OUT,
+        PB8_IOR_IN, PB8_IOR_OUT,
+
+        PB22MD_00, PB22MD_01, PB22MD_10,
+        PB21MD_0, PB21MD_1,
+        PB20MD_0, PB20MD_1,
+        PB19MD_00, PB19MD_01, PB19MD_10, PB19MD_11,
+        PB18MD_00, PB18MD_01, PB18MD_10, PB18MD_11,
+        PB17MD_00, PB17MD_01, PB17MD_10, PB17MD_11,
+        PB16MD_00, PB16MD_01, PB16MD_10, PB16MD_11,
+        PB15MD_00, PB15MD_01, PB15MD_10, PB15MD_11,
+        PB14MD_00, PB14MD_01, PB14MD_10, PB14MD_11,
+        PB13MD_00, PB13MD_01, PB13MD_10, PB13MD_11,
+        PB12MD_00, PB12MD_01, PB12MD_10, PB12MD_11,
+        PB11MD_00, PB11MD_01, PB11MD_10, PB11MD_11,
+        PB10MD_00, PB10MD_01, PB10MD_10, PB10MD_11,
+        PB9MD_00, PB9MD_01, PB9MD_10, PB9MD_11,
+        PB8MD_00, PB8MD_01, PB8MD_10, PB8MD_11,
+        PB7MD_00, PB7MD_01, PB7MD_10, PB7MD_11,
+        PB6MD_00, PB6MD_01, PB6MD_10, PB6MD_11,
+        PB5MD_00, PB5MD_01, PB5MD_10, PB5MD_11,
+        PB4MD_00, PB4MD_01, PB4MD_10, PB4MD_11,
+        PB3MD_0, PB3MD_1,
+        PB2MD_0, PB2MD_1,
+        PB1MD_0, PB1MD_1,
+
+        /* Port C */
+        PC14_IOR_IN, PC14_IOR_OUT,
+        PC13_IOR_IN, PC13_IOR_OUT,
+        PC12_IOR_IN, PC12_IOR_OUT,
+        PC11_IOR_IN, PC11_IOR_OUT,
+        PC10_IOR_IN, PC10_IOR_OUT,
+        PC9_IOR_IN, PC9_IOR_OUT,
+        PC8_IOR_IN, PC8_IOR_OUT,
+        PC7_IOR_IN, PC7_IOR_OUT,
+        PC6_IOR_IN, PC6_IOR_OUT,
+        PC5_IOR_IN, PC5_IOR_OUT,
+        PC4_IOR_IN, PC4_IOR_OUT,
+        PC3_IOR_IN, PC3_IOR_OUT,
+        PC2_IOR_IN, PC2_IOR_OUT,
+        PC1_IOR_IN, PC1_IOR_OUT,
+        PC0_IOR_IN, PC0_IOR_OUT,
+
+        PC10MD_0, PC10MD_1,
+        PC9MD_0, PC9MD_1,
+        PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11,
+        PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11,
+        PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11,
+        PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11,
+        PC4MD_0, PC4MD_1,
+        PC3MD_0, PC3MD_1,
+        PC2MD_0, PC2MD_1,
+        PC1MD_0, PC1MD_1,
+        PC0MD_0, PC0MD_1,
+
+        /* Port D */
+        PD15_IOR_IN, PD15_IOR_OUT,
+        PD14_IOR_IN, PD14_IOR_OUT,
+        PD13_IOR_IN, PD13_IOR_OUT,
+        PD12_IOR_IN, PD12_IOR_OUT,
+        PD11_IOR_IN, PD11_IOR_OUT,
+        PD10_IOR_IN, PD10_IOR_OUT,
+        PD9_IOR_IN, PD9_IOR_OUT,
+        PD8_IOR_IN, PD8_IOR_OUT,
+        PD7_IOR_IN, PD7_IOR_OUT,
+        PD6_IOR_IN, PD6_IOR_OUT,
+        PD5_IOR_IN, PD5_IOR_OUT,
+        PD4_IOR_IN, PD4_IOR_OUT,
+        PD3_IOR_IN, PD3_IOR_OUT,
+        PD2_IOR_IN, PD2_IOR_OUT,
+        PD1_IOR_IN, PD1_IOR_OUT,
+        PD0_IOR_IN, PD0_IOR_OUT,
+
+        PD15MD_00, PD15MD_01, PD15MD_10, PD15MD_11,
+        PD14MD_00, PD14MD_01, PD14MD_10, PD14MD_11,
+        PD13MD_00, PD13MD_01, PD13MD_10, PD13MD_11,
+        PD12MD_00, PD12MD_01, PD12MD_10, PD12MD_11,
+        PD11MD_00, PD11MD_01, PD11MD_10, PD11MD_11,
+        PD10MD_00, PD10MD_01, PD10MD_10, PD10MD_11,
+        PD9MD_00, PD9MD_01, PD9MD_10, PD9MD_11,
+        PD8MD_00, PD8MD_01, PD8MD_10, PD8MD_11,
+        PD7MD_00, PD7MD_01, PD7MD_10, PD7MD_11,
+        PD6MD_00, PD6MD_01, PD6MD_10, PD6MD_11,
+        PD5MD_00, PD5MD_01, PD5MD_10, PD5MD_11,
+        PD4MD_00, PD4MD_01, PD4MD_10, PD4MD_11,
+        PD3MD_00, PD3MD_01, PD3MD_10, PD3MD_11,
+        PD2MD_00, PD2MD_01, PD2MD_10, PD2MD_11,
+        PD1MD_00, PD1MD_01, PD1MD_10, PD1MD_11,
+        PD0MD_00, PD0MD_01, PD0MD_10, PD0MD_11,
+
+        /* Port E */
+        PE5_IOR_IN, PE5_IOR_OUT,
+        PE4_IOR_IN, PE4_IOR_OUT,
+        PE3_IOR_IN, PE3_IOR_OUT,
+        PE2_IOR_IN, PE2_IOR_OUT,
+        PE1_IOR_IN, PE1_IOR_OUT,
+        PE0_IOR_IN, PE0_IOR_OUT,
+
+        PE5MD_00, PE5MD_01, PE5MD_10, PE5MD_11,
+        PE4MD_00, PE4MD_01, PE4MD_10, PE4MD_11,
+        PE3MD_00, PE3MD_01, PE3MD_10, PE3MD_11,
+        PE2MD_00, PE2MD_01, PE2MD_10, PE2MD_11,
+        PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
+        PE1MD_100, PE1MD_101, PE1MD_110, PE1MD_111,
+        PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11,
+
+        /* Port F */
+        PF12_IOR_IN, PF12_IOR_OUT,
+        PF11_IOR_IN, PF11_IOR_OUT,
+        PF10_IOR_IN, PF10_IOR_OUT,
+        PF9_IOR_IN, PF9_IOR_OUT,
+        PF8_IOR_IN, PF8_IOR_OUT,
+        PF7_IOR_IN, PF7_IOR_OUT,
+        PF6_IOR_IN, PF6_IOR_OUT,
+        PF5_IOR_IN, PF5_IOR_OUT,
+        PF4_IOR_IN, PF4_IOR_OUT,
+        PF3_IOR_IN, PF3_IOR_OUT,
+        PF2_IOR_IN, PF2_IOR_OUT,
+        PF1_IOR_IN, PF1_IOR_OUT,
+        PF0_IOR_IN, PF0_IOR_OUT,
+
+        PF12MD_000, PF12MD_001, PF12MD_010, PF12MD_011,
+        PF12MD_100, PF12MD_101, PF12MD_110, PF12MD_111,
+        PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
+        PF11MD_100, PF11MD_101, PF11MD_110, PF11MD_111,
+        PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
+        PF10MD_100, PF10MD_101, PF10MD_110, PF10MD_111,
+        PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
+        PF9MD_100, PF9MD_101, PF9MD_110, PF9MD_111,
+        PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11,
+        PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
+        PF7MD_100, PF7MD_101, PF7MD_110, PF7MD_111,
+        PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
+        PF6MD_100, PF6MD_101, PF6MD_110, PF6MD_111,
+        PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
+        PF5MD_100, PF5MD_101, PF5MD_110, PF5MD_111,
+        PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
+        PF4MD_100, PF4MD_101, PF4MD_110, PF4MD_111,
+        PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
+        PF3MD_100, PF3MD_101, PF3MD_110, PF3MD_111,
+        PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
+        PF2MD_100, PF2MD_101, PF2MD_110, PF2MD_111,
+        PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
+        PF1MD_100, PF1MD_101, PF1MD_110, PF1MD_111,
+        PF0MD_000, PF0MD_001, PF0MD_010, PF0MD_011,
+        PF0MD_100, PF0MD_101, PF0MD_110, PF0MD_111,
+
+        /* Port G */
+        PG24_IOR_IN, PG24_IOR_OUT,
+        PG23_IOR_IN, PG23_IOR_OUT,
+        PG22_IOR_IN, PG22_IOR_OUT,
+        PG21_IOR_IN, PG21_IOR_OUT,
+        PG20_IOR_IN, PG20_IOR_OUT,
+        PG19_IOR_IN, PG19_IOR_OUT,
+        PG18_IOR_IN, PG18_IOR_OUT,
+        PG17_IOR_IN, PG17_IOR_OUT,
+        PG16_IOR_IN, PG16_IOR_OUT,
+        PG15_IOR_IN, PG15_IOR_OUT,
+        PG14_IOR_IN, PG14_IOR_OUT,
+        PG13_IOR_IN, PG13_IOR_OUT,
+        PG12_IOR_IN, PG12_IOR_OUT,
+        PG11_IOR_IN, PG11_IOR_OUT,
+        PG10_IOR_IN, PG10_IOR_OUT,
+        PG9_IOR_IN, PG9_IOR_OUT,
+        PG8_IOR_IN, PG8_IOR_OUT,
+        PG7_IOR_IN, PG7_IOR_OUT,
+        PG6_IOR_IN, PG6_IOR_OUT,
+        PG5_IOR_IN, PG5_IOR_OUT,
+        PG4_IOR_IN, PG4_IOR_OUT,
+        PG3_IOR_IN, PG3_IOR_OUT,
+        PG2_IOR_IN, PG2_IOR_OUT,
+        PG1_IOR_IN, PG1_IOR_OUT,
+        PG0_IOR_IN, PG0_IOR_OUT,
+
+        PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11,
+        PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11,
+        PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11,
+        PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11,
+        PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
+        PG20MD_100, PG20MD_101, PG20MD_110, PG20MD_111,
+        PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
+        PG19MD_100, PG19MD_101, PG19MD_110, PG19MD_111,
+        PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
+        PG18MD_100, PG18MD_101, PG18MD_110, PG18MD_111,
+        PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
+        PG17MD_100, PG17MD_101, PG17MD_110, PG17MD_111,
+        PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
+        PG16MD_100, PG16MD_101, PG16MD_110, PG16MD_111,
+        PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
+        PG15MD_100, PG15MD_101, PG15MD_110, PG15MD_111,
+        PG14MD_000, PG14MD_001, PG14MD_010, PG14MD_011,
+        PG14MD_100, PG14MD_101, PG14MD_110, PG14MD_111,
+        PG13MD_000, PG13MD_001, PG13MD_010, PG13MD_011,
+        PG13MD_100, PG13MD_101, PG13MD_110, PG13MD_111,
+        PG12MD_000, PG12MD_001, PG12MD_010, PG12MD_011,
+        PG12MD_100, PG12MD_101, PG12MD_110, PG12MD_111,
+        PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
+        PG11MD_100, PG11MD_101, PG11MD_110, PG11MD_111,
+        PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
+        PG10MD_100, PG10MD_101, PG10MD_110, PG10MD_111,
+        PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
+        PG9MD_100, PG9MD_101, PG9MD_110, PG9MD_111,
+        PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
+        PG8MD_100, PG8MD_101, PG8MD_110, PG8MD_111,
+        PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11,
+        PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11,
+        PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11,
+        PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11,
+        PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11,
+        PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11,
+        PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11,
+        PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
+        PG0MD_100, PG0MD_101, PG0MD_110, PG0MD_111,
+
+        /* Port H */
+        PH7MD_0, PH7MD_1,
+        PH6MD_0, PH6MD_1,
+        PH5MD_0, PH5MD_1,
+        PH4MD_0, PH4MD_1,
+        PH3MD_0, PH3MD_1,
+        PH2MD_0, PH2MD_1,
+        PH1MD_0, PH1MD_1,
+        PH0MD_0, PH0MD_1,
+
+        /* Port I - not on device */
+
+        /* Port J */
+        PJ11_IOR_IN, PJ11_IOR_OUT,
+        PJ10_IOR_IN, PJ10_IOR_OUT,
+        PJ9_IOR_IN, PJ9_IOR_OUT,
+        PJ8_IOR_IN, PJ8_IOR_OUT,
+        PJ7_IOR_IN, PJ7_IOR_OUT,
+        PJ6_IOR_IN, PJ6_IOR_OUT,
+        PJ5_IOR_IN, PJ5_IOR_OUT,
+        PJ4_IOR_IN, PJ4_IOR_OUT,
+        PJ3_IOR_IN, PJ3_IOR_OUT,
+        PJ2_IOR_IN, PJ2_IOR_OUT,
+        PJ1_IOR_IN, PJ1_IOR_OUT,
+        PJ0_IOR_IN, PJ0_IOR_OUT,
+
+        PJ11MD_00, PJ11MD_01, PJ11MD_10, PJ11MD_11,
+        PJ10MD_00, PJ10MD_01, PJ10MD_10, PJ10MD_11,
+        PJ9MD_00, PJ9MD_01, PJ9MD_10, PJ9MD_11,
+        PJ8MD_00, PJ8MD_01, PJ8MD_10, PJ8MD_11,
+        PJ7MD_00, PJ7MD_01, PJ7MD_10, PJ7MD_11,
+        PJ6MD_00, PJ6MD_01, PJ6MD_10, PJ6MD_11,
+        PJ5MD_00, PJ5MD_01, PJ5MD_10, PJ5MD_11,
+        PJ4MD_00, PJ4MD_01, PJ4MD_10, PJ4MD_11,
+        PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11,
+        PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
+        PJ2MD_100, PJ2MD_101, PJ2MD_110, PJ2MD_111,
+        PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
+        PJ1MD_100, PJ1MD_101, PJ1MD_110, PJ1MD_111,
+        PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
+        PJ0MD_100, PJ0MD_101, PJ0MD_110, PJ0MD_111,
+
+        /* Port K */
+        PK11_IOR_IN, PK11_IOR_OUT,
+        PK10_IOR_IN, PK10_IOR_OUT,
+        PK9_IOR_IN, PK9_IOR_OUT,
+        PK8_IOR_IN, PK8_IOR_OUT,
+        PK7_IOR_IN, PK7_IOR_OUT,
+        PK6_IOR_IN, PK6_IOR_OUT,
+        PK5_IOR_IN, PK5_IOR_OUT,
+        PK4_IOR_IN, PK4_IOR_OUT,
+        PK3_IOR_IN, PK3_IOR_OUT,
+        PK2_IOR_IN, PK2_IOR_OUT,
+        PK1_IOR_IN, PK1_IOR_OUT,
+        PK0_IOR_IN, PK0_IOR_OUT,
+
+        PK11MD_00, PK11MD_01, PK11MD_10, PK11MD_11,
+        PK10MD_00, PK10MD_01, PK10MD_10, PK10MD_11,
+        PK9MD_00, PK9MD_01, PK9MD_10, PK9MD_11,
+        PK8MD_00, PK8MD_01, PK8MD_10, PK8MD_11,
+        PK7MD_00, PK7MD_01, PK7MD_10, PK7MD_11,
+        PK6MD_00, PK6MD_01, PK6MD_10, PK6MD_11,
+        PK5MD_00, PK5MD_01, PK5MD_10, PK5MD_11,
+        PK4MD_00, PK4MD_01, PK4MD_10, PK4MD_11,
+        PK3MD_00, PK3MD_01, PK3MD_10, PK3MD_11,
+        PK2MD_00, PK2MD_01, PK2MD_10, PK2MD_11,
+        PK1MD_00, PK1MD_01, PK1MD_10, PK1MD_11,
+        PK0MD_00, PK0MD_01, PK0MD_10, PK0MD_11,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+        /* Port A */
+
+        /* Port B */
+
+        /* Port C */
+
+        /* Port D */
+
+        /* Port E */
+
+        /* Port F */
+
+        /* Port G */
+
+        /* Port H */
+        PHAN7_MARK, PHAN6_MARK, PHAN5_MARK, PHAN4_MARK,
+        PHAN3_MARK, PHAN2_MARK, PHAN1_MARK, PHAN0_MARK,
+
+        /* Port I - not on device */
+
+        /* Port J */
+
+        /* Port K */
+
+        IRQ7_PC_MARK, IRQ6_PC_MARK, IRQ5_PC_MARK, IRQ4_PC_MARK,
+        IRQ3_PG_MARK, IRQ2_PG_MARK, IRQ1_PJ_MARK, IRQ0_PJ_MARK,
+        IRQ3_PE_MARK, IRQ2_PE_MARK, IRQ1_PE_MARK, IRQ0_PE_MARK,
+
+        PINT7_PG_MARK, PINT6_PG_MARK, PINT5_PG_MARK, PINT4_PG_MARK,
+        PINT3_PG_MARK, PINT2_PG_MARK, PINT1_PG_MARK, PINT0_PG_MARK,
+
+        SD_CD_MARK, SD_D0_MARK, SD_D1_MARK, SD_D2_MARK, SD_D3_MARK,
+        SD_WP_MARK, SD_CLK_MARK, SD_CMD_MARK,
+        CRX0_MARK, CRX1_MARK,
+        CTX0_MARK, CTX1_MARK,
+
+        PWM1A_MARK, PWM1B_MARK, PWM1C_MARK, PWM1D_MARK,
+        PWM1E_MARK, PWM1F_MARK, PWM1G_MARK, PWM1H_MARK,
+        PWM2A_MARK, PWM2B_MARK, PWM2C_MARK, PWM2D_MARK,
+        PWM2E_MARK, PWM2F_MARK, PWM2G_MARK, PWM2H_MARK,
+        IERXD_MARK, IETXD_MARK,
+        CRX0CRX1_MARK,
+        WDTOVF_MARK,
+
+        CRX0X1_MARK,
+
+        /* DMAC */
+        TEND0_MARK, DACK0_MARK, DREQ0_MARK,
+        TEND1_MARK, DACK1_MARK, DREQ1_MARK,
+
+        /* ADC */
+        ADTRG_MARK,
+
+        /* BSC */
+        A25_MARK, A24_MARK,
+        A23_MARK, A22_MARK, A21_MARK, A20_MARK,
+        A19_MARK, A18_MARK, A17_MARK, A16_MARK,
+        A15_MARK, A14_MARK, A13_MARK, A12_MARK,
+        A11_MARK, A10_MARK, A9_MARK, A8_MARK,
+        A7_MARK, A6_MARK, A5_MARK, A4_MARK,
+        A3_MARK, A2_MARK, A1_MARK, A0_MARK,
+        D15_MARK, D14_MARK, D13_MARK, D12_MARK,
+        D11_MARK, D10_MARK, D9_MARK, D8_MARK,
+        D7_MARK, D6_MARK, D5_MARK, D4_MARK,
+        D3_MARK, D2_MARK, D1_MARK, D0_MARK,
+        BS_MARK,
+        CS4_MARK, CS3_MARK, CS2_MARK, CS1_MARK, CS0_MARK,
+        CS6CE1B_MARK, CS5CE1A_MARK,
+        CE2A_MARK, CE2B_MARK,
+        RD_MARK, RDWR_MARK,
+        ICIOWRAH_MARK,
+        ICIORD_MARK,
+        WE1DQMUWE_MARK,
+        WE0DQML_MARK,
+        RAS_MARK, CAS_MARK, CKE_MARK,
+        WAIT_MARK, BREQ_MARK, BACK_MARK, IOIS16_MARK,
+
+        /* TMU */
+        TIOC0A_MARK, TIOC0B_MARK, TIOC0C_MARK, TIOC0D_MARK,
+        TIOC1A_MARK, TIOC1B_MARK,
+        TIOC2A_MARK, TIOC2B_MARK,
+        TIOC3A_MARK, TIOC3B_MARK, TIOC3C_MARK, TIOC3D_MARK,
+        TIOC4A_MARK, TIOC4B_MARK, TIOC4C_MARK, TIOC4D_MARK,
+        TCLKA_MARK,     TCLKB_MARK, TCLKC_MARK, TCLKD_MARK,
+
+        /* SCIF */
+        SCK0_MARK, SCK1_MARK, SCK2_MARK, SCK3_MARK,
+        RXD0_MARK, RXD1_MARK, RXD2_MARK, RXD3_MARK,
+        TXD0_MARK, TXD1_MARK, TXD2_MARK, TXD3_MARK,
+        RXD4_MARK, RXD5_MARK, RXD6_MARK, RXD7_MARK,
+        TXD4_MARK, TXD5_MARK, TXD6_MARK, TXD7_MARK,
+        RTS1_MARK, RTS3_MARK,
+        CTS1_MARK, CTS3_MARK,
+
+        /* RSPI */
+        RSPCK0_MARK, RSPCK1_MARK,
+        MOSI0_MARK, MOSI1_MARK,
+        MISO0_PF12_MARK, MISO1_MARK, MISO1_PG19_MARK,
+        SSL00_MARK, SSL10_MARK,
+
+        /* IIC3 */
+        SCL0_MARK, SCL1_MARK, SCL2_MARK,
+        SDA0_MARK, SDA1_MARK, SDA2_MARK,
+
+        /* SSI */
+        SSISCK0_MARK,
+        SSIWS0_MARK,
+        SSITXD0_MARK,
+        SSIRXD0_MARK,
+        SSIWS1_MARK, SSIWS2_MARK, SSIWS3_MARK,
+        SSISCK1_MARK, SSISCK2_MARK, SSISCK3_MARK,
+        SSIDATA1_MARK, SSIDATA2_MARK, SSIDATA3_MARK,
+        AUDIO_CLK_MARK,
+
+        /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
+        SIOFTXD_MARK, SIOFRXD_MARK, SIOFSYNC_MARK, SIOFSCK_MARK,
+
+        /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
+        SPDIF_IN_MARK, SPDIF_OUT_MARK,
+
+        /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
+        FCE_MARK,
+        FRB_MARK,
+
+        /* VDC3 */
+        DV_CLK_MARK,
+        DV_VSYNC_MARK, DV_HSYNC_MARK,
+        DV_DATA7_MARK, DV_DATA6_MARK, DV_DATA5_MARK, DV_DATA4_MARK,
+        DV_DATA3_MARK, DV_DATA2_MARK, DV_DATA1_MARK, DV_DATA0_MARK,
+        LCD_CLK_MARK, LCD_EXTCLK_MARK,
+        LCD_VSYNC_MARK, LCD_HSYNC_MARK, LCD_DE_MARK,
+        LCD_DATA15_MARK, LCD_DATA14_MARK, LCD_DATA13_MARK, LCD_DATA12_MARK,
+        LCD_DATA11_MARK, LCD_DATA10_MARK, LCD_DATA9_MARK, LCD_DATA8_MARK,
+        LCD_DATA7_MARK, LCD_DATA6_MARK, LCD_DATA5_MARK, LCD_DATA4_MARK,
+        LCD_DATA3_MARK, LCD_DATA2_MARK, LCD_DATA1_MARK, LCD_DATA0_MARK,
+        LCD_M_DISP_MARK,
+        PINMUX_MARK_END,
+};
+
+static pinmux_enum_t pinmux_data[] = {
+
+        /* Port A */
+        PINMUX_DATA(PA3_DATA, PA3_IN),
+        PINMUX_DATA(PA2_DATA, PA2_IN),
+        PINMUX_DATA(PA1_DATA, PA1_IN),
+        PINMUX_DATA(PA0_DATA, PA0_IN),
+
+        /* Port B */
+        PINMUX_DATA(PB22_DATA, PB22MD_00, PB22_IN, PB22_OUT),
+        PINMUX_DATA(A22_MARK, PB22MD_01),
+        PINMUX_DATA(CS4_MARK, PB22MD_10),
+
+        PINMUX_DATA(PB21_DATA, PB21MD_0, PB21_IN, PB21_OUT),
+        PINMUX_DATA(A21_MARK, PB21MD_1),
+        PINMUX_DATA(A20_MARK, PB20MD_1),
+        PINMUX_DATA(A19_MARK, PB19MD_01),
+        PINMUX_DATA(A18_MARK, PB18MD_01),
+        PINMUX_DATA(A17_MARK, PB17MD_01),
+        PINMUX_DATA(A16_MARK, PB16MD_01),
+        PINMUX_DATA(A15_MARK, PB15MD_01),
+        PINMUX_DATA(A14_MARK, PB14MD_01),
+        PINMUX_DATA(A13_MARK, PB13MD_01),
+        PINMUX_DATA(A12_MARK, PB12MD_01),
+        PINMUX_DATA(A11_MARK, PB11MD_01),
+        PINMUX_DATA(A10_MARK, PB10MD_01),
+        PINMUX_DATA(A9_MARK, PB9MD_01),
+        PINMUX_DATA(A8_MARK, PB8MD_01),
+        PINMUX_DATA(A7_MARK, PB7MD_01),
+        PINMUX_DATA(A6_MARK, PB6MD_01),
+        PINMUX_DATA(A5_MARK, PB5MD_01),
+        PINMUX_DATA(A4_MARK, PB4MD_01),
+        PINMUX_DATA(A3_MARK, PB3MD_1),
+        PINMUX_DATA(A2_MARK, PB2MD_1),
+        PINMUX_DATA(A1_MARK, PB1MD_1),
+
+        /* Port C */
+        PINMUX_DATA(PC10_DATA, PC10MD_0),
+        PINMUX_DATA(TIOC2B_MARK, PC1MD_1),
+        PINMUX_DATA(PC9_DATA, PC9MD_0),
+        PINMUX_DATA(TIOC2A_MARK, PC9MD_1),
+        PINMUX_DATA(PC8_DATA, PC8MD_00),
+        PINMUX_DATA(CS3_MARK, PC8MD_01),
+        PINMUX_DATA(TIOC4D_MARK, PC8MD_10),
+        PINMUX_DATA(IRQ7_PC_MARK, PC8MD_11),
+        PINMUX_DATA(PC7_DATA, PC7MD_00),
+        PINMUX_DATA(CKE_MARK, PC7MD_01),
+        PINMUX_DATA(TIOC4C_MARK, PC7MD_10),
+        PINMUX_DATA(IRQ6_PC_MARK, PC7MD_11),
+        PINMUX_DATA(PC6_DATA, PC6MD_00),
+        PINMUX_DATA(CAS_MARK, PC6MD_01),
+        PINMUX_DATA(TIOC4B_MARK, PC6MD_10),
+        PINMUX_DATA(IRQ5_PC_MARK, PC6MD_11),
+        PINMUX_DATA(PC5_DATA, PC5MD_00),
+        PINMUX_DATA(RAS_MARK, PC5MD_01),
+        PINMUX_DATA(TIOC4A_MARK, PC5MD_10),
+        PINMUX_DATA(IRQ4_PC_MARK, PC5MD_11),
+        PINMUX_DATA(PC4_DATA, PC4MD_0),
+        PINMUX_DATA(WE1DQMUWE_MARK, PC4MD_1),
+        PINMUX_DATA(PC3_DATA, PC3MD_0),
+        PINMUX_DATA(WE0DQML_MARK, PC3MD_1),
+        PINMUX_DATA(PC2_DATA, PC2MD_0),
+        PINMUX_DATA(RDWR_MARK, PC2MD_1),
+        PINMUX_DATA(PC1_DATA, PC1MD_0),
+        PINMUX_DATA(RD_MARK, PC1MD_1),
+        PINMUX_DATA(PC0_DATA, PC0MD_0),
+        PINMUX_DATA(CS0_MARK, PC0MD_1),
+
+        /* Port D */
+        PINMUX_DATA(D15_MARK, PD15MD_01),
+        PINMUX_DATA(D14_MARK, PD14MD_01),
+        PINMUX_DATA(D13_MARK, PD13MD_01),
+        PINMUX_DATA(D12_MARK, PD12MD_01),
+        PINMUX_DATA(D11_MARK, PD11MD_01),
+        PINMUX_DATA(D10_MARK, PD10MD_01),
+        PINMUX_DATA(D9_MARK, PD9MD_01),
+        PINMUX_DATA(D8_MARK, PD8MD_01),
+        PINMUX_DATA(D7_MARK, PD7MD_01),
+        PINMUX_DATA(D6_MARK, PD6MD_01),
+        PINMUX_DATA(D5_MARK, PD5MD_01),
+        PINMUX_DATA(D4_MARK, PD4MD_01),
+        PINMUX_DATA(D3_MARK, PD3MD_01),
+        PINMUX_DATA(D2_MARK, PD2MD_01),
+        PINMUX_DATA(D1_MARK, PD1MD_01),
+        PINMUX_DATA(D0_MARK, PD0MD_01),
+
+        /* Port E */
+        PINMUX_DATA(PE5_DATA, PE5MD_00),
+        PINMUX_DATA(SDA2_MARK, PE5MD_01),
+        PINMUX_DATA(DV_HSYNC_MARK, PE5MD_11),
+
+        PINMUX_DATA(PE4_DATA, PE4MD_00),
+        PINMUX_DATA(SCL2_MARK, PE4MD_01),
+        PINMUX_DATA(DV_VSYNC_MARK, PE4MD_11),
+
+        PINMUX_DATA(PE3_DATA, PE3MD_00),
+        PINMUX_DATA(SDA1_MARK, PE3MD_01),
+        PINMUX_DATA(IRQ3_PE_MARK, PE3MD_11),
+
+        PINMUX_DATA(PE2_DATA, PE2MD_00),
+        PINMUX_DATA(SCL1_MARK, PE2MD_01),
+        PINMUX_DATA(IRQ2_PE_MARK, PE2MD_11),
+
+        PINMUX_DATA(PE1_DATA, PE1MD_000),
+        PINMUX_DATA(SDA0_MARK, PE1MD_001),
+        PINMUX_DATA(IOIS16_MARK, PE1MD_010),
+        PINMUX_DATA(IRQ1_PE_MARK, PE1MD_011),
+        PINMUX_DATA(TCLKA_MARK, PE1MD_100),
+        PINMUX_DATA(ADTRG_MARK, PE1MD_101),
+
+        PINMUX_DATA(PE0_DATA, PE0MD_00),
+        PINMUX_DATA(SCL0_MARK, PE0MD_01),
+        PINMUX_DATA(AUDIO_CLK_MARK, PE0MD_10),
+        PINMUX_DATA(IRQ0_PE_MARK, PE0MD_11),
+
+        /* Port F */
+        PINMUX_DATA(PF12_DATA, PF12MD_000),
+        PINMUX_DATA(BS_MARK, PF12MD_001),
+        PINMUX_DATA(MISO0_PF12_MARK, PF12MD_011),
+        PINMUX_DATA(TIOC3D_MARK, PF12MD_100),
+        PINMUX_DATA(SPDIF_OUT_MARK, PF12MD_101),
+
+        PINMUX_DATA(PF11_DATA, PF11MD_000),
+        PINMUX_DATA(A25_MARK, PF11MD_001),
+        PINMUX_DATA(SSIDATA3_MARK, PF11MD_010),
+        PINMUX_DATA(MOSI0_MARK, PF11MD_011),
+        PINMUX_DATA(TIOC3C_MARK, PF11MD_100),
+        PINMUX_DATA(SPDIF_IN_MARK, PF11MD_101),
+
+        PINMUX_DATA(PF10_DATA, PF10MD_000),
+        PINMUX_DATA(A24_MARK, PF10MD_001),
+        PINMUX_DATA(SSIWS3_MARK, PF10MD_010),
+        PINMUX_DATA(SSL00_MARK, PF10MD_011),
+        PINMUX_DATA(TIOC3B_MARK, PF10MD_100),
+        PINMUX_DATA(FCE_MARK, PF10MD_101),
+
+        PINMUX_DATA(PF9_DATA, PF9MD_000),
+        PINMUX_DATA(A23_MARK, PF9MD_001),
+        PINMUX_DATA(SSISCK3_MARK, PF9MD_010),
+        PINMUX_DATA(RSPCK0_MARK, PF9MD_011),
+        PINMUX_DATA(TIOC3A_MARK, PF9MD_100),
+        PINMUX_DATA(FRB_MARK, PF9MD_101),
+
+        PINMUX_DATA(PF8_DATA, PF8MD_00),
+        PINMUX_DATA(CE2B_MARK, PF8MD_01),
+        PINMUX_DATA(SSIDATA3_MARK, PF8MD_10),
+        PINMUX_DATA(DV_CLK_MARK, PF8MD_11),
+
+        PINMUX_DATA(PF7_DATA, PF7MD_000),
+        PINMUX_DATA(CE2A_MARK, PF7MD_001),
+        PINMUX_DATA(SSIWS3_MARK, PF7MD_010),
+        PINMUX_DATA(DV_DATA7_MARK, PF7MD_011),
+        PINMUX_DATA(TCLKD_MARK, PF7MD_100),
+
+        PINMUX_DATA(PF6_DATA, PF6MD_000),
+        PINMUX_DATA(CS6CE1B_MARK, PF6MD_001),
+        PINMUX_DATA(SSISCK3_MARK, PF6MD_010),
+        PINMUX_DATA(DV_DATA6_MARK, PF6MD_011),
+        PINMUX_DATA(TCLKB_MARK, PF6MD_100),
+
+        PINMUX_DATA(PF5_DATA, PF5MD_000),
+        PINMUX_DATA(CS5CE1A_MARK, PF5MD_001),
+        PINMUX_DATA(SSIDATA2_MARK, PF5MD_010),
+        PINMUX_DATA(DV_DATA5_MARK, PF5MD_011),
+        PINMUX_DATA(TCLKC_MARK, PF5MD_100),
+
+        PINMUX_DATA(PF4_DATA, PF4MD_000),
+        PINMUX_DATA(ICIOWRAH_MARK, PF4MD_001),
+        PINMUX_DATA(SSIWS2_MARK, PF4MD_010),
+        PINMUX_DATA(DV_DATA4_MARK, PF4MD_011),
+        PINMUX_DATA(TXD3_MARK, PF4MD_100),
+
+        PINMUX_DATA(PF3_DATA, PF3MD_000),
+        PINMUX_DATA(ICIORD_MARK, PF3MD_001),
+        PINMUX_DATA(SSISCK2_MARK, PF3MD_010),
+        PINMUX_DATA(DV_DATA3_MARK, PF3MD_011),
+        PINMUX_DATA(RXD3_MARK, PF3MD_100),
+
+        PINMUX_DATA(PF2_DATA, PF2MD_000),
+        PINMUX_DATA(BACK_MARK, PF2MD_001),
+        PINMUX_DATA(SSIDATA1_MARK, PF2MD_010),
+        PINMUX_DATA(DV_DATA2_MARK, PF2MD_011),
+        PINMUX_DATA(TXD2_MARK, PF2MD_100),
+        PINMUX_DATA(DACK0_MARK, PF2MD_101),
+
+        PINMUX_DATA(PF1_DATA, PF1MD_000),
+        PINMUX_DATA(BREQ_MARK, PF1MD_001),
+        PINMUX_DATA(SSIWS1_MARK, PF1MD_010),
+        PINMUX_DATA(DV_DATA1_MARK, PF1MD_011),
+        PINMUX_DATA(RXD2_MARK, PF1MD_100),
+        PINMUX_DATA(DREQ0_MARK, PF1MD_101),
+
+        PINMUX_DATA(PF0_DATA, PF0MD_000),
+        PINMUX_DATA(WAIT_MARK, PF0MD_001),
+        PINMUX_DATA(SSISCK1_MARK, PF0MD_010),
+        PINMUX_DATA(DV_DATA0_MARK, PF0MD_011),
+        PINMUX_DATA(SCK2_MARK, PF0MD_100),
+        PINMUX_DATA(TEND0_MARK, PF0MD_101),
+
+        /* Port G */
+        PINMUX_DATA(PG24_DATA, PG24MD_00),
+        PINMUX_DATA(MOSI0_MARK, PG24MD_01),
+        PINMUX_DATA(TIOC0D_MARK, PG24MD_10),
+
+        PINMUX_DATA(PG23_DATA, PG23MD_00),
+        PINMUX_DATA(MOSI1_MARK, PG23MD_01),
+        PINMUX_DATA(TIOC0C_MARK, PG23MD_10),
+
+        PINMUX_DATA(PG22_DATA, PG22MD_00),
+        PINMUX_DATA(SSL10_MARK, PG22MD_01),
+        PINMUX_DATA(TIOC0B_MARK, PG22MD_10),
+
+        PINMUX_DATA(PG21_DATA, PG21MD_00),
+        PINMUX_DATA(RSPCK1_MARK, PG21MD_01),
+        PINMUX_DATA(TIOC0A_MARK, PG21MD_10),
+
+        PINMUX_DATA(PG20_DATA, PG20MD_000),
+        PINMUX_DATA(LCD_EXTCLK_MARK, PG20MD_001),
+        PINMUX_DATA(MISO1_MARK, PG20MD_011),
+        PINMUX_DATA(TXD7_MARK, PG20MD_100),
+
+        PINMUX_DATA(PG19_DATA, PG19MD_000),
+        PINMUX_DATA(LCD_CLK_MARK, PG19MD_001),
+        PINMUX_DATA(TIOC2B_MARK, PG19MD_010),
+        PINMUX_DATA(MISO1_PG19_MARK, PG19MD_011),
+        PINMUX_DATA(RXD7_MARK, PG19MD_100),
+
+        PINMUX_DATA(PG18_DATA, PG18MD_000),
+        PINMUX_DATA(LCD_DE_MARK, PG18MD_001),
+        PINMUX_DATA(TIOC2A_MARK, PG18MD_010),
+        PINMUX_DATA(SSL10_MARK, PG18MD_011),
+        PINMUX_DATA(TXD6_MARK, PG18MD_100),
+
+        PINMUX_DATA(PG17_DATA, PG17MD_000),
+        PINMUX_DATA(LCD_HSYNC_MARK, PG17MD_001),
+        PINMUX_DATA(TIOC1B_MARK, PG17MD_010),
+        PINMUX_DATA(RSPCK1_MARK, PG17MD_011),
+        PINMUX_DATA(RXD6_MARK, PG17MD_100),
+
+        PINMUX_DATA(PG16_DATA, PG16MD_000),
+        PINMUX_DATA(LCD_VSYNC_MARK, PG16MD_001),
+        PINMUX_DATA(TIOC1A_MARK, PG16MD_010),
+        PINMUX_DATA(TXD3_MARK, PG16MD_011),
+        PINMUX_DATA(CTS1_MARK, PG16MD_100),
+
+        PINMUX_DATA(PG15_DATA, PG15MD_000),
+        PINMUX_DATA(LCD_DATA15_MARK, PG15MD_001),
+        PINMUX_DATA(TIOC0D_MARK, PG15MD_010),
+        PINMUX_DATA(RXD3_MARK, PG15MD_011),
+        PINMUX_DATA(RTS1_MARK, PG15MD_100),
+
+        PINMUX_DATA(PG14_DATA, PG14MD_000),
+        PINMUX_DATA(LCD_DATA14_MARK, PG14MD_001),
+        PINMUX_DATA(TIOC0C_MARK, PG14MD_010),
+        PINMUX_DATA(SCK1_MARK, PG14MD_100),
+
+        PINMUX_DATA(PG13_DATA, PG13MD_000),
+        PINMUX_DATA(LCD_DATA13_MARK, PG13MD_001),
+        PINMUX_DATA(TIOC0B_MARK, PG13MD_010),
+        PINMUX_DATA(TXD1_MARK, PG13MD_100),
+
+        PINMUX_DATA(PG12_DATA, PG12MD_000),
+        PINMUX_DATA(LCD_DATA12_MARK, PG12MD_001),
+        PINMUX_DATA(TIOC0A_MARK, PG12MD_010),
+        PINMUX_DATA(RXD1_MARK, PG12MD_100),
+
+        PINMUX_DATA(PG11_DATA, PG11MD_000),
+        PINMUX_DATA(LCD_DATA11_MARK, PG11MD_001),
+        PINMUX_DATA(SSITXD0_MARK, PG11MD_010),
+        PINMUX_DATA(IRQ3_PG_MARK, PG11MD_011),
+        PINMUX_DATA(TXD5_MARK, PG11MD_100),
+        PINMUX_DATA(SIOFTXD_MARK, PG11MD_101),
+
+        PINMUX_DATA(PG10_DATA, PG10MD_000),
+        PINMUX_DATA(LCD_DATA10_MARK, PG10MD_001),
+        PINMUX_DATA(SSIRXD0_MARK, PG10MD_010),
+        PINMUX_DATA(IRQ2_PG_MARK, PG10MD_011),
+        PINMUX_DATA(RXD5_MARK, PG10MD_100),
+        PINMUX_DATA(SIOFRXD_MARK, PG10MD_101),
+
+        PINMUX_DATA(PG9_DATA, PG9MD_000),
+        PINMUX_DATA(LCD_DATA9_MARK, PG9MD_001),
+        PINMUX_DATA(SSIWS0_MARK, PG9MD_010),
+        PINMUX_DATA(TXD4_MARK, PG9MD_100),
+        PINMUX_DATA(SIOFSYNC_MARK, PG9MD_101),
+
+        PINMUX_DATA(PG8_DATA, PG8MD_000),
+        PINMUX_DATA(LCD_DATA8_MARK, PG8MD_001),
+        PINMUX_DATA(SSISCK0_MARK, PG8MD_010),
+        PINMUX_DATA(RXD4_MARK, PG8MD_100),
+        PINMUX_DATA(SIOFSCK_MARK, PG8MD_101),
+
+        PINMUX_DATA(PG7_DATA, PG7MD_00),
+        PINMUX_DATA(LCD_DATA7_MARK, PG7MD_01),
+        PINMUX_DATA(SD_CD_MARK, PG7MD_10),
+        PINMUX_DATA(PINT7_PG_MARK, PG7MD_11),
+
+        PINMUX_DATA(PG6_DATA, PG7MD_00),
+        PINMUX_DATA(LCD_DATA6_MARK, PG7MD_01),
+        PINMUX_DATA(SD_WP_MARK, PG7MD_10),
+        PINMUX_DATA(PINT6_PG_MARK, PG7MD_11),
+
+        PINMUX_DATA(PG5_DATA, PG5MD_00),
+        PINMUX_DATA(LCD_DATA5_MARK, PG5MD_01),
+        PINMUX_DATA(SD_D1_MARK, PG5MD_10),
+        PINMUX_DATA(PINT5_PG_MARK, PG5MD_11),
+
+        PINMUX_DATA(PG4_DATA, PG4MD_00),
+        PINMUX_DATA(LCD_DATA4_MARK, PG4MD_01),
+        PINMUX_DATA(SD_D0_MARK, PG4MD_10),
+        PINMUX_DATA(PINT4_PG_MARK, PG4MD_11),
+
+        PINMUX_DATA(PG3_DATA, PG3MD_00),
+        PINMUX_DATA(LCD_DATA3_MARK, PG3MD_01),
+        PINMUX_DATA(SD_CLK_MARK, PG3MD_10),
+        PINMUX_DATA(PINT3_PG_MARK, PG3MD_11),
+
+        PINMUX_DATA(PG2_DATA, PG2MD_00),
+        PINMUX_DATA(LCD_DATA2_MARK, PG2MD_01),
+        PINMUX_DATA(SD_CMD_MARK, PG2MD_10),
+        PINMUX_DATA(PINT2_PG_MARK, PG2MD_11),
+
+        PINMUX_DATA(PG1_DATA, PG1MD_00),
+        PINMUX_DATA(LCD_DATA1_MARK, PG1MD_01),
+        PINMUX_DATA(SD_D3_MARK, PG1MD_10),
+        PINMUX_DATA(PINT1_PG_MARK, PG1MD_11),
+
+        PINMUX_DATA(PG0_DATA, PG0MD_000),
+        PINMUX_DATA(LCD_DATA0_MARK, PG0MD_001),
+        PINMUX_DATA(SD_D2_MARK, PG0MD_010),
+        PINMUX_DATA(PINT0_PG_MARK, PG0MD_011),
+        PINMUX_DATA(WDTOVF_MARK, PG0MD_100),
+
+        /* Port H */
+        PINMUX_DATA(PH7_DATA, PH7MD_0),
+        PINMUX_DATA(PHAN7_MARK, PH7MD_1),
+
+        PINMUX_DATA(PH6_DATA, PH6MD_0),
+        PINMUX_DATA(PHAN6_MARK, PH6MD_1),
+
+        PINMUX_DATA(PH5_DATA, PH5MD_0),
+        PINMUX_DATA(PHAN5_MARK, PH5MD_1),
+
+        PINMUX_DATA(PH4_DATA, PH4MD_0),
+        PINMUX_DATA(PHAN4_MARK, PH4MD_1),
+
+        PINMUX_DATA(PH3_DATA, PH3MD_0),
+        PINMUX_DATA(PHAN3_MARK, PH3MD_1),
+
+        PINMUX_DATA(PH2_DATA, PH2MD_0),
+        PINMUX_DATA(PHAN2_MARK, PH2MD_1),
+
+        PINMUX_DATA(PH1_DATA, PH1MD_0),
+        PINMUX_DATA(PHAN1_MARK, PH1MD_1),
+
+        PINMUX_DATA(PH0_DATA, PH0MD_0),
+        PINMUX_DATA(PHAN0_MARK, PH0MD_1),
+
+        /* Port I - not on device */
+
+        /* Port J */
+        PINMUX_DATA(PJ11_DATA, PJ11MD_00),
+        PINMUX_DATA(PWM2H_MARK, PJ11MD_01),
+        PINMUX_DATA(DACK1_MARK, PJ11MD_10),
+
+        PINMUX_DATA(PJ10_DATA, PJ10MD_00),
+        PINMUX_DATA(PWM2G_MARK, PJ10MD_01),
+        PINMUX_DATA(DREQ1_MARK, PJ10MD_10),
+
+        PINMUX_DATA(PJ9_DATA, PJ9MD_00),
+        PINMUX_DATA(PWM2F_MARK, PJ9MD_01),
+        PINMUX_DATA(TEND1_MARK, PJ9MD_10),
+
+        PINMUX_DATA(PJ8_DATA, PJ8MD_00),
+        PINMUX_DATA(PWM2E_MARK, PJ8MD_01),
+        PINMUX_DATA(RTS3_MARK, PJ8MD_10),
+
+        PINMUX_DATA(PJ7_DATA, PJ7MD_00),
+        PINMUX_DATA(TIOC1B_MARK, PJ7MD_01),
+        PINMUX_DATA(CTS3_MARK, PJ7MD_10),
+
+        PINMUX_DATA(PJ6_DATA, PJ6MD_00),
+        PINMUX_DATA(TIOC1A_MARK, PJ6MD_01),
+        PINMUX_DATA(SCK3_MARK, PJ6MD_10),
+
+        PINMUX_DATA(PJ5_DATA, PJ5MD_00),
+        PINMUX_DATA(IERXD_MARK, PJ5MD_01),
+        PINMUX_DATA(TXD3_MARK, PJ5MD_10),
+
+        PINMUX_DATA(PJ4_DATA, PJ4MD_00),
+        PINMUX_DATA(IETXD_MARK, PJ4MD_01),
+        PINMUX_DATA(RXD3_MARK, PJ4MD_10),
+
+        PINMUX_DATA(PJ3_DATA, PJ3MD_00),
+        PINMUX_DATA(CRX1_MARK, PJ3MD_01),
+        PINMUX_DATA(CRX0X1_MARK, PJ3MD_10),
+        PINMUX_DATA(IRQ1_PJ_MARK, PJ3MD_11),
+
+        PINMUX_DATA(PJ2_DATA, PJ2MD_000),
+        PINMUX_DATA(CTX1_MARK, PJ2MD_001),
+        PINMUX_DATA(CRX0CRX1_MARK, PJ2MD_010),
+        PINMUX_DATA(CS2_MARK, PJ2MD_011),
+        PINMUX_DATA(SCK0_MARK, PJ2MD_100),
+        PINMUX_DATA(LCD_M_DISP_MARK, PJ2MD_101),
+
+        PINMUX_DATA(PJ1_DATA, PJ1MD_000),
+        PINMUX_DATA(CRX0_MARK, PJ1MD_001),
+        PINMUX_DATA(IERXD_MARK, PJ1MD_010),
+        PINMUX_DATA(IRQ0_PJ_MARK, PJ1MD_011),
+        PINMUX_DATA(RXD0_MARK, PJ1MD_100),
+
+        PINMUX_DATA(PJ0_DATA, PJ0MD_000),
+        PINMUX_DATA(CTX0_MARK, PJ0MD_001),
+        PINMUX_DATA(IERXD_MARK, PJ0MD_010),
+        PINMUX_DATA(CS1_MARK, PJ0MD_011),
+        PINMUX_DATA(TXD0_MARK, PJ0MD_100),
+        PINMUX_DATA(A0_MARK, PJ0MD_101),
+
+        /* Port K */
+        PINMUX_DATA(PK11_DATA, PK11MD_00),
+        PINMUX_DATA(PWM2D_MARK, PK11MD_01),
+        PINMUX_DATA(SSITXD0_MARK, PK11MD_10),
+
+        PINMUX_DATA(PK10_DATA, PK10MD_00),
+        PINMUX_DATA(PWM2C_MARK, PK10MD_01),
+        PINMUX_DATA(SSIRXD0_MARK, PK10MD_10),
+
+        PINMUX_DATA(PK9_DATA, PK9MD_00),
+        PINMUX_DATA(PWM2B_MARK, PK9MD_01),
+        PINMUX_DATA(SSIWS0_MARK, PK9MD_10),
+
+        PINMUX_DATA(PK8_DATA, PK8MD_00),
+        PINMUX_DATA(PWM2A_MARK, PK8MD_01),
+        PINMUX_DATA(SSISCK0_MARK, PK8MD_10),
+
+        PINMUX_DATA(PK7_DATA, PK7MD_00),
+        PINMUX_DATA(PWM1H_MARK, PK7MD_01),
+        PINMUX_DATA(SD_CD_MARK, PK7MD_10),
+
+        PINMUX_DATA(PK6_DATA, PK6MD_00),
+        PINMUX_DATA(PWM1G_MARK, PK6MD_01),
+        PINMUX_DATA(SD_WP_MARK, PK6MD_10),
+
+        PINMUX_DATA(PK5_DATA, PK5MD_00),
+        PINMUX_DATA(PWM1F_MARK, PK5MD_01),
+        PINMUX_DATA(SD_D1_MARK, PK5MD_10),
+
+        PINMUX_DATA(PK4_DATA, PK4MD_00),
+        PINMUX_DATA(PWM1E_MARK, PK4MD_01),
+        PINMUX_DATA(SD_D0_MARK, PK4MD_10),
+
+        PINMUX_DATA(PK3_DATA, PK3MD_00),
+        PINMUX_DATA(PWM1D_MARK, PK3MD_01),
+        PINMUX_DATA(SD_CLK_MARK, PK3MD_10),
+
+        PINMUX_DATA(PK2_DATA, PK2MD_00),
+        PINMUX_DATA(PWM1C_MARK, PK2MD_01),
+        PINMUX_DATA(SD_CMD_MARK, PK2MD_10),
+
+        PINMUX_DATA(PK1_DATA, PK1MD_00),
+        PINMUX_DATA(PWM1B_MARK, PK1MD_01),
+        PINMUX_DATA(SD_D3_MARK, PK1MD_10),
+
+        PINMUX_DATA(PK0_DATA, PK0MD_00),
+        PINMUX_DATA(PWM1A_MARK, PK0MD_01),
+        PINMUX_DATA(SD_D2_MARK, PK0MD_10),
+};
+
+static struct pinmux_gpio pinmux_gpios[] = {
+
+        /* Port A */
+        PINMUX_GPIO(GPIO_PA3, PA3_DATA),
+        PINMUX_GPIO(GPIO_PA2, PA2_DATA),
+        PINMUX_GPIO(GPIO_PA1, PA1_DATA),
+        PINMUX_GPIO(GPIO_PA0, PA0_DATA),
+
+        /* Port B */
+        PINMUX_GPIO(GPIO_PB22, PB22_DATA),
+        PINMUX_GPIO(GPIO_PB21, PB21_DATA),
+        PINMUX_GPIO(GPIO_PB20, PB20_DATA),
+        PINMUX_GPIO(GPIO_PB19, PB19_DATA),
+        PINMUX_GPIO(GPIO_PB18, PB18_DATA),
+        PINMUX_GPIO(GPIO_PB17, PB17_DATA),
+        PINMUX_GPIO(GPIO_PB16, PB16_DATA),
+        PINMUX_GPIO(GPIO_PB15, PB15_DATA),
+        PINMUX_GPIO(GPIO_PB14, PB14_DATA),
+        PINMUX_GPIO(GPIO_PB13, PB13_DATA),
+        PINMUX_GPIO(GPIO_PB12, PB12_DATA),
+        PINMUX_GPIO(GPIO_PB11, PB11_DATA),
+        PINMUX_GPIO(GPIO_PB10, PB10_DATA),
+        PINMUX_GPIO(GPIO_PB9, PB9_DATA),
+        PINMUX_GPIO(GPIO_PB8, PB8_DATA),
+        PINMUX_GPIO(GPIO_PB7, PB7_DATA),
+        PINMUX_GPIO(GPIO_PB6, PB6_DATA),
+        PINMUX_GPIO(GPIO_PB5, PB5_DATA),
+        PINMUX_GPIO(GPIO_PB4, PB4_DATA),
+        PINMUX_GPIO(GPIO_PB3, PB3_DATA),
+        PINMUX_GPIO(GPIO_PB2, PB2_DATA),
+        PINMUX_GPIO(GPIO_PB1, PB1_DATA),
+
+        /* Port C */
+        PINMUX_GPIO(GPIO_PC10, PC10_DATA),
+        PINMUX_GPIO(GPIO_PC9, PC9_DATA),
+        PINMUX_GPIO(GPIO_PC8, PC8_DATA),
+        PINMUX_GPIO(GPIO_PC7, PC7_DATA),
+        PINMUX_GPIO(GPIO_PC6, PC6_DATA),
+        PINMUX_GPIO(GPIO_PC5, PC5_DATA),
+        PINMUX_GPIO(GPIO_PC4, PC4_DATA),
+        PINMUX_GPIO(GPIO_PC3, PC3_DATA),
+        PINMUX_GPIO(GPIO_PC2, PC2_DATA),
+        PINMUX_GPIO(GPIO_PC1, PC1_DATA),
+        PINMUX_GPIO(GPIO_PC0, PC0_DATA),
+
+        /* Port D */
+        PINMUX_GPIO(GPIO_PD15, PD15_DATA),
+        PINMUX_GPIO(GPIO_PD14, PD14_DATA),
+        PINMUX_GPIO(GPIO_PD13, PD13_DATA),
+        PINMUX_GPIO(GPIO_PD12, PD12_DATA),
+        PINMUX_GPIO(GPIO_PD11, PD11_DATA),
+        PINMUX_GPIO(GPIO_PD10, PD10_DATA),
+        PINMUX_GPIO(GPIO_PD9, PD9_DATA),
+        PINMUX_GPIO(GPIO_PD8, PD8_DATA),
+        PINMUX_GPIO(GPIO_PD7, PD7_DATA),
+        PINMUX_GPIO(GPIO_PD6, PD6_DATA),
+        PINMUX_GPIO(GPIO_PD5, PD5_DATA),
+        PINMUX_GPIO(GPIO_PD4, PD4_DATA),
+        PINMUX_GPIO(GPIO_PD3, PD3_DATA),
+        PINMUX_GPIO(GPIO_PD2, PD2_DATA),
+        PINMUX_GPIO(GPIO_PD1, PD1_DATA),
+        PINMUX_GPIO(GPIO_PD0, PD0_DATA),
+
+        /* Port E */
+        PINMUX_GPIO(GPIO_PE5, PE5_DATA),
+        PINMUX_GPIO(GPIO_PE4, PE4_DATA),
+        PINMUX_GPIO(GPIO_PE3, PE3_DATA),
+        PINMUX_GPIO(GPIO_PE2, PE2_DATA),
+        PINMUX_GPIO(GPIO_PE1, PE1_DATA),
+        PINMUX_GPIO(GPIO_PE0, PE0_DATA),
+
+        /* Port F */
+        PINMUX_GPIO(GPIO_PF12, PF12_DATA),
+        PINMUX_GPIO(GPIO_PF11, PF11_DATA),
+        PINMUX_GPIO(GPIO_PF10, PF10_DATA),
+        PINMUX_GPIO(GPIO_PF9, PF9_DATA),
+        PINMUX_GPIO(GPIO_PF8, PF8_DATA),
+        PINMUX_GPIO(GPIO_PF7, PF7_DATA),
+        PINMUX_GPIO(GPIO_PF6, PF6_DATA),
+        PINMUX_GPIO(GPIO_PF5, PF5_DATA),
+        PINMUX_GPIO(GPIO_PF4, PF4_DATA),
+        PINMUX_GPIO(GPIO_PF3, PF3_DATA),
+        PINMUX_GPIO(GPIO_PF2, PF2_DATA),
+        PINMUX_GPIO(GPIO_PF1, PF1_DATA),
+        PINMUX_GPIO(GPIO_PF0, PF0_DATA),
+
+        /* Port G */
+        PINMUX_GPIO(GPIO_PG24, PG24_DATA),
+        PINMUX_GPIO(GPIO_PG23, PG23_DATA),
+        PINMUX_GPIO(GPIO_PG22, PG22_DATA),
+        PINMUX_GPIO(GPIO_PG21, PG21_DATA),
+        PINMUX_GPIO(GPIO_PG20, PG20_DATA),
+        PINMUX_GPIO(GPIO_PG19, PG19_DATA),
+        PINMUX_GPIO(GPIO_PG18, PG18_DATA),
+        PINMUX_GPIO(GPIO_PG17, PG17_DATA),
+        PINMUX_GPIO(GPIO_PG16, PG16_DATA),
+        PINMUX_GPIO(GPIO_PG15, PG15_DATA),
+        PINMUX_GPIO(GPIO_PG14, PG14_DATA),
+        PINMUX_GPIO(GPIO_PG13, PG13_DATA),
+        PINMUX_GPIO(GPIO_PG12, PG12_DATA),
+        PINMUX_GPIO(GPIO_PG11, PG11_DATA),
+        PINMUX_GPIO(GPIO_PG10, PG10_DATA),
+        PINMUX_GPIO(GPIO_PG9, PG9_DATA),
+        PINMUX_GPIO(GPIO_PG8, PG8_DATA),
+        PINMUX_GPIO(GPIO_PG7, PG7_DATA),
+        PINMUX_GPIO(GPIO_PG6, PG6_DATA),
+        PINMUX_GPIO(GPIO_PG5, PG5_DATA),
+        PINMUX_GPIO(GPIO_PG4, PG4_DATA),
+        PINMUX_GPIO(GPIO_PG3, PG3_DATA),
+        PINMUX_GPIO(GPIO_PG2, PG2_DATA),
+        PINMUX_GPIO(GPIO_PG1, PG1_DATA),
+        PINMUX_GPIO(GPIO_PG0, PG0_DATA),
+
+        /* Port H - Port H does not have a Data Register */
+
+        /* Port I - not on device */
+
+        /* Port J */
+        PINMUX_GPIO(GPIO_PJ11, PJ11_DATA),
+        PINMUX_GPIO(GPIO_PJ10, PJ10_DATA),
+        PINMUX_GPIO(GPIO_PJ9, PJ9_DATA),
+        PINMUX_GPIO(GPIO_PJ8, PJ8_DATA),
+        PINMUX_GPIO(GPIO_PJ7, PJ7_DATA),
+        PINMUX_GPIO(GPIO_PJ6, PJ6_DATA),
+        PINMUX_GPIO(GPIO_PJ5, PJ5_DATA),
+        PINMUX_GPIO(GPIO_PJ4, PJ4_DATA),
+        PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
+        PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
+        PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
+        PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
+
+        /* Port K */
+        PINMUX_GPIO(GPIO_PK11, PK11_DATA),
+        PINMUX_GPIO(GPIO_PK10, PK10_DATA),
+        PINMUX_GPIO(GPIO_PK9, PK9_DATA),
+        PINMUX_GPIO(GPIO_PK8, PK8_DATA),
+        PINMUX_GPIO(GPIO_PK7, PK7_DATA),
+        PINMUX_GPIO(GPIO_PK6, PK6_DATA),
+        PINMUX_GPIO(GPIO_PK5, PK5_DATA),
+        PINMUX_GPIO(GPIO_PK4, PK4_DATA),
+        PINMUX_GPIO(GPIO_PK3, PK3_DATA),
+        PINMUX_GPIO(GPIO_PK2, PK2_DATA),
+        PINMUX_GPIO(GPIO_PK1, PK1_DATA),
+        PINMUX_GPIO(GPIO_PK0, PK0_DATA),
+
+        /* INTC */
+        PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK),
+
+        PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK),
+        PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK),
+
+        /* WDT */
+        PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK),
+
+        /* CAN */
+        PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK),
+        PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK),
+        PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK),
+        PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK),
+        PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0CRX1_MARK),
+
+        /* DMAC */
+        PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
+        PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
+        PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
+        PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
+
+        /* ADC */
+        PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK),
+
+        /* BSCh */
+        PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
+        PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
+        PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
+        PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
+        PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
+        PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
+        PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
+        PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
+        PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
+        PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
+        PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
+        PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
+        PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
+        PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
+        PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
+        PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
+        PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
+        PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
+        PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
+        PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
+        PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
+        PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
+        PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
+        PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
+        PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
+        PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
+
+        PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
+        PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
+        PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
+        PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
+        PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
+        PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
+        PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
+        PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
+        PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
+        PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
+        PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
+        PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
+        PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
+        PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
+        PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
+        PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
+
+        PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
+        PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
+        PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK),
+        PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK),
+        PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK),
+        PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
+        PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK),
+        PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK),
+        PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK),
+        PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
+        PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
+        PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK),
+        PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK),
+        PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK),
+        PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK),
+        PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK),
+        PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK),
+        PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK),
+        PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK),
+        PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK),
+        PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK),
+        PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK),
+
+        /* TMU */
+        PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK),
+        PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK),
+        PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK),
+
+        /* SCIF */
+        PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
+        PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK),
+        PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK),
+        PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK),
+        PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK),
+        PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK),
+
+        /* RSPI */
+        PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK),
+        PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK),
+        PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK),
+        PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK),
+        PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK),
+        PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK),
+        PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK),
+        PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK),
+        PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK),
+
+        /* IIC3 */
+        PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
+        PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
+        PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
+
+        /* SSI */
+        PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK),
+        PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK),
+        PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK),
+        PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK),
+        PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK),
+
+        /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
+        PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK),
+
+        /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
+        PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK),
+        PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK),
+
+        /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
+        PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK),
+        PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK),
+
+        /* VDC3 */
+        PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK),
+
+        PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK),
+
+        PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK),
+
+        PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK),
+        PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK),
+
+        PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PA3_IN, PA3_OUT,
+                PA2_IN, PA2_OUT,
+                PA1_IN, PA1_OUT,
+                PA0_IN, PA0_OUT }
+        },
+
+        { PINMUX_CFG_REG("PBCR5", 0xfffe3824, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PB22MD_00, PB22MD_01, PB22MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PB21MD_0, PB21MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB20MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+
+        },
+        { PINMUX_CFG_REG("PBCR4", 0xfffe3826, 16, 4) {
+                0, PB19MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB18MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB17MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB16MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCR3", 0xfffe3828, 16, 4) {
+                0, PB15MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB14MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB13MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB12MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCR2", 0xfffe382a, 16, 4) {
+                0, PB11MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB10MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB9MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB8MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCR1", 0xfffe382c, 16, 4) {
+                0, PB7MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB6MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB5MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB4MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PBCR0", 0xfffe382e, 16, 4) {
+                0, PB3MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB2MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB1MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PBIOR1", 0xfffe3830, 16, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0,
+                PB22_IN, PB22_OUT,
+                PB21_IN, PB21_OUT,
+                PB20_IN, PB20_OUT,
+                PB19_IN, PB19_OUT,
+                PB18_IN, PB18_OUT,
+                PB17_IN, PB17_OUT,
+                PB16_IN, PB16_OUT }
+        },
+
+        { PINMUX_CFG_REG("PBIOR0", 0xfffe3832, 16, 1) {
+                PB15_IN, PB15_OUT,
+                PB14_IN, PB14_OUT,
+                PB13_IN, PB13_OUT,
+                PB12_IN, PB12_OUT,
+                PB11_IN, PB11_OUT,
+                PB10_IN, PB10_OUT,
+                PB9_IN, PB9_OUT,
+                PB8_IN, PB8_OUT,
+                PB7_IN, PB7_OUT,
+                PB6_IN, PB6_OUT,
+                PB5_IN, PB5_OUT,
+                PB4_IN, PB4_OUT,
+                PB3_IN, PB3_OUT,
+                PB2_IN, PB2_OUT,
+                PB1_IN, PB1_OUT,
+                0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PCCR2", 0xfffe384a, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC10MD_0, PC10MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC9MD_0, PC9MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC8MD_00, PC8MD_01, PC8MD_10, PC8MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PCCR1", 0xfffe384c, 16, 4) {
+                PC7MD_00, PC7MD_01, PC7MD_10, PC7MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC6MD_00, PC6MD_01, PC6MD_10, PC6MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC5MD_00, PC5MD_01, PC5MD_10, PC5MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC4MD_0, PC4MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PCCR0", 0xfffe384e, 16, 4) {
+                PC3MD_0, PC3MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC2MD_0, PC2MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC1MD_0, PC1MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PC0MD_0, PC0MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PCIOR0", 0xfffe3852, 16, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+                PC10_IN, PC10_OUT,
+                PC9_IN, PC9_OUT,
+                PC8_IN, PC8_OUT,
+                PC7_IN, PC7_OUT,
+                PC6_IN, PC6_OUT,
+                PC5_IN, PC5_OUT,
+                PC4_IN, PC4_OUT,
+                PC3_IN, PC3_OUT,
+                PC2_IN, PC2_OUT,
+                PC1_IN, PC1_OUT,
+                PC0_IN, PC0_OUT
+         }
+        },
+
+        { PINMUX_CFG_REG("PDCR3", 0xfffe3868, 16, 4) {
+                0, PD15MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD14MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD13MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD12MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PDCR2", 0xfffe386a, 16, 4) {
+                0, PD11MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD10MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD9MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD8MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PDCR1", 0xfffe386c, 16, 4) {
+                0, PD7MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD6MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD5MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD4MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PDCR0", 0xfffe386e, 16, 4) {
+                0, PD3MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD2MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD1MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PD0MD_01, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PDIOR0", 0xfffe3872, 16, 1) {
+                PD15_IN, PD15_OUT,
+                PD14_IN, PD14_OUT,
+                PD13_IN, PD13_OUT,
+                PD12_IN, PD12_OUT,
+                PD11_IN, PD11_OUT,
+                PD10_IN, PD10_OUT,
+                PD9_IN, PD9_OUT,
+                PD8_IN, PD8_OUT,
+                PD7_IN, PD7_OUT,
+                PD6_IN, PD6_OUT,
+                PD5_IN, PD5_OUT,
+                PD4_IN, PD4_OUT,
+                PD3_IN, PD3_OUT,
+                PD2_IN, PD2_OUT,
+                PD1_IN, PD1_OUT,
+                PD0_IN, PD0_OUT }
+        },
+
+        { PINMUX_CFG_REG("PECR1", 0xfffe388c, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PE5MD_00, PE5MD_01, 0, PE5MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PE4MD_00, PE4MD_01, 0, PE4MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PECR0", 0xfffe388e, 16, 4) {
+                PE3MD_00, PE3MD_01, 0, PE3MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PE2MD_00, PE2MD_01, 0, PE2MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PE1MD_000, PE1MD_001, PE1MD_010, PE1MD_011,
+                PE1MD_100, PE1MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PE0MD_00, PE0MD_01, PE0MD_10, PE0MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PEIOR0", 0xfffe3892, 16, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0,
+                PE5_IN, PE5_OUT,
+                PE4_IN, PE4_OUT,
+                PE3_IN, PE3_OUT,
+                PE2_IN, PE2_OUT,
+                PE1_IN, PE1_OUT,
+                PE0_IN, PE0_OUT }
+        },
+
+        { PINMUX_CFG_REG("PFCR3", 0xfffe38a8, 16, 4) {
+                PF12MD_000, PF12MD_001, 0, PF12MD_011,
+                PF12MD_100, PF12MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PFCR2", 0xfffe38aa, 16, 4) {
+                PF11MD_000, PF11MD_001, PF11MD_010, PF11MD_011,
+                PF11MD_100, PF11MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF10MD_000, PF10MD_001, PF10MD_010, PF10MD_011,
+                PF10MD_100, PF10MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF9MD_000, PF9MD_001, PF9MD_010, PF9MD_011,
+                PF9MD_100, PF9MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF8MD_00, PF8MD_01, PF8MD_10, PF8MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PFCR1", 0xfffe38ac, 16, 4) {
+                PF7MD_000, PF7MD_001, PF7MD_010, PF7MD_011,
+                PF7MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF6MD_000, PF6MD_001, PF6MD_010, PF6MD_011,
+                PF6MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF5MD_000, PF5MD_001, PF5MD_010, PF5MD_011,
+                PF5MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF4MD_000, PF4MD_001, PF4MD_010, PF4MD_011,
+                PF4MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PFCR0", 0xfffe38ae, 16, 4) {
+                PF3MD_000, PF3MD_001, PF3MD_010, PF3MD_011,
+                PF3MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF2MD_000, PF2MD_001, PF2MD_010, PF2MD_011,
+                PF2MD_100, PF2MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PF1MD_000, PF1MD_001, PF1MD_010, PF1MD_011,
+                PF1MD_100, PF1MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0
+         }
+        },
+
+        { PINMUX_CFG_REG("PFIOR0", 0xfffe38b2, 16, 1) {
+                0, 0, 0, 0, 0, 0,
+                PF12_IN, PF12_OUT,
+                PF11_IN, PF11_OUT,
+                PF10_IN, PF10_OUT,
+                PF9_IN, PF9_OUT,
+                PF8_IN, PF8_OUT,
+                PF7_IN, PF7_OUT,
+                PF6_IN, PF6_OUT,
+                PF5_IN, PF5_OUT,
+                PF4_IN, PF4_OUT,
+                PF3_IN, PF3_OUT,
+                PF2_IN, PF2_OUT,
+                PF1_IN, PF1_OUT,
+                PF0_IN, PF0_OUT }
+        },
+
+        { PINMUX_CFG_REG("PGCR7", 0xfffe38c0, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG0MD_000, PG0MD_001, PG0MD_010, PG0MD_011,
+                PG0MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PGCR6", 0xfffe38c2, 16, 4) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG24MD_00, PG24MD_01, PG24MD_10, PG24MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PGCR5", 0xfffe38c4, 16, 4) {
+                PG23MD_00, PG23MD_01, PG23MD_10, PG23MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG22MD_00, PG22MD_01, PG22MD_10, PG22MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG21MD_00, PG21MD_01, PG21MD_10, PG21MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG20MD_000, PG20MD_001, PG20MD_010, PG20MD_011,
+                PG20MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PGCR4", 0xfffe38c6, 16, 4) {
+                PG19MD_000, PG19MD_001, PG19MD_010, PG19MD_011,
+                PG19MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG18MD_000, PG18MD_001, PG18MD_010, PG18MD_011,
+                PG18MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG17MD_000, PG17MD_001, PG17MD_010, PG17MD_011,
+                PG17MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG16MD_000, PG16MD_001, PG16MD_010, PG16MD_011,
+                PG16MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PGCR3", 0xfffe38c8, 16, 4) {
+                PG15MD_000, PG15MD_001, PG15MD_010, PG15MD_011,
+                PG15MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG14MD_000, PG14MD_001, PG14MD_010, 0,
+                PG14MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG13MD_000, PG13MD_001, PG13MD_010, 0,
+                PG13MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG12MD_000, PG12MD_001, PG12MD_010, 0,
+                PG12MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PGCR2", 0xfffe38ca, 16, 4) {
+                PG11MD_000, PG11MD_001, PG11MD_010, PG11MD_011,
+                PG11MD_100, PG11MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG10MD_000, PG10MD_001, PG10MD_010, PG10MD_011,
+                PG10MD_100, PG10MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG9MD_000, PG9MD_001, PG9MD_010, PG9MD_011,
+                PG9MD_100, PG9MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG8MD_000, PG8MD_001, PG8MD_010, PG8MD_011,
+                PG8MD_100, PG8MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PGCR1", 0xfffe38cc, 16, 4) {
+                PG7MD_00, PG7MD_01, PG7MD_10, PG7MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG6MD_00, PG6MD_01, PG6MD_10, PG6MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG5MD_00, PG5MD_01, PG5MD_10, PG5MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG4MD_00, PG4MD_01, PG4MD_10, PG4MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PGCR0", 0xfffe38ce, 16, 4) {
+                PG3MD_00, PG3MD_01, PG3MD_10, PG3MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG2MD_00, PG2MD_01, PG2MD_10, PG2MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PG1MD_00, PG1MD_01, PG1MD_10, PG1MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PGIOR1", 0xfffe38d0, 16, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0,
+                PG24_IN, PG24_OUT,
+                PG23_IN, PG23_OUT,
+                PG22_IN, PG22_OUT,
+                PG21_IN, PG21_OUT,
+                PG20_IN, PG20_OUT,
+                PG19_IN, PG19_OUT,
+                PG18_IN, PG18_OUT,
+                PG17_IN, PG17_OUT,
+                PG16_IN, PG16_OUT }
+        },
+
+        { PINMUX_CFG_REG("PGIOR0", 0xfffe38d2, 16, 1) {
+                PG15_IN, PG15_OUT,
+                PG14_IN, PG14_OUT,
+                PG13_IN, PG13_OUT,
+                PG12_IN, PG12_OUT,
+                PG11_IN, PG11_OUT,
+                PG10_IN, PG10_OUT,
+                PG9_IN, PG9_OUT,
+                PG8_IN, PG8_OUT,
+                PG7_IN, PG7_OUT,
+                PG6_IN, PG6_OUT,
+                PG5_IN, PG5_OUT,
+                PG4_IN, PG4_OUT,
+                PG3_IN, PG3_OUT,
+                PG2_IN, PG2_OUT,
+                PG1_IN, PG1_OUT,
+                PG0_IN, PG0_OUT
+         }
+        },
+
+        { PINMUX_CFG_REG("PHCR1", 0xfffe38ec, 16, 4) {
+                PH7MD_0, PH7MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PH6MD_0, PH6MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PH5MD_0, PH5MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PH4MD_0, PH4MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PHCR0", 0xfffe38ee, 16, 4) {
+                PH3MD_0, PH3MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PH2MD_0, PH2MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PH1MD_0, PH1MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PH0MD_0, PH0MD_1, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PJCR2", 0xfffe390a, 16, 4) {
+                PJ11MD_00, PJ11MD_01, PJ11MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ10MD_00, PJ10MD_01, PJ10MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ9MD_00, PJ9MD_01, PJ9MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ8MD_00, PJ8MD_01, PJ8MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PJCR1", 0xfffe390c, 16, 4) {
+                PJ7MD_00, PJ7MD_01, PJ7MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ6MD_00, PJ6MD_01, PJ6MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ5MD_00, PJ5MD_01, PJ5MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ4MD_00, PJ4MD_01, PJ4MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PJCR0", 0xfffe390e, 16, 4) {
+                PJ3MD_00, PJ3MD_01, PJ3MD_10, PJ3MD_11, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ2MD_000, PJ2MD_001, PJ2MD_010, PJ2MD_011,
+                PJ2MD_100, PJ2MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ1MD_000, PJ1MD_001, PJ1MD_010, PJ1MD_011,
+                PJ1MD_100, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ0MD_000, PJ0MD_001, PJ0MD_010, PJ0MD_011,
+                PJ0MD_100, PJ0MD_101, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG("PJIOR0", 0xfffe3912, 16, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ11_IN, PJ11_OUT,
+                PJ10_IN, PJ10_OUT,
+                PJ9_IN, PJ9_OUT,
+                PJ8_IN, PJ8_OUT,
+                PJ7_IN, PJ7_OUT,
+                PJ6_IN, PJ6_OUT,
+                PJ5_IN, PJ5_OUT,
+                PJ4_IN, PJ4_OUT,
+                PJ3_IN, PJ3_OUT,
+                PJ2_IN, PJ2_OUT,
+                PJ1_IN, PJ1_OUT,
+                PJ0_IN, PJ0_OUT }
+        },
+
+        { PINMUX_CFG_REG("PKCR2", 0xfffe392a, 16, 4) {
+                PK11MD_00, PK11MD_01, PK11MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK10MD_00, PK10MD_01, PK10MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK9MD_00, PK9MD_01, PK9MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK8MD_00, PK8MD_01, PK8MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PKCR1", 0xfffe392c, 16, 4) {
+                PK7MD_00, PK7MD_01, PK7MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK6MD_00, PK6MD_01, PK6MD_10, 0,  0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK5MD_00, PK5MD_01, PK5MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK4MD_00, PK4MD_01, PK4MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+        { PINMUX_CFG_REG("PKCR0", 0xfffe392e, 16, 4) {
+                PK3MD_00, PK3MD_01, PK3MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK2MD_00, PK2MD_01, PK2MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK1MD_00, PK1MD_01, PK1MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PK0MD_00, PK0MD_01, PK0MD_10, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0 }
+        },
+
+        { PINMUX_CFG_REG("PKIOR0", 0xfffe3932, 16, 1) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                PJ11_IN, PJ11_OUT,
+                PJ10_IN, PJ10_OUT,
+                PJ9_IN, PJ9_OUT,
+                PJ8_IN, PJ8_OUT,
+                PJ7_IN, PJ7_OUT,
+                PJ6_IN, PJ6_OUT,
+                PJ5_IN, PJ5_OUT,
+                PJ4_IN, PJ4_OUT,
+                PJ3_IN, PJ3_OUT,
+                PJ2_IN, PJ2_OUT,
+                PJ1_IN, PJ1_OUT,
+                PJ0_IN, PJ0_OUT }
+        },
+        {}
+};
+
+static struct pinmux_data_reg pinmux_data_regs[] = {
+        { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
+                0, 0, 0, 0, 0, 0, 0, PA3_DATA,
+                0, 0, 0, 0, 0, 0, 0, PA2_DATA }
+        },
+
+        { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
+                0, 0, 0, 0, 0, 0, 0, PA1_DATA,
+                0, 0, 0, 0, 0, 0, 0, PA0_DATA }
+        },
+
+        { PINMUX_DATA_REG("PBDR1", 0xfffe3834, 16) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, PB22_DATA, PB21_DATA, PB20_DATA,
+                PB19_DATA, PB18_DATA, PB17_DATA, PB16_DATA }
+        },
+
+        { PINMUX_DATA_REG("PBDR0", 0xfffe3836, 16) {
+                PB15_DATA, PB14_DATA, PB13_DATA, PB12_DATA,
+                PB11_DATA, PB10_DATA, PB9_DATA, PB8_DATA,
+                PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
+                PB3_DATA, PB2_DATA, PB1_DATA, 0 }
+        },
+
+        { PINMUX_DATA_REG("PCDR0", 0xfffe3856, 16) {
+                0, 0, 0, 0,
+                0, PC10_DATA, PC9_DATA, PC8_DATA,
+                PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
+                PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA }
+        },
+
+        { PINMUX_DATA_REG("PDDR0", 0xfffe3876, 16) {
+                PD15_DATA, PD14_DATA, PD13_DATA, PD12_DATA,
+                PD11_DATA, PD10_DATA, PD9_DATA, PD8_DATA,
+                PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
+                PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA }
+        },
+
+        { PINMUX_DATA_REG("PEDR0", 0xfffe3896, 16) {
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, PE5_DATA, PE4_DATA,
+                PE3_DATA, PE2_DATA, PE1_DATA, PE0_DATA }
+        },
+
+        { PINMUX_DATA_REG("PFDR0", 0xfffe38b6, 16) {
+                0, 0, 0, PF12_DATA,
+                PF11_DATA, PF10_DATA, PF9_DATA, PF8_DATA,
+                PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
+                PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA }
+        },
+
+        { PINMUX_DATA_REG("PGDR1", 0xfffe38d4, 16) {
+                0, 0, 0, 0, 0, 0, 0, PG24_DATA,
+                PG23_DATA, PG22_DATA, PG21_DATA, PG20_DATA,
+                PG19_DATA, PG18_DATA, PG17_DATA, PG16_DATA }
+        },
+
+        { PINMUX_DATA_REG("PGDR0", 0xfffe38d6, 16) {
+                PG15_DATA, PG14_DATA, PG13_DATA, PG12_DATA,
+                PG11_DATA, PG10_DATA, PG9_DATA, PG8_DATA,
+                PG7_DATA, PG6_DATA, PG5_DATA, PG4_DATA,
+                PG3_DATA, PG2_DATA, PG1_DATA, PG0_DATA }
+        },
+        { PINMUX_DATA_REG("PJDR0", 0xfffe3916, 16) {
+                0, 0, 0, PJ12_DATA,
+                PJ11_DATA, PJ10_DATA, PJ9_DATA, PJ8_DATA,
+                PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
+                PJ3_DATA, PJ2_DATA, PJ1_DATA, PJ0_DATA }
+        },
+        { PINMUX_DATA_REG("PKDR0", 0xfffe3936, 16) {
+                0, 0, 0, PK12_DATA,
+                PK11_DATA, PK10_DATA, PK9_DATA, PK8_DATA,
+                PK7_DATA, PK6_DATA, PK5_DATA, PK4_DATA,
+                PK3_DATA, PK2_DATA, PK1_DATA, PK0_DATA }
+        },
+        { }
+};
+
+static struct pinmux_info sh7264_pinmux_info = {
+        .name = "sh7264_pfc",
+        .reserved_id = PINMUX_RESERVED,
+        .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
+        .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
+        .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
+        .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .first_gpio = GPIO_PA3,
+        .last_gpio = GPIO_FN_LCD_M_DISP,
+
+        .gpios = pinmux_gpios,
+        .cfg_regs = pinmux_config_regs,
+        .data_regs = pinmux_data_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
+
+static int __init plat_pinmux_setup(void)
+{
+        return register_pinmux(&sh7264_pinmux_info);
+}
+arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/probe.c b/arch/sh/kernel/cpu/sh2a/probe.c
index 48e97a2a0c8d..414b2581c606 100644
--- a/arch/sh/kernel/cpu/sh2a/probe.c
+++ b/arch/sh/kernel/cpu/sh2a/probe.c
@@ -29,6 +29,9 @@ void __cpuinit cpu_probe(void)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7263)
         boot_cpu_data.type                      = CPU_SH7263;
         boot_cpu_data.flags                     |= CPU_HAS_FPU;
+#elif defined(CONFIG_CPU_SUBTYPE_SH7264)
+        boot_cpu_data.type                      = CPU_SH7264;
+        boot_cpu_data.flags                     |= CPU_HAS_FPU;
 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
         boot_cpu_data.type                      = CPU_SH7206;
         boot_cpu_data.flags                     |= CPU_HAS_DSP;
diff --git a/arch/sh/kernel/cpu/sh2a/setup-sh7264.c b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
new file mode 100644
index 000000000000..ce5c1b5aebfa
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh2a/setup-sh7264.c
@@ -0,0 +1,606 @@
+/*
+ * SH7264 Setup
+ *
+ * Copyright (C) 2012  Renesas Electronics Europe Ltd
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+#include <linux/usb/r8a66597.h>
+#include <linux/sh_timer.h>
+#include <linux/io.h>
+
+enum {
+        UNUSED = 0,
+
+        /* interrupt sources */
+        IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+        PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
+
+        DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
+        DMAC8, DMAC9, DMAC10, DMAC11, DMAC12, DMAC13, DMAC14, DMAC15,
+        USB, VDC3, CMT0, CMT1, BSC, WDT,
+        MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
+        MTU3_ABCD, MTU3_TCI3V, MTU4_ABCD, MTU4_TCI4V,
+        PWMT1, PWMT2, ADC_ADI,
+        SSIF0, SSII1, SSII2, SSII3,
+        RSPDIF,
+        IIC30, IIC31, IIC32, IIC33,
+        SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI,
+        SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI,
+        SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI,
+        SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI,
+        SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI,
+        SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI,
+        SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI,
+        SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI,
+        SIO_FIFO, RSPIC0, RSPIC1,
+        RCAN0, RCAN1, IEBC, CD_ROMD,
+        NFMC, SDHI, RTC,
+        SRCC0, SRCC1, DCOMU, OFFI, IFEI,
+
+        /* interrupt groups */
+        PINT, SCIF0, SCIF1, SCIF2, SCIF3, SCIF4, SCIF5, SCIF6, SCIF7,
+};
+
+static struct intc_vect vectors[] __initdata = {
+        INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
+        INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
+        INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
+        INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
+
+        INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
+        INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
+        INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
+        INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
+
+        INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
+        INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
+        INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
+        INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
+        INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
+        INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
+        INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
+        INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
+        INTC_IRQ(DMAC8, 140), INTC_IRQ(DMAC8, 141),
+        INTC_IRQ(DMAC9, 144), INTC_IRQ(DMAC9, 145),
+        INTC_IRQ(DMAC10, 148), INTC_IRQ(DMAC10, 149),
+        INTC_IRQ(DMAC11, 152), INTC_IRQ(DMAC11, 153),
+        INTC_IRQ(DMAC12, 156), INTC_IRQ(DMAC12, 157),
+        INTC_IRQ(DMAC13, 160), INTC_IRQ(DMAC13, 161),
+        INTC_IRQ(DMAC14, 164), INTC_IRQ(DMAC14, 165),
+        INTC_IRQ(DMAC15, 168), INTC_IRQ(DMAC15, 169),
+
+        INTC_IRQ(USB, 170),
+        INTC_IRQ(VDC3, 171), INTC_IRQ(VDC3, 172),
+        INTC_IRQ(VDC3, 173), INTC_IRQ(VDC3, 174),
+        INTC_IRQ(CMT0, 175), INTC_IRQ(CMT1, 176),
+        INTC_IRQ(BSC, 177), INTC_IRQ(WDT, 178),
+
+        INTC_IRQ(MTU0_ABCD, 179), INTC_IRQ(MTU0_ABCD, 180),
+        INTC_IRQ(MTU0_ABCD, 181), INTC_IRQ(MTU0_ABCD, 182),
+        INTC_IRQ(MTU0_VEF, 183),
+        INTC_IRQ(MTU0_VEF, 184), INTC_IRQ(MTU0_VEF, 185),
+        INTC_IRQ(MTU1_AB, 186), INTC_IRQ(MTU1_AB, 187),
+        INTC_IRQ(MTU1_VU, 188), INTC_IRQ(MTU1_VU, 189),
+        INTC_IRQ(MTU2_AB, 190), INTC_IRQ(MTU2_AB, 191),
+        INTC_IRQ(MTU2_VU, 192), INTC_IRQ(MTU2_VU, 193),
+        INTC_IRQ(MTU3_ABCD, 194), INTC_IRQ(MTU3_ABCD, 195),
+        INTC_IRQ(MTU3_ABCD, 196), INTC_IRQ(MTU3_ABCD, 197),
+        INTC_IRQ(MTU3_TCI3V, 198),
+        INTC_IRQ(MTU4_ABCD, 199), INTC_IRQ(MTU4_ABCD, 200),
+        INTC_IRQ(MTU4_ABCD, 201), INTC_IRQ(MTU4_ABCD, 202),
+        INTC_IRQ(MTU4_TCI4V, 203),
+
+        INTC_IRQ(PWMT1, 204), INTC_IRQ(PWMT2, 205),
+
+        INTC_IRQ(ADC_ADI, 206),
+
+        INTC_IRQ(SSIF0, 207), INTC_IRQ(SSIF0, 208),
+        INTC_IRQ(SSIF0, 209),
+        INTC_IRQ(SSII1, 210), INTC_IRQ(SSII1, 211),
+        INTC_IRQ(SSII2, 212), INTC_IRQ(SSII2, 213),
+        INTC_IRQ(SSII3, 214), INTC_IRQ(SSII3, 215),
+
+        INTC_IRQ(RSPDIF, 216),
+
+        INTC_IRQ(IIC30, 217), INTC_IRQ(IIC30, 218),
+        INTC_IRQ(IIC30, 219), INTC_IRQ(IIC30, 220),
+        INTC_IRQ(IIC30, 221),
+        INTC_IRQ(IIC31, 222), INTC_IRQ(IIC31, 223),
+        INTC_IRQ(IIC31, 224), INTC_IRQ(IIC31, 225),
+        INTC_IRQ(IIC31, 226),
+        INTC_IRQ(IIC32, 227), INTC_IRQ(IIC32, 228),
+        INTC_IRQ(IIC32, 229), INTC_IRQ(IIC32, 230),
+        INTC_IRQ(IIC32, 231),
+
+        INTC_IRQ(SCIF0_BRI, 232), INTC_IRQ(SCIF0_ERI, 233),
+        INTC_IRQ(SCIF0_RXI, 234), INTC_IRQ(SCIF0_TXI, 235),
+        INTC_IRQ(SCIF1_BRI, 236), INTC_IRQ(SCIF1_ERI, 237),
+        INTC_IRQ(SCIF1_RXI, 238), INTC_IRQ(SCIF1_TXI, 239),
+        INTC_IRQ(SCIF2_BRI, 240), INTC_IRQ(SCIF2_ERI, 241),
+        INTC_IRQ(SCIF2_RXI, 242), INTC_IRQ(SCIF2_TXI, 243),
+        INTC_IRQ(SCIF3_BRI, 244), INTC_IRQ(SCIF3_ERI, 245),
+        INTC_IRQ(SCIF3_RXI, 246), INTC_IRQ(SCIF3_TXI, 247),
+        INTC_IRQ(SCIF4_BRI, 248), INTC_IRQ(SCIF4_ERI, 249),
+        INTC_IRQ(SCIF4_RXI, 250), INTC_IRQ(SCIF4_TXI, 251),
+        INTC_IRQ(SCIF5_BRI, 252), INTC_IRQ(SCIF5_ERI, 253),
+        INTC_IRQ(SCIF5_RXI, 254), INTC_IRQ(SCIF5_TXI, 255),
+        INTC_IRQ(SCIF6_BRI, 256), INTC_IRQ(SCIF6_ERI, 257),
+        INTC_IRQ(SCIF6_RXI, 258), INTC_IRQ(SCIF6_TXI, 259),
+        INTC_IRQ(SCIF7_BRI, 260), INTC_IRQ(SCIF7_ERI, 261),
+        INTC_IRQ(SCIF7_RXI, 262), INTC_IRQ(SCIF7_TXI, 263),
+
+        INTC_IRQ(SIO_FIFO, 264),
+
+        INTC_IRQ(RSPIC0, 265), INTC_IRQ(RSPIC0, 266),
+        INTC_IRQ(RSPIC0, 267),
+        INTC_IRQ(RSPIC1, 268), INTC_IRQ(RSPIC1, 269),
+        INTC_IRQ(RSPIC1, 270),
+
+        INTC_IRQ(RCAN0, 271), INTC_IRQ(RCAN0, 272),
+        INTC_IRQ(RCAN0, 273), INTC_IRQ(RCAN0, 274),
+        INTC_IRQ(RCAN0, 275),
+        INTC_IRQ(RCAN1, 276), INTC_IRQ(RCAN1, 277),
+        INTC_IRQ(RCAN1, 278), INTC_IRQ(RCAN1, 279),
+        INTC_IRQ(RCAN1, 280),
+
+        INTC_IRQ(IEBC, 281),
+
+        INTC_IRQ(CD_ROMD, 282), INTC_IRQ(CD_ROMD, 283),
+        INTC_IRQ(CD_ROMD, 284), INTC_IRQ(CD_ROMD, 285),
+        INTC_IRQ(CD_ROMD, 286), INTC_IRQ(CD_ROMD, 287),
+
+        INTC_IRQ(NFMC, 288), INTC_IRQ(NFMC, 289),
+        INTC_IRQ(NFMC, 290), INTC_IRQ(NFMC, 291),
+
+        INTC_IRQ(SDHI, 292), INTC_IRQ(SDHI, 293),
+        INTC_IRQ(SDHI, 294),
+
+        INTC_IRQ(RTC, 296), INTC_IRQ(RTC, 297),
+        INTC_IRQ(RTC, 298),
+
+        INTC_IRQ(SRCC0, 299), INTC_IRQ(SRCC0, 300),
+        INTC_IRQ(SRCC0, 301), INTC_IRQ(SRCC0, 302),
+        INTC_IRQ(SRCC0, 303),
+        INTC_IRQ(SRCC1, 304), INTC_IRQ(SRCC1, 305),
+        INTC_IRQ(SRCC1, 306), INTC_IRQ(SRCC1, 307),
+        INTC_IRQ(SRCC1, 308),
+
+        INTC_IRQ(DCOMU, 310), INTC_IRQ(DCOMU, 311),
+        INTC_IRQ(DCOMU, 312),
+};
+
+static struct intc_group groups[] __initdata = {
+        INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
+                   PINT4, PINT5, PINT6, PINT7),
+        INTC_GROUP(SCIF0, SCIF0_BRI, SCIF0_ERI, SCIF0_RXI, SCIF0_TXI),
+        INTC_GROUP(SCIF1, SCIF1_BRI, SCIF1_ERI, SCIF1_RXI, SCIF1_TXI),
+        INTC_GROUP(SCIF2, SCIF2_BRI, SCIF2_ERI, SCIF2_RXI, SCIF2_TXI),
+        INTC_GROUP(SCIF3, SCIF3_BRI, SCIF3_ERI, SCIF3_RXI, SCIF3_TXI),
+        INTC_GROUP(SCIF4, SCIF4_BRI, SCIF4_ERI, SCIF4_RXI, SCIF4_TXI),
+        INTC_GROUP(SCIF5, SCIF5_BRI, SCIF5_ERI, SCIF5_RXI, SCIF5_TXI),
+        INTC_GROUP(SCIF6, SCIF6_BRI, SCIF6_ERI, SCIF6_RXI, SCIF6_TXI),
+        INTC_GROUP(SCIF7, SCIF7_BRI, SCIF7_ERI, SCIF7_RXI, SCIF7_TXI),
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+        { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
+        { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
+        { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
+        { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0,  DMAC1,  DMAC2,  DMAC3 } },
+        { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4,  DMAC5,  DMAC6,  DMAC7 } },
+        { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { DMAC8,  DMAC9,
+                                              DMAC10, DMAC11 } },
+        { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { DMAC12, DMAC13,
+                                              DMAC14, DMAC15 } },
+        { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { USB, VDC3, CMT0, CMT1 } },
+        { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
+        { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { MTU1_AB, MTU1_VU,
+                                              MTU2_AB, MTU2_VU } },
+        { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { MTU3_ABCD, MTU3_TCI3V,
+                                              MTU4_ABCD, MTU4_TCI4V } },
+        { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { PWMT1, PWMT2, ADC_ADI, 0 } },
+        { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSIF0, SSII1, SSII2, SSII3 } },
+        { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { RSPDIF, IIC30, IIC31, IIC32 } },
+        { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { SCIF0, SCIF1, SCIF2, SCIF3 } },
+        { 0xfffe0c18, 0, 16, 4, /* IPR18 */ { SCIF4, SCIF5, SCIF6, SCIF7 } },
+        { 0xfffe0c1a, 0, 16, 4, /* IPR19 */ { SIO_FIFO, 0, RSPIC0, RSPIC1, } },
+        { 0xfffe0c1c, 0, 16, 4, /* IPR20 */ { RCAN0, RCAN1, IEBC, CD_ROMD } },
+        { 0xfffe0c1e, 0, 16, 4, /* IPR21 */ { NFMC, SDHI, RTC, 0 } },
+        { 0xfffe0c20, 0, 16, 4, /* IPR22 */ { SRCC0, SRCC1, 0, DCOMU } },
+};
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+        { 0xfffe0808, 0, 16, /* PINTER */
+          { 0, 0, 0, 0, 0, 0, 0, 0,
+            PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7264", vectors, groups,
+                         mask_registers, prio_registers, NULL);
+
+static struct plat_sci_port scif0_platform_data = {
+        .mapbase        = 0xfffe8000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 233, 234, 235, 232 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif0_device = {
+        .name           = "sh-sci",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &scif0_platform_data,
+        },
+};
+
+static struct plat_sci_port scif1_platform_data = {
+        .mapbase        = 0xfffe8800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 237, 238, 239, 236 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif1_device = {
+        .name           = "sh-sci",
+        .id             = 1,
+        .dev            = {
+                .platform_data  = &scif1_platform_data,
+        },
+};
+
+static struct plat_sci_port scif2_platform_data = {
+        .mapbase        = 0xfffe9000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 241, 242, 243, 240 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif2_device = {
+        .name           = "sh-sci",
+        .id             = 2,
+        .dev            = {
+                .platform_data  = &scif2_platform_data,
+        },
+};
+
+static struct plat_sci_port scif3_platform_data = {
+        .mapbase        = 0xfffe9800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 245, 246, 247, 244 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif3_device = {
+        .name           = "sh-sci",
+        .id             = 3,
+        .dev            = {
+                .platform_data  = &scif3_platform_data,
+        },
+};
+
+static struct plat_sci_port scif4_platform_data = {
+        .mapbase        = 0xfffea000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 249, 250, 251, 248 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif4_device = {
+        .name           = "sh-sci",
+        .id             = 4,
+        .dev            = {
+                .platform_data  = &scif4_platform_data,
+        },
+};
+
+static struct plat_sci_port scif5_platform_data = {
+        .mapbase        = 0xfffea800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 253, 254, 255, 252 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif5_device = {
+        .name           = "sh-sci",
+        .id             = 5,
+        .dev            = {
+                .platform_data  = &scif5_platform_data,
+        },
+};
+
+static struct plat_sci_port scif6_platform_data = {
+        .mapbase        = 0xfffeb000,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 257, 258, 259, 256 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif6_device = {
+        .name           = "sh-sci",
+        .id             = 6,
+        .dev            = {
+                .platform_data  = &scif6_platform_data,
+        },
+};
+
+static struct plat_sci_port scif7_platform_data = {
+        .mapbase        = 0xfffeb800,
+        .flags          = UPF_BOOT_AUTOCONF,
+        .scscr          = SCSCR_RIE | SCSCR_TIE | SCSCR_RE | SCSCR_TE |
+                          SCSCR_REIE | SCSCR_TOIE,
+        .scbrr_algo_id  = SCBRR_ALGO_2,
+        .type           = PORT_SCIF,
+        .irqs           =  { 261, 262, 263, 260 },
+        .regtype        = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
+};
+
+static struct platform_device scif7_device = {
+        .name           = "sh-sci",
+        .id             = 7,
+        .dev            = {
+                .platform_data  = &scif7_platform_data,
+        },
+};
+
+static struct sh_timer_config cmt0_platform_data = {
+        .channel_offset = 0x02,
+        .timer_bit = 0,
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt0_resources[] = {
+        [0] = {
+                .name   = "CMT0",
+                .start  = 0xfffec002,
+                .end    = 0xfffec007,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 175,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt0_device = {
+        .name           = "sh_cmt",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &cmt0_platform_data,
+        },
+        .resource       = cmt0_resources,
+        .num_resources  = ARRAY_SIZE(cmt0_resources),
+};
+
+static struct sh_timer_config cmt1_platform_data = {
+        .name = "CMT1",
+        .channel_offset = 0x08,
+        .timer_bit = 1,
+        .clockevent_rating = 125,
+        .clocksource_rating = 0, /* disabled due to code generation issues */
+};
+
+static struct resource cmt1_resources[] = {
+        [0] = {
+                .name   = "CMT1",
+                .start  = 0xfffec008,
+                .end    = 0xfffec00d,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 176,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device cmt1_device = {
+        .name           = "sh_cmt",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &cmt1_platform_data,
+        },
+        .resource       = cmt1_resources,
+        .num_resources  = ARRAY_SIZE(cmt1_resources),
+};
+
+static struct sh_timer_config mtu2_0_platform_data = {
+        .name = "MTU2_0",
+        .channel_offset = -0x80,
+        .timer_bit = 0,
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_0_resources[] = {
+        [0] = {
+                .name   = "MTU2_0",
+                .start  = 0xfffe4300,
+                .end    = 0xfffe4326,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 179,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_0_device = {
+        .name           = "sh_mtu2",
+        .id             = 0,
+        .dev = {
+                .platform_data  = &mtu2_0_platform_data,
+        },
+        .resource       = mtu2_0_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_0_resources),
+};
+
+static struct sh_timer_config mtu2_1_platform_data = {
+        .name = "MTU2_1",
+        .channel_offset = -0x100,
+        .timer_bit = 1,
+        .clockevent_rating = 200,
+};
+
+static struct resource mtu2_1_resources[] = {
+        [0] = {
+                .name   = "MTU2_1",
+                .start  = 0xfffe4380,
+                .end    = 0xfffe4390,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 186,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device mtu2_1_device = {
+        .name           = "sh_mtu2",
+        .id             = 1,
+        .dev = {
+                .platform_data  = &mtu2_1_platform_data,
+        },
+        .resource       = mtu2_1_resources,
+        .num_resources  = ARRAY_SIZE(mtu2_1_resources),
+};
+
+static struct resource rtc_resources[] = {
+        [0] = {
+                .start  = 0xfffe6000,
+                .end    = 0xfffe6000 + 0x30 - 1,
+                .flags  = IORESOURCE_IO,
+        },
+        [1] = {
+                /* Shared Period/Carry/Alarm IRQ */
+                .start  = 296,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+
+static struct platform_device rtc_device = {
+        .name           = "sh-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(rtc_resources),
+        .resource       = rtc_resources,
+};
+
+/* USB Host */
+static void usb_port_power(int port, int power)
+{
+        __raw_writew(0x200 , 0xffffc0c2) ; /* Initialise UACS25 */
+}
+
+static struct r8a66597_platdata r8a66597_data = {
+        .on_chip = 1,
+        .endian = 1,
+        .port_power = usb_port_power,
+};
+
+static struct resource r8a66597_usb_host_resources[] = {
+        [0] = {
+                .start  = 0xffffc000,
+                .end    = 0xffffc0e4,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = 170,
+                .end    = 170,
+                .flags  = IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
+        },
+};
+
+static struct platform_device r8a66597_usb_host_device = {
+        .name           = "r8a66597_hcd",
+        .id             = 0,
+        .dev = {
+                .dma_mask               = NULL,         /*  not use dma */
+                .coherent_dma_mask      = 0xffffffff,
+                .platform_data          = &r8a66597_data,
+        },
+        .num_resources  = ARRAY_SIZE(r8a66597_usb_host_resources),
+        .resource       = r8a66597_usb_host_resources,
+};
+
+static struct platform_device *sh7264_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &cmt0_device,
+        &cmt1_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
+        &rtc_device,
+        &r8a66597_usb_host_device,
+};
+
+static int __init sh7264_devices_setup(void)
+{
+        return platform_add_devices(sh7264_devices,
+                                    ARRAY_SIZE(sh7264_devices));
+}
+arch_initcall(sh7264_devices_setup);
+
+void __init plat_irq_setup(void)
+{
+        register_intc_controller(&intc_desc);
+}
+
+static struct platform_device *sh7264_early_devices[] __initdata = {
+        &scif0_device,
+        &scif1_device,
+        &scif2_device,
+        &scif3_device,
+        &scif4_device,
+        &scif5_device,
+        &scif6_device,
+        &scif7_device,
+        &cmt0_device,
+        &cmt1_device,
+        &mtu2_0_device,
+        &mtu2_1_device,
+};
+
+void __init plat_early_device_setup(void)
+{
+        early_platform_add_devices(sh7264_early_devices,
+                                   ARRAY_SIZE(sh7264_early_devices));
+}
diff --git a/arch/sh/tools/mach-types b/arch/sh/tools/mach-types
index 6dd56c4d0054..d007c81acfad 100644
--- a/arch/sh/tools/mach-types
+++ b/arch/sh/tools/mach-types
@@ -51,6 +51,7 @@ SDK7780			SH_SDK7780
 MIGOR                   SH_MIGOR
 RSK7201                 SH_RSK7201
 RSK7203                 SH_RSK7203
+RSK7264                 SH_RSK7264
 AP325RXA                SH_AP325RXA
 SH2007                  SH_SH2007
 SH7757LCR               SH_SH7757LCR
diff --git a/arch/sparc/kernel/leon_smp.c b/arch/sparc/kernel/leon_smp.c
index 1210fde18740..160cac9c4036 100644
--- a/arch/sparc/kernel/leon_smp.c
+++ b/arch/sparc/kernel/leon_smp.c
@@ -23,6 +23,7 @@
 #include <linux/pm.h>
 #include <linux/delay.h>
 #include <linux/gfp.h>
+#include <linux/cpu.h>
 
 #include <asm/cacheflush.h>
 #include <asm/tlbflush.h>
@@ -78,6 +79,8 @@ void __cpuinit leon_callin(void)
         local_flush_tlb_all();
         leon_configure_cache_smp();
 
+        notify_cpu_starting(cpuid);
+
         /* Get our local ticker going. */
         smp_setup_percpu_timer();
 
diff --git a/arch/sparc/kernel/sys_sparc_64.c b/arch/sparc/kernel/sys_sparc_64.c
index 232df9949530..3ee51f189a55 100644
--- a/arch/sparc/kernel/sys_sparc_64.c
+++ b/arch/sparc/kernel/sys_sparc_64.c
@@ -566,15 +566,10 @@ out:
 
 SYSCALL_DEFINE2(64_munmap, unsigned long, addr, size_t, len)
 {
-        long ret;
-
         if (invalid_64bit_range(addr, len))
                 return -EINVAL;
 
-        down_write(&current->mm->mmap_sem);
-        ret = do_munmap(current->mm, addr, len);
-        up_write(&current->mm->mmap_sem);
-        return ret;
+        return vm_munmap(addr, len);
 }
 
 extern unsigned long do_mremap(unsigned long addr,
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index 5d5a635530bd..32e6cbe8dff3 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -47,8 +47,8 @@ struct pci_controller {
  */
 #define PCI_DMA_BUS_IS_PHYS     1
 
-int __devinit tile_pci_init(void);
-int __devinit pcibios_init(void);
+int __init tile_pci_init(void);
+int __init pcibios_init(void);
 
 static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
 
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index a1bb59eecc18..b56d12bf5900 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id,
  *
  * Returns the number of controllers discovered.
  */
-int __devinit tile_pci_init(void)
+int __init tile_pci_init(void)
 {
         int i;
 
@@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void)
  * The controllers have been set up by the time we get here, by a call to
  * tile_pci_init.
  */
-int __devinit pcibios_init(void)
+int __init pcibios_init(void)
 {
         int i;
 
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c
index 9efbc1391b3c..89529c9f0605 100644
--- a/arch/tile/kernel/single_step.c
+++ b/arch/tile/kernel/single_step.c
@@ -346,12 +346,10 @@ void single_step_once(struct pt_regs *regs)
                 }
 
                 /* allocate a cache line of writable, executable memory */
-                down_write(&current->mm->mmap_sem);
-                buffer = (void __user *) do_mmap(NULL, 0, 64,
+                buffer = (void __user *) vm_mmap(NULL, 0, 64,
                                           PROT_EXEC | PROT_READ | PROT_WRITE,
                                           MAP_PRIVATE | MAP_ANONYMOUS,
                                           0);
-                up_write(&current->mm->mmap_sem);
 
                 if (IS_ERR((void __force *)buffer)) {
                         kfree(state);
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 1d14cc6b79ad..c9866b0b77d8 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -81,7 +81,7 @@ config X86
         select CLKEVT_I8253
         select ARCH_HAVE_NMI_SAFE_CMPXCHG
         select GENERIC_IOMAP
-        select DCACHE_WORD_ACCESS if !DEBUG_PAGEALLOC
+        select DCACHE_WORD_ACCESS
 
 config INSTRUCTION_DECODER
         def_bool (KPROBES || PERF_EVENTS)
diff --git a/arch/x86/boot/compressed/head_32.S b/arch/x86/boot/compressed/head_32.S
index a0559930a180..c85e3ac99bba 100644
--- a/arch/x86/boot/compressed/head_32.S
+++ b/arch/x86/boot/compressed/head_32.S
@@ -33,6 +33,9 @@
         __HEAD
 ENTRY(startup_32)
 #ifdef CONFIG_EFI_STUB
+        jmp     preferred_addr
+
+        .balign 0x10
         /*
          * We don't need the return address, so set up the stack so
          * efi_main() can find its arugments.
@@ -41,12 +44,17 @@ ENTRY(startup_32)
 
         call    efi_main
         cmpl    $0, %eax
-        je      preferred_addr
         movl    %eax, %esi
-        call    1f
+        jne     2f
 1:
+        /* EFI init failed, so hang. */
+        hlt
+        jmp     1b
+2:
+        call    3f
+3:
         popl    %eax
-        subl    $1b, %eax
+        subl    $3b, %eax
         subl    BP_pref_address(%esi), %eax
         add     BP_code32_start(%esi), %eax
         leal    preferred_addr(%eax), %eax
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 558d76ce23bc..87e03a13d8e3 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -200,18 +200,28 @@ ENTRY(startup_64)
          * entire text+data+bss and hopefully all of memory.
          */
 #ifdef CONFIG_EFI_STUB
-        pushq   %rsi
+        /*
+         * The entry point for the PE/COFF executable is 0x210, so only
+         * legacy boot loaders will execute this jmp.
+         */
+        jmp     preferred_addr
+
+        .org 0x210
         mov     %rcx, %rdi
         mov     %rdx, %rsi
         call    efi_main
-        popq    %rsi
-        cmpq    $0,%rax
-        je      preferred_addr
         movq    %rax,%rsi
-        call    1f
+        cmpq    $0,%rax
+        jne     2f
 1:
+        /* EFI init failed, so hang. */
+        hlt
+        jmp     1b
+2:
+        call    3f
+3:
         popq    %rax
-        subq    $1b, %rax
+        subq    $3b, %rax
         subq    BP_pref_address(%rsi), %rax
         add     BP_code32_start(%esi), %eax
         leaq    preferred_addr(%rax), %rax
diff --git a/arch/x86/boot/compressed/relocs.c b/arch/x86/boot/compressed/relocs.c
index d3c0b0277666..fb7117a4ade1 100644
--- a/arch/x86/boot/compressed/relocs.c
+++ b/arch/x86/boot/compressed/relocs.c
@@ -403,13 +403,11 @@ static void print_absolute_symbols(void)
         for (i = 0; i < ehdr.e_shnum; i++) {
                 struct section *sec = &secs[i];
                 char *sym_strtab;
-                Elf32_Sym *sh_symtab;
                 int j;
 
                 if (sec->shdr.sh_type != SHT_SYMTAB) {
                         continue;
                 }
-                sh_symtab = sec->symtab;
                 sym_strtab = sec->link->strtab;
                 for (j = 0; j < sec->shdr.sh_size/sizeof(Elf32_Sym); j++) {
                         Elf32_Sym *sym;
diff --git a/arch/x86/boot/tools/build.c b/arch/x86/boot/tools/build.c
index ed549767a231..24443a332083 100644
--- a/arch/x86/boot/tools/build.c
+++ b/arch/x86/boot/tools/build.c
@@ -205,8 +205,13 @@ int main(int argc, char ** argv)
         put_unaligned_le32(file_sz, &buf[pe_header + 0x50]);
 
 #ifdef CONFIG_X86_32
-        /* Address of entry point */
-        put_unaligned_le32(i, &buf[pe_header + 0x28]);
+        /*
+         * Address of entry point.
+         *
+         * The EFI stub entry point is +16 bytes from the start of
+         * the .text section.
+         */
+        put_unaligned_le32(i + 16, &buf[pe_header + 0x28]);
 
         /* .text size */
         put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]);
@@ -217,9 +222,11 @@ int main(int argc, char ** argv)
         /*
          * Address of entry point. startup_32 is at the beginning and
          * the 64-bit entry point (startup_64) is always 512 bytes
-         * after.
+         * after. The EFI stub entry point is 16 bytes after that, as
+         * the first instruction allows legacy loaders to jump over
+         * the EFI stub initialisation
          */
-        put_unaligned_le32(i + 512, &buf[pe_header + 0x28]);
+        put_unaligned_le32(i + 528, &buf[pe_header + 0x28]);
 
         /* .text size */
         put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]);
diff --git a/arch/x86/ia32/ia32_aout.c b/arch/x86/ia32/ia32_aout.c
index d511d951a052..07b3a68d2d29 100644
--- a/arch/x86/ia32/ia32_aout.c
+++ b/arch/x86/ia32/ia32_aout.c
@@ -119,9 +119,7 @@ static void set_brk(unsigned long start, unsigned long end)
         end = PAGE_ALIGN(end);
         if (end <= start)
                 return;
-        down_write(&current->mm->mmap_sem);
-        do_brk(start, end - start);
-        up_write(&current->mm->mmap_sem);
+        vm_brk(start, end - start);
 }
 
 #ifdef CORE_DUMP
@@ -296,8 +294,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
 
         /* OK, This is the point of no return */
         set_personality(PER_LINUX);
-        set_thread_flag(TIF_IA32);
-        current->mm->context.ia32_compat = 1;
+        set_personality_ia32(false);
 
         setup_new_exec(bprm);
 
@@ -332,9 +329,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
                 pos = 32;
                 map_size = ex.a_text+ex.a_data;
 
-                down_write(&current->mm->mmap_sem);
-                error = do_brk(text_addr & PAGE_MASK, map_size);
-                up_write(&current->mm->mmap_sem);
+                error = vm_brk(text_addr & PAGE_MASK, map_size);
 
                 if (error != (text_addr & PAGE_MASK)) {
                         send_sig(SIGKILL, current, 0);
@@ -373,9 +368,7 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
                 if (!bprm->file->f_op->mmap || (fd_offset & ~PAGE_MASK) != 0) {
                         loff_t pos = fd_offset;
 
-                        down_write(&current->mm->mmap_sem);
-                        do_brk(N_TXTADDR(ex), ex.a_text+ex.a_data);
-                        up_write(&current->mm->mmap_sem);
+                        vm_brk(N_TXTADDR(ex), ex.a_text+ex.a_data);
                         bprm->file->f_op->read(bprm->file,
                                         (char __user *)N_TXTADDR(ex),
                                         ex.a_text+ex.a_data, &pos);
@@ -385,26 +378,22 @@ static int load_aout_binary(struct linux_binprm *bprm, struct pt_regs *regs)
                         goto beyond_if;
                 }
 
-                down_write(&current->mm->mmap_sem);
-                error = do_mmap(bprm->file, N_TXTADDR(ex), ex.a_text,
+                error = vm_mmap(bprm->file, N_TXTADDR(ex), ex.a_text,
                                 PROT_READ | PROT_EXEC,
                                 MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE |
                                 MAP_EXECUTABLE | MAP_32BIT,
                                 fd_offset);
-                up_write(&current->mm->mmap_sem);
 
                 if (error != N_TXTADDR(ex)) {
                         send_sig(SIGKILL, current, 0);
                         return error;
                 }
 
-                down_write(&current->mm->mmap_sem);
-                error = do_mmap(bprm->file, N_DATADDR(ex), ex.a_data,
+                error = vm_mmap(bprm->file, N_DATADDR(ex), ex.a_data,
                                 PROT_READ | PROT_WRITE | PROT_EXEC,
                                 MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE |
                                 MAP_EXECUTABLE | MAP_32BIT,
                                 fd_offset + ex.a_text);
-                up_write(&current->mm->mmap_sem);
                 if (error != N_DATADDR(ex)) {
                         send_sig(SIGKILL, current, 0);
                         return error;
@@ -476,9 +465,7 @@ static int load_aout_library(struct file *file)
                         error_time = jiffies;
                 }
 #endif
-                down_write(&current->mm->mmap_sem);
-                do_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss);
-                up_write(&current->mm->mmap_sem);
+                vm_brk(start_addr, ex.a_text + ex.a_data + ex.a_bss);
 
                 file->f_op->read(file, (char __user *)start_addr,
                         ex.a_text + ex.a_data, &pos);
@@ -490,12 +477,10 @@ static int load_aout_library(struct file *file)
                 goto out;
         }
         /* Now use mmap to map the library into memory. */
-        down_write(&current->mm->mmap_sem);
-        error = do_mmap(file, start_addr, ex.a_text + ex.a_data,
+        error = vm_mmap(file, start_addr, ex.a_text + ex.a_data,
                         PROT_READ | PROT_WRITE | PROT_EXEC,
                         MAP_FIXED | MAP_PRIVATE | MAP_DENYWRITE | MAP_32BIT,
                         N_TXTOFF(ex));
-        up_write(&current->mm->mmap_sem);
         retval = error;
         if (error != start_addr)
                 goto out;
@@ -503,9 +488,7 @@ static int load_aout_library(struct file *file)
         len = PAGE_ALIGN(ex.a_text + ex.a_data);
         bss = ex.a_text + ex.a_data + ex.a_bss;
         if (bss > len) {
-                down_write(&current->mm->mmap_sem);
-                error = do_brk(start_addr + len, bss - len);
-                up_write(&current->mm->mmap_sem);
+                error = vm_brk(start_addr + len, bss - len);
                 retval = error;
                 if (error != start_addr + len)
                         goto out;
diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h
index 3427b7798dbc..7ef7c3020e5c 100644
--- a/arch/x86/include/asm/posix_types.h
+++ b/arch/x86/include/asm/posix_types.h
@@ -7,9 +7,9 @@
 #else
 # ifdef __i386__
 #  include "posix_types_32.h"
-# elif defined(__LP64__)
-#  include "posix_types_64.h"
-# else
+# elif defined(__ILP32__)
 #  include "posix_types_x32.h"
+# else
+#  include "posix_types_64.h"
 # endif
 #endif
diff --git a/arch/x86/include/asm/sigcontext.h b/arch/x86/include/asm/sigcontext.h
index 4a085383af27..5ca71c065eef 100644
--- a/arch/x86/include/asm/sigcontext.h
+++ b/arch/x86/include/asm/sigcontext.h
@@ -257,7 +257,7 @@ struct sigcontext {
         __u64 oldmask;
         __u64 cr2;
         struct _fpstate __user *fpstate;        /* zero when no FPU context */
-#ifndef __LP64__
+#ifdef __ILP32__
         __u32 __fpstate_pad;
 #endif
         __u64 reserved1[8];
diff --git a/arch/x86/include/asm/siginfo.h b/arch/x86/include/asm/siginfo.h
index fc1aa5535646..34c47b3341c0 100644
--- a/arch/x86/include/asm/siginfo.h
+++ b/arch/x86/include/asm/siginfo.h
@@ -2,7 +2,13 @@
 #define _ASM_X86_SIGINFO_H
 
 #ifdef __x86_64__
-# define __ARCH_SI_PREAMBLE_SIZE        (4 * sizeof(int))
+# ifdef __ILP32__ /* x32 */
+typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
+#  define __ARCH_SI_CLOCK_T             __kernel_si_clock_t
+#  define __ARCH_SI_ATTRIBUTES          __attribute__((aligned(8)))
+# else /* x86-64 */
+#  define __ARCH_SI_PREAMBLE_SIZE       (4 * sizeof(int))
+# endif
 #endif
 
 #include <asm-generic/siginfo.h>
diff --git a/arch/x86/include/asm/unistd.h b/arch/x86/include/asm/unistd.h
index 37cdc9d99bb1..4437001d8e3d 100644
--- a/arch/x86/include/asm/unistd.h
+++ b/arch/x86/include/asm/unistd.h
@@ -63,10 +63,10 @@
 #else
 # ifdef __i386__
 #  include <asm/unistd_32.h>
-# elif defined(__LP64__)
-#  include <asm/unistd_64.h>
-# else
+# elif defined(__ILP32__)
 #  include <asm/unistd_x32.h>
+# else
+#  include <asm/unistd_64.h>
 # endif
 #endif
 
diff --git a/arch/x86/include/asm/word-at-a-time.h b/arch/x86/include/asm/word-at-a-time.h
index 6fe6767b7124..e58f03b206c3 100644
--- a/arch/x86/include/asm/word-at-a-time.h
+++ b/arch/x86/include/asm/word-at-a-time.h
@@ -43,4 +43,37 @@ static inline unsigned long has_zero(unsigned long a)
         return ((a - REPEAT_BYTE(0x01)) & ~a) & REPEAT_BYTE(0x80);
 }
 
+/*
+ * Load an unaligned word from kernel space.
+ *
+ * In the (very unlikely) case of the word being a page-crosser
+ * and the next page not being mapped, take the exception and
+ * return zeroes in the non-existing part.
+ */
+static inline unsigned long load_unaligned_zeropad(const void *addr)
+{
+        unsigned long ret, dummy;
+
+        asm(
+                "1:\tmov %2,%0\n"
+                "2:\n"
+                ".section .fixup,\"ax\"\n"
+                "3:\t"
+                "lea %2,%1\n\t"
+                "and %3,%1\n\t"
+                "mov (%1),%0\n\t"
+                "leal %2,%%ecx\n\t"
+                "andl %4,%%ecx\n\t"
+                "shll $3,%%ecx\n\t"
+                "shr %%cl,%0\n\t"
+                "jmp 2b\n"
+                ".previous\n"
+                _ASM_EXTABLE(1b, 3b)
+                :"=&r" (ret),"=&c" (dummy)
+                :"m" (*(unsigned long *)addr),
+                 "i" (-sizeof(unsigned long)),
+                 "i" (sizeof(unsigned long)-1));
+        return ret;
+}
+
 #endif /* _ASM_WORD_AT_A_TIME_H */
diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
index baaca8defec8..764b66a4cf89 100644
--- a/arch/x86/include/asm/x86_init.h
+++ b/arch/x86/include/asm/x86_init.h
@@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi;
 
 extern void x86_init_noop(void);
 extern void x86_init_uint_noop(unsigned int unused);
-extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node);
 
 #endif
diff --git a/arch/x86/kernel/acpi/sleep.c b/arch/x86/kernel/acpi/sleep.c
index 103b6ab368d3..146a49c763a4 100644
--- a/arch/x86/kernel/acpi/sleep.c
+++ b/arch/x86/kernel/acpi/sleep.c
@@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags;
 static char temp_stack[4096];
 #endif
 
+asmlinkage void acpi_enter_s3(void)
+{
+        acpi_enter_sleep_state(3, wake_sleep_flags);
+}
 /**
  * acpi_suspend_lowlevel - save kernel state
  *
diff --git a/arch/x86/kernel/acpi/sleep.h b/arch/x86/kernel/acpi/sleep.h
index 416d4be13fef..d68677a2a010 100644
--- a/arch/x86/kernel/acpi/sleep.h
+++ b/arch/x86/kernel/acpi/sleep.h
@@ -3,12 +3,16 @@
  */
 
 #include <asm/trampoline.h>
+#include <linux/linkage.h>
 
 extern unsigned long saved_video_mode;
 extern long saved_magic;
 
 extern int wakeup_pmode_return;
 
+extern u8 wake_sleep_flags;
+extern asmlinkage void acpi_enter_s3(void);
+
 extern unsigned long acpi_copy_wakeup_routine(unsigned long);
 extern void wakeup_long64(void);
 
diff --git a/arch/x86/kernel/acpi/wakeup_32.S b/arch/x86/kernel/acpi/wakeup_32.S
index 13ab720573e3..72610839f03b 100644
--- a/arch/x86/kernel/acpi/wakeup_32.S
+++ b/arch/x86/kernel/acpi/wakeup_32.S
@@ -74,9 +74,7 @@ restore_registers:
 ENTRY(do_suspend_lowlevel)
         call    save_processor_state
         call    save_registers
-        pushl   $3
-        call    acpi_enter_sleep_state
-        addl    $4, %esp
+        call    acpi_enter_s3
 
 #       In case of S3 failure, we'll emerge here.  Jump
 #       to ret_point to recover
diff --git a/arch/x86/kernel/acpi/wakeup_64.S b/arch/x86/kernel/acpi/wakeup_64.S
index 8ea5164cbd04..014d1d28c397 100644
--- a/arch/x86/kernel/acpi/wakeup_64.S
+++ b/arch/x86/kernel/acpi/wakeup_64.S
@@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel)
         movq    %rsi, saved_rsi
 
         addq    $8, %rsp
-        movl    $3, %edi
-        xorl    %eax, %eax
-        call    acpi_enter_sleep_state
+        call    acpi_enter_s3
         /* in case something went wrong, restore the machine status and go on */
         jmp     resume_point
 
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 11544d8f1e97..edc24480469f 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1637,9 +1637,11 @@ static int __init apic_verify(void)
         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 
         /* The BIOS may have set up the APIC at some other address */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        if (l & MSR_IA32_APICBASE_ENABLE)
-                mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+        if (boot_cpu_data.x86 >= 6) {
+                rdmsr(MSR_IA32_APICBASE, l, h);
+                if (l & MSR_IA32_APICBASE_ENABLE)
+                        mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
+        }
 
         pr_info("Found and enabled local APIC!\n");
         return 0;
@@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr)
          * MSR. This can only be done in software for Intel P6 or later
          * and AMD K7 (Model > 1) or later.
          */
-        rdmsr(MSR_IA32_APICBASE, l, h);
-        if (!(l & MSR_IA32_APICBASE_ENABLE)) {
-                pr_info("Local APIC disabled by BIOS -- reenabling.\n");
-                l &= ~MSR_IA32_APICBASE_BASE;
-                l |= MSR_IA32_APICBASE_ENABLE | addr;
-                wrmsr(MSR_IA32_APICBASE, l, h);
-                enabled_via_apicbase = 1;
+        if (boot_cpu_data.x86 >= 6) {
+                rdmsr(MSR_IA32_APICBASE, l, h);
+                if (!(l & MSR_IA32_APICBASE_ENABLE)) {
+                        pr_info("Local APIC disabled by BIOS -- reenabling.\n");
+                        l &= ~MSR_IA32_APICBASE_BASE;
+                        l |= MSR_IA32_APICBASE_ENABLE | addr;
+                        wrmsr(MSR_IA32_APICBASE, l, h);
+                        enabled_via_apicbase = 1;
+                }
         }
         return apic_verify();
 }
@@ -2209,10 +2213,12 @@ static void lapic_resume(void)
                  * FIXME! This will be wrong if we ever support suspend on
                  * SMP! We'll need to do this as part of the CPU restore!
                  */
-                rdmsr(MSR_IA32_APICBASE, l, h);
-                l &= ~MSR_IA32_APICBASE_BASE;
-                l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
-                wrmsr(MSR_IA32_APICBASE, l, h);
+                if (boot_cpu_data.x86 >= 6) {
+                        rdmsr(MSR_IA32_APICBASE, l, h);
+                        l &= ~MSR_IA32_APICBASE_BASE;
+                        l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
+                        wrmsr(MSR_IA32_APICBASE, l, h);
+                }
         }
 
         maxlvt = lapic_get_maxlvt();
diff --git a/arch/x86/kernel/apic/apic_numachip.c b/arch/x86/kernel/apic/apic_numachip.c
index 899803e03214..23e75422e013 100644
--- a/arch/x86/kernel/apic/apic_numachip.c
+++ b/arch/x86/kernel/apic/apic_numachip.c
@@ -207,8 +207,11 @@ static void __init map_csrs(void)
 
 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
 {
-        c->phys_proc_id = node;
-        per_cpu(cpu_llc_id, smp_processor_id()) = node;
+
+        if (c->phys_proc_id != node) {
+                c->phys_proc_id = node;
+                per_cpu(cpu_llc_id, smp_processor_id()) = node;
+        }
 }
 
 static int __init numachip_system_init(void)
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index 8a778db45e3a..991e315f4227 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 {
         if (x2apic_phys)
                 return x2apic_enabled();
+        else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
+                (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
+                x2apic_enabled()) {
+                printk(KERN_DEBUG "System requires x2apic physical mode\n");
+                return 1;
+        }
         else
                 return 0;
 }
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 0a44b90602b0..146bb6218eec 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -26,7 +26,8 @@
  *      contact AMD for precise details and a CPU swap.
  *
  *      See     http://www.multimania.com/poulot/k6bug.html
- *              http://www.amd.com/K6/k6docs/revgd.html
+ *      and     section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
+ *              (Publication # 21266  Issue Date: August 1998)
  *
  *      The following test is erm.. interesting. AMD neglected to up
  *      the chip setting when fixing the bug but they also tweaked some
@@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
                                 "system stability may be impaired when more than 32 MB are used.\n");
                 else
                         printk(KERN_CONT "probably OK (after B9730xxxx).\n");
-                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
         }
 
         /* K6 with old style WHCR */
@@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
                 node = per_cpu(cpu_llc_id, cpu);
 
         /*
-         * If core numbers are inconsistent, it's likely a multi-fabric platform,
-         * so invoke platform-specific handler
+         * On multi-fabric platform (e.g. Numascale NumaChip) a
+         * platform-specific handler needs to be called to fixup some
+         * IDs of the CPU.
          */
-        if (c->phys_proc_id != node)
+        if (x86_cpuinit.fixup_cpu_id)
                 x86_cpuinit.fixup_cpu_id(c, node);
 
         if (!node_online(node)) {
@@ -579,6 +580,24 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 }
         }
 
+        /* re-enable TopologyExtensions if switched off by BIOS */
+        if ((c->x86 == 0x15) &&
+            (c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
+            !cpu_has(c, X86_FEATURE_TOPOEXT)) {
+                u64 val;
+
+                if (!rdmsrl_amd_safe(0xc0011005, &val)) {
+                        val |= 1ULL << 54;
+                        wrmsrl_amd_safe(0xc0011005, val);
+                        rdmsrl(0xc0011005, val);
+                        if (val & (1ULL << 54)) {
+                                set_cpu_cap(c, X86_FEATURE_TOPOEXT);
+                                printk(KERN_INFO FW_INFO "CPU: Re-enabling "
+                                  "disabled Topology Extensions Support\n");
+                        }
+                }
+        }
+
         cpu_detect_cache_sizes(c);
 
         /* Multi core CPU? */
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 67e258362a3d..cf79302198a6 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1163,15 +1163,6 @@ static void dbg_restore_debug_regs(void)
 #endif /* ! CONFIG_KGDB */
 
 /*
- * Prints an error where the NUMA and configured core-number mismatch and the
- * platform didn't override this to fix it up
- */
-void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
-{
-        pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
-}
-
-/*
  * cpu_init() initializes state that is per-CPU. Some data is already
  * initialized (naturally) in the bootstrap process, such as the GDT
  * and IDT. We reload them nevertheless, this function acts as a
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 73d08ed98a64..b8f3653dddbc 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
         /*  check if @slot is already used or the index is already disabled */
         ret = amd_get_l3_disable_slot(nb, slot);
         if (ret >= 0)
-                return -EINVAL;
+                return -EEXIST;
 
         if (index > nb->l3_cache.indices)
                 return -EINVAL;
 
         /* check whether the other slot has disabled the same index already */
         if (index == amd_get_l3_disable_slot(nb, !slot))
-                return -EINVAL;
+                return -EEXIST;
 
         amd_l3_disable_index(nb, cpu, slot, index);
 
@@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
         err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
         if (err) {
                 if (err == -EEXIST)
-                        printk(KERN_WARNING "L3 disable slot %d in use!\n",
-                                            slot);
+                        pr_warning("L3 slot %d in use/index already disabled!\n",
+                                   slot);
                 return err;
         }
         return count;
diff --git a/arch/x86/kernel/i387.c b/arch/x86/kernel/i387.c
index 7734bcbb5a3a..2d6e6498c176 100644
--- a/arch/x86/kernel/i387.c
+++ b/arch/x86/kernel/i387.c
@@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk)
         if (tsk_used_math(tsk)) {
                 if (HAVE_HWFP && tsk == current)
                         unlazy_fpu(tsk);
+                tsk->thread.fpu.last_cpu = ~0;
                 return 0;
         }
 
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index b8ba6e4a27e4..e554e5ad2fe8 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -79,7 +79,6 @@ struct kvm_task_sleep_node {
         u32 token;
         int cpu;
         bool halted;
-        struct mm_struct *mm;
 };
 
 static struct kvm_task_sleep_head {
@@ -126,9 +125,7 @@ void kvm_async_pf_task_wait(u32 token)
 
         n.token = token;
         n.cpu = smp_processor_id();
-        n.mm = current->active_mm;
         n.halted = idle || preempt_count() > 1;
-        atomic_inc(&n.mm->mm_count);
         init_waitqueue_head(&n.wq);
         hlist_add_head(&n.link, &b->list);
         spin_unlock(&b->lock);
@@ -161,9 +158,6 @@ EXPORT_SYMBOL_GPL(kvm_async_pf_task_wait);
 static void apf_task_wake_one(struct kvm_task_sleep_node *n)
 {
         hlist_del_init(&n->link);
-        if (!n->mm)
-                return;
-        mmdrop(n->mm);
         if (n->halted)
                 smp_send_reschedule(n->cpu);
         else if (waitqueue_active(&n->wq))
@@ -207,7 +201,7 @@ again:
                  * async PF was not yet handled.
                  * Add dummy entry for the token.
                  */
-                n = kmalloc(sizeof(*n), GFP_ATOMIC);
+                n = kzalloc(sizeof(*n), GFP_ATOMIC);
                 if (!n) {
                         /*
                          * Allocation failed! Busy wait while other cpu
@@ -219,7 +213,6 @@ again:
                 }
                 n->token = token;
                 n->cpu = smp_processor_id();
-                n->mm = NULL;
                 init_waitqueue_head(&n->wq);
                 hlist_add_head(&n->link, &b->list);
         } else
diff --git a/arch/x86/kernel/microcode_amd.c b/arch/x86/kernel/microcode_amd.c
index 73465aab28f8..8a2ce8fd41c0 100644
--- a/arch/x86/kernel/microcode_amd.c
+++ b/arch/x86/kernel/microcode_amd.c
@@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
 {
         struct cpuinfo_x86 *c = &cpu_data(cpu);
 
-        if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
-                pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
-                return -1;
-        }
-
         csig->rev = c->microcode;
         pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
 
@@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = {
 
 struct microcode_ops * __init init_amd_microcode(void)
 {
+        struct cpuinfo_x86 *c = &cpu_data(0);
+
+        if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
+                pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
+                return NULL;
+        }
+
         patch = (void *)get_zeroed_page(GFP_KERNEL);
         if (!patch)
                 return NULL;
diff --git a/arch/x86/kernel/microcode_core.c b/arch/x86/kernel/microcode_core.c
index 87a0f8688301..c9bda6d6035c 100644
--- a/arch/x86/kernel/microcode_core.c
+++ b/arch/x86/kernel/microcode_core.c
@@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif)
         if (err)
                 return err;
 
-        if (microcode_init_cpu(cpu) == UCODE_ERROR) {
-                sysfs_remove_group(&dev->kobj, &mc_attr_group);
+        if (microcode_init_cpu(cpu) == UCODE_ERROR)
                 return -EINVAL;
-        }
 
         return err;
 }
@@ -528,11 +526,11 @@ static int __init microcode_init(void)
                 microcode_ops = init_intel_microcode();
         else if (c->x86_vendor == X86_VENDOR_AMD)
                 microcode_ops = init_amd_microcode();
-
-        if (!microcode_ops) {
+        else
                 pr_err("no support for this CPU vendor\n");
+
+        if (!microcode_ops)
                 return -ENODEV;
-        }
 
         microcode_pdev = platform_device_register_simple("microcode", -1,
                                                          NULL, 0);
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 733ca39f367e..43d8b48b23e6 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -423,6 +423,7 @@ void set_personality_ia32(bool x32)
                 current_thread_info()->status |= TS_COMPAT;
         }
 }
+EXPORT_SYMBOL_GPL(set_personality_ia32);
 
 unsigned long get_wchan(struct task_struct *p)
 {
diff --git a/arch/x86/kernel/setup_percpu.c b/arch/x86/kernel/setup_percpu.c
index 71f4727da373..5a98aa272184 100644
--- a/arch/x86/kernel/setup_percpu.c
+++ b/arch/x86/kernel/setup_percpu.c
@@ -185,10 +185,22 @@ void __init setup_per_cpu_areas(void)
 #endif
         rc = -EINVAL;
         if (pcpu_chosen_fc != PCPU_FC_PAGE) {
-                const size_t atom_size = cpu_has_pse ? PMD_SIZE : PAGE_SIZE;
                 const size_t dyn_size = PERCPU_MODULE_RESERVE +
                         PERCPU_DYNAMIC_RESERVE - PERCPU_FIRST_CHUNK_RESERVE;
+                size_t atom_size;
 
+                /*
+                 * On 64bit, use PMD_SIZE for atom_size so that embedded
+                 * percpu areas are aligned to PMD.  This, in the future,
+                 * can also allow using PMD mappings in vmalloc area.  Use
+                 * PAGE_SIZE on 32bit as vmalloc space is highly contended
+                 * and large vmalloc area allocs can easily fail.
+                 */
+#ifdef CONFIG_X86_64
+                atom_size = PMD_SIZE;
+#else
+                atom_size = PAGE_SIZE;
+#endif
                 rc = pcpu_embed_first_chunk(PERCPU_FIRST_CHUNK_RESERVE,
                                             dyn_size, atom_size,
                                             pcpu_cpu_distance,
diff --git a/arch/x86/kernel/x86_init.c b/arch/x86/kernel/x86_init.c
index e9f265fd79ae..9cf71d0b2d37 100644
--- a/arch/x86/kernel/x86_init.c
+++ b/arch/x86/kernel/x86_init.c
@@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = {
 struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
         .early_percpu_clock_init        = x86_init_noop,
         .setup_percpu_clockev           = setup_secondary_APIC_clock,
-        .fixup_cpu_id                   = x86_default_fixup_cpu_id,
 };
 
 static void default_nmi_init(void) { };
diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c
index 173df38dbda5..2e88438ffd83 100644
--- a/arch/x86/kvm/pmu.c
+++ b/arch/x86/kvm/pmu.c
@@ -459,17 +459,17 @@ void kvm_pmu_cpuid_update(struct kvm_vcpu *vcpu)
         pmu->available_event_types = ~entry->ebx & ((1ull << bitmap_len) - 1);
 
         if (pmu->version == 1) {
-                pmu->global_ctrl = (1 << pmu->nr_arch_gp_counters) - 1;
-                return;
+                pmu->nr_arch_fixed_counters = 0;
+        } else {
+                pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f),
+                                X86_PMC_MAX_FIXED);
+                pmu->counter_bitmask[KVM_PMC_FIXED] =
+                        ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1;
         }
 
-        pmu->nr_arch_fixed_counters = min((int)(entry->edx & 0x1f),
-                        X86_PMC_MAX_FIXED);
-        pmu->counter_bitmask[KVM_PMC_FIXED] =
-                ((u64)1 << ((entry->edx >> 5) & 0xff)) - 1;
-        pmu->global_ctrl_mask = ~(((1 << pmu->nr_arch_gp_counters) - 1)
-                        | (((1ull << pmu->nr_arch_fixed_counters) - 1)
-                                << X86_PMC_IDX_FIXED));
+        pmu->global_ctrl = ((1 << pmu->nr_arch_gp_counters) - 1) |
+                (((1ull << pmu->nr_arch_fixed_counters) - 1) << X86_PMC_IDX_FIXED);
+        pmu->global_ctrl_mask = ~pmu->global_ctrl;
 }
 
 void kvm_pmu_init(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index ad85adfef843..4ff0ab9bc3c8 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -2210,9 +2210,12 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
                 msr = find_msr_entry(vmx, msr_index);
                 if (msr) {
                         msr->data = data;
-                        if (msr - vmx->guest_msrs < vmx->save_nmsrs)
+                        if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
+                                preempt_disable();
                                 kvm_set_shared_msr(msr->index, msr->data,
                                                    msr->mask);
+                                preempt_enable();
+                        }
                         break;
                 }
                 ret = kvm_set_msr_common(vcpu, msr_index, data);
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 4044ce0bf7c1..185a2b823a2d 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -6336,13 +6336,11 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
                 if (npages && !old.rmap) {
                         unsigned long userspace_addr;
 
-                        down_write(&current->mm->mmap_sem);
-                        userspace_addr = do_mmap(NULL, 0,
+                        userspace_addr = vm_mmap(NULL, 0,
                                                  npages * PAGE_SIZE,
                                                  PROT_READ | PROT_WRITE,
                                                  map_flags,
                                                  0);
-                        up_write(&current->mm->mmap_sem);
 
                         if (IS_ERR((void *)userspace_addr))
                                 return PTR_ERR((void *)userspace_addr);
@@ -6366,10 +6364,8 @@ void kvm_arch_commit_memory_region(struct kvm *kvm,
         if (!user_alloc && !old.user_alloc && old.rmap && !npages) {
                 int ret;
 
-                down_write(&current->mm->mmap_sem);
-                ret = do_munmap(current->mm, old.userspace_addr,
+                ret = vm_munmap(old.userspace_addr,
                                 old.npages * PAGE_SIZE);
-                up_write(&current->mm->mmap_sem);
                 if (ret < 0)
                         printk(KERN_WARNING
                                "kvm_vm_ioctl_set_memory_region: "
@@ -6585,6 +6581,7 @@ void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
                 kvm_inject_page_fault(vcpu, &fault);
         }
         vcpu->arch.apf.halted = false;
+        vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
 }
 
 bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
diff --git a/arch/x86/platform/geode/net5501.c b/arch/x86/platform/geode/net5501.c
index 66d377e334f7..646e3b5b4bb6 100644
--- a/arch/x86/platform/geode/net5501.c
+++ b/arch/x86/platform/geode/net5501.c
@@ -63,7 +63,7 @@ static struct gpio_led net5501_leds[] = {
                 .name = "net5501:1",
                 .gpio = 6,
                 .default_trigger = "default-on",
-                .active_low = 1,
+                .active_low = 0,
         },
 };
 
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index e0a37233c0af..e31bcd8f2eee 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -805,7 +805,7 @@ void intel_scu_devices_create(void)
                 } else
                         i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
         }
-        intel_scu_notifier_post(SCU_AVAILABLE, 0L);
+        intel_scu_notifier_post(SCU_AVAILABLE, NULL);
 }
 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
 
@@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void)
 {
         int i;
 
-        intel_scu_notifier_post(SCU_DOWN, 0L);
+        intel_scu_notifier_post(SCU_DOWN, NULL);
 
         for (i = 0; i < ipc_next_dev; i++)
                 platform_device_del(ipc_devs[i]);
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index 4f51bebac02c..95dccce8e979 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -63,6 +63,7 @@
 #include <asm/stackprotector.h>
 #include <asm/hypervisor.h>
 #include <asm/mwait.h>
+#include <asm/pci_x86.h>
 
 #ifdef CONFIG_ACPI
 #include <linux/acpi.h>
@@ -261,7 +262,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
 
 static bool __init xen_check_mwait(void)
 {
-#ifdef CONFIG_ACPI
+#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \
+        !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE)
         struct xen_platform_op op = {
                 .cmd                    = XENPF_set_processor_pminfo,
                 .u.set_pminfo.id        = -1,
@@ -349,7 +351,6 @@ static void __init xen_init_cpuid_mask(void)
         /* Xen will set CR4.OSXSAVE if supported and not disabled by force */
         if ((cx & xsave_mask) != xsave_mask)
                 cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
-
         if (xen_check_mwait())
                 cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
 }
@@ -809,9 +810,40 @@ static void xen_io_delay(void)
 }
 
 #ifdef CONFIG_X86_LOCAL_APIC
+static unsigned long xen_set_apic_id(unsigned int x)
+{
+        WARN_ON(1);
+        return x;
+}
+static unsigned int xen_get_apic_id(unsigned long x)
+{
+        return ((x)>>24) & 0xFFu;
+}
 static u32 xen_apic_read(u32 reg)
 {
-        return 0;
+        struct xen_platform_op op = {
+                .cmd = XENPF_get_cpuinfo,
+                .interface_version = XENPF_INTERFACE_VERSION,
+                .u.pcpu_info.xen_cpuid = 0,
+        };
+        int ret = 0;
+
+        /* Shouldn't need this as APIC is turned off for PV, and we only
+         * get called on the bootup processor. But just in case. */
+        if (!xen_initial_domain() || smp_processor_id())
+                return 0;
+
+        if (reg == APIC_LVR)
+                return 0x10;
+
+        if (reg != APIC_ID)
+                return 0;
+
+        ret = HYPERVISOR_dom0_op(&op);
+        if (ret)
+                return 0;
+
+        return op.u.pcpu_info.apic_id << 24;
 }
 
 static void xen_apic_write(u32 reg, u32 val)
@@ -849,6 +881,8 @@ static void set_xen_basic_apic_ops(void)
         apic->icr_write = xen_apic_icr_write;
         apic->wait_icr_idle = xen_apic_wait_icr_idle;
         apic->safe_wait_icr_idle = xen_safe_apic_wait_icr_idle;
+        apic->set_apic_id = xen_set_apic_id;
+        apic->get_apic_id = xen_get_apic_id;
 }
 
 #endif
@@ -1365,8 +1399,10 @@ asmlinkage void __init xen_start_kernel(void)
                 /* Make sure ACS will be enabled */
                 pci_request_acs();
         }
-                
-
+#ifdef CONFIG_PCI
+        /* PCI BIOS service won't work from a PV guest. */
+        pci_probe &= ~PCI_PROBE_BIOS;
+#endif
         xen_raw_console_write("about to get started...\n");
 
         xen_setup_runstate_info(0);
diff --git a/arch/x86/xen/mmu.c b/arch/x86/xen/mmu.c
index b8e279479a6b..69f5857660ac 100644
--- a/arch/x86/xen/mmu.c
+++ b/arch/x86/xen/mmu.c
@@ -353,8 +353,13 @@ static pteval_t pte_mfn_to_pfn(pteval_t val)
 {
         if (val & _PAGE_PRESENT) {
                 unsigned long mfn = (val & PTE_PFN_MASK) >> PAGE_SHIFT;
+                unsigned long pfn = mfn_to_pfn(mfn);
+
                 pteval_t flags = val & PTE_FLAGS_MASK;
-                val = ((pteval_t)mfn_to_pfn(mfn) << PAGE_SHIFT) | flags;
+                if (unlikely(pfn == ~0))
+                        val = flags & ~_PAGE_PRESENT;
+                else
+                        val = ((pteval_t)pfn << PAGE_SHIFT) | flags;
         }
 
         return val;
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 5fac6919b957..0503c0c493a9 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void)
 static void __init xen_filter_cpu_maps(void)
 {
         int i, rc;
+        unsigned int subtract = 0;
 
         if (!xen_initial_domain())
                 return;
@@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void)
                 } else {
                         set_cpu_possible(i, false);
                         set_cpu_present(i, false);
+                        subtract++;
                 }
         }
+#ifdef CONFIG_HOTPLUG_CPU
+        /* This is akin to using 'nr_cpus' on the Linux command line.
+         * Which is OK as when we use 'dom0_max_vcpus=X' we can only
+         * have up to X, while nr_cpu_ids is greater than X. This
+         * normally is not a problem, except when CPU hotplugging
+         * is involved and then there might be more than X CPUs
+         * in the guest - which will not work as there is no
+         * hypercall to expand the max number of VCPUs an already
+         * running guest has. So cap it up to X. */
+        if (subtract)
+                nr_cpu_ids = nr_cpu_ids - subtract;
+#endif
+
 }
 
 static void __init xen_smp_prepare_boot_cpu(void)
diff --git a/arch/x86/xen/xen-asm.S b/arch/x86/xen/xen-asm.S
index 79d7362ad6d1..3e45aa000718 100644
--- a/arch/x86/xen/xen-asm.S
+++ b/arch/x86/xen/xen-asm.S
@@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct)
 
         /* check for unmasked and pending */
         cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
-        jz 1f
+        jnz 1f
 2:      call check_events
 1:
 ENDPATCH(xen_restore_fl_direct)
diff --git a/arch/xtensa/include/asm/hardirq.h b/arch/xtensa/include/asm/hardirq.h
index 26664cef8f11..91695a135498 100644
--- a/arch/xtensa/include/asm/hardirq.h
+++ b/arch/xtensa/include/asm/hardirq.h
@@ -11,9 +11,6 @@
 #ifndef _XTENSA_HARDIRQ_H
 #define _XTENSA_HARDIRQ_H
 
-void ack_bad_irq(unsigned int irq);
-#define ack_bad_irq ack_bad_irq
-
 #include <asm-generic/hardirq.h>
 
 #endif  /* _XTENSA_HARDIRQ_H */
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index d04cd3a625fa..4beb43c087d3 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -14,6 +14,7 @@
 #ifdef __KERNEL__
 #include <asm/byteorder.h>
 #include <asm/page.h>
+#include <linux/bug.h>
 #include <linux/kernel.h>
 
 #include <linux/types.h>
diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c
index b69b000349fc..d78869a00b11 100644
--- a/arch/xtensa/kernel/signal.c
+++ b/arch/xtensa/kernel/signal.c
@@ -496,6 +496,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
         signr = get_signal_to_deliver(&info, &ka, regs, NULL);
 
         if (signr > 0) {
+                int ret;
 
                 /* Are we from a system call? */