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author | Sascha Hauer <s.hauer@pengutronix.de> | 2010-03-19 06:12:02 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-03-19 06:18:27 -0400 |
commit | fc300206ad07e771ed003d35b1dc179eaf0c508f (patch) | |
tree | 639b0d7e9f642f57da5c4664ab65f271dea644a5 /arch | |
parent | 5443856cadac7faaaeefeed9d769f497a8c6fa4b (diff) |
i.MX51: remove NFC AXI static mapping
This area contains the Nand Flash controller registers. There
is no need to map them statically as the Nand driver uses ioremap().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx5/mm.c | 5 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 9 |
2 files changed, 2 insertions, 12 deletions
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 9fe7beb32dac..b7677ef80cc4 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c | |||
@@ -49,11 +49,6 @@ static struct map_desc mxc_io_desc[] __initdata = { | |||
49 | .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), | 49 | .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR), |
50 | .length = MX51_AIPS2_SIZE, | 50 | .length = MX51_AIPS2_SIZE, |
51 | .type = MT_DEVICE | 51 | .type = MT_DEVICE |
52 | }, { | ||
53 | .virtual = MX51_NFC_AXI_BASE_ADDR_VIRT, | ||
54 | .pfn = __phys_to_pfn(MX51_NFC_AXI_BASE_ADDR), | ||
55 | .length = MX51_NFC_AXI_SIZE, | ||
56 | .type = MT_DEVICE | ||
57 | }, | 52 | }, |
58 | }; | 53 | }; |
59 | 54 | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index fd255a9dbcdc..5aad344d5651 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
@@ -23,7 +23,7 @@ | |||
23 | * C8000000 64M CS3 Flash | 23 | * C8000000 64M CS3 Flash |
24 | * CC000000 32M CS4 SRAM | 24 | * CC000000 32M CS4 SRAM |
25 | * CE000000 32M CS5 SRAM | 25 | * CE000000 32M CS5 SRAM |
26 | * F9000000 CFFF0000 64K NFC (NAND Flash AXI) | 26 | * CFFF0000 64K NFC (NAND Flash AXI) |
27 | * | 27 | * |
28 | */ | 28 | */ |
29 | 29 | ||
@@ -46,7 +46,6 @@ | |||
46 | * NFC | 46 | * NFC |
47 | */ | 47 | */ |
48 | #define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ | 48 | #define MX51_NFC_AXI_BASE_ADDR 0xCFFF0000 /* NAND flash AXI */ |
49 | #define MX51_NFC_AXI_BASE_ADDR_VIRT 0xF9000000 | ||
50 | #define MX51_NFC_AXI_SIZE SZ_64K | 49 | #define MX51_NFC_AXI_SIZE SZ_64K |
51 | 50 | ||
52 | /* | 51 | /* |
@@ -240,8 +239,7 @@ | |||
240 | MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ | 239 | MX51_IS_MODULE(x, DEBUG) ? MX51_DEBUG_IO_ADDRESS(x) : \ |
241 | MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ | 240 | MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) : \ |
242 | MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ | 241 | MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) : \ |
243 | MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ | 242 | MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \ |
244 | MX51_IS_MODULE(x, NFC_AXI) ? MX51_NFC_AXI_IO_ADDRESS(x) : \ | ||
245 | 0xDEADBEEF) | 243 | 0xDEADBEEF) |
246 | 244 | ||
247 | /* | 245 | /* |
@@ -262,9 +260,6 @@ | |||
262 | #define MX51_AIPS2_IO_ADDRESS(x) \ | 260 | #define MX51_AIPS2_IO_ADDRESS(x) \ |
263 | (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) | 261 | (((x) - MX51_AIPS2_BASE_ADDR) + MX51_AIPS2_BASE_ADDR_VIRT) |
264 | 262 | ||
265 | #define MX51_NFC_AXI_IO_ADDRESS(x) \ | ||
266 | (((x) - MX51_NFC_AXI_BASE_ADDR) + MX51_NFC_AXI_BASE_ADDR_VIRT) | ||
267 | |||
268 | #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 | 263 | #define MX51_IS_MEM_DEVICE_NONSHARED(x) 0 |
269 | 264 | ||
270 | /* | 265 | /* |