Merge branch 'linus' into tracing/hw-breakpoints

Conflicts: arch/x86/kernel/process_64.c Semantic conflict fixed in: arch/x86/kvm/x86.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
author: Ingo Molnar <mingo@elte.hu> 2009-09-15 06:18:15 -0400
committer: Ingo Molnar <mingo@elte.hu> 2009-09-15 06:18:15 -0400
commit: dca2d6ac09d9ef59ff46820d4f0c94b08a671202 (patch)
tree: fdec753b842dad09e3a4151954fab3eb5c43500d /arch
parent: d6a65dffb30d8636b1e5d4c201564ef401a246cf (diff)
parent: 18240904960a39e582ced8ba8ececb10b8c22dd3 (diff)
855 files changed, 60466 insertions, 9801 deletions
diff --git a/arch/Kconfig b/arch/Kconfig
index c72f18fde319..8847f47aa82c 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -30,6 +30,18 @@ config OPROFILE_IBS
          If unsure, say N.
+config OPROFILE_EVENT_MULTIPLEX
+        bool "OProfile multiplexing support (EXPERIMENTAL)"
+        default n
+        depends on OPROFILE && X86
+        help
+          The number of hardware counters is limited. The multiplexing
+          feature enables OProfile to gather more events than counters
+          are provided by the hardware. This is realized by switching
+          between events at an user specified time interval.
+          If unsure, say N.
 config HAVE_OPROFILE
        bool
diff --git a/arch/alpha/include/asm/socket.h b/arch/alpha/include/asm/socket.h
index 3641ec1452f4..26773e3246e2 100644
--- a/arch/alpha/include/asm/socket.h
+++ b/arch/alpha/include/asm/socket.h
@@ -32,6 +32,8 @@
 #define SO_RCVTIMEO     0x1012
 #define SO_SNDTIMEO     0x1013
 #define SO_ACCEPTCONN   0x1014
+#define SO_PROTOCOL     0x1028
+#define SO_DOMAIN       0x1029
 /* linux-specific, might as well be the same as on i386 */
 #define SO_NO_CHECK     11
diff --git a/arch/alpha/include/asm/thread_info.h b/arch/alpha/include/asm/thread_info.h
index 60c83abfde70..5076a8860b18 100644
--- a/arch/alpha/include/asm/thread_info.h
+++ b/arch/alpha/include/asm/thread_info.h
@@ -75,6 +75,7 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define TIF_UAC_SIGBUS          7
 #define TIF_MEMDIE              8
 #define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal */
+#define TIF_NOTIFY_RESUME       10      /* callback before returning to user */
 #define TIF_FREEZE              16      /* is freezing for suspend */
 #define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
@@ -82,10 +83,12 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
 /* Work to do on interrupt/exception return.  */
-#define _TIF_WORK_MASK          (_TIF_SIGPENDING | _TIF_NEED_RESCHED)
+#define _TIF_WORK_MASK          (_TIF_SIGPENDING | _TIF_NEED_RESCHED | \
+                                 _TIF_NOTIFY_RESUME)
 /* Work to do on any return to userspace.  */
 #define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK         \
diff --git a/arch/alpha/kernel/signal.c b/arch/alpha/kernel/signal.c
index df65eaa84c4c..0932dbb1ef8e 100644
--- a/arch/alpha/kernel/signal.c
+++ b/arch/alpha/kernel/signal.c
@@ -20,6 +20,7 @@
 #include <linux/binfmts.h>
 #include <linux/bitops.h>
 #include <linux/syscalls.h>
+#include <linux/tracehook.h>
 #include <asm/uaccess.h>
 #include <asm/sigcontext.h>
@@ -683,4 +684,11 @@ do_notify_resume(struct pt_regs *regs, struct switch_stack *sw,
 {
        if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
                do_signal(regs, sw, r0, r19);
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index aef63c8e3d2d..d778a699f577 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -46,10 +46,6 @@ config GENERIC_CLOCKEVENTS_BROADCAST
        depends on GENERIC_CLOCKEVENTS
        default y if SMP && !LOCAL_TIMERS
-config MMU
-        bool
-        default y
 config NO_IOPORT
        bool
@@ -126,6 +122,13 @@ config ARCH_HAS_ILOG2_U32
 config ARCH_HAS_ILOG2_U64
        bool
+config ARCH_HAS_CPUFREQ
+        bool
+        help
+          Internal node to signify that the ARCH has CPUFREQ support
+          and that the relevant menu configurations are displayed for
+          it.
 config GENERIC_HWEIGHT
        bool
        default y
@@ -188,6 +191,13 @@ source "kernel/Kconfig.freezer"
 menu "System Type"
+config MMU
+        bool "MMU-based Paged Memory Management Support"
+        default y
+        help
+          Select if you want MMU-based virtualised addressing space
+          support by paged memory management. If unsure, say 'Y'.
 choice
        prompt "ARM system type"
        default ARCH_VERSATILE
@@ -203,6 +213,7 @@ config ARCH_AAEC2000
 config ARCH_INTEGRATOR
        bool "ARM Ltd. Integrator family"
        select ARM_AMBA
+        select ARCH_HAS_CPUFREQ
        select HAVE_CLK
        select COMMON_CLKDEV
        select ICST525
@@ -217,6 +228,7 @@ config ARCH_REALVIEW
        select ICST307
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
        help
          This enables support for ARM Ltd RealView boards.
@@ -229,6 +241,7 @@ config ARCH_VERSATILE
        select ICST307
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
        help
          This enables support for ARM Ltd Versatile board.
@@ -327,6 +340,20 @@ config ARCH_H720X
        help
          This enables support for systems based on the Hynix HMS720x
+config ARCH_NOMADIK
+        bool "STMicroelectronics Nomadik"
+        select ARM_AMBA
+        select ARM_VIC
+        select CPU_ARM926T
+        select HAVE_CLK
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select GENERIC_GPIO
+        select ARCH_REQUIRE_GPIOLIB
+        help
+          Support for the Nomadik platform by ST-Ericsson
 config ARCH_IOP13XX
        bool "IOP13xx-based"
        depends on MMU
@@ -493,10 +520,18 @@ config ARCH_W90X900
        select CPU_ARM926T
        select ARCH_REQUIRE_GPIOLIB
        select GENERIC_GPIO
+        select HAVE_CLK
        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
        help
-                Support for Nuvoton (Winbond logic dept.) ARM9 processor,You
+          Support for Nuvoton (Winbond logic dept.) ARM9 processor,
-                can login www.mcuos.com or www.nuvoton.com to know more.
+          At present, the w90x900 has been renamed nuc900, regarding
+          the ARM series product line, you can login the following
+          link address to know more.
+          <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
+                ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
 config ARCH_PNX4008
        bool "Philips Nexperia PNX4008 Mobile"
@@ -509,6 +544,7 @@ config ARCH_PXA
        bool "PXA2xx/PXA3xx-based"
        depends on MMU
        select ARCH_MTD_XIP
+        select ARCH_HAS_CPUFREQ
        select GENERIC_GPIO
        select HAVE_CLK
        select COMMON_CLKDEV
@@ -551,6 +587,7 @@ config ARCH_SA1100
        select ISA
        select ARCH_SPARSEMEM_ENABLE
        select ARCH_MTD_XIP
+        select ARCH_HAS_CPUFREQ
        select GENERIC_GPIO
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
@@ -563,6 +600,7 @@ config ARCH_SA1100
 config ARCH_S3C2410
        bool "Samsung S3C2410, S3C2412, S3C2413, S3C2440, S3C2442, S3C2443"
        select GENERIC_GPIO
+        select ARCH_HAS_CPUFREQ
        select HAVE_CLK
        help
          Samsung S3C2410X CPU based systems, such as the Simtec Electronics
@@ -573,9 +611,18 @@ config ARCH_S3C64XX
        bool "Samsung S3C64XX"
        select GENERIC_GPIO
        select HAVE_CLK
+        select ARCH_HAS_CPUFREQ
        help
          Samsung S3C64XX series based systems
+config ARCH_S5PC1XX
+        bool "Samsung S5PC1XX"
+        select GENERIC_GPIO
+        select HAVE_CLK
+        select CPU_V7
+        help
+          Samsung S5PC1XX series based systems
 config ARCH_SHARK
        bool "Shark"
        select CPU_SA110
@@ -632,11 +679,24 @@ config ARCH_OMAP
        select GENERIC_GPIO
        select HAVE_CLK
        select ARCH_REQUIRE_GPIOLIB
+        select ARCH_HAS_CPUFREQ
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
        help
          Support for TI's OMAP platform (OMAP1 and OMAP2).
+config ARCH_BCMRING
+        bool "Broadcom BCMRING"
+        depends on MMU
+        select CPU_V6
+        select ARM_AMBA
+        select COMMON_CLKDEV
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
+        select ARCH_WANT_OPTIONAL_GPIOLIB
+        help
+          Support for Broadcom's BCMRing platform.
 endchoice
 source "arch/arm/mach-clps711x/Kconfig"
@@ -685,6 +745,7 @@ source "arch/arm/mach-kirkwood/Kconfig"
 source "arch/arm/plat-s3c24xx/Kconfig"
 source "arch/arm/plat-s3c64xx/Kconfig"
 source "arch/arm/plat-s3c/Kconfig"
+source "arch/arm/plat-s5pc1xx/Kconfig"
 if ARCH_S3C2410
 source "arch/arm/mach-s3c2400/Kconfig"
@@ -702,6 +763,10 @@ endif
 source "arch/arm/plat-stmp3xxx/Kconfig"
+if ARCH_S5PC1XX
+source "arch/arm/mach-s5pc100/Kconfig"
+endif
 source "arch/arm/mach-lh7a40x/Kconfig"
 source "arch/arm/mach-h720x/Kconfig"
@@ -716,6 +781,8 @@ source "arch/arm/mach-at91/Kconfig"
 source "arch/arm/plat-mxc/Kconfig"
+source "arch/arm/mach-nomadik/Kconfig"
 source "arch/arm/mach-netx/Kconfig"
 source "arch/arm/mach-ns9xxx/Kconfig"
@@ -730,6 +797,8 @@ source "arch/arm/mach-u300/Kconfig"
 source "arch/arm/mach-w90x900/Kconfig"
+source "arch/arm/mach-bcmring/Kconfig"
 # Definitions to make life easier
 config ARCH_ACORN
        bool
@@ -962,18 +1031,7 @@ config LOCAL_TIMERS
          accounting to be spread across the timer interval, preventing a
          "thundering herd" at every timer tick.
-config PREEMPT
+source kernel/Kconfig.preempt
-        bool "Preemptible Kernel (EXPERIMENTAL)"
-        depends on EXPERIMENTAL
-        help
-          This option reduces the latency of the kernel when reacting to
-          real-time or interactive events by allowing a low priority process to
-          be preempted even if it is in kernel mode executing a system call.
-          This allows applications to run more reliably even when the system is
-          under load.
-          Say Y here if you are building a kernel for a desktop, embedded
-          or real-time system.  Say N if you are unsure.
 config HZ
        int
@@ -983,6 +1041,21 @@ config HZ
        default AT91_TIMER_HZ if ARCH_AT91
        default 100
+config THUMB2_KERNEL
+        bool "Compile the kernel in Thumb-2 mode"
+        depends on CPU_V7 && EXPERIMENTAL
+        select AEABI
+        select ARM_ASM_UNIFIED
+        help
+          By enabling this option, the kernel will be compiled in
+          Thumb-2 mode. A compiler/assembler that understand the unified
+          ARM-Thumb syntax is needed.
+          If unsure, say N.
+config ARM_ASM_UNIFIED
+        bool
 config AEABI
        bool "Use the ARM EABI to compile the kernel"
        help
@@ -1054,6 +1127,11 @@ config HIGHMEM
          If unsure, say n.
+config HIGHPTE
+        bool "Allocate 2nd-level pagetables from highmem"
+        depends on HIGHMEM
+        depends on !OUTER_CACHE
 source "mm/Kconfig"
 config LEDS
@@ -1241,7 +1319,7 @@ endmenu
 menu "CPU Power Management"
-if (ARCH_SA1100 || ARCH_INTEGRATOR || ARCH_OMAP || ARCH_PXA || ARCH_S3C64XX)
+if ARCH_HAS_CPUFREQ
 source "drivers/cpufreq/Kconfig"
@@ -1276,6 +1354,52 @@ config CPU_FREQ_S3C64XX
        bool "CPUfreq support for Samsung S3C64XX CPUs"
        depends on CPU_FREQ && CPU_S3C6410
+config CPU_FREQ_S3C
+        bool
+        help
+          Internal configuration node for common cpufreq on Samsung SoC
+config CPU_FREQ_S3C24XX
+        bool "CPUfreq driver for Samsung S3C24XX series CPUs"
+        depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
+        select CPU_FREQ_S3C
+        help
+          This enables the CPUfreq driver for the Samsung S3C24XX family
+          of CPUs.
+          For details, take a look at <file:Documentation/cpu-freq>.
+          If in doubt, say N.
+config CPU_FREQ_S3C24XX_PLL
+        bool "Support CPUfreq changing of PLL frequency"
+        depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
+        help
+          Compile in support for changing the PLL frequency from the
+          S3C24XX series CPUfreq driver. The PLL takes time to settle
+          after a frequency change, so by default it is not enabled.
+          This also means that the PLL tables for the selected CPU(s) will
+          be built which may increase the size of the kernel image.
+config CPU_FREQ_S3C24XX_DEBUG
+        bool "Debug CPUfreq Samsung driver core"
+        depends on CPU_FREQ_S3C24XX
+        help
+          Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
+config CPU_FREQ_S3C24XX_IODEBUG
+        bool "Debug CPUfreq Samsung driver IO timing"
+        depends on CPU_FREQ_S3C24XX
+        help
+          Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
+config CPU_FREQ_S3C24XX_DEBUGFS
+        bool "Export debugfs for CPUFreq"
+        depends on CPU_FREQ_S3C24XX && DEBUG_FS
+        help
+          Export status information via debugfs.
 endif
 source "drivers/cpuidle/Kconfig"
@@ -1377,107 +1501,7 @@ endmenu
 source "net/Kconfig"
-menu "Device Drivers"
+source "drivers/Kconfig"
-source "drivers/base/Kconfig"
-source "drivers/connector/Kconfig"
-if ALIGNMENT_TRAP || !CPU_CP15_MMU
-source "drivers/mtd/Kconfig"
-endif
-source "drivers/parport/Kconfig"
-source "drivers/pnp/Kconfig"
-source "drivers/block/Kconfig"
-# misc before ide - BLK_DEV_SGIIOC4 depends on SGI_IOC4
-source "drivers/misc/Kconfig"
-source "drivers/ide/Kconfig"
-source "drivers/scsi/Kconfig"
-source "drivers/ata/Kconfig"
-source "drivers/md/Kconfig"
-source "drivers/message/fusion/Kconfig"
-source "drivers/ieee1394/Kconfig"
-source "drivers/message/i2o/Kconfig"
-source "drivers/net/Kconfig"
-source "drivers/isdn/Kconfig"
-# input before char - char/joystick depends on it. As does USB.
-source "drivers/input/Kconfig"
-source "drivers/char/Kconfig"
-source "drivers/i2c/Kconfig"
-source "drivers/spi/Kconfig"
-source "drivers/gpio/Kconfig"
-source "drivers/w1/Kconfig"
-source "drivers/power/Kconfig"
-source "drivers/hwmon/Kconfig"
-source "drivers/thermal/Kconfig"
-source "drivers/watchdog/Kconfig"
-source "drivers/ssb/Kconfig"
-#source "drivers/l3/Kconfig"
-source "drivers/mfd/Kconfig"
-source "drivers/media/Kconfig"
-source "drivers/video/Kconfig"
-source "sound/Kconfig"
-source "drivers/hid/Kconfig"
-source "drivers/usb/Kconfig"
-source "drivers/uwb/Kconfig"
-source "drivers/mmc/Kconfig"
-source "drivers/memstick/Kconfig"
-source "drivers/accessibility/Kconfig"
-source "drivers/leds/Kconfig"
-source "drivers/rtc/Kconfig"
-source "drivers/dma/Kconfig"
-source "drivers/dca/Kconfig"
-source "drivers/auxdisplay/Kconfig"
-source "drivers/regulator/Kconfig"
-source "drivers/uio/Kconfig"
-source "drivers/staging/Kconfig"
-endmenu
 source "fs/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index a89e4734b8f0..1a6f70e52921 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -8,6 +8,7 @@ source "lib/Kconfig.debug"
 # n, but then RMK will have to kill you ;).
 config FRAME_POINTER
        bool
+        depends on !THUMB2_KERNEL
        default y if !ARM_UNWIND
        help
          If you say N here, the resulting kernel will be slightly smaller and
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c877d6df23d1..7350557a81e0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -93,9 +93,16 @@ ifeq ($(CONFIG_ARM_UNWIND),y)
 CFLAGS_ABI      +=-funwind-tables
 endif
+ifeq ($(CONFIG_THUMB2_KERNEL),y)
+AFLAGS_AUTOIT   :=$(call as-option,-Wa$(comma)-mimplicit-it=thumb,-Wa$(comma)-mauto-it)
+AFLAGS_NOWARN   :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W)
+CFLAGS_THUMB2   :=-mthumb $(AFLAGS_AUTOIT) $(AFLAGS_NOWARN)
+AFLAGS_THUMB2   :=$(CFLAGS_THUMB2) -Wa$(comma)-mthumb
+endif
 # Need -Uarm for gcc < 3.x
-KBUILD_CFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
+KBUILD_CFLAGS   +=$(CFLAGS_ABI) $(CFLAGS_THUMB2) $(arch-y) $(tune-y) $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,)) -msoft-float -Uarm
-KBUILD_AFLAGS   +=$(CFLAGS_ABI) $(arch-y) $(tune-y) -msoft-float
+KBUILD_AFLAGS   +=$(CFLAGS_ABI) $(AFLAGS_THUMB2) $(arch-y) $(tune-y) -include asm/unified.h -msoft-float
 CHECKFLAGS      += -D__arm__
@@ -112,6 +119,7 @@ endif
 # by CONFIG_* macro name.
 machine-$(CONFIG_ARCH_AAEC2000)         := aaec2000
 machine-$(CONFIG_ARCH_AT91)             := at91
+machine-$(CONFIG_ARCH_BCMRING)          := bcmring
 machine-$(CONFIG_ARCH_CLPS711X)         := clps711x
 machine-$(CONFIG_ARCH_DAVINCI)          := davinci
 machine-$(CONFIG_ARCH_EBSA110)          := ebsa110
@@ -135,8 +143,10 @@ machine-$(CONFIG_ARCH_MSM)		:= msm
 machine-$(CONFIG_ARCH_MV78XX0)          := mv78xx0
 machine-$(CONFIG_ARCH_MX1)              := mx1
 machine-$(CONFIG_ARCH_MX2)              := mx2
+machine-$(CONFIG_ARCH_MX25)             := mx25
 machine-$(CONFIG_ARCH_MX3)              := mx3
 machine-$(CONFIG_ARCH_NETX)             := netx
+machine-$(CONFIG_ARCH_NOMADIK)          := nomadik
 machine-$(CONFIG_ARCH_NS9XXX)           := ns9xxx
 machine-$(CONFIG_ARCH_OMAP1)            := omap1
 machine-$(CONFIG_ARCH_OMAP2)            := omap2
@@ -150,6 +160,7 @@ machine-$(CONFIG_ARCH_RPC)		:= rpc
 machine-$(CONFIG_ARCH_S3C2410)          := s3c2410 s3c2400 s3c2412 s3c2440 s3c2442 s3c2443
 machine-$(CONFIG_ARCH_S3C24A0)          := s3c24a0
 machine-$(CONFIG_ARCH_S3C64XX)          := s3c6400 s3c6410
+machine-$(CONFIG_ARCH_S5PC1XX)          := s5pc100
 machine-$(CONFIG_ARCH_SA1100)           := sa1100
 machine-$(CONFIG_ARCH_SHARK)            := shark
 machine-$(CONFIG_ARCH_STMP378X)         := stmp378x
@@ -158,6 +169,7 @@ machine-$(CONFIG_ARCH_U300)		:= u300
 machine-$(CONFIG_ARCH_VERSATILE)        := versatile
 machine-$(CONFIG_ARCH_W90X900)          := w90x900
 machine-$(CONFIG_FOOTBRIDGE)            := footbridge
+machine-$(CONFIG_ARCH_MXC91231)         := mxc91231
 # Platform directory name.  This list is sorted alphanumerically
 # by CONFIG_* macro name.
@@ -168,6 +180,7 @@ plat-$(CONFIG_PLAT_ORION)	:= orion
 plat-$(CONFIG_PLAT_PXA)         := pxa
 plat-$(CONFIG_PLAT_S3C24XX)     := s3c24xx s3c
 plat-$(CONFIG_PLAT_S3C64XX)     := s3c64xx s3c
+plat-$(CONFIG_PLAT_S5PC1XX)     := s5pc1xx s3c
 plat-$(CONFIG_ARCH_STMP3XXX)    := stmp3xxx
 ifeq ($(CONFIG_ARCH_EBSA110),y)
diff --git a/arch/arm/boot/Makefile b/arch/arm/boot/Makefile
index da226abce2d0..4a590f4113e2 100644
--- a/arch/arm/boot/Makefile
+++ b/arch/arm/boot/Makefile
@@ -61,7 +61,7 @@ endif
 quiet_cmd_uimage = UIMAGE  $@
      cmd_uimage = $(CONFIG_SHELL) $(MKIMAGE) -A arm -O linux -T kernel \
-                   -C none -a $(LOADADDR) -e $(LOADADDR) \
+                   -C none -a $(LOADADDR) -e $(STARTADDR) \
                   -n 'Linux-$(KERNELRELEASE)' -d $< $@
 ifeq ($(CONFIG_ZBOOT_ROM),y)
@@ -70,6 +70,13 @@ else
 $(obj)/uImage: LOADADDR=$(ZRELADDR)
 endif
+ifeq ($(CONFIG_THUMB2_KERNEL),y)
+# Set bit 0 to 1 so that "mov pc, rx" switches to Thumb-2 mode
+$(obj)/uImage: STARTADDR=$(shell echo $(LOADADDR) | sed -e "s/.$$/1/")
+else
+$(obj)/uImage: STARTADDR=$(LOADADDR)
+endif
 $(obj)/uImage:  $(obj)/zImage FORCE
        $(call if_changed,uimage)
        @echo '  Image $@ is ready'
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 4515728c5345..fa6fbf45cf3b 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -140,7 +140,8 @@ start:
                tst     r2, #3                  @ not user?
                bne     not_angel
                mov     r0, #0x17               @ angel_SWIreason_EnterSVC
-                swi     0x123456                @ angel_SWI_ARM
+ ARM(           swi     0x123456        )       @ angel_SWI_ARM
+ THUMB(         svc     0xab            )       @ angel_SWI_THUMB
 not_angel:
                mrs     r2, cpsr                @ turn off interrupts to
                orr     r2, r2, #0xc0           @ prevent angel from running
@@ -161,7 +162,9 @@ not_angel:
                .text
                adr     r0, LC0
-                ldmia   r0, {r1, r2, r3, r4, r5, r6, ip, sp}
+ ARM(           ldmia   r0, {r1, r2, r3, r4, r5, r6, ip, sp}    )
+ THUMB(         ldmia   r0, {r1, r2, r3, r4, r5, r6, ip}        )
+ THUMB(         ldr     sp, [r0, #28]                           )
                subs    r0, r0, r1              @ calculate the delta offset
                                                @ if delta is zero, we are
@@ -263,22 +266,25 @@ not_relocated:	mov	r0, #0
 * r6     = processor ID
 * r7     = architecture ID
 * r8     = atags pointer
- * r9-r14 = corrupted
+ * r9-r12,r14 = corrupted
 */
                add     r1, r5, r0              @ end of decompressed kernel
                adr     r2, reloc_start
                ldr     r3, LC1
                add     r3, r2, r3
-1:              ldmia   r2!, {r9 - r14}         @ copy relocation code
+1:              ldmia   r2!, {r9 - r12, r14}    @ copy relocation code
-                stmia   r1!, {r9 - r14}
+                stmia   r1!, {r9 - r12, r14}
-                ldmia   r2!, {r9 - r14}
+                ldmia   r2!, {r9 - r12, r14}
-                stmia   r1!, {r9 - r14}
+                stmia   r1!, {r9 - r12, r14}
                cmp     r2, r3
                blo     1b
-                add     sp, r1, #128            @ relocate the stack
+                mov     sp, r1
+                add     sp, sp, #128            @ relocate the stack
                bl      cache_clean_flush
-                add     pc, r5, r0              @ call relocation code
+ ARM(           add     pc, r5, r0              ) @ call relocation code
+ THUMB(         add     r12, r5, r0             )
+ THUMB(         mov     pc, r12                 ) @ call relocation code
 /*
 * We're not in danger of overwriting ourselves.  Do this the simple way.
@@ -291,6 +297,7 @@ wont_overwrite:	mov	r0, r4
                bl      decompress_kernel
                b       call_kernel
+                .align  2
                .type   LC0, #object
 LC0:            .word   LC0                     @ r1
                .word   __bss_start             @ r2
@@ -431,6 +438,7 @@ ENDPROC(__setup_mmu)
 __armv4_mmu_cache_on:
                mov     r12, lr
+#ifdef CONFIG_MMU
                bl      __setup_mmu
                mov     r0, #0
                mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
@@ -444,10 +452,12 @@ __armv4_mmu_cache_on:
                bl      __common_mmu_cache_on
                mov     r0, #0
                mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
+#endif
                mov     pc, r12
 __armv7_mmu_cache_on:
                mov     r12, lr
+#ifdef CONFIG_MMU
                mrc     p15, 0, r11, c0, c1, 4  @ read ID_MMFR0
                tst     r11, #0xf               @ VMSA
                blne    __setup_mmu
@@ -455,9 +465,11 @@ __armv7_mmu_cache_on:
                mcr     p15, 0, r0, c7, c10, 4  @ drain write buffer
                tst     r11, #0xf               @ VMSA
                mcrne   p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
+#endif
                mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                orr     r0, r0, #0x003c         @ write buffer
+#ifdef CONFIG_MMU
 #ifdef CONFIG_CPU_ENDIAN_BE8
                orr     r0, r0, #1 << 25        @ big-endian page tables
 #endif
@@ -465,6 +477,7 @@ __armv7_mmu_cache_on:
                movne   r1, #-1
                mcrne   p15, 0, r3, c2, c0, 0   @ load page table pointer
                mcrne   p15, 0, r1, c3, c0, 0   @ load domain access control
+#endif
                mcr     p15, 0, r0, c1, c0, 0   @ load control register
                mrc     p15, 0, r0, c1, c0, 0   @ and read it back
                mov     r0, #0
@@ -498,6 +511,7 @@ __arm6_mmu_cache_on:
                mov     pc, r12
 __common_mmu_cache_on:
+#ifndef CONFIG_THUMB2_KERNEL
 #ifndef DEBUG
                orr     r0, r0, #0x000d         @ Write buffer, mmu
 #endif
@@ -509,6 +523,7 @@ __common_mmu_cache_on:
 1:              mcr     p15, 0, r0, c1, c0, 0   @ load control register
                mrc     p15, 0, r0, c1, c0, 0   @ and read it back to
                sub     pc, lr, r0, lsr #32     @ properly flush pipeline
+#endif
 /*
 * All code following this line is relocatable.  It is relocated by
@@ -522,7 +537,7 @@ __common_mmu_cache_on:
 * r6     = processor ID
 * r7     = architecture ID
 * r8     = atags pointer
- * r9-r14 = corrupted
+ * r9-r12,r14 = corrupted
 */
                .align  5
 reloc_start:    add     r9, r5, r0
@@ -531,13 +546,14 @@ reloc_start:	add	r9, r5, r0
                mov     r1, r4
 1:
                .rept   4
-                ldmia   r5!, {r0, r2, r3, r10 - r14}    @ relocate kernel
+                ldmia   r5!, {r0, r2, r3, r10 - r12, r14}       @ relocate kernel
-                stmia   r1!, {r0, r2, r3, r10 - r14}
+                stmia   r1!, {r0, r2, r3, r10 - r12, r14}
                .endr
                cmp     r5, r9
                blo     1b
-                add     sp, r1, #128            @ relocate the stack
+                mov     sp, r1
+                add     sp, sp, #128            @ relocate the stack
                debug_reloc_end
 call_kernel:    bl      cache_clean_flush
@@ -571,7 +587,9 @@ call_cache_fn:	adr	r12, proc_types
                ldr     r2, [r12, #4]           @ get mask
                eor     r1, r1, r6              @ (real ^ match)
                tst     r1, r2                  @       & mask
-                addeq   pc, r12, r3             @ call cache function
+ ARM(           addeq   pc, r12, r3             ) @ call cache function
+ THUMB(         addeq   r12, r3                 )
+ THUMB(         moveq   pc, r12                 ) @ call cache function
                add     r12, r12, #4*5
                b       1b
@@ -589,13 +607,15 @@ call_cache_fn:	adr	r12, proc_types
 * methods.  Writeback caches _must_ have the flush method
 * defined.
 */
+                .align  2
                .type   proc_types,#object
 proc_types:
                .word   0x41560600              @ ARM6/610
                .word   0xffffffe0
-                b       __arm6_mmu_cache_off    @ works, but slow
+                W(b)    __arm6_mmu_cache_off    @ works, but slow
-                b       __arm6_mmu_cache_off
+                W(b)    __arm6_mmu_cache_off
                mov     pc, lr
+ THUMB(         nop                             )
 @               b       __arm6_mmu_cache_on             @ untested
 @               b       __arm6_mmu_cache_off
 @               b       __armv3_mmu_cache_flush
@@ -603,76 +623,84 @@ proc_types:
                .word   0x00000000              @ old ARM ID
                .word   0x0000f000
                mov     pc, lr
+ THUMB(         nop                             )
                mov     pc, lr
+ THUMB(         nop                             )
                mov     pc, lr
+ THUMB(         nop                             )
                .word   0x41007000              @ ARM7/710
                .word   0xfff8fe00
-                b       __arm7_mmu_cache_off
+                W(b)    __arm7_mmu_cache_off
-                b       __arm7_mmu_cache_off
+                W(b)    __arm7_mmu_cache_off
                mov     pc, lr
+ THUMB(         nop                             )
                .word   0x41807200              @ ARM720T (writethrough)
                .word   0xffffff00
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
                mov     pc, lr
+ THUMB(         nop                             )
                .word   0x41007400              @ ARM74x
                .word   0xff00ff00
-                b       __armv3_mpu_cache_on
+                W(b)    __armv3_mpu_cache_on
-                b       __armv3_mpu_cache_off
+                W(b)    __armv3_mpu_cache_off
-                b       __armv3_mpu_cache_flush
+                W(b)    __armv3_mpu_cache_flush
                
                .word   0x41009400              @ ARM94x
                .word   0xff00ff00
-                b       __armv4_mpu_cache_on
+                W(b)    __armv4_mpu_cache_on
-                b       __armv4_mpu_cache_off
+                W(b)    __armv4_mpu_cache_off
-                b       __armv4_mpu_cache_flush
+                W(b)    __armv4_mpu_cache_flush
                .word   0x00007000              @ ARM7 IDs
                .word   0x0000f000
                mov     pc, lr
+ THUMB(         nop                             )
                mov     pc, lr
+ THUMB(         nop                             )
                mov     pc, lr
+ THUMB(         nop                             )
                @ Everything from here on will be the new ID system.
                .word   0x4401a100              @ sa110 / sa1100
                .word   0xffffffe0
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_flush
                .word   0x6901b110              @ sa1110
                .word   0xfffffff0
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_flush
                .word   0x56056930
                .word   0xff0ffff0              @ PXA935
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_flush
                .word   0x56158000              @ PXA168
                .word   0xfffff000
-                b __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b __armv5tej_mmu_cache_flush
+                W(b)    __armv5tej_mmu_cache_flush
                .word   0x56056930
                .word   0xff0ffff0              @ PXA935
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_flush
                .word   0x56050000              @ Feroceon
                .word   0xff0f0000
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv5tej_mmu_cache_flush
+                W(b)    __armv5tej_mmu_cache_flush
 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
                /* this conflicts with the standard ARMv5TE entry */
@@ -685,47 +713,50 @@ proc_types:
                .word   0x66015261              @ FA526
                .word   0xff01fff1
-                b       __fa526_cache_on
+                W(b)    __fa526_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __fa526_cache_flush
+                W(b)    __fa526_cache_flush
                @ These match on the architecture ID
                .word   0x00020000              @ ARMv4T
                .word   0x000f0000
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_flush
                .word   0x00050000              @ ARMv5TE
                .word   0x000f0000
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv4_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_flush
                .word   0x00060000              @ ARMv5TEJ
                .word   0x000f0000
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv5tej_mmu_cache_flush
+                W(b)    __armv4_mmu_cache_flush
                .word   0x0007b000              @ ARMv6
                .word   0x000ff000
-                b       __armv4_mmu_cache_on
+                W(b)    __armv4_mmu_cache_on
-                b       __armv4_mmu_cache_off
+                W(b)    __armv4_mmu_cache_off
-                b       __armv6_mmu_cache_flush
+                W(b)    __armv6_mmu_cache_flush
                .word   0x000f0000              @ new CPU Id
                .word   0x000f0000
-                b       __armv7_mmu_cache_on
+                W(b)    __armv7_mmu_cache_on
-                b       __armv7_mmu_cache_off
+                W(b)    __armv7_mmu_cache_off
-                b       __armv7_mmu_cache_flush
+                W(b)    __armv7_mmu_cache_flush
                .word   0                       @ unrecognised type
                .word   0
                mov     pc, lr
+ THUMB(         nop                             )
                mov     pc, lr
+ THUMB(         nop                             )
                mov     pc, lr
+ THUMB(         nop                             )
                .size   proc_types, . - proc_types
@@ -760,22 +791,30 @@ __armv3_mpu_cache_off:
                mov     pc, lr
 __armv4_mmu_cache_off:
+#ifdef CONFIG_MMU
                mrc     p15, 0, r0, c1, c0
                bic     r0, r0, #0x000d
                mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
                mov     r0, #0
                mcr     p15, 0, r0, c7, c7      @ invalidate whole cache v4
                mcr     p15, 0, r0, c8, c7      @ invalidate whole TLB v4
+#endif
                mov     pc, lr
 __armv7_mmu_cache_off:
                mrc     p15, 0, r0, c1, c0
+#ifdef CONFIG_MMU
                bic     r0, r0, #0x000d
+#else
+                bic     r0, r0, #0x000c
+#endif
                mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
                mov     r12, lr
                bl      __armv7_mmu_cache_flush
                mov     r0, #0
+#ifdef CONFIG_MMU
                mcr     p15, 0, r0, c8, c7, 0   @ invalidate whole TLB
+#endif
                mcr     p15, 0, r0, c7, c5, 6   @ invalidate BTC
                mcr     p15, 0, r0, c7, c10, 4  @ DSB
                mcr     p15, 0, r0, c7, c5, 4   @ ISB
@@ -852,7 +891,7 @@ __armv7_mmu_cache_flush:
                b       iflush
 hierarchical:
                mcr     p15, 0, r10, c7, c10, 5 @ DMB
-                stmfd   sp!, {r0-r5, r7, r9, r11}
+                stmfd   sp!, {r0-r7, r9-r11}
                mrc     p15, 1, r0, c0, c0, 1   @ read clidr
                ands    r3, r0, #0x7000000      @ extract loc from clidr
                mov     r3, r3, lsr #23         @ left align loc bit field
@@ -877,8 +916,12 @@ loop1:
 loop2:
                mov     r9, r4                  @ create working copy of max way size
 loop3:
-                orr     r11, r10, r9, lsl r5    @ factor way and cache number into r11
+ ARM(           orr     r11, r10, r9, lsl r5    ) @ factor way and cache number into r11
-                orr     r11, r11, r7, lsl r2    @ factor index number into r11
+ ARM(           orr     r11, r11, r7, lsl r2    ) @ factor index number into r11
+ THUMB(         lsl     r6, r9, r5              )
+ THUMB(         orr     r11, r10, r6            ) @ factor way and cache number into r11
+ THUMB(         lsl     r6, r7, r2              )
+ THUMB(         orr     r11, r11, r6            ) @ factor index number into r11
                mcr     p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
                subs    r9, r9, #1              @ decrement the way
                bge     loop3
@@ -889,7 +932,7 @@ skip:
                cmp     r3, r10
                bgt     loop1
 finished:
-                ldmfd   sp!, {r0-r5, r7, r9, r11}
+                ldmfd   sp!, {r0-r7, r9-r11}
                mov     r10, #0                 @ swith back to cache level 0
                mcr     p15, 2, r10, c0, c0, 0  @ select current cache level in cssr
 iflush:
@@ -923,9 +966,13 @@ __armv4_mmu_cache_flush:
                mov     r11, #8
                mov     r11, r11, lsl r3        @ cache line size in bytes
 no_cache_id:
-                bic     r1, pc, #63             @ align to longest cache line
+                mov     r1, pc
+                bic     r1, r1, #63             @ align to longest cache line
                add     r2, r1, r2
-1:              ldr     r3, [r1], r11           @ s/w flush D cache
+1:
+ ARM(           ldr     r3, [r1], r11           ) @ s/w flush D cache
+ THUMB(         ldr     r3, [r1]                ) @ s/w flush D cache
+ THUMB(         add     r1, r1, r11             )
                teq     r1, r2
                bne     1b
@@ -945,6 +992,7 @@ __armv3_mpu_cache_flush:
 * memory, which again must be relocatable.
 */
 #ifdef DEBUG
+                .align  2
                .type   phexbuf,#object
 phexbuf:        .space  12
                .size   phexbuf, . - phexbuf
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index 6ed89836e908..920ced0b73c5 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -22,10 +22,20 @@
 #include <linux/list.h>
 #include <linux/io.h>
 #include <linux/sysdev.h>
+#include <linux/amba/bus.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/vic.h>
+static void vic_ack_irq(unsigned int irq)
+{
+        void __iomem *base = get_irq_chip_data(irq);
+        irq &= 31;
+        writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
+        /* moreover, clear the soft-triggered, in case it was the reason */
+        writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
+}
 static void vic_mask_irq(unsigned int irq)
 {
        void __iomem *base = get_irq_chip_data(irq);
@@ -253,12 +263,16 @@ static inline void vic_pm_register(void __iomem *base, unsigned int irq, u32 arg
 static struct irq_chip vic_chip = {
        .name   = "VIC",
-        .ack    = vic_mask_irq,
+        .ack    = vic_ack_irq,
        .mask   = vic_mask_irq,
        .unmask = vic_unmask_irq,
        .set_wake = vic_set_wake,
 };
+/* The PL190 cell from ARM has been modified by ST, so handle both here */
+static void vik_init_st(void __iomem *base, unsigned int irq_start,
+                         u32 vic_sources);
 /**
 * vic_init - initialise a vectored interrupt controller
 * @base: iomem base address
@@ -270,6 +284,28 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
                     u32 vic_sources, u32 resume_sources)
 {
        unsigned int i;
+        u32 cellid = 0;
+        enum amba_vendor vendor;
+        /* Identify which VIC cell this one is, by reading the ID */
+        for (i = 0; i < 4; i++) {
+                u32 addr = ((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
+                cellid |= (readl(addr) & 0xff) << (8 * i);
+        }
+        vendor = (cellid >> 12) & 0xff;
+        printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
+               base, cellid, vendor);
+        switch(vendor) {
+        case AMBA_VENDOR_ST:
+                vik_init_st(base, irq_start, vic_sources);
+                return;
+        default:
+                printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
+                /* fall through */
+        case AMBA_VENDOR_ARM:
+                break;
+        }
        /* Disable all interrupts initially. */
@@ -306,3 +342,60 @@ void __init vic_init(void __iomem *base, unsigned int irq_start,
        vic_pm_register(base, irq_start, resume_sources);
 }
+/*
+ * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
+ * The original cell has 32 interrupts, while the modified one has 64,
+ * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
+ * the probe function is called twice, with base set to offset 000
+ *  and 020 within the page. We call this "second block".
+ */
+static void __init vik_init_st(void __iomem *base, unsigned int irq_start,
+                                u32 vic_sources)
+{
+        unsigned int i;
+        int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
+        /* Disable all interrupts initially. */
+        writel(0, base + VIC_INT_SELECT);
+        writel(0, base + VIC_INT_ENABLE);
+        writel(~0, base + VIC_INT_ENABLE_CLEAR);
+        writel(0, base + VIC_IRQ_STATUS);
+        writel(0, base + VIC_ITCR);
+        writel(~0, base + VIC_INT_SOFT_CLEAR);
+        /*
+         * Make sure we clear all existing interrupts. The vector registers
+         * in this cell are after the second block of general registers,
+         * so we can address them using standard offsets, but only from
+         * the second base address, which is 0x20 in the page
+         */
+        if (vic_2nd_block) {
+                writel(0, base + VIC_PL190_VECT_ADDR);
+                for (i = 0; i < 19; i++) {
+                        unsigned int value;
+                        value = readl(base + VIC_PL190_VECT_ADDR);
+                        writel(value, base + VIC_PL190_VECT_ADDR);
+                }
+                /* ST has 16 vectors as well, but we don't enable them by now */
+                for (i = 0; i < 16; i++) {
+                        void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
+                        writel(0, reg);
+                }
+                writel(32, base + VIC_PL190_DEF_VECT_ADDR);
+        }
+        for (i = 0; i < 32; i++) {
+                if (vic_sources & (1 << i)) {
+                        unsigned int irq = irq_start + i;
+                        set_irq_chip(irq, &vic_chip);
+                        set_irq_chip_data(irq, base);
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+}
diff --git a/arch/arm/configs/bcmring_defconfig b/arch/arm/configs/bcmring_defconfig
new file mode 100644
index 000000000000..bcc0bac551a5
--- /dev/null
+++ b/arch/arm/configs/bcmring_defconfig
@@ -0,0 +1,725 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Fri Jul 17 12:07:28 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+# CONFIG_SYSFS_DEPRECATED_V2 is not set
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+# CONFIG_HOTPLUG is not set
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+# CONFIG_ELF_CORE is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+# CONFIG_EPOLL is not set
+# CONFIG_SIGNALFD is not set
+# CONFIG_TIMERFD is not set
+# CONFIG_EVENTFD is not set
+CONFIG_SHMEM=y
+# CONFIG_AIO is not set
+#
+# Performance Counters
+#
+# CONFIG_VM_EVENT_COUNTERS is not set
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+CONFIG_ARCH_BCMRING=y
+# CONFIG_ARCH_FPGA11107 is not set
+CONFIG_ARCH_BCM11107=y
+#
+# BCMRING Options
+#
+CONFIG_BCM_ZRELADDR=0x8000
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_V6=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v6=y
+CONFIG_CPU_ABRT_EV6=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V6=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V6=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+# CONFIG_ARM_ERRATA_411920 is not set
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+#
+# Kernel Features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0e000000
+CONFIG_ZBOOT_ROM_BSS=0x0ea00000
+CONFIG_ZBOOT_ROM=y
+CONFIG_CMDLINE=""
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+# CONFIG_PACKET is not set
+# CONFIG_UNIX is not set
+# CONFIG_NET_KEY is not set
+# CONFIG_INET is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=y
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+CONFIG_MTD_CFI_ADV_OPTIONS=y
+CONFIG_MTD_CFI_NOSWAP=y
+# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
+# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
+CONFIG_MTD_CFI_GEOMETRY=y
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+# CONFIG_MTD_CFI_I2 is not set
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_OTP is not set
+# CONFIG_MTD_CFI_INTELEXT is not set
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+CONFIG_MTD_NAND_BCM_UMI=y
+CONFIG_MTD_NAND_BCM_UMI_HWCS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_NETDEVICES is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=64
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+# CONFIG_EXT2_FS is not set
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_FILE_LOCKING is not set
+# CONFIG_FSNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+# CONFIG_PROC_PAGE_MONITOR is not set
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+CONFIG_JFFS2_FS_POSIX_ACL=y
+# CONFIG_JFFS2_FS_SECURITY is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+CONFIG_HEADERS_CHECK=y
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_BUILD_DOCSRC is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/cpu9260_defconfig b/arch/arm/configs/cpu9260_defconfig
new file mode 100644
index 000000000000..601e7f3d5e97
--- /dev/null
+++ b/arch/arm/configs/cpu9260_defconfig
@@ -0,0 +1,1338 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Tue Jul 14 14:57:55 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+CONFIG_ARCH_AT91SAM9260=y
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+#
+# AT91SAM9260 Variants
+#
+# CONFIG_ARCH_AT91SAM9260_SAM9XE is not set
+#
+# AT91SAM9260 / AT91SAM9XE Board Type
+#
+# CONFIG_MACH_AT91SAM9260EK is not set
+# CONFIG_MACH_CAM60 is not set
+# CONFIG_MACH_SAM9_L9260 is not set
+# CONFIG_MACH_AFEB9260 is not set
+# CONFIG_MACH_USB_A9260 is not set
+# CONFIG_MACH_QIL_A9260 is not set
+CONFIG_MACH_CPU9260=y
+#
+# AT91 Board Options
+#
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=y
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+CONFIG_MTD_NAND_ATMEL_ECC_HW=y
+# CONFIG_MTD_NAND_ATMEL_ECC_SOFT is not set
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+#
+# SPI RTC drivers
+#
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/cpu9g20_defconfig b/arch/arm/configs/cpu9g20_defconfig
new file mode 100644
index 000000000000..b5b9cbbc6977
--- /dev/null
+++ b/arch/arm/configs/cpu9g20_defconfig
@@ -0,0 +1,1328 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Tue Jul 14 15:03:43 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+#
+# Atmel AT91 System-on-Chip
+#
+# CONFIG_ARCH_AT91RM9200 is not set
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+CONFIG_ARCH_AT91SAM9G20=y
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+#
+# AT91SAM9G20 Board Type
+#
+# CONFIG_MACH_AT91SAM9G20EK is not set
+CONFIG_MACH_CPU9G20=y
+#
+# AT91 Board Options
+#
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=y
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_ATMEL=y
+# CONFIG_MTD_NAND_ATMEL_ECC_HW is not set
+CONFIG_MTD_NAND_ATMEL_ECC_SOFT=y
+# CONFIG_MTD_NAND_ATMEL_ECC_NONE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ALAUDA is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+CONFIG_SMSC_PHY=y
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_MACB=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91SAM9X_WATCHDOG=y
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+#
+# SPI RTC drivers
+#
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91SAM9 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/cpuat91_defconfig b/arch/arm/configs/cpuat91_defconfig
new file mode 100644
index 000000000000..4901827253fb
--- /dev/null
+++ b/arch/arm/configs/cpuat91_defconfig
@@ -0,0 +1,1316 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.31-rc3
+# Tue Jul 14 14:45:01 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+# CONFIG_BLK_DEV_INITRD is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+CONFIG_ARCH_AT91=y
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+#
+# Atmel AT91 System-on-Chip
+#
+CONFIG_ARCH_AT91RM9200=y
+# CONFIG_ARCH_AT91SAM9260 is not set
+# CONFIG_ARCH_AT91SAM9261 is not set
+# CONFIG_ARCH_AT91SAM9263 is not set
+# CONFIG_ARCH_AT91SAM9RL is not set
+# CONFIG_ARCH_AT91SAM9G20 is not set
+# CONFIG_ARCH_AT91CAP9 is not set
+# CONFIG_ARCH_AT91X40 is not set
+CONFIG_AT91_PMC_UNIT=y
+#
+# AT91RM9200 Board Type
+#
+# CONFIG_MACH_ONEARM is not set
+# CONFIG_ARCH_AT91RM9200DK is not set
+# CONFIG_MACH_AT91RM9200EK is not set
+# CONFIG_MACH_CSB337 is not set
+# CONFIG_MACH_CSB637 is not set
+# CONFIG_MACH_CARMEVA is not set
+# CONFIG_MACH_ATEB9200 is not set
+# CONFIG_MACH_KB9200 is not set
+# CONFIG_MACH_PICOTUX2XX is not set
+# CONFIG_MACH_KAFA is not set
+# CONFIG_MACH_ECBAT91 is not set
+# CONFIG_MACH_YL9200 is not set
+CONFIG_MACH_CPUAT91=y
+#
+# AT91 Board Options
+#
+#
+# AT91 Feature Selections
+#
+# CONFIG_AT91_PROGRAMMABLE_CLOCKS is not set
+CONFIG_AT91_TIMER_HZ=100
+CONFIG_AT91_EARLY_DBGU=y
+# CONFIG_AT91_EARLY_USART0 is not set
+# CONFIG_AT91_EARLY_USART1 is not set
+# CONFIG_AT91_EARLY_USART2 is not set
+# CONFIG_AT91_EARLY_USART3 is not set
+# CONFIG_AT91_EARLY_USART4 is not set
+# CONFIG_AT91_EARLY_USART5 is not set
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM920T=y
+CONFIG_CPU_32v4T=y
+CONFIG_CPU_ABRT_EV4T=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_V4WT=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+# CONFIG_ARM_THUMB is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+# CONFIG_AEABI is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_LEDS is not set
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_ARTHUR is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+# CONFIG_MTD_CFI_AMDSTD is not set
+# CONFIG_MTD_CFI_STAA is not set
+CONFIG_MTD_CFI_UTIL=y
+CONFIG_MTD_RAM=y
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+CONFIG_MTD_PHYSMAP=y
+# CONFIG_MTD_PHYSMAP_COMPAT is not set
+# CONFIG_MTD_ARM_INTEGRATOR is not set
+CONFIG_MTD_PLATRAM=y
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_NBD=y
+# CONFIG_BLK_DEV_UB is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_MISC_DEVICES is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+# CONFIG_SCSI_CONSTANTS is not set
+# CONFIG_SCSI_LOGGING is not set
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+CONFIG_PHYLIB=y
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+CONFIG_ARM_AT91_ETHER=y
+# CONFIG_AX88796 is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_USBNET is not set
+# CONFIG_WAN is not set
+CONFIG_PPP=y
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=y
+# CONFIG_PPP_SYNC_TTY is not set
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=y
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_ATMEL=y
+CONFIG_SERIAL_ATMEL_CONSOLE=y
+CONFIG_SERIAL_ATMEL_PDC=y
+# CONFIG_SERIAL_ATMEL_TTYAT is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=32
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_DESIGNWARE is not set
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+CONFIG_AT91RM9200_WATCHDOG=y
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+#
+# Miscellaneous USB options
+#
+# CONFIG_USB_DEVICEFS is not set
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB is not set
+# CONFIG_USB_WUSB_CBAF is not set
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_HWA_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_GADGET_MUSB_HDRC is not set
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_LIBUSUAL is not set
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+#
+# USB port drivers
+#
+# CONFIG_USB_SERIAL is not set
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_VST is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_SELECTED=y
+CONFIG_USB_GADGET_AT91=y
+CONFIG_USB_AT91=y
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
+# CONFIG_USB_GADGET_LH7A40X is not set
+# CONFIG_USB_GADGET_OMAP is not set
+# CONFIG_USB_GADGET_PXA25X is not set
+# CONFIG_USB_GADGET_PXA27X is not set
+# CONFIG_USB_GADGET_S3C_HSOTG is not set
+# CONFIG_USB_GADGET_IMX is not set
+# CONFIG_USB_GADGET_S3C2410 is not set
+# CONFIG_USB_GADGET_M66592 is not set
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_FSL_QE is not set
+# CONFIG_USB_GADGET_CI13XXX is not set
+# CONFIG_USB_GADGET_NET2280 is not set
+# CONFIG_USB_GADGET_GOKU is not set
+# CONFIG_USB_GADGET_LANGWELL is not set
+# CONFIG_USB_GADGET_DUMMY_HCD is not set
+# CONFIG_USB_GADGET_DUALSPEED is not set
+# CONFIG_USB_ZERO is not set
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=y
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FILE_STORAGE is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_NOP_USB_XCEIV is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+# CONFIG_MMC_SDHCI is not set
+CONFIG_MMC_AT91=y
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+#
+# LED drivers
+#
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_BD2802 is not set
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+#
+# iptables trigger is under Netfilter config (LED target)
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+CONFIG_RTC_DRV_PCF8563=y
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+#
+# SPI RTC drivers
+#
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_AT91RM9200 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+# CONFIG_EXT3_FS_XATTR is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+CONFIG_JFFS2_SUMMARY=y
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+CONFIG_MINIX_FS=y
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_FRAME_POINTER=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_DEBUG_USER is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=y
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
index f3074e49f2fa..df9bfbea8612 100644
--- a/arch/arm/configs/jornada720_defconfig
+++ b/arch/arm/configs/jornada720_defconfig
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
-# Linux kernel version: 2.6.27-rc6
+# Linux kernel version: 2.6.31-rc6
-# Tue Sep 16 18:56:58 2008
+# Fri Aug 21 15:41:39 2009
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -9,7 +9,6 @@ CONFIG_GENERIC_GPIO=y
 CONFIG_GENERIC_TIME=y
 CONFIG_GENERIC_CLOCKEVENTS=y
 CONFIG_MMU=y
-# CONFIG_NO_IOPORT is not set
 CONFIG_GENERIC_HARDIRQS=y
 CONFIG_STACKTRACE_SUPPORT=y
 CONFIG_HAVE_LATENCYTOP_SUPPORT=y
@@ -18,16 +17,14 @@ CONFIG_TRACE_IRQFLAGS_SUPPORT=y
 CONFIG_HARDIRQS_SW_RESEND=y
 CONFIG_GENERIC_IRQ_PROBE=y
 CONFIG_RWSEM_GENERIC_SPINLOCK=y
-# CONFIG_ARCH_HAS_ILOG2_U32 is not set
-# CONFIG_ARCH_HAS_ILOG2_U64 is not set
 CONFIG_GENERIC_HWEIGHT=y
 CONFIG_GENERIC_CALIBRATE_DELAY=y
-CONFIG_ARCH_SUPPORTS_AOUT=y
 CONFIG_ZONE_DMA=y
 CONFIG_ARCH_MTD_XIP=y
 CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
 CONFIG_VECTORS_BASE=0xffff0000
 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
 #
 # General setup
@@ -44,10 +41,19 @@ CONFIG_SYSVIPC_SYSCTL=y
 # CONFIG_BSD_PROCESS_ACCT is not set
 # CONFIG_TASKSTATS is not set
 # CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
 # CONFIG_IKCONFIG is not set
 CONFIG_LOG_BUF_SHIFT=14
-# CONFIG_CGROUPS is not set
 # CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
 CONFIG_SYSFS_DEPRECATED=y
 CONFIG_SYSFS_DEPRECATED_V2=y
 # CONFIG_RELAY is not set
@@ -56,9 +62,11 @@ CONFIG_NAMESPACES=y
 # CONFIG_IPC_NS is not set
 # CONFIG_USER_NS is not set
 # CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
 # CONFIG_BLK_DEV_INITRD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
 CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
 # CONFIG_EMBEDDED is not set
 CONFIG_UID16=y
 CONFIG_SYSCTL_SYSCALL=y
@@ -69,17 +77,22 @@ CONFIG_HOTPLUG=y
 CONFIG_PRINTK=y
 CONFIG_BUG=y
 CONFIG_ELF_CORE=y
-CONFIG_COMPAT_BRK=y
 CONFIG_BASE_FULL=y
 CONFIG_FUTEX=y
-CONFIG_ANON_INODES=y
 CONFIG_EPOLL=y
 CONFIG_SIGNALFD=y
 CONFIG_TIMERFD=y
 CONFIG_EVENTFD=y
 CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Performance Counters
+#
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
 # CONFIG_SLAB is not set
 CONFIG_SLUB=y
 # CONFIG_SLOB is not set
@@ -87,30 +100,25 @@ CONFIG_SLUB=y
 # CONFIG_MARKERS is not set
 CONFIG_HAVE_OPROFILE=y
 # CONFIG_KPROBES is not set
-# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
-# CONFIG_HAVE_IOREMAP_PROT is not set
 CONFIG_HAVE_KPROBES=y
 CONFIG_HAVE_KRETPROBES=y
-# CONFIG_HAVE_ARCH_TRACEHOOK is not set
-# CONFIG_HAVE_DMA_ATTRS is not set
-# CONFIG_USE_GENERIC_SMP_HELPERS is not set
 CONFIG_HAVE_CLK=y
-CONFIG_PROC_PAGE_MONITOR=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
 CONFIG_HAVE_GENERIC_DMA_COHERENT=y
 CONFIG_SLABINFO=y
 CONFIG_RT_MUTEXES=y
-# CONFIG_TINY_SHMEM is not set
 CONFIG_BASE_SMALL=0
 CONFIG_MODULES=y
 # CONFIG_MODULE_FORCE_LOAD is not set
 # CONFIG_MODULE_UNLOAD is not set
 # CONFIG_MODVERSIONS is not set
 # CONFIG_MODULE_SRCVERSION_ALL is not set
-CONFIG_KMOD=y
 CONFIG_BLOCK=y
-# CONFIG_LBD is not set
+CONFIG_LBDAF=y
-# CONFIG_BLK_DEV_IO_TRACE is not set
-# CONFIG_LSF is not set
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_BLK_DEV_INTEGRITY is not set
@@ -126,7 +134,7 @@ CONFIG_IOSCHED_CFQ=y
 CONFIG_DEFAULT_CFQ=y
 # CONFIG_DEFAULT_NOOP is not set
 CONFIG_DEFAULT_IOSCHED="cfq"
-CONFIG_CLASSIC_RCU=y
+CONFIG_FREEZER=y
 #
 # System Type
@@ -136,14 +144,15 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_REALVIEW is not set
 # CONFIG_ARCH_VERSATILE is not set
 # CONFIG_ARCH_AT91 is not set
-# CONFIG_ARCH_CLPS7500 is not set
 # CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
 # CONFIG_ARCH_EBSA110 is not set
 # CONFIG_ARCH_EP93XX is not set
 # CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
 # CONFIG_ARCH_NETX is not set
 # CONFIG_ARCH_H720X is not set
-# CONFIG_ARCH_IMX is not set
 # CONFIG_ARCH_IOP13XX is not set
 # CONFIG_ARCH_IOP32X is not set
 # CONFIG_ARCH_IOP33X is not set
@@ -152,23 +161,25 @@ CONFIG_CLASSIC_RCU=y
 # CONFIG_ARCH_IXP4XX is not set
 # CONFIG_ARCH_L7200 is not set
 # CONFIG_ARCH_KIRKWOOD is not set
-# CONFIG_ARCH_KS8695 is not set
-# CONFIG_ARCH_NS9XXX is not set
 # CONFIG_ARCH_LOKI is not set
 # CONFIG_ARCH_MV78XX0 is not set
-# CONFIG_ARCH_MXC is not set
 # CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
 # CONFIG_ARCH_PNX4008 is not set
 # CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
 # CONFIG_ARCH_RPC is not set
 CONFIG_ARCH_SA1100=y
 # CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
 # CONFIG_ARCH_SHARK is not set
 # CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
 # CONFIG_ARCH_DAVINCI is not set
 # CONFIG_ARCH_OMAP is not set
-# CONFIG_ARCH_MSM7X00A is not set
-CONFIG_DMABOUNCE=y
 #
 # SA11x0 Implementations
@@ -189,14 +200,6 @@ CONFIG_SA1100_JORNADA720_SSP=y
 CONFIG_SA1100_SSP=y
 #
-# Boot options
-#
-#
-# Power management
-#
-#
 # Processor Type
 #
 CONFIG_CPU_32=y
@@ -215,8 +218,8 @@ CONFIG_CPU_CP15_MMU=y
 #
 # CONFIG_CPU_ICACHE_DISABLE is not set
 # CONFIG_CPU_DCACHE_DISABLE is not set
-# CONFIG_OUTER_CACHE is not set
 CONFIG_SA1111=y
+CONFIG_DMABOUNCE=y
 CONFIG_FORCE_MAX_ZONEORDER=9
 #
@@ -246,30 +249,36 @@ CONFIG_TICK_ONESHOT=y
 # CONFIG_NO_HZ is not set
 # CONFIG_HIGH_RES_TIMERS is not set
 CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
 # CONFIG_PREEMPT is not set
 CONFIG_HZ=100
 # CONFIG_AEABI is not set
-CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
 CONFIG_ARCH_SPARSEMEM_ENABLE=y
-CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_SPARSEMEM_DEFAULT=y
-CONFIG_NODES_SHIFT=2
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
 CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_FLATMEM_MANUAL is not set
-CONFIG_DISCONTIGMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
-# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_SPARSEMEM_MANUAL=y
-CONFIG_DISCONTIGMEM=y
+CONFIG_SPARSEMEM=y
-CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMORY_PRESENT=y
-CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_SPARSEMEM_EXTREME=y
-# CONFIG_SPARSEMEM_STATIC is not set
-# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
 CONFIG_PAGEFLAGS_EXTENDED=y
 CONFIG_SPLIT_PTLOCK_CPUS=4096
-# CONFIG_RESOURCES_64BIT is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
 CONFIG_ZONE_DMA_FLAG=1
 CONFIG_BOUNCE=y
 CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
 # CONFIG_LEDS is not set
 CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
 #
 # Boot options
@@ -281,9 +290,10 @@ CONFIG_CMDLINE=""
 # CONFIG_KEXEC is not set
 #
-# CPU Frequency scaling
+# CPU Power Management
 #
 # CONFIG_CPU_FREQ is not set
+# CONFIG_CPU_IDLE is not set
 #
 # Floating point emulation
@@ -294,12 +304,14 @@ CONFIG_CMDLINE=""
 #
 CONFIG_FPE_NWFPE=y
 # CONFIG_FPE_NWFPE_XP is not set
-CONFIG_FPE_FASTFPE=y
+# CONFIG_FPE_FASTFPE is not set
 #
 # Userspace binary formats
 #
 CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
 CONFIG_BINFMT_AOUT=y
 # CONFIG_BINFMT_MISC is not set
 # CONFIG_ARTHUR is not set
@@ -353,7 +365,6 @@ CONFIG_INET_TCP_DIAG=y
 CONFIG_TCP_CONG_CUBIC=y
 CONFIG_DEFAULT_TCP_CONG="cubic"
 # CONFIG_TCP_MD5SIG is not set
-# CONFIG_IP_VS is not set
 # CONFIG_IPV6 is not set
 # CONFIG_NETWORK_SECMARK is not set
 CONFIG_NETFILTER=y
@@ -367,10 +378,12 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_NETFILTER_NETLINK_LOG is not set
 # CONFIG_NF_CONNTRACK is not set
 # CONFIG_NETFILTER_XTABLES is not set
+# CONFIG_IP_VS is not set
 #
 # IP: Netfilter Configuration
 #
+# CONFIG_NF_DEFRAG_IPV4 is not set
 # CONFIG_IP_NF_QUEUE is not set
 # CONFIG_IP_NF_IPTABLES is not set
 # CONFIG_IP_NF_ARPTABLES is not set
@@ -379,6 +392,7 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_TIPC is not set
 # CONFIG_ATM is not set
 # CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
 # CONFIG_VLAN_8021Q is not set
 # CONFIG_DECNET is not set
 # CONFIG_LLC2 is not set
@@ -388,7 +402,10 @@ CONFIG_NETFILTER_ADVANCED=y
 # CONFIG_LAPB is not set
 # CONFIG_ECONET is not set
 # CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
 # CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
 #
 # Network testing
@@ -431,14 +448,17 @@ CONFIG_IRCOMM=m
 CONFIG_SA1100_FIR=m
 # CONFIG_BT is not set
 # CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+# CONFIG_WIRELESS_OLD_REGULATORY is not set
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
 #
-# Wireless
+# CFG80211 needs to be enabled for MAC80211
 #
-# CONFIG_CFG80211 is not set
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
-# CONFIG_WIRELESS_EXT is not set
+# CONFIG_WIMAX is not set
-# CONFIG_MAC80211 is not set
-# CONFIG_IEEE80211 is not set
 # CONFIG_RFKILL is not set
 # CONFIG_NET_9P is not set
@@ -464,29 +484,34 @@ CONFIG_EXTRA_FIRMWARE=""
 # CONFIG_PNP is not set
 CONFIG_BLK_DEV=y
 # CONFIG_BLK_DEV_COW_COMMON is not set
-CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_LOOP=y
 # CONFIG_BLK_DEV_CRYPTOLOOP is not set
-CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_NBD=y
 # CONFIG_BLK_DEV_RAM is not set
 # CONFIG_CDROM_PKTCDVD is not set
 # CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
 CONFIG_MISC_DEVICES=y
-# CONFIG_EEPROM_93CX6 is not set
 # CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
 CONFIG_HAVE_IDE=y
 CONFIG_IDE=y
-CONFIG_BLK_DEV_IDE=y
 #
 # Please see Documentation/ide/ide.txt for help/info on IDE drives
 #
 # CONFIG_BLK_DEV_IDE_SATA is not set
-CONFIG_BLK_DEV_IDEDISK=y
+CONFIG_IDE_GD=y
-# CONFIG_IDEDISK_MULTI_MODE is not set
+CONFIG_IDE_GD_ATA=y
+# CONFIG_IDE_GD_ATAPI is not set
 CONFIG_BLK_DEV_IDECS=y
 # CONFIG_BLK_DEV_IDECD is not set
 # CONFIG_BLK_DEV_IDETAPE is not set
-# CONFIG_BLK_DEV_IDEFLOPPY is not set
 # CONFIG_IDE_TASK_IOCTL is not set
 CONFIG_IDE_PROC_FS=y
@@ -513,8 +538,34 @@ CONFIG_DUMMY=y
 # CONFIG_TUN is not set
 # CONFIG_VETH is not set
 # CONFIG_ARCNET is not set
-# CONFIG_NET_ETHERNET is not set
+# CONFIG_PHYLIB is not set
-CONFIG_MII=m
+CONFIG_NET_ETHERNET=y
+# CONFIG_MII is not set
+# CONFIG_AX88796 is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_SMC is not set
+# CONFIG_SMC91X is not set
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_NET_VENDOR_RACAL is not set
+# CONFIG_DNET is not set
+# CONFIG_AT1700 is not set
+# CONFIG_DEPCA is not set
+# CONFIG_HP100 is not set
+# CONFIG_NET_ISA is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_CS89x0 is not set
+# CONFIG_KS8842 is not set
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 # CONFIG_TR is not set
@@ -523,17 +574,27 @@ CONFIG_MII=m
 # Wireless LAN
 #
 # CONFIG_WLAN_PRE80211 is not set
-# CONFIG_WLAN_80211 is not set
+CONFIG_WLAN_80211=y
-# CONFIG_IWLWIFI_LEDS is not set
+# CONFIG_PCMCIA_RAYCS is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AIRO_CS is not set
+# CONFIG_PCMCIA_WL3501 is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_HERMES is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
 CONFIG_NET_PCMCIA=y
-CONFIG_PCMCIA_3C589=m
+# CONFIG_PCMCIA_3C589 is not set
-CONFIG_PCMCIA_3C574=m
+# CONFIG_PCMCIA_3C574 is not set
-CONFIG_PCMCIA_FMVJ18X=m
+# CONFIG_PCMCIA_FMVJ18X is not set
-CONFIG_PCMCIA_PCNET=m
+# CONFIG_PCMCIA_PCNET is not set
-CONFIG_PCMCIA_NMCLAN=m
+# CONFIG_PCMCIA_NMCLAN is not set
-CONFIG_PCMCIA_SMC91C92=m
+# CONFIG_PCMCIA_SMC91C92 is not set
-CONFIG_PCMCIA_XIRC2PS=m
+# CONFIG_PCMCIA_XIRC2PS is not set
-CONFIG_PCMCIA_AXNET=m
+# CONFIG_PCMCIA_AXNET is not set
 # CONFIG_WAN is not set
 # CONFIG_PPP is not set
 # CONFIG_SLIP is not set
@@ -565,20 +626,23 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
 #
 CONFIG_INPUT_KEYBOARD=y
 # CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_KEYBOARD_SUNKBD is not set
 # CONFIG_KEYBOARD_LKKBD is not set
-# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+CONFIG_KEYBOARD_HP7XX=y
 # CONFIG_KEYBOARD_NEWTON is not set
 # CONFIG_KEYBOARD_STOWAWAY is not set
-CONFIG_KEYBOARD_HP7XX=y
+# CONFIG_KEYBOARD_SUNKBD is not set
-# CONFIG_KEYBOARD_GPIO is not set
+# CONFIG_KEYBOARD_XTKBD is not set
 # CONFIG_INPUT_MOUSE is not set
 # CONFIG_INPUT_JOYSTICK is not set
 # CONFIG_INPUT_TABLET is not set
 CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_AD7879 is not set
 # CONFIG_TOUCHSCREEN_FUJITSU is not set
 # CONFIG_TOUCHSCREEN_GUNZE is not set
 # CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
 # CONFIG_TOUCHSCREEN_MTOUCH is not set
 # CONFIG_TOUCHSCREEN_INEXIO is not set
 # CONFIG_TOUCHSCREEN_MK712 is not set
@@ -587,8 +651,8 @@ CONFIG_TOUCHSCREEN_HP7XX=y
 # CONFIG_TOUCHSCREEN_PENMOUNT is not set
 # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
 # CONFIG_TOUCHSCREEN_TOUCHWIN is not set
-# CONFIG_TOUCHSCREEN_UCB1400 is not set
 # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
 # CONFIG_INPUT_MISC is not set
 #
@@ -624,11 +688,12 @@ CONFIG_SERIAL_SA1100_CONSOLE=y
 CONFIG_SERIAL_CORE=y
 CONFIG_SERIAL_CORE_CONSOLE=y
 CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
 CONFIG_LEGACY_PTYS=y
 CONFIG_LEGACY_PTY_COUNT=32
 # CONFIG_IPMI_HANDLER is not set
 CONFIG_HW_RANDOM=m
-# CONFIG_NVRAM is not set
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
 # CONFIG_DTLK is not set
 # CONFIG_R3964 is not set
@@ -650,6 +715,10 @@ CONFIG_GPIOLIB=y
 # CONFIG_GPIO_SYSFS is not set
 #
+# Memory mapped GPIO expanders:
+#
+#
 # I2C GPIO expanders:
 #
@@ -663,12 +732,14 @@ CONFIG_GPIOLIB=y
 # CONFIG_W1 is not set
 # CONFIG_POWER_SUPPLY is not set
 # CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
 # CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
 #
 # Sonics Silicon Backplane
 #
-CONFIG_SSB_POSSIBLE=y
 # CONFIG_SSB is not set
 #
@@ -676,6 +747,7 @@ CONFIG_SSB_POSSIBLE=y
 #
 # CONFIG_MFD_CORE is not set
 # CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
 # CONFIG_HTC_EGPIO is not set
 # CONFIG_HTC_PASIC3 is not set
 # CONFIG_MFD_TMIO is not set
@@ -687,22 +759,7 @@ CONFIG_SSB_POSSIBLE=y
 # Multimedia Capabilities Port drivers
 #
 # CONFIG_MCP_SA11X0 is not set
+# CONFIG_MEDIA_SUPPORT is not set
-#
-# Multimedia devices
-#
-#
-# Multimedia core support
-#
-# CONFIG_VIDEO_DEV is not set
-# CONFIG_DVB_CORE is not set
-# CONFIG_VIDEO_MEDIA is not set
-#
-# Multimedia drivers
-#
-# CONFIG_DAB is not set
 #
 # Graphics support
@@ -712,6 +769,7 @@ CONFIG_SSB_POSSIBLE=y
 CONFIG_FB=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
 CONFIG_FB_CFB_FILLRECT=y
 CONFIG_FB_CFB_COPYAREA=y
 CONFIG_FB_CFB_IMAGEBLIT=y
@@ -733,7 +791,17 @@ CONFIG_FB_CFB_IMAGEBLIT=y
 # CONFIG_FB_SA1100 is not set
 CONFIG_FB_S1D13XXX=y
 # CONFIG_FB_VIRTUAL is not set
-# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_PLATFORM is not set
+CONFIG_LCD_HP700=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_HP700=y
 #
 # Display device support
@@ -757,6 +825,8 @@ CONFIG_FONT_8x16=y
 # CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 # CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
 # CONFIG_NEW_LEDS is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y
@@ -781,12 +851,15 @@ CONFIG_RTC_INTF_DEV=y
 # Platform RTC drivers
 #
 # CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
 # CONFIG_RTC_DRV_DS1511 is not set
 # CONFIG_RTC_DRV_DS1553 is not set
 # CONFIG_RTC_DRV_DS1742 is not set
 # CONFIG_RTC_DRV_STK17TA8 is not set
 # CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
 # CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
 # CONFIG_RTC_DRV_V3020 is not set
 #
@@ -794,15 +867,10 @@ CONFIG_RTC_INTF_DEV=y
 #
 CONFIG_RTC_DRV_SA1100=y
 # CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
-#
-# Voltage and Current regulators
-#
 # CONFIG_REGULATOR is not set
-# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
-# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
-# CONFIG_REGULATOR_BQ24022 is not set
 # CONFIG_UIO is not set
+# CONFIG_STAGING is not set
 #
 # File systems
@@ -811,12 +879,16 @@ CONFIG_EXT2_FS=y
 # CONFIG_EXT2_FS_XATTR is not set
 # CONFIG_EXT2_FS_XIP is not set
 # CONFIG_EXT3_FS is not set
-# CONFIG_EXT4DEV_FS is not set
+# CONFIG_EXT4_FS is not set
 # CONFIG_REISERFS_FS is not set
 # CONFIG_JFS_FS is not set
 # CONFIG_FS_POSIX_ACL is not set
 # CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
 # CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
 CONFIG_DNOTIFY=y
 CONFIG_INOTIFY=y
 CONFIG_INOTIFY_USER=y
@@ -826,6 +898,11 @@ CONFIG_INOTIFY_USER=y
 # CONFIG_FUSE_FS is not set
 #
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
 # CD-ROM/DVD Filesystems
 #
 # CONFIG_ISO9660_FS is not set
@@ -846,14 +923,12 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
 #
 CONFIG_PROC_FS=y
 CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
 CONFIG_SYSFS=y
 # CONFIG_TMPFS is not set
 # CONFIG_HUGETLB_PAGE is not set
 # CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
-#
-# Miscellaneous filesystems
-#
 # CONFIG_ADFS_FS is not set
 # CONFIG_AFFS_FS is not set
 # CONFIG_HFS_FS is not set
@@ -862,6 +937,7 @@ CONFIG_SYSFS=y
 # CONFIG_BFS_FS is not set
 # CONFIG_EFS_FS is not set
 # CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
 # CONFIG_VXFS_FS is not set
 # CONFIG_MINIX_FS is not set
 # CONFIG_OMFS_FS is not set
@@ -870,6 +946,7 @@ CONFIG_SYSFS=y
 # CONFIG_ROMFS_FS is not set
 # CONFIG_SYSV_FS is not set
 # CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
 # CONFIG_NETWORK_FILESYSTEMS is not set
 #
@@ -935,12 +1012,16 @@ CONFIG_DEBUG_KERNEL=y
 CONFIG_DETECT_SOFTLOCKUP=y
 # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
 CONFIG_SCHED_DEBUG=y
 # CONFIG_SCHEDSTATS is not set
 # CONFIG_TIMER_STATS is not set
 # CONFIG_DEBUG_OBJECTS is not set
 # CONFIG_SLUB_DEBUG_ON is not set
 # CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
 # CONFIG_DEBUG_RT_MUTEXES is not set
 # CONFIG_RT_MUTEX_TESTER is not set
 # CONFIG_DEBUG_SPINLOCK is not set
@@ -958,19 +1039,20 @@ CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_MEMORY_INIT=y
 # CONFIG_DEBUG_LIST is not set
 # CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
 CONFIG_FRAME_POINTER=y
 # CONFIG_BOOT_PRINTK_DELAY is not set
 # CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
 # CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
 # CONFIG_FAULT_INJECTION is not set
 # CONFIG_LATENCYTOP is not set
 # CONFIG_SYSCTL_SYSCALL_CHECK is not set
-CONFIG_HAVE_FTRACE=y
+# CONFIG_PAGE_POISONING is not set
-CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
 # CONFIG_FTRACE is not set
-# CONFIG_IRQSOFF_TRACER is not set
-# CONFIG_SCHED_TRACER is not set
-# CONFIG_CONTEXT_SWITCH_TRACER is not set
 # CONFIG_SAMPLES is not set
 CONFIG_HAVE_ARCH_KGDB=y
 # CONFIG_KGDB is not set
@@ -985,13 +1067,16 @@ CONFIG_DEBUG_LL=y
 #
 # CONFIG_KEYS is not set
 # CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
 # CONFIG_SECURITY_FILE_CAPABILITIES is not set
 CONFIG_CRYPTO=y
 #
 # Crypto core or helper
 #
+# CONFIG_CRYPTO_FIPS is not set
 # CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
 # CONFIG_CRYPTO_GF128MUL is not set
 # CONFIG_CRYPTO_NULL is not set
 # CONFIG_CRYPTO_CRYPTD is not set
@@ -1062,15 +1147,21 @@ CONFIG_CRYPTO=y
 # Compression
 #
 # CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
 # CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
 CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
 #
 # Library routines
 #
 CONFIG_BITREVERSE=y
-# CONFIG_GENERIC_FIND_FIRST_BIT is not set
+CONFIG_GENERIC_FIND_LAST_BIT=y
-# CONFIG_GENERIC_FIND_NEXT_BIT is not set
 CONFIG_CRC_CCITT=m
 # CONFIG_CRC16 is not set
 # CONFIG_CRC_T10DIF is not set
@@ -1078,7 +1169,7 @@ CONFIG_CRC_CCITT=m
 CONFIG_CRC32=y
 # CONFIG_CRC7 is not set
 # CONFIG_LIBCRC32C is not set
-CONFIG_PLIST=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
 CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
new file mode 100644
index 000000000000..9bb45b932f04
--- /dev/null
+++ b/arch/arm/configs/nhk8815_defconfig
@@ -0,0 +1,1316 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30
+# Tue Jun 23 22:57:16 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_MMU=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=14
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_DEFAULT_AS=y
+# CONFIG_DEFAULT_DEADLINE is not set
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="anticipatory"
+CONFIG_FREEZER=y
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+CONFIG_ARCH_NOMADIK=y
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+#
+# Nomadik boards
+#
+CONFIG_MACH_NOMADIK_8815NHK=y
+CONFIG_NOMADIK_8815=y
+CONFIG_I2C_BITBANG_8815NHK=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_ARM926T=y
+CONFIG_CPU_32v5=y
+CONFIG_CPU_ABRT_EV5TJ=y
+CONFIG_CPU_PABRT_NOIFAR=y
+CONFIG_CPU_CACHE_VIVT=y
+CONFIG_CPU_COPY_V4WB=y
+CONFIG_CPU_TLB_V4WBI=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
+# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
+CONFIG_OUTER_CACHE=y
+CONFIG_CACHE_L2X0=y
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+CONFIG_COMMON_CLKDEV=y
+#
+# Bus support
+#
+CONFIG_ARM_AMBA=y
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+# CONFIG_NO_HZ is not set
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_PREEMPT=y
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4096
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE=""
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+CONFIG_FPE_NWFPE=y
+# CONFIG_FPE_NWFPE_XP is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+CONFIG_PM=y
+# CONFIG_PM_DEBUG is not set
+CONFIG_PM_SLEEP=y
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_NET=y
+#
+# Networking options
+#
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_NET_KEY=y
+# CONFIG_NET_KEY_MIGRATE is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+# CONFIG_IP_MULTIPLE_TABLES is not set
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_PIMSM_V1 is not set
+# CONFIG_IP_PIMSM_V2 is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_L2CAP=m
+CONFIG_BT_SCO=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+#
+# Bluetooth device drivers
+#
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+# CONFIG_BT_HCIUART_LL is not set
+CONFIG_BT_HCIVHCI=m
+# CONFIG_AF_RXRPC is not set
+CONFIG_WIRELESS=y
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_OLD_REGULATORY=y
+# CONFIG_WIRELESS_EXT is not set
+# CONFIG_LIB80211 is not set
+#
+# CFG80211 needs to be enabled for MAC80211
+#
+CONFIG_MAC80211_DEFAULT_PS_VALUE=0
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_TESTS=m
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_AFS_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PLATRAM is not set
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_VERIFY_WRITE=y
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+# CONFIG_MTD_NAND_GPIO is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+CONFIG_MTD_NAND_NOMADIK=y
+CONFIG_MTD_ONENAND=y
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_ONENAND_GENERIC=y
+# CONFIG_MTD_ONENAND_OTP is not set
+# CONFIG_MTD_ONENAND_2X_PROGRAM is not set
+# CONFIG_MTD_ONENAND_SIM is not set
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=4096
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+CONFIG_CHR_DEV_SG=y
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_WAIT_SCAN=m
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_PHYLIB is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_AX88796 is not set
+CONFIG_SMC91X=y
+# CONFIG_DM9000 is not set
+# CONFIG_ETHOC is not set
+# CONFIG_SMC911X is not set
+# CONFIG_SMSC911X is not set
+# CONFIG_DNET is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_B44 is not set
+# CONFIG_KS8842 is not set
+CONFIG_NETDEV_1000=y
+CONFIG_NETDEV_10000=y
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+CONFIG_PPP=m
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPP_FILTER is not set
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+# CONFIG_PPPOL2TP is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+CONFIG_NETCONSOLE=m
+# CONFIG_NETCONSOLE_DYNAMIC is not set
+CONFIG_NETPOLL=y
+# CONFIG_NETPOLL_TRAP is not set
+CONFIG_NET_POLL_CONTROLLER=y
+# CONFIG_ISDN is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ATKBD is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_AMBA_PL010 is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_GPIO=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+CONFIG_DEBUG_GPIO=y
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+# CONFIG_GPIO_PL061 is not set
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+#
+# Special HID drivers
+#
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_WACOM is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+#
+# Enable Host or Gadget support to see Inventra options
+#
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+# CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+#
+# SPI RTC drivers
+#
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PL030 is not set
+# CONFIG_RTC_DRV_PL031 is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+CONFIG_SMB_FS=m
+# CONFIG_SMB_NLS_DEFAULT is not set
+CONFIG_CIFS=m
+# CONFIG_CIFS_STATS is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+# CONFIG_CIFS_XATTR is not set
+# CONFIG_CIFS_DEBUG2 is not set
+# CONFIG_CIFS_EXPERIMENTAL is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=y
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+# CONFIG_DLM is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_DEBUG_SLAB is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_PREEMPT_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_ERRORS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_LL is not set
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+CONFIG_CRYPTO_ECB=m
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+CONFIG_CRYPTO_MD5=y
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=m
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+CONFIG_CRC_CCITT=m
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_NLATTR=y
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig
new file mode 100644
index 000000000000..b0d7d3d3a5e3
--- /dev/null
+++ b/arch/arm/configs/s5pc100_defconfig
@@ -0,0 +1,892 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.30
+# Wed Jul  1 15:53:07 2009
+#
+CONFIG_ARM=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_GENERIC_GPIO=y
+CONFIG_MMU=y
+CONFIG_NO_IOPORT=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_SWAP=y
+# CONFIG_SYSVIPC is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+# CONFIG_EMBEDDED is not set
+CONFIG_UID16=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+#
+# Performance Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_STRIP_ASM_SYMS is not set
+CONFIG_COMPAT_BRK=y
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+# CONFIG_MARKERS is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_CLK=y
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_SLOW_WORK is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_AS=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+# CONFIG_FREEZER is not set
+#
+# System Type
+#
+# CONFIG_ARCH_AAEC2000 is not set
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_MXC is not set
+# CONFIG_ARCH_STMP3XXX is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_H720X is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP23XX is not set
+# CONFIG_ARCH_IXP2000 is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_L7200 is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_LOKI is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_NS9XXX is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_PNX4008 is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C2410 is not set
+# CONFIG_ARCH_S3C64XX is not set
+CONFIG_ARCH_S5PC1XX=y
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_LH7A40X is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP is not set
+CONFIG_PLAT_S3C=y
+#
+# Boot options
+#
+# CONFIG_S3C_BOOT_ERROR_RESET is not set
+CONFIG_S3C_BOOT_UART_FORCE_FIFO=y
+#
+# Power management
+#
+CONFIG_S3C_LOWLEVEL_UART_PORT=0
+CONFIG_S3C_GPIO_SPACE=0
+CONFIG_S3C_GPIO_TRACK=y
+CONFIG_S3C_GPIO_PULL_UPDOWN=y
+CONFIG_PLAT_S5PC1XX=y
+CONFIG_CPU_S5PC100_INIT=y
+CONFIG_CPU_S5PC100_CLOCK=y
+CONFIG_S5PC100_SETUP_I2C0=y
+CONFIG_CPU_S5PC100=y
+CONFIG_MACH_SMDKC100=y
+#
+# Processor Type
+#
+CONFIG_CPU_32=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_IFAR=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+#
+# Processor Features
+#
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_HAS_TLS_REG=y
+# CONFIG_ARM_ERRATA_430973 is not set
+# CONFIG_ARM_ERRATA_458693 is not set
+# CONFIG_ARM_ERRATA_460075 is not set
+CONFIG_ARM_VIC=y
+CONFIG_ARM_VIC_NR=2
+#
+# Bus support
+#
+# CONFIG_PCI_SYSCALL is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCCARD is not set
+#
+# Kernel Features
+#
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+# CONFIG_PREEMPT is not set
+CONFIG_HZ=100
+CONFIG_AEABI=y
+CONFIG_OABI_COMPAT=y
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+# CONFIG_HIGHMEM is not set
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+CONFIG_HAVE_MLOCK=y
+CONFIG_HAVE_MLOCKED_PAGE_BIT=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+#
+# Boot options
+#
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M"
+# CONFIG_XIP_KERNEL is not set
+# CONFIG_KEXEC is not set
+#
+# CPU Power Management
+#
+# CONFIG_CPU_IDLE is not set
+#
+# Floating point emulation
+#
+#
+# At least one emulation must be selected
+#
+# CONFIG_FPE_NWFPE is not set
+# CONFIG_FPE_FASTFPE is not set
+# CONFIG_VFP is not set
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_HAVE_AOUT=y
+# CONFIG_BINFMT_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+#
+# Power management options
+#
+# CONFIG_PM is not set
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+# CONFIG_NET is not set
+#
+# Device Drivers
+#
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=8192
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_MG_DISK is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_C2PORT is not set
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_MOUSEDEV_PSAUX=y
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_GPIO is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=y
+CONFIG_MOUSE_PS2_ALPS=y
+CONFIG_MOUSE_PS2_LOGIPS2PP=y
+CONFIG_MOUSE_PS2_SYNAPTICS=y
+CONFIG_MOUSE_PS2_TRACKPOINT=y
+# CONFIG_MOUSE_PS2_ELANTECH is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=y
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_GAMEPORT is not set
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+CONFIG_DEVKMEM=y
+# CONFIG_SERIAL_NONSTANDARD is not set
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_CONSOLE is not set
+CONFIG_SERIAL_8250_NR_UARTS=4
+CONFIG_SERIAL_8250_RUNTIME_UARTS=4
+# CONFIG_SERIAL_8250_EXTENDED is not set
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_SAMSUNG=y
+CONFIG_SERIAL_SAMSUNG_UARTS=3
+# CONFIG_SERIAL_SAMSUNG_DEBUG is not set
+CONFIG_SERIAL_SAMSUNG_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+CONFIG_LEGACY_PTYS=y
+CONFIG_LEGACY_PTY_COUNT=256
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_R3964 is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+#
+# I2C Hardware Bus support
+#
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_GPIO is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIOLIB=y
+# CONFIG_DEBUG_GPIO is not set
+# CONFIG_GPIO_SYSFS is not set
+#
+# Memory mapped GPIO expanders:
+#
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_GPIO_PCF857X is not set
+#
+# PCI GPIO expanders:
+#
+#
+# SPI GPIO expanders:
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7473 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_AB3100_CORE is not set
+# CONFIG_MEDIA_SUPPORT is not set
+#
+# Graphics support
+#
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+CONFIG_HID_SUPPORT=y
+CONFIG_HID=y
+CONFIG_HID_DEBUG=y
+# CONFIG_HIDRAW is not set
+# CONFIG_HID_PID is not set
+#
+# Special HID drivers
+#
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+# CONFIG_USB_ARCH_HAS_OHCI is not set
+# CONFIG_USB_ARCH_HAS_EHCI is not set
+# CONFIG_USB is not set
+#
+# Enable Host or Gadget support to see Inventra options
+#
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+# CONFIG_USB_GADGET is not set
+#
+# OTG and related infrastructure
+#
+CONFIG_MMC=y
+CONFIG_MMC_DEBUG=y
+CONFIG_MMC_UNSAFE_RESUME=y
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_BOUNCE=y
+CONFIG_SDIO_UART=y
+# CONFIG_MMC_TEST is not set
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_NEW_LEDS is not set
+CONFIG_RTC_LIB=y
+# CONFIG_RTC_CLASS is not set
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_FS_POSIX_ACL=y
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+CONFIG_GENERIC_ACL=y
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_CRAMFS=y
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BLOCK=y
+# CONFIG_ROMFS_BACKED_BY_MTD is not set
+# CONFIG_ROMFS_BACKED_BY_BOTH is not set
+CONFIG_ROMFS_ON_BLOCK=y
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_RT_MUTEXES=y
+CONFIG_DEBUG_PI_LIST=y
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_MUTEXES=y
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_BOOT_PRINTK_DELAY is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_LATENCYTOP is not set
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+# CONFIG_PAGE_POISONING is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_FUNCTION_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+# CONFIG_BOOT_TRACER is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_STACK_TRACER is not set
+# CONFIG_KMEMTRACE is not set
+# CONFIG_WORKQUEUE_TRACER is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+CONFIG_ARM_UNWIND=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_ERRORS=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_LL=y
+# CONFIG_DEBUG_ICEDCC is not set
+CONFIG_DEBUG_S3C_PORT=y
+CONFIG_DEBUG_S3C_UART=0
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+# CONFIG_CRYPTO is not set
+# CONFIG_BINARY_PRINTF is not set
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_DECOMPRESS_BZIP2=y
+CONFIG_DECOMPRESS_LZMA=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_DMA=y
diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h
index 15f8a092b700..00f46d9ce299 100644
--- a/arch/arm/include/asm/assembler.h
+++ b/arch/arm/include/asm/assembler.h
@@ -74,23 +74,56 @@
 * Enable and disable interrupts
 */
 #if __LINUX_ARM_ARCH__ >= 6
-        .macro  disable_irq
+        .macro  disable_irq_notrace
        cpsid   i
        .endm
-        .macro  enable_irq
+        .macro  enable_irq_notrace
        cpsie   i
        .endm
 #else
-        .macro  disable_irq
+        .macro  disable_irq_notrace
        msr     cpsr_c, #PSR_I_BIT | SVC_MODE
        .endm
-        .macro  enable_irq
+        .macro  enable_irq_notrace
        msr     cpsr_c, #SVC_MODE
        .endm
 #endif
+        .macro asm_trace_hardirqs_off
+#if defined(CONFIG_TRACE_IRQFLAGS)
+        stmdb   sp!, {r0-r3, ip, lr}
+        bl      trace_hardirqs_off
+        ldmia   sp!, {r0-r3, ip, lr}
+#endif
+        .endm
+        .macro asm_trace_hardirqs_on_cond, cond
+#if defined(CONFIG_TRACE_IRQFLAGS)
+        /*
+         * actually the registers should be pushed and pop'd conditionally, but
+         * after bl the flags are certainly clobbered
+         */
+        stmdb   sp!, {r0-r3, ip, lr}
+        bl\cond trace_hardirqs_on
+        ldmia   sp!, {r0-r3, ip, lr}
+#endif
+        .endm
+        .macro asm_trace_hardirqs_on
+        asm_trace_hardirqs_on_cond al
+        .endm
+        .macro disable_irq
+        disable_irq_notrace
+        asm_trace_hardirqs_off
+        .endm
+        .macro enable_irq
+        asm_trace_hardirqs_on
+        enable_irq_notrace
+        .endm
 /*
 * Save the current IRQ state and disable IRQs.  Note that this macro
 * assumes FIQs are enabled, and that the processor is in SVC mode.
@@ -104,10 +137,16 @@
 * Restore interrupt state previously stored in a register.  We don't
 * guarantee that this will preserve the flags.
 */
-        .macro  restore_irqs, oldcpsr
+        .macro  restore_irqs_notrace, oldcpsr
        msr     cpsr_c, \oldcpsr
        .endm
+        .macro restore_irqs, oldcpsr
+        tst     \oldcpsr, #PSR_I_BIT
+        asm_trace_hardirqs_on_cond eq
+        restore_irqs_notrace \oldcpsr
+        .endm
 #define USER(x...)                              \
 9999:   x;                                      \
        .section __ex_table,"a";                \
@@ -127,3 +166,87 @@
 #endif
 #endif
        .endm
+#ifdef CONFIG_THUMB2_KERNEL
+        .macro  setmode, mode, reg
+        mov     \reg, #\mode
+        msr     cpsr_c, \reg
+        .endm
+#else
+        .macro  setmode, mode, reg
+        msr     cpsr_c, #\mode
+        .endm
+#endif
+/*
+ * STRT/LDRT access macros with ARM and Thumb-2 variants
+ */
+#ifdef CONFIG_THUMB2_KERNEL
+        .macro  usraccoff, instr, reg, ptr, inc, off, cond, abort
+9999:
+        .if     \inc == 1
+        \instr\cond\()bt \reg, [\ptr, #\off]
+        .elseif \inc == 4
+        \instr\cond\()t \reg, [\ptr, #\off]
+        .else
+        .error  "Unsupported inc macro argument"
+        .endif
+        .section __ex_table,"a"
+        .align  3
+        .long   9999b, \abort
+        .previous
+        .endm
+        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
+        @ explicit IT instruction needed because of the label
+        @ introduced by the USER macro
+        .ifnc   \cond,al
+        .if     \rept == 1
+        itt     \cond
+        .elseif \rept == 2
+        ittt    \cond
+        .else
+        .error  "Unsupported rept macro argument"
+        .endif
+        .endif
+        @ Slightly optimised to avoid incrementing the pointer twice
+        usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
+        .if     \rept == 2
+        usraccoff \instr, \reg, \ptr, \inc, 4, \cond, \abort
+        .endif
+        add\cond \ptr, #\rept * \inc
+        .endm
+#else   /* !CONFIG_THUMB2_KERNEL */
+        .macro  usracc, instr, reg, ptr, inc, cond, rept, abort
+        .rept   \rept
+9999:
+        .if     \inc == 1
+        \instr\cond\()bt \reg, [\ptr], #\inc
+        .elseif \inc == 4
+        \instr\cond\()t \reg, [\ptr], #\inc
+        .else
+        .error  "Unsupported inc macro argument"
+        .endif
+        .section __ex_table,"a"
+        .align  3
+        .long   9999b, \abort
+        .previous
+        .endr
+        .endm
+#endif  /* CONFIG_THUMB2_KERNEL */
+        .macro  strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
+        usracc  str, \reg, \ptr, \inc, \cond, \rept, \abort
+        .endm
+        .macro  ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
+        usracc  ldr, \reg, \ptr, \inc, \cond, \rept, \abort
+        .endm
diff --git a/arch/arm/include/asm/device.h b/arch/arm/include/asm/device.h
index c61642b40603..9f390ce335cb 100644
--- a/arch/arm/include/asm/device.h
+++ b/arch/arm/include/asm/device.h
@@ -12,4 +12,7 @@ struct dev_archdata {
 #endif
 };
+struct pdev_archdata {
+};
 #endif
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index c207504de84d..c3b911ee9151 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -55,6 +55,9 @@ typedef struct user_fp elf_fpregset_t;
 #define R_ARM_MOVW_ABS_NC       43
 #define R_ARM_MOVT_ABS          44
+#define R_ARM_THM_CALL          10
+#define R_ARM_THM_JUMP24        30
 /*
 * These are used to set parameters in the core dumps.
 */
diff --git a/arch/arm/include/asm/ftrace.h b/arch/arm/include/asm/ftrace.h
index 39c8bc1a006a..103f7ee97313 100644
--- a/arch/arm/include/asm/ftrace.h
+++ b/arch/arm/include/asm/ftrace.h
@@ -7,8 +7,43 @@
 #ifndef __ASSEMBLY__
 extern void mcount(void);
+extern void __gnu_mcount_nc(void);
 #endif
 #endif
+#ifndef __ASSEMBLY__
+#if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND)
+/*
+ * return_address uses walk_stackframe to do it's work.  If both
+ * CONFIG_FRAME_POINTER=y and CONFIG_ARM_UNWIND=y walk_stackframe uses unwind
+ * information.  For this to work in the function tracer many functions would
+ * have to be marked with __notrace.  So for now just depend on
+ * !CONFIG_ARM_UNWIND.
+ */
+void *return_address(unsigned int);
+#else
+extern inline void *return_address(unsigned int level)
+{
+        return NULL;
+}
+#endif
+#define HAVE_ARCH_CALLER_ADDR
+#define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
+#define CALLER_ADDR1 ((unsigned long)return_address(1))
+#define CALLER_ADDR2 ((unsigned long)return_address(2))
+#define CALLER_ADDR3 ((unsigned long)return_address(3))
+#define CALLER_ADDR4 ((unsigned long)return_address(4))
+#define CALLER_ADDR5 ((unsigned long)return_address(5))
+#define CALLER_ADDR6 ((unsigned long)return_address(6))
+#endif /* ifndef __ASSEMBLY__ */
 #endif /* _ASM_ARM_FTRACE */
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 9ee743b95de8..bfcc15929a7f 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -99,6 +99,7 @@ futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
        __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
        "1:     ldrt    %0, [%3]\n"
        "       teq     %0, %1\n"
+        "       it      eq      @ explicit IT needed for the 2b label\n"
        "2:     streqt  %2, [%3]\n"
        "3:\n"
        "       .section __ex_table,\"a\"\n"
diff --git a/arch/arm/include/asm/mach/mmc.h b/arch/arm/include/asm/mach/mmc.h
index 4da332b03144..b490ecc79def 100644
--- a/arch/arm/include/asm/mach/mmc.h
+++ b/arch/arm/include/asm/mach/mmc.h
@@ -10,6 +10,8 @@ struct mmc_platform_data {
        unsigned int ocr_mask;                  /* available voltages */
        u32 (*translate_vdd)(struct device *, unsigned int);
        unsigned int (*status)(struct device *);
+        int     gpio_wp;
+        int     gpio_cd;
 };
 #endif
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 85763db87449..cefedf062138 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -44,7 +44,13 @@
 * The module space lives between the addresses given by TASK_SIZE
 * and PAGE_OFFSET - it must be within 32MB of the kernel text.
 */
+#ifndef CONFIG_THUMB2_KERNEL
 #define MODULES_VADDR           (PAGE_OFFSET - 16*1024*1024)
+#else
+/* smaller range for Thumb-2 symbols relocation (2^24)*/
+#define MODULES_VADDR           (PAGE_OFFSET - 8*1024*1024)
+#endif
 #if TASK_SIZE > MODULES_VADDR
 #error Top of user space clashes with start of module space
 #endif
@@ -212,7 +218,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 *
 *  page_to_pfn(page)   convert a struct page * to a PFN number
 *  pfn_to_page(pfn)    convert a _valid_ PFN number to struct page *
- *  pfn_valid(pfn)      indicates whether a PFN number is valid
 *
 *  virt_to_page(k)     convert a _valid_ virtual address to struct page *
 *  virt_addr_valid(k)  indicates whether a virtual address is valid
@@ -221,10 +226,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define ARCH_PFN_OFFSET         PHYS_PFN_OFFSET
-#ifndef CONFIG_SPARSEMEM
-#define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
-#endif
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
@@ -241,18 +242,6 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
 #define arch_pfn_to_nid(pfn)    PFN_TO_NID(pfn)
 #define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
-#define pfn_valid(pfn)                                          \
-        ({                                                      \
-                unsigned int nid = PFN_TO_NID(pfn);             \
-                int valid = nid < MAX_NUMNODES;                 \
-                if (valid) {                                    \
-                        pg_data_t *node = NODE_DATA(nid);       \
-                        valid = (pfn - node->node_start_pfn) <  \
-                                node->node_spanned_pages;       \
-                }                                               \
-                valid;                                          \
-        })
 #define virt_to_page(kaddr)                                     \
        (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
diff --git a/arch/arm/include/asm/mmu_context.h b/arch/arm/include/asm/mmu_context.h
index 263fed05ea33..bcdb9291ef0c 100644
--- a/arch/arm/include/asm/mmu_context.h
+++ b/arch/arm/include/asm/mmu_context.h
@@ -62,8 +62,10 @@ static inline void check_context(struct mm_struct *mm)
 static inline void check_context(struct mm_struct *mm)
 {
+#ifdef CONFIG_MMU
        if (unlikely(mm->context.kvm_seq != init_mm.context.kvm_seq))
                __check_kvm_seq(mm);
+#endif
 }
 #define init_new_context(tsk,mm)        0
diff --git a/arch/arm/include/asm/page-nommu.h b/arch/arm/include/asm/page-nommu.h
index 3574c0deb37f..d1b162a18dcb 100644
--- a/arch/arm/include/asm/page-nommu.h
+++ b/arch/arm/include/asm/page-nommu.h
@@ -43,7 +43,4 @@ typedef unsigned long pgprot_t;
 #define __pmd(x)        (x)
 #define __pgprot(x)     (x)
-extern unsigned long memory_start;
-extern unsigned long memory_end;
 #endif
diff --git a/arch/arm/include/asm/page.h b/arch/arm/include/asm/page.h
index 9c746af1bf6e..3a32af4cce30 100644
--- a/arch/arm/include/asm/page.h
+++ b/arch/arm/include/asm/page.h
@@ -194,6 +194,10 @@ typedef unsigned long pgprot_t;
 typedef struct page *pgtable_t;
+#ifndef CONFIG_SPARSEMEM
+extern int pfn_valid(unsigned long);
+#endif
 #include <asm/memory.h>
 #endif /* !__ASSEMBLY__ */
diff --git a/arch/arm/include/asm/pgalloc.h b/arch/arm/include/asm/pgalloc.h
index 3dcd64bf1824..b12cc98bbe04 100644
--- a/arch/arm/include/asm/pgalloc.h
+++ b/arch/arm/include/asm/pgalloc.h
@@ -36,6 +36,8 @@ extern void free_pgd_slow(struct mm_struct *mm, pgd_t *pgd);
 #define pgd_alloc(mm)                   get_pgd_slow(mm)
 #define pgd_free(mm, pgd)               free_pgd_slow(mm, pgd)
+#define PGALLOC_GFP     (GFP_KERNEL | __GFP_NOTRACK | __GFP_REPEAT | __GFP_ZERO)
 /*
 * Allocate one PTE table.
 *
@@ -57,7 +59,7 @@ pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
 {
        pte_t *pte;
-        pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
+        pte = (pte_t *)__get_free_page(PGALLOC_GFP);
        if (pte) {
                clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE);
                pte += PTRS_PER_PTE;
@@ -71,10 +73,16 @@ pte_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
        struct page *pte;
-        pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
+#ifdef CONFIG_HIGHPTE
+        pte = alloc_pages(PGALLOC_GFP | __GFP_HIGHMEM, 0);
+#else
+        pte = alloc_pages(PGALLOC_GFP, 0);
+#endif
        if (pte) {
-                void *page = page_address(pte);
+                if (!PageHighMem(pte)) {
-                clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
+                        void *page = page_address(pte);
+                        clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
+                }
                pgtable_page_ctor(pte);
        }
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index c433c6c73112..201ccaa11f61 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -162,10 +162,8 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
 * entries are stored 1024 bytes below.
 */
 #define L_PTE_PRESENT           (1 << 0)
-#define L_PTE_FILE              (1 << 1)        /* only when !PRESENT */
 #define L_PTE_YOUNG             (1 << 1)
-#define L_PTE_BUFFERABLE        (1 << 2)        /* obsolete, matches PTE */
+#define L_PTE_FILE              (1 << 2)        /* only when !PRESENT */
-#define L_PTE_CACHEABLE         (1 << 3)        /* obsolete, matches PTE */
 #define L_PTE_DIRTY             (1 << 6)
 #define L_PTE_WRITE             (1 << 7)
 #define L_PTE_USER              (1 << 8)
@@ -264,10 +262,19 @@ extern struct page *empty_zero_page;
 #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
 #define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
 #define pte_offset_kernel(dir,addr)     (pmd_page_vaddr(*(dir)) + __pte_index(addr))
-#define pte_offset_map(dir,addr)        (pmd_page_vaddr(*(dir)) + __pte_index(addr))
-#define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
+#define pte_offset_map(dir,addr)        (__pte_map(dir, KM_PTE0) + __pte_index(addr))
-#define pte_unmap(pte)          do { } while (0)
+#define pte_offset_map_nested(dir,addr) (__pte_map(dir, KM_PTE1) + __pte_index(addr))
-#define pte_unmap_nested(pte)   do { } while (0)
+#define pte_unmap(pte)                  __pte_unmap(pte, KM_PTE0)
+#define pte_unmap_nested(pte)           __pte_unmap(pte, KM_PTE1)
+#ifndef CONFIG_HIGHPTE
+#define __pte_map(dir,km)       pmd_page_vaddr(*(dir))
+#define __pte_unmap(pte,km)     do { } while (0)
+#else
+#define __pte_map(dir,km)       ((pte_t *)kmap_atomic(pmd_page(*(dir)), km) + PTRS_PER_PTE)
+#define __pte_unmap(pte,km)     kunmap_atomic((pte - PTRS_PER_PTE), km)
+#endif
 #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
@@ -381,13 +388,13 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 *
 *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *   <--------------- offset --------------------> <--- type --> 0 0
+ *   <--------------- offset --------------------> <- type --> 0 0 0
 *
- * This gives us up to 127 swap files and 32GB per swap file.  Note that
+ * This gives us up to 63 swap files and 32GB per swap file.  Note that
 * the offset field is always non-zero.
 */
-#define __SWP_TYPE_SHIFT        2
+#define __SWP_TYPE_SHIFT        3
-#define __SWP_TYPE_BITS         7
+#define __SWP_TYPE_BITS         6
 #define __SWP_TYPE_MASK         ((1 << __SWP_TYPE_BITS) - 1)
 #define __SWP_OFFSET_SHIFT      (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
@@ -411,13 +418,13 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 *
 *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- *   <------------------------ offset -------------------------> 1 0
+ *   <----------------------- offset ------------------------> 1 0 0
 */
 #define pte_file(pte)           (pte_val(pte) & L_PTE_FILE)
-#define pte_to_pgoff(x)         (pte_val(x) >> 2)
+#define pte_to_pgoff(x)         (pte_val(x) >> 3)
-#define pgoff_to_pte(x)         __pte(((x) << 2) | L_PTE_FILE)
+#define pgoff_to_pte(x)         __pte(((x) << 3) | L_PTE_FILE)
-#define PTE_FILE_MAX_BITS       30
+#define PTE_FILE_MAX_BITS       29
 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
 /* FIXME: this is not correct */
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index 67b833c9b6b9..bbecccda76d0 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -82,6 +82,14 @@
 #define PSR_ENDSTATE    0
 #endif
+/* 
+ * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
+ * process is located in memory.
+ */
+#define PT_TEXT_ADDR            0x10000
+#define PT_DATA_ADDR            0x10004
+#define PT_TEXT_END_ADDR        0x10008
 #ifndef __ASSEMBLY__
 /*
diff --git a/arch/arm/include/asm/socket.h b/arch/arm/include/asm/socket.h
index 537de4e0ef50..92ac61d294fd 100644
--- a/arch/arm/include/asm/socket.h
+++ b/arch/arm/include/asm/socket.h
@@ -57,4 +57,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
index 73394e50cbca..2dfb7d7a66e9 100644
--- a/arch/arm/include/asm/thread_info.h
+++ b/arch/arm/include/asm/thread_info.h
@@ -130,23 +130,28 @@ extern void vfp_sync_state(struct thread_info *thread);
 *  TIF_SYSCALL_TRACE   - syscall trace active
 *  TIF_SIGPENDING      - signal pending
 *  TIF_NEED_RESCHED    - rescheduling necessary
+ *  TIF_NOTIFY_RESUME   - callback before returning to user
 *  TIF_USEDFPU         - FPU was used by this task this quantum (SMP)
 *  TIF_POLLING_NRFLAG  - true if poll_idle() is polling TIF_NEED_RESCHED
 */
 #define TIF_SIGPENDING          0
 #define TIF_NEED_RESCHED        1
+#define TIF_NOTIFY_RESUME       2       /* callback before returning to user */
 #define TIF_SYSCALL_TRACE       8
 #define TIF_POLLING_NRFLAG      16
 #define TIF_USING_IWMMXT        17
 #define TIF_MEMDIE              18
 #define TIF_FREEZE              19
+#define TIF_RESTORE_SIGMASK     20
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
 #define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
+#define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
 /*
 * Change these and you break ASM code in entry-common.S
diff --git a/arch/arm/include/asm/uaccess.h b/arch/arm/include/asm/uaccess.h
index 0da9bc9b3b1d..1d6bd40a4322 100644
--- a/arch/arm/include/asm/uaccess.h
+++ b/arch/arm/include/asm/uaccess.h
@@ -17,6 +17,7 @@
 #include <asm/memory.h>
 #include <asm/domain.h>
 #include <asm/system.h>
+#include <asm/unified.h>
 #define VERIFY_READ 0
 #define VERIFY_WRITE 1
@@ -365,8 +366,10 @@ do {									\
 #define __put_user_asm_dword(x,__pu_addr,err)                   \
        __asm__ __volatile__(                                   \
-        "1:     strt    " __reg_oper1 ", [%1], #4\n"            \
+ ARM(   "1:     strt    " __reg_oper1 ", [%1], #4\n"    )       \
-        "2:     strt    " __reg_oper0 ", [%1]\n"                \
+ ARM(   "2:     strt    " __reg_oper0 ", [%1]\n"        )       \
+ THUMB( "1:     strt    " __reg_oper1 ", [%1]\n"        )       \
+ THUMB( "2:     strt    " __reg_oper0 ", [%1, #4]\n"    )       \
        "3:\n"                                                  \
        "       .section .fixup,\"ax\"\n"                       \
        "       .align  2\n"                                    \
diff --git a/arch/arm/include/asm/unified.h b/arch/arm/include/asm/unified.h
new file mode 100644
index 000000000000..073e85b9b961
--- /dev/null
+++ b/arch/arm/include/asm/unified.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-arm/unified.h - Unified Assembler Syntax helper macros
+ *
+ * Copyright (C) 2008 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_UNIFIED_H
+#define __ASM_UNIFIED_H
+#if defined(__ASSEMBLY__) && defined(CONFIG_ARM_ASM_UNIFIED)
+        .syntax unified
+#endif
+#ifdef CONFIG_THUMB2_KERNEL
+#if __GNUC__ < 4
+#error Thumb-2 kernel requires gcc >= 4
+#endif
+/* The CPSR bit describing the instruction set (Thumb) */
+#define PSR_ISETSTATE   PSR_T_BIT
+#define ARM(x...)
+#define THUMB(x...)     x
+#define W(instr)        instr.w
+#define BSYM(sym)       sym + 1
+#else   /* !CONFIG_THUMB2_KERNEL */
+/* The CPSR bit describing the instruction set (ARM) */
+#define PSR_ISETSTATE   0
+#define ARM(x...)       x
+#define THUMB(x...)
+#define W(instr)        instr
+#define BSYM(sym)       sym
+#endif  /* CONFIG_THUMB2_KERNEL */
+#ifndef CONFIG_ARM_ASM_UNIFIED
+/*
+ * If the unified assembly syntax isn't used (in ARM mode), these
+ * macros expand to an empty string
+ */
+#ifdef __ASSEMBLY__
+        .macro  it, cond
+        .endm
+        .macro  itt, cond
+        .endm
+        .macro  ite, cond
+        .endm
+        .macro  ittt, cond
+        .endm
+        .macro  itte, cond
+        .endm
+        .macro  itet, cond
+        .endm
+        .macro  itee, cond
+        .endm
+        .macro  itttt, cond
+        .endm
+        .macro  ittte, cond
+        .endm
+        .macro  ittet, cond
+        .endm
+        .macro  ittee, cond
+        .endm
+        .macro  itett, cond
+        .endm
+        .macro  itete, cond
+        .endm
+        .macro  iteet, cond
+        .endm
+        .macro  iteee, cond
+        .endm
+#else   /* !__ASSEMBLY__ */
+__asm__(
+"       .macro  it, cond\n"
+"       .endm\n"
+"       .macro  itt, cond\n"
+"       .endm\n"
+"       .macro  ite, cond\n"
+"       .endm\n"
+"       .macro  ittt, cond\n"
+"       .endm\n"
+"       .macro  itte, cond\n"
+"       .endm\n"
+"       .macro  itet, cond\n"
+"       .endm\n"
+"       .macro  itee, cond\n"
+"       .endm\n"
+"       .macro  itttt, cond\n"
+"       .endm\n"
+"       .macro  ittte, cond\n"
+"       .endm\n"
+"       .macro  ittet, cond\n"
+"       .endm\n"
+"       .macro  ittee, cond\n"
+"       .endm\n"
+"       .macro  itett, cond\n"
+"       .endm\n"
+"       .macro  itete, cond\n"
+"       .endm\n"
+"       .macro  iteet, cond\n"
+"       .endm\n"
+"       .macro  iteee, cond\n"
+"       .endm\n");
+#endif  /* __ASSEMBLY__ */
+#endif  /* CONFIG_ARM_ASM_UNIFIED */
+#endif  /* !__ASM_UNIFIED_H */
diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h
index 0e97b8cb77d5..9122c9ee18fb 100644
--- a/arch/arm/include/asm/unistd.h
+++ b/arch/arm/include/asm/unistd.h
@@ -360,8 +360,8 @@
 #define __NR_readlinkat                 (__NR_SYSCALL_BASE+332)
 #define __NR_fchmodat                   (__NR_SYSCALL_BASE+333)
 #define __NR_faccessat                  (__NR_SYSCALL_BASE+334)
-                                        /* 335 for pselect6 */
+#define __NR_pselect6                   (__NR_SYSCALL_BASE+335)
-                                        /* 336 for ppoll */
+#define __NR_ppoll                      (__NR_SYSCALL_BASE+336)
 #define __NR_unshare                    (__NR_SYSCALL_BASE+337)
 #define __NR_set_robust_list            (__NR_SYSCALL_BASE+338)
 #define __NR_get_robust_list            (__NR_SYSCALL_BASE+339)
@@ -372,7 +372,7 @@
 #define __NR_vmsplice                   (__NR_SYSCALL_BASE+343)
 #define __NR_move_pages                 (__NR_SYSCALL_BASE+344)
 #define __NR_getcpu                     (__NR_SYSCALL_BASE+345)
-                                        /* 346 for epoll_pwait */
+#define __NR_epoll_pwait                (__NR_SYSCALL_BASE+346)
 #define __NR_kexec_load                 (__NR_SYSCALL_BASE+347)
 #define __NR_utimensat                  (__NR_SYSCALL_BASE+348)
 #define __NR_signalfd                   (__NR_SYSCALL_BASE+349)
@@ -432,6 +432,7 @@
 #define __ARCH_WANT_SYS_SIGPENDING
 #define __ARCH_WANT_SYS_SIGPROCMASK
 #define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
 #if !defined(CONFIG_AEABI) || defined(CONFIG_OABI_COMPAT)
 #define __ARCH_WANT_SYS_TIME
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index ff89d0b3abc5..3213c9382b17 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -8,10 +8,12 @@ ifdef CONFIG_DYNAMIC_FTRACE
 CFLAGS_REMOVE_ftrace.o = -pg
 endif
+CFLAGS_REMOVE_return_address.o = -pg
 # Object file lists.
 obj-y           := compat.o elf.o entry-armv.o entry-common.o irq.o \
-                   process.o ptrace.o setup.o signal.o \
+                   process.o ptrace.o return_address.o setup.o signal.o \
                   sys_arm.o stacktrace.o time.o traps.o
 obj-$(CONFIG_ISA_DMA_API)       += dma.o
diff --git a/arch/arm/kernel/armksyms.c b/arch/arm/kernel/armksyms.c
index 531e1860e546..0e627705f746 100644
--- a/arch/arm/kernel/armksyms.c
+++ b/arch/arm/kernel/armksyms.c
@@ -186,4 +186,5 @@ EXPORT_SYMBOL(_find_next_bit_be);
 #ifdef CONFIG_FUNCTION_TRACER
 EXPORT_SYMBOL(mcount);
+EXPORT_SYMBOL(__gnu_mcount_nc);
 #endif
diff --git a/arch/arm/kernel/calls.S b/arch/arm/kernel/calls.S
index f776e72a4cb8..ecfa98954d1d 100644
--- a/arch/arm/kernel/calls.S
+++ b/arch/arm/kernel/calls.S
@@ -81,7 +81,7 @@
                CALL(sys_ni_syscall)            /* was sys_ssetmask */
 /* 70 */        CALL(sys_setreuid16)
                CALL(sys_setregid16)
-                CALL(sys_sigsuspend_wrapper)
+                CALL(sys_sigsuspend)
                CALL(sys_sigpending)
                CALL(sys_sethostname)
 /* 75 */        CALL(sys_setrlimit)
@@ -188,7 +188,7 @@
                CALL(sys_rt_sigpending)
                CALL(sys_rt_sigtimedwait)
                CALL(sys_rt_sigqueueinfo)
-                CALL(sys_rt_sigsuspend_wrapper)
+                CALL(sys_rt_sigsuspend)
 /* 180 */       CALL(ABI(sys_pread64, sys_oabi_pread64))
                CALL(ABI(sys_pwrite64, sys_oabi_pwrite64))
                CALL(sys_chown16)
@@ -344,8 +344,8 @@
                CALL(sys_readlinkat)
                CALL(sys_fchmodat)
                CALL(sys_faccessat)
-/* 335 */       CALL(sys_ni_syscall)            /* eventually pselect6 */
+/* 335 */       CALL(sys_pselect6)
-                CALL(sys_ni_syscall)            /* eventually ppoll */
+                CALL(sys_ppoll)
                CALL(sys_unshare)
                CALL(sys_set_robust_list)
                CALL(sys_get_robust_list)
@@ -355,7 +355,7 @@
                CALL(sys_vmsplice)
                CALL(sys_move_pages)
 /* 345 */       CALL(sys_getcpu)
-                CALL(sys_ni_syscall)            /* eventually epoll_pwait */
+                CALL(sys_epoll_pwait)
                CALL(sys_kexec_load)
                CALL(sys_utimensat)
                CALL(sys_signalfd)
diff --git a/arch/arm/kernel/crunch.c b/arch/arm/kernel/crunch.c
index 99995c2b2312..769abe15cf91 100644
--- a/arch/arm/kernel/crunch.c
+++ b/arch/arm/kernel/crunch.c
@@ -31,7 +31,7 @@ void crunch_task_release(struct thread_info *thread)
 static int crunch_enabled(u32 devcfg)
 {
-        return !!(devcfg & EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE);
+        return !!(devcfg & EP93XX_SYSCON_DEVCFG_CPENA);
 }
 static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
@@ -56,11 +56,16 @@ static int crunch_do(struct notifier_block *self, unsigned long cmd, void *t)
                break;
        case THREAD_NOTIFY_SWITCH:
-                devcfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
+                devcfg = __raw_readl(EP93XX_SYSCON_DEVCFG);
                if (crunch_enabled(devcfg) || crunch_owner == crunch_state) {
-                        devcfg ^= EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
+                        /*
+                         * We don't use ep93xx_syscon_swlocked_write() here
+                         * because we are on the context switch path and
+                         * preemption is already disabled.
+                         */
+                        devcfg ^= EP93XX_SYSCON_DEVCFG_CPENA;
                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-                        __raw_writel(devcfg, EP93XX_SYSCON_DEVICE_CONFIG);
+                        __raw_writel(devcfg, EP93XX_SYSCON_DEVCFG);
                }
                break;
        }
diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index fc8af43c5000..3d727a8a23bc 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -34,7 +34,7 @@
        @
        @ routine called with r0 = irq number, r1 = struct pt_regs *
        @
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
        bne     asm_do_IRQ
 #ifdef CONFIG_SMP
@@ -46,13 +46,13 @@
         */
        test_for_ipi r0, r6, r5, lr
        movne   r0, sp
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
        bne     do_IPI
 #ifdef CONFIG_LOCAL_TIMERS
        test_for_ltirq r0, r6, r5, lr
        movne   r0, sp
-        adrne   lr, 1b
+        adrne   lr, BSYM(1b)
        bne     do_local_timer
 #endif
 #endif
@@ -70,7 +70,10 @@
 */
        .macro  inv_entry, reason
        sub     sp, sp, #S_FRAME_SIZE
-        stmib   sp, {r1 - lr}
+ ARM(   stmib   sp, {r1 - lr}           )
+ THUMB( stmia   sp, {r0 - r12}          )
+ THUMB( str     sp, [sp, #S_SP]         )
+ THUMB( str     lr, [sp, #S_LR]         )
        mov     r1, #\reason
        .endm
@@ -126,17 +129,24 @@ ENDPROC(__und_invalid)
        .macro  svc_entry, stack_hole=0
 UNWIND(.fnstart                )
 UNWIND(.save {r0 - pc}         )
-        sub     sp, sp, #(S_FRAME_SIZE + \stack_hole)
+        sub     sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
+#ifdef CONFIG_THUMB2_KERNEL
+ SPFIX( str     r0, [sp]        )       @ temporarily saved
+ SPFIX( mov     r0, sp          )
+ SPFIX( tst     r0, #4          )       @ test original stack alignment
+ SPFIX( ldr     r0, [sp]        )       @ restored
+#else
 SPFIX( tst     sp, #4          )
- SPFIX( bicne   sp, sp, #4      )
+#endif
-        stmib   sp, {r1 - r12}
+ SPFIX( subeq   sp, sp, #4      )
+        stmia   sp, {r1 - r12}
        ldmia   r0, {r1 - r3}
-        add     r5, sp, #S_SP           @ here for interlock avoidance
+        add     r5, sp, #S_SP - 4       @ here for interlock avoidance
        mov     r4, #-1                 @  ""  ""      ""       ""
-        add     r0, sp, #(S_FRAME_SIZE + \stack_hole)
+        add     r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
- SPFIX( addne   r0, r0, #4      )
+ SPFIX( addeq   r0, r0, #4      )
-        str     r1, [sp]                @ save the "real" r0 copied
+        str     r1, [sp, #-4]!          @ save the "real" r0 copied
                                        @ from the exception stack
        mov     r1, lr
@@ -151,6 +161,8 @@ ENDPROC(__und_invalid)
        @  r4 - orig_r0 (see pt_regs definition in ptrace.h)
        @
        stmia   r5, {r0 - r4}
+        asm_trace_hardirqs_off
        .endm
        .align  5
@@ -196,9 +208,8 @@ __dabt_svc:
        @
        @ restore SPSR and restart the instruction
        @
-        ldr     r0, [sp, #S_PSR]
+        ldr     r2, [sp, #S_PSR]
-        msr     spsr_cxsf, r0
+        svc_exit r2                             @ return from exception
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
 UNWIND(.fnend          )
 ENDPROC(__dabt_svc)
@@ -206,9 +217,6 @@ ENDPROC(__dabt_svc)
 __irq_svc:
        svc_entry
-#ifdef CONFIG_TRACE_IRQFLAGS
-        bl      trace_hardirqs_off
-#endif
 #ifdef CONFIG_PREEMPT
        get_thread_info tsk
        ldr     r8, [tsk, #TI_PREEMPT]          @ get preempt count
@@ -225,13 +233,12 @@ __irq_svc:
        tst     r0, #_TIF_NEED_RESCHED
        blne    svc_preempt
 #endif
-        ldr     r0, [sp, #S_PSR]                @ irqs are already disabled
+        ldr     r4, [sp, #S_PSR]                @ irqs are already disabled
-        msr     spsr_cxsf, r0
 #ifdef CONFIG_TRACE_IRQFLAGS
-        tst     r0, #PSR_I_BIT
+        tst     r4, #PSR_I_BIT
        bleq    trace_hardirqs_on
 #endif
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        svc_exit r4                             @ return from exception
 UNWIND(.fnend          )
 ENDPROC(__irq_svc)
@@ -266,7 +273,7 @@ __und_svc:
        @  r0 - instruction
        @
        ldr     r0, [r2, #-4]
-        adr     r9, 1f
+        adr     r9, BSYM(1f)
        bl      call_fpe
        mov     r0, sp                          @ struct pt_regs *regs
@@ -280,9 +287,8 @@ __und_svc:
        @
        @ restore SPSR and restart the instruction
        @
-        ldr     lr, [sp, #S_PSR]                @ Get SVC cpsr
+        ldr     r2, [sp, #S_PSR]                @ Get SVC cpsr
-        msr     spsr_cxsf, lr
+        svc_exit r2                             @ return from exception
-        ldmia   sp, {r0 - pc}^                  @ Restore SVC registers
 UNWIND(.fnend          )
 ENDPROC(__und_svc)
@@ -323,9 +329,8 @@ __pabt_svc:
        @
        @ restore SPSR and restart the instruction
        @
-        ldr     r0, [sp, #S_PSR]
+        ldr     r2, [sp, #S_PSR]
-        msr     spsr_cxsf, r0
+        svc_exit r2                             @ return from exception
-        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
 UNWIND(.fnend          )
 ENDPROC(__pabt_svc)
@@ -353,7 +358,8 @@ ENDPROC(__pabt_svc)
 UNWIND(.fnstart        )
 UNWIND(.cantunwind     )       @ don't unwind the user space
        sub     sp, sp, #S_FRAME_SIZE
-        stmib   sp, {r1 - r12}
+ ARM(   stmib   sp, {r1 - r12}  )
+ THUMB( stmia   sp, {r0 - r12}  )
        ldmia   r0, {r1 - r3}
        add     r0, sp, #S_PC           @ here for interlock avoidance
@@ -372,7 +378,8 @@ ENDPROC(__pabt_svc)
        @ Also, separately save sp_usr and lr_usr
        @
        stmia   r0, {r2 - r4}
-        stmdb   r0, {sp, lr}^
+ ARM(   stmdb   r0, {sp, lr}^                   )
+ THUMB( store_user_sp_lr r0, r1, S_SP - S_PC    )
        @
        @ Enable the alignment trap while in kernel mode
@@ -383,6 +390,8 @@ ENDPROC(__pabt_svc)
        @ Clear FP to mark the first stack frame
        @
        zero_fp
+        asm_trace_hardirqs_off
        .endm
        .macro  kuser_cmpxchg_check
@@ -427,7 +436,7 @@ __dabt_usr:
        @
        enable_irq
        mov     r2, sp
-        adr     lr, ret_from_exception
+        adr     lr, BSYM(ret_from_exception)
        b       do_DataAbort
 UNWIND(.fnend          )
 ENDPROC(__dabt_usr)
@@ -437,9 +446,6 @@ __irq_usr:
        usr_entry
        kuser_cmpxchg_check
-#ifdef CONFIG_TRACE_IRQFLAGS
-        bl      trace_hardirqs_off
-#endif
        get_thread_info tsk
 #ifdef CONFIG_PREEMPT
        ldr     r8, [tsk, #TI_PREEMPT]          @ get preempt count
@@ -452,7 +458,9 @@ __irq_usr:
        ldr     r0, [tsk, #TI_PREEMPT]
        str     r8, [tsk, #TI_PREEMPT]
        teq     r0, r7
-        strne   r0, [r0, -r0]
+ ARM(   strne   r0, [r0, -r0]   )
+ THUMB( movne   r0, #0          )
+ THUMB( strne   r0, [r0]        )
 #endif
 #ifdef CONFIG_TRACE_IRQFLAGS
        bl      trace_hardirqs_on
@@ -476,9 +484,10 @@ __und_usr:
        @
        @  r0 - instruction
        @
-        adr     r9, ret_from_exception
+        adr     r9, BSYM(ret_from_exception)
-        adr     lr, __und_usr_unknown
+        adr     lr, BSYM(__und_usr_unknown)
        tst     r3, #PSR_T_BIT                  @ Thumb mode?
+        itet    eq                              @ explicit IT needed for the 1f label
        subeq   r4, r2, #4                      @ ARM instr at LR - 4
        subne   r4, r2, #2                      @ Thumb instr at LR - 2
 1:      ldreqt  r0, [r4]
@@ -488,7 +497,10 @@ __und_usr:
        beq     call_fpe
        @ Thumb instruction
 #if __LINUX_ARM_ARCH__ >= 7
-2:      ldrht   r5, [r4], #2
+2:
+ ARM(   ldrht   r5, [r4], #2    )
+ THUMB( ldrht   r5, [r4]        )
+ THUMB( add     r4, r4, #2      )
        and     r0, r5, #0xf800                 @ mask bits 111x x... .... ....
        cmp     r0, #0xe800                     @ 32bit instruction if xx != 0
        blo     __und_usr_unknown
@@ -577,9 +589,11 @@ call_fpe:
        moveq   pc, lr
        get_thread_info r10                     @ get current thread
        and     r8, r0, #0x00000f00             @ mask out CP number
+ THUMB( lsr     r8, r8, #8              )
        mov     r7, #1
        add     r6, r10, #TI_USED_CP
-        strb    r7, [r6, r8, lsr #8]            @ set appropriate used_cp[]
+ ARM(   strb    r7, [r6, r8, lsr #8]    )       @ set appropriate used_cp[]
+ THUMB( strb    r7, [r6, r8]            )       @ set appropriate used_cp[]
 #ifdef CONFIG_IWMMXT
        @ Test if we need to give access to iWMMXt coprocessors
        ldr     r5, [r10, #TI_FLAGS]
@@ -587,36 +601,38 @@ call_fpe:
        movcss  r7, r5, lsr #(TIF_USING_IWMMXT + 1)
        bcs     iwmmxt_task_enable
 #endif
-        add     pc, pc, r8, lsr #6
+ ARM(   add     pc, pc, r8, lsr #6      )
-        mov     r0, r0
+ THUMB( lsl     r8, r8, #2              )
+ THUMB( add     pc, r8                  )
-        mov     pc, lr                          @ CP#0
+        nop
-        b       do_fpe                          @ CP#1 (FPE)
-        b       do_fpe                          @ CP#2 (FPE)
+        W(mov)  pc, lr                          @ CP#0
-        mov     pc, lr                          @ CP#3
+        W(b)    do_fpe                          @ CP#1 (FPE)
+        W(b)    do_fpe                          @ CP#2 (FPE)
+        W(mov)  pc, lr                          @ CP#3
 #ifdef CONFIG_CRUNCH
        b       crunch_task_enable              @ CP#4 (MaverickCrunch)
        b       crunch_task_enable              @ CP#5 (MaverickCrunch)
        b       crunch_task_enable              @ CP#6 (MaverickCrunch)
 #else
-        mov     pc, lr                          @ CP#4
+        W(mov)  pc, lr                          @ CP#4
-        mov     pc, lr                          @ CP#5
+        W(mov)  pc, lr                          @ CP#5
-        mov     pc, lr                          @ CP#6
+        W(mov)  pc, lr                          @ CP#6
 #endif
-        mov     pc, lr                          @ CP#7
+        W(mov)  pc, lr                          @ CP#7
-        mov     pc, lr                          @ CP#8
+        W(mov)  pc, lr                          @ CP#8
-        mov     pc, lr                          @ CP#9
+        W(mov)  pc, lr                          @ CP#9
 #ifdef CONFIG_VFP
-        b       do_vfp                          @ CP#10 (VFP)
+        W(b)    do_vfp                          @ CP#10 (VFP)
-        b       do_vfp                          @ CP#11 (VFP)
+        W(b)    do_vfp                          @ CP#11 (VFP)
 #else
-        mov     pc, lr                          @ CP#10 (VFP)
+        W(mov)  pc, lr                          @ CP#10 (VFP)
-        mov     pc, lr                          @ CP#11 (VFP)
+        W(mov)  pc, lr                          @ CP#11 (VFP)
 #endif
-        mov     pc, lr                          @ CP#12
+        W(mov)  pc, lr                          @ CP#12
-        mov     pc, lr                          @ CP#13
+        W(mov)  pc, lr                          @ CP#13
-        mov     pc, lr                          @ CP#14 (Debug)
+        W(mov)  pc, lr                          @ CP#14 (Debug)
-        mov     pc, lr                          @ CP#15 (Control)
+        W(mov)  pc, lr                          @ CP#15 (Control)
 #ifdef CONFIG_NEON
        .align  6
@@ -667,7 +683,7 @@ no_fp:	mov	pc, lr
 __und_usr_unknown:
        enable_irq
        mov     r0, sp
-        adr     lr, ret_from_exception
+        adr     lr, BSYM(ret_from_exception)
        b       do_undefinstr
 ENDPROC(__und_usr_unknown)
@@ -711,7 +727,10 @@ ENTRY(__switch_to)
 UNWIND(.cantunwind     )
        add     ip, r1, #TI_CPU_SAVE
        ldr     r3, [r2, #TI_TP_VALUE]
-        stmia   ip!, {r4 - sl, fp, sp, lr}      @ Store most regs on stack
+ ARM(   stmia   ip!, {r4 - sl, fp, sp, lr} )    @ Store most regs on stack
+ THUMB( stmia   ip!, {r4 - sl, fp}         )    @ Store most regs on stack
+ THUMB( str     sp, [ip], #4               )
+ THUMB( str     lr, [ip], #4               )
 #ifdef CONFIG_MMU
        ldr     r6, [r2, #TI_CPU_DOMAIN]
 #endif
@@ -736,8 +755,12 @@ ENTRY(__switch_to)
        ldr     r0, =thread_notify_head
        mov     r1, #THREAD_NOTIFY_SWITCH
        bl      atomic_notifier_call_chain
+ THUMB( mov     ip, r4                     )
        mov     r0, r5
-        ldmia   r4, {r4 - sl, fp, sp, pc}       @ Load all regs saved previously
+ ARM(   ldmia   r4, {r4 - sl, fp, sp, pc}  )    @ Load all regs saved previously
+ THUMB( ldmia   ip!, {r4 - sl, fp}         )    @ Load all regs saved previously
+ THUMB( ldr     sp, [ip], #4               )
+ THUMB( ldr     pc, [ip]                   )
 UNWIND(.fnend          )
 ENDPROC(__switch_to)
@@ -772,6 +795,7 @@ ENDPROC(__switch_to)
 * if your compiled code is not going to use the new instructions for other
 * purpose.
 */
+ THUMB( .arm    )
        .macro  usr_ret, reg
 #ifdef CONFIG_ARM_THUMB
@@ -1020,6 +1044,7 @@ __kuser_helper_version:				@ 0xffff0ffc
        .globl  __kuser_helper_end
 __kuser_helper_end:
+ THUMB( .thumb  )
 /*
 * Vector stubs.
@@ -1054,17 +1079,23 @@ vector_\name:
        @ Prepare for SVC32 mode.  IRQs remain disabled.
        @
        mrs     r0, cpsr
-        eor     r0, r0, #(\mode ^ SVC_MODE)
+        eor     r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
        msr     spsr_cxsf, r0
        @
        @ the branch table must immediately follow this code
        @
        and     lr, lr, #0x0f
+ THUMB( adr     r0, 1f                  )
+ THUMB( ldr     lr, [r0, lr, lsl #2]    )
        mov     r0, sp
-        ldr     lr, [pc, lr, lsl #2]
+ ARM(   ldr     lr, [pc, lr, lsl #2]    )
        movs    pc, lr                  @ branch to handler in SVC mode
 ENDPROC(vector_\name)
+        .align  2
+        @ handler addresses follow this label
+1:
        .endm
        .globl  __stubs_start
@@ -1202,14 +1233,16 @@ __stubs_end:
        .globl  __vectors_start
 __vectors_start:
-        swi     SYS_ERROR0
+ ARM(   swi     SYS_ERROR0      )
-        b       vector_und + stubs_offset
+ THUMB( svc     #0              )
-        ldr     pc, .LCvswi + stubs_offset
+ THUMB( nop                     )
-        b       vector_pabt + stubs_offset
+        W(b)    vector_und + stubs_offset
-        b       vector_dabt + stubs_offset
+        W(ldr)  pc, .LCvswi + stubs_offset
-        b       vector_addrexcptn + stubs_offset
+        W(b)    vector_pabt + stubs_offset
-        b       vector_irq + stubs_offset
+        W(b)    vector_dabt + stubs_offset
-        b       vector_fiq + stubs_offset
+        W(b)    vector_addrexcptn + stubs_offset
+        W(b)    vector_irq + stubs_offset
+        W(b)    vector_fiq + stubs_offset
        .globl  __vectors_end
 __vectors_end:
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index 8c3de1a350b5..807cfebb0f44 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -33,14 +33,7 @@ ret_fast_syscall:
        /* perform architecture specific actions before user return */
        arch_ret_to_user r1, lr
-        @ fast_restore_user_regs
+        restore_user_regs fast = 1, offset = S_OFF
-        ldr     r1, [sp, #S_OFF + S_PSR]        @ get calling cpsr
-        ldr     lr, [sp, #S_OFF + S_PC]!        @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
 UNWIND(.fnend          )
 /*
@@ -51,7 +44,7 @@ fast_work_pending:
 work_pending:
        tst     r1, #_TIF_NEED_RESCHED
        bne     work_resched
-        tst     r1, #_TIF_SIGPENDING
+        tst     r1, #_TIF_SIGPENDING|_TIF_NOTIFY_RESUME
        beq     no_work_pending
        mov     r0, sp                          @ 'regs'
        mov     r2, why                         @ 'syscall'
@@ -73,14 +66,7 @@ no_work_pending:
        /* perform architecture specific actions before user return */
        arch_ret_to_user r1, lr
-        @ slow_restore_user_regs
+        restore_user_regs fast = 0, offset = 0
-        ldr     r1, [sp, #S_PSR]                @ get calling cpsr
-        ldr     lr, [sp, #S_PC]!                @ get pc
-        msr     spsr_cxsf, r1                   @ save in spsr_svc
-        ldmdb   sp, {r0 - lr}^                  @ get calling r0 - lr
-        mov     r0, r0
-        add     sp, sp, #S_FRAME_SIZE - S_PC
-        movs    pc, lr                          @ return & move spsr_svc into cpsr
 ENDPROC(ret_to_user)
 /*
@@ -132,6 +118,25 @@ ftrace_call:
 #else
+ENTRY(__gnu_mcount_nc)
+        stmdb sp!, {r0-r3, lr}
+        ldr r0, =ftrace_trace_function
+        ldr r2, [r0]
+        adr r0, ftrace_stub
+        cmp r0, r2
+        bne gnu_trace
+        ldmia sp!, {r0-r3, ip, lr}
+        bx ip
+gnu_trace:
+        ldr r1, [sp, #20]                       @ lr of instrumented routine
+        mov r0, lr
+        sub r0, r0, #MCOUNT_INSN_SIZE
+        mov lr, pc
+        mov pc, r2
+        ldmia sp!, {r0-r3, ip, lr}
+        bx ip
 ENTRY(mcount)
        stmdb sp!, {r0-r3, lr}
        ldr r0, =ftrace_trace_function
@@ -182,8 +187,10 @@ ftrace_stub:
 ENTRY(vector_swi)
        sub     sp, sp, #S_FRAME_SIZE
        stmia   sp, {r0 - r12}                  @ Calling r0 - r12
-        add     r8, sp, #S_PC
+ ARM(   add     r8, sp, #S_PC           )
-        stmdb   r8, {sp, lr}^                   @ Calling sp, lr
+ ARM(   stmdb   r8, {sp, lr}^           )       @ Calling sp, lr
+ THUMB( mov     r8, sp                  )
+ THUMB( store_user_sp_lr r8, r10, S_SP  )       @ calling sp, lr
        mrs     r8, spsr                        @ called from non-FIQ mode, so ok.
        str     lr, [sp, #S_PC]                 @ Save calling PC
        str     r8, [sp, #S_PSR]                @ Save CPSR
@@ -272,7 +279,7 @@ ENTRY(vector_swi)
        bne     __sys_trace
        cmp     scno, #NR_syscalls              @ check upper syscall limit
-        adr     lr, ret_fast_syscall            @ return address
+        adr     lr, BSYM(ret_fast_syscall)      @ return address
        ldrcc   pc, [tbl, scno, lsl #2]         @ call sys_* routine
        add     r1, sp, #S_OFF
@@ -293,7 +300,7 @@ __sys_trace:
        mov     r0, #0                          @ trace entry [IP = 0]
        bl      syscall_trace
-        adr     lr, __sys_trace_return          @ return address
+        adr     lr, BSYM(__sys_trace_return)    @ return address
        mov     scno, r0                        @ syscall number (possibly new)
        add     r1, sp, #S_R0 + S_OFF           @ pointer to regs
        cmp     scno, #NR_syscalls              @ check upper syscall limit
@@ -373,16 +380,6 @@ sys_clone_wrapper:
                b       sys_clone
 ENDPROC(sys_clone_wrapper)
-sys_sigsuspend_wrapper:
-                add     r3, sp, #S_OFF
-                b       sys_sigsuspend
-ENDPROC(sys_sigsuspend_wrapper)
-sys_rt_sigsuspend_wrapper:
-                add     r2, sp, #S_OFF
-                b       sys_rt_sigsuspend
-ENDPROC(sys_rt_sigsuspend_wrapper)
 sys_sigreturn_wrapper:
                add     r0, sp, #S_OFF
                b       sys_sigreturn
diff --git a/arch/arm/kernel/entry-header.S b/arch/arm/kernel/entry-header.S
index 87ab4e157997..a4eaf4f920c5 100644
--- a/arch/arm/kernel/entry-header.S
+++ b/arch/arm/kernel/entry-header.S
@@ -36,11 +36,6 @@
 #endif
        .endm
-        .macro  get_thread_info, rd
-        mov     \rd, sp, lsr #13
-        mov     \rd, \rd, lsl #13
-        .endm
        .macro  alignment_trap, rtemp
 #ifdef CONFIG_ALIGNMENT_TRAP
        ldr     \rtemp, .LCcralign
@@ -49,6 +44,93 @@
 #endif
        .endm
+        @
+        @ Store/load the USER SP and LR registers by switching to the SYS
+        @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
+        @ available. Should only be called from SVC mode
+        @
+        .macro  store_user_sp_lr, rd, rtemp, offset = 0
+        mrs     \rtemp, cpsr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch to the SYS mode
+        str     sp, [\rd, #\offset]             @ save sp_usr
+        str     lr, [\rd, #\offset + 4]         @ save lr_usr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch back to the SVC mode
+        .endm
+        .macro  load_user_sp_lr, rd, rtemp, offset = 0
+        mrs     \rtemp, cpsr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch to the SYS mode
+        ldr     sp, [\rd, #\offset]             @ load sp_usr
+        ldr     lr, [\rd, #\offset + 4]         @ load lr_usr
+        eor     \rtemp, \rtemp, #(SVC_MODE ^ SYSTEM_MODE)
+        msr     cpsr_c, \rtemp                  @ switch back to the SVC mode
+        .endm
+#ifndef CONFIG_THUMB2_KERNEL
+        .macro  svc_exit, rpsr
+        msr     spsr_cxsf, \rpsr
+        ldmia   sp, {r0 - pc}^                  @ load r0 - pc, cpsr
+        .endm
+        .macro  restore_user_regs, fast = 0, offset = 0
+        ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
+        ldr     lr, [sp, #\offset + S_PC]!      @ get pc
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        .if     \fast
+        ldmdb   sp, {r1 - lr}^                  @ get calling r1 - lr
+        .else
+        ldmdb   sp, {r0 - lr}^                  @ get calling r0 - lr
+        .endif
+        add     sp, sp, #S_FRAME_SIZE - S_PC
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        .endm
+        .macro  get_thread_info, rd
+        mov     \rd, sp, lsr #13
+        mov     \rd, \rd, lsl #13
+        .endm
+#else   /* CONFIG_THUMB2_KERNEL */
+        .macro  svc_exit, rpsr
+        ldr     r0, [sp, #S_SP]                 @ top of the stack
+        ldr     r1, [sp, #S_PC]                 @ return address
+        tst     r0, #4                          @ orig stack 8-byte aligned?
+        stmdb   r0, {r1, \rpsr}                 @ rfe context
+        ldmia   sp, {r0 - r12}
+        ldr     lr, [sp, #S_LR]
+        addeq   sp, sp, #S_FRAME_SIZE - 8       @ aligned
+        addne   sp, sp, #S_FRAME_SIZE - 4       @ not aligned
+        rfeia   sp!
+        .endm
+        .macro  restore_user_regs, fast = 0, offset = 0
+        mov     r2, sp
+        load_user_sp_lr r2, r3, \offset + S_SP  @ calling sp, lr
+        ldr     r1, [sp, #\offset + S_PSR]      @ get calling cpsr
+        ldr     lr, [sp, #\offset + S_PC]       @ get pc
+        add     sp, sp, #\offset + S_SP
+        msr     spsr_cxsf, r1                   @ save in spsr_svc
+        .if     \fast
+        ldmdb   sp, {r1 - r12}                  @ get calling r1 - r12
+        .else
+        ldmdb   sp, {r0 - r12}                  @ get calling r0 - r12
+        .endif
+        add     sp, sp, #S_FRAME_SIZE - S_SP
+        movs    pc, lr                          @ return & move spsr_svc into cpsr
+        .endm
+        .macro  get_thread_info, rd
+        mov     \rd, sp
+        lsr     \rd, \rd, #13
+        mov     \rd, \rd, lsl #13
+        .endm
+#endif  /* !CONFIG_THUMB2_KERNEL */
 /*
 * These are the registers used in the syscall handler, and allow us to
diff --git a/arch/arm/kernel/head-common.S b/arch/arm/kernel/head-common.S
index 991952c644d1..93ad576b2d74 100644
--- a/arch/arm/kernel/head-common.S
+++ b/arch/arm/kernel/head-common.S
@@ -14,6 +14,7 @@
 #define ATAG_CORE 0x54410001
 #define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
+        .align  2
        .type   __switch_data, %object
 __switch_data:
        .long   __mmap_switched
@@ -51,7 +52,9 @@ __mmap_switched:
        strcc   fp, [r6],#4
        bcc     1b
-        ldmia   r3, {r4, r5, r6, r7, sp}
+ ARM(   ldmia   r3, {r4, r5, r6, r7, sp})
+ THUMB( ldmia   r3, {r4, r5, r6, r7}    )
+ THUMB( ldr     sp, [r3, #16]           )
        str     r9, [r4]                        @ Save processor ID
        str     r1, [r5]                        @ Save machine type
        str     r2, [r6]                        @ Save atags pointer
@@ -155,7 +158,8 @@ ENDPROC(__error)
 */
 __lookup_processor_type:
        adr     r3, 3f
-        ldmda   r3, {r5 - r7}
+        ldmia   r3, {r5 - r7}
+        add     r3, r3, #8
        sub     r3, r3, r7                      @ get offset between virt&phys
        add     r5, r5, r3                      @ convert virt addresses to
        add     r6, r6, r3                      @ physical address space
@@ -185,9 +189,10 @@ ENDPROC(lookup_processor_type)
 * Look in <asm/procinfo.h> and arch/arm/kernel/arch.[ch] for
 * more information about the __proc_info and __arch_info structures.
 */
-        .long   __proc_info_begin
+        .align  2
+3:      .long   __proc_info_begin
        .long   __proc_info_end
-3:      .long   .
+4:      .long   .
        .long   __arch_info_begin
        .long   __arch_info_end
@@ -203,7 +208,7 @@ ENDPROC(lookup_processor_type)
 *  r5 = mach_info pointer in physical address space
 */
 __lookup_machine_type:
-        adr     r3, 3b
+        adr     r3, 4b
        ldmia   r3, {r4, r5, r6}
        sub     r3, r3, r4                      @ get offset between virt&phys
        add     r5, r5, r3                      @ convert virt addresses to
diff --git a/arch/arm/kernel/head-nommu.S b/arch/arm/kernel/head-nommu.S
index cc87e1765ed2..e5dfc2895e24 100644
--- a/arch/arm/kernel/head-nommu.S
+++ b/arch/arm/kernel/head-nommu.S
@@ -34,7 +34,7 @@
 */
        .section ".text.head", "ax"
 ENTRY(stext)
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                @ and irqs disabled
 #ifndef CONFIG_CPU_CP15
        ldr     r9, =CONFIG_PROCESSOR_ID
@@ -50,8 +50,10 @@ ENTRY(stext)
        ldr     r13, __switch_data              @ address to jump to after
                                                @ the initialization is done
-        adr     lr, __after_proc_init           @ return (PIC) address
+        adr     lr, BSYM(__after_proc_init)     @ return (PIC) address
-        add     pc, r10, #PROCINFO_INITFUNC
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(stext)
 /*
@@ -59,7 +61,10 @@ ENDPROC(stext)
 */
 __after_proc_init:
 #ifdef CONFIG_CPU_CP15
-        mrc     p15, 0, r0, c1, c0, 0           @ read control reg
+        /*
+         * CP15 system control register value returned in r0 from
+         * the CPU init function.
+         */
 #ifdef CONFIG_ALIGNMENT_TRAP
        orr     r0, r0, #CR_A
 #else
@@ -82,7 +87,8 @@ __after_proc_init:
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
 #endif /* CONFIG_CPU_CP15 */
-        mov     pc, r13                         @ clear the BSS and jump
+        mov     r3, r13
+        mov     pc, r3                          @ clear the BSS and jump
                                                @ to start_kernel
 ENDPROC(__after_proc_init)
        .ltorg
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 21e17dc94cb5..38ccbe1d3b2c 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -76,7 +76,7 @@
 */
        .section ".text.head", "ax"
 ENTRY(stext)
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
                                                @ and irqs disabled
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
@@ -97,8 +97,10 @@ ENTRY(stext)
         */
        ldr     r13, __switch_data              @ address to jump to after
                                                @ mmu has been enabled
-        adr     lr, __enable_mmu                @ return (PIC) address
+        adr     lr, BSYM(__enable_mmu)          @ return (PIC) address
-        add     pc, r10, #PROCINFO_INITFUNC
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     )
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(stext)
 #if defined(CONFIG_SMP)
@@ -110,7 +112,7 @@ ENTRY(secondary_startup)
         * the processor type - there is no need to check the machine type
         * as it has already been validated by the primary processor.
         */
-        msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
+        setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
        mrc     p15, 0, r9, c0, c0              @ get processor id
        bl      __lookup_processor_type
        movs    r10, r5                         @ invalid processor?
@@ -121,12 +123,15 @@ ENTRY(secondary_startup)
         * Use the page tables supplied from  __cpu_up.
         */
        adr     r4, __secondary_data
-        ldmia   r4, {r5, r7, r13}               @ address to jump to after
+        ldmia   r4, {r5, r7, r12}               @ address to jump to after
        sub     r4, r4, r5                      @ mmu has been enabled
        ldr     r4, [r7, r4]                    @ get secondary_data.pgdir
-        adr     lr, __enable_mmu                @ return address
+        adr     lr, BSYM(__enable_mmu)          @ return address
-        add     pc, r10, #PROCINFO_INITFUNC     @ initialise processor
+        mov     r13, r12                        @ __secondary_switched address
-                                                @ (return control reg)
+ ARM(   add     pc, r10, #PROCINFO_INITFUNC     ) @ initialise processor
+                                                  @ (return control reg)
+ THUMB( add     r12, r10, #PROCINFO_INITFUNC    )
+ THUMB( mov     pc, r12                         )
 ENDPROC(secondary_startup)
        /*
@@ -193,8 +198,8 @@ __turn_mmu_on:
        mcr     p15, 0, r0, c1, c0, 0           @ write control reg
        mrc     p15, 0, r3, c0, c0, 0           @ read id reg
        mov     r3, r3
-        mov     r3, r3
+        mov     r3, r13
-        mov     pc, r13
+        mov     pc, r3
 ENDPROC(__turn_mmu_on)
@@ -235,7 +240,8 @@ __create_page_tables:
         * will be removed by paging_init().  We use our current program
         * counter to determine corresponding section base address.
         */
-        mov     r6, pc, lsr #20                 @ start of kernel section
+        mov     r6, pc
+        mov     r6, r6, lsr #20                 @ start of kernel section
        orr     r3, r7, r6, lsl #20             @ flags + kernel base
        str     r3, [r4, r6, lsl #2]            @ identity mapping
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index b7c3490eaa24..c9a8619f3856 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -86,7 +86,7 @@ int show_interrupts(struct seq_file *p, void *v)
 unlock:
                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
        } else if (i == NR_IRQS) {
-#ifdef CONFIG_ARCH_ACORN
+#ifdef CONFIG_FIQ
                show_fiq_list(p, v);
 #endif
 #ifdef CONFIG_SMP
diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c
index bac03c81489d..f28c5e9c51ea 100644
--- a/arch/arm/kernel/module.c
+++ b/arch/arm/kernel/module.c
@@ -102,6 +102,7 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                unsigned long loc;
                Elf32_Sym *sym;
                s32 offset;
+                u32 upper, lower, sign, j1, j2;
                offset = ELF32_R_SYM(rel->r_info);
                if (offset < 0 || offset > (symsec->sh_size / sizeof(Elf32_Sym))) {
@@ -184,6 +185,58 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex,
                                        (offset & 0x0fff);
                        break;
+                case R_ARM_THM_CALL:
+                case R_ARM_THM_JUMP24:
+                        upper = *(u16 *)loc;
+                        lower = *(u16 *)(loc + 2);
+                        /*
+                         * 25 bit signed address range (Thumb-2 BL and B.W
+                         * instructions):
+                         *   S:I1:I2:imm10:imm11:0
+                         * where:
+                         *   S     = upper[10]   = offset[24]
+                         *   I1    = ~(J1 ^ S)   = offset[23]
+                         *   I2    = ~(J2 ^ S)   = offset[22]
+                         *   imm10 = upper[9:0]  = offset[21:12]
+                         *   imm11 = lower[10:0] = offset[11:1]
+                         *   J1    = lower[13]
+                         *   J2    = lower[11]
+                         */
+                        sign = (upper >> 10) & 1;
+                        j1 = (lower >> 13) & 1;
+                        j2 = (lower >> 11) & 1;
+                        offset = (sign << 24) | ((~(j1 ^ sign) & 1) << 23) |
+                                ((~(j2 ^ sign) & 1) << 22) |
+                                ((upper & 0x03ff) << 12) |
+                                ((lower & 0x07ff) << 1);
+                        if (offset & 0x01000000)
+                                offset -= 0x02000000;
+                        offset += sym->st_value - loc;
+                        /* only Thumb addresses allowed (no interworking) */
+                        if (!(offset & 1) ||
+                            offset <= (s32)0xff000000 ||
+                            offset >= (s32)0x01000000) {
+                                printk(KERN_ERR
+                                       "%s: relocation out of range, section "
+                                       "%d reloc %d sym '%s'\n", module->name,
+                                       relindex, i, strtab + sym->st_name);
+                                return -ENOEXEC;
+                        }
+                        sign = (offset >> 24) & 1;
+                        j1 = sign ^ (~(offset >> 23) & 1);
+                        j2 = sign ^ (~(offset >> 22) & 1);
+                        *(u16 *)loc = (u16)((upper & 0xf800) | (sign << 10) |
+                                            ((offset >> 12) & 0x03ff));
+                        *(u16 *)(loc + 2) = (u16)((lower & 0xd000) |
+                                                  (j1 << 13) | (j2 << 11) |
+                                                  ((offset >> 1) & 0x07ff));
+                        upper = *(u16 *)loc;
+                        lower = *(u16 *)(loc + 2);
+                        break;
                default:
                        printk(KERN_ERR "%s: unknown relocation: %u\n",
                               module->name, ELF32_R_TYPE(rel->r_info));
diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
index 39196dff478c..790fbee92ec5 100644
--- a/arch/arm/kernel/process.c
+++ b/arch/arm/kernel/process.c
@@ -388,7 +388,7 @@ pid_t kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
        regs.ARM_r2 = (unsigned long)fn;
        regs.ARM_r3 = (unsigned long)kernel_thread_exit;
        regs.ARM_pc = (unsigned long)kernel_thread_helper;
-        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE;
+        regs.ARM_cpsr = SVC_MODE | PSR_ENDSTATE | PSR_ISETSTATE;
        return do_fork(flags|CLONE_VM|CLONE_UNTRACED, 0, &regs, 0, NULL, NULL);
 }
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 89882a1d0187..a2ea3854cb3c 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -521,7 +521,13 @@ static int ptrace_read_user(struct task_struct *tsk, unsigned long off,
                return -EIO;
        tmp = 0;
-        if (off < sizeof(struct pt_regs))
+        if (off == PT_TEXT_ADDR)
+                tmp = tsk->mm->start_code;
+        else if (off == PT_DATA_ADDR)
+                tmp = tsk->mm->start_data;
+        else if (off == PT_TEXT_END_ADDR)
+                tmp = tsk->mm->end_code;
+        else if (off < sizeof(struct pt_regs))
                tmp = get_user_reg(tsk, off >> 2);
        return put_user(tmp, ret);
diff --git a/arch/arm/kernel/return_address.c b/arch/arm/kernel/return_address.c
new file mode 100644
index 000000000000..df246da4ceca
--- /dev/null
+++ b/arch/arm/kernel/return_address.c
@@ -0,0 +1,71 @@
+/*
+ * arch/arm/kernel/return_address.c
+ *
+ * Copyright (C) 2009 Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ * for Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+#include <linux/module.h>
+#if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND)
+#include <linux/sched.h>
+#include <asm/stacktrace.h>
+struct return_address_data {
+        unsigned int level;
+        void *addr;
+};
+static int save_return_addr(struct stackframe *frame, void *d)
+{
+        struct return_address_data *data = d;
+        if (!data->level) {
+                data->addr = (void *)frame->lr;
+                return 1;
+        } else {
+                --data->level;
+                return 0;
+        }
+}
+void *return_address(unsigned int level)
+{
+        struct return_address_data data;
+        struct stackframe frame;
+        register unsigned long current_sp asm ("sp");
+        data.level = level + 1;
+        frame.fp = (unsigned long)__builtin_frame_address(0);
+        frame.sp = current_sp;
+        frame.lr = (unsigned long)__builtin_return_address(0);
+        frame.pc = (unsigned long)return_address;
+        walk_stackframe(&frame, save_return_addr, &data);
+        if (!data.level)
+                return data.addr;
+        else
+                return NULL;
+}
+#else /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) */
+#if defined(CONFIG_ARM_UNWIND)
+#warning "TODO: return_address should use unwind tables"
+#endif
+void *return_address(unsigned int level)
+{
+        return NULL;
+}
+#endif /* if defined(CONFIG_FRAME_POINTER) && !defined(CONFIG_ARM_UNWIND) / else */
+EXPORT_SYMBOL_GPL(return_address);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index bc5e4128f9f3..d4d4f77c91b2 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -25,6 +25,7 @@
 #include <linux/smp.h>
 #include <linux/fs.h>
+#include <asm/unified.h>
 #include <asm/cpu.h>
 #include <asm/cputype.h>
 #include <asm/elf.h>
@@ -327,25 +328,38 @@ void cpu_init(void)
        }
        /*
+         * Define the placement constraint for the inline asm directive below.
+         * In Thumb-2, msr with an immediate value is not allowed.
+         */
+#ifdef CONFIG_THUMB2_KERNEL
+#define PLC     "r"
+#else
+#define PLC     "I"
+#endif
+        /*
         * setup stacks for re-entrant exception handlers
         */
        __asm__ (
        "msr    cpsr_c, %1\n\t"
-        "add    sp, %0, %2\n\t"
+        "add    r14, %0, %2\n\t"
+        "mov    sp, r14\n\t"
        "msr    cpsr_c, %3\n\t"
-        "add    sp, %0, %4\n\t"
+        "add    r14, %0, %4\n\t"
+        "mov    sp, r14\n\t"
        "msr    cpsr_c, %5\n\t"
-        "add    sp, %0, %6\n\t"
+        "add    r14, %0, %6\n\t"
+        "mov    sp, r14\n\t"
        "msr    cpsr_c, %7"
            :
            : "r" (stk),
-              "I" (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | IRQ_MODE),
              "I" (offsetof(struct stack, irq[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | ABT_MODE),
              "I" (offsetof(struct stack, abt[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | UND_MODE),
+              PLC (PSR_F_BIT | PSR_I_BIT | UND_MODE),
              "I" (offsetof(struct stack, und[0])),
-              "I" (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
+              PLC (PSR_F_BIT | PSR_I_BIT | SVC_MODE)
            : "r14");
 }
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index f6bc5d442782..1423a3419789 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -12,6 +12,7 @@
 #include <linux/personality.h>
 #include <linux/freezer.h>
 #include <linux/uaccess.h>
+#include <linux/tracehook.h>
 #include <asm/elf.h>
 #include <asm/cacheflush.h>
@@ -47,57 +48,22 @@ const unsigned long sigreturn_codes[7] = {
        MOV_R7_NR_RT_SIGRETURN, SWI_SYS_RT_SIGRETURN, SWI_THUMB_RT_SIGRETURN,
 };
-static int do_signal(sigset_t *oldset, struct pt_regs * regs, int syscall);
 /*
 * atomically swap in the new signal mask, and wait for a signal.
 */
-asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask, struct pt_regs *regs)
+asmlinkage int sys_sigsuspend(int restart, unsigned long oldmask, old_sigset_t mask)
 {
-        sigset_t saveset;
        mask &= _BLOCKABLE;
        spin_lock_irq(&current->sighand->siglock);
-        saveset = current->blocked;
+        current->saved_sigmask = current->blocked;
        siginitset(&current->blocked, mask);
        recalc_sigpending();
        spin_unlock_irq(&current->sighand->siglock);
-        regs->ARM_r0 = -EINTR;
-        while (1) {
+        current->state = TASK_INTERRUPTIBLE;
-                current->state = TASK_INTERRUPTIBLE;
+        schedule();
-                schedule();
+        set_restore_sigmask();
-                if (do_signal(&saveset, regs, 0))
+        return -ERESTARTNOHAND;
-                        return regs->ARM_r0;
-        }
-}
-asmlinkage int
-sys_rt_sigsuspend(sigset_t __user *unewset, size_t sigsetsize, struct pt_regs *regs)
-{
-        sigset_t saveset, newset;
-        /* XXX: Don't preclude handling different sized sigset_t's. */
-        if (sigsetsize != sizeof(sigset_t))
-                return -EINVAL;
-        if (copy_from_user(&newset, unewset, sizeof(newset)))
-                return -EFAULT;
-        sigdelsetmask(&newset, ~_BLOCKABLE);
-        spin_lock_irq(&current->sighand->siglock);
-        saveset = current->blocked;
-        current->blocked = newset;
-        recalc_sigpending();
-        spin_unlock_irq(&current->sighand->siglock);
-        regs->ARM_r0 = -EINTR;
-        while (1) {
-                current->state = TASK_INTERRUPTIBLE;
-                schedule();
-                if (do_signal(&saveset, regs, 0))
-                        return regs->ARM_r0;
-        }
 }
 asmlinkage int 
@@ -545,7 +511,7 @@ static inline void setup_syscall_restart(struct pt_regs *regs)
 /*
 * OK, we're invoking a handler
 */     
-static void
+static int
 handle_signal(unsigned long sig, struct k_sigaction *ka,
              siginfo_t *info, sigset_t *oldset,
              struct pt_regs * regs, int syscall)
@@ -596,7 +562,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
        if (ret != 0) {
                force_sigsegv(sig, tsk);
-                return;
+                return ret;
        }
        /*
@@ -610,6 +576,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
        recalc_sigpending();
        spin_unlock_irq(&tsk->sighand->siglock);
+        return 0;
 }
 /*
@@ -621,7 +588,7 @@ handle_signal(unsigned long sig, struct k_sigaction *ka,
 * the kernel can handle, and then we build all the user-level signal handling
 * stack-frames in one go after that.
 */
-static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
+static void do_signal(struct pt_regs *regs, int syscall)
 {
        struct k_sigaction ka;
        siginfo_t info;
@@ -634,7 +601,7 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
         * if so.
         */
        if (!user_mode(regs))
-                return 0;
+                return;
        if (try_to_freeze())
                goto no_signal;
@@ -643,9 +610,24 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
        signr = get_signal_to_deliver(&info, &ka, regs, NULL);
        if (signr > 0) {
-                handle_signal(signr, &ka, &info, oldset, regs, syscall);
+                sigset_t *oldset;
+                if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                        oldset = &current->saved_sigmask;
+                else
+                        oldset = &current->blocked;
+                if (handle_signal(signr, &ka, &info, oldset, regs, syscall) == 0) {
+                        /*
+                         * A signal was successfully delivered; the saved
+                         * sigmask will have been stored in the signal frame,
+                         * and will be restored by sigreturn, so we can simply
+                         * clear the TIF_RESTORE_SIGMASK flag.
+                         */
+                        if (test_thread_flag(TIF_RESTORE_SIGMASK))
+                                clear_thread_flag(TIF_RESTORE_SIGMASK);
+                }
                single_step_set(current);
-                return 1;
+                return;
        }
 no_signal:
@@ -697,14 +679,28 @@ static int do_signal(sigset_t *oldset, struct pt_regs *regs, int syscall)
                    regs->ARM_r0 == -ERESTARTNOINTR) {
                        setup_syscall_restart(regs);
                }
+                /* If there's no signal to deliver, we just put the saved sigmask
+                 * back.
+                 */
+                if (test_thread_flag(TIF_RESTORE_SIGMASK)) {
+                        clear_thread_flag(TIF_RESTORE_SIGMASK);
+                        sigprocmask(SIG_SETMASK, &current->saved_sigmask, NULL);
+                }
        }
        single_step_set(current);
-        return 0;
 }
 asmlinkage void
 do_notify_resume(struct pt_regs *regs, unsigned int thread_flags, int syscall)
 {
        if (thread_flags & _TIF_SIGPENDING)
-                do_signal(&current->blocked, regs, syscall);
+                do_signal(regs, syscall);
+        if (thread_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/arm/kernel/stacktrace.c b/arch/arm/kernel/stacktrace.c
index 9f444e5cc165..20b7411e47fd 100644
--- a/arch/arm/kernel/stacktrace.c
+++ b/arch/arm/kernel/stacktrace.c
@@ -21,7 +21,7 @@
 * Note that with framepointer enabled, even the leaf functions have the same
 * prologue and epilogue, therefore we can ignore the LR value in this case.
 */
-int unwind_frame(struct stackframe *frame)
+int notrace unwind_frame(struct stackframe *frame)
 {
        unsigned long high, low;
        unsigned long fp = frame->fp;
@@ -43,7 +43,7 @@ int unwind_frame(struct stackframe *frame)
 }
 #endif
-void walk_stackframe(struct stackframe *frame,
+void notrace walk_stackframe(struct stackframe *frame,
                     int (*fn)(struct stackframe *, void *), void *data)
 {
        while (1) {
diff --git a/arch/arm/kernel/unwind.c b/arch/arm/kernel/unwind.c
index dd56e11f339a..39baf1128bfa 100644
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -62,7 +62,11 @@ struct unwind_ctrl_block {
 };
 enum regs {
+#ifdef CONFIG_THUMB2_KERNEL
+        FP = 7,
+#else
        FP = 11,
+#endif
        SP = 13,
        LR = 14,
        PC = 15
diff --git a/arch/arm/lib/ashldi3.S b/arch/arm/lib/ashldi3.S
index 1154d924080b..638deb13da1c 100644
--- a/arch/arm/lib/ashldi3.S
+++ b/arch/arm/lib/ashldi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_llsl)
        rsb     ip, r2, #32
        movmi   ah, ah, lsl r2
        movpl   ah, al, lsl r3
-        orrmi   ah, ah, al, lsr ip
+ ARM(   orrmi   ah, ah, al, lsr ip      )
+ THUMB( lsrmi   r3, al, ip              )
+ THUMB( orrmi   ah, ah, r3              )
        mov     al, al, lsl r2
        mov     pc, lr
diff --git a/arch/arm/lib/ashrdi3.S b/arch/arm/lib/ashrdi3.S
index 9f8b35572f8c..015e8aa5a1d1 100644
--- a/arch/arm/lib/ashrdi3.S
+++ b/arch/arm/lib/ashrdi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_lasr)
        rsb     ip, r2, #32
        movmi   al, al, lsr r2
        movpl   al, ah, asr r3
-        orrmi   al, al, ah, lsl ip
+ ARM(   orrmi   al, al, ah, lsl ip      )
+ THUMB( lslmi   r3, ah, ip              )
+ THUMB( orrmi   al, al, r3              )
        mov     ah, ah, asr r2
        mov     pc, lr
diff --git a/arch/arm/lib/backtrace.S b/arch/arm/lib/backtrace.S
index b0951d0e8b2c..aaf7220d9e30 100644
--- a/arch/arm/lib/backtrace.S
+++ b/arch/arm/lib/backtrace.S
@@ -38,7 +38,9 @@ ENDPROC(c_backtrace)
                beq     no_frame                @ we have no stack frames
                tst     r1, #0x10               @ 26 or 32-bit mode?
-                moveq   mask, #0xfc000003       @ mask for 26-bit
+ ARM(           moveq   mask, #0xfc000003       )
+ THUMB(         moveq   mask, #0xfc000000       )
+ THUMB(         orreq   mask, #0x03             )
                movne   mask, #0                @ mask for 32-bit
 1:              stmfd   sp!, {pc}               @ calculate offset of PC stored
@@ -126,7 +128,9 @@ ENDPROC(c_backtrace)
                mov     reg, #10
                mov     r7, #0
 1:              mov     r3, #1
-                tst     instr, r3, lsl reg
+ ARM(           tst     instr, r3, lsl reg      )
+ THUMB(         lsl     r3, reg                 )
+ THUMB(         tst     instr, r3               )
                beq     2f
                add     r7, r7, #1
                teq     r7, #6
diff --git a/arch/arm/lib/bitops.h b/arch/arm/lib/bitops.h
index c7f2627385e7..d42252918bfb 100644
--- a/arch/arm/lib/bitops.h
+++ b/arch/arm/lib/bitops.h
@@ -60,8 +60,8 @@
        tst     r2, r0, lsl r3
        \instr  r2, r2, r0, lsl r3
        \store  r2, [r1]
-        restore_irqs ip
        moveq   r0, #0
+        restore_irqs ip
        mov     pc, lr
        .endm
 #endif
diff --git a/arch/arm/lib/clear_user.S b/arch/arm/lib/clear_user.S
index 844f56785ebc..1279abd8b886 100644
--- a/arch/arm/lib/clear_user.S
+++ b/arch/arm/lib/clear_user.S
@@ -27,21 +27,20 @@ WEAK(__clear_user)
                ands    ip, r0, #3
                beq     1f
                cmp     ip, #2
-USER(           strbt   r2, [r0], #1)
+                strusr  r2, r0, 1
-USER(           strlebt r2, [r0], #1)
+                strusr  r2, r0, 1, le
-USER(           strltbt r2, [r0], #1)
+                strusr  r2, r0, 1, lt
                rsb     ip, ip, #4
                sub     r1, r1, ip              @  7  6  5  4  3  2  1
 1:              subs    r1, r1, #8              @ -1 -2 -3 -4 -5 -6 -7
-USER(           strplt  r2, [r0], #4)
+                strusr  r2, r0, 4, pl, rept=2
-USER(           strplt  r2, [r0], #4)
                bpl     1b
                adds    r1, r1, #4              @  3  2  1  0 -1 -2 -3
-USER(           strplt  r2, [r0], #4)
+                strusr  r2, r0, 4, pl
 2:              tst     r1, #2                  @ 1x 1x 0x 0x 1x 1x 0x
-USER(           strnebt r2, [r0], #1)
+                strusr  r2, r0, 1, ne, rept=2
-USER(           strnebt r2, [r0], #1)
                tst     r1, #1                  @ x1 x0 x1 x0 x1 x0 x1
+                it      ne                      @ explicit IT needed for the label
 USER(           strnebt r2, [r0])
                mov     r0, #0
                ldmfd   sp!, {r1, pc}
diff --git a/arch/arm/lib/copy_from_user.S b/arch/arm/lib/copy_from_user.S
index 56799a165cc4..e4fe124acedc 100644
--- a/arch/arm/lib/copy_from_user.S
+++ b/arch/arm/lib/copy_from_user.S
@@ -33,11 +33,15 @@
 *      Number of bytes NOT copied.
 */
+#ifndef CONFIG_THUMB2_KERNEL
+#define LDR1W_SHIFT     0
+#else
+#define LDR1W_SHIFT     1
+#endif
+#define STR1W_SHIFT     0
        .macro ldr1w ptr reg abort
-100:    ldrt \reg, [\ptr], #4
+        ldrusr  \reg, \ptr, 4, abort=\abort
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
        .endm
        .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -53,14 +57,11 @@
        .endm
        .macro ldr1b ptr reg cond=al abort
-100:    ldr\cond\()bt \reg, [\ptr], #1
+        ldrusr  \reg, \ptr, 1, \cond, abort=\abort
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
        .endm
        .macro str1w ptr reg abort
-        str \reg, [\ptr], #4
+        W(str) \reg, [\ptr], #4
        .endm
        .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
diff --git a/arch/arm/lib/copy_template.S b/arch/arm/lib/copy_template.S
index 139cce646055..805e3f8fb007 100644
--- a/arch/arm/lib/copy_template.S
+++ b/arch/arm/lib/copy_template.S
@@ -57,6 +57,13 @@
 *
 *      Restore registers with the values previously saved with the
 *      'preserv' macro. Called upon code termination.
+ *
+ * LDR1W_SHIFT
+ * STR1W_SHIFT
+ *
+ *      Correction to be applied to the "ip" register when branching into
+ *      the ldr1w or str1w instructions (some of these macros may expand to
+ *      than one 32bit instruction in Thumb-2)
 */
@@ -99,9 +106,15 @@
 5:              ands    ip, r2, #28
                rsb     ip, ip, #32
+#if LDR1W_SHIFT > 0
+                lsl     ip, ip, #LDR1W_SHIFT
+#endif
                addne   pc, pc, ip              @ C is always clear here
                b       7f
-6:              nop
+6:
+                .rept   (1 << LDR1W_SHIFT)
+                W(nop)
+                .endr
                ldr1w   r1, r3, abort=20f
                ldr1w   r1, r4, abort=20f
                ldr1w   r1, r5, abort=20f
@@ -110,9 +123,16 @@
                ldr1w   r1, r8, abort=20f
                ldr1w   r1, lr, abort=20f
+#if LDR1W_SHIFT < STR1W_SHIFT
+                lsl     ip, ip, #STR1W_SHIFT - LDR1W_SHIFT
+#elif LDR1W_SHIFT > STR1W_SHIFT
+                lsr     ip, ip, #LDR1W_SHIFT - STR1W_SHIFT
+#endif
                add     pc, pc, ip
                nop
-                nop
+                .rept   (1 << STR1W_SHIFT)
+                W(nop)
+                .endr
                str1w   r0, r3, abort=20f
                str1w   r0, r4, abort=20f
                str1w   r0, r5, abort=20f
diff --git a/arch/arm/lib/copy_to_user.S b/arch/arm/lib/copy_to_user.S
index 878820f0a320..1a71e1584442 100644
--- a/arch/arm/lib/copy_to_user.S
+++ b/arch/arm/lib/copy_to_user.S
@@ -33,8 +33,15 @@
 *      Number of bytes NOT copied.
 */
+#define LDR1W_SHIFT     0
+#ifndef CONFIG_THUMB2_KERNEL
+#define STR1W_SHIFT     0
+#else
+#define STR1W_SHIFT     1
+#endif
        .macro ldr1w ptr reg abort
-        ldr \reg, [\ptr], #4
+        W(ldr) \reg, [\ptr], #4
        .endm
        .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -50,10 +57,7 @@
        .endm
        .macro str1w ptr reg abort
-100:    strt \reg, [\ptr], #4
+        strusr  \reg, \ptr, 4, abort=\abort
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
        .endm
        .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
@@ -68,10 +72,7 @@
        .endm
        .macro str1b ptr reg cond=al abort
-100:    str\cond\()bt \reg, [\ptr], #1
+        strusr  \reg, \ptr, 1, \cond, abort=\abort
-        .section __ex_table, "a"
-        .long 100b, \abort
-        .previous
        .endm
        .macro enter reg1 reg2
diff --git a/arch/arm/lib/csumpartialcopyuser.S b/arch/arm/lib/csumpartialcopyuser.S
index 14677fb4b0c4..fd0e9dcd9fdc 100644
--- a/arch/arm/lib/csumpartialcopyuser.S
+++ b/arch/arm/lib/csumpartialcopyuser.S
@@ -26,50 +26,28 @@
                .endm
                .macro  load1b, reg1
-9999:           ldrbt   \reg1, [r0], $1
+                ldrusr  \reg1, r0, 1
-                .section __ex_table, "a"
-                .align  3
-                .long   9999b, 6001f
-                .previous
                .endm
                .macro  load2b, reg1, reg2
-9999:           ldrbt   \reg1, [r0], $1
+                ldrusr  \reg1, r0, 1
-9998:           ldrbt   \reg2, [r0], $1
+                ldrusr  \reg2, r0, 1
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .previous
                .endm
                .macro  load1l, reg1
-9999:           ldrt    \reg1, [r0], $4
+                ldrusr  \reg1, r0, 4
-                .section __ex_table, "a"
-                .align  3
-                .long   9999b, 6001f
-                .previous
                .endm
                .macro  load2l, reg1, reg2
-9999:           ldrt    \reg1, [r0], $4
+                ldrusr  \reg1, r0, 4
-9998:           ldrt    \reg2, [r0], $4
+                ldrusr  \reg2, r0, 4
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .previous
                .endm
                .macro  load4l, reg1, reg2, reg3, reg4
-9999:           ldrt    \reg1, [r0], $4
+                ldrusr  \reg1, r0, 4
-9998:           ldrt    \reg2, [r0], $4
+                ldrusr  \reg2, r0, 4
-9997:           ldrt    \reg3, [r0], $4
+                ldrusr  \reg3, r0, 4
-9996:           ldrt    \reg4, [r0], $4
+                ldrusr  \reg4, r0, 4
-                .section __ex_table, "a"
-                .long   9999b, 6001f
-                .long   9998b, 6001f
-                .long   9997b, 6001f
-                .long   9996b, 6001f
-                .previous
                .endm
 /*
@@ -92,14 +70,14 @@
 */
                .section .fixup,"ax"
                .align  4
-6001:           mov     r4, #-EFAULT
+9001:           mov     r4, #-EFAULT
                ldr     r5, [fp, #4]            @ *err_ptr
                str     r4, [r5]
                ldmia   sp, {r1, r2}            @ retrieve dst, len
                add     r2, r2, r1
                mov     r0, #0                  @ zero the buffer
-6002:           teq     r2, r1
+9002:           teq     r2, r1
                strneb  r0, [r1], #1
-                bne     6002b
+                bne     9002b
                load_regs
                .previous
diff --git a/arch/arm/lib/div64.S b/arch/arm/lib/div64.S
index 1425e789ba86..faa7748142da 100644
--- a/arch/arm/lib/div64.S
+++ b/arch/arm/lib/div64.S
@@ -177,7 +177,9 @@ ENTRY(__do_div64)
        mov     yh, xh, lsr ip
        mov     yl, xl, lsr ip
        rsb     ip, ip, #32
-        orr     yl, yl, xh, lsl ip
+ ARM(   orr     yl, yl, xh, lsl ip      )
+ THUMB( lsl     xh, xh, ip              )
+ THUMB( orr     yl, yl, xh              )
        mov     xh, xl, lsl ip
        mov     xh, xh, lsr ip
        mov     pc, lr
diff --git a/arch/arm/lib/findbit.S b/arch/arm/lib/findbit.S
index 8c4defc4f3c4..1e4cbd4e7be9 100644
--- a/arch/arm/lib/findbit.S
+++ b/arch/arm/lib/findbit.S
@@ -25,7 +25,10 @@ ENTRY(_find_first_zero_bit_le)
                teq     r1, #0  
                beq     3f
                mov     r2, #0
-1:              ldrb    r3, [r0, r2, lsr #3]
+1:
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                eors    r3, r3, #0xff           @ invert bits
                bne     .L_found                @ any now set - found zero bit
                add     r2, r2, #8              @ next bit pointer
@@ -44,7 +47,9 @@ ENTRY(_find_next_zero_bit_le)
                beq     3b
                ands    ip, r2, #7
                beq     1b                      @ If new byte, goto old routine
-                ldrb    r3, [r0, r2, lsr #3]
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                eor     r3, r3, #0xff           @ now looking for a 1 bit
                movs    r3, r3, lsr ip          @ shift off unused bits
                bne     .L_found
@@ -61,7 +66,10 @@ ENTRY(_find_first_bit_le)
                teq     r1, #0  
                beq     3f
                mov     r2, #0
-1:              ldrb    r3, [r0, r2, lsr #3]
+1:
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                movs    r3, r3
                bne     .L_found                @ any now set - found zero bit
                add     r2, r2, #8              @ next bit pointer
@@ -80,7 +88,9 @@ ENTRY(_find_next_bit_le)
                beq     3b
                ands    ip, r2, #7
                beq     1b                      @ If new byte, goto old routine
-                ldrb    r3, [r0, r2, lsr #3]
+ ARM(           ldrb    r3, [r0, r2, lsr #3]    )
+ THUMB(         lsr     r3, r2, #3              )
+ THUMB(         ldrb    r3, [r0, r3]            )
                movs    r3, r3, lsr ip          @ shift off unused bits
                bne     .L_found
                orr     r2, r2, #7              @ if zero, then no bits here
@@ -95,7 +105,9 @@ ENTRY(_find_first_zero_bit_be)
                beq     3f
                mov     r2, #0
 1:              eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                eors    r3, r3, #0xff           @ invert bits
                bne     .L_found                @ any now set - found zero bit
                add     r2, r2, #8              @ next bit pointer
@@ -111,7 +123,9 @@ ENTRY(_find_next_zero_bit_be)
                ands    ip, r2, #7
                beq     1b                      @ If new byte, goto old routine
                eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                eor     r3, r3, #0xff           @ now looking for a 1 bit
                movs    r3, r3, lsr ip          @ shift off unused bits
                bne     .L_found
@@ -125,7 +139,9 @@ ENTRY(_find_first_bit_be)
                beq     3f
                mov     r2, #0
 1:              eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                movs    r3, r3
                bne     .L_found                @ any now set - found zero bit
                add     r2, r2, #8              @ next bit pointer
@@ -141,7 +157,9 @@ ENTRY(_find_next_bit_be)
                ands    ip, r2, #7
                beq     1b                      @ If new byte, goto old routine
                eor     r3, r2, #0x18           @ big endian byte ordering
-                ldrb    r3, [r0, r3, lsr #3]
+ ARM(           ldrb    r3, [r0, r3, lsr #3]    )
+ THUMB(         lsr     r3, #3                  )
+ THUMB(         ldrb    r3, [r0, r3]            )
                movs    r3, r3, lsr ip          @ shift off unused bits
                bne     .L_found
                orr     r2, r2, #7              @ if zero, then no bits here
diff --git a/arch/arm/lib/getuser.S b/arch/arm/lib/getuser.S
index 6763088b7607..a1814d927122 100644
--- a/arch/arm/lib/getuser.S
+++ b/arch/arm/lib/getuser.S
@@ -36,8 +36,13 @@ ENTRY(__get_user_1)
 ENDPROC(__get_user_1)
 ENTRY(__get_user_2)
+#ifdef CONFIG_THUMB2_KERNEL
+2:      ldrbt   r2, [r0]
+3:      ldrbt   r3, [r0, #1]
+#else
 2:      ldrbt   r2, [r0], #1
 3:      ldrbt   r3, [r0]
+#endif
 #ifndef __ARMEB__
        orr     r2, r2, r3, lsl #8
 #else
diff --git a/arch/arm/lib/io-writesw-armv4.S b/arch/arm/lib/io-writesw-armv4.S
index d6585612c86b..ff4f71b579ee 100644
--- a/arch/arm/lib/io-writesw-armv4.S
+++ b/arch/arm/lib/io-writesw-armv4.S
@@ -75,7 +75,10 @@ ENTRY(__raw_writesw)
 #endif
 .Loutsw_noalign:
-                ldr     r3, [r1, -r3]!
+ ARM(           ldr     r3, [r1, -r3]!  )
+ THUMB(         rsb     r3, r3, #0      )
+ THUMB(         ldr     r3, [r1, r3]    )
+ THUMB(         sub     r1, r3          )
                subcs   r2, r2, #1
                bcs     2f
                subs    r2, r2, #2
diff --git a/arch/arm/lib/lshrdi3.S b/arch/arm/lib/lshrdi3.S
index 99ea338bf87c..f83d449141f7 100644
--- a/arch/arm/lib/lshrdi3.S
+++ b/arch/arm/lib/lshrdi3.S
@@ -43,7 +43,9 @@ ENTRY(__aeabi_llsr)
        rsb     ip, r2, #32
        movmi   al, al, lsr r2
        movpl   al, ah, lsr r3
-        orrmi   al, al, ah, lsl ip
+ ARM(   orrmi   al, al, ah, lsl ip      )
+ THUMB( lslmi   r3, ah, ip              )
+ THUMB( orrmi   al, al, r3              )
        mov     ah, ah, lsr r2
        mov     pc, lr
diff --git a/arch/arm/lib/memcpy.S b/arch/arm/lib/memcpy.S
index e0d002641d3f..a9b9e2287a09 100644
--- a/arch/arm/lib/memcpy.S
+++ b/arch/arm/lib/memcpy.S
@@ -13,8 +13,11 @@
 #include <linux/linkage.h>
 #include <asm/assembler.h>
+#define LDR1W_SHIFT     0
+#define STR1W_SHIFT     0
        .macro ldr1w ptr reg abort
-        ldr \reg, [\ptr], #4
+        W(ldr) \reg, [\ptr], #4
        .endm
        .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
@@ -30,7 +33,7 @@
        .endm
        .macro str1w ptr reg abort
-        str \reg, [\ptr], #4
+        W(str) \reg, [\ptr], #4
        .endm
        .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
diff --git a/arch/arm/lib/memmove.S b/arch/arm/lib/memmove.S
index 12549187088c..5025c863713d 100644
--- a/arch/arm/lib/memmove.S
+++ b/arch/arm/lib/memmove.S
@@ -75,24 +75,24 @@ ENTRY(memmove)
                addne   pc, pc, ip              @ C is always clear here
                b       7f
 6:              nop
-                ldr     r3, [r1, #-4]!
+                W(ldr)  r3, [r1, #-4]!
-                ldr     r4, [r1, #-4]!
+                W(ldr)  r4, [r1, #-4]!
-                ldr     r5, [r1, #-4]!
+                W(ldr)  r5, [r1, #-4]!
-                ldr     r6, [r1, #-4]!
+                W(ldr)  r6, [r1, #-4]!
-                ldr     r7, [r1, #-4]!
+                W(ldr)  r7, [r1, #-4]!
-                ldr     r8, [r1, #-4]!
+                W(ldr)  r8, [r1, #-4]!
-                ldr     lr, [r1, #-4]!
+                W(ldr)  lr, [r1, #-4]!
                add     pc, pc, ip
                nop
                nop
-                str     r3, [r0, #-4]!
+                W(str)  r3, [r0, #-4]!
-                str     r4, [r0, #-4]!
+                W(str)  r4, [r0, #-4]!
-                str     r5, [r0, #-4]!
+                W(str)  r5, [r0, #-4]!
-                str     r6, [r0, #-4]!
+                W(str)  r6, [r0, #-4]!
-                str     r7, [r0, #-4]!
+                W(str)  r7, [r0, #-4]!
-                str     r8, [r0, #-4]!
+                W(str)  r8, [r0, #-4]!
-                str     lr, [r0, #-4]!
+                W(str)  lr, [r0, #-4]!
        CALGN(  bcs     2b                      )
diff --git a/arch/arm/lib/putuser.S b/arch/arm/lib/putuser.S
index 864f3c1c4f18..02fedbf07c0d 100644
--- a/arch/arm/lib/putuser.S
+++ b/arch/arm/lib/putuser.S
@@ -37,6 +37,15 @@ ENDPROC(__put_user_1)
 ENTRY(__put_user_2)
        mov     ip, r2, lsr #8
+#ifdef CONFIG_THUMB2_KERNEL
+#ifndef __ARMEB__
+2:      strbt   r2, [r0]
+3:      strbt   ip, [r0, #1]
+#else
+2:      strbt   ip, [r0]
+3:      strbt   r2, [r0, #1]
+#endif
+#else   /* !CONFIG_THUMB2_KERNEL */
 #ifndef __ARMEB__
 2:      strbt   r2, [r0], #1
 3:      strbt   ip, [r0]
@@ -44,6 +53,7 @@ ENTRY(__put_user_2)
 2:      strbt   ip, [r0], #1
 3:      strbt   r2, [r0]
 #endif
+#endif  /* CONFIG_THUMB2_KERNEL */
        mov     r0, #0
        mov     pc, lr
 ENDPROC(__put_user_2)
@@ -55,8 +65,13 @@ ENTRY(__put_user_4)
 ENDPROC(__put_user_4)
 ENTRY(__put_user_8)
+#ifdef CONFIG_THUMB2_KERNEL
+5:      strt    r2, [r0]
+6:      strt    r3, [r0, #4]
+#else
 5:      strt    r2, [r0], #4
 6:      strt    r3, [r0]
+#endif
        mov     r0, #0
        mov     pc, lr
 ENDPROC(__put_user_8)
diff --git a/arch/arm/lib/sha1.S b/arch/arm/lib/sha1.S
index a16fb208c841..09b548cac1a4 100644
--- a/arch/arm/lib/sha1.S
+++ b/arch/arm/lib/sha1.S
@@ -187,6 +187,7 @@ ENTRY(sha_transform)
 ENDPROC(sha_transform)
+        .align  2
 .L_sha_K:
        .word   0x5a827999, 0x6ed9eba1, 0x8f1bbcdc, 0xca62c1d6
@@ -195,6 +196,7 @@ ENDPROC(sha_transform)
 * void sha_init(__u32 *buf)
 */
+        .align  2
 .L_sha_initial_digest:
        .word   0x67452301, 0xefcdab89, 0x98badcfe, 0x10325476, 0xc3d2e1f0
diff --git a/arch/arm/lib/strncpy_from_user.S b/arch/arm/lib/strncpy_from_user.S
index 330373c26dd9..1c9814f346c6 100644
--- a/arch/arm/lib/strncpy_from_user.S
+++ b/arch/arm/lib/strncpy_from_user.S
@@ -23,7 +23,7 @@
 ENTRY(__strncpy_from_user)
        mov     ip, r1
 1:      subs    r2, r2, #1
-USER(   ldrplbt r3, [r1], #1)
+        ldrusr  r3, r1, 1, pl
        bmi     2f
        strb    r3, [r0], #1
        teq     r3, #0
diff --git a/arch/arm/lib/strnlen_user.S b/arch/arm/lib/strnlen_user.S
index 90bb9d020836..7855b2906659 100644
--- a/arch/arm/lib/strnlen_user.S
+++ b/arch/arm/lib/strnlen_user.S
@@ -23,7 +23,7 @@
 ENTRY(__strnlen_user)
        mov     r2, r0
 1:
-USER(   ldrbt   r3, [r0], #1)
+        ldrusr  r3, r0, 1
        teq     r3, #0
        beq     2f
        subs    r1, r1, #1
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 323b47f2b52f..a24d824c428b 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -23,6 +23,12 @@ config ARCH_AT91SAM9261
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+config ARCH_AT91SAM9G10
+        bool "AT91SAM9G10"
+        select CPU_ARM926T
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 config ARCH_AT91SAM9263
        bool "AT91SAM9263"
        select CPU_ARM926T
@@ -41,6 +47,12 @@ config ARCH_AT91SAM9G20
        select GENERIC_TIME
        select GENERIC_CLOCKEVENTS
+config ARCH_AT91SAM9G45
+        bool "AT91SAM9G45"
+        select CPU_ARM926T
+        select GENERIC_TIME
+        select GENERIC_CLOCKEVENTS
 config ARCH_AT91CAP9
        bool "AT91CAP9"
        select CPU_ARM926T
@@ -144,6 +156,13 @@ config MACH_YL9200
        help
          Select this if you are using the ucDragon YL-9200 board.
+config MACH_CPUAT91
+        bool "Eukrea CPUAT91"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using the Eukrea Electromatique's
+          CPUAT91 board <http://www.eukrea.com/>.
 endif
 # ----------------------------------------------------------
@@ -205,6 +224,13 @@ config MACH_QIL_A9260
          Select this if you are using a Calao Systems QIL-A9260 Board.
          <http://www.calao-systems.com>
+config MACH_CPU9260
+        bool "Eukrea CPU9260 board"
+        depends on ARCH_AT91SAM9260
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9260 Board <http://www.eukrea.com/>
 endif
 # ----------------------------------------------------------
@@ -224,6 +250,21 @@ endif
 # ----------------------------------------------------------
+if ARCH_AT91SAM9G10
+comment "AT91SAM9G10 Board Type"
+config MACH_AT91SAM9G10EK
+        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+        depends on ARCH_AT91SAM9G10
+        help
+          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
+endif
+# ----------------------------------------------------------
 if ARCH_AT91SAM9263
 comment "AT91SAM9263 Board Type"
@@ -276,6 +317,29 @@ config MACH_AT91SAM9G20EK
        help
          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit.
+config MACH_CPU9G20
+        bool "Eukrea CPU9G20 board"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9G20 Board <http://www.eukrea.com/>
+endif
+# ----------------------------------------------------------
+if ARCH_AT91SAM9G45
+comment "AT91SAM9G45 Board Type"
+config MACH_AT91SAM9G45EKES
+        bool "Atmel AT91SAM9G45-EKES Evaluation Kit"
+        depends on ARCH_AT91SAM9G45
+        help
+          Select this if you are using Atmel's AT91SAM9G45-EKES Evaluation Kit.
+          "ES" at the end of the name means that this board is an
+          Engineering Sample.
 endif
 # ----------------------------------------------------------
@@ -315,13 +379,13 @@ comment "AT91 Board Options"
 config MTD_AT91_DATAFLASH_CARD
        bool "Enable DataFlash Card support"
-        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926)
+        depends on (ARCH_AT91RM9200DK || MACH_AT91RM9200EK || MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_ECBAT91 || MACH_SAM9_L9260 || MACH_AT91CAP9ADK || MACH_NEOCORE926)
        help
          Enable support for the DataFlash card.
 config MTD_NAND_ATMEL_BUSWIDTH_16
        bool "Enable 16-bit data bus interface to NAND flash"
-        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91CAP9ADK)
+        depends on (MACH_AT91SAM9260EK || MACH_AT91SAM9261EK || MACH_AT91SAM9G10EK || MACH_AT91SAM9263EK || MACH_AT91SAM9G20EK || MACH_AT91SAM9G45EKES || MACH_AT91CAP9ADK)
        help
          On AT91SAM926x boards both types of NAND flash can be present
          (8 and 16 bit data bus width).
@@ -383,7 +447,7 @@ config AT91_EARLY_USART2
 config AT91_EARLY_USART3
        bool "USART3"
-        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+        depends on (ARCH_AT91RM9200 || ARCH_AT91SAM9RL || ARCH_AT91SAM9260 || ARCH_AT91SAM9G20 || ARCH_AT91SAM9G45)
 config AT91_EARLY_USART4
        bool "USART4"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index c69ff237fd14..a6ed015d82ed 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -13,9 +13,11 @@ obj-$(CONFIG_AT91_PMC_UNIT)	+= clock.o
 obj-$(CONFIG_ARCH_AT91RM9200)   += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o
 obj-$(CONFIG_ARCH_AT91SAM9260)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9261)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
+obj-$(CONFIG_ARCH_AT91SAM9G10)  += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9263)  += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9RL)   += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91SAM9G20)  += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o  sam9_smc.o
+ obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91CAP9)     += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o
 obj-$(CONFIG_ARCH_AT91X40)      += at91x40.o at91x40_time.o
@@ -32,6 +34,7 @@ obj-$(CONFIG_MACH_KAFA)		+= board-kafa.o
 obj-$(CONFIG_MACH_PICOTUX2XX)   += board-picotux200.o
 obj-$(CONFIG_MACH_ECBAT91)      += board-ecbat91.o
 obj-$(CONFIG_MACH_YL9200)       += board-yl-9200.o
+obj-$(CONFIG_MACH_CPUAT91)      += board-cpuat91.o
 # AT91SAM9260 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o
@@ -40,9 +43,11 @@ obj-$(CONFIG_MACH_SAM9_L9260)	+= board-sam9-l9260.o
 obj-$(CONFIG_MACH_USB_A9260)    += board-usb-a9260.o
 obj-$(CONFIG_MACH_QIL_A9260)    += board-qil-a9260.o
 obj-$(CONFIG_MACH_AFEB9260)     += board-afeb-9260v1.o
+obj-$(CONFIG_MACH_CPU9260)      += board-cpu9krea.o
 # AT91SAM9261 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9261EK) += board-sam9261ek.o
+obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o
 # AT91SAM9263 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o
@@ -54,6 +59,10 @@ obj-$(CONFIG_MACH_AT91SAM9RLEK)	+= board-sam9rlek.o
 # AT91SAM9G20 board-specific support
 obj-$(CONFIG_MACH_AT91SAM9G20EK) += board-sam9g20ek.o
+obj-$(CONFIG_MACH_CPU9G20)      += board-cpu9krea.o
+# AT91SAM9G45 board-specific support
+obj-$(CONFIG_MACH_AT91SAM9G45EKES) += board-sam9m10g45ek.o
 # AT91CAP9 board-specific support
 obj-$(CONFIG_MACH_AT91CAP9ADK)  += board-cap9adk.o
diff --git a/arch/arm/mach-at91/Makefile.boot b/arch/arm/mach-at91/Makefile.boot
index 071a2506a69f..3462b815054a 100644
--- a/arch/arm/mach-at91/Makefile.boot
+++ b/arch/arm/mach-at91/Makefile.boot
@@ -7,6 +7,10 @@ ifeq ($(CONFIG_ARCH_AT91CAP9),y)
   zreladdr-y   := 0x70008000
 params_phys-y   := 0x70000100
 initrd_phys-y   := 0x70410000
+else ifeq ($(CONFIG_ARCH_AT91SAM9G45),y)
+   zreladdr-y   := 0x70008000
+params_phys-y   := 0x70000100
+initrd_phys-y   := 0x70410000
 else
   zreladdr-y   := 0x20008000
 params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index d74c9ac007e7..ee4ea0e720cf 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -1113,6 +1113,122 @@ void __init at91_set_serial_console(unsigned portnr) {}
 void __init at91_add_device_serial(void) {}
 #endif
+/* --------------------------------------------------------------------
+ *  CF/IDE
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE) || \
+        defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE) || \
+        defined(CONFIG_AT91_CF) || defined(CONFIG_AT91_CF_MODULE)
+static struct at91_cf_data cf0_data;
+static struct resource cf0_resources[] = {
+        [0] = {
+                .start  = AT91_CHIPSELECT_4,
+                .end    = AT91_CHIPSELECT_4 + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device cf0_device = {
+        .id             = 0,
+        .dev            = {
+                                .platform_data  = &cf0_data,
+        },
+        .resource       = cf0_resources,
+        .num_resources  = ARRAY_SIZE(cf0_resources),
+};
+static struct at91_cf_data cf1_data;
+static struct resource cf1_resources[] = {
+        [0] = {
+                .start  = AT91_CHIPSELECT_5,
+                .end    = AT91_CHIPSELECT_5 + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device cf1_device = {
+        .id             = 1,
+        .dev            = {
+                                .platform_data  = &cf1_data,
+        },
+        .resource       = cf1_resources,
+        .num_resources  = ARRAY_SIZE(cf1_resources),
+};
+void __init at91_add_device_cf(struct at91_cf_data *data)
+{
+        struct platform_device *pdev;
+        unsigned long csa;
+        if (!data)
+                return;
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        switch (data->chipselect) {
+        case 4:
+                at91_set_multi_drive(AT91_PIN_PC8, 0);
+                at91_set_A_periph(AT91_PIN_PC8, 0);
+                csa |= AT91_MATRIX_CS4A_SMC_CF1;
+                cf0_data = *data;
+                pdev = &cf0_device;
+                break;
+        case 5:
+                at91_set_multi_drive(AT91_PIN_PC9, 0);
+                at91_set_A_periph(AT91_PIN_PC9, 0);
+                csa |= AT91_MATRIX_CS5A_SMC_CF2;
+                cf1_data = *data;
+                pdev = &cf1_device;
+                break;
+        default:
+                printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
+                       data->chipselect);
+                return;
+        }
+        at91_sys_write(AT91_MATRIX_EBICSA, csa);
+        if (data->rst_pin) {
+                at91_set_multi_drive(data->rst_pin, 0);
+                at91_set_gpio_output(data->rst_pin, 1);
+        }
+        if (data->irq_pin) {
+                at91_set_gpio_input(data->irq_pin, 0);
+                at91_set_deglitch(data->irq_pin, 1);
+        }
+        if (data->det_pin) {
+                at91_set_gpio_input(data->det_pin, 0);
+                at91_set_deglitch(data->det_pin, 1);
+        }
+        at91_set_B_periph(AT91_PIN_PC6, 0);     /* CFCE1 */
+        at91_set_B_periph(AT91_PIN_PC7, 0);     /* CFCE2 */
+        at91_set_A_periph(AT91_PIN_PC10, 0);    /* CFRNW */
+        at91_set_A_periph(AT91_PIN_PC15, 1);    /* NWAIT */
+        if (data->flags & AT91_CF_TRUE_IDE)
+#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
+                pdev->name = "pata_at91";
+#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
+                pdev->name = "at91_ide";
+#else
+#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
+#endif
+        else
+                pdev->name = "at91_cf";
+        platform_device_register(pdev);
+}
+#else
+void __init at91_add_device_cf(struct at91_cf_data * data) {}
+#endif
 /* -------------------------------------------------------------------- */
 /*
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 3acd7d7e6a42..4ecf37996c77 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -16,6 +16,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <mach/cpu.h>
 #include <mach/at91sam9261.h>
 #include <mach/at91_pmc.h>
 #include <mach/at91_rstc.h>
@@ -30,7 +31,11 @@ static struct map_desc at91sam9261_io_desc[] __initdata = {
                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
                .length         = SZ_16K,
                .type           = MT_DEVICE,
-        }, {
+        },
+};
+static struct map_desc at91sam9261_sram_desc[] __initdata = {
+        {
                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9261_SRAM_SIZE,
                .pfn            = __phys_to_pfn(AT91SAM9261_SRAM_BASE),
                .length         = AT91SAM9261_SRAM_SIZE,
@@ -38,6 +43,15 @@ static struct map_desc at91sam9261_io_desc[] __initdata = {
        },
 };
+static struct map_desc at91sam9g10_sram_desc[] __initdata = {
+        {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G10_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G10_SRAM_BASE),
+                .length         = AT91SAM9G10_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
 /* --------------------------------------------------------------------
 *  Clocks
 * -------------------------------------------------------------------- */
@@ -263,6 +277,12 @@ void __init at91sam9261_initialize(unsigned long main_clock)
        /* Map peripherals */
        iotable_init(at91sam9261_io_desc, ARRAY_SIZE(at91sam9261_io_desc));
+        if (cpu_is_at91sam9g10())
+                iotable_init(at91sam9g10_sram_desc, ARRAY_SIZE(at91sam9g10_sram_desc));
+        else
+                iotable_init(at91sam9261_sram_desc, ARRAY_SIZE(at91sam9261_sram_desc));
        at91_arch_reset = at91sam9261_reset;
        pm_power_off = at91sam9261_poweroff;
        at91_extern_irq = (1 << AT91SAM9261_ID_IRQ0) | (1 << AT91SAM9261_ID_IRQ1)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index b7f233242315..55719a974276 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -707,9 +707,9 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
 *  AC97
 * -------------------------------------------------------------------- */
-#if defined(CONFIG_SND_AT91_AC97) || defined(CONFIG_SND_AT91_AC97_MODULE)
+#if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
 static u64 ac97_dmamask = DMA_BIT_MASK(32);
-static struct atmel_ac97_data ac97_data;
+static struct ac97c_platform_data ac97_data;
 static struct resource ac97_resources[] = {
        [0] = {
@@ -725,8 +725,8 @@ static struct resource ac97_resources[] = {
 };
 static struct platform_device at91sam9263_ac97_device = {
-        .name           = "ac97c",
+        .name           = "atmel_ac97c",
-        .id             = 1,
+        .id             = 0,
        .dev            = {
                                .dma_mask               = &ac97_dmamask,
                                .coherent_dma_mask      = DMA_BIT_MASK(32),
@@ -736,7 +736,7 @@ static struct platform_device at91sam9263_ac97_device = {
        .num_resources  = ARRAY_SIZE(ac97_resources),
 };
-void __init at91_add_device_ac97(struct atmel_ac97_data *data)
+void __init at91_add_device_ac97(struct ac97c_platform_data *data)
 {
        if (!data)
                return;
@@ -750,11 +750,11 @@ void __init at91_add_device_ac97(struct atmel_ac97_data *data)
        if (data->reset_pin)
                at91_set_gpio_output(data->reset_pin, 0);
-        ac97_data = *ek_data;
+        ac97_data = *data;
        platform_device_register(&at91sam9263_ac97_device);
 }
 #else
-void __init at91_add_device_ac97(struct atmel_ac97_data *data) {}
+void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
 #endif
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
new file mode 100644
index 000000000000..85166b7e69a1
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -0,0 +1,360 @@
+/*
+ *  Chip-specific setup code for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2009 Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <linux/module.h>
+#include <linux/pm.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/at91sam9g45.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_rstc.h>
+#include <mach/at91_shdwc.h>
+#include "generic.h"
+#include "clock.h"
+static struct map_desc at91sam9g45_io_desc[] __initdata = {
+        {
+                .virtual        = AT91_VA_BASE_SYS,
+                .pfn            = __phys_to_pfn(AT91_BASE_SYS),
+                .length         = SZ_16K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = AT91_IO_VIRT_BASE - AT91SAM9G45_SRAM_SIZE,
+                .pfn            = __phys_to_pfn(AT91SAM9G45_SRAM_BASE),
+                .length         = AT91SAM9G45_SRAM_SIZE,
+                .type           = MT_DEVICE,
+        }
+};
+/* --------------------------------------------------------------------
+ *  Clocks
+ * -------------------------------------------------------------------- */
+/*
+ * The peripheral clocks.
+ */
+static struct clk pioA_clk = {
+        .name           = "pioA_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+        .name           = "pioB_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+        .name           = "pioC_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIOC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioDE_clk = {
+        .name           = "pioDE_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PIODE,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+        .name           = "usart0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+        .name           = "usart1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+        .name           = "usart2_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US2,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart3_clk = {
+        .name           = "usart3_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_US3,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc0_clk = {
+        .name           = "mci0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_MCI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi0_clk = {
+        .name           = "twi0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TWI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi1_clk = {
+        .name           = "twi1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TWI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi0_clk = {
+        .name           = "spi0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SPI0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi1_clk = {
+        .name           = "spi1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SPI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc0_clk = {
+        .name           = "ssc0_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SSC0,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ssc1_clk = {
+        .name           = "ssc1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_SSC1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tcb_clk = {
+        .name           = "tcb_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TCB,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pwm_clk = {
+        .name           = "pwm_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_PWMC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk tsc_clk = {
+        .name           = "tsc_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_TSC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk dma_clk = {
+        .name           = "dma_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_DMA,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk uhphs_clk = {
+        .name           = "uhphs_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_UHPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk lcdc_clk = {
+        .name           = "lcdc_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_LCDC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ac97_clk = {
+        .name           = "ac97_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_AC97C,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk macb_clk = {
+        .name           = "macb_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_EMAC,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk isi_clk = {
+        .name           = "isi_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_ISI,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk udphs_clk = {
+        .name           = "udphs_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_UDPHS,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc1_clk = {
+        .name           = "mci1_clk",
+        .pmc_mask       = 1 << AT91SAM9G45_ID_MCI1,
+        .type           = CLK_TYPE_PERIPHERAL,
+};
+/* One additional fake clock for ohci */
+static struct clk ohci_clk = {
+        .name           = "ohci_clk",
+        .pmc_mask       = 0,
+        .type           = CLK_TYPE_PERIPHERAL,
+        .parent         = &uhphs_clk,
+};
+static struct clk *periph_clocks[] __initdata = {
+        &pioA_clk,
+        &pioB_clk,
+        &pioC_clk,
+        &pioDE_clk,
+        &usart0_clk,
+        &usart1_clk,
+        &usart2_clk,
+        &usart3_clk,
+        &mmc0_clk,
+        &twi0_clk,
+        &twi1_clk,
+        &spi0_clk,
+        &spi1_clk,
+        &ssc0_clk,
+        &ssc1_clk,
+        &tcb_clk,
+        &pwm_clk,
+        &tsc_clk,
+        &dma_clk,
+        &uhphs_clk,
+        &lcdc_clk,
+        &ac97_clk,
+        &macb_clk,
+        &isi_clk,
+        &udphs_clk,
+        &mmc1_clk,
+        // irq0
+        &ohci_clk,
+};
+/*
+ * The two programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+        .name           = "pck0",
+        .pmc_mask       = AT91_PMC_PCK0,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 0,
+};
+static struct clk pck1 = {
+        .name           = "pck1",
+        .pmc_mask       = AT91_PMC_PCK1,
+        .type           = CLK_TYPE_PROGRAMMABLE,
+        .id             = 1,
+};
+static void __init at91sam9g45_register_clocks(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+                clk_register(periph_clocks[i]);
+        clk_register(&pck0);
+        clk_register(&pck1);
+}
+/* --------------------------------------------------------------------
+ *  GPIO
+ * -------------------------------------------------------------------- */
+static struct at91_gpio_bank at91sam9g45_gpio[] = {
+        {
+                .id             = AT91SAM9G45_ID_PIOA,
+                .offset         = AT91_PIOA,
+                .clock          = &pioA_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIOB,
+                .offset         = AT91_PIOB,
+                .clock          = &pioB_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIOC,
+                .offset         = AT91_PIOC,
+                .clock          = &pioC_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIODE,
+                .offset         = AT91_PIOD,
+                .clock          = &pioDE_clk,
+        }, {
+                .id             = AT91SAM9G45_ID_PIODE,
+                .offset         = AT91_PIOE,
+                .clock          = &pioDE_clk,
+        }
+};
+static void at91sam9g45_reset(void)
+{
+        at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_PROCRST | AT91_RSTC_PERRST);
+}
+static void at91sam9g45_poweroff(void)
+{
+        at91_sys_write(AT91_SHDW_CR, AT91_SHDW_KEY | AT91_SHDW_SHDW);
+}
+/* --------------------------------------------------------------------
+ *  AT91SAM9G45 processor initialization
+ * -------------------------------------------------------------------- */
+void __init at91sam9g45_initialize(unsigned long main_clock)
+{
+        /* Map peripherals */
+        iotable_init(at91sam9g45_io_desc, ARRAY_SIZE(at91sam9g45_io_desc));
+        at91_arch_reset = at91sam9g45_reset;
+        pm_power_off = at91sam9g45_poweroff;
+        at91_extern_irq = (1 << AT91SAM9G45_ID_IRQ0);
+        /* Init clock subsystem */
+        at91_clock_init(main_clock);
+        /* Register the processor-specific clocks */
+        at91sam9g45_register_clocks();
+        /* Register GPIO subsystem */
+        at91_gpio_init(at91sam9g45_gpio, 5);
+}
+/* --------------------------------------------------------------------
+ *  Interrupt initialization
+ * -------------------------------------------------------------------- */
+/*
+ * The default interrupt priority levels (0 = lowest, 7 = highest).
+ */
+static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = {
+        7,      /* Advanced Interrupt Controller (FIQ) */
+        7,      /* System Peripherals */
+        1,      /* Parallel IO Controller A */
+        1,      /* Parallel IO Controller B */
+        1,      /* Parallel IO Controller C */
+        1,      /* Parallel IO Controller D and E */
+        0,
+        5,      /* USART 0 */
+        5,      /* USART 1 */
+        5,      /* USART 2 */
+        5,      /* USART 3 */
+        0,      /* Multimedia Card Interface 0 */
+        6,      /* Two-Wire Interface 0 */
+        6,      /* Two-Wire Interface 1 */
+        5,      /* Serial Peripheral Interface 0 */
+        5,      /* Serial Peripheral Interface 1 */
+        4,      /* Serial Synchronous Controller 0 */
+        4,      /* Serial Synchronous Controller 1 */
+        0,      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+        0,      /* Pulse Width Modulation Controller */
+        0,      /* Touch Screen Controller */
+        0,      /* DMA Controller */
+        2,      /* USB Host High Speed port */
+        3,      /* LDC Controller */
+        5,      /* AC97 Controller */
+        3,      /* Ethernet */
+        0,      /* Image Sensor Interface */
+        2,      /* USB Device High speed port */
+        0,
+        0,      /* Multimedia Card Interface 1 */
+        0,
+        0,      /* Advanced Interrupt Controller (IRQ0) */
+};
+void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])
+{
+        if (!priority)
+                priority = at91sam9g45_default_irq_priority;
+        /* Initialize the AIC interrupt controller */
+        at91_aic_init(priority);
+        /* Enable GPIO interrupts */
+        at91_gpio_irq_setup();
+}
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
new file mode 100644
index 000000000000..d746e8621bc2
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -0,0 +1,1230 @@
+/*
+ *  On-Chip devices setup code for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2009 Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/i2c-gpio.h>
+#include <linux/fb.h>
+#include <video/atmel_lcdc.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9g45.h>
+#include <mach/at91sam9g45_matrix.h>
+#include <mach/at91sam9_smc.h>
+#include "generic.h"
+/* --------------------------------------------------------------------
+ *  USB Host (OHCI)
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
+static u64 ohci_dmamask = DMA_BIT_MASK(32);
+static struct at91_usbh_data usbh_ohci_data;
+static struct resource usbh_ohci_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_OHCI_BASE,
+                .end    = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_UHPHS,
+                .end    = AT91SAM9G45_ID_UHPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91_usbh_ohci_device = {
+        .name           = "at91_ohci",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &ohci_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &usbh_ohci_data,
+        },
+        .resource       = usbh_ohci_resources,
+        .num_resources  = ARRAY_SIZE(usbh_ohci_resources),
+};
+void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
+{
+        int i;
+        if (!data)
+                return;
+        /* Enable VBus control for UHP ports */
+        for (i = 0; i < data->ports; i++) {
+                if (data->vbus_pin[i])
+                        at91_set_gpio_output(data->vbus_pin[i], 0);
+        }
+        usbh_ohci_data = *data;
+        platform_device_register(&at91_usbh_ohci_device);
+}
+#else
+void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  USB HS Device (Gadget)
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
+static struct resource usba_udc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_UDPHS_FIFO,
+                .end    = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_BASE_UDPHS,
+                .end    = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [2] = {
+                .start  = AT91SAM9G45_ID_UDPHS,
+                .end    = AT91SAM9G45_ID_UDPHS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+#define EP(nam, idx, maxpkt, maxbk, dma, isoc)                  \
+        [idx] = {                                               \
+                .name           = nam,                          \
+                .index          = idx,                          \
+                .fifo_size      = maxpkt,                       \
+                .nr_banks       = maxbk,                        \
+                .can_dma        = dma,                          \
+                .can_isoc       = isoc,                         \
+        }
+static struct usba_ep_data usba_udc_ep[] __initdata = {
+        EP("ep0", 0, 64, 1, 0, 0),
+        EP("ep1", 1, 1024, 2, 1, 1),
+        EP("ep2", 2, 1024, 2, 1, 1),
+        EP("ep3", 3, 1024, 3, 1, 0),
+        EP("ep4", 4, 1024, 3, 1, 0),
+        EP("ep5", 5, 1024, 3, 1, 1),
+        EP("ep6", 6, 1024, 3, 1, 1),
+};
+#undef EP
+/*
+ * pdata doesn't have room for any endpoints, so we need to
+ * append room for the ones we need right after it.
+ */
+static struct {
+        struct usba_platform_data pdata;
+        struct usba_ep_data ep[7];
+} usba_udc_data;
+static struct platform_device at91_usba_udc_device = {
+        .name           = "atmel_usba_udc",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &usba_udc_data.pdata,
+        },
+        .resource       = usba_udc_resources,
+        .num_resources  = ARRAY_SIZE(usba_udc_resources),
+};
+void __init at91_add_device_usba(struct usba_platform_data *data)
+{
+        usba_udc_data.pdata.vbus_pin = -EINVAL;
+        usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
+        memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
+        if (data && data->vbus_pin > 0) {
+                at91_set_gpio_input(data->vbus_pin, 0);
+                at91_set_deglitch(data->vbus_pin, 1);
+                usba_udc_data.pdata.vbus_pin = data->vbus_pin;
+        }
+        /* Pullup pin is handled internally by USB device peripheral */
+        /* Clocks */
+        at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
+        at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
+        platform_device_register(&at91_usba_udc_device);
+}
+#else
+void __init at91_add_device_usba(struct usba_platform_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  Ethernet
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
+static u64 eth_dmamask = DMA_BIT_MASK(32);
+static struct at91_eth_data eth_data;
+static struct resource eth_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_EMAC,
+                .end    = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_EMAC,
+                .end    = AT91SAM9G45_ID_EMAC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_eth_device = {
+        .name           = "macb",
+        .id             = -1,
+        .dev            = {
+                                .dma_mask               = &eth_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &eth_data,
+        },
+        .resource       = eth_resources,
+        .num_resources  = ARRAY_SIZE(eth_resources),
+};
+void __init at91_add_device_eth(struct at91_eth_data *data)
+{
+        if (!data)
+                return;
+        if (data->phy_irq_pin) {
+                at91_set_gpio_input(data->phy_irq_pin, 0);
+                at91_set_deglitch(data->phy_irq_pin, 1);
+        }
+        /* Pins used for MII and RMII */
+        at91_set_A_periph(AT91_PIN_PA17, 0);    /* ETXCK_EREFCK */
+        at91_set_A_periph(AT91_PIN_PA15, 0);    /* ERXDV */
+        at91_set_A_periph(AT91_PIN_PA12, 0);    /* ERX0 */
+        at91_set_A_periph(AT91_PIN_PA13, 0);    /* ERX1 */
+        at91_set_A_periph(AT91_PIN_PA16, 0);    /* ERXER */
+        at91_set_A_periph(AT91_PIN_PA14, 0);    /* ETXEN */
+        at91_set_A_periph(AT91_PIN_PA10, 0);    /* ETX0 */
+        at91_set_A_periph(AT91_PIN_PA11, 0);    /* ETX1 */
+        at91_set_A_periph(AT91_PIN_PA19, 0);    /* EMDIO */
+        at91_set_A_periph(AT91_PIN_PA18, 0);    /* EMDC */
+        if (!data->is_rmii) {
+                at91_set_B_periph(AT91_PIN_PA29, 0);    /* ECRS */
+                at91_set_B_periph(AT91_PIN_PA30, 0);    /* ECOL */
+                at91_set_B_periph(AT91_PIN_PA8,  0);    /* ERX2 */
+                at91_set_B_periph(AT91_PIN_PA9,  0);    /* ERX3 */
+                at91_set_B_periph(AT91_PIN_PA28, 0);    /* ERXCK */
+                at91_set_B_periph(AT91_PIN_PA6,  0);    /* ETX2 */
+                at91_set_B_periph(AT91_PIN_PA7,  0);    /* ETX3 */
+                at91_set_B_periph(AT91_PIN_PA27, 0);    /* ETXER */
+        }
+        eth_data = *data;
+        platform_device_register(&at91sam9g45_eth_device);
+}
+#else
+void __init at91_add_device_eth(struct at91_eth_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  NAND / SmartMedia
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
+static struct atmel_nand_data nand_data;
+#define NAND_BASE       AT91_CHIPSELECT_3
+static struct resource nand_resources[] = {
+        [0] = {
+                .start  = NAND_BASE,
+                .end    = NAND_BASE + SZ_256M - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_BASE_SYS + AT91_ECC,
+                .end    = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device at91sam9g45_nand_device = {
+        .name           = "atmel_nand",
+        .id             = -1,
+        .dev            = {
+                                .platform_data  = &nand_data,
+        },
+        .resource       = nand_resources,
+        .num_resources  = ARRAY_SIZE(nand_resources),
+};
+void __init at91_add_device_nand(struct atmel_nand_data *data)
+{
+        unsigned long csa;
+        if (!data)
+                return;
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+        /* enable pin */
+        if (data->enable_pin)
+                at91_set_gpio_output(data->enable_pin, 1);
+        /* ready/busy pin */
+        if (data->rdy_pin)
+                at91_set_gpio_input(data->rdy_pin, 1);
+        /* card detect pin */
+        if (data->det_pin)
+                at91_set_gpio_input(data->det_pin, 1);
+        nand_data = *data;
+        platform_device_register(&at91sam9g45_nand_device);
+}
+#else
+void __init at91_add_device_nand(struct atmel_nand_data *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  TWI (i2c)
+ * -------------------------------------------------------------------- */
+/*
+ * Prefer the GPIO code since the TWI controller isn't robust
+ * (gets overruns and underruns under load) and can only issue
+ * repeated STARTs in one scenario (the driver doesn't yet handle them).
+ */
+#if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
+static struct i2c_gpio_platform_data pdata_i2c0 = {
+        .sda_pin                = AT91_PIN_PA20,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = AT91_PIN_PA21,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+};
+static struct platform_device at91sam9g45_twi0_device = {
+        .name                   = "i2c-gpio",
+        .id                     = 0,
+        .dev.platform_data      = &pdata_i2c0,
+};
+static struct i2c_gpio_platform_data pdata_i2c1 = {
+        .sda_pin                = AT91_PIN_PB10,
+        .sda_is_open_drain      = 1,
+        .scl_pin                = AT91_PIN_PB11,
+        .scl_is_open_drain      = 1,
+        .udelay                 = 2,            /* ~100 kHz */
+};
+static struct platform_device at91sam9g45_twi1_device = {
+        .name                   = "i2c-gpio",
+        .id                     = 1,
+        .dev.platform_data      = &pdata_i2c1,
+};
+void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+        i2c_register_board_info(i2c_id, devices, nr_devices);
+        if (i2c_id == 0) {
+                at91_set_GPIO_periph(AT91_PIN_PA20, 1);         /* TWD (SDA) */
+                at91_set_multi_drive(AT91_PIN_PA20, 1);
+                at91_set_GPIO_periph(AT91_PIN_PA21, 1);         /* TWCK (SCL) */
+                at91_set_multi_drive(AT91_PIN_PA21, 1);
+                platform_device_register(&at91sam9g45_twi0_device);
+        } else {
+                at91_set_GPIO_periph(AT91_PIN_PB10, 1);         /* TWD (SDA) */
+                at91_set_multi_drive(AT91_PIN_PB10, 1);
+                at91_set_GPIO_periph(AT91_PIN_PB11, 1);         /* TWCK (SCL) */
+                at91_set_multi_drive(AT91_PIN_PB11, 1);
+                platform_device_register(&at91sam9g45_twi1_device);
+        }
+}
+#elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
+static struct resource twi0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TWI0,
+                .end    = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TWI0,
+                .end    = AT91SAM9G45_ID_TWI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_twi0_device = {
+        .name           = "at91_i2c",
+        .id             = 0,
+        .resource       = twi0_resources,
+        .num_resources  = ARRAY_SIZE(twi0_resources),
+};
+static struct resource twi1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TWI1,
+                .end    = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TWI1,
+                .end    = AT91SAM9G45_ID_TWI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_twi1_device = {
+        .name           = "at91_i2c",
+        .id             = 1,
+        .resource       = twi1_resources,
+        .num_resources  = ARRAY_SIZE(twi1_resources),
+};
+void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
+{
+        i2c_register_board_info(i2c_id, devices, nr_devices);
+        /* pins used for TWI interface */
+        if (i2c_id == 0) {
+                at91_set_A_periph(AT91_PIN_PA20, 0);            /* TWD */
+                at91_set_multi_drive(AT91_PIN_PA20, 1);
+                at91_set_A_periph(AT91_PIN_PA21, 0);            /* TWCK */
+                at91_set_multi_drive(AT91_PIN_PA21, 1);
+                platform_device_register(&at91sam9g45_twi0_device);
+        } else {
+                at91_set_A_periph(AT91_PIN_PB10, 0);            /* TWD */
+                at91_set_multi_drive(AT91_PIN_PB10, 1);
+                at91_set_A_periph(AT91_PIN_PB11, 0);            /* TWCK */
+                at91_set_multi_drive(AT91_PIN_PB11, 1);
+                platform_device_register(&at91sam9g45_twi1_device);
+        }
+}
+#else
+void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
+#endif
+/* --------------------------------------------------------------------
+ *  SPI
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
+static u64 spi_dmamask = DMA_BIT_MASK(32);
+static struct resource spi0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SPI0,
+                .end    = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SPI0,
+                .end    = AT91SAM9G45_ID_SPI0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_spi0_device = {
+        .name           = "atmel_spi",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi0_resources,
+        .num_resources  = ARRAY_SIZE(spi0_resources),
+};
+static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
+static struct resource spi1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SPI1,
+                .end    = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SPI1,
+                .end    = AT91SAM9G45_ID_SPI1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_spi1_device = {
+        .name           = "atmel_spi",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &spi_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = spi1_resources,
+        .num_resources  = ARRAY_SIZE(spi1_resources),
+};
+static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
+{
+        int i;
+        unsigned long cs_pin;
+        short enable_spi0 = 0;
+        short enable_spi1 = 0;
+        /* Choose SPI chip-selects */
+        for (i = 0; i < nr_devices; i++) {
+                if (devices[i].controller_data)
+                        cs_pin = (unsigned long) devices[i].controller_data;
+                else if (devices[i].bus_num == 0)
+                        cs_pin = spi0_standard_cs[devices[i].chip_select];
+                else
+                        cs_pin = spi1_standard_cs[devices[i].chip_select];
+                if (devices[i].bus_num == 0)
+                        enable_spi0 = 1;
+                else
+                        enable_spi1 = 1;
+                /* enable chip-select pin */
+                at91_set_gpio_output(cs_pin, 1);
+                /* pass chip-select pin to driver */
+                devices[i].controller_data = (void *) cs_pin;
+        }
+        spi_register_board_info(devices, nr_devices);
+        /* Configure SPI bus(es) */
+        if (enable_spi0) {
+                at91_set_A_periph(AT91_PIN_PB0, 0);     /* SPI0_MISO */
+                at91_set_A_periph(AT91_PIN_PB1, 0);     /* SPI0_MOSI */
+                at91_set_A_periph(AT91_PIN_PB2, 0);     /* SPI0_SPCK */
+                at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
+                platform_device_register(&at91sam9g45_spi0_device);
+        }
+        if (enable_spi1) {
+                at91_set_A_periph(AT91_PIN_PB14, 0);    /* SPI1_MISO */
+                at91_set_A_periph(AT91_PIN_PB15, 0);    /* SPI1_MOSI */
+                at91_set_A_periph(AT91_PIN_PB16, 0);    /* SPI1_SPCK */
+                at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
+                platform_device_register(&at91sam9g45_spi1_device);
+        }
+}
+#else
+void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
+#endif
+/* --------------------------------------------------------------------
+ *  LCD Controller
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
+static u64 lcdc_dmamask = DMA_BIT_MASK(32);
+static struct atmel_lcdfb_info lcdc_data;
+static struct resource lcdc_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_LCDC_BASE,
+                .end    = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_LCDC,
+                .end    = AT91SAM9G45_ID_LCDC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91_lcdc_device = {
+        .name           = "atmel_lcdfb",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &lcdc_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &lcdc_data,
+        },
+        .resource       = lcdc_resources,
+        .num_resources  = ARRAY_SIZE(lcdc_resources),
+};
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
+{
+        if (!data)
+                return;
+        at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
+        at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
+        at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
+        at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
+        at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
+        at91_set_A_periph(AT91_PIN_PE6, 0);     /* LCDDEN */
+        at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
+        at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
+        at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
+        at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
+        at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
+        at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
+        at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
+        at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
+        at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
+        at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
+        at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
+        at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
+        at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
+        at91_set_A_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
+        at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
+        at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
+        at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
+        at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
+        at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
+        at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
+        at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
+        at91_set_A_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
+        at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
+        at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
+        lcdc_data = *data;
+        platform_device_register(&at91_lcdc_device);
+}
+#else
+void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
+#endif
+/* --------------------------------------------------------------------
+ *  Timer/Counter block
+ * -------------------------------------------------------------------- */
+#ifdef CONFIG_ATMEL_TCLIB
+static struct resource tcb0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TCB0,
+                .end    = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TCB,
+                .end    = AT91SAM9G45_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_tcb0_device = {
+        .name           = "atmel_tcb",
+        .id             = 0,
+        .resource       = tcb0_resources,
+        .num_resources  = ARRAY_SIZE(tcb0_resources),
+};
+/* TCB1 begins with TC3 */
+static struct resource tcb1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_TCB1,
+                .end    = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_TCB,
+                .end    = AT91SAM9G45_ID_TCB,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_tcb1_device = {
+        .name           = "atmel_tcb",
+        .id             = 1,
+        .resource       = tcb1_resources,
+        .num_resources  = ARRAY_SIZE(tcb1_resources),
+};
+static void __init at91_add_device_tc(void)
+{
+        /* this chip has one clock and irq for all six TC channels */
+        at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
+        platform_device_register(&at91sam9g45_tcb0_device);
+        at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
+        platform_device_register(&at91sam9g45_tcb1_device);
+}
+#else
+static void __init at91_add_device_tc(void) { }
+#endif
+/* --------------------------------------------------------------------
+ *  RTC
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
+static struct platform_device at91sam9g45_rtc_device = {
+        .name           = "at91_rtc",
+        .id             = -1,
+        .num_resources  = 0,
+};
+static void __init at91_add_device_rtc(void)
+{
+        platform_device_register(&at91sam9g45_rtc_device);
+}
+#else
+static void __init at91_add_device_rtc(void) {}
+#endif
+/* --------------------------------------------------------------------
+ *  RTT
+ * -------------------------------------------------------------------- */
+static struct resource rtt_resources[] = {
+        {
+                .start  = AT91_BASE_SYS + AT91_RTT,
+                .end    = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device at91sam9g45_rtt_device = {
+        .name           = "at91_rtt",
+        .id             = 0,
+        .resource       = rtt_resources,
+        .num_resources  = ARRAY_SIZE(rtt_resources),
+};
+static void __init at91_add_device_rtt(void)
+{
+        platform_device_register(&at91sam9g45_rtt_device);
+}
+/* --------------------------------------------------------------------
+ *  Watchdog
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
+static struct platform_device at91sam9g45_wdt_device = {
+        .name           = "at91_wdt",
+        .id             = -1,
+        .num_resources  = 0,
+};
+static void __init at91_add_device_watchdog(void)
+{
+        platform_device_register(&at91sam9g45_wdt_device);
+}
+#else
+static void __init at91_add_device_watchdog(void) {}
+#endif
+/* --------------------------------------------------------------------
+ *  PWM
+ * --------------------------------------------------------------------*/
+#if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
+static u32 pwm_mask;
+static struct resource pwm_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_PWMC,
+                .end    = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_PWMC,
+                .end    = AT91SAM9G45_ID_PWMC,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_pwm0_device = {
+        .name   = "atmel_pwm",
+        .id     = -1,
+        .dev    = {
+                .platform_data          = &pwm_mask,
+        },
+        .resource       = pwm_resources,
+        .num_resources  = ARRAY_SIZE(pwm_resources),
+};
+void __init at91_add_device_pwm(u32 mask)
+{
+        if (mask & (1 << AT91_PWM0))
+                at91_set_B_periph(AT91_PIN_PD24, 1);    /* enable PWM0 */
+        if (mask & (1 << AT91_PWM1))
+                at91_set_B_periph(AT91_PIN_PD31, 1);    /* enable PWM1 */
+        if (mask & (1 << AT91_PWM2))
+                at91_set_B_periph(AT91_PIN_PD26, 1);    /* enable PWM2 */
+        if (mask & (1 << AT91_PWM3))
+                at91_set_B_periph(AT91_PIN_PD0, 1);     /* enable PWM3 */
+        pwm_mask = mask;
+        platform_device_register(&at91sam9g45_pwm0_device);
+}
+#else
+void __init at91_add_device_pwm(u32 mask) {}
+#endif
+/* --------------------------------------------------------------------
+ *  SSC -- Synchronous Serial Controller
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
+static u64 ssc0_dmamask = DMA_BIT_MASK(32);
+static struct resource ssc0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SSC0,
+                .end    = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SSC0,
+                .end    = AT91SAM9G45_ID_SSC0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_ssc0_device = {
+        .name   = "ssc",
+        .id     = 0,
+        .dev    = {
+                .dma_mask               = &ssc0_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = ssc0_resources,
+        .num_resources  = ARRAY_SIZE(ssc0_resources),
+};
+static inline void configure_ssc0_pins(unsigned pins)
+{
+        if (pins & ATMEL_SSC_TF)
+                at91_set_A_periph(AT91_PIN_PD1, 1);
+        if (pins & ATMEL_SSC_TK)
+                at91_set_A_periph(AT91_PIN_PD0, 1);
+        if (pins & ATMEL_SSC_TD)
+                at91_set_A_periph(AT91_PIN_PD2, 1);
+        if (pins & ATMEL_SSC_RD)
+                at91_set_A_periph(AT91_PIN_PD3, 1);
+        if (pins & ATMEL_SSC_RK)
+                at91_set_A_periph(AT91_PIN_PD4, 1);
+        if (pins & ATMEL_SSC_RF)
+                at91_set_A_periph(AT91_PIN_PD5, 1);
+}
+static u64 ssc1_dmamask = DMA_BIT_MASK(32);
+static struct resource ssc1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_SSC1,
+                .end    = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_SSC1,
+                .end    = AT91SAM9G45_ID_SSC1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct platform_device at91sam9g45_ssc1_device = {
+        .name   = "ssc",
+        .id     = 1,
+        .dev    = {
+                .dma_mask               = &ssc1_dmamask,
+                .coherent_dma_mask      = DMA_BIT_MASK(32),
+        },
+        .resource       = ssc1_resources,
+        .num_resources  = ARRAY_SIZE(ssc1_resources),
+};
+static inline void configure_ssc1_pins(unsigned pins)
+{
+        if (pins & ATMEL_SSC_TF)
+                at91_set_A_periph(AT91_PIN_PD14, 1);
+        if (pins & ATMEL_SSC_TK)
+                at91_set_A_periph(AT91_PIN_PD12, 1);
+        if (pins & ATMEL_SSC_TD)
+                at91_set_A_periph(AT91_PIN_PD10, 1);
+        if (pins & ATMEL_SSC_RD)
+                at91_set_A_periph(AT91_PIN_PD11, 1);
+        if (pins & ATMEL_SSC_RK)
+                at91_set_A_periph(AT91_PIN_PD13, 1);
+        if (pins & ATMEL_SSC_RF)
+                at91_set_A_periph(AT91_PIN_PD15, 1);
+}
+/*
+ * SSC controllers are accessed through library code, instead of any
+ * kind of all-singing/all-dancing driver.  For example one could be
+ * used by a particular I2S audio codec's driver, while another one
+ * on the same system might be used by a custom data capture driver.
+ */
+void __init at91_add_device_ssc(unsigned id, unsigned pins)
+{
+        struct platform_device *pdev;
+        /*
+         * NOTE: caller is responsible for passing information matching
+         * "pins" to whatever will be using each particular controller.
+         */
+        switch (id) {
+        case AT91SAM9G45_ID_SSC0:
+                pdev = &at91sam9g45_ssc0_device;
+                configure_ssc0_pins(pins);
+                at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
+                break;
+        case AT91SAM9G45_ID_SSC1:
+                pdev = &at91sam9g45_ssc1_device;
+                configure_ssc1_pins(pins);
+                at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
+                break;
+        default:
+                return;
+        }
+        platform_device_register(pdev);
+}
+#else
+void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
+#endif
+/* --------------------------------------------------------------------
+ *  UART
+ * -------------------------------------------------------------------- */
+#if defined(CONFIG_SERIAL_ATMEL)
+static struct resource dbgu_resources[] = {
+        [0] = {
+                .start  = AT91_VA_BASE_SYS + AT91_DBGU,
+                .end    = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91_ID_SYS,
+                .end    = AT91_ID_SYS,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data dbgu_data = {
+        .use_dma_tx     = 0,
+        .use_dma_rx     = 0,
+        .regs           = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
+};
+static u64 dbgu_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at91sam9g45_dbgu_device = {
+        .name           = "atmel_usart",
+        .id             = 0,
+        .dev            = {
+                                .dma_mask               = &dbgu_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &dbgu_data,
+        },
+        .resource       = dbgu_resources,
+        .num_resources  = ARRAY_SIZE(dbgu_resources),
+};
+static inline void configure_dbgu_pins(void)
+{
+        at91_set_A_periph(AT91_PIN_PB12, 0);            /* DRXD */
+        at91_set_A_periph(AT91_PIN_PB13, 1);            /* DTXD */
+}
+static struct resource uart0_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US0,
+                .end    = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US0,
+                .end    = AT91SAM9G45_ID_US0,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data uart0_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+static u64 uart0_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at91sam9g45_uart0_device = {
+        .name           = "atmel_usart",
+        .id             = 1,
+        .dev            = {
+                                .dma_mask               = &uart0_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart0_data,
+        },
+        .resource       = uart0_resources,
+        .num_resources  = ARRAY_SIZE(uart0_resources),
+};
+static inline void configure_usart0_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB19, 1);            /* TXD0 */
+        at91_set_A_periph(AT91_PIN_PB18, 0);            /* RXD0 */
+        if (pins & ATMEL_UART_RTS)
+                at91_set_B_periph(AT91_PIN_PB17, 0);    /* RTS0 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_B_periph(AT91_PIN_PB15, 0);    /* CTS0 */
+}
+static struct resource uart1_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US1,
+                .end    = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US1,
+                .end    = AT91SAM9G45_ID_US1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data uart1_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+static u64 uart1_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at91sam9g45_uart1_device = {
+        .name           = "atmel_usart",
+        .id             = 2,
+        .dev            = {
+                                .dma_mask               = &uart1_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart1_data,
+        },
+        .resource       = uart1_resources,
+        .num_resources  = ARRAY_SIZE(uart1_resources),
+};
+static inline void configure_usart1_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB4, 1);             /* TXD1 */
+        at91_set_A_periph(AT91_PIN_PB5, 0);             /* RXD1 */
+        if (pins & ATMEL_UART_RTS)
+                at91_set_A_periph(AT91_PIN_PD16, 0);    /* RTS1 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_A_periph(AT91_PIN_PD17, 0);    /* CTS1 */
+}
+static struct resource uart2_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US2,
+                .end    = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US2,
+                .end    = AT91SAM9G45_ID_US2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data uart2_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+static u64 uart2_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at91sam9g45_uart2_device = {
+        .name           = "atmel_usart",
+        .id             = 3,
+        .dev            = {
+                                .dma_mask               = &uart2_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart2_data,
+        },
+        .resource       = uart2_resources,
+        .num_resources  = ARRAY_SIZE(uart2_resources),
+};
+static inline void configure_usart2_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB6, 1);             /* TXD2 */
+        at91_set_A_periph(AT91_PIN_PB7, 0);             /* RXD2 */
+        if (pins & ATMEL_UART_RTS)
+                at91_set_B_periph(AT91_PIN_PC9, 0);     /* RTS2 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_B_periph(AT91_PIN_PC11, 0);    /* CTS2 */
+}
+static struct resource uart3_resources[] = {
+        [0] = {
+                .start  = AT91SAM9G45_BASE_US3,
+                .end    = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = AT91SAM9G45_ID_US3,
+                .end    = AT91SAM9G45_ID_US3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct atmel_uart_data uart3_data = {
+        .use_dma_tx     = 1,
+        .use_dma_rx     = 1,
+};
+static u64 uart3_dmamask = DMA_BIT_MASK(32);
+static struct platform_device at91sam9g45_uart3_device = {
+        .name           = "atmel_usart",
+        .id             = 4,
+        .dev            = {
+                                .dma_mask               = &uart3_dmamask,
+                                .coherent_dma_mask      = DMA_BIT_MASK(32),
+                                .platform_data          = &uart3_data,
+        },
+        .resource       = uart3_resources,
+        .num_resources  = ARRAY_SIZE(uart3_resources),
+};
+static inline void configure_usart3_pins(unsigned pins)
+{
+        at91_set_A_periph(AT91_PIN_PB8, 1);             /* TXD3 */
+        at91_set_A_periph(AT91_PIN_PB9, 0);             /* RXD3 */
+        if (pins & ATMEL_UART_RTS)
+                at91_set_B_periph(AT91_PIN_PA23, 0);    /* RTS3 */
+        if (pins & ATMEL_UART_CTS)
+                at91_set_B_periph(AT91_PIN_PA24, 0);    /* CTS3 */
+}
+static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART];   /* the UARTs to use */
+struct platform_device *atmel_default_console_device;   /* the serial console device */
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
+{
+        struct platform_device *pdev;
+        switch (id) {
+                case 0:         /* DBGU */
+                        pdev = &at91sam9g45_dbgu_device;
+                        configure_dbgu_pins();
+                        at91_clock_associate("mck", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US0:
+                        pdev = &at91sam9g45_uart0_device;
+                        configure_usart0_pins(pins);
+                        at91_clock_associate("usart0_clk", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US1:
+                        pdev = &at91sam9g45_uart1_device;
+                        configure_usart1_pins(pins);
+                        at91_clock_associate("usart1_clk", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US2:
+                        pdev = &at91sam9g45_uart2_device;
+                        configure_usart2_pins(pins);
+                        at91_clock_associate("usart2_clk", &pdev->dev, "usart");
+                        break;
+                case AT91SAM9G45_ID_US3:
+                        pdev = &at91sam9g45_uart3_device;
+                        configure_usart3_pins(pins);
+                        at91_clock_associate("usart3_clk", &pdev->dev, "usart");
+                        break;
+                default:
+                        return;
+        }
+        pdev->id = portnr;              /* update to mapped ID */
+        if (portnr < ATMEL_MAX_UART)
+                at91_uarts[portnr] = pdev;
+}
+void __init at91_set_serial_console(unsigned portnr)
+{
+        if (portnr < ATMEL_MAX_UART)
+                atmel_default_console_device = at91_uarts[portnr];
+}
+void __init at91_add_device_serial(void)
+{
+        int i;
+        for (i = 0; i < ATMEL_MAX_UART; i++) {
+                if (at91_uarts[i])
+                        platform_device_register(at91_uarts[i]);
+        }
+        if (!atmel_default_console_device)
+                printk(KERN_INFO "AT91: No default serial console defined.\n");
+}
+#else
+void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
+void __init at91_set_serial_console(unsigned portnr) {}
+void __init at91_add_device_serial(void) {}
+#endif
+/* -------------------------------------------------------------------- */
+/*
+ * These devices are always present and don't need any board-specific
+ * setup.
+ */
+static int __init at91_add_standard_devices(void)
+{
+        at91_add_device_rtc();
+        at91_add_device_rtt();
+        at91_add_device_watchdog();
+        at91_add_device_tc();
+        return 0;
+}
+arch_initcall(at91_add_standard_devices);
diff --git a/arch/arm/mach-at91/board-afeb-9260v1.c b/arch/arm/mach-at91/board-afeb-9260v1.c
index 970fd6b6753e..61e52b66bc72 100644
--- a/arch/arm/mach-at91/board-afeb-9260v1.c
+++ b/arch/arm/mach-at91/board-afeb-9260v1.c
@@ -174,6 +174,16 @@ static struct i2c_board_info __initdata afeb9260_i2c_devices[] = {
        },
 };
+/*
+ * IDE (CF True IDE mode)
+ */
+static struct at91_cf_data afeb9260_cf_data = {
+        .chipselect = 4,
+        .irq_pin    = AT91_PIN_PA6,
+        .rst_pin    = AT91_PIN_PA7,
+        .flags      = AT91_CF_TRUE_IDE,
+};
 static void __init afeb9260_board_init(void)
 {
        /* Serial */
@@ -202,6 +212,8 @@ static void __init afeb9260_board_init(void)
                        ARRAY_SIZE(afeb9260_i2c_devices));
        /* Audio */
        at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX);
+        /* IDE */
+        at91_add_device_cf(&afeb9260_cf_data);
 }
 MACHINE_START(AFEB9260, "Custom afeb9260 board")
diff --git a/arch/arm/mach-at91/board-cpu9krea.c b/arch/arm/mach-at91/board-cpu9krea.c
new file mode 100644
index 000000000000..4bc2e9f6ebb5
--- /dev/null
+++ b/arch/arm/mach-at91/board-cpu9krea.c
@@ -0,0 +1,385 @@
+/*
+ * linux/arch/arm/mach-at91/board-cpu9krea.c
+ *
+ *  Copyright (C) 2005 SAN People
+ *  Copyright (C) 2006 Atmel
+ *  Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/mtd/physmap.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91sam9260_matrix.h>
+#include "sam9_smc.h"
+#include "generic.h"
+static void __init cpu9krea_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91sam9260_initialize(18432000);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS |
+                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
+                ATMEL_UART_DCD | ATMEL_UART_RI);
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+        /* USART2 on ttyS3. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9260_ID_US2, 3, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+        /* USART3 on ttyS4. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US3, 4, 0);
+        /* USART4 on ttyS5. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US4, 5, 0);
+        /* USART5 on ttyS6. (Rx, Tx) */
+        at91_register_uart(AT91SAM9260_ID_US5, 6, 0);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init cpu9krea_init_irq(void)
+{
+        at91sam9260_init_interrupts(NULL);
+}
+/*
+ * USB Host port
+ */
+static struct at91_usbh_data __initdata cpu9krea_usbh_data = {
+        .ports          = 2,
+};
+/*
+ * USB Device port
+ */
+static struct at91_udc_data __initdata cpu9krea_udc_data = {
+        .vbus_pin       = AT91_PIN_PC8,
+        .pullup_pin     = 0,            /* pull-up driven by UDC */
+};
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata cpu9krea_macb_data = {
+        .is_rmii        = 1,
+};
+/*
+ * NAND flash
+ */
+static struct atmel_nand_data __initdata cpu9krea_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC13,
+        .enable_pin     = AT91_PIN_PC14,
+        .bus_width_16   = 0,
+};
+#ifdef CONFIG_MACH_CPU9260
+static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 1,
+        .ncs_read_pulse         = 3,
+        .nrd_pulse              = 3,
+        .ncs_write_pulse        = 3,
+        .nwe_pulse              = 3,
+        .read_cycle             = 5,
+        .write_cycle            = 5,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
+        .tdf_cycles             = 2,
+};
+#else
+static struct sam9_smc_config __initdata cpu9krea_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 2,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 2,
+        .ncs_read_pulse         = 4,
+        .nrd_pulse              = 4,
+        .ncs_write_pulse        = 4,
+        .nwe_pulse              = 4,
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_DBW_8,
+        .tdf_cycles             = 3,
+};
+#endif
+static void __init cpu9krea_add_device_nand(void)
+{
+        sam9_smc_configure(3, &cpu9krea_nand_smc_config);
+        at91_add_device_nand(&cpu9krea_nand_data);
+}
+/*
+ * NOR flash
+ */
+static struct physmap_flash_data cpuat9260_nor_data = {
+        .width          = 2,
+};
+#define NOR_BASE        AT91_CHIPSELECT_0
+#define NOR_SIZE        SZ_64M
+static struct resource nor_flash_resources[] = {
+        {
+                .start  = NOR_BASE,
+                .end    = NOR_BASE + NOR_SIZE - 1,
+                .flags  = IORESOURCE_MEM,
+        }
+};
+static struct platform_device cpu9krea_nor_flash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev            = {
+                .platform_data  = &cpuat9260_nor_data,
+        },
+        .resource       = nor_flash_resources,
+        .num_resources  = ARRAY_SIZE(nor_flash_resources),
+};
+#ifdef CONFIG_MACH_CPU9260
+static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 1,
+        .ncs_read_pulse         = 10,
+        .nrd_pulse              = 10,
+        .ncs_write_pulse        = 6,
+        .nwe_pulse              = 6,
+        .read_cycle             = 12,
+        .write_cycle            = 8,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
+                        | AT91_SMC_DBW_16,
+        .tdf_cycles             = 2,
+};
+#else
+static struct sam9_smc_config __initdata cpu9krea_nor_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 1,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 1,
+        .ncs_read_pulse         = 13,
+        .nrd_pulse              = 13,
+        .ncs_write_pulse        = 8,
+        .nwe_pulse              = 8,
+        .read_cycle             = 15,
+        .write_cycle            = 10,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE
+                        | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
+                        | AT91_SMC_DBW_16,
+        .tdf_cycles             = 2,
+};
+#endif
+static __init void cpu9krea_add_device_nor(void)
+{
+        unsigned long csa;
+        csa = at91_sys_read(AT91_MATRIX_EBICSA);
+        at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_VDDIOMSEL_3_3V);
+        /* configure chip-select 0 (NOR) */
+        sam9_smc_configure(0, &cpu9krea_nor_smc_config);
+        platform_device_register(&cpu9krea_nor_flash);
+}
+/*
+ * LEDs
+ */
+static struct gpio_led cpu9krea_leds[] = {
+        {       /* LED1 */
+                .name                   = "LED1",
+                .gpio                   = AT91_PIN_PC11,
+                .active_low             = 1,
+                .default_trigger        = "timer",
+        },
+        {       /* LED2 */
+                .name                   = "LED2",
+                .gpio                   = AT91_PIN_PC12,
+                .active_low             = 1,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* LED3 */
+                .name                   = "LED3",
+                .gpio                   = AT91_PIN_PC7,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* LED4 */
+                .name                   = "LED4",
+                .gpio                   = AT91_PIN_PC9,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        }
+};
+static struct i2c_board_info __initdata cpu9krea_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rtc-ds1307", 0x68),
+                .type   = "ds1339",
+        },
+};
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button cpu9krea_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PC3,
+                .code           = BTN_0,
+                .desc           = "BP1",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB20,
+                .code           = BTN_1,
+                .desc           = "BP2",
+                .active_low     = 1,
+                .wakeup         = 1,
+        }
+};
+static struct gpio_keys_platform_data cpu9krea_button_data = {
+        .buttons        = cpu9krea_buttons,
+        .nbuttons       = ARRAY_SIZE(cpu9krea_buttons),
+};
+static struct platform_device cpu9krea_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &cpu9krea_button_data,
+        }
+};
+static void __init cpu9krea_add_device_buttons(void)
+{
+        at91_set_gpio_input(AT91_PIN_PC3, 1);   /* BP1 */
+        at91_set_deglitch(AT91_PIN_PC3, 1);
+        at91_set_gpio_input(AT91_PIN_PB20, 1);  /* BP2 */
+        at91_set_deglitch(AT91_PIN_PB20, 1);
+        platform_device_register(&cpu9krea_button_device);
+}
+#else
+static void __init cpu9krea_add_device_buttons(void)
+{
+}
+#endif
+/*
+ * MCI (SD/MMC)
+ */
+static struct at91_mmc_data __initdata cpu9krea_mmc_data = {
+        .slot_b         = 0,
+        .wire4          = 1,
+        .det_pin        = AT91_PIN_PA29,
+};
+static void __init cpu9krea_board_init(void)
+{
+        /* NOR */
+        cpu9krea_add_device_nor();
+        /* Serial */
+        at91_add_device_serial();
+        /* USB Host */
+        at91_add_device_usbh(&cpu9krea_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&cpu9krea_udc_data);
+        /* NAND */
+        cpu9krea_add_device_nand();
+        /* Ethernet */
+        at91_add_device_eth(&cpu9krea_macb_data);
+        /* MMC */
+        at91_add_device_mmc(0, &cpu9krea_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(cpu9krea_i2c_devices,
+                ARRAY_SIZE(cpu9krea_i2c_devices));
+        /* LEDs */
+        at91_gpio_leds(cpu9krea_leds, ARRAY_SIZE(cpu9krea_leds));
+        /* Push Buttons */
+        cpu9krea_add_device_buttons();
+}
+#ifdef CONFIG_MACH_CPU9260
+MACHINE_START(CPUAT9260, "Eukrea CPU9260")
+#else
+MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")
+#endif
+        /* Maintainer: Eric Benard - EUKREA Electromatique */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = cpu9krea_map_io,
+        .init_irq       = cpu9krea_init_irq,
+        .init_machine   = cpu9krea_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-cpuat91.c b/arch/arm/mach-at91/board-cpuat91.c
new file mode 100644
index 000000000000..a28d99656190
--- /dev/null
+++ b/arch/arm/mach-at91/board-cpuat91.c
@@ -0,0 +1,185 @@
+/*
+ * linux/arch/arm/mach-at91/board-cpuat91.c
+ *
+ *  Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
+#include <mach/hardware.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91rm9200_mc.h>
+#include "generic.h"
+static struct gpio_led cpuat91_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = AT91_PIN_PC0,
+        },
+};
+static void __init cpuat91_map_io(void)
+{
+        /* Initialize processor: 18.432 MHz crystal */
+        at91rm9200_initialize(18432000, AT91RM9200_PQFP);
+        /* DBGU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 on ttyS1. (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US0, 1, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+        /* USART1 on ttyS2. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */
+        at91_register_uart(AT91RM9200_ID_US1, 2, ATMEL_UART_CTS |
+                ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR |
+                ATMEL_UART_DCD | ATMEL_UART_RI);
+        /* USART2 on ttyS3 (Rx, Tx) */
+        at91_register_uart(AT91RM9200_ID_US2, 3, 0);
+        /* USART3 on ttyS4 (Rx, Tx, CTS, RTS) */
+        at91_register_uart(AT91RM9200_ID_US3, 4, ATMEL_UART_CTS |
+                ATMEL_UART_RTS);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init cpuat91_init_irq(void)
+{
+        at91rm9200_init_interrupts(NULL);
+}
+static struct at91_eth_data __initdata cpuat91_eth_data = {
+        .is_rmii        = 1,
+};
+static struct at91_usbh_data __initdata cpuat91_usbh_data = {
+        .ports          = 1,
+};
+static struct at91_udc_data __initdata cpuat91_udc_data = {
+        .vbus_pin       = AT91_PIN_PC15,
+        .pullup_pin     = AT91_PIN_PC14,
+};
+static struct at91_mmc_data __initdata cpuat91_mmc_data = {
+        .det_pin        = AT91_PIN_PC2,
+        .wire4          = 1,
+};
+static struct physmap_flash_data cpuat91_flash_data = {
+        .width          = 2,
+};
+static struct resource cpuat91_flash_resource = {
+        .start          = AT91_CHIPSELECT_0,
+        .end            = AT91_CHIPSELECT_0 + SZ_16M - 1,
+        .flags          = IORESOURCE_MEM,
+};
+static struct platform_device cpuat91_norflash = {
+        .name           = "physmap-flash",
+        .id             = 0,
+        .dev    = {
+                .platform_data  = &cpuat91_flash_data,
+        },
+        .resource       = &cpuat91_flash_resource,
+        .num_resources  = 1,
+};
+#ifdef CONFIG_MTD_PLATRAM
+struct platdata_mtd_ram at91_sram_pdata = {
+        .mapname        = "SRAM",
+        .bankwidth      = 2,
+};
+static struct resource at91_sram_resource[] = {
+        [0] = {
+                .start = AT91RM9200_SRAM_BASE,
+                .end   = AT91RM9200_SRAM_BASE + AT91RM9200_SRAM_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+};
+static struct platform_device at91_sram = {
+        .name           = "mtd-ram",
+        .id             = 0,
+        .resource       = at91_sram_resource,
+        .num_resources  = ARRAY_SIZE(at91_sram_resource),
+        .dev    = {
+                .platform_data = &at91_sram_pdata,
+        },
+};
+#endif /* MTD_PLATRAM */
+static struct platform_device *platform_devices[] __initdata = {
+        &cpuat91_norflash,
+#ifdef CONFIG_MTD_PLATRAM
+        &at91_sram,
+#endif /* CONFIG_MTD_PLATRAM */
+};
+static void __init cpuat91_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* LEDs. */
+        at91_gpio_leds(cpuat91_leds, ARRAY_SIZE(cpuat91_leds));
+        /* Ethernet */
+        at91_add_device_eth(&cpuat91_eth_data);
+        /* USB Host */
+        at91_add_device_usbh(&cpuat91_usbh_data);
+        /* USB Device */
+        at91_add_device_udc(&cpuat91_udc_data);
+        /* MMC */
+        at91_add_device_mmc(0, &cpuat91_mmc_data);
+        /* I2C */
+        at91_add_device_i2c(NULL, 0);
+        /* Platform devices */
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+MACHINE_START(CPUAT91, "Eukrea")
+        /* Maintainer: Eric Benard - EUKREA Electromatique */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91rm9200_timer,
+        .map_io         = cpuat91_map_io,
+        .init_irq       = cpuat91_init_irq,
+        .init_machine   = cpuat91_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9261ek.c b/arch/arm/mach-at91/board-sam9261ek.c
index d5266da55311..f9b19993a7a9 100644
--- a/arch/arm/mach-at91/board-sam9261ek.c
+++ b/arch/arm/mach-at91/board-sam9261ek.c
@@ -287,7 +287,11 @@ static void __init ek_add_device_ts(void) {}
 */
 static struct at73c213_board_info at73c213_data = {
        .ssc_id         = 1,
+#if defined(CONFIG_MACH_AT91SAM9261EK)
        .shortname      = "AT91SAM9261-EK external DAC",
+#else
+        .shortname      = "AT91SAM9G10-EK external DAC",
+#endif
 };
 #if defined(CONFIG_SND_AT73C213) || defined(CONFIG_SND_AT73C213_MODULE)
@@ -414,6 +418,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
        .default_monspecs               = &at91fb_default_stn_monspecs,
        .atmel_lcdfb_power_control      = at91_lcdc_stn_power_control,
        .guard_time                     = 1,
+#if defined(CONFIG_MACH_AT91SAM9G10EK)
+        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
+#endif
 };
 #else
@@ -467,6 +474,9 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
        .default_monspecs               = &at91fb_default_tft_monspecs,
        .atmel_lcdfb_power_control      = at91_lcdc_tft_power_control,
        .guard_time                     = 1,
+#if defined(CONFIG_MACH_AT91SAM9G10EK)
+        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
+#endif
 };
 #endif
@@ -600,7 +610,11 @@ static void __init ek_board_init(void)
        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
 }
+#if defined(CONFIG_MACH_AT91SAM9261EK)
 MACHINE_START(AT91SAM9261EK, "Atmel AT91SAM9261-EK")
+#else
+MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")
+#endif
        /* Maintainer: Atmel */
        .phys_io        = AT91_BASE_SYS,
        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
diff --git a/arch/arm/mach-at91/board-sam9263ek.c b/arch/arm/mach-at91/board-sam9263ek.c
index 57d52528f224..1bf7bd4cbe13 100644
--- a/arch/arm/mach-at91/board-sam9263ek.c
+++ b/arch/arm/mach-at91/board-sam9263ek.c
@@ -364,9 +364,9 @@ static void __init ek_add_device_buttons(void) {}
 /*
 * AC97
+ * reset_pin is not connected: NRST
 */
-static struct atmel_ac97_data ek_ac97_data = {
+static struct ac97c_platform_data ek_ac97_data = {
-        .reset_pin      = AT91_PIN_PA13,
 };
diff --git a/arch/arm/mach-at91/board-sam9g20ek.c b/arch/arm/mach-at91/board-sam9g20ek.c
index a55398ed1211..ca470d504ea0 100644
--- a/arch/arm/mach-at91/board-sam9g20ek.c
+++ b/arch/arm/mach-at91/board-sam9g20ek.c
@@ -273,6 +273,7 @@ static void __init ek_add_device_buttons(void) {}
 static struct i2c_board_info __initdata ek_i2c_devices[] = {
        {
                I2C_BOARD_INFO("24c512", 0x50),
+                I2C_BOARD_INFO("wm8731", 0x1b),
        },
 };
diff --git a/arch/arm/mach-at91/board-sam9m10g45ek.c b/arch/arm/mach-at91/board-sam9m10g45ek.c
new file mode 100644
index 000000000000..b8558eae5229
--- /dev/null
+++ b/arch/arm/mach-at91/board-sam9m10g45ek.c
@@ -0,0 +1,389 @@
+/*
+ *  Board-specific setup code for the AT91SAM9M10G45 Evaluation Kit family
+ *
+ *  Covers: * AT91SAM9G45-EKES  board
+ *          * AT91SAM9M10G45-EK board
+ *
+ *  Copyright (C) 2009 Atmel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/fb.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/leds.h>
+#include <linux/clk.h>
+#include <mach/hardware.h>
+#include <video/atmel_lcdc.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/irq.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/board.h>
+#include <mach/gpio.h>
+#include <mach/at91sam9_smc.h>
+#include <mach/at91_shdwc.h>
+#include "sam9_smc.h"
+#include "generic.h"
+static void __init ek_map_io(void)
+{
+        /* Initialize processor: 12.000 MHz crystal */
+        at91sam9g45_initialize(12000000);
+        /* DGBU on ttyS0. (Rx & Tx only) */
+        at91_register_uart(0, 0, 0);
+        /* USART0 not connected on the -EK board */
+        /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */
+        at91_register_uart(AT91SAM9G45_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS);
+        /* set serial console to ttyS0 (ie, DBGU) */
+        at91_set_serial_console(0);
+}
+static void __init ek_init_irq(void)
+{
+        at91sam9g45_init_interrupts(NULL);
+}
+/*
+ * USB HS Host port (common to OHCI & EHCI)
+ */
+static struct at91_usbh_data __initdata ek_usbh_hs_data = {
+        .ports          = 2,
+        .vbus_pin       = {AT91_PIN_PD1, AT91_PIN_PD3},
+};
+/*
+ * USB HS Device port
+ */
+static struct usba_platform_data __initdata ek_usba_udc_data = {
+        .vbus_pin       = AT91_PIN_PB19,
+};
+/*
+ * SPI devices.
+ */
+static struct spi_board_info ek_spi_devices[] = {
+        {       /* DataFlash chip */
+                .modalias       = "mtd_dataflash",
+                .chip_select    = 0,
+                .max_speed_hz   = 15 * 1000 * 1000,
+                .bus_num        = 0,
+        },
+};
+/*
+ * MACB Ethernet device
+ */
+static struct at91_eth_data __initdata ek_macb_data = {
+        .phy_irq_pin    = AT91_PIN_PD5,
+        .is_rmii        = 1,
+};
+/*
+ * NAND flash
+ */
+static struct mtd_partition __initdata ek_nand_partition[] = {
+        {
+                .name   = "Partition 1",
+                .offset = 0,
+                .size   = SZ_64M,
+        },
+        {
+                .name   = "Partition 2",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size   = MTDPART_SIZ_FULL,
+        },
+};
+static struct mtd_partition * __init nand_partitions(int size, int *num_partitions)
+{
+        *num_partitions = ARRAY_SIZE(ek_nand_partition);
+        return ek_nand_partition;
+}
+/* det_pin is not connected */
+static struct atmel_nand_data __initdata ek_nand_data = {
+        .ale            = 21,
+        .cle            = 22,
+        .rdy_pin        = AT91_PIN_PC8,
+        .enable_pin     = AT91_PIN_PC14,
+        .partition_info = nand_partitions,
+#if defined(CONFIG_MTD_NAND_AT91_BUSWIDTH_16)
+        .bus_width_16   = 1,
+#else
+        .bus_width_16   = 0,
+#endif
+};
+static struct sam9_smc_config __initdata ek_nand_smc_config = {
+        .ncs_read_setup         = 0,
+        .nrd_setup              = 2,
+        .ncs_write_setup        = 0,
+        .nwe_setup              = 2,
+        .ncs_read_pulse         = 4,
+        .nrd_pulse              = 4,
+        .ncs_write_pulse        = 4,
+        .nwe_pulse              = 4,
+        .read_cycle             = 7,
+        .write_cycle            = 7,
+        .mode                   = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+        .tdf_cycles             = 3,
+};
+static void __init ek_add_device_nand(void)
+{
+        /* setup bus-width (8 or 16) */
+        if (ek_nand_data.bus_width_16)
+                ek_nand_smc_config.mode |= AT91_SMC_DBW_16;
+        else
+                ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
+        /* configure chip-select 3 (NAND) */
+        sam9_smc_configure(3, &ek_nand_smc_config);
+        at91_add_device_nand(&ek_nand_data);
+}
+/*
+ * LCD Controller
+ */
+#if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
+static struct fb_videomode at91_tft_vga_modes[] = {
+        {
+                .name           = "LG",
+                .refresh        = 60,
+                .xres           = 480,          .yres           = 272,
+                .pixclock       = KHZ2PICOS(9000),
+                .left_margin    = 1,            .right_margin   = 1,
+                .upper_margin   = 40,           .lower_margin   = 1,
+                .hsync_len      = 45,           .vsync_len      = 1,
+                .sync           = 0,
+                .vmode          = FB_VMODE_NONINTERLACED,
+        },
+};
+static struct fb_monspecs at91fb_default_monspecs = {
+        .manufacturer   = "LG",
+        .monitor        = "LB043WQ1",
+        .modedb         = at91_tft_vga_modes,
+        .modedb_len     = ARRAY_SIZE(at91_tft_vga_modes),
+        .hfmin          = 15000,
+        .hfmax          = 17640,
+        .vfmin          = 57,
+        .vfmax          = 67,
+};
+#define AT91SAM9G45_DEFAULT_LCDCON2     (ATMEL_LCDC_MEMOR_LITTLE \
+                                        | ATMEL_LCDC_DISTYPE_TFT \
+                                        | ATMEL_LCDC_CLKMOD_ALWAYSACTIVE)
+/* Driver datas */
+static struct atmel_lcdfb_info __initdata ek_lcdc_data = {
+        .lcdcon_is_backlight            = true,
+        .default_bpp                    = 32,
+        .default_dmacon                 = ATMEL_LCDC_DMAEN,
+        .default_lcdcon2                = AT91SAM9G45_DEFAULT_LCDCON2,
+        .default_monspecs               = &at91fb_default_monspecs,
+        .guard_time                     = 9,
+        .lcd_wiring_mode                = ATMEL_LCDC_WIRING_RGB,
+};
+#else
+static struct atmel_lcdfb_info __initdata ek_lcdc_data;
+#endif
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {       /* BP1, "leftclic" */
+                .code           = BTN_LEFT,
+                .gpio           = AT91_PIN_PB6,
+                .active_low     = 1,
+                .desc           = "left_click",
+                .wakeup         = 1,
+        },
+        {       /* BP2, "rightclic" */
+                .code           = BTN_RIGHT,
+                .gpio           = AT91_PIN_PB7,
+                .active_low     = 1,
+                .desc           = "right_click",
+                .wakeup         = 1,
+        },
+                /* BP3, "joystick" */
+        {
+                .code           = KEY_LEFT,
+                .gpio           = AT91_PIN_PB14,
+                .active_low     = 1,
+                .desc           = "Joystick Left",
+        },
+        {
+                .code           = KEY_RIGHT,
+                .gpio           = AT91_PIN_PB15,
+                .active_low     = 1,
+                .desc           = "Joystick Right",
+        },
+        {
+                .code           = KEY_UP,
+                .gpio           = AT91_PIN_PB16,
+                .active_low     = 1,
+                .desc           = "Joystick Up",
+        },
+        {
+                .code           = KEY_DOWN,
+                .gpio           = AT91_PIN_PB17,
+                .active_low     = 1,
+                .desc           = "Joystick Down",
+        },
+        {
+                .code           = KEY_ENTER,
+                .gpio           = AT91_PIN_PB18,
+                .active_low     = 1,
+                .desc           = "Joystick Press",
+        },
+};
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+static void __init ek_add_device_buttons(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(ek_buttons); i++) {
+                at91_set_GPIO_periph(ek_buttons[i].gpio, 1);
+                at91_set_deglitch(ek_buttons[i].gpio, 1);
+        }
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
+/*
+ * LEDs ... these could all be PWM-driven, for variable brightness
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "top" led, red, powerled */
+                .name                   = "d8",
+                .gpio                   = AT91_PIN_PD30,
+                .default_trigger        = "heartbeat",
+        },
+        {       /* "left" led, green, userled2, pwm3 */
+                .name                   = "d6",
+                .gpio                   = AT91_PIN_PD0,
+                .active_low             = 1,
+                .default_trigger        = "nand-disk",
+        },
+#if !(defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE))
+        {       /* "right" led, green, userled1, pwm1 */
+                .name                   = "d7",
+                .gpio                   = AT91_PIN_PD31,
+                .active_low             = 1,
+                .default_trigger        = "mmc0",
+        },
+#endif
+};
+/*
+ * PWM Leds
+ */
+static struct gpio_led ek_pwm_led[] = {
+#if defined(CONFIG_LEDS_ATMEL_PWM) || defined(CONFIG_LEDS_ATMEL_PWM_MODULE)
+        {       /* "right" led, green, userled1, pwm1 */
+                .name                   = "d7",
+                .gpio                   = 1,    /* is PWM channel number */
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+#endif
+};
+static void __init ek_board_init(void)
+{
+        /* Serial */
+        at91_add_device_serial();
+        /* USB HS Host */
+        at91_add_device_usbh_ohci(&ek_usbh_hs_data);
+        /* USB HS Device */
+        at91_add_device_usba(&ek_usba_udc_data);
+        /* SPI */
+        at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices));
+        /* Ethernet */
+        at91_add_device_eth(&ek_macb_data);
+        /* NAND */
+        ek_add_device_nand();
+        /* I2C */
+        at91_add_device_i2c(0, NULL, 0);
+        /* LCD Controller */
+        at91_add_device_lcdc(&ek_lcdc_data);
+        /* Push Buttons */
+        ek_add_device_buttons();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        at91_pwm_leds(ek_pwm_led, ARRAY_SIZE(ek_pwm_led));
+}
+MACHINE_START(AT91SAM9G45EKES, "Atmel AT91SAM9G45-EKES")
+        /* Maintainer: Atmel */
+        .phys_io        = AT91_BASE_SYS,
+        .io_pg_offst    = (AT91_VA_BASE_SYS >> 18) & 0xfffc,
+        .boot_params    = AT91_SDRAM_BASE + 0x100,
+        .timer          = &at91sam926x_timer,
+        .map_io         = ek_map_io,
+        .init_irq       = ek_init_irq,
+        .init_machine   = ek_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-at91/board-sam9rlek.c b/arch/arm/mach-at91/board-sam9rlek.c
index f6b5672cabd6..9d07679efce7 100644
--- a/arch/arm/mach-at91/board-sam9rlek.c
+++ b/arch/arm/mach-at91/board-sam9rlek.c
@@ -15,6 +15,8 @@
 #include <linux/spi/spi.h>
 #include <linux/fb.h>
 #include <linux/clk.h>
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
 #include <video/atmel_lcdc.h>
@@ -208,6 +210,79 @@ static struct atmel_lcdfb_info __initdata ek_lcdc_data;
 #endif
+/*
+ * LEDs
+ */
+static struct gpio_led ek_leds[] = {
+        {       /* "bottom" led, green, userled1 to be defined */
+                .name                   = "ds1",
+                .gpio                   = AT91_PIN_PD15,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "bottom" led, green, userled2 to be defined */
+                .name                   = "ds2",
+                .gpio                   = AT91_PIN_PD16,
+                .active_low             = 1,
+                .default_trigger        = "none",
+        },
+        {       /* "power" led, yellow */
+                .name                   = "ds3",
+                .gpio                   = AT91_PIN_PD14,
+                .default_trigger        = "heartbeat",
+        }
+};
+/*
+ * GPIO Buttons
+ */
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+static struct gpio_keys_button ek_buttons[] = {
+        {
+                .gpio           = AT91_PIN_PB0,
+                .code           = BTN_2,
+                .desc           = "Right Click",
+                .active_low     = 1,
+                .wakeup         = 1,
+        },
+        {
+                .gpio           = AT91_PIN_PB1,
+                .code           = BTN_1,
+                .desc           = "Left Click",
+                .active_low     = 1,
+                .wakeup         = 1,
+        }
+};
+static struct gpio_keys_platform_data ek_button_data = {
+        .buttons        = ek_buttons,
+        .nbuttons       = ARRAY_SIZE(ek_buttons),
+};
+static struct platform_device ek_button_device = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .num_resources  = 0,
+        .dev            = {
+                .platform_data  = &ek_button_data,
+        }
+};
+static void __init ek_add_device_buttons(void)
+{
+        at91_set_gpio_input(AT91_PIN_PB1, 1);   /* btn1 */
+        at91_set_deglitch(AT91_PIN_PB1, 1);
+        at91_set_gpio_input(AT91_PIN_PB0, 1);   /* btn2 */
+        at91_set_deglitch(AT91_PIN_PB0, 1);
+        platform_device_register(&ek_button_device);
+}
+#else
+static void __init ek_add_device_buttons(void) {}
+#endif
 static void __init ek_board_init(void)
 {
        /* Serial */
@@ -226,6 +301,10 @@ static void __init ek_board_init(void)
        at91_add_device_lcdc(&ek_lcdc_data);
        /* Touch Screen Controller */
        at91_add_device_tsadcc();
+        /* LEDs */
+        at91_gpio_leds(ek_leds, ARRAY_SIZE(ek_leds));
+        /* Push Buttons */
+        ek_add_device_buttons();
 }
 MACHINE_START(AT91SAM9RLEK, "Atmel AT91SAM9RL-EK")
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index bac578fe0d3d..c042dcf4725f 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -47,20 +47,25 @@
 * Chips have some kind of clocks : group them by functionality
 */
 #define cpu_has_utmi()          (  cpu_is_at91cap9() \
-                                || cpu_is_at91sam9rl())
+                                || cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45())
-#define cpu_has_800M_plla()     (cpu_is_at91sam9g20())
+#define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
+                                || cpu_is_at91sam9g45())
-#define cpu_has_pllb()          (!cpu_is_at91sam9rl())
+#define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
-#define cpu_has_upll()          (0)
+#define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45()))
+#define cpu_has_upll()          (cpu_is_at91sam9g45())
 /* USB host HS & FS */
 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
 /* USB device FS only */
-#define cpu_has_udpfs()         (!cpu_is_at91sam9rl())
+#define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
+                                || cpu_is_at91sam9g45()))
 static LIST_HEAD(clocks);
 static DEFINE_SPINLOCK(clk_lock);
@@ -133,6 +138,13 @@ static void pmc_uckr_mode(struct clk *clk, int is_on)
 {
        unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
+        if (cpu_is_at91sam9g45()) {
+                if (is_on)
+                        uckr |= AT91_PMC_BIASEN;
+                else
+                        uckr &= ~AT91_PMC_BIASEN;
+        }
        if (is_on) {
                is_on = AT91_PMC_LOCKU;
                at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
@@ -310,6 +322,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
        unsigned long   flags;
        unsigned        prescale;
        unsigned long   actual;
+        unsigned long   prev = ULONG_MAX;
        if (!clk_is_programmable(clk))
                return -EINVAL;
@@ -317,8 +330,16 @@ long clk_round_rate(struct clk *clk, unsigned long rate)
        actual = clk->parent->rate_hz;
        for (prescale = 0; prescale < 7; prescale++) {
-                if (actual && actual <= rate)
+                if (actual > rate)
+                        prev = actual;
+                if (actual && actual <= rate) {
+                        if ((prev - rate) < (rate - actual)) {
+                                actual = prev;
+                                prescale--;
+                        }
                        break;
+                }
                actual >>= 1;
        }
@@ -373,6 +394,10 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
                return -EBUSY;
        if (!clk_is_primary(parent) || !clk_is_programmable(clk))
                return -EINVAL;
+        if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
+                return -EINVAL;
        spin_lock_irqsave(&clk_lock, flags);
        clk->rate_hz = parent->rate_hz;
@@ -601,7 +626,9 @@ static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
                uhpck.pmc_mask = AT91RM9200_PMC_UHP;
                udpck.pmc_mask = AT91RM9200_PMC_UDP;
                at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
+                   cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
+                   cpu_is_at91sam9g10()) {
                uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
                udpck.pmc_mask = AT91SAM926x_PMC_UDP;
        } else if (cpu_is_at91cap9()) {
@@ -637,6 +664,7 @@ int __init at91_clock_init(unsigned long main_clock)
 {
        unsigned tmp, freq, mckr;
        int i;
+        int pll_overclock = false;
        /*
         * When the bootloader initialized the main oscillator correctly,
@@ -654,12 +682,25 @@ int __init at91_clock_init(unsigned long main_clock)
        /* report if PLLA is more than mildly overclocked */
        plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
-        if ((!cpu_has_800M_plla() && plla.rate_hz > 209000000)
+        if (cpu_has_300M_plla()) {
-           || (cpu_has_800M_plla() && plla.rate_hz > 800000000))
+                if (plla.rate_hz > 300000000)
+                        pll_overclock = true;
+        } else if (cpu_has_800M_plla()) {
+                if (plla.rate_hz > 800000000)
+                        pll_overclock = true;
+        } else {
+                if (plla.rate_hz > 209000000)
+                        pll_overclock = true;
+        }
+        if (pll_overclock)
                pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
+        if (cpu_is_at91sam9g45()) {
+                mckr = at91_sys_read(AT91_PMC_MCKR);
+                plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
+        }
-        if (cpu_has_upll() && !cpu_has_pllb()) {
+        if (!cpu_has_pllb() && cpu_has_upll()) {
                /* setup UTMI clock as the fourth primary clock
                 * (instead of pllb) */
                utmi_clk.type |= CLK_TYPE_PRIMARY;
@@ -701,6 +742,9 @@ int __init at91_clock_init(unsigned long main_clock)
                        freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
                if (mckr & AT91_PMC_PDIV)
                        freq /= 2;              /* processor clock division */
+        } else if (cpu_is_at91sam9g45()) {
+                mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
+                        freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
        } else {
                mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));      /* mdiv */
        }
diff --git a/arch/arm/mach-at91/generic.h b/arch/arm/mach-at91/generic.h
index b5daf7f5e011..88e413b38480 100644
--- a/arch/arm/mach-at91/generic.h
+++ b/arch/arm/mach-at91/generic.h
@@ -14,6 +14,7 @@ extern void __init at91sam9260_initialize(unsigned long main_clock);
 extern void __init at91sam9261_initialize(unsigned long main_clock);
 extern void __init at91sam9263_initialize(unsigned long main_clock);
 extern void __init at91sam9rl_initialize(unsigned long main_clock);
+extern void __init at91sam9g45_initialize(unsigned long main_clock);
 extern void __init at91x40_initialize(unsigned long main_clock);
 extern void __init at91cap9_initialize(unsigned long main_clock);
@@ -23,6 +24,7 @@ extern void __init at91sam9260_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9261_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9263_init_interrupts(unsigned int priority[]);
 extern void __init at91sam9rl_init_interrupts(unsigned int priority[]);
+extern void __init at91sam9g45_init_interrupts(unsigned int priority[]);
 extern void __init at91x40_init_interrupts(unsigned int priority[]);
 extern void __init at91cap9_init_interrupts(unsigned int priority[]);
 extern void __init at91_aic_init(unsigned int priority[]);
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index f2236f0e101f..ae4772e744ac 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -44,13 +44,11 @@ static int at91_gpiolib_direction_output(struct gpio_chip *chip,
                                         unsigned offset, int val);
 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
                                        unsigned offset);
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
 #define AT91_GPIO_CHIP(name, base_gpio, nr_gpio)                        \
        {                                                               \
                .chip = {                                               \
                        .label            = name,                       \
-                        .request          = at91_gpiolib_request,       \
                        .direction_input  = at91_gpiolib_direction_input, \
                        .direction_output = at91_gpiolib_direction_output, \
                        .get              = at91_gpiolib_get,           \
@@ -588,19 +586,6 @@ static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
        __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
 }
-static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
-{
-        unsigned pin = chip->base + offset;
-        void __iomem *pio = pin_to_controller(pin);
-        unsigned mask = pin_to_mask(pin);
-        /* Cannot request GPIOs that are in alternate function mode */
-        if (!(__raw_readl(pio + PIO_PSR) & mask))
-                return -EPERM;
-        return 0;
-}
 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 {
        int i;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 3a348ca20773..87de8be17484 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -95,6 +95,9 @@
 #define AT91SAM9261_SRAM_BASE   0x00300000      /* Internal SRAM base address */
 #define AT91SAM9261_SRAM_SIZE   0x00028000      /* Internal SRAM size (160Kb) */
+#define AT91SAM9G10_SRAM_BASE   AT91SAM9261_SRAM_BASE   /* Internal SRAM base address */
+#define AT91SAM9G10_SRAM_SIZE   0x00004000      /* Internal SRAM size (16Kb) */
 #define AT91SAM9261_ROM_BASE    0x00400000      /* Internal ROM base address */
 #define AT91SAM9261_ROM_SIZE    SZ_32K          /* Internal ROM size (32Kb) */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
new file mode 100644
index 000000000000..a526869aee37
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -0,0 +1,155 @@
+/*
+ * Chip-specific header file for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2008-2009 Atmel Corporation.
+ *
+ * Common definitions.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9G45_H
+#define AT91SAM9G45_H
+/*
+ * Peripheral identifiers/interrupts.
+ */
+#define AT91_ID_FIQ             0       /* Advanced Interrupt Controller (FIQ) */
+#define AT91_ID_SYS             1       /* System Controller Interrupt */
+#define AT91SAM9G45_ID_PIOA     2       /* Parallel I/O Controller A */
+#define AT91SAM9G45_ID_PIOB     3       /* Parallel I/O Controller B */
+#define AT91SAM9G45_ID_PIOC     4       /* Parallel I/O Controller C */
+#define AT91SAM9G45_ID_PIODE    5       /* Parallel I/O Controller D and E */
+#define AT91SAM9G45_ID_TRNG     6       /* True Random Number Generator */
+#define AT91SAM9G45_ID_US0      7       /* USART 0 */
+#define AT91SAM9G45_ID_US1      8       /* USART 1 */
+#define AT91SAM9G45_ID_US2      9       /* USART 2 */
+#define AT91SAM9G45_ID_US3      10      /* USART 3 */
+#define AT91SAM9G45_ID_MCI0     11      /* High Speed Multimedia Card Interface 0 */
+#define AT91SAM9G45_ID_TWI0     12      /* Two-Wire Interface 0 */
+#define AT91SAM9G45_ID_TWI1     13      /* Two-Wire Interface 1 */
+#define AT91SAM9G45_ID_SPI0     14      /* Serial Peripheral Interface 0 */
+#define AT91SAM9G45_ID_SPI1     15      /* Serial Peripheral Interface 1 */
+#define AT91SAM9G45_ID_SSC0     16      /* Synchronous Serial Controller 0 */
+#define AT91SAM9G45_ID_SSC1     17      /* Synchronous Serial Controller 1 */
+#define AT91SAM9G45_ID_TCB      18      /* Timer Counter 0, 1, 2, 3, 4 and 5 */
+#define AT91SAM9G45_ID_PWMC     19      /* Pulse Width Modulation Controller */
+#define AT91SAM9G45_ID_TSC      20      /* Touch Screen ADC Controller */
+#define AT91SAM9G45_ID_DMA      21      /* DMA Controller */
+#define AT91SAM9G45_ID_UHPHS    22      /* USB Host High Speed */
+#define AT91SAM9G45_ID_LCDC     23      /* LCD Controller */
+#define AT91SAM9G45_ID_AC97C    24      /* AC97 Controller */
+#define AT91SAM9G45_ID_EMAC     25      /* Ethernet MAC */
+#define AT91SAM9G45_ID_ISI      26      /* Image Sensor Interface */
+#define AT91SAM9G45_ID_UDPHS    27      /* USB Device High Speed */
+#define AT91SAM9G45_ID_AESTDESSHA 28    /* AES + T-DES + SHA */
+#define AT91SAM9G45_ID_MCI1     29      /* High Speed Multimedia Card Interface 1 */
+#define AT91SAM9G45_ID_VDEC     30      /* Video Decoder */
+#define AT91SAM9G45_ID_IRQ0     31      /* Advanced Interrupt Controller */
+/*
+ * User Peripheral physical base addresses.
+ */
+#define AT91SAM9G45_BASE_UDPHS          0xfff78000
+#define AT91SAM9G45_BASE_TCB0           0xfff7c000
+#define AT91SAM9G45_BASE_TC0            0xfff7c000
+#define AT91SAM9G45_BASE_TC1            0xfff7c040
+#define AT91SAM9G45_BASE_TC2            0xfff7c080
+#define AT91SAM9G45_BASE_MCI0           0xfff80000
+#define AT91SAM9G45_BASE_TWI0           0xfff84000
+#define AT91SAM9G45_BASE_TWI1           0xfff88000
+#define AT91SAM9G45_BASE_US0            0xfff8c000
+#define AT91SAM9G45_BASE_US1            0xfff90000
+#define AT91SAM9G45_BASE_US2            0xfff94000
+#define AT91SAM9G45_BASE_US3            0xfff98000
+#define AT91SAM9G45_BASE_SSC0           0xfff9c000
+#define AT91SAM9G45_BASE_SSC1           0xfffa0000
+#define AT91SAM9G45_BASE_SPI0           0xfffa4000
+#define AT91SAM9G45_BASE_SPI1           0xfffa8000
+#define AT91SAM9G45_BASE_AC97C          0xfffac000
+#define AT91SAM9G45_BASE_TSC            0xfffb0000
+#define AT91SAM9G45_BASE_ISI            0xfffb4000
+#define AT91SAM9G45_BASE_PWMC           0xfffb8000
+#define AT91SAM9G45_BASE_EMAC           0xfffbc000
+#define AT91SAM9G45_BASE_AES            0xfffc0000
+#define AT91SAM9G45_BASE_TDES           0xfffc4000
+#define AT91SAM9G45_BASE_SHA            0xfffc8000
+#define AT91SAM9G45_BASE_TRNG           0xfffcc000
+#define AT91SAM9G45_BASE_MCI1           0xfffd0000
+#define AT91SAM9G45_BASE_TCB1           0xfffd4000
+#define AT91SAM9G45_BASE_TC3            0xfffd4000
+#define AT91SAM9G45_BASE_TC4            0xfffd4040
+#define AT91SAM9G45_BASE_TC5            0xfffd4080
+#define AT91_BASE_SYS                   0xffffe200
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_ECC        (0xffffe200 - AT91_BASE_SYS)
+#define AT91_DDRSDRC1   (0xffffe400 - AT91_BASE_SYS)
+#define AT91_DDRSDRC0   (0xffffe600 - AT91_BASE_SYS)
+#define AT91_SMC        (0xffffe800 - AT91_BASE_SYS)
+#define AT91_MATRIX     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_DMA        (0xffffec00 - AT91_BASE_SYS)
+#define AT91_DBGU       (0xffffee00 - AT91_BASE_SYS)
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
+#define AT91_PIOA       (0xfffff200 - AT91_BASE_SYS)
+#define AT91_PIOB       (0xfffff400 - AT91_BASE_SYS)
+#define AT91_PIOC       (0xfffff600 - AT91_BASE_SYS)
+#define AT91_PIOD       (0xfffff800 - AT91_BASE_SYS)
+#define AT91_PIOE       (0xfffffa00 - AT91_BASE_SYS)
+#define AT91_PMC        (0xfffffc00 - AT91_BASE_SYS)
+#define AT91_RSTC       (0xfffffd00 - AT91_BASE_SYS)
+#define AT91_SHDWC      (0xfffffd10 - AT91_BASE_SYS)
+#define AT91_RTT        (0xfffffd20 - AT91_BASE_SYS)
+#define AT91_PIT        (0xfffffd30 - AT91_BASE_SYS)
+#define AT91_WDT        (0xfffffd40 - AT91_BASE_SYS)
+#define AT91_GPBR       (0xfffffd60 - AT91_BASE_SYS)
+#define AT91_RTC        (0xfffffdb0 - AT91_BASE_SYS)
+#define AT91_USART0     AT91SAM9G45_BASE_US0
+#define AT91_USART1     AT91SAM9G45_BASE_US1
+#define AT91_USART2     AT91SAM9G45_BASE_US2
+#define AT91_USART3     AT91SAM9G45_BASE_US3
+/*
+ * Internal Memory.
+ */
+#define AT91SAM9G45_SRAM_BASE   0x00300000      /* Internal SRAM base address */
+#define AT91SAM9G45_SRAM_SIZE   SZ_64K          /* Internal SRAM size (64Kb) */
+#define AT91SAM9G45_ROM_BASE    0x00400000      /* Internal ROM base address */
+#define AT91SAM9G45_ROM_SIZE    SZ_64K          /* Internal ROM size (64Kb) */
+#define AT91SAM9G45_LCDC_BASE   0x00500000      /* LCD Controller */
+#define AT91SAM9G45_UDPHS_FIFO  0x00600000      /* USB Device HS controller */
+#define AT91SAM9G45_OHCI_BASE   0x00700000      /* USB Host controller (OHCI) */
+#define AT91SAM9G45_EHCI_BASE   0x00800000      /* USB Host controller (EHCI) */
+#define AT91SAM9G45_VDEC_BASE   0x00900000      /* Video Decoder Controller */
+#define CONFIG_DRAM_BASE        AT91_CHIPSELECT_6
+#define CONSISTENT_DMA_SIZE     SZ_4M
+/*
+ * DMA peripheral identifiers
+ * for hardware handshaking interface
+ */
+#define AT_DMA_ID_MCI0           0
+#define AT_DMA_ID_SPI0_TX        1
+#define AT_DMA_ID_SPI0_RX        2
+#define AT_DMA_ID_SPI1_TX        3
+#define AT_DMA_ID_SPI1_RX        4
+#define AT_DMA_ID_SSC0_TX        5
+#define AT_DMA_ID_SSC0_RX        6
+#define AT_DMA_ID_SSC1_TX        7
+#define AT_DMA_ID_SSC1_RX        8
+#define AT_DMA_ID_AC97_TX        9
+#define AT_DMA_ID_AC97_RX       10
+#define AT_DMA_ID_MCI1          13
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
new file mode 100644
index 000000000000..c972d60e0aeb
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -0,0 +1,153 @@
+/*
+ * Matrix-centric header file for the AT91SAM9G45 family
+ *
+ *  Copyright (C) 2008-2009 Atmel Corporation.
+ *
+ * Memory Controllers (MATRIX, EBI) - System peripherals registers.
+ * Based on AT91SAM9G45 preliminary datasheet.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91SAM9G45_MATRIX_H
+#define AT91SAM9G45_MATRIX_H
+#define AT91_MATRIX_MCFG0       (AT91_MATRIX + 0x00)    /* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1       (AT91_MATRIX + 0x04)    /* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2       (AT91_MATRIX + 0x08)    /* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3       (AT91_MATRIX + 0x0C)    /* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4       (AT91_MATRIX + 0x10)    /* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5       (AT91_MATRIX + 0x14)    /* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6       (AT91_MATRIX + 0x18)    /* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7       (AT91_MATRIX + 0x1C)    /* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8       (AT91_MATRIX + 0x20)    /* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9       (AT91_MATRIX + 0x24)    /* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10      (AT91_MATRIX + 0x28)    /* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11      (AT91_MATRIX + 0x2C)    /* Master Configuration Register 11 */
+#define         AT91_MATRIX_ULBT        (7 << 0)        /* Undefined Length Burst Type */
+#define                 AT91_MATRIX_ULBT_INFINITE       (0 << 0)
+#define                 AT91_MATRIX_ULBT_SINGLE         (1 << 0)
+#define                 AT91_MATRIX_ULBT_FOUR           (2 << 0)
+#define                 AT91_MATRIX_ULBT_EIGHT          (3 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTEEN        (4 << 0)
+#define                 AT91_MATRIX_ULBT_THIRTYTWO      (5 << 0)
+#define                 AT91_MATRIX_ULBT_SIXTYFOUR      (6 << 0)
+#define                 AT91_MATRIX_ULBT_128            (7 << 0)
+#define AT91_MATRIX_SCFG0       (AT91_MATRIX + 0x40)    /* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1       (AT91_MATRIX + 0x44)    /* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2       (AT91_MATRIX + 0x48)    /* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3       (AT91_MATRIX + 0x4C)    /* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4       (AT91_MATRIX + 0x50)    /* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5       (AT91_MATRIX + 0x54)    /* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6       (AT91_MATRIX + 0x58)    /* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7       (AT91_MATRIX + 0x5C)    /* Slave Configuration Register 7 */
+#define         AT91_MATRIX_SLOT_CYCLE          (0x1ff << 0)    /* Maximum Number of Allowed Cycles for a Burst */
+#define         AT91_MATRIX_DEFMSTR_TYPE        (3    << 16)    /* Default Master Type */
+#define                 AT91_MATRIX_DEFMSTR_TYPE_NONE   (0 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_LAST   (1 << 16)
+#define                 AT91_MATRIX_DEFMSTR_TYPE_FIXED  (2 << 16)
+#define         AT91_MATRIX_FIXED_DEFMSTR       (0xf  << 18)    /* Fixed Index of Default Master */
+#define AT91_MATRIX_PRAS0       (AT91_MATRIX + 0x80)    /* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0       (AT91_MATRIX + 0x84)    /* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1       (AT91_MATRIX + 0x88)    /* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1       (AT91_MATRIX + 0x8C)    /* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2       (AT91_MATRIX + 0x90)    /* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2       (AT91_MATRIX + 0x94)    /* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3       (AT91_MATRIX + 0x98)    /* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3       (AT91_MATRIX + 0x9C)    /* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4       (AT91_MATRIX + 0xA0)    /* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4       (AT91_MATRIX + 0xA4)    /* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5       (AT91_MATRIX + 0xA8)    /* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5       (AT91_MATRIX + 0xAC)    /* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6       (AT91_MATRIX + 0xB0)    /* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6       (AT91_MATRIX + 0xB4)    /* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7       (AT91_MATRIX + 0xB8)    /* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7       (AT91_MATRIX + 0xBC)    /* Priority Register B for Slave 7 */
+#define         AT91_MATRIX_M0PR                (3 << 0)        /* Master 0 Priority */
+#define         AT91_MATRIX_M1PR                (3 << 4)        /* Master 1 Priority */
+#define         AT91_MATRIX_M2PR                (3 << 8)        /* Master 2 Priority */
+#define         AT91_MATRIX_M3PR                (3 << 12)       /* Master 3 Priority */
+#define         AT91_MATRIX_M4PR                (3 << 16)       /* Master 4 Priority */
+#define         AT91_MATRIX_M5PR                (3 << 20)       /* Master 5 Priority */
+#define         AT91_MATRIX_M6PR                (3 << 24)       /* Master 6 Priority */
+#define         AT91_MATRIX_M7PR                (3 << 28)       /* Master 7 Priority */
+#define         AT91_MATRIX_M8PR                (3 << 0)        /* Master 8 Priority (in Register B) */
+#define         AT91_MATRIX_M9PR                (3 << 4)        /* Master 9 Priority (in Register B) */
+#define         AT91_MATRIX_M10PR               (3 << 8)        /* Master 10 Priority (in Register B) */
+#define         AT91_MATRIX_M11PR               (3 << 12)       /* Master 11 Priority (in Register B) */
+#define AT91_MATRIX_MRCR        (AT91_MATRIX + 0x100)   /* Master Remap Control Register */
+#define         AT91_MATRIX_RCB0                (1 << 0)        /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define         AT91_MATRIX_RCB1                (1 << 1)        /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define         AT91_MATRIX_RCB2                (1 << 2)
+#define         AT91_MATRIX_RCB3                (1 << 3)
+#define         AT91_MATRIX_RCB4                (1 << 4)
+#define         AT91_MATRIX_RCB5                (1 << 5)
+#define         AT91_MATRIX_RCB6                (1 << 6)
+#define         AT91_MATRIX_RCB7                (1 << 7)
+#define         AT91_MATRIX_RCB8                (1 << 8)
+#define         AT91_MATRIX_RCB9                (1 << 9)
+#define         AT91_MATRIX_RCB10               (1 << 10)
+#define         AT91_MATRIX_RCB11               (1 << 11)
+#define AT91_MATRIX_TCMR        (AT91_MATRIX + 0x110)   /* TCM Configuration Register */
+#define         AT91_MATRIX_ITCM_SIZE           (0xf << 0)      /* Size of ITCM enabled memory block */
+#define                 AT91_MATRIX_ITCM_0              (0 << 0)
+#define                 AT91_MATRIX_ITCM_32             (6 << 0)
+#define         AT91_MATRIX_DTCM_SIZE           (0xf << 4)      /* Size of DTCM enabled memory block */
+#define                 AT91_MATRIX_DTCM_0              (0 << 4)
+#define                 AT91_MATRIX_DTCM_32             (6 << 4)
+#define                 AT91_MATRIX_DTCM_64             (7 << 4)
+#define         AT91_MATRIX_TCM_NWS             (0x1 << 11)     /* Wait state TCM register */
+#define                 AT91_MATRIX_TCM_NO_WS           (0x0 << 11)
+#define                 AT91_MATRIX_TCM_ONE_WS          (0x1 << 11)
+#define AT91_MATRIX_VIDEO       (AT91_MATRIX + 0x118)   /* Video Mode Configuration Register */
+#define         AT91C_VDEC_SEL                  (0x1 <<  0) /* Video Mode Selection */
+#define                 AT91C_VDEC_SEL_OFF              (0 << 0)
+#define                 AT91C_VDEC_SEL_ON               (1 << 0)
+#define AT91_MATRIX_EBICSA      (AT91_MATRIX + 0x128)   /* EBI Chip Select Assignment Register */
+#define         AT91_MATRIX_EBI_CS1A            (1 << 1)        /* Chip Select 1 Assignment */
+#define                 AT91_MATRIX_EBI_CS1A_SMC                (0 << 1)
+#define                 AT91_MATRIX_EBI_CS1A_SDRAMC             (1 << 1)
+#define         AT91_MATRIX_EBI_CS3A            (1 << 3)        /* Chip Select 3 Assignment */
+#define                 AT91_MATRIX_EBI_CS3A_SMC                (0 << 3)
+#define                 AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA     (1 << 3)
+#define         AT91_MATRIX_EBI_CS4A            (1 << 4)        /* Chip Select 4 Assignment */
+#define                 AT91_MATRIX_EBI_CS4A_SMC                (0 << 4)
+#define                 AT91_MATRIX_EBI_CS4A_SMC_CF0            (1 << 4)
+#define         AT91_MATRIX_EBI_CS5A            (1 << 5)        /* Chip Select 5 Assignment */
+#define                 AT91_MATRIX_EBI_CS5A_SMC                (0 << 5)
+#define                 AT91_MATRIX_EBI_CS5A_SMC_CF1            (1 << 5)
+#define         AT91_MATRIX_EBI_DBPUC           (1 << 8)        /* Data Bus Pull-up Configuration */
+#define                 AT91_MATRIX_EBI_DBPU_ON                 (0 << 8)
+#define                 AT91_MATRIX_EBI_DBPU_OFF                (1 << 8)
+#define         AT91_MATRIX_EBI_VDDIOMSEL       (1 << 16)       /* Memory voltage selection */
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_1_8V          (0 << 16)
+#define                 AT91_MATRIX_EBI_VDDIOMSEL_3_3V          (1 << 16)
+#define         AT91_MATRIX_EBI_EBI_IOSR        (1 << 17)       /* EBI I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_EBI_IOSR_REDUCED        (0 << 17)
+#define                 AT91_MATRIX_EBI_EBI_IOSR_NORMAL         (1 << 17)
+#define         AT91_MATRIX_EBI_DDR_IOSR        (1 << 18)       /* DDR2 dedicated port I/O slew rate selection */
+#define                 AT91_MATRIX_EBI_DDR_IOSR_REDUCED        (0 << 18)
+#define                 AT91_MATRIX_EBI_DDR_IOSR_NORMAL         (1 << 18)
+#define AT91_MATRIX_WPMR        (AT91_MATRIX + 0x1E4)   /* Write Protect Mode Register */
+#define         AT91_MATRIX_WPMR_WPEN           (1 << 0)        /* Write Protect ENable */
+#define                 AT91_MATRIX_WPMR_WP_WPDIS               (0 << 0)
+#define                 AT91_MATRIX_WPMR_WP_WPEN                (1 << 0)
+#define         AT91_MATRIX_WPMR_WPKEY          (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91_MATRIX_WPSR        (AT91_MATRIX + 0x1E8)   /* Write Protect Status Register */
+#define         AT91_MATRIX_WPSR_WPVS           (1 << 0)        /* Write Protect Violation Status */
+#define                 AT91_MATRIX_WPSR_NO_WPV         (0 << 0)
+#define                 AT91_MATRIX_WPSR_WPV            (1 << 0)
+#define         AT91_MATRIX_WPSR_WPVSRC         (0xFFFF << 8)   /* Write Protect Violation Source */
+#endif
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index e6afff849b85..13f27a4b882d 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -37,6 +37,7 @@
 #include <linux/leds.h>
 #include <linux/spi/spi.h>
 #include <linux/usb/atmel_usba_udc.h>
+#include <sound/atmel-ac97c.h>
 /* USB Device */
 struct at91_udc_data {
@@ -80,7 +81,8 @@ struct at91_eth_data {
 };
 extern void __init at91_add_device_eth(struct at91_eth_data *data);
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
+#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9) \
+        || defined(CONFIG_ARCH_AT91SAM9G45)
 #define eth_platform_data       at91_eth_data
 #endif
@@ -90,6 +92,7 @@ struct at91_usbh_data {
        u8              vbus_pin[2];    /* port power-control pin */
 };
 extern void __init at91_add_device_usbh(struct at91_usbh_data *data);
+extern void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data);
 /* NAND / SmartMedia */
 struct atmel_nand_data {
@@ -105,7 +108,11 @@ struct atmel_nand_data {
 extern void __init at91_add_device_nand(struct atmel_nand_data *data);
 /* I2C*/
+#if defined(CONFIG_ARCH_AT91SAM9G45)
+extern void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices);
+#else
 extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices);
+#endif
 /* SPI */
 extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
@@ -168,10 +175,7 @@ struct atmel_lcdfb_info;
 extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
 /* AC97 */
-struct atmel_ac97_data {
+extern void __init at91_add_device_ac97(struct ac97c_platform_data *data);
-        u8              reset_pin;      /* reset */
-};
-extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
 /* ISI */
 extern void __init at91_add_device_isi(void);
diff --git a/arch/arm/mach-at91/include/mach/cpu.h b/arch/arm/mach-at91/include/mach/cpu.h
index c554c3e4d553..34a9502c48bc 100644
--- a/arch/arm/mach-at91/include/mach/cpu.h
+++ b/arch/arm/mach-at91/include/mach/cpu.h
@@ -21,8 +21,10 @@
 #define ARCH_ID_AT91SAM9260     0x019803a0
 #define ARCH_ID_AT91SAM9261     0x019703a0
 #define ARCH_ID_AT91SAM9263     0x019607a0
+#define ARCH_ID_AT91SAM9G10     0x819903a0
 #define ARCH_ID_AT91SAM9G20     0x019905a0
 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
+#define ARCH_ID_AT91SAM9G45     0x819b05a0
 #define ARCH_ID_AT91CAP9        0x039A03A0
 #define ARCH_ID_AT91SAM9XE128   0x329973a0
@@ -39,6 +41,15 @@ static inline unsigned long at91_cpu_identify(void)
        return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
 }
+#define ARCH_EXID_AT91SAM9M11   0x00000001
+#define ARCH_EXID_AT91SAM9M10   0x00000002
+#define ARCH_EXID_AT91SAM9G45   0x00000004
+static inline unsigned long at91_exid_identify(void)
+{
+        return at91_sys_read(AT91_DBGU_EXID);
+}
 #define ARCH_FAMILY_AT91X92     0x09200000
 #define ARCH_FAMILY_AT91SAM9    0x01900000
@@ -87,6 +98,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91sam9261()    (0)
 #endif
+#ifdef CONFIG_ARCH_AT91SAM9G10
+#define cpu_is_at91sam9g10()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G10)
+#else
+#define cpu_is_at91sam9g10()    (0)
+#endif
 #ifdef CONFIG_ARCH_AT91SAM9263
 #define cpu_is_at91sam9263()    (at91_cpu_identify() == ARCH_ID_AT91SAM9263)
 #else
@@ -99,6 +116,12 @@ static inline unsigned long at91cap9_rev_identify(void)
 #define cpu_is_at91sam9rl()     (0)
 #endif
+#ifdef CONFIG_ARCH_AT91SAM9G45
+#define cpu_is_at91sam9g45()    (at91_cpu_identify() == ARCH_ID_AT91SAM9G45)
+#else
+#define cpu_is_at91sam9g45()    (0)
+#endif
 #ifdef CONFIG_ARCH_AT91CAP9
 #define cpu_is_at91cap9()       (at91_cpu_identify() == ARCH_ID_AT91CAP9)
 #define cpu_is_at91cap9_revB()  (at91cap9_rev_identify() == ARCH_REVISION_CAP9_B)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index da0b681c652c..a0df8b022df2 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -20,12 +20,14 @@
 #include <mach/at91rm9200.h>
 #elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
 #include <mach/at91sam9260.h>
-#elif defined(CONFIG_ARCH_AT91SAM9261)
+#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
 #include <mach/at91sam9261.h>
 #elif defined(CONFIG_ARCH_AT91SAM9263)
 #include <mach/at91sam9263.h>
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
 #include <mach/at91sam9rl.h>
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#include <mach/at91sam9g45.h>
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #include <mach/at91cap9.h>
 #elif defined(CONFIG_ARCH_AT91X40)
diff --git a/arch/arm/mach-at91/include/mach/timex.h b/arch/arm/mach-at91/include/mach/timex.h
index d84c9948becf..31ac2d97f14c 100644
--- a/arch/arm/mach-at91/include/mach/timex.h
+++ b/arch/arm/mach-at91/include/mach/timex.h
@@ -42,6 +42,11 @@
 #define AT91SAM9_MASTER_CLOCK   99300000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+#elif defined(CONFIG_ARCH_AT91SAM9G10)
+#define AT91SAM9_MASTER_CLOCK   133000000
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 #elif defined(CONFIG_ARCH_AT91SAM9263)
 #if defined(CONFIG_MACH_USB_A9263)
@@ -62,6 +67,11 @@
 #define AT91SAM9_MASTER_CLOCK   132096000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+#elif defined(CONFIG_ARCH_AT91SAM9G45)
+#define AT91SAM9_MASTER_CLOCK   133333333
+#define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
 #elif defined(CONFIG_ARCH_AT91CAP9)
 #define AT91CAP9_MASTER_CLOCK   100000000
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index e26c4fe61fae..4028724d490d 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -201,7 +201,8 @@ static int at91_pm_verify_clocks(void)
                        pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
                        return 0;
                }
-        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263() || cpu_is_at91sam9g20()) {
+        } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() || cpu_is_at91sam9263()
+                        || cpu_is_at91sam9g20() || cpu_is_at91sam9g10()) {
                if ((scsr & (AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP)) != 0) {
                        pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
                        return 0;
diff --git a/arch/arm/mach-bcmring/Kconfig b/arch/arm/mach-bcmring/Kconfig
new file mode 100644
index 000000000000..457b4384913e
--- /dev/null
+++ b/arch/arm/mach-bcmring/Kconfig
@@ -0,0 +1,21 @@
+choice
+        prompt "Processor selection in BCMRING family of devices"
+        depends on ARCH_BCMRING
+        default ARCH_BCM11107
+config ARCH_FPGA11107
+        bool "FPGA11107"
+config ARCH_BCM11107
+        bool "BCM11107"
+endchoice
+menu "BCMRING Options"
+        depends on ARCH_BCMRING
+config BCM_ZRELADDR
+        hex "Compressed ZREL ADDR"
+endmenu
+# source "drivers/char/bcmring/Kconfig"
diff --git a/arch/arm/mach-bcmring/Makefile b/arch/arm/mach-bcmring/Makefile
new file mode 100644
index 000000000000..f8d9fcedf917
--- /dev/null
+++ b/arch/arm/mach-bcmring/Makefile
@@ -0,0 +1,8 @@
+#
+# Makefile for the linux kernel.
+#
+# Object file lists.
+obj-y := arch.o mm.o irq.o clock.o core.o timer.o dma.o
+obj-y += csp/
diff --git a/arch/arm/mach-bcmring/Makefile.boot b/arch/arm/mach-bcmring/Makefile.boot
new file mode 100644
index 000000000000..fb53b283bebb
--- /dev/null
+++ b/arch/arm/mach-bcmring/Makefile.boot
@@ -0,0 +1,6 @@
+# Address where decompressor will be written and eventually executed.
+#
+# default to SDRAM
+zreladdr-y      := $(CONFIG_BCM_ZRELADDR)
+params_phys-y   := 0x00000800
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
new file mode 100644
index 000000000000..0da693b0f7e1
--- /dev/null
+++ b/arch/arm/mach-bcmring/arch.c
@@ -0,0 +1,157 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <linux/proc_fs.h>
+#include <linux/sysctl.h>
+#include <asm/irq.h>
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <mach/dma.h>
+#include <mach/hardware.h>
+#include <mach/csp/mm_io.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <cfg_global.h>
+#include "core.h"
+HW_DECLARE_SPINLOCK(arch)
+HW_DECLARE_SPINLOCK(gpio)
+#if defined(CONFIG_DEBUG_SPINLOCK)
+    EXPORT_SYMBOL(bcmring_gpio_reg_lock);
+#endif
+/* FIXME: temporary solution */
+#define BCM_SYSCTL_REBOOT_WARM               1
+#define CTL_BCM_REBOOT                 112
+/* sysctl */
+int bcmring_arch_warm_reboot;   /* do a warm reboot on hard reset */
+static struct ctl_table_header *bcmring_sysctl_header;
+static struct ctl_table bcmring_sysctl_warm_reboot[] = {
+        {
+         .ctl_name = BCM_SYSCTL_REBOOT_WARM,
+         .procname = "warm",
+         .data = &bcmring_arch_warm_reboot,
+         .maxlen = sizeof(int),
+         .mode = 0644,
+         .proc_handler = &proc_dointvec},
+        {}
+};
+static struct ctl_table bcmring_sysctl_reboot[] = {
+        {
+         .ctl_name = CTL_BCM_REBOOT,
+         .procname = "reboot",
+         .mode = 0555,
+         .child = bcmring_sysctl_warm_reboot},
+        {}
+};
+static struct platform_device nand_device = {
+        .name = "bcm-nand",
+        .id = -1,
+};
+static struct platform_device *devices[] __initdata = {
+        &nand_device,
+};
+/****************************************************************************
+*
+*   Called from the customize_machine function in arch/arm/kernel/setup.c
+*
+*   The customize_machine function is tagged as an arch_initcall
+*   (see include/linux/init.h for the order that the various init sections
+*   are called in.
+*
+*****************************************************************************/
+static void __init bcmring_init_machine(void)
+{
+        bcmring_sysctl_header = register_sysctl_table(bcmring_sysctl_reboot);
+        /* Enable spread spectrum */
+        chipcHw_enableSpreadSpectrum();
+        platform_add_devices(devices, ARRAY_SIZE(devices));
+        bcmring_amba_init();
+        dma_init();
+}
+/****************************************************************************
+*
+*   Called from setup_arch (in arch/arm/kernel/setup.c) to fixup any tags
+*   passed in by the boot loader.
+*
+*****************************************************************************/
+static void __init bcmring_fixup(struct machine_desc *desc,
+     struct tag *t, char **cmdline, struct meminfo *mi) {
+#ifdef CONFIG_BLK_DEV_INITRD
+        printk(KERN_NOTICE "bcmring_fixup\n");
+        t->hdr.tag = ATAG_CORE;
+        t->hdr.size = tag_size(tag_core);
+        t->u.core.flags = 0;
+        t->u.core.pagesize = PAGE_SIZE;
+        t->u.core.rootdev = 31 << 8 | 0;
+        t = tag_next(t);
+        t->hdr.tag = ATAG_MEM;
+        t->hdr.size = tag_size(tag_mem32);
+        t->u.mem.start = CFG_GLOBAL_RAM_BASE;
+        t->u.mem.size = CFG_GLOBAL_RAM_SIZE;
+        t = tag_next(t);
+        t->hdr.tag = ATAG_NONE;
+        t->hdr.size = 0;
+#endif
+}
+/****************************************************************************
+*
+*   Machine Description
+*
+*****************************************************************************/
+MACHINE_START(BCMRING, "BCMRING")
+        /* Maintainer: Broadcom Corporation */
+        .phys_io = MM_IO_START,
+        .io_pg_offst = (MM_IO_BASE >> 18) & 0xfffc,
+        .fixup = bcmring_fixup,
+        .map_io = bcmring_map_io,
+        .init_irq = bcmring_init_irq,
+        .timer = &bcmring_timer,
+        .init_machine = bcmring_init_machine
+MACHINE_END
diff --git a/arch/arm/mach-bcmring/clock.c b/arch/arm/mach-bcmring/clock.c
new file mode 100644
index 000000000000..14bafc38f2dc
--- /dev/null
+++ b/arch/arm/mach-bcmring/clock.c
@@ -0,0 +1,224 @@
+/*****************************************************************************
+* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <mach/csp/hw_cfg.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_reg.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <asm/clkdev.h>
+#include "clock.h"
+#define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
+#define clk_is_pll1(x)          ((x)->type & CLK_TYPE_PLL1)
+#define clk_is_pll2(x)          ((x)->type & CLK_TYPE_PLL2)
+#define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
+#define clk_is_bypassable(x)    ((x)->type & CLK_TYPE_BYPASSABLE)
+#define clk_is_using_xtal(x)    ((x)->mode & CLK_MODE_XTAL)
+static DEFINE_SPINLOCK(clk_lock);
+static void __clk_enable(struct clk *clk)
+{
+        if (!clk)
+                return;
+        /* enable parent clock first */
+        if (clk->parent)
+                __clk_enable(clk->parent);
+        if (clk->use_cnt++ == 0) {
+                if (clk_is_pll1(clk)) { /* PLL1 */
+                        chipcHw_pll1Enable(clk->rate_hz, 0);
+                } else if (clk_is_pll2(clk)) {  /* PLL2 */
+                        chipcHw_pll2Enable(clk->rate_hz);
+                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
+                        if (!clk_is_primary(clk))
+                                chipcHw_bypassClockEnable(clk->csp_id);
+                } else {        /* source is PLL */
+                        chipcHw_setClockEnable(clk->csp_id);
+                }
+        }
+}
+int clk_enable(struct clk *clk)
+{
+        unsigned long flags;
+        if (!clk)
+                return -EINVAL;
+        spin_lock_irqsave(&clk_lock, flags);
+        __clk_enable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+static void __clk_disable(struct clk *clk)
+{
+        if (!clk)
+                return;
+        BUG_ON(clk->use_cnt == 0);
+        if (--clk->use_cnt == 0) {
+                if (clk_is_pll1(clk)) { /* PLL1 */
+                        chipcHw_pll1Disable();
+                } else if (clk_is_pll2(clk)) {  /* PLL2 */
+                        chipcHw_pll2Disable();
+                } else if (clk_is_using_xtal(clk)) {    /* source is crystal */
+                        if (!clk_is_primary(clk))
+                                chipcHw_bypassClockDisable(clk->csp_id);
+                } else {        /* source is PLL */
+                        chipcHw_setClockDisable(clk->csp_id);
+                }
+        }
+        if (clk->parent)
+                __clk_disable(clk->parent);
+}
+void clk_disable(struct clk *clk)
+{
+        unsigned long flags;
+        if (!clk)
+                return;
+        spin_lock_irqsave(&clk_lock, flags);
+        __clk_disable(clk);
+        spin_unlock_irqrestore(&clk_lock, flags);
+}
+EXPORT_SYMBOL(clk_disable);
+unsigned long clk_get_rate(struct clk *clk)
+{
+        if (!clk)
+                return 0;
+        return clk->rate_hz;
+}
+EXPORT_SYMBOL(clk_get_rate);
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        unsigned long actual;
+        unsigned long rate_hz;
+        if (!clk)
+                return -EINVAL;
+        if (!clk_is_programmable(clk))
+                return -EINVAL;
+        if (clk->use_cnt)
+                return -EBUSY;
+        spin_lock_irqsave(&clk_lock, flags);
+        actual = clk->parent->rate_hz;
+        rate_hz = min(actual, rate);
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return rate_hz;
+}
+EXPORT_SYMBOL(clk_round_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        unsigned long flags;
+        unsigned long actual;
+        unsigned long rate_hz;
+        if (!clk)
+                return -EINVAL;
+        if (!clk_is_programmable(clk))
+                return -EINVAL;
+        if (clk->use_cnt)
+                return -EBUSY;
+        spin_lock_irqsave(&clk_lock, flags);
+        actual = clk->parent->rate_hz;
+        rate_hz = min(actual, rate);
+        rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
+        clk->rate_hz = rate_hz;
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_rate);
+struct clk *clk_get_parent(struct clk *clk)
+{
+        if (!clk)
+                return NULL;
+        return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+        unsigned long flags;
+        struct clk *old_parent;
+        if (!clk || !parent)
+                return -EINVAL;
+        if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
+                return -EINVAL;
+        /* if more than one user, parent is not allowed */
+        if (clk->use_cnt > 1)
+                return -EBUSY;
+        if (clk->parent == parent)
+                return 0;
+        spin_lock_irqsave(&clk_lock, flags);
+        old_parent = clk->parent;
+        clk->parent = parent;
+        if (clk_is_using_xtal(parent))
+                clk->mode |= CLK_MODE_XTAL;
+        else
+                clk->mode &= (~CLK_MODE_XTAL);
+        /* if clock is active */
+        if (clk->use_cnt != 0) {
+                clk->use_cnt--;
+                /* enable clock with the new parent */
+                __clk_enable(clk);
+                /* disable the old parent */
+                __clk_disable(old_parent);
+        }
+        spin_unlock_irqrestore(&clk_lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(clk_set_parent);
diff --git a/arch/arm/mach-bcmring/clock.h b/arch/arm/mach-bcmring/clock.h
new file mode 100644
index 000000000000..5e0b98138973
--- /dev/null
+++ b/arch/arm/mach-bcmring/clock.h
@@ -0,0 +1,33 @@
+/*****************************************************************************
+* Copyright 2001 - 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <mach/csp/chipcHw_def.h>
+#define CLK_TYPE_PRIMARY         1      /* primary clock must NOT have a parent */
+#define CLK_TYPE_PLL1            2      /* PPL1 */
+#define CLK_TYPE_PLL2            4      /* PPL2 */
+#define CLK_TYPE_PROGRAMMABLE    8      /* programmable clock rate */
+#define CLK_TYPE_BYPASSABLE      16     /* parent can be changed */
+#define CLK_MODE_XTAL            1      /* clock source is from crystal */
+struct clk {
+        const char *name;       /* clock name */
+        unsigned int type;      /* clock type */
+        unsigned int mode;      /* current mode */
+        volatile int use_bypass;        /* indicate if it's in bypass mode */
+        chipcHw_CLOCK_e csp_id; /* clock ID for CSP CHIPC */
+        unsigned long rate_hz;  /* clock rate in Hz */
+        unsigned int use_cnt;   /* usage count */
+        struct clk *parent;     /* parent clock */
+};
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
new file mode 100644
index 000000000000..492c649f451e
--- /dev/null
+++ b/arch/arm/mach-bcmring/core.c
@@ -0,0 +1,367 @@
+/*
+ *  derived from linux/arch/arm/mach-versatile/core.c
+ *  linux/arch/arm/mach-bcmring/core.c
+ *
+ *  Copyright (C) 1999 - 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* Portions copyright Broadcom 2008 */
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/sysdev.h>
+#include <linux/interrupt.h>
+#include <linux/amba/bus.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/amba/bus.h>
+#include <mach/csp/mm_addr.h>
+#include <mach/hardware.h>
+#include <asm/clkdev.h>
+#include <linux/io.h>
+#include <asm/irq.h>
+#include <asm/hardware/arm_timer.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/flash.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/mach/mmc.h>
+#include <cfg_global.h>
+#include "clock.h"
+#include <csp/secHw.h>
+#include <mach/csp/secHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <mach/csp/tmrHw_reg.h>
+#define AMBA_DEVICE(name, initname, base, plat, size)       \
+static struct amba_device name##_device = {     \
+   .dev = {                                     \
+      .coherent_dma_mask = ~0,                  \
+      .init_name = initname,                    \
+      .platform_data = plat                     \
+   },                                           \
+   .res = {                                     \
+      .start = MM_ADDR_IO_##base,               \
+                .end = MM_ADDR_IO_##base + (size) - 1,    \
+      .flags = IORESOURCE_MEM                   \
+   },                                           \
+   .dma_mask = ~0,                              \
+   .irq = {                                     \
+      IRQ_##base                                \
+   }                                            \
+}
+AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
+AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
+static struct clk pll1_clk = {
+        .name = "PLL1",
+        .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
+        .rate_hz = 2000000000,
+        .use_cnt = 7,
+};
+static struct clk uart_clk = {
+        .name = "UART",
+        .type = CLK_TYPE_PROGRAMMABLE,
+        .csp_id = chipcHw_CLOCK_UART,
+        .rate_hz = HW_CFG_UART_CLK_HZ,
+        .parent = &pll1_clk,
+};
+static struct clk_lookup lookups[] = {
+        {                       /* UART0 */
+         .dev_id = "uarta",
+         .clk = &uart_clk,
+         }, {                   /* UART1 */
+             .dev_id = "uartb",
+             .clk = &uart_clk,
+             }
+};
+static struct amba_device *amba_devs[] __initdata = {
+        &uartA_device,
+        &uartB_device,
+};
+void __init bcmring_amba_init(void)
+{
+        int i;
+        u32 bus_clock;
+/* Linux is run initially in non-secure mode. Secure peripherals */
+/* generate FIQ, and must be handled in secure mode. Until we have */
+/* a linux security monitor implementation, keep everything in */
+/* non-secure mode. */
+        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
+        secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
+                          secHw_BLK_MASK_KEY_SCAN |
+                          secHw_BLK_MASK_TOUCH_SCREEN |
+                          secHw_BLK_MASK_UART0 |
+                          secHw_BLK_MASK_UART1 |
+                          secHw_BLK_MASK_WATCHDOG |
+                          secHw_BLK_MASK_SPUM |
+                          secHw_BLK_MASK_DDR2 |
+                          secHw_BLK_MASK_SPU |
+                          secHw_BLK_MASK_PKA |
+                          secHw_BLK_MASK_RNG |
+                          secHw_BLK_MASK_RTC |
+                          secHw_BLK_MASK_OTP |
+                          secHw_BLK_MASK_BOOT |
+                          secHw_BLK_MASK_MPU |
+                          secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
+        /* Only the devices attached to the AMBA bus are enabled just before the bus is */
+        /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
+        /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
+        /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
+        bus_clock = chipcHw_REG_BUS_CLOCK_GE
+            | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
+        chipcHw_busInterfaceClockEnable(bus_clock);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                struct amba_device *d = amba_devs[i];
+                amba_device_register(d, &iomem_resource);
+        }
+}
+/*
+ * Where is the timer (VA)?
+ */
+#define TIMER0_VA_BASE           MM_IO_BASE_TMR
+#define TIMER1_VA_BASE          (MM_IO_BASE_TMR + 0x20)
+#define TIMER2_VA_BASE          (MM_IO_BASE_TMR + 0x40)
+#define TIMER3_VA_BASE          (MM_IO_BASE_TMR + 0x60)
+/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically  150-166 MHz */
+#if defined(CONFIG_ARCH_FPGA11107)
+/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
+/* slow down Linux's sense of time */
+#define TIMER0_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
+#define TIMER1_FREQUENCY_MHZ  (tmrHw_LOW_FREQUENCY_MHZ * 30)
+#define TIMER3_FREQUENCY_MHZ  (tmrHw_HIGH_FREQUENCY_MHZ * 30)
+#define TIMER3_FREQUENCY_KHZ   (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
+#else
+#define TIMER0_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
+#define TIMER1_FREQUENCY_MHZ  tmrHw_LOW_FREQUENCY_MHZ
+#define TIMER3_FREQUENCY_MHZ  tmrHw_HIGH_FREQUENCY_MHZ
+#define TIMER3_FREQUENCY_KHZ  (tmrHw_HIGH_FREQUENCY_HZ / 1000)
+#endif
+#define TICKS_PER_uSEC     TIMER0_FREQUENCY_MHZ
+/*
+ *  These are useconds NOT ticks.
+ *
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+/*
+ * How long is the timer interval?
+ */
+#define TIMER_INTERVAL  (TICKS_PER_uSEC * mSEC_10)
+#if TIMER_INTERVAL >= 0x100000
+#define TIMER_RELOAD    (TIMER_INTERVAL >> 8)
+#define TIMER_DIVISOR   (TIMER_CTRL_DIV256)
+#define TICKS2USECS(x)  (256 * (x) / TICKS_PER_uSEC)
+#elif TIMER_INTERVAL >= 0x10000
+#define TIMER_RELOAD    (TIMER_INTERVAL >> 4)   /* Divide by 16 */
+#define TIMER_DIVISOR   (TIMER_CTRL_DIV16)
+#define TICKS2USECS(x)  (16 * (x) / TICKS_PER_uSEC)
+#else
+#define TIMER_RELOAD    (TIMER_INTERVAL)
+#define TIMER_DIVISOR   (TIMER_CTRL_DIV1)
+#define TICKS2USECS(x)  ((x) / TICKS_PER_uSEC)
+#endif
+static void timer_set_mode(enum clock_event_mode mode,
+                           struct clock_event_device *clk)
+{
+        unsigned long ctrl;
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
+                ctrl = TIMER_CTRL_PERIODIC;
+                ctrl |=
+                    TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
+                    TIMER_CTRL_ENABLE;
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* period set, and timer enabled in 'next_event' hook */
+                ctrl = TIMER_CTRL_ONESHOT;
+                ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                ctrl = 0;
+        }
+        writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
+}
+static int timer_set_next_event(unsigned long evt,
+                                struct clock_event_device *unused)
+{
+        unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
+        writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
+        writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
+        return 0;
+}
+static struct clock_event_device timer0_clockevent = {
+        .name = "timer0",
+        .shift = 32,
+        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode = timer_set_mode,
+        .set_next_event = timer_set_next_event,
+};
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &timer0_clockevent;
+        writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+static struct irqaction bcmring_timer_irq = {
+        .name = "bcmring Timer Tick",
+        .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler = bcmring_timer_interrupt,
+};
+static cycle_t bcmring_get_cycles_timer1(void)
+{
+        return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
+}
+static cycle_t bcmring_get_cycles_timer3(void)
+{
+        return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
+}
+static struct clocksource clocksource_bcmring_timer1 = {
+        .name = "timer1",
+        .rating = 200,
+        .read = bcmring_get_cycles_timer1,
+        .mask = CLOCKSOURCE_MASK(32),
+        .shift = 20,
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static struct clocksource clocksource_bcmring_timer3 = {
+        .name = "timer3",
+        .rating = 100,
+        .read = bcmring_get_cycles_timer3,
+        .mask = CLOCKSOURCE_MASK(32),
+        .shift = 20,
+        .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static int __init bcmring_clocksource_init(void)
+{
+        /* setup timer1 as free-running clocksource */
+        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
+        writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
+        writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
+        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
+               TIMER1_VA_BASE + TIMER_CTRL);
+        clocksource_bcmring_timer1.mult =
+            clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
+                                 clocksource_bcmring_timer1.shift);
+        clocksource_register(&clocksource_bcmring_timer1);
+        /* setup timer3 as free-running clocksource */
+        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+        writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
+        writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
+        writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
+               TIMER3_VA_BASE + TIMER_CTRL);
+        clocksource_bcmring_timer3.mult =
+            clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
+                                 clocksource_bcmring_timer3.shift);
+        clocksource_register(&clocksource_bcmring_timer3);
+        return 0;
+}
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+void __init bcmring_init_timer(void)
+{
+        printk(KERN_INFO "bcmring_init_timer\n");
+        /*
+         * Initialise to a known state (all timers off)
+         */
+        writel(0, TIMER0_VA_BASE + TIMER_CTRL);
+        writel(0, TIMER1_VA_BASE + TIMER_CTRL);
+        writel(0, TIMER2_VA_BASE + TIMER_CTRL);
+        writel(0, TIMER3_VA_BASE + TIMER_CTRL);
+        /*
+         * Make irqs happen for the system timer
+         */
+        setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
+        bcmring_clocksource_init();
+        timer0_clockevent.mult =
+            div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
+        timer0_clockevent.max_delta_ns =
+            clockevent_delta2ns(0xffffffff, &timer0_clockevent);
+        timer0_clockevent.min_delta_ns =
+            clockevent_delta2ns(0xf, &timer0_clockevent);
+        timer0_clockevent.cpumask = cpumask_of(0);
+        clockevents_register_device(&timer0_clockevent);
+}
+struct sys_timer bcmring_timer = {
+        .init = bcmring_init_timer,
+};
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
new file mode 100644
index 000000000000..b197ba48e36e
--- /dev/null
+++ b/arch/arm/mach-bcmring/core.h
@@ -0,0 +1,30 @@
+/*
+ *  linux/arch/arm/mach-versatile/core.h
+ *
+ *  Copyright (C) 2004 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* Portions copyright Broadcom 2008 */
+#ifndef __ASM_ARCH_BCMRING_H
+#define __ASM_ARCH_BCMRING_H
+void __init bcmring_amba_init(void);
+void __init bcmring_map_io(void);
+void __init bcmring_init_irq(void);
+extern struct sys_timer bcmring_timer;
+#endif
diff --git a/arch/arm/mach-bcmring/csp/Makefile b/arch/arm/mach-bcmring/csp/Makefile
new file mode 100644
index 000000000000..648c0377530e
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/Makefile
@@ -0,0 +1,3 @@
+obj-y += dmac/
+obj-y += tmr/
+obj-y += chipc/
diff --git a/arch/arm/mach-bcmring/csp/chipc/Makefile b/arch/arm/mach-bcmring/csp/chipc/Makefile
new file mode 100644
index 000000000000..673952768ee5
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/Makefile
@@ -0,0 +1 @@
+obj-y += chipcHw.o chipcHw_str.o chipcHw_reset.o chipcHw_init.o
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
new file mode 100644
index 000000000000..b3a61d860c65
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw.c
@@ -0,0 +1,776 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    chipcHw.c
+*
+*  @brief   Low level Various CHIP clock controlling routines
+*
+*  @note
+*
+*   These routines provide basic clock controlling functionality only.
+*/
+/****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/errno.h>
+#include <csp/stdint.h>
+#include <csp/module.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <csp/reg.h>
+#include <csp/delay.h>
+/* ---- Private Constants and Types --------------------------------------- */
+/* VPM alignment algorithm uses this */
+#define MAX_PHASE_ADJUST_COUNT         0xFFFF   /* Max number of times allowed to adjust the phase */
+#define MAX_PHASE_ALIGN_ATTEMPTS       10       /* Max number of attempt to align the phase */
+/* Local definition of clock type */
+#define PLL_CLOCK                      1        /* PLL Clock */
+#define NON_PLL_CLOCK                  2        /* Divider clock */
+static int chipcHw_divide(int num, int denom)
+    __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in hertz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
+    ) {
+        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
+        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
+        uint32_t dependentClockType = 0;
+        uint32_t vcoHz = 0;
+        /* Get VCO frequencies */
+        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+                uint64_t adjustFreq = 0;
+                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
+                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
+                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
+                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
+                vcoFreqPll1Hz += (uint32_t) adjustFreq;
+        } else {
+                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+        }
+        vcoFreqPll2Hz =
+            chipcHw_XTAL_FREQ_Hz *
+                 chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+        switch (clock) {
+        case chipcHw_CLOCK_DDR:
+                pPLLReg = &pChipcHw->DDRClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ARM:
+                pPLLReg = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW:
+                pPLLReg = &pChipcHw->ESWClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_VPM:
+                pPLLReg = &pChipcHw->VPMClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW125:
+                pPLLReg = &pChipcHw->ESW125Clock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_UART:
+                pPLLReg = &pChipcHw->UARTClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO0:
+                pPLLReg = &pChipcHw->SDIO0Clock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO1:
+                pPLLReg = &pChipcHw->SDIO1Clock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SPI:
+                pPLLReg = &pChipcHw->SPIClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ETM:
+                pPLLReg = &pChipcHw->ETMClock;
+                vcoHz = vcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_USB:
+                pPLLReg = &pChipcHw->USBClock;
+                vcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_LCD:
+                pPLLReg = &pChipcHw->LCDClock;
+                vcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_APM:
+                pPLLReg = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_BUS:
+                pClockCtrl = &pChipcHw->ACLKClock;
+                pDependentClock = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_OTP:
+                pClockCtrl = &pChipcHw->OTPClock;
+                break;
+        case chipcHw_CLOCK_I2C:
+                pClockCtrl = &pChipcHw->I2CClock;
+                break;
+        case chipcHw_CLOCK_I2S0:
+                pClockCtrl = &pChipcHw->I2S0Clock;
+                break;
+        case chipcHw_CLOCK_RTBUS:
+                pClockCtrl = &pChipcHw->RTBUSClock;
+                pDependentClock = &pChipcHw->ACLKClock;
+                dependentClockType = NON_PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_APM100:
+                pClockCtrl = &pChipcHw->APM100Clock;
+                pDependentClock = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_TSC:
+                pClockCtrl = &pChipcHw->TSCClock;
+                break;
+        case chipcHw_CLOCK_LED:
+                pClockCtrl = &pChipcHw->LEDClock;
+                break;
+        case chipcHw_CLOCK_I2S1:
+                pClockCtrl = &pChipcHw->I2S1Clock;
+                break;
+        }
+        if (pPLLReg) {
+                /* Obtain PLL clock frequency */
+                if (*pPLLReg & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                        /* Return crystal clock frequency when bypassed */
+                        return chipcHw_XTAL_FREQ_Hz;
+                } else if (clock == chipcHw_CLOCK_DDR) {
+                        /* DDR frequency is configured in PLLDivider register */
+                        return chipcHw_divide (vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                } else {
+                        /* From chip revision number B0, LCD clock is internally divided by 2 */
+                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
+                                vcoHz >>= 1;
+                        }
+                        /* Obtain PLL clock frequency using VCO dividers */
+                        return chipcHw_divide(vcoHz, ((*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*pPLLReg & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                }
+        } else if (pClockCtrl) {
+                /* Obtain divider clock frequency */
+                uint32_t div;
+                uint32_t freq = 0;
+                if (*pClockCtrl & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                        /* Return crystal clock frequency when bypassed */
+                        return chipcHw_XTAL_FREQ_Hz;
+                } else if (pDependentClock) {
+                        /* Identify the dependent clock frequency */
+                        switch (dependentClockType) {
+                        case PLL_CLOCK:
+                                if (*pDependentClock & chipcHw_REG_PLL_CLOCK_BYPASS_SELECT) {
+                                        /* Use crystal clock frequency when dependent PLL clock is bypassed */
+                                        freq = chipcHw_XTAL_FREQ_Hz;
+                                } else {
+                                        /* Obtain PLL clock frequency using VCO dividers */
+                                        div = *pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK;
+                                        freq = div ? chipcHw_divide(vcoHz, div) : 0;
+                                }
+                                break;
+                        case NON_PLL_CLOCK:
+                                if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                        freq = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
+                                } else {
+                                        if (*pDependentClock & chipcHw_REG_DIV_CLOCK_BYPASS_SELECT) {
+                                                /* Use crystal clock frequency when dependent divider clock is bypassed */
+                                                freq = chipcHw_XTAL_FREQ_Hz;
+                                        } else {
+                                                /* Obtain divider clock frequency using XTAL dividers */
+                                                div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                freq = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, (div ? div : 256));
+                                        }
+                                }
+                                break;
+                        }
+                } else {
+                        /* Dependent on crystal clock */
+                        freq = chipcHw_XTAL_FREQ_Hz;
+                }
+                div = *pClockCtrl & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                return chipcHw_divide(freq, (div ? div : 256));
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in Hz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
+                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
+    ) {
+        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        volatile uint32_t *pDependentClock = (uint32_t *) 0x0;
+        uint32_t vcoFreqPll1Hz = 0;     /* Effective VCO frequency for PLL1 in Hz */
+        uint32_t desVcoFreqPll1Hz = 0;  /* Desired VCO frequency for PLL1 in Hz */
+        uint32_t vcoFreqPll2Hz = 0;     /* Effective VCO frequency for PLL2 in Hz */
+        uint32_t dependentClockType = 0;
+        uint32_t vcoHz = 0;
+        uint32_t desVcoHz = 0;
+        /* Get VCO frequencies */
+        if ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) != chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+                uint64_t adjustFreq = 0;
+                vcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+                /* Adjusted frequency due to chipcHw_REG_PLL_DIVIDER_NDIV_f_SS */
+                adjustFreq = (uint64_t) chipcHw_XTAL_FREQ_Hz *
+                        (uint64_t) chipcHw_REG_PLL_DIVIDER_NDIV_f_SS *
+                        chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, (chipcHw_REG_PLL_PREDIVIDER_P2 * (uint64_t) chipcHw_REG_PLL_DIVIDER_FRAC));
+                vcoFreqPll1Hz += (uint32_t) adjustFreq;
+                /* Desired VCO frequency */
+                desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    (((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                      chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) + 1);
+        } else {
+                vcoFreqPll1Hz = desVcoFreqPll1Hz = chipcHw_XTAL_FREQ_Hz *
+                    chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+                    ((pChipcHw->PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+        }
+        vcoFreqPll2Hz = chipcHw_XTAL_FREQ_Hz * chipcHw_divide(chipcHw_REG_PLL_PREDIVIDER_P1, chipcHw_REG_PLL_PREDIVIDER_P2) *
+            ((pChipcHw->PLLPreDivider2 & chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK) >>
+             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT);
+        switch (clock) {
+        case chipcHw_CLOCK_DDR:
+                /* Configure the DDR_ctrl:BUS ratio settings */
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        /* Dvide DDR_phy by two to obtain DDR_ctrl clock */
+                        pChipcHw->DDRClock = (pChipcHw->DDRClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((((freq / 2) / chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
+                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+                pPLLReg = &pChipcHw->DDRClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ARM:
+                pPLLReg = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW:
+                pPLLReg = &pChipcHw->ESWClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_VPM:
+                /* Configure the VPM:BUS ratio settings */
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK) | ((chipcHw_divide (freq, chipcHw_getClockFrequency(chipcHw_CLOCK_BUS)) - 1)
+                                << chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT);
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+                pPLLReg = &pChipcHw->VPMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ESW125:
+                pPLLReg = &pChipcHw->ESW125Clock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_UART:
+                pPLLReg = &pChipcHw->UARTClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO0:
+                pPLLReg = &pChipcHw->SDIO0Clock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SDIO1:
+                pPLLReg = &pChipcHw->SDIO1Clock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_SPI:
+                pPLLReg = &pChipcHw->SPIClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_ETM:
+                pPLLReg = &pChipcHw->ETMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                break;
+        case chipcHw_CLOCK_USB:
+                pPLLReg = &pChipcHw->USBClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_LCD:
+                pPLLReg = &pChipcHw->LCDClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_APM:
+                pPLLReg = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                break;
+        case chipcHw_CLOCK_BUS:
+                pClockCtrl = &pChipcHw->ACLKClock;
+                pDependentClock = &pChipcHw->ARMClock;
+                vcoHz = vcoFreqPll1Hz;
+                desVcoHz = desVcoFreqPll1Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_OTP:
+                pClockCtrl = &pChipcHw->OTPClock;
+                break;
+        case chipcHw_CLOCK_I2C:
+                pClockCtrl = &pChipcHw->I2CClock;
+                break;
+        case chipcHw_CLOCK_I2S0:
+                pClockCtrl = &pChipcHw->I2S0Clock;
+                break;
+        case chipcHw_CLOCK_RTBUS:
+                pClockCtrl = &pChipcHw->RTBUSClock;
+                pDependentClock = &pChipcHw->ACLKClock;
+                dependentClockType = NON_PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_APM100:
+                pClockCtrl = &pChipcHw->APM100Clock;
+                pDependentClock = &pChipcHw->APMClock;
+                vcoHz = vcoFreqPll2Hz;
+                desVcoHz = vcoFreqPll2Hz;
+                dependentClockType = PLL_CLOCK;
+                break;
+        case chipcHw_CLOCK_TSC:
+                pClockCtrl = &pChipcHw->TSCClock;
+                break;
+        case chipcHw_CLOCK_LED:
+                pClockCtrl = &pChipcHw->LEDClock;
+                break;
+        case chipcHw_CLOCK_I2S1:
+                pClockCtrl = &pChipcHw->I2S1Clock;
+                break;
+        }
+        if (pPLLReg) {
+                /* Select XTAL as bypass source */
+                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_SOURCE_GPIO);
+                reg32_modify_or(pPLLReg, chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                /* For DDR settings use only the PLL divider clock */
+                if (pPLLReg == &pChipcHw->DDRClock) {
+                        /* Set M1DIV for PLL1, which controls the DDR clock */
+                        reg32_write(&pChipcHw->PLLDivider, (pChipcHw->PLLDivider & 0x00FFFFFF) | ((chipcHw_REG_PLL_DIVIDER_MDIV (desVcoHz, freq)) << 24));
+                        /* Calculate expected frequency */
+                        freq = chipcHw_divide(vcoHz, (((pChipcHw->PLLDivider & 0xFF000000) >> 24) ? ((pChipcHw->PLLDivider & 0xFF000000) >> 24) : 256));
+                } else {
+                        /* From chip revision number B0, LCD clock is internally divided by 2 */
+                        if ((pPLLReg == &pChipcHw->LCDClock) && (chipcHw_getChipRevisionNumber() != chipcHw_REV_NUMBER_A0)) {
+                                desVcoHz >>= 1;
+                                vcoHz >>= 1;
+                        }
+                        /* Set MDIV to change the frequency */
+                        reg32_modify_and(pPLLReg, ~(chipcHw_REG_PLL_CLOCK_MDIV_MASK));
+                        reg32_modify_or(pPLLReg, chipcHw_REG_PLL_DIVIDER_MDIV(desVcoHz, freq));
+                        /* Calculate expected frequency */
+                        freq = chipcHw_divide(vcoHz, ((*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) ? (*(pPLLReg) & chipcHw_REG_PLL_CLOCK_MDIV_MASK) : 256));
+                }
+                /* Wait for for atleast 200ns as per the protocol to change frequency */
+                udelay(1);
+                /* Do not bypass */
+                reg32_modify_and(pPLLReg, ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                /* Return the configured frequency */
+                return freq;
+        } else if (pClockCtrl) {
+                uint32_t divider = 0;
+                /* Divider clock should not be bypassed  */
+                reg32_modify_and(pClockCtrl,
+                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
+                /* Identify the clock source */
+                if (pDependentClock) {
+                        switch (dependentClockType) {
+                        case PLL_CLOCK:
+                                divider = chipcHw_divide(chipcHw_divide (desVcoHz, (*pDependentClock & chipcHw_REG_PLL_CLOCK_MDIV_MASK)), freq);
+                                break;
+                        case NON_PLL_CLOCK:
+                                {
+                                        uint32_t sourceClock = 0;
+                                        if (pDependentClock == (uint32_t *) &pChipcHw->ACLKClock) {
+                                                sourceClock = chipcHw_getClockFrequency (chipcHw_CLOCK_BUS);
+                                        } else {
+                                                uint32_t div = *pDependentClock & chipcHw_REG_DIV_CLOCK_DIV_MASK;
+                                                sourceClock = chipcHw_divide (chipcHw_XTAL_FREQ_Hz, ((div) ? div : 256));
+                                        }
+                                        divider = chipcHw_divide(sourceClock, freq);
+                                }
+                                break;
+                        }
+                } else {
+                        divider = chipcHw_divide(chipcHw_XTAL_FREQ_Hz, freq);
+                }
+                if (divider) {
+                        REG_LOCAL_IRQ_SAVE;
+                        /* Set the divider to obtain the required frequency */
+                        *pClockCtrl = (*pClockCtrl & (~chipcHw_REG_DIV_CLOCK_DIV_MASK)) | (((divider > 256) ? chipcHw_REG_DIV_CLOCK_DIV_256 : divider) & chipcHw_REG_DIV_CLOCK_DIV_MASK);
+                        REG_LOCAL_IRQ_RESTORE;
+                        return freq;
+                }
+        }
+        return 0;
+}
+EXPORT_SYMBOL(chipcHw_setClockFrequency);
+/****************************************************************************/
+/**
+*  @brief   Set VPM clock in sync with BUS clock for Chip Rev #A0
+*
+*  This function does the phase adjustment between VPM and BUS clock
+*
+*  @return >= 0 : On success (# of adjustment required)
+*            -1 : On failure
+*
+*/
+/****************************************************************************/
+static int vpmPhaseAlignA0(void)
+{
+        uint32_t phaseControl;
+        uint32_t phaseValue;
+        uint32_t prevPhaseComp;
+        int iter = 0;
+        int adjustCount = 0;
+        int count = 0;
+        for (iter = 0; (iter < MAX_PHASE_ALIGN_ATTEMPTS) && (adjustCount < MAX_PHASE_ADJUST_COUNT); iter++) {
+                phaseControl = (pChipcHw->VPMClock & chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT;
+                phaseValue = 0;
+                prevPhaseComp = 0;
+                /* Step 1: Look for falling PH_COMP transition */
+                /* Read the contents of VPM Clock resgister */
+                phaseValue = pChipcHw->VPMClock;
+                do {
+                        /* Store previous value of phase comparator */
+                        prevPhaseComp = phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP;
+                        /* Change the value of PH_CTRL. */
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        /* Read the contents of  VPM Clock resgister. */
+                        phaseValue = pChipcHw->VPMClock;
+                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
+                                phaseControl = (0x3F & (phaseControl - 1));
+                        } else {
+                                /* Increment to the Phase count value for next write, if Phase is not stable. */
+                                phaseControl = (0x3F & (phaseControl + 1));
+                        }
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || /* Look for a transition */
+                          ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) &&  /* Look for a falling edge */
+                         (adjustCount < MAX_PHASE_ADJUST_COUNT) /* Do not exceed the limit while trying */
+                    );
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+                /* Step 2: Keep moving forward to make sure falling PH_COMP transition was valid */
+                for (count = 0; (count < 5) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
+                        phaseControl = (0x3F & (phaseControl + 1));
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        phaseValue = pChipcHw->VPMClock;
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                }
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+                if (count != 5) {
+                        /* Detected false transition */
+                        continue;
+                }
+                /* Step 3: Keep moving backward to make sure falling PH_COMP transition was stable */
+                for (count = 0; (count < 3) && ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0); count++) {
+                        phaseControl = (0x3F & (phaseControl - 1));
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        phaseValue = pChipcHw->VPMClock;
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                }
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+                if (count != 3) {
+                        /* Detected noisy transition */
+                        continue;
+                }
+                /* Step 4: Keep moving backward before the original transition took place. */
+                for (count = 0; (count < 5); count++) {
+                        phaseControl = (0x3F & (phaseControl - 1));
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        phaseValue = pChipcHw->VPMClock;
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                }
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries */
+                        return -1;
+                }
+                if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0) {
+                        /* Detected false transition */
+                        continue;
+                }
+                /* Step 5: Re discover the valid transition */
+                do {
+                        /* Store previous value of phase comparator */
+                        prevPhaseComp = phaseValue;
+                        /* Change the value of PH_CTRL. */
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^=
+                            chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        /* Read the contents of  VPM Clock resgister. */
+                        phaseValue = pChipcHw->VPMClock;
+                        if ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) == 0x0) {
+                                phaseControl = (0x3F & (phaseControl - 1));
+                        } else {
+                                /* Increment to the Phase count value for next write, if Phase is not stable. */
+                                phaseControl = (0x3F & (phaseControl + 1));
+                        }
+                        /* Count number of adjustment made */
+                        adjustCount++;
+                } while (((prevPhaseComp == (phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP)) || ((phaseValue & chipcHw_REG_PLL_CLOCK_PHASE_COMP) != 0x0)) && (adjustCount < MAX_PHASE_ADJUST_COUNT));
+                if (adjustCount >= MAX_PHASE_ADJUST_COUNT) {
+                        /* Failed to align VPM phase after MAX_PHASE_ADJUST_COUNT tries  */
+                        return -1;
+                } else {
+                        /* Valid phase must have detected */
+                        break;
+                }
+        }
+        /* For VPM Phase should be perfectly aligned. */
+        phaseControl = (((pChipcHw->VPMClock >> chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT) - 1) & 0x3F);
+        {
+                REG_LOCAL_IRQ_SAVE;
+                pChipcHw->VPMClock = (pChipcHw->VPMClock & ~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT);
+                /* Load new phase value */
+                pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                REG_LOCAL_IRQ_RESTORE;
+        }
+        /* Return the status */
+        return (int)adjustCount;
+}
+/****************************************************************************/
+/**
+*  @brief   Set VPM clock in sync with BUS clock
+*
+*  This function does the phase adjustment between VPM and BUS clock
+*
+*  @return >= 0 : On success (# of adjustment required)
+*            -1 : On failure
+*
+*/
+/****************************************************************************/
+int chipcHw_vpmPhaseAlign(void)
+{
+        if (chipcHw_getChipRevisionNumber() == chipcHw_REV_NUMBER_A0) {
+                return vpmPhaseAlignA0();
+        } else {
+                uint32_t phaseControl = chipcHw_getVpmPhaseControl();
+                uint32_t phaseValue = 0;
+                int adjustCount = 0;
+                /* Disable VPM access */
+                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                /* Disable HW VPM phase alignment  */
+                chipcHw_vpmHwPhaseAlignDisable();
+                /* Enable SW VPM phase alignment  */
+                chipcHw_vpmSwPhaseAlignEnable();
+                /* Adjust VPM phase */
+                while (adjustCount < MAX_PHASE_ADJUST_COUNT) {
+                        phaseValue = chipcHw_getVpmHwPhaseAlignStatus();
+                        /* Adjust phase control value */
+                        if (phaseValue > 0xF) {
+                                /* Increment phase control value */
+                                phaseControl++;
+                        } else if (phaseValue < 0xF) {
+                                /* Decrement phase control value */
+                                phaseControl--;
+                        } else {
+                                /* Enable VPM access */
+                                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+                                /* Return adjust count */
+                                return adjustCount;
+                        }
+                        /* Change the value of PH_CTRL. */
+                        reg32_write(&pChipcHw->VPMClock, (pChipcHw->VPMClock & (~chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK)) | (phaseControl << chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT));
+                        /* Wait atleast 20 ns */
+                        udelay(1);
+                        /* Toggle the LOAD_CH after phase control is written. */
+                        pChipcHw->VPMClock ^= chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE;
+                        /* Count adjustment */
+                        adjustCount++;
+                }
+        }
+        /* Disable VPM access */
+        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE;
+        return -1;
+}
+/****************************************************************************/
+/**
+*  @brief   Local Divide function
+*
+*  This function does the divide
+*
+*  @return divide value
+*
+*/
+/****************************************************************************/
+static int chipcHw_divide(int num, int denom)
+{
+        int r;
+        int t = 1;
+        /* Shift denom and t up to the largest value to optimize algorithm */
+        /* t contains the units of each divide */
+        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
+                denom = denom << 1;
+                t = t << 1;
+        }
+        /* Intialize the result */
+        r = 0;
+        do {
+                /* Determine if there exists a positive remainder */
+                if ((num - denom) >= 0) {
+                        /* Accumlate t to the result and calculate a new remainder */
+                        num = num - denom;
+                        r = r + t;
+                }
+                /* Continue to shift denom and shift t down to 0 */
+                denom = denom >> 1;
+                t = t >> 1;
+        } while (t != 0);
+        return r;
+}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
new file mode 100644
index 000000000000..367df75d4bb3
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_init.c
@@ -0,0 +1,293 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    chipcHw_init.c
+*
+*  @brief   Low level CHIPC PLL configuration functions
+*
+*  @note
+*
+*   These routines provide basic PLL controlling functionality only.
+*/
+/****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/errno.h>
+#include <csp/stdint.h>
+#include <csp/module.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <csp/reg.h>
+#include <csp/delay.h>
+/* ---- Private Constants and Types --------------------------------------- */
+/*
+    Calculation for NDIV_i to obtain VCO frequency
+    -----------------------------------------------
+        Freq_vco = Freq_ref * (P2 / P1) * (PLL_NDIV_i + PLL_NDIV_f)
+        for Freq_vco = VCO_FREQ_MHz
+                Freq_ref = chipcHw_XTAL_FREQ_Hz
+                PLL_P1 = PLL_P2 = 1
+                and
+                PLL_NDIV_f = 0
+        We get:
+                PLL_NDIV_i = Freq_vco / Freq_ref = VCO_FREQ_MHz / chipcHw_XTAL_FREQ_Hz
+    Calculation for PLL MDIV to obtain frequency Freq_x for channel x
+    -----------------------------------------------------------------
+                Freq_x = chipcHw_XTAL_FREQ_Hz * PLL_NDIV_i / PLL_MDIV_x = VCO_FREQ_MHz / PLL_MDIV_x
+                PLL_MDIV_x = VCO_FREQ_MHz / Freq_x
+*/
+/* ---- Private Variables ------------------------------------------------- */
+/****************************************************************************/
+/**
+*  @brief  Initializes the PLL2
+*
+*  This function initializes the PLL2
+*
+*/
+/****************************************************************************/
+void chipcHw_pll2Enable(uint32_t vcoFreqHz)
+{
+        uint32_t pllPreDivider2 = 0;
+        {
+                REG_LOCAL_IRQ_SAVE;
+                pChipcHw->PLLConfig2 =
+                    chipcHw_REG_PLL_CONFIG_D_RESET |
+                    chipcHw_REG_PLL_CONFIG_A_RESET;
+                pllPreDivider2 = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
+                    chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
+                    (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
+                     chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
+                    (chipcHw_REG_PLL_PREDIVIDER_P1 <<
+                     chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
+                    (chipcHw_REG_PLL_PREDIVIDER_P2 <<
+                     chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
+                /* Enable CHIPC registers to control the PLL */
+                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+                /* Set pre divider to get desired VCO frequency */
+                pChipcHw->PLLPreDivider2 = pllPreDivider2;
+                /* Set NDIV Frac */
+                pChipcHw->PLLDivider2 = chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                /* This has to be removed once the default values are fixed for PLL2. */
+                pChipcHw->PLLControl12 = 0x38000700;
+                pChipcHw->PLLControl22 = 0x00000015;
+                /* Reset PLL2 */
+                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
+                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                } else {
+                        pChipcHw->PLLConfig2 = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                }
+                REG_LOCAL_IRQ_RESTORE;
+        }
+        /* Insert certain amount of delay before deasserting ARESET. */
+        udelay(1);
+        {
+                REG_LOCAL_IRQ_SAVE;
+                /* Remove analog reset and Power on the PLL */
+                pChipcHw->PLLConfig2 &=
+                    ~(chipcHw_REG_PLL_CONFIG_A_RESET |
+                      chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                REG_LOCAL_IRQ_RESTORE;
+        }
+        /* Wait until PLL is locked */
+        while (!(pChipcHw->PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+                ;
+        {
+                REG_LOCAL_IRQ_SAVE;
+                /* Remove digital reset */
+                pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+EXPORT_SYMBOL(chipcHw_pll2Enable);
+/****************************************************************************/
+/**
+*  @brief  Initializes the PLL1
+*
+*  This function initializes the PLL1
+*
+*/
+/****************************************************************************/
+void chipcHw_pll1Enable(uint32_t vcoFreqHz, chipcHw_SPREAD_SPECTRUM_e ssSupport)
+{
+        uint32_t pllPreDivider = 0;
+        {
+                REG_LOCAL_IRQ_SAVE;
+                pChipcHw->PLLConfig =
+                    chipcHw_REG_PLL_CONFIG_D_RESET |
+                    chipcHw_REG_PLL_CONFIG_A_RESET;
+                /* Setting VCO frequency */
+                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
+                        pllPreDivider =
+                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8 |
+                            ((chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) -
+                              1) << chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
+                } else {
+                        pllPreDivider = chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN |
+                            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER |
+                            (chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vcoFreqHz) <<
+                             chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P1 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT) |
+                            (chipcHw_REG_PLL_PREDIVIDER_P2 <<
+                             chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT);
+                }
+                /* Enable CHIPC registers to control the PLL */
+                pChipcHw->PLLStatus |= chipcHw_REG_PLL_STATUS_CONTROL_ENABLE;
+                /* Set pre divider to get desired VCO frequency */
+                pChipcHw->PLLPreDivider = pllPreDivider;
+                /* Set NDIV Frac */
+                if (ssSupport == chipcHw_SPREAD_SPECTRUM_ALLOW) {
+                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
+                            chipcHw_REG_PLL_DIVIDER_NDIV_f_SS;
+                } else {
+                        pChipcHw->PLLDivider = chipcHw_REG_PLL_DIVIDER_M1DIV |
+                            chipcHw_REG_PLL_DIVIDER_NDIV_f;
+                }
+                /* Reset PLL1 */
+                if (vcoFreqHz > chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ) {
+                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_1601_3200 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                } else {
+                        pChipcHw->PLLConfig = chipcHw_REG_PLL_CONFIG_D_RESET |
+                            chipcHw_REG_PLL_CONFIG_A_RESET |
+                            chipcHw_REG_PLL_CONFIG_VCO_800_1600 |
+                            chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+                }
+                REG_LOCAL_IRQ_RESTORE;
+                /* Insert certain amount of delay before deasserting ARESET. */
+                udelay(1);
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        /* Remove analog reset and Power on the PLL */
+                        pChipcHw->PLLConfig &=
+                            ~(chipcHw_REG_PLL_CONFIG_A_RESET |
+                              chipcHw_REG_PLL_CONFIG_POWER_DOWN);
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+                /* Wait until PLL is locked */
+                while (!(pChipcHw->PLLStatus & chipcHw_REG_PLL_STATUS_LOCKED)
+                       || !(pChipcHw->
+                            PLLStatus2 & chipcHw_REG_PLL_STATUS_LOCKED))
+                        ;
+                /* Remove digital reset */
+                {
+                        REG_LOCAL_IRQ_SAVE;
+                        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_D_RESET;
+                        REG_LOCAL_IRQ_RESTORE;
+                }
+        }
+}
+EXPORT_SYMBOL(chipcHw_pll1Enable);
+/****************************************************************************/
+/**
+*  @brief  Initializes the chipc module
+*
+*  This function initializes the PLLs and core system clocks
+*
+*/
+/****************************************************************************/
+void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
+    ) {
+#if !(defined(__KERNEL__) && !defined(STANDALONE))
+        delay_init();
+#endif
+        /* Do not program PLL, when warm reset */
+        if (!(chipcHw_getStickyBits() & chipcHw_REG_STICKY_CHIP_WARM_RESET)) {
+                chipcHw_pll1Enable(initParam->pllVcoFreqHz,
+                                   initParam->ssSupport);
+                chipcHw_pll2Enable(initParam->pll2VcoFreqHz);
+        } else {
+                /* Clear sticky bits */
+                chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_WARM_RESET);
+        }
+        /* Clear sticky bits */
+        chipcHw_clearStickyBits(chipcHw_REG_STICKY_CHIP_SOFT_RESET);
+        /* Before configuring the ARM clock, atleast we need to make sure BUS clock maintains the proper ratio with ARM clock */
+        pChipcHw->ACLKClock =
+            (pChipcHw->
+             ACLKClock & ~chipcHw_REG_ACLKClock_CLK_DIV_MASK) | (initParam->
+                                                                 armBusRatio &
+                                                                 chipcHw_REG_ACLKClock_CLK_DIV_MASK);
+        /* Set various core component frequencies. The order in which this is done is important for some. */
+        /* The RTBUS (DDR PHY) is derived from the BUS, and the BUS from the ARM, and VPM needs to know BUS */
+        /* frequency to find its ratio with the BUS.  Hence we must set the ARM first, followed by the BUS,  */
+        /* then VPM and RTBUS. */
+        chipcHw_setClockFrequency(chipcHw_CLOCK_ARM,
+                                  initParam->busClockFreqHz *
+                                  initParam->armBusRatio);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_BUS, initParam->busClockFreqHz);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_VPM,
+                                  initParam->busClockFreqHz *
+                                  initParam->vpmBusRatio);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_DDR,
+                                  initParam->busClockFreqHz *
+                                  initParam->ddrBusRatio);
+        chipcHw_setClockFrequency(chipcHw_CLOCK_RTBUS,
+                                  initParam->busClockFreqHz / 2);
+}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
new file mode 100644
index 000000000000..2671d8896bbb
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_reset.c
@@ -0,0 +1,124 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+#include <mach/csp/chipcHw_def.h>
+#include <mach/csp/chipcHw_inline.h>
+#include <csp/intcHw.h>
+#include <csp/cache.h>
+/* ---- Private Constants and Types --------------------------------------- */
+/* ---- Private Variables ------------------------------------------------- */
+void chipcHw_reset_run_from_aram(void);
+typedef void (*RUNFUNC) (void);
+/****************************************************************************/
+/**
+*  @brief   warmReset
+*
+*  @note warmReset configures the clocks which are not reset back to the state
+*   required to execute on reset.  To do so we need to copy the code into internal
+*   memory to change the ARM clock while we are not executing from DDR.
+*/
+/****************************************************************************/
+void chipcHw_reset(uint32_t mask)
+{
+        int i = 0;
+        RUNFUNC runFunc = (RUNFUNC) (unsigned long)MM_ADDR_IO_ARAM;
+        /* Disable all interrupts */
+        intcHw_irq_disable(INTCHW_INTC0, 0xffffffff);
+        intcHw_irq_disable(INTCHW_INTC1, 0xffffffff);
+        intcHw_irq_disable(INTCHW_SINTC, 0xffffffff);
+        {
+                REG_LOCAL_IRQ_SAVE;
+                if (mask & chipcHw_REG_SOFT_RESET_CHIP_SOFT) {
+                        chipcHw_softReset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+                }
+                /* Bypass the PLL clocks before reboot */
+                pChipcHw->UARTClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+                pChipcHw->SPIClock |= chipcHw_REG_PLL_CLOCK_BYPASS_SELECT;
+                /* Copy the chipcHw_warmReset_run_from_aram function into ARAM */
+                do {
+                        ((uint32_t *) MM_IO_BASE_ARAM)[i] =
+                            ((uint32_t *) &chipcHw_reset_run_from_aram)[i];
+                        i++;
+                } while (((uint32_t *) MM_IO_BASE_ARAM)[i - 1] != 0xe1a0f00f);  /* 0xe1a0f00f == asm ("mov r15, r15"); */
+                CSP_CACHE_FLUSH_ALL;
+                /* run the function from ARAM */
+                runFunc();
+                /* Code will never get here, but include it to balance REG_LOCAL_IRQ_SAVE above */
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+/* This function must run from internal memory */
+void chipcHw_reset_run_from_aram(void)
+{
+/* Make sure, pipeline is filled with instructions coming from ARAM */
+__asm (" nop                                                            \n\t"
+                " nop                                                            \n\t"
+#if defined(__KERNEL__) && !defined(STANDALONE)
+                " MRC      p15,#0x0,r0,c1,c0,#0                                  \n\t"
+                " BIC      r0,r0,#0xd                                            \n\t"
+                " MCR      p15,#0x0,r0,c1,c0,#0                                  \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+#endif
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+/* Bypass the ARM clock and switch to XTAL clock */
+                " MOV      r2,#0x80000000                                        \n\t"
+                " LDR      r3,[r2,#8]                                            \n\t"
+                " ORR      r3,r3,#0x20000                                        \n\t"
+                " STR      r3,[r2,#8]                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+                " nop                                                            \n\t"
+/* Issue reset */
+                " MOV      r3,#0x2                                               \n\t"
+                " STR      r3,[r2,#0x80]                                         \n\t"
+/* End here */
+                " MOV      pc,pc                                                 \n\t");
+/* 0xe1a0f00f ==  asm ("mov r15, r15"); */
+}
diff --git a/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
new file mode 100644
index 000000000000..54ad964fe94c
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/chipc/chipcHw_str.c
@@ -0,0 +1,64 @@
+/*****************************************************************************
+* Copyright 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    chipcHw_str.c
+*
+*  @brief   Contains strings which are useful to linux and csp
+*
+*  @note
+*/
+/****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/csp/chipcHw_inline.h>
+/* ---- Private Constants and Types --------------------------------------- */
+static const char *gMuxStr[] = {
+        "GPIO",                 /* 0 */
+        "KeyPad",               /* 1 */
+        "I2C-Host",             /* 2 */
+        "SPI",                  /* 3 */
+        "Uart",                 /* 4 */
+        "LED-Mtx-P",            /* 5 */
+        "LED-Mtx-S",            /* 6 */
+        "SDIO-0",               /* 7 */
+        "SDIO-1",               /* 8 */
+        "PCM",                  /* 9 */
+        "I2S",                  /* 10 */
+        "ETM",                  /* 11 */
+        "Debug",                /* 12 */
+        "Misc",                 /* 13 */
+        "0xE",                  /* 14 */
+        "0xF",                  /* 15 */
+};
+/****************************************************************************/
+/**
+*  @brief   Retrieves a string representation of the mux setting for a pin.
+*
+*  @return  Pointer to a character string.
+*/
+/****************************************************************************/
+const char *chipcHw_getGpioPinFunctionStr(int pin)
+{
+        if ((pin < 0) || (pin >= chipcHw_GPIO_COUNT)) {
+                return "";
+        }
+        return gMuxStr[chipcHw_getGpioPinFunction(pin)];
+}
diff --git a/arch/arm/mach-bcmring/csp/dmac/Makefile b/arch/arm/mach-bcmring/csp/dmac/Makefile
new file mode 100644
index 000000000000..fb1104fe56b2
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/Makefile
@@ -0,0 +1 @@
+obj-y += dmacHw.o dmacHw_extra.o
+\ No newline at end of file
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
new file mode 100644
index 000000000000..7b9bac2d79a5
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw.c
@@ -0,0 +1,917 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    dmacHw.c
+*
+*  @brief   Low level DMA controller driver routines
+*
+*  @note
+*
+*   These routines provide basic DMA functionality only.
+*/
+/****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+#include <csp/string.h>
+#include <stddef.h>
+#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw_reg.h>
+#include <mach/csp/dmacHw_priv.h>
+#include <mach/csp/chipcHw_inline.h>
+/* ---- External Function Prototypes ------------------------------------- */
+/* Allocate DMA control blocks */
+dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];
+uint32_t dmaChannelCount_0 = dmacHw_MAX_CHANNEL_COUNT / 2;
+uint32_t dmaChannelCount_1 = dmacHw_MAX_CHANNEL_COUNT / 2;
+/****************************************************************************/
+/**
+*  @brief   Get maximum FIFO for a DMA channel
+*
+*  @return  Maximum allowable FIFO size
+*
+*
+*/
+/****************************************************************************/
+static uint32_t GetFifoSize(dmacHw_HANDLE_t handle      /*   [ IN ] DMA Channel handle */
+    ) {
+        uint32_t val = 0;
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_MISC_t *pMiscReg =
+            (dmacHw_MISC_t *) dmacHw_REG_MISC_BASE(pCblk->module);
+        switch (pCblk->channel) {
+        case 0:
+                val = (pMiscReg->CompParm2.lo & 0x70000000) >> 28;
+                break;
+        case 1:
+                val = (pMiscReg->CompParm3.hi & 0x70000000) >> 28;
+                break;
+        case 2:
+                val = (pMiscReg->CompParm3.lo & 0x70000000) >> 28;
+                break;
+        case 3:
+                val = (pMiscReg->CompParm4.hi & 0x70000000) >> 28;
+                break;
+        case 4:
+                val = (pMiscReg->CompParm4.lo & 0x70000000) >> 28;
+                break;
+        case 5:
+                val = (pMiscReg->CompParm5.hi & 0x70000000) >> 28;
+                break;
+        case 6:
+                val = (pMiscReg->CompParm5.lo & 0x70000000) >> 28;
+                break;
+        case 7:
+                val = (pMiscReg->CompParm6.hi & 0x70000000) >> 28;
+                break;
+        }
+        if (val <= 0x4) {
+                return 8 << val;
+        } else {
+                dmacHw_ASSERT(0);
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Program channel register to initiate transfer
+*
+*  @return  void
+*
+*
+*  @note
+*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
+*     - This function should also be called from ISR to program the channel with
+*       pending descriptors
+*/
+/****************************************************************************/
+void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
+                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                             void *pDescriptor  /*   [ IN ] Descriptor buffer */
+    ) {
+        dmacHw_DESC_RING_t *pRing;
+        dmacHw_DESC_t *pProg;
+        dmacHw_CBLK_t *pCblk;
+        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
+                /* Not safe yet to program the channel */
+                return;
+        }
+        if (pCblk->varDataStarted) {
+                if (pCblk->descUpdated) {
+                        pCblk->descUpdated = 0;
+                        pProg =
+                            (dmacHw_DESC_t *) ((uint32_t)
+                                               dmacHw_REG_LLP(pCblk->module,
+                                                              pCblk->channel) +
+                                               pRing->virt2PhyOffset);
+                        /* Load descriptor if not loaded */
+                        if (!(pProg->ctl.hi & dmacHw_REG_CTL_DONE)) {
+                                dmacHw_SET_SAR(pCblk->module, pCblk->channel,
+                                               pProg->sar);
+                                dmacHw_SET_DAR(pCblk->module, pCblk->channel,
+                                               pProg->dar);
+                                dmacHw_REG_CTL_LO(pCblk->module,
+                                                  pCblk->channel) =
+                                    pProg->ctl.lo;
+                                dmacHw_REG_CTL_HI(pCblk->module,
+                                                  pCblk->channel) =
+                                    pProg->ctl.hi;
+                        } else if (pProg == (dmacHw_DESC_t *) pRing->pEnd->llp) {
+                                /* Return as end descriptor is processed */
+                                return;
+                        } else {
+                                dmacHw_ASSERT(0);
+                        }
+                } else {
+                        return;
+                }
+        } else {
+                if (pConfig->transferMode == dmacHw_TRANSFER_MODE_PERIODIC) {
+                        /* Do not make a single chain, rather process one descriptor at a time */
+                        pProg = pRing->pHead;
+                        /* Point to the next descriptor for next iteration */
+                        dmacHw_NEXT_DESC(pRing, pHead);
+                } else {
+                        /* Return if no more pending descriptor */
+                        if (pRing->pEnd == NULL) {
+                                return;
+                        }
+                        pProg = pRing->pProg;
+                        if (pConfig->transferMode ==
+                            dmacHw_TRANSFER_MODE_CONTINUOUS) {
+                                /* Make sure a complete ring can be formed */
+                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pEnd->
+                                              llp == pRing->pProg);
+                                /* Make sure pProg pointing to the pHead */
+                                dmacHw_ASSERT((dmacHw_DESC_t *) pRing->pProg ==
+                                              pRing->pHead);
+                                /* Make a complete ring */
+                                do {
+                                        pRing->pProg->ctl.lo |=
+                                            (dmacHw_REG_CTL_LLP_DST_EN |
+                                             dmacHw_REG_CTL_LLP_SRC_EN);
+                                        pRing->pProg =
+                                            (dmacHw_DESC_t *) pRing->pProg->llp;
+                                } while (pRing->pProg != pRing->pHead);
+                        } else {
+                                /* Make a single long chain */
+                                while (pRing->pProg != pRing->pEnd) {
+                                        pRing->pProg->ctl.lo |=
+                                            (dmacHw_REG_CTL_LLP_DST_EN |
+                                             dmacHw_REG_CTL_LLP_SRC_EN);
+                                        pRing->pProg =
+                                            (dmacHw_DESC_t *) pRing->pProg->llp;
+                                }
+                        }
+                }
+                /* Program the channel registers */
+                dmacHw_SET_SAR(pCblk->module, pCblk->channel, pProg->sar);
+                dmacHw_SET_DAR(pCblk->module, pCblk->channel, pProg->dar);
+                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
+                               (uint32_t) pProg - pRing->virt2PhyOffset);
+                dmacHw_REG_CTL_LO(pCblk->module, pCblk->channel) =
+                    pProg->ctl.lo;
+                dmacHw_REG_CTL_HI(pCblk->module, pCblk->channel) =
+                    pProg->ctl.hi;
+                if (pRing->pEnd) {
+                        /* Remember the descriptor to use next */
+                        pRing->pProg = (dmacHw_DESC_t *) pRing->pEnd->llp;
+                }
+                /* Indicate no more pending descriptor  */
+                pRing->pEnd = (dmacHw_DESC_t *) NULL;
+        }
+        /* Start DMA operation */
+        dmacHw_DMA_START(pCblk->module, pCblk->channel);
+}
+/****************************************************************************/
+/**
+*  @brief   Initializes DMA
+*
+*  This function initializes DMA CSP driver
+*
+*  @note
+*     Must be called before using any DMA channel
+*/
+/****************************************************************************/
+void dmacHw_initDma(void)
+{
+        uint32_t i = 0;
+        dmaChannelCount_0 = dmacHw_GET_NUM_CHANNEL(0);
+        dmaChannelCount_1 = dmacHw_GET_NUM_CHANNEL(1);
+        /* Enable access to the DMA block */
+        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC0);
+        chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_DMAC1);
+        if ((dmaChannelCount_0 + dmaChannelCount_1) > dmacHw_MAX_CHANNEL_COUNT) {
+                dmacHw_ASSERT(0);
+        }
+        memset((void *)dmacHw_gCblk, 0,
+               sizeof(dmacHw_CBLK_t) * (dmaChannelCount_0 + dmaChannelCount_1));
+        for (i = 0; i < dmaChannelCount_0; i++) {
+                dmacHw_gCblk[i].module = 0;
+                dmacHw_gCblk[i].channel = i;
+        }
+        for (i = 0; i < dmaChannelCount_1; i++) {
+                dmacHw_gCblk[i + dmaChannelCount_0].module = 1;
+                dmacHw_gCblk[i + dmaChannelCount_0].channel = i;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Exit function for  DMA
+*
+*  This function isolates DMA from the system
+*
+*/
+/****************************************************************************/
+void dmacHw_exitDma(void)
+{
+        /* Disable access to the DMA block */
+        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC0);
+        chipcHw_busInterfaceClockDisable(chipcHw_REG_BUS_CLOCK_DMAC1);
+}
+/****************************************************************************/
+/**
+*  @brief   Gets a handle to a DMA channel
+*
+*  This function returns a handle, representing a control block of a particular DMA channel
+*
+*  @return  -1       - On Failure
+*            handle  - On Success, representing a channel control block
+*
+*  @note
+*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
+    ) {
+        int idx;
+        switch ((channelId >> 8)) {
+        case 0:
+                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_0);
+                idx = (channelId & 0xff);
+                break;
+        case 1:
+                dmacHw_ASSERT((channelId & 0xff) < dmaChannelCount_1);
+                idx = dmaChannelCount_0 + (channelId & 0xff);
+                break;
+        default:
+                dmacHw_ASSERT(0);
+                return (dmacHw_HANDLE_t) -1;
+        }
+        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[idx]);
+}
+/****************************************************************************/
+/**
+*  @brief   Initializes a DMA channel for use
+*
+*  This function initializes and resets a DMA channel for use
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*   [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        int module = pCblk->module;
+        int channel = pCblk->channel;
+        /* Reinitialize the control block */
+        memset((void *)pCblk, 0, sizeof(dmacHw_CBLK_t));
+        pCblk->module = module;
+        pCblk->channel = channel;
+        /* Enable DMA controller */
+        dmacHw_DMA_ENABLE(pCblk->module);
+        /* Reset DMA channel */
+        dmacHw_RESET_CONTROL_LO(pCblk->module, pCblk->channel);
+        dmacHw_RESET_CONTROL_HI(pCblk->module, pCblk->channel);
+        dmacHw_RESET_CONFIG_LO(pCblk->module, pCblk->channel);
+        dmacHw_RESET_CONFIG_HI(pCblk->module, pCblk->channel);
+        /* Clear all raw interrupt status */
+        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
+        /* Mask event specific interrupts */
+        dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_STRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_DTRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief  Finds amount of memory required to form a descriptor ring
+*
+*
+*  @return   Number of bytes required to form a descriptor ring
+*
+*
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorLen(uint32_t descCnt  /* [ IN ] Number of descriptor in the ring */
+    ) {
+        /* Need extra 4 byte to ensure 32 bit alignment  */
+        return (descCnt * sizeof(dmacHw_DESC_t)) + sizeof(dmacHw_DESC_RING_t) +
+                sizeof(uint32_t);
+}
+/****************************************************************************/
+/**
+*  @brief   Initializes descriptor ring
+*
+*  This function will initializes the descriptor ring of a DMA channel
+*
+*
+*  @return   -1 - On failure
+*             0 - On success
+*  @note
+*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
+*     - Descriptor buffer MUST be 32 bit aligned and uncached as it is
+*       accessed by ARM and DMA
+*/
+/****************************************************************************/
+int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
+                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
+                          uint32_t len, /*  [ IN ] Size of the pBuf */
+                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
+    ) {
+        uint32_t i;
+        dmacHw_DESC_RING_t *pRing;
+        dmacHw_DESC_t *pDesc;
+        /* Check the alignment of the descriptor */
+        if ((uint32_t) pDescriptorVirt & 0x00000003) {
+                dmacHw_ASSERT(0);
+                return -1;
+        }
+        /* Check if enough space has been allocated for descriptor ring */
+        if (len < dmacHw_descriptorLen(num)) {
+                return -1;
+        }
+        pRing = dmacHw_GET_DESC_RING(pDescriptorVirt);
+        pRing->pHead =
+            (dmacHw_DESC_t *) ((uint32_t) pRing + sizeof(dmacHw_DESC_RING_t));
+        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
+        pRing->pProg = dmacHw_DESC_INIT;
+        /* Initialize link item chain, starting from the head */
+        pDesc = pRing->pHead;
+        /* Find the offset between virtual to physical address */
+        pRing->virt2PhyOffset = (uint32_t) pDescriptorVirt - descriptorPhyAddr;
+        /* Form the descriptor ring */
+        for (i = 0; i < num - 1; i++) {
+                /* Clear link list item */
+                memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
+                /* Point to the next item in the physical address */
+                pDesc->llpPhy = (uint32_t) (pDesc + 1) - pRing->virt2PhyOffset;
+                /* Point to the next item in the virtual address */
+                pDesc->llp = (uint32_t) (pDesc + 1);
+                /* Mark descriptor is ready to use */
+                pDesc->ctl.hi = dmacHw_DESC_FREE;
+                /* Look into next link list item */
+                pDesc++;
+        }
+        /* Clear last link list item */
+        memset((void *)pDesc, 0, sizeof(dmacHw_DESC_t));
+        /* Last item pointing to the first item in the
+           physical address to complete the ring */
+        pDesc->llpPhy = (uint32_t) pRing->pHead - pRing->virt2PhyOffset;
+        /* Last item pointing to the first item in the
+           virtual address to complete the ring
+         */
+        pDesc->llp = (uint32_t) pRing->pHead;
+        /* Mark descriptor is ready to use */
+        pDesc->ctl.hi = dmacHw_DESC_FREE;
+        /* Set the number of descriptors in the ring */
+        pRing->num = num;
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Configure DMA channel
+*
+*  @return  0  : On success
+*           -1 : On failure
+*/
+/****************************************************************************/
+int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*   [ IN ] DMA Channel handle */
+                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        uint32_t cfgHigh = 0;
+        int srcTrSize;
+        int dstTrSize;
+        pCblk->varDataStarted = 0;
+        pCblk->userData = NULL;
+        /* Configure
+           - Burst transaction when enough data in available in FIFO
+           - AHB Access protection 1
+           - Source and destination peripheral ports
+         */
+        cfgHigh =
+            dmacHw_REG_CFG_HI_FIFO_ENOUGH | dmacHw_REG_CFG_HI_AHB_HPROT_1 |
+            dmacHw_SRC_PERI_INTF(pConfig->
+                                 srcPeripheralPort) |
+            dmacHw_DST_PERI_INTF(pConfig->dstPeripheralPort);
+        /* Set priority */
+        dmacHw_SET_CHANNEL_PRIORITY(pCblk->module, pCblk->channel,
+                                    pConfig->channelPriority);
+        if (pConfig->dstStatusRegisterAddress != 0) {
+                /* Destination status update enable */
+                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_DST_STAT;
+                /* Configure status registers */
+                dmacHw_SET_DSTATAR(pCblk->module, pCblk->channel,
+                                   pConfig->dstStatusRegisterAddress);
+        }
+        if (pConfig->srcStatusRegisterAddress != 0) {
+                /* Source status update enable */
+                cfgHigh |= dmacHw_REG_CFG_HI_UPDATE_SRC_STAT;
+                /* Source status update enable */
+                dmacHw_SET_SSTATAR(pCblk->module, pCblk->channel,
+                                   pConfig->srcStatusRegisterAddress);
+        }
+        /* Configure the config high register */
+        dmacHw_GET_CONFIG_HI(pCblk->module, pCblk->channel) = cfgHigh;
+        /* Clear all raw interrupt status */
+        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
+        /* Configure block interrupt */
+        if (pConfig->blockTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
+                dmacHw_BLOCK_INT_ENABLE(pCblk->module, pCblk->channel);
+        } else {
+                dmacHw_BLOCK_INT_DISABLE(pCblk->module, pCblk->channel);
+        }
+        /* Configure complete transfer interrupt */
+        if (pConfig->completeTransferInterrupt == dmacHw_INTERRUPT_ENABLE) {
+                dmacHw_TRAN_INT_ENABLE(pCblk->module, pCblk->channel);
+        } else {
+                dmacHw_TRAN_INT_DISABLE(pCblk->module, pCblk->channel);
+        }
+        /* Configure error interrupt */
+        if (pConfig->errorInterrupt == dmacHw_INTERRUPT_ENABLE) {
+                dmacHw_ERROR_INT_ENABLE(pCblk->module, pCblk->channel);
+        } else {
+                dmacHw_ERROR_INT_DISABLE(pCblk->module, pCblk->channel);
+        }
+        /* Configure gather register */
+        if (pConfig->srcGatherWidth) {
+                srcTrSize =
+                    dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+                if (!
+                    ((pConfig->srcGatherWidth % srcTrSize)
+                     && (pConfig->srcGatherJump % srcTrSize))) {
+                        dmacHw_REG_SGR_LO(pCblk->module, pCblk->channel) =
+                            ((pConfig->srcGatherWidth /
+                              srcTrSize) << 20) | (pConfig->srcGatherJump /
+                                                   srcTrSize);
+                } else {
+                        return -1;
+                }
+        }
+        /* Configure scatter register */
+        if (pConfig->dstScatterWidth) {
+                dstTrSize =
+                    dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
+                if (!
+                    ((pConfig->dstScatterWidth % dstTrSize)
+                     && (pConfig->dstScatterJump % dstTrSize))) {
+                        dmacHw_REG_DSR_LO(pCblk->module, pCblk->channel) =
+                            ((pConfig->dstScatterWidth /
+                              dstTrSize) << 20) | (pConfig->dstScatterJump /
+                                                   dstTrSize);
+                } else {
+                        return -1;
+                }
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Indicates whether DMA transfer is in progress or completed
+*
+*  @return   DMA transfer status
+*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
+*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
+*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
+*
+*/
+/****************************************************************************/
+dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        if (CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
+                return dmacHw_TRANSFER_STATUS_BUSY;
+        } else if (dmacHw_REG_INT_RAW_ERROR(pCblk->module) &
+                   (0x00000001 << pCblk->channel)) {
+                return dmacHw_TRANSFER_STATUS_ERROR;
+        }
+        return dmacHw_TRANSFER_STATUS_DONE;
+}
+/****************************************************************************/
+/**
+*  @brief   Set descriptors for known data length
+*
+*  When DMA has to work as a flow controller, this function prepares the
+*  descriptor chain to transfer data
+*
+*  from:
+*          - Memory to memory
+*          - Peripheral to memory
+*          - Memory to Peripheral
+*          - Peripheral to Peripheral
+*
+*  @return   -1 - On failure
+*             0 - On success
+*
+*/
+/****************************************************************************/
+int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                             void *pDescriptor, /*   [ IN ] Descriptor buffer */
+                             void *pSrcAddr,    /*   [ IN ] Source (Peripheral/Memory) address */
+                             void *pDstAddr,    /*   [ IN ] Destination (Peripheral/Memory) address */
+                             size_t dataLen     /*   [ IN ] Data length in bytes */
+    ) {
+        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
+        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        dmacHw_DESC_t *pStart;
+        dmacHw_DESC_t *pProg;
+        int srcTs = 0;
+        int blkTs = 0;
+        int oddSize = 0;
+        int descCount = 0;
+        int count = 0;
+        int dstTrSize = 0;
+        int srcTrSize = 0;
+        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
+        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
+        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+        /* Skip Tx if buffer is NULL  or length is unknown */
+        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
+                /* Do not initiate transfer */
+                return -1;
+        }
+        /* Ensure scatter and gather are transaction aligned */
+        if ((pConfig->srcGatherWidth % srcTrSize)
+            || (pConfig->dstScatterWidth % dstTrSize)) {
+                return -2;
+        }
+        /*
+           Background 1: DMAC can not perform DMA if source and destination addresses are
+           not properly aligned with the channel's transaction width. So, for successful
+           DMA transfer, transaction width must be set according to the alignment of the
+           source and destination address.
+         */
+        /* Adjust destination transaction width if destination address is not aligned properly */
+        dstTrWidth = pConfig->dstMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
+                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
+                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
+        }
+        /* Adjust source transaction width if source address is not aligned properly */
+        srcTrWidth = pConfig->srcMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
+                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
+                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
+        }
+        /* Find the maximum transaction per descriptor */
+        if (pConfig->maxDataPerBlock
+            && ((pConfig->maxDataPerBlock / srcTrSize) <
+                dmacHw_MAX_BLOCKSIZE)) {
+                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
+        }
+        /* Find number of source transactions needed to complete the DMA transfer */
+        srcTs = dataLen / srcTrSize;
+        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
+        if (srcTs && (dstTrSize > srcTrSize)) {
+                oddSize = dataLen % dstTrSize;
+                /* Adjust source transaction count due to "oddSize" */
+                srcTs = srcTs - (oddSize / srcTrSize);
+        } else {
+                oddSize = dataLen % srcTrSize;
+        }
+        /* Adjust "descCount" due to "oddSize" */
+        if (oddSize) {
+                descCount++;
+        }
+        /* Find the number of descriptor needed for total "srcTs" */
+        if (srcTs) {
+                descCount += ((srcTs - 1) / maxBlockSize) + 1;
+        }
+        /* Check the availability of "descCount" discriptors in the ring */
+        pProg = pRing->pHead;
+        for (count = 0; (descCount <= pRing->num) && (count < descCount);
+             count++) {
+                if ((pProg->ctl.hi & dmacHw_DESC_FREE) == 0) {
+                        /* Sufficient descriptors are not available */
+                        return -3;
+                }
+                pProg = (dmacHw_DESC_t *) pProg->llp;
+        }
+        /* Remember the link list item to program the channel registers */
+        pStart = pProg = pRing->pHead;
+        /* Make a link list with "descCount(=count)" number of descriptors */
+        while (count) {
+                /* Reset channel control information */
+                pProg->ctl.lo = 0;
+                /* Enable source gather if configured */
+                if (pConfig->srcGatherWidth) {
+                        pProg->ctl.lo |= dmacHw_REG_CTL_SG_ENABLE;
+                }
+                /* Enable destination scatter if configured */
+                if (pConfig->dstScatterWidth) {
+                        pProg->ctl.lo |= dmacHw_REG_CTL_DS_ENABLE;
+                }
+                /* Set source and destination address */
+                pProg->sar = (uint32_t) pSrcAddr;
+                pProg->dar = (uint32_t) pDstAddr;
+                /* Use "devCtl" to mark that user memory need to be freed later if needed */
+                if (pProg == pRing->pHead) {
+                        pProg->devCtl = dmacHw_FREE_USER_MEMORY;
+                } else {
+                        pProg->devCtl = 0;
+                }
+                blkTs = srcTs;
+                /* Special treatmeant for last descriptor */
+                if (count == 1) {
+                        /* Mark the last descriptor */
+                        pProg->ctl.lo &=
+                            ~(dmacHw_REG_CTL_LLP_DST_EN |
+                              dmacHw_REG_CTL_LLP_SRC_EN);
+                        /* Treatment for odd data bytes */
+                        if (oddSize) {
+                                /* Adjust for single byte transaction width */
+                                switch (pConfig->transferType) {
+                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                                        dstTrWidth =
+                                            dmacHw_DST_TRANSACTION_WIDTH_8;
+                                        blkTs =
+                                            (oddSize / srcTrSize) +
+                                            ((oddSize % srcTrSize) ? 1 : 0);
+                                        break;
+                                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                                        srcTrWidth =
+                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
+                                        blkTs = oddSize;
+                                        break;
+                                case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
+                                        srcTrWidth =
+                                            dmacHw_SRC_TRANSACTION_WIDTH_8;
+                                        dstTrWidth =
+                                            dmacHw_DST_TRANSACTION_WIDTH_8;
+                                        blkTs = oddSize;
+                                        break;
+                                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
+                                        /* Do not adjust the transaction width  */
+                                        break;
+                                }
+                        } else {
+                                srcTs -= blkTs;
+                        }
+                } else {
+                        if (srcTs / maxBlockSize) {
+                                blkTs = maxBlockSize;
+                        }
+                        /* Remaining source transactions for next iteration */
+                        srcTs -= blkTs;
+                }
+                /* Must have a valid source transactions */
+                dmacHw_ASSERT(blkTs > 0);
+                /* Set control information */
+                if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
+                        pProg->ctl.lo |= pConfig->transferType |
+                            pConfig->srcUpdate |
+                            pConfig->dstUpdate |
+                            srcTrWidth |
+                            dstTrWidth |
+                            pConfig->srcMaxBurstWidth |
+                            pConfig->dstMaxBurstWidth |
+                            pConfig->srcMasterInterface |
+                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
+                } else {
+                        uint32_t transferType = 0;
+                        switch (pConfig->transferType) {
+                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                                transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
+                                break;
+                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                                transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
+                                break;
+                        default:
+                                dmacHw_ASSERT(0);
+                        }
+                        pProg->ctl.lo |= transferType |
+                            pConfig->srcUpdate |
+                            pConfig->dstUpdate |
+                            srcTrWidth |
+                            dstTrWidth |
+                            pConfig->srcMaxBurstWidth |
+                            pConfig->dstMaxBurstWidth |
+                            pConfig->srcMasterInterface |
+                            pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
+                }
+                /* Set block transaction size */
+                pProg->ctl.hi = blkTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
+                /* Look for next descriptor */
+                if (count > 1) {
+                        /* Point to the next descriptor */
+                        pProg = (dmacHw_DESC_t *) pProg->llp;
+                        /* Update source and destination address for next iteration */
+                        switch (pConfig->transferType) {
+                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                                if (pConfig->dstScatterWidth) {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->dstScatterWidth) *
+                                             pConfig->dstScatterJump);
+                                } else {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize;
+                                }
+                                break;
+                        case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                                if (pConfig->srcGatherWidth) {
+                                        pSrcAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->srcGatherWidth) *
+                                             pConfig->srcGatherJump);
+                                } else {
+                                        pSrcAddr =
+                                            (char *)pSrcAddr +
+                                            blkTs * srcTrSize;
+                                }
+                                break;
+                        case dmacHw_TRANSFER_TYPE_MEM_TO_MEM:
+                                if (pConfig->dstScatterWidth) {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->dstScatterWidth) *
+                                             pConfig->dstScatterJump);
+                                } else {
+                                        pDstAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize;
+                                }
+                                if (pConfig->srcGatherWidth) {
+                                        pSrcAddr =
+                                            (char *)pDstAddr +
+                                            blkTs * srcTrSize +
+                                            (((blkTs * srcTrSize) /
+                                              pConfig->srcGatherWidth) *
+                                             pConfig->srcGatherJump);
+                                } else {
+                                        pSrcAddr =
+                                            (char *)pSrcAddr +
+                                            blkTs * srcTrSize;
+                                }
+                                break;
+                        case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL:
+                                /* Do not adjust the address */
+                                break;
+                        default:
+                                dmacHw_ASSERT(0);
+                        }
+                } else {
+                        /* At the end of transfer "srcTs" must be zero */
+                        dmacHw_ASSERT(srcTs == 0);
+                }
+                count--;
+        }
+        /* Remember the descriptor to initialize the registers */
+        if (pRing->pProg == dmacHw_DESC_INIT) {
+                pRing->pProg = pStart;
+        }
+        /* Indicate that the descriptor is updated */
+        pRing->pEnd = pProg;
+        /* Head pointing to the next descriptor */
+        pRing->pHead = (dmacHw_DESC_t *) pProg->llp;
+        /* Update Tail pointer if destination is a peripheral,
+           because no one is going to read from the pTail
+         */
+        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
+                pRing->pTail = pRing->pHead;
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Provides DMA controller attributes
+*
+*
+*  @return  DMA controller attributes
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle */
+                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controler attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        switch (attr) {
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM:
+                return dmacHw_GET_NUM_CHANNEL(pCblk->module);
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE:
+                return (1 <<
+                         (dmacHw_GET_MAX_BLOCK_SIZE
+                          (pCblk->module, pCblk->module) + 2)) - 8;
+        case dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM:
+                return dmacHw_GET_NUM_INTERFACE(pCblk->module);
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH:
+                return 32 << dmacHw_GET_CHANNEL_DATA_WIDTH(pCblk->module,
+                                                           pCblk->channel);
+        case dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE:
+                return GetFifoSize(handle);
+        }
+        dmacHw_ASSERT(0);
+        return 0;
+}
diff --git a/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
new file mode 100644
index 000000000000..ff7b436d0935
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/dmac/dmacHw_extra.c
@@ -0,0 +1,1017 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    dmacHw_extra.c
+*
+*  @brief   Extra Low level DMA controller driver routines
+*
+*  @note
+*
+*   These routines provide basic DMA functionality only.
+*/
+/****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+#include <stddef.h>
+#include <csp/dmacHw.h>
+#include <mach/csp/dmacHw_reg.h>
+#include <mach/csp/dmacHw_priv.h>
+extern dmacHw_CBLK_t dmacHw_gCblk[dmacHw_MAX_CHANNEL_COUNT];    /* Declared in dmacHw.c */
+/* ---- External Function Prototypes ------------------------------------- */
+/* ---- Internal Use Function Prototypes --------------------------------- */
+/****************************************************************************/
+/**
+*  @brief   Overwrites data length in the descriptor
+*
+*  This function overwrites data length in the descriptor
+*
+*
+*  @return   void
+*
+*  @note
+*          This is only used for PCM channel
+*/
+/****************************************************************************/
+void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
+                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
+                          size_t dataLen        /*   [ IN ] Data length in bytes */
+    );
+/****************************************************************************/
+/**
+*  @brief   Helper function to display DMA registers
+*
+*  @return  void
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static void DisplayRegisterContents(int module, /*   [ IN ] DMA Controller unit  (0-1) */
+                                    int channel,        /*   [ IN ] DMA Channel          (0-7) / -1(all) */
+                                    int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
+    ) {
+        int chan;
+        (*fpPrint) ("Displaying register content \n\n");
+        (*fpPrint) ("Module %d: Interrupt raw transfer              0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt raw block                 0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt raw src transfer          0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt raw dst transfer          0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt raw error                 0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_RAW_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: Interrupt stat transfer             0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt stat block                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt stat src transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt stat dst transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt stat error                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_STAT_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: Interrupt mask transfer             0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt mask block                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt mask src transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt mask dst transfer         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt mask error                0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_MASK_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: Interrupt clear transfer            0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_TRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt clear block               0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_BLOCK(module)));
+        (*fpPrint) ("Module %d: Interrupt clear src transfer        0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_STRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt clear dst transfer        0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_DTRAN(module)));
+        (*fpPrint) ("Module %d: Interrupt clear error               0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_INT_CLEAR_ERROR(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: SW source req                       0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_REQ(module)));
+        (*fpPrint) ("Module %d: SW dest req                         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_REQ(module)));
+        (*fpPrint) ("Module %d: SW source signal                    0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_SGL_REQ(module)));
+        (*fpPrint) ("Module %d: SW dest signal                      0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_SGL_REQ(module)));
+        (*fpPrint) ("Module %d: SW source last                      0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_SRC_LST_REQ(module)));
+        (*fpPrint) ("Module %d: SW dest last                        0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_SW_HS_DST_LST_REQ(module)));
+        (*fpPrint) ("--------------------------------------------------\n");
+        (*fpPrint) ("Module %d: misc config                         0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_CFG(module)));
+        (*fpPrint) ("Module %d: misc channel enable                 0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_CH_ENABLE(module)));
+        (*fpPrint) ("Module %d: misc ID                             0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_ID(module)));
+        (*fpPrint) ("Module %d: misc test                           0x%X\n",
+                    module, (uint32_t) (dmacHw_REG_MISC_TEST(module)));
+        if (channel == -1) {
+                for (chan = 0; chan < 8; chan++) {
+                        (*fpPrint)
+                            ("--------------------------------------------------\n");
+                        (*fpPrint)
+                            ("Module %d: Channel %d Source                   0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_SAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Destination              0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_DAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d LLP                      0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_LLP(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Control (LO)             0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Control (HI)             0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Source Stats             0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Dest Stats               0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Source Stats Addr        0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Config (LO)              0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
+                        (*fpPrint)
+                            ("Module %d: Channel %d Config (HI)              0x%X\n",
+                             module, chan,
+                             (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
+                }
+        } else {
+                chan = channel;
+                (*fpPrint)
+                    ("--------------------------------------------------\n");
+                (*fpPrint)
+                    ("Module %d: Channel %d Source                   0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_SAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Destination              0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_DAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d LLP                      0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_LLP(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Control (LO)             0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CTL_LO(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Control (HI)             0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CTL_HI(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Source Stats             0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_SSTAT(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Dest Stats               0x%X\n",
+                     module, chan, (uint32_t) (dmacHw_REG_DSTAT(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Source Stats Addr        0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_SSTATAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Dest Stats Addr          0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_DSTATAR(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Config (LO)              0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CFG_LO(module, chan)));
+                (*fpPrint)
+                    ("Module %d: Channel %d Config (HI)              0x%X\n",
+                     module, chan,
+                     (uint32_t) (dmacHw_REG_CFG_HI(module, chan)));
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Helper function to display descriptor ring
+*
+*  @return  void
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static void DisplayDescRing(void *pDescriptor,  /*   [ IN ] Descriptor buffer */
+                            int (*fpPrint) (const char *, ...)  /*   [ IN ] Callback to the print function */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        dmacHw_DESC_t *pStart;
+        if (pRing->pHead == NULL) {
+                return;
+        }
+        pStart = pRing->pHead;
+        while ((dmacHw_DESC_t *) pStart->llp != pRing->pHead) {
+                if (pStart == pRing->pHead) {
+                        (*fpPrint) ("Head\n");
+                }
+                if (pStart == pRing->pTail) {
+                        (*fpPrint) ("Tail\n");
+                }
+                if (pStart == pRing->pProg) {
+                        (*fpPrint) ("Prog\n");
+                }
+                if (pStart == pRing->pEnd) {
+                        (*fpPrint) ("End\n");
+                }
+                if (pStart == pRing->pFree) {
+                        (*fpPrint) ("Free\n");
+                }
+                (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
+                (*fpPrint) ("sar    0x%0X\n", pStart->sar);
+                (*fpPrint) ("dar    0x%0X\n", pStart->dar);
+                (*fpPrint) ("llp    0x%0X\n", pStart->llp);
+                (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
+                (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
+                (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
+                (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
+                (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
+                pStart = (dmacHw_DESC_t *) pStart->llp;
+        }
+        if (pStart == pRing->pHead) {
+                (*fpPrint) ("Head\n");
+        }
+        if (pStart == pRing->pTail) {
+                (*fpPrint) ("Tail\n");
+        }
+        if (pStart == pRing->pProg) {
+                (*fpPrint) ("Prog\n");
+        }
+        if (pStart == pRing->pEnd) {
+                (*fpPrint) ("End\n");
+        }
+        if (pStart == pRing->pFree) {
+                (*fpPrint) ("Free\n");
+        }
+        (*fpPrint) ("0x%X:\n", (uint32_t) pStart);
+        (*fpPrint) ("sar    0x%0X\n", pStart->sar);
+        (*fpPrint) ("dar    0x%0X\n", pStart->dar);
+        (*fpPrint) ("llp    0x%0X\n", pStart->llp);
+        (*fpPrint) ("ctl.lo 0x%0X\n", pStart->ctl.lo);
+        (*fpPrint) ("ctl.hi 0x%0X\n", pStart->ctl.hi);
+        (*fpPrint) ("sstat  0x%0X\n", pStart->sstat);
+        (*fpPrint) ("dstat  0x%0X\n", pStart->dstat);
+        (*fpPrint) ("devCtl 0x%0X\n", pStart->devCtl);
+}
+/****************************************************************************/
+/**
+*  @brief   Check if DMA channel is the flow controller
+*
+*  @return  1 : If DMA is a flow controler
+*           0 : Peripheral is the flow controller
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static inline int DmaIsFlowController(void *pDescriptor /*   [ IN ] Descriptor buffer */
+    ) {
+        uint32_t ttfc =
+            (dmacHw_GET_DESC_RING(pDescriptor))->pTail->ctl.
+            lo & dmacHw_REG_CTL_TTFC_MASK;
+        switch (ttfc) {
+        case dmacHw_REG_CTL_TTFC_MM_DMAC:
+        case dmacHw_REG_CTL_TTFC_MP_DMAC:
+        case dmacHw_REG_CTL_TTFC_PM_DMAC:
+        case dmacHw_REG_CTL_TTFC_PP_DMAC:
+                return 1;
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Overwrites data length in the descriptor
+*
+*  This function overwrites data length in the descriptor
+*
+*
+*  @return   void
+*
+*  @note
+*          This is only used for PCM channel
+*/
+/****************************************************************************/
+void dmacHw_setDataLength(dmacHw_CONFIG_t *pConfig,     /*   [ IN ] Configuration settings */
+                          void *pDescriptor,    /*   [ IN ] Descriptor buffer */
+                          size_t dataLen        /*   [ IN ] Data length in bytes */
+    ) {
+        dmacHw_DESC_t *pProg;
+        dmacHw_DESC_t *pHead;
+        int srcTs = 0;
+        int srcTrSize = 0;
+        pHead = (dmacHw_GET_DESC_RING(pDescriptor))->pHead;
+        pProg = pHead;
+        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+        srcTs = dataLen / srcTrSize;
+        do {
+                pProg->ctl.hi = srcTs & dmacHw_REG_CTL_BLOCK_TS_MASK;
+                pProg = (dmacHw_DESC_t *) pProg->llp;
+        } while (pProg != pHead);
+}
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the DMA channel specific interrupt
+*
+*
+*  @return   void
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /* [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_TRAN_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_BLOCK_INT_CLEAR(pCblk->module, pCblk->channel);
+        dmacHw_ERROR_INT_CLEAR(pCblk->module, pCblk->channel);
+}
+/****************************************************************************/
+/**
+*  @brief   Returns the cause of channel specific DMA interrupt
+*
+*  This function returns the cause of interrupt
+*
+*  @return  Interrupt status, each bit representing a specific type of interrupt
+*
+*  @note
+*     Should be called under the context of ISR
+*/
+/****************************************************************************/
+dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /* [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_INTERRUPT_STATUS_e status = dmacHw_INTERRUPT_STATUS_NONE;
+        if (dmacHw_REG_INT_STAT_TRAN(pCblk->module) &
+            ((0x00000001 << pCblk->channel))) {
+                status |= dmacHw_INTERRUPT_STATUS_TRANS;
+        }
+        if (dmacHw_REG_INT_STAT_BLOCK(pCblk->module) &
+            ((0x00000001 << pCblk->channel))) {
+                status |= dmacHw_INTERRUPT_STATUS_BLOCK;
+        }
+        if (dmacHw_REG_INT_STAT_ERROR(pCblk->module) &
+            ((0x00000001 << pCblk->channel))) {
+                status |= dmacHw_INTERRUPT_STATUS_ERROR;
+        }
+        return status;
+}
+/****************************************************************************/
+/**
+*  @brief   Indentifies a DMA channel causing interrupt
+*
+*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
+*
+*  @return  NULL   : No channel causing DMA interrupt
+*           ! NULL : Handle to a channel causing DMA interrupt
+*  @note
+*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getInterruptSource(void)
+{
+        uint32_t i;
+        for (i = 0; i < dmaChannelCount_0 + dmaChannelCount_1; i++) {
+                if ((dmacHw_REG_INT_STAT_TRAN(dmacHw_gCblk[i].module) &
+                     ((0x00000001 << dmacHw_gCblk[i].channel)))
+                    || (dmacHw_REG_INT_STAT_BLOCK(dmacHw_gCblk[i].module) &
+                        ((0x00000001 << dmacHw_gCblk[i].channel)))
+                    || (dmacHw_REG_INT_STAT_ERROR(dmacHw_gCblk[i].module) &
+                        ((0x00000001 << dmacHw_gCblk[i].channel)))
+                    ) {
+                        return dmacHw_CBLK_TO_HANDLE(&dmacHw_gCblk[i]);
+                }
+        }
+        return dmacHw_CBLK_TO_HANDLE(NULL);
+}
+/****************************************************************************/
+/**
+*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
+*
+*
+*  @return  On failure : -1
+*           On success : Number of descriptor count
+*
+*
+*/
+/****************************************************************************/
+int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
+                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
+                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
+                                    size_t dataLen      /*   [ IN ] Data length in bytes */
+    ) {
+        int srcTs = 0;
+        int oddSize = 0;
+        int descCount = 0;
+        int dstTrSize = 0;
+        int srcTrSize = 0;
+        uint32_t maxBlockSize = dmacHw_MAX_BLOCKSIZE;
+        dmacHw_TRANSACTION_WIDTH_e dstTrWidth;
+        dmacHw_TRANSACTION_WIDTH_e srcTrWidth;
+        dstTrSize = dmacHw_GetTrWidthInBytes(pConfig->dstMaxTransactionWidth);
+        srcTrSize = dmacHw_GetTrWidthInBytes(pConfig->srcMaxTransactionWidth);
+        /* Skip Tx if buffer is NULL  or length is unknown */
+        if ((pSrcAddr == NULL) || (pDstAddr == NULL) || (dataLen == 0)) {
+                /* Do not initiate transfer */
+                return -1;
+        }
+        /* Ensure scatter and gather are transaction aligned */
+        if (pConfig->srcGatherWidth % srcTrSize
+            || pConfig->dstScatterWidth % dstTrSize) {
+                return -1;
+        }
+        /*
+           Background 1: DMAC can not perform DMA if source and destination addresses are
+           not properly aligned with the channel's transaction width. So, for successful
+           DMA transfer, transaction width must be set according to the alignment of the
+           source and destination address.
+         */
+        /* Adjust destination transaction width if destination address is not aligned properly */
+        dstTrWidth = pConfig->dstMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(dstTrSize) & (uint32_t) pDstAddr) {
+                dstTrWidth = dmacHw_GetNextTrWidth(dstTrWidth);
+                dstTrSize = dmacHw_GetTrWidthInBytes(dstTrWidth);
+        }
+        /* Adjust source transaction width if source address is not aligned properly */
+        srcTrWidth = pConfig->srcMaxTransactionWidth;
+        while (dmacHw_ADDRESS_MASK(srcTrSize) & (uint32_t) pSrcAddr) {
+                srcTrWidth = dmacHw_GetNextTrWidth(srcTrWidth);
+                srcTrSize = dmacHw_GetTrWidthInBytes(srcTrWidth);
+        }
+        /* Find the maximum transaction per descriptor */
+        if (pConfig->maxDataPerBlock
+            && ((pConfig->maxDataPerBlock / srcTrSize) <
+                dmacHw_MAX_BLOCKSIZE)) {
+                maxBlockSize = pConfig->maxDataPerBlock / srcTrSize;
+        }
+        /* Find number of source transactions needed to complete the DMA transfer */
+        srcTs = dataLen / srcTrSize;
+        /* Find the odd number of bytes that need to be transferred as single byte transaction width */
+        if (srcTs && (dstTrSize > srcTrSize)) {
+                oddSize = dataLen % dstTrSize;
+                /* Adjust source transaction count due to "oddSize" */
+                srcTs = srcTs - (oddSize / srcTrSize);
+        } else {
+                oddSize = dataLen % srcTrSize;
+        }
+        /* Adjust "descCount" due to "oddSize" */
+        if (oddSize) {
+                descCount++;
+        }
+        /* Find the number of descriptor needed for total "srcTs" */
+        if (srcTs) {
+                descCount += ((srcTs - 1) / maxBlockSize) + 1;
+        }
+        return descCount;
+}
+/****************************************************************************/
+/**
+*  @brief   Check the existance of pending descriptor
+*
+*  This function confirmes if there is any pending descriptor in the chain
+*  to program the channel
+*
+*  @return  1 : Channel need to be programmed with pending descriptor
+*           0 : No more pending descriptor to programe the channel
+*
+*  @note
+*     - This function should be called from ISR in case there are pending
+*       descriptor to program the channel.
+*
+*     Example:
+*
+*     dmac_isr ()
+*     {
+*         ...
+*         if (dmacHw_descriptorPending (handle))
+*         {
+*            dmacHw_initiateTransfer (handle);
+*         }
+*     }
+*
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
+                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        /* Make sure channel is not busy */
+        if (!CHANNEL_BUSY(pCblk->module, pCblk->channel)) {
+                /* Check if pEnd is not processed */
+                if (pRing->pEnd) {
+                        /* Something left for processing */
+                        return 1;
+                }
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Program channel register to stop transfer
+*
+*  Ensures the channel is not doing any transfer after calling this function
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk;
+        pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        /* Stop the channel */
+        dmacHw_DMA_STOP(pCblk->module, pCblk->channel);
+}
+/****************************************************************************/
+/**
+*  @brief   Deallocates source or destination memory, allocated
+*
+*  This function can be called to deallocate data memory that was DMAed successfully
+*
+*  @return  On failure : -1
+*           On success : Number of buffer freed
+*
+*  @note
+*     This function will be called ONLY, when source OR destination address is pointing
+*     to dynamic memory
+*/
+/****************************************************************************/
+int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*   [ IN ] Configuration settings */
+                   void *pDescriptor,   /*   [ IN ] Descriptor buffer */
+                   void (*fpFree) (void *)      /*   [ IN ] Function pointer to free data memory */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        uint32_t count = 0;
+        if (fpFree == NULL) {
+                return -1;
+        }
+        while ((pRing->pFree != pRing->pTail)
+               && (pRing->pFree->ctl.lo & dmacHw_DESC_FREE)) {
+                if (pRing->pFree->devCtl == dmacHw_FREE_USER_MEMORY) {
+                        /* Identify, which memory to free */
+                        if (dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
+                                (*fpFree) ((void *)pRing->pFree->dar);
+                        } else {
+                                /* Destination was a peripheral */
+                                (*fpFree) ((void *)pRing->pFree->sar);
+                        }
+                        /* Unmark user memory to indicate it is freed */
+                        pRing->pFree->devCtl = ~dmacHw_FREE_USER_MEMORY;
+                }
+                dmacHw_NEXT_DESC(pRing, pFree);
+                count++;
+        }
+        return count;
+}
+/****************************************************************************/
+/**
+*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
+*
+*  This function will update the discriptor ring by allocating buffers, when source peripheral
+*  has to work as a flow controller to transfer data from:
+*           - Peripheral to memory.
+*
+*  @return  On failure : -1
+*           On success : Number of descriptor updated
+*
+*
+*  @note
+*     Channel must be configured for peripheral to memory transfer
+*
+*/
+/****************************************************************************/
+int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
+                                     dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                                     void *pDescriptor, /*   [ IN ] Descriptor buffer */
+                                     uint32_t srcAddr,  /*   [ IN ] Source peripheral address */
+                                     void *(*fpAlloc) (int len),        /*   [ IN ] Function pointer  that provides destination memory */
+                                     int len,   /*   [ IN ] Number of bytes "fpAlloc" will allocate for destination */
+                                     int num    /*   [ IN ] Number of descriptor to set */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        dmacHw_DESC_t *pProg = NULL;
+        dmacHw_DESC_t *pLast = NULL;
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        uint32_t dstAddr;
+        uint32_t controlParam;
+        int i;
+        dmacHw_ASSERT(pConfig->transferType ==
+                      dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM);
+        if (num > pRing->num) {
+                return -1;
+        }
+        pLast = pRing->pEnd;    /* Last descriptor updated */
+        pProg = pRing->pHead;   /* First descriptor in the new list */
+        controlParam = pConfig->srcUpdate |
+            pConfig->dstUpdate |
+            pConfig->srcMaxTransactionWidth |
+            pConfig->dstMaxTransactionWidth |
+            pConfig->srcMasterInterface |
+            pConfig->dstMasterInterface |
+            pConfig->srcMaxBurstWidth |
+            pConfig->dstMaxBurstWidth |
+            dmacHw_REG_CTL_TTFC_PM_PERI |
+            dmacHw_REG_CTL_LLP_DST_EN |
+            dmacHw_REG_CTL_LLP_SRC_EN | dmacHw_REG_CTL_INT_EN;
+        for (i = 0; i < num; i++) {
+                /* Allocate Rx buffer only for idle descriptor */
+                if (((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) ||
+                    ((dmacHw_DESC_t *) pRing->pHead->llp == pRing->pTail)
+                    ) {
+                        /* Rx descriptor is not idle */
+                        break;
+                }
+                /* Set source address */
+                pRing->pHead->sar = srcAddr;
+                if (fpAlloc) {
+                        /* Allocate memory for buffer in descriptor */
+                        dstAddr = (uint32_t) (*fpAlloc) (len);
+                        /* Check the destination address */
+                        if (dstAddr == 0) {
+                                if (i == 0) {
+                                        /* Not a single descriptor is available */
+                                        return -1;
+                                }
+                                break;
+                        }
+                        /* Set destination address */
+                        pRing->pHead->dar = dstAddr;
+                }
+                /* Set control information */
+                pRing->pHead->ctl.lo = controlParam;
+                /* Use "devCtl" to mark the memory that need to be freed later */
+                pRing->pHead->devCtl = dmacHw_FREE_USER_MEMORY;
+                /* Descriptor is now owned by the channel */
+                pRing->pHead->ctl.hi = 0;
+                /* Remember the descriptor last updated */
+                pRing->pEnd = pRing->pHead;
+                /* Update next descriptor */
+                dmacHw_NEXT_DESC(pRing, pHead);
+        }
+        /* Mark the end of the list */
+        pRing->pEnd->ctl.lo &=
+            ~(dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN);
+        /* Connect the list */
+        if (pLast != pProg) {
+                pLast->ctl.lo |=
+                    dmacHw_REG_CTL_LLP_DST_EN | dmacHw_REG_CTL_LLP_SRC_EN;
+        }
+        /* Mark the descriptors are updated */
+        pCblk->descUpdated = 1;
+        if (!pCblk->varDataStarted) {
+                /* LLP must be pointing to the first descriptor */
+                dmacHw_SET_LLP(pCblk->module, pCblk->channel,
+                               (uint32_t) pProg - pRing->virt2PhyOffset);
+                /* Channel, handling variable data started */
+                pCblk->varDataStarted = 1;
+        }
+        return i;
+}
+/****************************************************************************/
+/**
+*  @brief   Read data DMAed to memory
+*
+*  This function will read data that has been DMAed to memory while transfering from:
+*          - Memory to memory
+*          - Peripheral to memory
+*
+*  @param    handle     -
+*  @param    ppBbuf     -
+*  @param    pLen       -
+*
+*  @return  0 - No more data is available to read
+*           1 - More data might be available to read
+*
+*/
+/****************************************************************************/
+int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
+                               dmacHw_CONFIG_t *pConfig,        /*   [ IN ]  Configuration settings */
+                               void *pDescriptor,       /*   [ IN ] Descriptor buffer */
+                               void **ppBbuf,   /*   [ OUT ] Data received */
+                               size_t *pLlen    /*   [ OUT ] Length of the data received */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        (void)handle;
+        if (pConfig->transferMode != dmacHw_TRANSFER_MODE_CONTINUOUS) {
+                if (((pRing->pTail->ctl.hi & dmacHw_DESC_FREE) == 0) ||
+                    (pRing->pTail == pRing->pHead)
+                    ) {
+                        /* No receive data available */
+                        *ppBbuf = (char *)NULL;
+                        *pLlen = 0;
+                        return 0;
+                }
+        }
+        /* Return read buffer and length */
+        *ppBbuf = (char *)pRing->pTail->dar;
+        /* Extract length of the received data */
+        if (DmaIsFlowController(pDescriptor)) {
+                uint32_t srcTrSize = 0;
+                switch (pRing->pTail->ctl.lo & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_8:
+                        srcTrSize = 1;
+                        break;
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_16:
+                        srcTrSize = 2;
+                        break;
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_32:
+                        srcTrSize = 4;
+                        break;
+                case dmacHw_REG_CTL_SRC_TR_WIDTH_64:
+                        srcTrSize = 8;
+                        break;
+                default:
+                        dmacHw_ASSERT(0);
+                }
+                /* Calculate length from the block size */
+                *pLlen =
+                    (pRing->pTail->ctl.hi & dmacHw_REG_CTL_BLOCK_TS_MASK) *
+                    srcTrSize;
+        } else {
+                /* Extract length from the source peripheral */
+                *pLlen = pRing->pTail->sstat;
+        }
+        /* Advance tail to next descriptor */
+        dmacHw_NEXT_DESC(pRing, pTail);
+        return 1;
+}
+/****************************************************************************/
+/**
+*  @brief   Set descriptor carrying control information
+*
+*  This function will be used to send specific control information to the device
+*  using the DMA channel
+*
+*
+*  @return  -1 - On failure
+*            0 - On success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*   [ IN ] Configuration settings */
+                                void *pDescriptor,      /*   [ IN ] Descriptor buffer */
+                                uint32_t ctlAddress,    /*   [ IN ] Address of the device control register */
+                                uint32_t control        /*   [ IN ] Device control information */
+    ) {
+        dmacHw_DESC_RING_t *pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        if (ctlAddress == 0) {
+                return -1;
+        }
+        /* Check the availability of descriptors in the ring */
+        if ((pRing->pHead->ctl.hi & dmacHw_DESC_FREE) == 0) {
+                return -1;
+        }
+        /* Set control information */
+        pRing->pHead->devCtl = control;
+        /* Set source and destination address */
+        pRing->pHead->sar = (uint32_t) &pRing->pHead->devCtl;
+        pRing->pHead->dar = ctlAddress;
+        /* Set control parameters */
+        if (pConfig->flowControler == dmacHw_FLOW_CONTROL_DMA) {
+                pRing->pHead->ctl.lo = pConfig->transferType |
+                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
+                    pConfig->dstMaxTransactionWidth |
+                    dmacHw_SRC_BURST_WIDTH_0 |
+                    dmacHw_DST_BURST_WIDTH_0 |
+                    pConfig->srcMasterInterface |
+                    pConfig->dstMasterInterface | dmacHw_REG_CTL_INT_EN;
+        } else {
+                uint32_t transferType = 0;
+                switch (pConfig->transferType) {
+                case dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM:
+                        transferType = dmacHw_REG_CTL_TTFC_PM_PERI;
+                        break;
+                case dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL:
+                        transferType = dmacHw_REG_CTL_TTFC_MP_PERI;
+                        break;
+                default:
+                        dmacHw_ASSERT(0);
+                }
+                pRing->pHead->ctl.lo = transferType |
+                    dmacHw_SRC_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_DST_ADDRESS_UPDATE_MODE_INC |
+                    dmacHw_SRC_TRANSACTION_WIDTH_32 |
+                    pConfig->dstMaxTransactionWidth |
+                    dmacHw_SRC_BURST_WIDTH_0 |
+                    dmacHw_DST_BURST_WIDTH_0 |
+                    pConfig->srcMasterInterface |
+                    pConfig->dstMasterInterface |
+                    pConfig->flowControler | dmacHw_REG_CTL_INT_EN;
+        }
+        /* Set block transaction size to one 32 bit transaction */
+        pRing->pHead->ctl.hi = dmacHw_REG_CTL_BLOCK_TS_MASK & 1;
+        /* Remember the descriptor to initialize the registers */
+        if (pRing->pProg == dmacHw_DESC_INIT) {
+                pRing->pProg = pRing->pHead;
+        }
+        pRing->pEnd = pRing->pHead;
+        /* Advance the descriptor */
+        dmacHw_NEXT_DESC(pRing, pHead);
+        /* Update Tail pointer if destination is a peripheral */
+        if (!dmacHw_DST_IS_MEMORY(pConfig->transferType)) {
+                pRing->pTail = pRing->pHead;
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Sets channel specific user data
+*
+*  This function associates user data to a specif DMA channel
+*
+*/
+/****************************************************************************/
+void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle */
+                               void *userData   /*  [ IN ] User data */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        pCblk->userData = userData;
+}
+/****************************************************************************/
+/**
+*  @brief   Gets channel specific user data
+*
+*  This function returns user data specific to a DMA channel
+*
+*  @return   user data
+*/
+/****************************************************************************/
+void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        return pCblk->userData;
+}
+/****************************************************************************/
+/**
+*  @brief   Resets descriptor control information
+*
+*  @return  void
+*/
+/****************************************************************************/
+void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
+    ) {
+        int i;
+        dmacHw_DESC_RING_t *pRing;
+        dmacHw_DESC_t *pDesc;
+        pRing = dmacHw_GET_DESC_RING(pDescriptor);
+        pDesc = pRing->pHead;
+        for (i = 0; i < pRing->num; i++) {
+                /* Mark descriptor is ready to use */
+                pDesc->ctl.hi = dmacHw_DESC_FREE;
+                /* Look into next link list item */
+                pDesc++;
+        }
+        pRing->pFree = pRing->pTail = pRing->pEnd = pRing->pHead;
+        pRing->pProg = dmacHw_DESC_INIT;
+}
+/****************************************************************************/
+/**
+*  @brief   Displays channel specific registers and other control parameters
+*
+*  @return  void
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle */
+                           void *pDescriptor,   /*   [ IN ] Descriptor buffer */
+                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
+    ) {
+        dmacHw_CBLK_t *pCblk = dmacHw_HANDLE_TO_CBLK(handle);
+        DisplayRegisterContents(pCblk->module, pCblk->channel, fpPrint);
+        DisplayDescRing(pDescriptor, fpPrint);
+}
diff --git a/arch/arm/mach-bcmring/csp/tmr/Makefile b/arch/arm/mach-bcmring/csp/tmr/Makefile
new file mode 100644
index 000000000000..244a61ab7697
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/tmr/Makefile
@@ -0,0 +1 @@
+obj-y += tmrHw.o
diff --git a/arch/arm/mach-bcmring/csp/tmr/tmrHw.c b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
new file mode 100644
index 000000000000..5c1c9a0e5ed2
--- /dev/null
+++ b/arch/arm/mach-bcmring/csp/tmr/tmrHw.c
@@ -0,0 +1,576 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    tmrHw.c
+*
+*  @brief   Low level Timer driver routines
+*
+*  @note
+*
+*   These routines provide basic timer functionality only.
+*/
+/****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/errno.h>
+#include <csp/stdint.h>
+#include <csp/tmrHw.h>
+#include <mach/csp/tmrHw_reg.h>
+#define tmrHw_ASSERT(a)                     if (!(a)) *(char *)0 = 0
+#define tmrHw_MILLISEC_PER_SEC              (1000)
+#define tmrHw_LOW_1_RESOLUTION_COUNT        (tmrHw_LOW_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
+#define tmrHw_LOW_1_MAX_MILLISEC            (0xFFFFFFFF / tmrHw_LOW_1_RESOLUTION_COUNT)
+#define tmrHw_LOW_16_RESOLUTION_COUNT       (tmrHw_LOW_1_RESOLUTION_COUNT / 16)
+#define tmrHw_LOW_16_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_LOW_16_RESOLUTION_COUNT)
+#define tmrHw_LOW_256_RESOLUTION_COUNT      (tmrHw_LOW_1_RESOLUTION_COUNT / 256)
+#define tmrHw_LOW_256_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_LOW_256_RESOLUTION_COUNT)
+#define tmrHw_HIGH_1_RESOLUTION_COUNT       (tmrHw_HIGH_RESOLUTION_CLOCK / tmrHw_MILLISEC_PER_SEC)
+#define tmrHw_HIGH_1_MAX_MILLISEC           (0xFFFFFFFF / tmrHw_HIGH_1_RESOLUTION_COUNT)
+#define tmrHw_HIGH_16_RESOLUTION_COUNT      (tmrHw_HIGH_1_RESOLUTION_COUNT / 16)
+#define tmrHw_HIGH_16_MAX_MILLISEC          (0xFFFFFFFF / tmrHw_HIGH_16_RESOLUTION_COUNT)
+#define tmrHw_HIGH_256_RESOLUTION_COUNT     (tmrHw_HIGH_1_RESOLUTION_COUNT / 256)
+#define tmrHw_HIGH_256_MAX_MILLISEC         (0xFFFFFFFF / tmrHw_HIGH_256_RESOLUTION_COUNT)
+static void ResetTimer(tmrHw_ID_t timerId)
+    __attribute__ ((section(".aramtext")));
+static int tmrHw_divide(int num, int denom)
+    __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Get timer capability
+*
+*  This function returns various capabilities/attributes of a timer
+*
+*  @return  Capability
+*
+*/
+/****************************************************************************/
+uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
+                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
+) {
+        switch (capability) {
+        case tmrHw_CAPABILITY_CLOCK:
+                return (timerId <=
+                        1) ? tmrHw_LOW_RESOLUTION_CLOCK :
+                    tmrHw_HIGH_RESOLUTION_CLOCK;
+        case tmrHw_CAPABILITY_RESOLUTION:
+                return 32;
+        default:
+                return 0;
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Resets a timer
+*
+*  This function initializes  timer
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+static void ResetTimer(tmrHw_ID_t timerId       /*  [ IN ] Timer Id */
+) {
+        /* Reset timer */
+        pTmrHw[timerId].LoadValue = 0;
+        pTmrHw[timerId].CurrentValue = 0xFFFFFFFF;
+        pTmrHw[timerId].Control = 0;
+        pTmrHw[timerId].BackgroundLoad = 0;
+        /* Always configure as a 32 bit timer */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_32BIT;
+        /* Clear interrupt only if raw status interrupt is set */
+        if (pTmrHw[timerId].RawInterruptStatus) {
+                pTmrHw[timerId].InterruptClear = 0xFFFFFFFF;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Sets counter value for an interval in ms
+*
+*  @return   On success: Effective counter value set
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+static tmrHw_INTERVAL_t SetTimerPeriod(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                       tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
+) {
+        uint32_t scale = 0;
+        uint32_t count = 0;
+        if (timerId == 0 || timerId == 1) {
+                if (msec <= tmrHw_LOW_1_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+                        scale = tmrHw_LOW_1_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_LOW_16_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
+                        scale = tmrHw_LOW_16_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_LOW_256_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
+                        scale = tmrHw_LOW_256_RESOLUTION_COUNT;
+                } else {
+                        return 0;
+                }
+                count = msec * scale;
+                /* Set counter value */
+                pTmrHw[timerId].LoadValue = count;
+                pTmrHw[timerId].BackgroundLoad = count;
+        } else if (timerId == 2 || timerId == 3) {
+                if (msec <= tmrHw_HIGH_1_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+                        scale = tmrHw_HIGH_1_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_HIGH_16_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
+                        scale = tmrHw_HIGH_16_RESOLUTION_COUNT;
+                } else if (msec <= tmrHw_HIGH_256_MAX_MILLISEC) {
+                        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
+                        scale = tmrHw_HIGH_256_RESOLUTION_COUNT;
+                } else {
+                        return 0;
+                }
+                count = msec * scale;
+                /* Set counter value */
+                pTmrHw[timerId].LoadValue = count;
+                pTmrHw[timerId].BackgroundLoad = count;
+        }
+        return count / scale;
+}
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer in terms of timer interrupt rate
+*
+*  This function initializes a periodic timer to generate specific number of
+*  timer interrupt per second
+*
+*  @return   On success: Effective timer frequency
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
+) {
+        uint32_t resolution = 0;
+        uint32_t count = 0;
+        ResetTimer(timerId);
+        /* Set timer mode periodic */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
+        /* Set timer in highest resolution */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+        if (rate && (timerId == 0 || timerId == 1)) {
+                if (rate > tmrHw_LOW_RESOLUTION_CLOCK) {
+                        return 0;
+                }
+                resolution = tmrHw_LOW_RESOLUTION_CLOCK;
+        } else if (rate && (timerId == 2 || timerId == 3)) {
+                if (rate > tmrHw_HIGH_RESOLUTION_CLOCK) {
+                        return 0;
+                } else {
+                        resolution = tmrHw_HIGH_RESOLUTION_CLOCK;
+                }
+        } else {
+                return 0;
+        }
+        /* Find the counter value */
+        count = resolution / rate;
+        /* Set counter value */
+        pTmrHw[timerId].LoadValue = count;
+        pTmrHw[timerId].BackgroundLoad = count;
+        return resolution / count;
+}
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt after
+*           certain time interval
+*
+*  This function initializes a periodic timer to generate timer interrupt
+*  after every time interval in millisecond
+*
+*  @return   On success: Effective interval set in milli-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in milli-second */
+) {
+        ResetTimer(timerId);
+        /* Set timer mode periodic */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
+        return SetTimerPeriod(timerId, msec);
+}
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt just once
+*           after certain time interval
+*
+*  This function initializes a periodic timer to generate a single ticks after
+*  certain time interval in millisecond
+*
+*  @return   On success: Effective interval set in milli-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in milli-second */
+) {
+        ResetTimer(timerId);
+        /* Set timer mode oneshot */
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_ONESHOT;
+        return SetTimerPeriod(timerId, msec);
+}
+/****************************************************************************/
+/**
+*  @brief   Configures a timer to run as a free running timer
+*
+*  This function initializes a timer to run as a free running timer
+*
+*  @return   Timer resolution (count / sec)
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
+) {
+        uint32_t scale = 0;
+        ResetTimer(timerId);
+        /* Set timer as free running mode */
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_PERIODIC;
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_ONESHOT;
+        if (divider >= 64) {
+                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_256;
+                scale = 256;
+        } else if (divider >= 8) {
+                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_16;
+                scale = 16;
+        } else {
+                pTmrHw[timerId].Control |= tmrHw_CONTROL_PRESCALE_1;
+                scale = 1;
+        }
+        if (timerId == 0 || timerId == 1) {
+                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, scale);
+        } else if (timerId == 2 || timerId == 3) {
+                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, scale);
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Starts a timer
+*
+*  This function starts a preconfigured timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*/
+/****************************************************************************/
+int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_TIMER_ENABLE;
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Stops a timer
+*
+*  This function stops a running timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*/
+/****************************************************************************/
+int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_TIMER_ENABLE;
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Gets current timer count
+*
+*  This function returns the current timer value
+*
+*  @return  Current downcounting timer value
+*
+*/
+/****************************************************************************/
+uint32_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId       /*  [ IN ] Timer id */
+) {
+        /* return 32 bit timer value */
+        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_MODE_MASK) {
+        case tmrHw_CONTROL_FREE_RUNNING:
+                if (pTmrHw[timerId].CurrentValue) {
+                        return tmrHw_MAX_COUNT - pTmrHw[timerId].CurrentValue;
+                }
+                break;
+        case tmrHw_CONTROL_PERIODIC:
+        case tmrHw_CONTROL_ONESHOT:
+                return pTmrHw[timerId].BackgroundLoad -
+                    pTmrHw[timerId].CurrentValue;
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Gets timer count rate
+*
+*  This function returns the number of counts per second
+*
+*  @return  Count rate
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
+) {
+        uint32_t divider = 0;
+        switch (pTmrHw[timerId].Control & tmrHw_CONTROL_PRESCALE_MASK) {
+        case tmrHw_CONTROL_PRESCALE_1:
+                divider = 1;
+                break;
+        case tmrHw_CONTROL_PRESCALE_16:
+                divider = 16;
+                break;
+        case tmrHw_CONTROL_PRESCALE_256:
+                divider = 256;
+                break;
+        default:
+                tmrHw_ASSERT(0);
+        }
+        if (timerId == 0 || timerId == 1) {
+                return tmrHw_divide(tmrHw_LOW_RESOLUTION_CLOCK, divider);
+        } else {
+                return tmrHw_divide(tmrHw_HIGH_RESOLUTION_CLOCK, divider);
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Enables timer interrupt
+*
+*  This function enables the timer interrupt
+*
+*  @return   N/A
+*
+*/
+/****************************************************************************/
+void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control |= tmrHw_CONTROL_INTERRUPT_ENABLE;
+}
+/****************************************************************************/
+/**
+*  @brief   Disables timer interrupt
+*
+*  This function disable the timer interrupt
+*
+*  @return   N/A
+*
+*/
+/****************************************************************************/
+void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].Control &= ~tmrHw_CONTROL_INTERRUPT_ENABLE;
+}
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the timer interrupt
+*
+*  @return   N/A
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+) {
+        pTmrHw[timerId].InterruptClear = 0x1;
+}
+/****************************************************************************/
+/**
+*  @brief   Gets the interrupt status
+*
+*  This function returns timer interrupt status
+*
+*  @return   Interrupt status
+*/
+/****************************************************************************/
+tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+) {
+        if (pTmrHw[timerId].InterruptStatus) {
+                return tmrHw_INTERRUPT_STATUS_SET;
+        } else {
+                return tmrHw_INTERRUPT_STATUS_UNSET;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Indentifies a timer causing interrupt
+*
+*  This functions returns a timer causing interrupt
+*
+*  @return  0xFFFFFFFF   : No timer causing an interrupt
+*           ! 0xFFFFFFFF : timer causing an interrupt
+*  @note
+*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
+*/
+/****************************************************************************/
+tmrHw_ID_t tmrHw_getInterruptSource(void        /*  void */
+) {
+        int i;
+        for (i = 0; i < tmrHw_TIMER_NUM_COUNT; i++) {
+                if (pTmrHw[i].InterruptStatus) {
+                        return i;
+                }
+        }
+        return 0xFFFFFFFF;
+}
+/****************************************************************************/
+/**
+*  @brief   Displays specific timer registers
+*
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
+) {
+        (*fpPrint) ("Displaying register contents \n\n");
+        (*fpPrint) ("Timer %d: Load value              0x%X\n", timerId,
+                    pTmrHw[timerId].LoadValue);
+        (*fpPrint) ("Timer %d: Background load value   0x%X\n", timerId,
+                    pTmrHw[timerId].BackgroundLoad);
+        (*fpPrint) ("Timer %d: Control                 0x%X\n", timerId,
+                    pTmrHw[timerId].Control);
+        (*fpPrint) ("Timer %d: Interrupt clear         0x%X\n", timerId,
+                    pTmrHw[timerId].InterruptClear);
+        (*fpPrint) ("Timer %d: Interrupt raw interrupt 0x%X\n", timerId,
+                    pTmrHw[timerId].RawInterruptStatus);
+        (*fpPrint) ("Timer %d: Interrupt status        0x%X\n", timerId,
+                    pTmrHw[timerId].InterruptStatus);
+}
+/****************************************************************************/
+/**
+*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
+*
+*  @return   N/A
+*/
+/****************************************************************************/
+void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                  unsigned long usecs /*  [ IN ] usec to delay */
+) {
+        tmrHw_RATE_t usec_tick_rate;
+        tmrHw_COUNT_t start_time;
+        tmrHw_COUNT_t delta_time;
+        start_time = tmrHw_GetCurrentCount(timerId);
+        usec_tick_rate = tmrHw_divide(tmrHw_getCountRate(timerId), 1000000);
+        delta_time = usecs * usec_tick_rate;
+        /* Busy wait */
+        while (delta_time > (tmrHw_GetCurrentCount(timerId) - start_time))
+                ;
+}
+/****************************************************************************/
+/**
+*  @brief   Local Divide function
+*
+*  This function does the divide
+*
+*  @return divide value
+*
+*/
+/****************************************************************************/
+static int tmrHw_divide(int num, int denom)
+{
+        int r;
+        int t = 1;
+        /* Shift denom and t up to the largest value to optimize algorithm */
+        /* t contains the units of each divide */
+        while ((denom & 0x40000000) == 0) {     /* fails if denom=0 */
+                denom = denom << 1;
+                t = t << 1;
+        }
+        /* Intialize the result */
+        r = 0;
+        do {
+                /* Determine if there exists a positive remainder */
+                if ((num - denom) >= 0) {
+                        /* Accumlate t to the result and calculate a new remainder */
+                        num = num - denom;
+                        r = r + t;
+                }
+                /* Continue to shift denom and shift t down to 0 */
+                denom = denom >> 1;
+                t = t >> 1;
+        } while (t != 0);
+        return r;
+}
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
new file mode 100644
index 000000000000..7b20fccb9d4e
--- /dev/null
+++ b/arch/arm/mach-bcmring/dma.c
@@ -0,0 +1,2321 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*   @file   dma.c
+*
+*   @brief  Implements the DMA interface.
+*/
+/****************************************************************************/
+/* ---- Include Files ---------------------------------------------------- */
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/irqreturn.h>
+#include <linux/proc_fs.h>
+#include <mach/timer.h>
+#include <linux/mm.h>
+#include <linux/pfn.h>
+#include <asm/atomic.h>
+#include <mach/dma.h>
+/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
+/* especially since dc4 doesn't use kmalloc'd memory. */
+#define ALLOW_MAP_OF_KMALLOC_MEMORY 0
+/* ---- Public Variables ------------------------------------------------- */
+/* ---- Private Constants and Types -------------------------------------- */
+#define MAKE_HANDLE(controllerIdx, channelIdx)    (((controllerIdx) << 4) | (channelIdx))
+#define CONTROLLER_FROM_HANDLE(handle)    (((handle) >> 4) & 0x0f)
+#define CHANNEL_FROM_HANDLE(handle)       ((handle) & 0x0f)
+#define DMA_MAP_DEBUG   0
+#if DMA_MAP_DEBUG
+#   define  DMA_MAP_PRINT(fmt, args...)   printk("%s: " fmt, __func__,  ## args)
+#else
+#   define  DMA_MAP_PRINT(fmt, args...)
+#endif
+/* ---- Private Variables ------------------------------------------------ */
+static DMA_Global_t gDMA;
+static struct proc_dir_entry *gDmaDir;
+static atomic_t gDmaStatMemTypeKmalloc = ATOMIC_INIT(0);
+static atomic_t gDmaStatMemTypeVmalloc = ATOMIC_INIT(0);
+static atomic_t gDmaStatMemTypeUser = ATOMIC_INIT(0);
+static atomic_t gDmaStatMemTypeCoherent = ATOMIC_INIT(0);
+#include "dma_device.c"
+/* ---- Private Function Prototypes -------------------------------------- */
+/* ---- Functions  ------------------------------------------------------- */
+/****************************************************************************/
+/**
+*   Displays information for /proc/dma/mem-type
+*/
+/****************************************************************************/
+static int dma_proc_read_mem_type(char *buf, char **start, off_t offset,
+                                  int count, int *eof, void *data)
+{
+        int len = 0;
+        len += sprintf(buf + len, "dma_map_mem statistics\n");
+        len +=
+            sprintf(buf + len, "coherent: %d\n",
+                    atomic_read(&gDmaStatMemTypeCoherent));
+        len +=
+            sprintf(buf + len, "kmalloc:  %d\n",
+                    atomic_read(&gDmaStatMemTypeKmalloc));
+        len +=
+            sprintf(buf + len, "vmalloc:  %d\n",
+                    atomic_read(&gDmaStatMemTypeVmalloc));
+        len +=
+            sprintf(buf + len, "user:     %d\n",
+                    atomic_read(&gDmaStatMemTypeUser));
+        return len;
+}
+/****************************************************************************/
+/**
+*   Displays information for /proc/dma/channels
+*/
+/****************************************************************************/
+static int dma_proc_read_channels(char *buf, char **start, off_t offset,
+                                  int count, int *eof, void *data)
+{
+        int controllerIdx;
+        int channelIdx;
+        int limit = count - 200;
+        int len = 0;
+        DMA_Channel_t *channel;
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
+             controllerIdx++) {
+                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
+                     channelIdx++) {
+                        if (len >= limit) {
+                                break;
+                        }
+                        channel =
+                            &gDMA.controller[controllerIdx].channel[channelIdx];
+                        len +=
+                            sprintf(buf + len, "%d:%d ", controllerIdx,
+                                    channelIdx);
+                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
+                            0) {
+                                len +=
+                                    sprintf(buf + len, "Dedicated for %s ",
+                                            DMA_gDeviceAttribute[channel->
+                                                                 devType].name);
+                        } else {
+                                len += sprintf(buf + len, "Shared ");
+                        }
+                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) != 0) {
+                                len += sprintf(buf + len, "No ISR ");
+                        }
+                        if ((channel->flags & DMA_CHANNEL_FLAG_LARGE_FIFO) != 0) {
+                                len += sprintf(buf + len, "Fifo: 128 ");
+                        } else {
+                                len += sprintf(buf + len, "Fifo: 64  ");
+                        }
+                        if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
+                                len +=
+                                    sprintf(buf + len, "InUse by %s",
+                                            DMA_gDeviceAttribute[channel->
+                                                                 devType].name);
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                                len +=
+                                    sprintf(buf + len, " (%s:%d)",
+                                            channel->fileName,
+                                            channel->lineNum);
+#endif
+                        } else {
+                                len += sprintf(buf + len, "Avail ");
+                        }
+                        if (channel->lastDevType != DMA_DEVICE_NONE) {
+                                len +=
+                                    sprintf(buf + len, "Last use: %s ",
+                                            DMA_gDeviceAttribute[channel->
+                                                                 lastDevType].
+                                            name);
+                        }
+                        len += sprintf(buf + len, "\n");
+                }
+        }
+        up(&gDMA.lock);
+        *eof = 1;
+        return len;
+}
+/****************************************************************************/
+/**
+*   Displays information for /proc/dma/devices
+*/
+/****************************************************************************/
+static int dma_proc_read_devices(char *buf, char **start, off_t offset,
+                                 int count, int *eof, void *data)
+{
+        int limit = count - 200;
+        int len = 0;
+        int devIdx;
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
+                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
+                if (devAttr->name == NULL) {
+                        continue;
+                }
+                if (len >= limit) {
+                        break;
+                }
+                len += sprintf(buf + len, "%-12s ", devAttr->name);
+                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
+                        len +=
+                            sprintf(buf + len, "Dedicated %d:%d ",
+                                    devAttr->dedicatedController,
+                                    devAttr->dedicatedChannel);
+                } else {
+                        len += sprintf(buf + len, "Shared DMA:");
+                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA0) != 0) {
+                                len += sprintf(buf + len, "0");
+                        }
+                        if ((devAttr->flags & DMA_DEVICE_FLAG_ON_DMA1) != 0) {
+                                len += sprintf(buf + len, "1");
+                        }
+                        len += sprintf(buf + len, " ");
+                }
+                if ((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0) {
+                        len += sprintf(buf + len, "NoISR ");
+                }
+                if ((devAttr->flags & DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO) != 0) {
+                        len += sprintf(buf + len, "Allow-128 ");
+                }
+                len +=
+                    sprintf(buf + len,
+                            "Xfer #: %Lu Ticks: %Lu Bytes: %Lu DescLen: %u\n",
+                            devAttr->numTransfers, devAttr->transferTicks,
+                            devAttr->transferBytes,
+                            devAttr->ring.bytesAllocated);
+        }
+        up(&gDMA.lock);
+        *eof = 1;
+        return len;
+}
+/****************************************************************************/
+/**
+*   Determines if a DMA_Device_t is "valid".
+*
+*   @return
+*       TRUE        - dma device is valid
+*       FALSE       - dma device isn't valid
+*/
+/****************************************************************************/
+static inline int IsDeviceValid(DMA_Device_t device)
+{
+        return (device >= 0) && (device < DMA_NUM_DEVICE_ENTRIES);
+}
+/****************************************************************************/
+/**
+*   Translates a DMA handle into a pointer to a channel.
+*
+*   @return
+*       non-NULL    - pointer to DMA_Channel_t
+*       NULL        - DMA Handle was invalid
+*/
+/****************************************************************************/
+static inline DMA_Channel_t *HandleToChannel(DMA_Handle_t handle)
+{
+        int controllerIdx;
+        int channelIdx;
+        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
+        channelIdx = CHANNEL_FROM_HANDLE(handle);
+        if ((controllerIdx > DMA_NUM_CONTROLLERS)
+            || (channelIdx > DMA_NUM_CHANNELS)) {
+                return NULL;
+        }
+        return &gDMA.controller[controllerIdx].channel[channelIdx];
+}
+/****************************************************************************/
+/**
+*   Interrupt handler which is called to process DMA interrupts.
+*/
+/****************************************************************************/
+static irqreturn_t dma_interrupt_handler(int irq, void *dev_id)
+{
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int irqStatus;
+        channel = (DMA_Channel_t *) dev_id;
+        /* Figure out why we were called, and knock down the interrupt */
+        irqStatus = dmacHw_getInterruptStatus(channel->dmacHwHandle);
+        dmacHw_clearInterrupt(channel->dmacHwHandle);
+        if ((channel->devType < 0)
+            || (channel->devType > DMA_NUM_DEVICE_ENTRIES)) {
+                printk(KERN_ERR "dma_interrupt_handler: Invalid devType: %d\n",
+                       channel->devType);
+                return IRQ_NONE;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        /* Update stats */
+        if ((irqStatus & dmacHw_INTERRUPT_STATUS_TRANS) != 0) {
+                devAttr->transferTicks +=
+                    (timer_get_tick_count() - devAttr->transferStartTime);
+        }
+        if ((irqStatus & dmacHw_INTERRUPT_STATUS_ERROR) != 0) {
+                printk(KERN_ERR
+                       "dma_interrupt_handler: devType :%d DMA error (%s)\n",
+                       channel->devType, devAttr->name);
+        } else {
+                devAttr->numTransfers++;
+                devAttr->transferBytes += devAttr->numBytes;
+        }
+        /* Call any installed handler */
+        if (devAttr->devHandler != NULL) {
+                devAttr->devHandler(channel->devType, irqStatus,
+                                    devAttr->userData);
+        }
+        return IRQ_HANDLED;
+}
+/****************************************************************************/
+/**
+*   Allocates memory to hold a descriptor ring. The descriptor ring then
+*   needs to be populated by making one or more calls to
+*   dna_add_descriptors.
+*
+*   The returned descriptor ring will be automatically initialized.
+*
+*   @return
+*       0           Descriptor ring was allocated successfully
+*       -EINVAL     Invalid parameters passed in
+*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
+*/
+/****************************************************************************/
+int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
+                              int numDescriptors        /* Number of descriptors that need to be allocated. */
+    ) {
+        size_t bytesToAlloc = dmacHw_descriptorLen(numDescriptors);
+        if ((ring == NULL) || (numDescriptors <= 0)) {
+                return -EINVAL;
+        }
+        ring->physAddr = 0;
+        ring->descriptorsAllocated = 0;
+        ring->bytesAllocated = 0;
+        ring->virtAddr = dma_alloc_writecombine(NULL,
+                                                     bytesToAlloc,
+                                                     &ring->physAddr,
+                                                     GFP_KERNEL);
+        if (ring->virtAddr == NULL) {
+                return -ENOMEM;
+        }
+        ring->bytesAllocated = bytesToAlloc;
+        ring->descriptorsAllocated = numDescriptors;
+        return dma_init_descriptor_ring(ring, numDescriptors);
+}
+EXPORT_SYMBOL(dma_alloc_descriptor_ring);
+/****************************************************************************/
+/**
+*   Releases the memory which was previously allocated for a descriptor ring.
+*/
+/****************************************************************************/
+void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
+    ) {
+        if (ring->virtAddr != NULL) {
+                dma_free_writecombine(NULL,
+                                      ring->bytesAllocated,
+                                      ring->virtAddr, ring->physAddr);
+        }
+        ring->bytesAllocated = 0;
+        ring->descriptorsAllocated = 0;
+        ring->virtAddr = NULL;
+        ring->physAddr = 0;
+}
+EXPORT_SYMBOL(dma_free_descriptor_ring);
+/****************************************************************************/
+/**
+*   Initializes a descriptor ring, so that descriptors can be added to it.
+*   Once a descriptor ring has been allocated, it may be reinitialized for
+*   use with additional/different regions of memory.
+*
+*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
+*   initialize the ring with a smaller number of descriptors. The amount
+*   of memory allocated for the descriptor ring will not be reduced, and
+*   the descriptor ring may be reinitialized later
+*
+*   @return
+*       0           Descriptor ring was initialized successfully
+*       -ENOMEM     The descriptor which was passed in has insufficient space
+*                   to hold the desired number of descriptors.
+*/
+/****************************************************************************/
+int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
+                             int numDescriptors /* Number of descriptors to initialize. */
+    ) {
+        if (ring->virtAddr == NULL) {
+                return -EINVAL;
+        }
+        if (dmacHw_initDescriptor(ring->virtAddr,
+                                  ring->physAddr,
+                                  ring->bytesAllocated, numDescriptors) < 0) {
+                printk(KERN_ERR
+                       "dma_init_descriptor_ring: dmacHw_initDescriptor failed\n");
+                return -ENOMEM;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(dma_init_descriptor_ring);
+/****************************************************************************/
+/**
+*   Determines the number of descriptors which would be required for a
+*   transfer of the indicated memory region.
+*
+*   This function also needs to know which DMA device this transfer will
+*   be destined for, so that the appropriate DMA configuration can be retrieved.
+*   DMA parameters such as transfer width, and whether this is a memory-to-memory
+*   or memory-to-peripheral, etc can all affect the actual number of descriptors
+*   required.
+*
+*   @return
+*       > 0     Returns the number of descriptors required for the indicated transfer
+*       -ENODEV - Device handed in is invalid.
+*       -EINVAL Invalid parameters
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
+                                   dma_addr_t srcData,  /* Place to get data to write to device */
+                                   dma_addr_t dstData,  /* Pointer to device data address */
+                                   size_t numBytes      /* Number of bytes to transfer to the device */
+    ) {
+        int numDescriptors;
+        DMA_DeviceAttribute_t *devAttr;
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
+                                                              (void *)srcData,
+                                                              (void *)dstData,
+                                                              numBytes);
+        if (numDescriptors < 0) {
+                printk(KERN_ERR
+                       "dma_calculate_descriptor_count: dmacHw_calculateDescriptorCount failed\n");
+                return -EINVAL;
+        }
+        return numDescriptors;
+}
+EXPORT_SYMBOL(dma_calculate_descriptor_count);
+/****************************************************************************/
+/**
+*   Adds a region of memory to the descriptor ring. Note that it may take
+*   multiple descriptors for each region of memory. It is the callers
+*   responsibility to allocate a sufficiently large descriptor ring.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -ENODEV Device handed in is invalid.
+*       -EINVAL Invalid parameters
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
+                        DMA_Device_t device,    /* DMA Device that descriptors are for */
+                        dma_addr_t srcData,     /* Place to get data (memory or device) */
+                        dma_addr_t dstData,     /* Place to put data (memory or device) */
+                        size_t numBytes /* Number of bytes to transfer to the device */
+    ) {
+        int rc;
+        DMA_DeviceAttribute_t *devAttr;
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+        rc = dmacHw_setDataDescriptor(&devAttr->config,
+                                      ring->virtAddr,
+                                      (void *)srcData,
+                                      (void *)dstData, numBytes);
+        if (rc < 0) {
+                printk(KERN_ERR
+                       "dma_add_descriptors: dmacHw_setDataDescriptor failed with code: %d\n",
+                       rc);
+                return -ENOMEM;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(dma_add_descriptors);
+/****************************************************************************/
+/**
+*   Sets the descriptor ring associated with a device.
+*
+*   Once set, the descriptor ring will be associated with the device, even
+*   across channel request/free calls. Passing in a NULL descriptor ring
+*   will release any descriptor ring currently associated with the device.
+*
+*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
+*         the descriptor ring may be released and reallocated.
+*
+*   Note: This function will release the descriptor memory for any current
+*         descriptor ring associated with this device.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -ENODEV Device handed in is invalid.
+*/
+/****************************************************************************/
+int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+        /* Free the previously allocated descriptor ring */
+        dma_free_descriptor_ring(&devAttr->ring);
+        if (ring != NULL) {
+                /* Copy in the new one */
+                devAttr->ring = *ring;
+        }
+        /* Set things up so that if dma_transfer is called then this descriptor */
+        /* ring will get freed. */
+        devAttr->prevSrcData = 0;
+        devAttr->prevDstData = 0;
+        devAttr->prevNumBytes = 0;
+        return 0;
+}
+EXPORT_SYMBOL(dma_set_device_descriptor_ring);
+/****************************************************************************/
+/**
+*   Retrieves the descriptor ring associated with a device.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -ENODEV Device handed in is invalid.
+*/
+/****************************************************************************/
+int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+        memset(ring, 0, sizeof(*ring));
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+        *ring = devAttr->ring;
+        return 0;
+}
+EXPORT_SYMBOL(dma_get_device_descriptor_ring);
+/****************************************************************************/
+/**
+*   Configures a DMA channel.
+*
+*   @return
+*       >= 0    - Initialization was successfull.
+*
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+static int ConfigChannel(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int controllerIdx;
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        controllerIdx = CONTROLLER_FROM_HANDLE(handle);
+        if ((devAttr->flags & DMA_DEVICE_FLAG_PORT_PER_DMAC) != 0) {
+                if (devAttr->config.transferType ==
+                    dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL) {
+                        devAttr->config.dstPeripheralPort =
+                            devAttr->dmacPort[controllerIdx];
+                } else if (devAttr->config.transferType ==
+                           dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) {
+                        devAttr->config.srcPeripheralPort =
+                            devAttr->dmacPort[controllerIdx];
+                }
+        }
+        if (dmacHw_configChannel(channel->dmacHwHandle, &devAttr->config) != 0) {
+                printk(KERN_ERR "ConfigChannel: dmacHw_configChannel failed\n");
+                return -EIO;
+        }
+        return 0;
+}
+/****************************************************************************/
+/**
+*   Intializes all of the data structures associated with the DMA.
+*   @return
+*       >= 0    - Initialization was successfull.
+*
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+int dma_init(void)
+{
+        int rc = 0;
+        int controllerIdx;
+        int channelIdx;
+        DMA_Device_t devIdx;
+        DMA_Channel_t *channel;
+        DMA_Handle_t dedicatedHandle;
+        memset(&gDMA, 0, sizeof(gDMA));
+        init_MUTEX_LOCKED(&gDMA.lock);
+        init_waitqueue_head(&gDMA.freeChannelQ);
+        /* Initialize the Hardware */
+        dmacHw_initDma();
+        /* Start off by marking all of the DMA channels as shared. */
+        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
+             controllerIdx++) {
+                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
+                     channelIdx++) {
+                        channel =
+                            &gDMA.controller[controllerIdx].channel[channelIdx];
+                        channel->flags = 0;
+                        channel->devType = DMA_DEVICE_NONE;
+                        channel->lastDevType = DMA_DEVICE_NONE;
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                        channel->fileName = "";
+                        channel->lineNum = 0;
+#endif
+                        channel->dmacHwHandle =
+                            dmacHw_getChannelHandle(dmacHw_MAKE_CHANNEL_ID
+                                                    (controllerIdx,
+                                                     channelIdx));
+                        dmacHw_initChannel(channel->dmacHwHandle);
+                }
+        }
+        /* Record any special attributes that channels may have */
+        gDMA.controller[0].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+        gDMA.controller[0].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+        gDMA.controller[1].channel[0].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+        gDMA.controller[1].channel[1].flags |= DMA_CHANNEL_FLAG_LARGE_FIFO;
+        /* Now walk through and record the dedicated channels. */
+        for (devIdx = 0; devIdx < DMA_NUM_DEVICE_ENTRIES; devIdx++) {
+                DMA_DeviceAttribute_t *devAttr = &DMA_gDeviceAttribute[devIdx];
+                if (((devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) != 0)
+                    && ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0)) {
+                        printk(KERN_ERR
+                               "DMA Device: %s Can only request NO_ISR for dedicated devices\n",
+                               devAttr->name);
+                        rc = -EINVAL;
+                        goto out;
+                }
+                if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
+                        /* This is a dedicated device. Mark the channel as being reserved. */
+                        if (devAttr->dedicatedController >= DMA_NUM_CONTROLLERS) {
+                                printk(KERN_ERR
+                                       "DMA Device: %s DMA Controller %d is out of range\n",
+                                       devAttr->name,
+                                       devAttr->dedicatedController);
+                                rc = -EINVAL;
+                                goto out;
+                        }
+                        if (devAttr->dedicatedChannel >= DMA_NUM_CHANNELS) {
+                                printk(KERN_ERR
+                                       "DMA Device: %s DMA Channel %d is out of range\n",
+                                       devAttr->name,
+                                       devAttr->dedicatedChannel);
+                                rc = -EINVAL;
+                                goto out;
+                        }
+                        dedicatedHandle =
+                            MAKE_HANDLE(devAttr->dedicatedController,
+                                        devAttr->dedicatedChannel);
+                        channel = HandleToChannel(dedicatedHandle);
+                        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) !=
+                            0) {
+                                printk
+                                    ("DMA Device: %s attempting to use same DMA Controller:Channel (%d:%d) as %s\n",
+                                     devAttr->name,
+                                     devAttr->dedicatedController,
+                                     devAttr->dedicatedChannel,
+                                     DMA_gDeviceAttribute[channel->devType].
+                                     name);
+                                rc = -EBUSY;
+                                goto out;
+                        }
+                        channel->flags |= DMA_CHANNEL_FLAG_IS_DEDICATED;
+                        channel->devType = devIdx;
+                        if (devAttr->flags & DMA_DEVICE_FLAG_NO_ISR) {
+                                channel->flags |= DMA_CHANNEL_FLAG_NO_ISR;
+                        }
+                        /* For dedicated channels, we can go ahead and configure the DMA channel now */
+                        /* as well. */
+                        ConfigChannel(dedicatedHandle);
+                }
+        }
+        /* Go through and register the interrupt handlers */
+        for (controllerIdx = 0; controllerIdx < DMA_NUM_CONTROLLERS;
+             controllerIdx++) {
+                for (channelIdx = 0; channelIdx < DMA_NUM_CHANNELS;
+                     channelIdx++) {
+                        channel =
+                            &gDMA.controller[controllerIdx].channel[channelIdx];
+                        if ((channel->flags & DMA_CHANNEL_FLAG_NO_ISR) == 0) {
+                                snprintf(channel->name, sizeof(channel->name),
+                                         "dma %d:%d %s", controllerIdx,
+                                         channelIdx,
+                                         channel->devType ==
+                                         DMA_DEVICE_NONE ? "" :
+                                         DMA_gDeviceAttribute[channel->devType].
+                                         name);
+                                rc =
+                                     request_irq(IRQ_DMA0C0 +
+                                                 (controllerIdx *
+                                                  DMA_NUM_CHANNELS) +
+                                                 channelIdx,
+                                                 dma_interrupt_handler,
+                                                 IRQF_DISABLED, channel->name,
+                                                 channel);
+                                if (rc != 0) {
+                                        printk(KERN_ERR
+                                               "request_irq for IRQ_DMA%dC%d failed\n",
+                                               controllerIdx, channelIdx);
+                                }
+                        }
+                }
+        }
+        /* Create /proc/dma/channels and /proc/dma/devices */
+        gDmaDir = create_proc_entry("dma", S_IFDIR | S_IRUGO | S_IXUGO, NULL);
+        if (gDmaDir == NULL) {
+                printk(KERN_ERR "Unable to create /proc/dma\n");
+        } else {
+                create_proc_read_entry("channels", 0, gDmaDir,
+                                       dma_proc_read_channels, NULL);
+                create_proc_read_entry("devices", 0, gDmaDir,
+                                       dma_proc_read_devices, NULL);
+                create_proc_read_entry("mem-type", 0, gDmaDir,
+                                       dma_proc_read_mem_type, NULL);
+        }
+out:
+        up(&gDMA.lock);
+        return rc;
+}
+/****************************************************************************/
+/**
+*   Reserves a channel for use with @a dev. If the device is setup to use
+*   a shared channel, then this function will block until a free channel
+*   becomes available.
+*
+*   @return
+*       >= 0    - A valid DMA Handle.
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+#if (DMA_DEBUG_TRACK_RESERVATION)
+DMA_Handle_t dma_request_channel_dbg
+    (DMA_Device_t dev, const char *fileName, int lineNum)
+#else
+DMA_Handle_t dma_request_channel(DMA_Device_t dev)
+#endif
+{
+        DMA_Handle_t handle;
+        DMA_DeviceAttribute_t *devAttr;
+        DMA_Channel_t *channel;
+        int controllerIdx;
+        int controllerIdx2;
+        int channelIdx;
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+        if ((dev < 0) || (dev >= DMA_NUM_DEVICE_ENTRIES)) {
+                handle = -ENODEV;
+                goto out;
+        }
+        devAttr = &DMA_gDeviceAttribute[dev];
+#if (DMA_DEBUG_TRACK_RESERVATION)
+        {
+                char *s;
+                s = strrchr(fileName, '/');
+                if (s != NULL) {
+                        fileName = s + 1;
+                }
+        }
+#endif
+        if ((devAttr->flags & DMA_DEVICE_FLAG_IN_USE) != 0) {
+                /* This device has already been requested and not been freed */
+                printk(KERN_ERR "%s: device %s is already requested\n",
+                       __func__, devAttr->name);
+                handle = -EBUSY;
+                goto out;
+        }
+        if ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) != 0) {
+                /* This device has a dedicated channel. */
+                channel =
+                    &gDMA.controller[devAttr->dedicatedController].
+                    channel[devAttr->dedicatedChannel];
+                if ((channel->flags & DMA_CHANNEL_FLAG_IN_USE) != 0) {
+                        handle = -EBUSY;
+                        goto out;
+                }
+                channel->flags |= DMA_CHANNEL_FLAG_IN_USE;
+                devAttr->flags |= DMA_DEVICE_FLAG_IN_USE;
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                channel->fileName = fileName;
+                channel->lineNum = lineNum;
+#endif
+                handle =
+                    MAKE_HANDLE(devAttr->dedicatedController,
+                                devAttr->dedicatedChannel);
+                goto out;
+        }
+        /* This device needs to use one of the shared channels. */
+        handle = DMA_INVALID_HANDLE;
+        while (handle == DMA_INVALID_HANDLE) {
+                /* Scan through the shared channels and see if one is available */
+                for (controllerIdx2 = 0; controllerIdx2 < DMA_NUM_CONTROLLERS;
+                     controllerIdx2++) {
+                        /* Check to see if we should try on controller 1 first. */
+                        controllerIdx = controllerIdx2;
+                        if ((devAttr->
+                             flags & DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST) != 0) {
+                                controllerIdx = 1 - controllerIdx;
+                        }
+                        /* See if the device is available on the controller being tested */
+                        if ((devAttr->
+                             flags & (DMA_DEVICE_FLAG_ON_DMA0 << controllerIdx))
+                            != 0) {
+                                for (channelIdx = 0;
+                                     channelIdx < DMA_NUM_CHANNELS;
+                                     channelIdx++) {
+                                        channel =
+                                            &gDMA.controller[controllerIdx].
+                                            channel[channelIdx];
+                                        if (((channel->
+                                              flags &
+                                              DMA_CHANNEL_FLAG_IS_DEDICATED) ==
+                                             0)
+                                            &&
+                                            ((channel->
+                                              flags & DMA_CHANNEL_FLAG_IN_USE)
+                                             == 0)) {
+                                                if (((channel->
+                                                      flags &
+                                                      DMA_CHANNEL_FLAG_LARGE_FIFO)
+                                                     != 0)
+                                                    &&
+                                                    ((devAttr->
+                                                      flags &
+                                                      DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO)
+                                                     == 0)) {
+                                                        /* This channel is a large fifo - don't tie it up */
+                                                        /* with devices that we don't want using it. */
+                                                        continue;
+                                                }
+                                                channel->flags |=
+                                                    DMA_CHANNEL_FLAG_IN_USE;
+                                                channel->devType = dev;
+                                                devAttr->flags |=
+                                                    DMA_DEVICE_FLAG_IN_USE;
+#if (DMA_DEBUG_TRACK_RESERVATION)
+                                                channel->fileName = fileName;
+                                                channel->lineNum = lineNum;
+#endif
+                                                handle =
+                                                    MAKE_HANDLE(controllerIdx,
+                                                                channelIdx);
+                                                /* Now that we've reserved the channel - we can go ahead and configure it */
+                                                if (ConfigChannel(handle) != 0) {
+                                                        handle = -EIO;
+                                                        printk(KERN_ERR
+                                                               "dma_request_channel: ConfigChannel failed\n");
+                                                }
+                                                goto out;
+                                        }
+                                }
+                        }
+                }
+                /* No channels are currently available. Let's wait for one to free up. */
+                {
+                        DEFINE_WAIT(wait);
+                        prepare_to_wait(&gDMA.freeChannelQ, &wait,
+                                        TASK_INTERRUPTIBLE);
+                        up(&gDMA.lock);
+                        schedule();
+                        finish_wait(&gDMA.freeChannelQ, &wait);
+                        if (signal_pending(current)) {
+                                /* We don't currently hold gDMA.lock, so we return directly */
+                                return -ERESTARTSYS;
+                        }
+                }
+                if (down_interruptible(&gDMA.lock)) {
+                        return -ERESTARTSYS;
+                }
+        }
+out:
+        up(&gDMA.lock);
+        return handle;
+}
+/* Create both _dbg and non _dbg functions for modules. */
+#if (DMA_DEBUG_TRACK_RESERVATION)
+#undef dma_request_channel
+DMA_Handle_t dma_request_channel(DMA_Device_t dev)
+{
+        return dma_request_channel_dbg(dev, __FILE__, __LINE__);
+}
+EXPORT_SYMBOL(dma_request_channel_dbg);
+#endif
+EXPORT_SYMBOL(dma_request_channel);
+/****************************************************************************/
+/**
+*   Frees a previously allocated DMA Handle.
+*/
+/****************************************************************************/
+int dma_free_channel(DMA_Handle_t handle        /* DMA handle. */
+    ) {
+        int rc = 0;
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        if (down_interruptible(&gDMA.lock) < 0) {
+                return -ERESTARTSYS;
+        }
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                rc = -EINVAL;
+                goto out;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        if ((channel->flags & DMA_CHANNEL_FLAG_IS_DEDICATED) == 0) {
+                channel->lastDevType = channel->devType;
+                channel->devType = DMA_DEVICE_NONE;
+        }
+        channel->flags &= ~DMA_CHANNEL_FLAG_IN_USE;
+        devAttr->flags &= ~DMA_DEVICE_FLAG_IN_USE;
+out:
+        up(&gDMA.lock);
+        wake_up_interruptible(&gDMA.freeChannelQ);
+        return rc;
+}
+EXPORT_SYMBOL(dma_free_channel);
+/****************************************************************************/
+/**
+*   Determines if a given device has been configured as using a shared
+*   channel.
+*
+*   @return
+*       0           Device uses a dedicated channel
+*       > zero      Device uses a shared channel
+*       < zero      Error code
+*/
+/****************************************************************************/
+int dma_device_is_channel_shared(DMA_Device_t device    /* Device to check. */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+        if (!IsDeviceValid(device)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[device];
+        return ((devAttr->flags & DMA_DEVICE_FLAG_IS_DEDICATED) == 0);
+}
+EXPORT_SYMBOL(dma_device_is_channel_shared);
+/****************************************************************************/
+/**
+*   Allocates buffers for the descriptors. This is normally done automatically
+*   but needs to be done explicitly when initiating a dma from interrupt
+*   context.
+*
+*   @return
+*       0       Descriptors were allocated successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
+                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
+                          dma_addr_t srcData,   /* Place to get data to write to device */
+                          dma_addr_t dstData,   /* Pointer to device data address */
+                          size_t numBytes       /* Number of bytes to transfer to the device */
+    ) {
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int numDescriptors;
+        size_t ringBytesRequired;
+        int rc = 0;
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        if (devAttr->config.transferType != transferType) {
+                return -EINVAL;
+        }
+        /* Figure out how many descriptors we need. */
+        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
+        /*        srcData, dstData, numBytes); */
+        numDescriptors = dmacHw_calculateDescriptorCount(&devAttr->config,
+                                                              (void *)srcData,
+                                                              (void *)dstData,
+                                                              numBytes);
+        if (numDescriptors < 0) {
+                printk(KERN_ERR "%s: dmacHw_calculateDescriptorCount failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
+        /* a new one. */
+        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
+        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
+        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
+                /* Make sure that this code path is never taken from interrupt context. */
+                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
+                /* allocation needs to have already been done. */
+                might_sleep();
+                /* Free the old descriptor ring and allocate a new one. */
+                dma_free_descriptor_ring(&devAttr->ring);
+                /* And allocate a new one. */
+                rc =
+                     dma_alloc_descriptor_ring(&devAttr->ring,
+                                               numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
+                               __func__, numDescriptors);
+                        return rc;
+                }
+                /* Setup the descriptor for this transfer */
+                if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
+                                          devAttr->ring.physAddr,
+                                          devAttr->ring.bytesAllocated,
+                                          numDescriptors) < 0) {
+                        printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n",
+                               __func__);
+                        return -EINVAL;
+                }
+        } else {
+                /* We've already got enough ring buffer allocated. All we need to do is reset */
+                /* any control information, just in case the previous DMA was stopped. */
+                dmacHw_resetDescriptorControl(devAttr->ring.virtAddr);
+        }
+        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
+        /* as last time, then we don't need to call setDataDescriptor again. */
+        if (dmacHw_setDataDescriptor(&devAttr->config,
+                                     devAttr->ring.virtAddr,
+                                     (void *)srcData,
+                                     (void *)dstData, numBytes) < 0) {
+                printk(KERN_ERR "%s: dmacHw_setDataDescriptor failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+        /* Remember the critical information for this transfer so that we can eliminate */
+        /* another call to dma_alloc_descriptors if the caller reuses the same buffers */
+        devAttr->prevSrcData = srcData;
+        devAttr->prevDstData = dstData;
+        devAttr->prevNumBytes = numBytes;
+        return 0;
+}
+EXPORT_SYMBOL(dma_alloc_descriptors);
+/****************************************************************************/
+/**
+*   Allocates and sets up descriptors for a double buffered circular buffer.
+*
+*   This is primarily intended to be used for things like the ingress samples
+*   from a microphone.
+*
+*   @return
+*       > 0     Number of descriptors actually allocated.
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
+                                     dma_addr_t srcData,        /* Physical address of source data */
+                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
+                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
+                                     size_t numBytes    /* Number of bytes in each destination buffer */
+    ) {
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int numDst1Descriptors;
+        int numDst2Descriptors;
+        int numDescriptors;
+        size_t ringBytesRequired;
+        int rc = 0;
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        /* Figure out how many descriptors we need. */
+        /* printk("srcData: 0x%08x dstData: 0x%08x, numBytes: %d\n", */
+        /*        srcData, dstData, numBytes); */
+        numDst1Descriptors =
+             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
+                                             (void *)dstData1, numBytes);
+        if (numDst1Descriptors < 0) {
+                return -EINVAL;
+        }
+        numDst2Descriptors =
+             dmacHw_calculateDescriptorCount(&devAttr->config, (void *)srcData,
+                                             (void *)dstData2, numBytes);
+        if (numDst2Descriptors < 0) {
+                return -EINVAL;
+        }
+        numDescriptors = numDst1Descriptors + numDst2Descriptors;
+        /* printk("numDescriptors: %d\n", numDescriptors); */
+        /* Check to see if we can reuse the existing descriptor ring, or if we need to allocate */
+        /* a new one. */
+        ringBytesRequired = dmacHw_descriptorLen(numDescriptors);
+        /* printk("ringBytesRequired: %d\n", ringBytesRequired); */
+        if (ringBytesRequired > devAttr->ring.bytesAllocated) {
+                /* Make sure that this code path is never taken from interrupt context. */
+                /* It's OK for an interrupt to initiate a DMA transfer, but the descriptor */
+                /* allocation needs to have already been done. */
+                might_sleep();
+                /* Free the old descriptor ring and allocate a new one. */
+                dma_free_descriptor_ring(&devAttr->ring);
+                /* And allocate a new one. */
+                rc =
+                     dma_alloc_descriptor_ring(&devAttr->ring,
+                                               numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_alloc_descriptor_ring(%d) failed\n",
+                               __func__, ringBytesRequired);
+                        return rc;
+                }
+        }
+        /* Setup the descriptor for this transfer. Since this function is used with */
+        /* CONTINUOUS DMA operations, we need to reinitialize every time, otherwise */
+        /* setDataDescriptor will keep trying to append onto the end. */
+        if (dmacHw_initDescriptor(devAttr->ring.virtAddr,
+                                  devAttr->ring.physAddr,
+                                  devAttr->ring.bytesAllocated,
+                                  numDescriptors) < 0) {
+                printk(KERN_ERR "%s: dmacHw_initDescriptor failed\n", __func__);
+                return -EINVAL;
+        }
+        /* dma_alloc/free both set the prevSrc/DstData to 0. If they happen to be the same */
+        /* as last time, then we don't need to call setDataDescriptor again. */
+        if (dmacHw_setDataDescriptor(&devAttr->config,
+                                     devAttr->ring.virtAddr,
+                                     (void *)srcData,
+                                     (void *)dstData1, numBytes) < 0) {
+                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 1 failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+        if (dmacHw_setDataDescriptor(&devAttr->config,
+                                     devAttr->ring.virtAddr,
+                                     (void *)srcData,
+                                     (void *)dstData2, numBytes) < 0) {
+                printk(KERN_ERR "%s: dmacHw_setDataDescriptor 2 failed\n",
+                       __func__);
+                return -EINVAL;
+        }
+        /* You should use dma_start_transfer rather than dma_transfer_xxx so we don't */
+        /* try to make the 'prev' variables right. */
+        devAttr->prevSrcData = 0;
+        devAttr->prevDstData = 0;
+        devAttr->prevNumBytes = 0;
+        return numDescriptors;
+}
+EXPORT_SYMBOL(dma_alloc_double_dst_descriptors);
+/****************************************************************************/
+/**
+*   Initiates a transfer when the descriptors have already been setup.
+*
+*   This is a special case, and normally, the dma_transfer_xxx functions should
+*   be used.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+int dma_start_transfer(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
+                                devAttr->ring.virtAddr);
+        /* Since we got this far, everything went successfully */
+        return 0;
+}
+EXPORT_SYMBOL(dma_start_transfer);
+/****************************************************************************/
+/**
+*   Stops a previously started DMA transfer.
+*
+*   @return
+*       0       Transfer was stopped successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+int dma_stop_transfer(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        dmacHw_stopTransfer(channel->dmacHwHandle);
+        return 0;
+}
+EXPORT_SYMBOL(dma_stop_transfer);
+/****************************************************************************/
+/**
+*   Waits for a DMA to complete by polling. This function is only intended
+*   to be used for testing. Interrupts should be used for most DMA operations.
+*/
+/****************************************************************************/
+int dma_wait_transfer_done(DMA_Handle_t handle)
+{
+        DMA_Channel_t *channel;
+        dmacHw_TRANSFER_STATUS_e status;
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        while ((status =
+                dmacHw_transferCompleted(channel->dmacHwHandle)) ==
+               dmacHw_TRANSFER_STATUS_BUSY) {
+                ;
+        }
+        if (status == dmacHw_TRANSFER_STATUS_ERROR) {
+                printk(KERN_ERR "%s: DMA transfer failed\n", __func__);
+                return -EIO;
+        }
+        return 0;
+}
+EXPORT_SYMBOL(dma_wait_transfer_done);
+/****************************************************************************/
+/**
+*   Initiates a DMA, allocating the descriptors as required.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
+*/
+/****************************************************************************/
+int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
+                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
+                 dma_addr_t srcData,    /* Place to get data to write to device */
+                 dma_addr_t dstData,    /* Pointer to device data address */
+                 size_t numBytes        /* Number of bytes to transfer to the device */
+    ) {
+        DMA_Channel_t *channel;
+        DMA_DeviceAttribute_t *devAttr;
+        int rc = 0;
+        channel = HandleToChannel(handle);
+        if (channel == NULL) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[channel->devType];
+        if (devAttr->config.transferType != transferType) {
+                return -EINVAL;
+        }
+        /* We keep track of the information about the previous request for this */
+        /* device, and if the attributes match, then we can use the descriptors we setup */
+        /* the last time, and not have to reinitialize everything. */
+        {
+                rc =
+                     dma_alloc_descriptors(handle, transferType, srcData,
+                                           dstData, numBytes);
+                if (rc != 0) {
+                        return rc;
+                }
+        }
+        /* And kick off the transfer */
+        devAttr->numBytes = numBytes;
+        devAttr->transferStartTime = timer_get_tick_count();
+        dmacHw_initiateTransfer(channel->dmacHwHandle, &devAttr->config,
+                                devAttr->ring.virtAddr);
+        /* Since we got this far, everything went successfully */
+        return 0;
+}
+EXPORT_SYMBOL(dma_transfer);
+/****************************************************************************/
+/**
+*   Set the callback function which will be called when a transfer completes.
+*   If a NULL callback function is set, then no callback will occur.
+*
+*   @note   @a devHandler will be called from IRQ context.
+*
+*   @return
+*       0       - Success
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
+                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
+                           void *userData       /* Pointer which will be passed to devHandler. */
+    ) {
+        DMA_DeviceAttribute_t *devAttr;
+        unsigned long flags;
+        if (!IsDeviceValid(dev)) {
+                return -ENODEV;
+        }
+        devAttr = &DMA_gDeviceAttribute[dev];
+        local_irq_save(flags);
+        devAttr->userData = userData;
+        devAttr->devHandler = devHandler;
+        local_irq_restore(flags);
+        return 0;
+}
+EXPORT_SYMBOL(dma_set_device_handler);
+/****************************************************************************/
+/**
+*   Initializes a memory mapping structure
+*/
+/****************************************************************************/
+int dma_init_mem_map(DMA_MemMap_t *memMap)
+{
+        memset(memMap, 0, sizeof(*memMap));
+        init_MUTEX(&memMap->lock);
+        return 0;
+}
+EXPORT_SYMBOL(dma_init_mem_map);
+/****************************************************************************/
+/**
+*   Releases any memory currently being held by a memory mapping structure.
+*/
+/****************************************************************************/
+int dma_term_mem_map(DMA_MemMap_t *memMap)
+{
+        down(&memMap->lock);    /* Just being paranoid */
+        /* Free up any allocated memory */
+        up(&memMap->lock);
+        memset(memMap, 0, sizeof(*memMap));
+        return 0;
+}
+EXPORT_SYMBOL(dma_term_mem_map);
+/****************************************************************************/
+/**
+*   Looks at a memory address and categorizes it.
+*
+*   @return One of the values from the DMA_MemType_t enumeration.
+*/
+/****************************************************************************/
+DMA_MemType_t dma_mem_type(void *addr)
+{
+        unsigned long addrVal = (unsigned long)addr;
+        if (addrVal >= VMALLOC_END) {
+                /* NOTE: DMA virtual memory space starts at 0xFFxxxxxx */
+                /* dma_alloc_xxx pages are physically and virtually contiguous */
+                return DMA_MEM_TYPE_DMA;
+        }
+        /* Technically, we could add one more classification. Addresses between VMALLOC_END */
+        /* and the beginning of the DMA virtual address could be considered to be I/O space. */
+        /* Right now, nobody cares about this particular classification, so we ignore it. */
+        if (is_vmalloc_addr(addr)) {
+                /* Address comes from the vmalloc'd region. Pages are virtually */
+                /* contiguous but NOT physically contiguous */
+                return DMA_MEM_TYPE_VMALLOC;
+        }
+        if (addrVal >= PAGE_OFFSET) {
+                /* PAGE_OFFSET is typically 0xC0000000 */
+                /* kmalloc'd pages are physically contiguous */
+                return DMA_MEM_TYPE_KMALLOC;
+        }
+        return DMA_MEM_TYPE_USER;
+}
+EXPORT_SYMBOL(dma_mem_type);
+/****************************************************************************/
+/**
+*   Looks at a memory address and determines if we support DMA'ing to/from
+*   that type of memory.
+*
+*   @return boolean -
+*               return value != 0 means dma supported
+*               return value == 0 means dma not supported
+*/
+/****************************************************************************/
+int dma_mem_supports_dma(void *addr)
+{
+        DMA_MemType_t memType = dma_mem_type(addr);
+        return (memType == DMA_MEM_TYPE_DMA)
+#if ALLOW_MAP_OF_KMALLOC_MEMORY
+            || (memType == DMA_MEM_TYPE_KMALLOC)
+#endif
+            || (memType == DMA_MEM_TYPE_USER);
+}
+EXPORT_SYMBOL(dma_mem_supports_dma);
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
+                  enum dma_data_direction dir   /* Direction that the mapping will be going */
+    ) {
+        int rc;
+        down(&memMap->lock);
+        DMA_MAP_PRINT("memMap: %p\n", memMap);
+        if (memMap->inUse) {
+                printk(KERN_ERR "%s: memory map %p is already being used\n",
+                       __func__, memMap);
+                rc = -EBUSY;
+                goto out;
+        }
+        memMap->inUse = 1;
+        memMap->dir = dir;
+        memMap->numRegionsUsed = 0;
+        rc = 0;
+out:
+        DMA_MAP_PRINT("returning %d", rc);
+        up(&memMap->lock);
+        return rc;
+}
+EXPORT_SYMBOL(dma_map_start);
+/****************************************************************************/
+/**
+*   Adds a segment of memory to a memory map. Each segment is both
+*   physically and virtually contiguous.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+static int dma_map_add_segment(DMA_MemMap_t *memMap,    /* Stores state information about the map */
+                               DMA_Region_t *region,    /* Region that the segment belongs to */
+                               void *virtAddr,  /* Virtual address of the segment being added */
+                               dma_addr_t physAddr,     /* Physical address of the segment being added */
+                               size_t numBytes  /* Number of bytes of the segment being added */
+    ) {
+        DMA_Segment_t *segment;
+        DMA_MAP_PRINT("memMap:%p va:%p pa:0x%x #:%d\n", memMap, virtAddr,
+                      physAddr, numBytes);
+        /* Sanity check */
+        if (((unsigned long)virtAddr < (unsigned long)region->virtAddr)
+            || (((unsigned long)virtAddr + numBytes)) >
+            ((unsigned long)region->virtAddr + region->numBytes)) {
+                printk(KERN_ERR
+                       "%s: virtAddr %p is outside region @ %p len: %d\n",
+                       __func__, virtAddr, region->virtAddr, region->numBytes);
+                return -EINVAL;
+        }
+        if (region->numSegmentsUsed > 0) {
+                /* Check to see if this segment is physically contiguous with the previous one */
+                segment = &region->segment[region->numSegmentsUsed - 1];
+                if ((segment->physAddr + segment->numBytes) == physAddr) {
+                        /* It is - just add on to the end */
+                        DMA_MAP_PRINT("appending %d bytes to last segment\n",
+                                      numBytes);
+                        segment->numBytes += numBytes;
+                        return 0;
+                }
+        }
+        /* Reallocate to hold more segments, if required. */
+        if (region->numSegmentsUsed >= region->numSegmentsAllocated) {
+                DMA_Segment_t *newSegment;
+                size_t oldSize =
+                    region->numSegmentsAllocated * sizeof(*newSegment);
+                int newAlloc = region->numSegmentsAllocated + 4;
+                size_t newSize = newAlloc * sizeof(*newSegment);
+                newSegment = kmalloc(newSize, GFP_KERNEL);
+                if (newSegment == NULL) {
+                        return -ENOMEM;
+                }
+                memcpy(newSegment, region->segment, oldSize);
+                memset(&((uint8_t *) newSegment)[oldSize], 0,
+                       newSize - oldSize);
+                kfree(region->segment);
+                region->numSegmentsAllocated = newAlloc;
+                region->segment = newSegment;
+        }
+        segment = &region->segment[region->numSegmentsUsed];
+        region->numSegmentsUsed++;
+        segment->virtAddr = virtAddr;
+        segment->physAddr = physAddr;
+        segment->numBytes = numBytes;
+        DMA_MAP_PRINT("returning success\n");
+        return 0;
+}
+/****************************************************************************/
+/**
+*   Adds a region of memory to a memory map. Each region is virtually
+*   contiguous, but not necessarily physically contiguous.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+int dma_map_add_region(DMA_MemMap_t *memMap,    /* Stores state information about the map */
+                       void *mem,       /* Virtual address that we want to get a map of */
+                       size_t numBytes  /* Number of bytes being mapped */
+    ) {
+        unsigned long addr = (unsigned long)mem;
+        unsigned int offset;
+        int rc = 0;
+        DMA_Region_t *region;
+        dma_addr_t physAddr;
+        down(&memMap->lock);
+        DMA_MAP_PRINT("memMap:%p va:%p #:%d\n", memMap, mem, numBytes);
+        if (!memMap->inUse) {
+                printk(KERN_ERR "%s: Make sure you call dma_map_start first\n",
+                       __func__);
+                rc = -EINVAL;
+                goto out;
+        }
+        /* Reallocate to hold more regions. */
+        if (memMap->numRegionsUsed >= memMap->numRegionsAllocated) {
+                DMA_Region_t *newRegion;
+                size_t oldSize =
+                    memMap->numRegionsAllocated * sizeof(*newRegion);
+                int newAlloc = memMap->numRegionsAllocated + 4;
+                size_t newSize = newAlloc * sizeof(*newRegion);
+                newRegion = kmalloc(newSize, GFP_KERNEL);
+                if (newRegion == NULL) {
+                        rc = -ENOMEM;
+                        goto out;
+                }
+                memcpy(newRegion, memMap->region, oldSize);
+                memset(&((uint8_t *) newRegion)[oldSize], 0, newSize - oldSize);
+                kfree(memMap->region);
+                memMap->numRegionsAllocated = newAlloc;
+                memMap->region = newRegion;
+        }
+        region = &memMap->region[memMap->numRegionsUsed];
+        memMap->numRegionsUsed++;
+        offset = addr & ~PAGE_MASK;
+        region->memType = dma_mem_type(mem);
+        region->virtAddr = mem;
+        region->numBytes = numBytes;
+        region->numSegmentsUsed = 0;
+        region->numLockedPages = 0;
+        region->lockedPages = NULL;
+        switch (region->memType) {
+        case DMA_MEM_TYPE_VMALLOC:
+                {
+                        atomic_inc(&gDmaStatMemTypeVmalloc);
+                        /* printk(KERN_ERR "%s: vmalloc'd pages are not supported\n", __func__); */
+                        /* vmalloc'd pages are not physically contiguous */
+                        rc = -EINVAL;
+                        break;
+                }
+        case DMA_MEM_TYPE_KMALLOC:
+                {
+                        atomic_inc(&gDmaStatMemTypeKmalloc);
+                        /* kmalloc'd pages are physically contiguous, so they'll have exactly */
+                        /* one segment */
+#if ALLOW_MAP_OF_KMALLOC_MEMORY
+                        physAddr =
+                            dma_map_single(NULL, mem, numBytes, memMap->dir);
+                        rc = dma_map_add_segment(memMap, region, mem, physAddr,
+                                                 numBytes);
+#else
+                        rc = -EINVAL;
+#endif
+                        break;
+                }
+        case DMA_MEM_TYPE_DMA:
+                {
+                        /* dma_alloc_xxx pages are physically contiguous */
+                        atomic_inc(&gDmaStatMemTypeCoherent);
+                        physAddr = (vmalloc_to_pfn(mem) << PAGE_SHIFT) + offset;
+                        dma_sync_single_for_cpu(NULL, physAddr, numBytes,
+                                                memMap->dir);
+                        rc = dma_map_add_segment(memMap, region, mem, physAddr,
+                                                 numBytes);
+                        break;
+                }
+        case DMA_MEM_TYPE_USER:
+                {
+                        size_t firstPageOffset;
+                        size_t firstPageSize;
+                        struct page **pages;
+                        struct task_struct *userTask;
+                        atomic_inc(&gDmaStatMemTypeUser);
+#if 1
+                        /* If the pages are user pages, then the dma_mem_map_set_user_task function */
+                        /* must have been previously called. */
+                        if (memMap->userTask == NULL) {
+                                printk(KERN_ERR
+                                       "%s: must call dma_mem_map_set_user_task when using user-mode memory\n",
+                                       __func__);
+                                return -EINVAL;
+                        }
+                        /* User pages need to be locked. */
+                        firstPageOffset =
+                            (unsigned long)region->virtAddr & (PAGE_SIZE - 1);
+                        firstPageSize = PAGE_SIZE - firstPageOffset;
+                        region->numLockedPages = (firstPageOffset
+                                                  + region->numBytes +
+                                                  PAGE_SIZE - 1) / PAGE_SIZE;
+                        pages =
+                            kmalloc(region->numLockedPages *
+                                    sizeof(struct page *), GFP_KERNEL);
+                        if (pages == NULL) {
+                                region->numLockedPages = 0;
+                                return -ENOMEM;
+                        }
+                        userTask = memMap->userTask;
+                        down_read(&userTask->mm->mmap_sem);
+                        rc = get_user_pages(userTask,   /* task */
+                                            userTask->mm,       /* mm */
+                                            (unsigned long)region->virtAddr,    /* start */
+                                            region->numLockedPages,     /* len */
+                                            memMap->dir == DMA_FROM_DEVICE,     /* write */
+                                            0,  /* force */
+                                            pages,      /* pages (array of pointers to page) */
+                                            NULL);      /* vmas */
+                        up_read(&userTask->mm->mmap_sem);
+                        if (rc != region->numLockedPages) {
+                                kfree(pages);
+                                region->numLockedPages = 0;
+                                if (rc >= 0) {
+                                        rc = -EINVAL;
+                                }
+                        } else {
+                                uint8_t *virtAddr = region->virtAddr;
+                                size_t bytesRemaining;
+                                int pageIdx;
+                                rc = 0; /* Since get_user_pages returns +ve number */
+                                region->lockedPages = pages;
+                                /* We've locked the user pages. Now we need to walk them and figure */
+                                /* out the physical addresses. */
+                                /* The first page may be partial */
+                                dma_map_add_segment(memMap,
+                                                    region,
+                                                    virtAddr,
+                                                    PFN_PHYS(page_to_pfn
+                                                             (pages[0])) +
+                                                    firstPageOffset,
+                                                    firstPageSize);
+                                virtAddr += firstPageSize;
+                                bytesRemaining =
+                                    region->numBytes - firstPageSize;
+                                for (pageIdx = 1;
+                                     pageIdx < region->numLockedPages;
+                                     pageIdx++) {
+                                        size_t bytesThisPage =
+                                            (bytesRemaining >
+                                             PAGE_SIZE ? PAGE_SIZE :
+                                             bytesRemaining);
+                                        DMA_MAP_PRINT
+                                            ("pageIdx:%d pages[pageIdx]=%p pfn=%u phys=%u\n",
+                                             pageIdx, pages[pageIdx],
+                                             page_to_pfn(pages[pageIdx]),
+                                             PFN_PHYS(page_to_pfn
+                                                      (pages[pageIdx])));
+                                        dma_map_add_segment(memMap,
+                                                            region,
+                                                            virtAddr,
+                                                            PFN_PHYS(page_to_pfn
+                                                                     (pages
+                                                                      [pageIdx])),
+                                                            bytesThisPage);
+                                        virtAddr += bytesThisPage;
+                                        bytesRemaining -= bytesThisPage;
+                                }
+                        }
+#else
+                        printk(KERN_ERR
+                               "%s: User mode pages are not yet supported\n",
+                               __func__);
+                        /* user pages are not physically contiguous */
+                        rc = -EINVAL;
+#endif
+                        break;
+                }
+        default:
+                {
+                        printk(KERN_ERR "%s: Unsupported memory type: %d\n",
+                               __func__, region->memType);
+                        rc = -EINVAL;
+                        break;
+                }
+        }
+        if (rc != 0) {
+                memMap->numRegionsUsed--;
+        }
+out:
+        DMA_MAP_PRINT("returning %d\n", rc);
+        up(&memMap->lock);
+        return rc;
+}
+EXPORT_SYMBOL(dma_map_add_segment);
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+int dma_map_mem(DMA_MemMap_t *memMap,   /* Stores state information about the map */
+                void *mem,      /* Virtual address that we want to get a map of */
+                size_t numBytes,        /* Number of bytes being mapped */
+                enum dma_data_direction dir     /* Direction that the mapping will be going */
+    ) {
+        int rc;
+        rc = dma_map_start(memMap, dir);
+        if (rc == 0) {
+                rc = dma_map_add_region(memMap, mem, numBytes);
+                if (rc < 0) {
+                        /* Since the add fails, this function will fail, and the caller won't */
+                        /* call unmap, so we need to do it here. */
+                        dma_unmap(memMap, 0);
+                }
+        }
+        return rc;
+}
+EXPORT_SYMBOL(dma_map_mem);
+/****************************************************************************/
+/**
+*   Setup a descriptor ring for a given memory map.
+*
+*   It is assumed that the descriptor ring has already been initialized, and
+*   this routine will only reallocate a new descriptor ring if the existing
+*   one is too small.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+int dma_map_create_descriptor_ring(DMA_Device_t dev,    /* DMA device (where the ring is stored) */
+                                   DMA_MemMap_t *memMap,        /* Memory map that will be used */
+                                   dma_addr_t devPhysAddr       /* Physical address of device */
+    ) {
+        int rc;
+        int numDescriptors;
+        DMA_DeviceAttribute_t *devAttr;
+        DMA_Region_t *region;
+        DMA_Segment_t *segment;
+        dma_addr_t srcPhysAddr;
+        dma_addr_t dstPhysAddr;
+        int regionIdx;
+        int segmentIdx;
+        devAttr = &DMA_gDeviceAttribute[dev];
+        down(&memMap->lock);
+        /* Figure out how many descriptors we need */
+        numDescriptors = 0;
+        for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
+                region = &memMap->region[regionIdx];
+                for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
+                     segmentIdx++) {
+                        segment = &region->segment[segmentIdx];
+                        if (memMap->dir == DMA_TO_DEVICE) {
+                                srcPhysAddr = segment->physAddr;
+                                dstPhysAddr = devPhysAddr;
+                        } else {
+                                srcPhysAddr = devPhysAddr;
+                                dstPhysAddr = segment->physAddr;
+                        }
+                        rc =
+                             dma_calculate_descriptor_count(dev, srcPhysAddr,
+                                                            dstPhysAddr,
+                                                            segment->
+                                                            numBytes);
+                        if (rc < 0) {
+                                printk(KERN_ERR
+                                       "%s: dma_calculate_descriptor_count failed: %d\n",
+                                       __func__, rc);
+                                goto out;
+                        }
+                        numDescriptors += rc;
+                }
+        }
+        /* Adjust the size of the ring, if it isn't big enough */
+        if (numDescriptors > devAttr->ring.descriptorsAllocated) {
+                dma_free_descriptor_ring(&devAttr->ring);
+                rc =
+                     dma_alloc_descriptor_ring(&devAttr->ring,
+                                               numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_alloc_descriptor_ring failed: %d\n",
+                               __func__, rc);
+                        goto out;
+                }
+        } else {
+                rc =
+                     dma_init_descriptor_ring(&devAttr->ring,
+                                              numDescriptors);
+                if (rc < 0) {
+                        printk(KERN_ERR
+                               "%s: dma_init_descriptor_ring failed: %d\n",
+                               __func__, rc);
+                        goto out;
+                }
+        }
+        /* Populate the descriptors */
+        for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
+                region = &memMap->region[regionIdx];
+                for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
+                     segmentIdx++) {
+                        segment = &region->segment[segmentIdx];
+                        if (memMap->dir == DMA_TO_DEVICE) {
+                                srcPhysAddr = segment->physAddr;
+                                dstPhysAddr = devPhysAddr;
+                        } else {
+                                srcPhysAddr = devPhysAddr;
+                                dstPhysAddr = segment->physAddr;
+                        }
+                        rc =
+                             dma_add_descriptors(&devAttr->ring, dev,
+                                                 srcPhysAddr, dstPhysAddr,
+                                                 segment->numBytes);
+                        if (rc < 0) {
+                                printk(KERN_ERR
+                                       "%s: dma_add_descriptors failed: %d\n",
+                                       __func__, rc);
+                                goto out;
+                        }
+                }
+        }
+        rc = 0;
+out:
+        up(&memMap->lock);
+        return rc;
+}
+EXPORT_SYMBOL(dma_map_create_descriptor_ring);
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+int dma_unmap(DMA_MemMap_t *memMap,     /* Stores state information about the map */
+              int dirtied       /* non-zero if any of the pages were modified */
+    ) {
+        int regionIdx;
+        int segmentIdx;
+        DMA_Region_t *region;
+        DMA_Segment_t *segment;
+        for (regionIdx = 0; regionIdx < memMap->numRegionsUsed; regionIdx++) {
+                region = &memMap->region[regionIdx];
+                for (segmentIdx = 0; segmentIdx < region->numSegmentsUsed;
+                     segmentIdx++) {
+                        segment = &region->segment[segmentIdx];
+                        switch (region->memType) {
+                        case DMA_MEM_TYPE_VMALLOC:
+                                {
+                                        printk(KERN_ERR
+                                               "%s: vmalloc'd pages are not yet supported\n",
+                                               __func__);
+                                        return -EINVAL;
+                                }
+                        case DMA_MEM_TYPE_KMALLOC:
+                                {
+#if ALLOW_MAP_OF_KMALLOC_MEMORY
+                                        dma_unmap_single(NULL,
+                                                         segment->physAddr,
+                                                         segment->numBytes,
+                                                         memMap->dir);
+#endif
+                                        break;
+                                }
+                        case DMA_MEM_TYPE_DMA:
+                                {
+                                        dma_sync_single_for_cpu(NULL,
+                                                                segment->
+                                                                physAddr,
+                                                                segment->
+                                                                numBytes,
+                                                                memMap->dir);
+                                        break;
+                                }
+                        case DMA_MEM_TYPE_USER:
+                                {
+                                        /* Nothing to do here. */
+                                        break;
+                                }
+                        default:
+                                {
+                                        printk(KERN_ERR
+                                               "%s: Unsupported memory type: %d\n",
+                                               __func__, region->memType);
+                                        return -EINVAL;
+                                }
+                        }
+                        segment->virtAddr = NULL;
+                        segment->physAddr = 0;
+                        segment->numBytes = 0;
+                }
+                if (region->numLockedPages > 0) {
+                        int pageIdx;
+                        /* Some user pages were locked. We need to go and unlock them now. */
+                        for (pageIdx = 0; pageIdx < region->numLockedPages;
+                             pageIdx++) {
+                                struct page *page =
+                                    region->lockedPages[pageIdx];
+                                if (memMap->dir == DMA_FROM_DEVICE) {
+                                        SetPageDirty(page);
+                                }
+                                page_cache_release(page);
+                        }
+                        kfree(region->lockedPages);
+                        region->numLockedPages = 0;
+                        region->lockedPages = NULL;
+                }
+                region->memType = DMA_MEM_TYPE_NONE;
+                region->virtAddr = NULL;
+                region->numBytes = 0;
+                region->numSegmentsUsed = 0;
+        }
+        memMap->userTask = NULL;
+        memMap->numRegionsUsed = 0;
+        memMap->inUse = 0;
+        up(&memMap->lock);
+        return 0;
+}
+EXPORT_SYMBOL(dma_unmap);
diff --git a/arch/arm/mach-bcmring/dma_device.c b/arch/arm/mach-bcmring/dma_device.c
new file mode 100644
index 000000000000..ca0ad736870b
--- /dev/null
+++ b/arch/arm/mach-bcmring/dma_device.c
@@ -0,0 +1,593 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*   @file   dma_device.c
+*
+*   @brief  private array of DMA_DeviceAttribute_t
+*/
+/****************************************************************************/
+DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES] = {
+        [DMA_DEVICE_MEM_TO_MEM] =       /* MEM 2 MEM */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "mem-to-mem",
+         .config = {
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    },
+         },
+        [DMA_DEVICE_VPM_MEM_TO_MEM] =   /* VPM */
+        {
+         .flags = DMA_DEVICE_FLAG_IS_DEDICATED | DMA_DEVICE_FLAG_NO_ISR,
+         .name = "vpm",
+         .dedicatedController = 0,
+         .dedicatedChannel = 0,
+         /* reserve DMA0:0 for VPM */
+         },
+        [DMA_DEVICE_NAND_MEM_TO_MEM] =  /* NAND */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "nand",
+         .config = {
+                    .srcPeripheralPort = 0,
+                    .dstPeripheralPort = 0,
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_6,
+                    },
+         },
+        [DMA_DEVICE_PIF_MEM_TO_DEV] =   /* PIF TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
+         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
+         | DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST | DMA_DEVICE_FLAG_PORT_PER_DMAC,
+         .name = "pif_tx",
+         .dmacPort = {14, 5},
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    /* dstPeripheralPort          = 5 or 14 */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .maxDataPerBlock = 16256,
+                    },
+         },
+        [DMA_DEVICE_PIF_DEV_TO_MEM] =   /* PIF RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1
+         | DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO
+         /* DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST */
+         | DMA_DEVICE_FLAG_PORT_PER_DMAC,
+         .name = "pif_rx",
+         .dmacPort = {14, 5},
+         .config = {
+                    /* srcPeripheralPort          = 5 or 14 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .maxDataPerBlock = 16256,
+                    },
+         },
+        [DMA_DEVICE_I2S0_DEV_TO_MEM] =  /* I2S RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "i2s0_rx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: I2S0 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_I2S0_MEM_TO_DEV] =  /* I2S TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "i2s0_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 1,     /* DST: I2S0 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_I2S1_DEV_TO_MEM] =  /* I2S1 RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "i2s1_rx",
+         .config = {
+                    .srcPeripheralPort = 2,     /* SRC: I2S1 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_16,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_I2S1_MEM_TO_DEV] =  /* I2S1 TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "i2s1_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 3,     /* DST: I2S1 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_16,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_ESW_MEM_TO_DEV] =   /* ESW TX */
+        {
+         .name = "esw_tx",
+         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
+         .dedicatedController = 1,
+         .dedicatedChannel = 3,
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 1,     /* DST: ESW (MTP) */
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    /* DMAx_AHB_SSTATARy */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    /* DMAx_AHB_DSTATARy */
+                    .dstStatusRegisterAddress = 0x30490010,
+                    /* DMAx_AHB_CFGy */
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    /* DMAx_AHB_CTLy */
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_0,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    },
+         },
+        [DMA_DEVICE_ESW_DEV_TO_MEM] =   /* ESW RX */
+        {
+         .name = "esw_rx",
+         .flags = DMA_DEVICE_FLAG_IS_DEDICATED,
+         .dedicatedController = 1,
+         .dedicatedChannel = 2,
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: ESW (PTM) */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    /* DMAx_AHB_SSTATARy */
+                    .srcStatusRegisterAddress = 0x30480010,
+                    /* DMAx_AHB_DSTATARy */
+                    .dstStatusRegisterAddress = 0x00000000,
+                    /* DMAx_AHB_CFGy */
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    /* DMAx_AHB_CTLy */
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_0,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM] =   /* APM Codec A Ingress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_a_rx",
+         .config = {
+                    .srcPeripheralPort = 2,     /* SRC: Codec A Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV] =   /* APM Codec A Egress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_a_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 3,     /* DST: Codec A Egress FIFO */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM] =   /* APM Codec B Ingress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_b_rx",
+         .config = {
+                    .srcPeripheralPort = 4,     /* SRC: Codec B Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV] =   /* APM Codec B Egress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "apm_b_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 5,     /* DST: Codec B Egress FIFO */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM] =   /* APM Codec C Ingress */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "apm_c_rx",
+         .config = {
+                    .srcPeripheralPort = 4,     /* SRC: Codec C Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM0_DEV_TO_MEM] =      /* PCM0 RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "pcm0_rx",
+         .config = {
+                    .srcPeripheralPort = 12,    /* SRC: PCM0 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM0_MEM_TO_DEV] =      /* PCM0 TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0,
+         .name = "pcm0_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 13,    /* DST: PCM0 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM1_DEV_TO_MEM] =      /* PCM1 RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "pcm1_rx",
+         .config = {
+                    .srcPeripheralPort = 14,    /* SRC: PCM1 */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_4,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_CONTINUOUS,
+                    },
+         },
+        [DMA_DEVICE_APM_PCM1_MEM_TO_DEV] =      /* PCM1 TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "pcm1_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 15,    /* DST: PCM1 */
+                    .srcStatusRegisterAddress = 0,
+                    .dstStatusRegisterAddress = 0,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_4,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_SPUM_DEV_TO_MEM] =  /* SPUM RX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "spum_rx",
+         .config = {
+                    .srcPeripheralPort = 6,     /* SRC: Codec A Ingress FIFO */
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    /* Busrt size **MUST** be 16 for SPUM to work */
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    /* on the RX side, SPU needs to be the flow controller */
+                    .flowControler = dmacHw_FLOW_CONTROL_PERIPHERAL,
+                    },
+         },
+        [DMA_DEVICE_SPUM_MEM_TO_DEV] =  /* SPUM TX */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "spum_tx",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .dstPeripheralPort = 7,     /* DST: SPUM */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .blockTransferInterrupt = dmacHw_INTERRUPT_DISABLE,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_32,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_32,
+                    /* Busrt size **MUST** be 16 for SPUM to work */
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_16,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_16,
+                    .transferMode = dmacHw_TRANSFER_MODE_PERREQUEST,
+                    },
+         },
+        [DMA_DEVICE_MEM_TO_VRAM] =      /* MEM 2 VRAM */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "mem-to-vram",
+         .config = {
+                    .srcPeripheralPort = 0,     /* SRC: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_1,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_2,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    },
+         },
+        [DMA_DEVICE_VRAM_TO_MEM] =      /* VRAM 2 MEM */
+        {
+         .flags = DMA_DEVICE_FLAG_ON_DMA0 | DMA_DEVICE_FLAG_ON_DMA1,
+         .name = "vram-to-mem",
+         .config = {
+                    .dstPeripheralPort = 0,     /* DST: memory */
+                    .srcStatusRegisterAddress = 0x00000000,
+                    .dstStatusRegisterAddress = 0x00000000,
+                    .srcUpdate = dmacHw_SRC_ADDRESS_UPDATE_MODE_INC,
+                    .dstUpdate = dmacHw_DST_ADDRESS_UPDATE_MODE_INC,
+                    .transferType = dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                    .srcMasterInterface = dmacHw_SRC_MASTER_INTERFACE_2,
+                    .dstMasterInterface = dmacHw_DST_MASTER_INTERFACE_1,
+                    .completeTransferInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .errorInterrupt = dmacHw_INTERRUPT_ENABLE,
+                    .channelPriority = dmacHw_CHANNEL_PRIORITY_7,
+                    .srcMaxTransactionWidth = dmacHw_SRC_TRANSACTION_WIDTH_64,
+                    .dstMaxTransactionWidth = dmacHw_DST_TRANSACTION_WIDTH_64,
+                    .srcMaxBurstWidth = dmacHw_SRC_BURST_WIDTH_8,
+                    .dstMaxBurstWidth = dmacHw_DST_BURST_WIDTH_8,
+                    },
+         },
+};
+EXPORT_SYMBOL(DMA_gDeviceAttribute);    /* primarily for dma-test.c */
diff --git a/arch/arm/mach-bcmring/include/cfg_global.h b/arch/arm/mach-bcmring/include/cfg_global.h
new file mode 100644
index 000000000000..f01da877148e
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/cfg_global.h
@@ -0,0 +1,13 @@
+#ifndef _CFG_GLOBAL_H_
+#define _CFG_GLOBAL_H_
+#include <cfg_global_defines.h>
+#define CFG_GLOBAL_CHIP                         BCM11107
+#define CFG_GLOBAL_CHIP_FAMILY                  CFG_GLOBAL_CHIP_FAMILY_BCMRING
+#define CFG_GLOBAL_CHIP_REV                     0xB0
+#define CFG_GLOBAL_RAM_SIZE                     0x10000000
+#define CFG_GLOBAL_RAM_BASE                     0x00000000
+#define CFG_GLOBAL_RAM_RESERVED_SIZE            0x000000
+#endif /* _CFG_GLOBAL_H_ */
diff --git a/arch/arm/mach-bcmring/include/cfg_global_defines.h b/arch/arm/mach-bcmring/include/cfg_global_defines.h
new file mode 100644
index 000000000000..b5beb0b30734
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/cfg_global_defines.h
@@ -0,0 +1,40 @@
+/*****************************************************************************
+* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CFG_GLOBAL_DEFINES_H
+#define CFG_GLOBAL_DEFINES_H
+/* CHIP */
+#define BCM1103 1
+#define BCM1191 4
+#define BCM2153 5
+#define BCM2820 6
+#define BCM2826 8
+#define FPGA11107 9
+#define BCM11107   10
+#define BCM11109   11
+#define BCM11170   12
+#define BCM11110   13
+#define BCM11211   14
+/* CFG_GLOBAL_CHIP_FAMILY types */
+#define CFG_GLOBAL_CHIP_FAMILY_NONE        0
+#define CFG_GLOBAL_CHIP_FAMILY_BCM116X     2
+#define CFG_GLOBAL_CHIP_FAMILY_BCMRING     4
+#define CFG_GLOBAL_CHIP_FAMILY_BCM1103     8
+#define IMAGE_HEADER_SIZE_CHECKSUM    4
+#endif
diff --git a/arch/arm/mach-bcmring/include/csp/cache.h b/arch/arm/mach-bcmring/include/csp/cache.h
new file mode 100644
index 000000000000..caa20e59db99
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/cache.h
@@ -0,0 +1,35 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CSP_CACHE_H
+#define CSP_CACHE_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+/* ---- Public Constants and Types --------------------------------------- */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+#include <asm/cacheflush.h>
+#define CSP_CACHE_FLUSH_ALL      flush_cache_all()
+#else
+#define CSP_CACHE_FLUSH_ALL
+#endif
+#endif /* CSP_CACHE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/delay.h b/arch/arm/mach-bcmring/include/csp/delay.h
new file mode 100644
index 000000000000..8b3d80367293
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/delay.h
@@ -0,0 +1,36 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CSP_DELAY_H
+#define CSP_DELAY_H
+/* ---- Include Files ---------------------------------------------------- */
+/* Some CSP routines require use of the following delay routines. Use the OS */
+/* version if available, otherwise use a CSP specific definition. */
+/* void udelay(unsigned long usecs); */
+/* void mdelay(unsigned long msecs); */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+   #include <linux/delay.h>
+#else
+   #include <mach/csp/delay.h>
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /*  CSP_DELAY_H */
diff --git a/arch/arm/mach-bcmring/include/csp/dmacHw.h b/arch/arm/mach-bcmring/include/csp/dmacHw.h
new file mode 100644
index 000000000000..5d510130a25f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/dmacHw.h
@@ -0,0 +1,596 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    dmacHw.h
+*
+*  @brief   API definitions for low level DMA controller driver
+*
+*/
+/****************************************************************************/
+#ifndef _DMACHW_H
+#define _DMACHW_H
+#include <stddef.h>
+#include <csp/stdint.h>
+#include <mach/csp/dmacHw_reg.h>
+/* Define DMA Channel ID using DMA controller number (m) and channel number (c).
+   System specific channel ID should be defined as follows
+   For example:
+   #include <dmacHw.h>
+   ...
+   #define systemHw_LCD_CHANNEL_ID                dmacHw_MAKE_CHANNEL_ID(0,5)
+   #define systemHw_SWITCH_RX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,0)
+   #define systemHw_SWITCH_TX_CHANNEL_ID          dmacHw_MAKE_CHANNEL_ID(0,1)
+   #define systemHw_APM_RX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,3)
+   #define systemHw_APM_TX_CHANNEL_ID             dmacHw_MAKE_CHANNEL_ID(0,4)
+   ...
+   #define systemHw_SHARED1_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,4)
+   #define systemHw_SHARED2_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(1,5)
+   #define systemHw_SHARED3_CHANNEL_ID            dmacHw_MAKE_CHANNEL_ID(0,6)
+   ...
+*/
+#define dmacHw_MAKE_CHANNEL_ID(m, c)         (m << 8 | c)
+typedef enum {
+        dmacHw_CHANNEL_PRIORITY_0 = dmacHw_REG_CFG_LO_CH_PRIORITY_0,    /* Channel priority 0. Lowest priority DMA channel */
+        dmacHw_CHANNEL_PRIORITY_1 = dmacHw_REG_CFG_LO_CH_PRIORITY_1,    /* Channel priority 1 */
+        dmacHw_CHANNEL_PRIORITY_2 = dmacHw_REG_CFG_LO_CH_PRIORITY_2,    /* Channel priority 2 */
+        dmacHw_CHANNEL_PRIORITY_3 = dmacHw_REG_CFG_LO_CH_PRIORITY_3,    /* Channel priority 3 */
+        dmacHw_CHANNEL_PRIORITY_4 = dmacHw_REG_CFG_LO_CH_PRIORITY_4,    /* Channel priority 4 */
+        dmacHw_CHANNEL_PRIORITY_5 = dmacHw_REG_CFG_LO_CH_PRIORITY_5,    /* Channel priority 5 */
+        dmacHw_CHANNEL_PRIORITY_6 = dmacHw_REG_CFG_LO_CH_PRIORITY_6,    /* Channel priority 6 */
+        dmacHw_CHANNEL_PRIORITY_7 = dmacHw_REG_CFG_LO_CH_PRIORITY_7     /* Channel priority 7. Highest priority DMA channel */
+} dmacHw_CHANNEL_PRIORITY_e;
+/* Source destination master interface */
+typedef enum {
+        dmacHw_SRC_MASTER_INTERFACE_1 = dmacHw_REG_CTL_SMS_1,   /* Source DMA master interface 1 */
+        dmacHw_SRC_MASTER_INTERFACE_2 = dmacHw_REG_CTL_SMS_2,   /* Source DMA master interface 2 */
+        dmacHw_DST_MASTER_INTERFACE_1 = dmacHw_REG_CTL_DMS_1,   /* Destination DMA master interface 1 */
+        dmacHw_DST_MASTER_INTERFACE_2 = dmacHw_REG_CTL_DMS_2    /* Destination DMA master interface 2 */
+} dmacHw_MASTER_INTERFACE_e;
+typedef enum {
+        dmacHw_SRC_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_SRC_TR_WIDTH_8, /* Source 8 bit  (1 byte) per transaction */
+        dmacHw_SRC_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_SRC_TR_WIDTH_16,       /* Source 16 bit (2 byte) per transaction */
+        dmacHw_SRC_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_SRC_TR_WIDTH_32,       /* Source 32 bit (4 byte) per transaction */
+        dmacHw_SRC_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_SRC_TR_WIDTH_64,       /* Source 64 bit (8 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_8 = dmacHw_REG_CTL_DST_TR_WIDTH_8, /* Destination 8 bit  (1 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_16 = dmacHw_REG_CTL_DST_TR_WIDTH_16,       /* Destination 16 bit (2 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_32 = dmacHw_REG_CTL_DST_TR_WIDTH_32,       /* Destination 32 bit (4 byte) per transaction */
+        dmacHw_DST_TRANSACTION_WIDTH_64 = dmacHw_REG_CTL_DST_TR_WIDTH_64        /* Destination 64 bit (8 byte) per transaction */
+} dmacHw_TRANSACTION_WIDTH_e;
+typedef enum {
+        dmacHw_SRC_BURST_WIDTH_0 = dmacHw_REG_CTL_SRC_MSIZE_0,  /* Source No burst */
+        dmacHw_SRC_BURST_WIDTH_4 = dmacHw_REG_CTL_SRC_MSIZE_4,  /* Source 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_SRC_BURST_WIDTH_8 = dmacHw_REG_CTL_SRC_MSIZE_8,  /* Source 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_SRC_BURST_WIDTH_16 = dmacHw_REG_CTL_SRC_MSIZE_16,        /* Source 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_DST_BURST_WIDTH_0 = dmacHw_REG_CTL_DST_MSIZE_0,  /* Destination No burst */
+        dmacHw_DST_BURST_WIDTH_4 = dmacHw_REG_CTL_DST_MSIZE_4,  /* Destination 4  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_DST_BURST_WIDTH_8 = dmacHw_REG_CTL_DST_MSIZE_8,  /* Destination 8  X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+        dmacHw_DST_BURST_WIDTH_16 = dmacHw_REG_CTL_DST_MSIZE_16 /* Destination 16 X dmacHw_TRANSACTION_WIDTH_xxx bytes per burst */
+} dmacHw_BURST_WIDTH_e;
+typedef enum {
+        dmacHw_TRANSFER_TYPE_MEM_TO_MEM = dmacHw_REG_CTL_TTFC_MM_DMAC,  /* Memory to memory transfer */
+        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM = dmacHw_REG_CTL_TTFC_PM_DMAC,   /* Peripheral to memory transfer */
+        dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_MP_DMAC,   /* Memory to peripheral transfer */
+        dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_PERIPHERAL = dmacHw_REG_CTL_TTFC_PP_DMAC     /* Peripheral to peripheral transfer */
+} dmacHw_TRANSFER_TYPE_e;
+typedef enum {
+        dmacHw_TRANSFER_MODE_PERREQUEST,        /* Block transfer per DMA request */
+        dmacHw_TRANSFER_MODE_CONTINUOUS,        /* Continuous transfer of streaming data */
+        dmacHw_TRANSFER_MODE_PERIODIC   /* Periodic transfer of streaming data */
+} dmacHw_TRANSFER_MODE_e;
+typedef enum {
+        dmacHw_SRC_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_SINC_INC,   /* Increment source address after every transaction */
+        dmacHw_SRC_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_SINC_DEC,   /* Decrement source address after every transaction */
+        dmacHw_DST_ADDRESS_UPDATE_MODE_INC = dmacHw_REG_CTL_DINC_INC,   /* Increment destination address after every transaction */
+        dmacHw_DST_ADDRESS_UPDATE_MODE_DEC = dmacHw_REG_CTL_DINC_DEC,   /* Decrement destination address after every transaction */
+        dmacHw_SRC_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_SINC_NC,     /* No change in source address after every transaction */
+        dmacHw_DST_ADDRESS_UPDATE_MODE_NC = dmacHw_REG_CTL_DINC_NC      /* No change in destination address after every transaction */
+} dmacHw_ADDRESS_UPDATE_MODE_e;
+typedef enum {
+        dmacHw_FLOW_CONTROL_DMA,        /* DMA working as flow controller (default) */
+        dmacHw_FLOW_CONTROL_PERIPHERAL  /* Peripheral working as flow controller */
+} dmacHw_FLOW_CONTROL_e;
+typedef enum {
+        dmacHw_TRANSFER_STATUS_BUSY,    /* DMA Transfer ongoing */
+        dmacHw_TRANSFER_STATUS_DONE,    /* DMA Transfer completed */
+        dmacHw_TRANSFER_STATUS_ERROR    /* DMA Transfer error */
+} dmacHw_TRANSFER_STATUS_e;
+typedef enum {
+        dmacHw_INTERRUPT_DISABLE,       /* Interrupt disable  */
+        dmacHw_INTERRUPT_ENABLE /* Interrupt enable */
+} dmacHw_INTERRUPT_e;
+typedef enum {
+        dmacHw_INTERRUPT_STATUS_NONE = 0x0,     /* No DMA interrupt */
+        dmacHw_INTERRUPT_STATUS_TRANS = 0x1,    /* End of DMA transfer interrupt */
+        dmacHw_INTERRUPT_STATUS_BLOCK = 0x2,    /* End of block transfer interrupt */
+        dmacHw_INTERRUPT_STATUS_ERROR = 0x4     /* Error interrupt */
+} dmacHw_INTERRUPT_STATUS_e;
+typedef enum {
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_NUM,   /* Number of DMA channel */
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_MAX_BLOCK_SIZE,        /* Maximum channel burst size */
+        dmacHw_CONTROLLER_ATTRIB_MASTER_INTF_NUM,       /* Number of DMA master interface */
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_BUS_WIDTH,     /* Channel Data bus width */
+        dmacHw_CONTROLLER_ATTRIB_CHANNEL_FIFO_SIZE      /* Channel FIFO size */
+} dmacHw_CONTROLLER_ATTRIB_e;
+typedef unsigned long dmacHw_HANDLE_t;  /* DMA channel handle */
+typedef uint32_t dmacHw_ID_t;   /* DMA channel Id.  Must be created using
+                                   "dmacHw_MAKE_CHANNEL_ID" macro
+                                 */
+/* DMA channel configuration parameters */
+typedef struct {
+        uint32_t srcPeripheralPort;     /* Source peripheral port */
+        uint32_t dstPeripheralPort;     /* Destination peripheral port */
+        uint32_t srcStatusRegisterAddress;      /* Source status register address */
+        uint32_t dstStatusRegisterAddress;      /* Destination status register address of type  */
+        uint32_t srcGatherWidth;        /* Number of bytes gathered before successive gather opearation */
+        uint32_t srcGatherJump; /* Number of bytes jumpped before successive gather opearation */
+        uint32_t dstScatterWidth;       /* Number of bytes sacattered before successive scatter opearation */
+        uint32_t dstScatterJump;        /* Number of bytes jumpped  before successive scatter opearation */
+        uint32_t maxDataPerBlock;       /* Maximum number of bytes to be transferred per block/descrptor.
+                                           0 = Maximum possible.
+                                         */
+        dmacHw_ADDRESS_UPDATE_MODE_e srcUpdate; /* Source address update mode */
+        dmacHw_ADDRESS_UPDATE_MODE_e dstUpdate; /* Destination address update mode */
+        dmacHw_TRANSFER_TYPE_e transferType;    /* DMA transfer type  */
+        dmacHw_TRANSFER_MODE_e transferMode;    /* DMA transfer mode */
+        dmacHw_MASTER_INTERFACE_e srcMasterInterface;   /* DMA source interface  */
+        dmacHw_MASTER_INTERFACE_e dstMasterInterface;   /* DMA destination interface */
+        dmacHw_TRANSACTION_WIDTH_e srcMaxTransactionWidth;      /* Source transaction width   */
+        dmacHw_TRANSACTION_WIDTH_e dstMaxTransactionWidth;      /* Destination transaction width */
+        dmacHw_BURST_WIDTH_e srcMaxBurstWidth;  /* Source burst width */
+        dmacHw_BURST_WIDTH_e dstMaxBurstWidth;  /* Destination burst width */
+        dmacHw_INTERRUPT_e blockTransferInterrupt;      /* Block trsnafer interrupt */
+        dmacHw_INTERRUPT_e completeTransferInterrupt;   /* Complete DMA trsnafer interrupt */
+        dmacHw_INTERRUPT_e errorInterrupt;      /* Error interrupt */
+        dmacHw_CHANNEL_PRIORITY_e channelPriority;      /* Channel priority */
+        dmacHw_FLOW_CONTROL_e flowControler;    /* Data flow controller */
+} dmacHw_CONFIG_t;
+/****************************************************************************/
+/**
+*  @brief   Initializes DMA
+*
+*  This function initializes DMA CSP driver
+*
+*  @note
+*     Must be called before using any DMA channel
+*/
+/****************************************************************************/
+void dmacHw_initDma(void);
+/****************************************************************************/
+/**
+*  @brief   Exit function for  DMA
+*
+*  This function isolates DMA from the system
+*
+*/
+/****************************************************************************/
+void dmacHw_exitDma(void);
+/****************************************************************************/
+/**
+*  @brief   Gets a handle to a DMA channel
+*
+*  This function returns a handle, representing a control block of a particular DMA channel
+*
+*  @return  -1       - On Failure
+*            handle  - On Success, representing a channel control block
+*
+*  @note
+*     None  Channel ID must be created using "dmacHw_MAKE_CHANNEL_ID" macro
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getChannelHandle(dmacHw_ID_t channelId   /* [ IN ] DMA Channel Id */
+    );
+/****************************************************************************/
+/**
+*  @brief   Initializes a DMA channel for use
+*
+*  This function initializes and resets a DMA channel for use
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_initChannel(dmacHw_HANDLE_t handle   /*  [ IN ] DMA Channel handle  */
+    );
+/****************************************************************************/
+/**
+*  @brief  Estimates number of descriptor needed to perform certain DMA transfer
+*
+*
+*  @return  On failure : -1
+*           On success : Number of descriptor count
+*
+*
+*/
+/****************************************************************************/
+int dmacHw_calculateDescriptorCount(dmacHw_CONFIG_t *pConfig,   /*   [ IN ] Configuration settings */
+                                    void *pSrcAddr,     /*   [ IN ] Source (Peripheral/Memory) address */
+                                    void *pDstAddr,     /*   [ IN ] Destination (Peripheral/Memory) address */
+                                    size_t dataLen      /*   [ IN ] Data length in bytes */
+    );
+/****************************************************************************/
+/**
+*  @brief   Initializes descriptor ring
+*
+*  This function will initializes the descriptor ring of a DMA channel
+*
+*
+*  @return   -1 - On failure
+*             0 - On success
+*  @note
+*     - "len" parameter should be obtained from "dmacHw_descriptorLen"
+*     - Descriptor buffer MUST be 32 bit aligned and uncached as it
+*       is accessed by ARM and DMA
+*/
+/****************************************************************************/
+int dmacHw_initDescriptor(void *pDescriptorVirt,        /*  [ IN ] Virtual address of uncahced buffer allocated to form descriptor ring */
+                          uint32_t descriptorPhyAddr,   /*  [ IN ] Physical address of pDescriptorVirt (descriptor buffer) */
+                          uint32_t len, /*  [ IN ] Size of the pBuf */
+                          uint32_t num  /*  [ IN ] Number of descriptor in the ring */
+    );
+/****************************************************************************/
+/**
+*  @brief  Finds amount of memory required to form a descriptor ring
+*
+*
+*  @return   Number of bytes required to form a descriptor ring
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorLen(uint32_t descCnt  /*  [ IN ] Number of descriptor in the ring */
+    );
+/****************************************************************************/
+/**
+*  @brief   Configure DMA channel
+*
+*  @return  0  : On success
+*           -1 : On failure
+*/
+/****************************************************************************/
+int dmacHw_configChannel(dmacHw_HANDLE_t handle,        /*  [ IN ] DMA Channel handle  */
+                         dmacHw_CONFIG_t *pConfig       /*   [ IN ] Configuration settings */
+    );
+/****************************************************************************/
+/**
+*  @brief   Set descriptors for known data length
+*
+*  When DMA has to work as a flow controller, this function prepares the
+*  descriptor chain to transfer data
+*
+*  from:
+*          - Memory to memory
+*          - Peripheral to memory
+*          - Memory to Peripheral
+*          - Peripheral to Peripheral
+*
+*  @return   -1 - On failure
+*             0 - On success
+*
+*/
+/****************************************************************************/
+int dmacHw_setDataDescriptor(dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
+                             void *pDescriptor, /*  [ IN ] Descriptor buffer  */
+                             void *pSrcAddr,    /*  [ IN ] Source (Peripheral/Memory) address */
+                             void *pDstAddr,    /*  [ IN ] Destination (Peripheral/Memory) address */
+                             size_t dataLen     /*  [ IN ] Length in bytes   */
+    );
+/****************************************************************************/
+/**
+*  @brief   Indicates whether DMA transfer is in progress or completed
+*
+*  @return   DMA transfer status
+*          dmacHw_TRANSFER_STATUS_BUSY:         DMA Transfer ongoing
+*          dmacHw_TRANSFER_STATUS_DONE:         DMA Transfer completed
+*          dmacHw_TRANSFER_STATUS_ERROR:        DMA Transfer error
+*
+*/
+/****************************************************************************/
+dmacHw_TRANSFER_STATUS_e dmacHw_transferCompleted(dmacHw_HANDLE_t handle        /*   [ IN ] DMA Channel handle  */
+    );
+/****************************************************************************/
+/**
+*  @brief   Set descriptor carrying control information
+*
+*  This function will be used to send specific control information to the device
+*  using the DMA channel
+*
+*
+*  @return  -1 - On failure
+*            0 - On success
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_setControlDescriptor(dmacHw_CONFIG_t *pConfig,       /*  [ IN ] Configuration settings */
+                                void *pDescriptor,      /*  [ IN ] Descriptor buffer  */
+                                uint32_t ctlAddress,    /*  [ IN ] Address of the device control register  */
+                                uint32_t control        /*  [ IN ] Device control information */
+    );
+/****************************************************************************/
+/**
+*  @brief   Read data DMA transferred to memory
+*
+*  This function will read data that has been DMAed to memory while transfering from:
+*          - Memory to memory
+*          - Peripheral to memory
+*
+*  @return  0 - No more data is available to read
+*           1 - More data might be available to read
+*
+*/
+/****************************************************************************/
+int dmacHw_readTransferredData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle    */
+                               dmacHw_CONFIG_t *pConfig,        /*  [ IN ]  Configuration settings */
+                               void *pDescriptor,       /*  [ IN ] Descriptor buffer  */
+                               void **ppBbuf,   /*  [ OUT ] Data received */
+                               size_t *pLlen    /*  [ OUT ] Length of the data received */
+    );
+/****************************************************************************/
+/**
+*  @brief   Prepares descriptor ring, when source peripheral working as a flow controller
+*
+*  This function will form the descriptor ring by allocating buffers, when source peripheral
+*  has to work as a flow controller to transfer data from:
+*           - Peripheral to memory.
+*
+*  @return  -1 - On failure
+*            0 - On success
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+int dmacHw_setVariableDataDescriptor(dmacHw_HANDLE_t handle,    /*  [ IN ] DMA Channel handle   */
+                                     dmacHw_CONFIG_t *pConfig,  /*  [ IN ] Configuration settings */
+                                     void *pDescriptor, /*  [ IN ] Descriptor buffer  */
+                                     uint32_t srcAddr,  /*  [ IN ] Source peripheral address */
+                                     void *(*fpAlloc) (int len),        /*  [ IN ] Function pointer  that provides destination memory */
+                                     int len,   /*  [ IN ] Number of bytes "fpAlloc" will allocate for destination */
+                                     int num    /*  [ IN ] Number of descriptor to set */
+    );
+/****************************************************************************/
+/**
+*  @brief   Program channel register to initiate transfer
+*
+*  @return  void
+*
+*
+*  @note
+*     - Descriptor buffer MUST ALWAYS be flushed before calling this function
+*     - This function should also be called from ISR to program the channel with
+*       pending descriptors
+*/
+/****************************************************************************/
+void dmacHw_initiateTransfer(dmacHw_HANDLE_t handle,    /*   [ IN ] DMA Channel handle */
+                             dmacHw_CONFIG_t *pConfig,  /*   [ IN ] Configuration settings */
+                             void *pDescriptor  /*   [ IN ] Descriptor buffer  */
+    );
+/****************************************************************************/
+/**
+*  @brief   Resets descriptor control information
+*
+*  @return  void
+*/
+/****************************************************************************/
+void dmacHw_resetDescriptorControl(void *pDescriptor    /*   [ IN ] Descriptor buffer  */
+    );
+/****************************************************************************/
+/**
+*  @brief   Program channel register to stop transfer
+*
+*  Ensures the channel is not doing any transfer after calling this function
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void dmacHw_stopTransfer(dmacHw_HANDLE_t handle /*   [ IN ] DMA Channel handle */
+    );
+/****************************************************************************/
+/**
+*  @brief   Check the existance of pending descriptor
+*
+*  This function confirmes if there is any pending descriptor in the chain
+*  to program the channel
+*
+*  @return  1 : Channel need to be programmed with pending descriptor
+*           0 : No more pending descriptor to programe the channel
+*
+*  @note
+*     - This function should be called from ISR in case there are pending
+*       descriptor to program the channel.
+*
+*     Example:
+*
+*     dmac_isr ()
+*     {
+*         ...
+*         if (dmacHw_descriptorPending (handle))
+*         {
+*            dmacHw_initiateTransfer (handle);
+*         }
+*     }
+*
+*/
+/****************************************************************************/
+uint32_t dmacHw_descriptorPending(dmacHw_HANDLE_t handle,       /*   [ IN ] DMA Channel handle */
+                                  void *pDescriptor     /*   [ IN ] Descriptor buffer */
+    );
+/****************************************************************************/
+/**
+*  @brief   Deallocates source or destination memory, allocated
+*
+*  This function can be called to deallocate data memory that was DMAed successfully
+*
+*  @return  -1  - On failure
+*            0  - On success
+*
+*  @note
+*     This function will be called ONLY, when source OR destination address is pointing
+*     to dynamic memory
+*/
+/****************************************************************************/
+int dmacHw_freeMem(dmacHw_CONFIG_t *pConfig,    /*  [ IN ] Configuration settings */
+                   void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
+                   void (*fpFree) (void *)      /*  [ IN ] Function pointer to free data memory */
+    );
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the DMA channel specific interrupt
+*
+*  @return   N/A
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void dmacHw_clearInterrupt(dmacHw_HANDLE_t handle       /*  [ IN ] DMA Channel handle  */
+    );
+/****************************************************************************/
+/**
+*  @brief   Returns the cause of channel specific DMA interrupt
+*
+*  This function returns the cause of interrupt
+*
+*  @return  Interrupt status, each bit representing a specific type of interrupt
+*           of type dmacHw_INTERRUPT_STATUS_e
+*  @note
+*           This function should be called under the context of ISR
+*/
+/****************************************************************************/
+dmacHw_INTERRUPT_STATUS_e dmacHw_getInterruptStatus(dmacHw_HANDLE_t handle      /*  [ IN ] DMA Channel handle  */
+    );
+/****************************************************************************/
+/**
+*  @brief   Indentifies a DMA channel causing interrupt
+*
+*  This functions returns a channel causing interrupt of type dmacHw_INTERRUPT_STATUS_e
+*
+*  @return  NULL   : No channel causing DMA interrupt
+*           ! NULL : Handle to a channel causing DMA interrupt
+*  @note
+*     dmacHw_clearInterrupt() must be called with a valid handle after calling this function
+*/
+/****************************************************************************/
+dmacHw_HANDLE_t dmacHw_getInterruptSource(void);
+/****************************************************************************/
+/**
+*  @brief   Sets channel specific user data
+*
+*  This function associates user data to a specif DMA channel
+*
+*/
+/****************************************************************************/
+void dmacHw_setChannelUserData(dmacHw_HANDLE_t handle,  /*  [ IN ] DMA Channel handle  */
+                               void *userData   /*  [ IN ] User data  */
+    );
+/****************************************************************************/
+/**
+*  @brief   Gets channel specific user data
+*
+*  This function returns user data specific to a DMA channel
+*
+*  @return   user data
+*/
+/****************************************************************************/
+void *dmacHw_getChannelUserData(dmacHw_HANDLE_t handle  /*  [ IN ] DMA Channel handle  */
+    );
+/****************************************************************************/
+/**
+*  @brief   Displays channel specific registers and other control parameters
+*
+*
+*  @return  void
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+void dmacHw_printDebugInfo(dmacHw_HANDLE_t handle,      /*  [ IN ] DMA Channel handle  */
+                           void *pDescriptor,   /*  [ IN ] Descriptor buffer  */
+                           int (*fpPrint) (const char *, ...)   /*  [ IN ] Print callback function */
+    );
+/****************************************************************************/
+/**
+*  @brief   Provides DMA controller attributes
+*
+*
+*  @return  DMA controller attributes
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+uint32_t dmacHw_getDmaControllerAttribute(dmacHw_HANDLE_t handle,       /*  [ IN ]  DMA Channel handle  */
+                                          dmacHw_CONTROLLER_ATTRIB_e attr       /*  [ IN ]  DMA Controler attribute of type  dmacHw_CONTROLLER_ATTRIB_e */
+    );
+#endif /* _DMACHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/errno.h b/arch/arm/mach-bcmring/include/csp/errno.h
new file mode 100644
index 000000000000..51357dd5b666
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/errno.h
@@ -0,0 +1,32 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CSP_ERRNO_H
+#define CSP_ERRNO_H
+/* ---- Include Files ---------------------------------------------------- */
+#if   defined(__KERNEL__)
+#include <linux/errno.h>
+#elif defined(CSP_SIMULATION)
+#include <asm-generic/errno.h>
+#else
+#include <errno.h>
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /* CSP_ERRNO_H */
diff --git a/arch/arm/mach-bcmring/include/csp/intcHw.h b/arch/arm/mach-bcmring/include/csp/intcHw.h
new file mode 100644
index 000000000000..1c639c8ee08f
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/intcHw.h
@@ -0,0 +1,40 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    intcHw.h
+*
+*  @brief   generic interrupt controller API
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+#ifndef _INTCHW_H
+#define _INTCHW_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/csp/intcHw_reg.h>
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+static inline void intcHw_irq_disable(void *basep, uint32_t mask);
+static inline void intcHw_irq_enable(void *basep, uint32_t mask);
+#endif /* _INTCHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/module.h b/arch/arm/mach-bcmring/include/csp/module.h
new file mode 100644
index 000000000000..c30d2a5975a6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/module.h
@@ -0,0 +1,32 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CSP_MODULE_H
+#define CSP_MODULE_H
+/* ---- Include Files ---------------------------------------------------- */
+#ifdef __KERNEL__
+    #include <linux/module.h>
+#else
+    #define EXPORT_SYMBOL(symbol)
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /* CSP_MODULE_H */
diff --git a/arch/arm/mach-bcmring/include/csp/reg.h b/arch/arm/mach-bcmring/include/csp/reg.h
new file mode 100644
index 000000000000..e5f60bf5a1f3
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/reg.h
@@ -0,0 +1,114 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    reg.h
+*
+*  @brief   Generic register defintions used in CSP
+*/
+/****************************************************************************/
+#ifndef CSP_REG_H
+#define CSP_REG_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+/* ---- Public Constants and Types --------------------------------------- */
+#define __REG32(x)      (*((volatile uint32_t *)(x)))
+#define __REG16(x)      (*((volatile uint16_t *)(x)))
+#define __REG8(x)       (*((volatile uint8_t *) (x)))
+/* Macros used to define a sequence of reserved registers. The start / end */
+/* are byte offsets in the particular register definition, with the "end" */
+/* being the offset of the next un-reserved register. E.g. if offsets */
+/* 0x10 through to 0x1f are reserved, then this reserved area could be */
+/* specified as follows. */
+/*  typedef struct */
+/*  { */
+/*      uint32_t reg1;           offset 0x00 */
+/*      uint32_t reg2;           offset 0x04 */
+/*      uint32_t reg3;           offset 0x08 */
+/*      uint32_t reg4;           offset 0x0c */
+/*      REG32_RSVD(0x10, 0x20); */
+/*      uint32_t reg5;           offset 0x20 */
+/*      ... */
+/*  } EXAMPLE_REG_t; */
+#define REG8_RSVD(start, end)   uint8_t rsvd_##start[(end - start) / sizeof(uint8_t)]
+#define REG16_RSVD(start, end)  uint16_t rsvd_##start[(end - start) / sizeof(uint16_t)]
+#define REG32_RSVD(start, end)  uint32_t rsvd_##start[(end - start) / sizeof(uint32_t)]
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+/* Note: When protecting multiple statements, the REG_LOCAL_IRQ_SAVE and */
+/* REG_LOCAL_IRQ_RESTORE must be enclosed in { } to allow the  */
+/* flags variable to be declared locally. */
+/* e.g. */
+/*    statement1; */
+/*    { */
+/*       REG_LOCAL_IRQ_SAVE; */
+/*       <multiple statements here> */
+/*       REG_LOCAL_IRQ_RESTORE; */
+/*    } */
+/*    statement2; */
+/*  */
+#if defined(__KERNEL__) && !defined(STANDALONE)
+#include <mach/hardware.h>
+#include <linux/interrupt.h>
+#define REG_LOCAL_IRQ_SAVE      HW_DECLARE_SPINLOCK(reg32) \
+        unsigned long flags; HW_IRQ_SAVE(reg32, flags)
+#define REG_LOCAL_IRQ_RESTORE   HW_IRQ_RESTORE(reg32, flags)
+#else
+#define REG_LOCAL_IRQ_SAVE
+#define REG_LOCAL_IRQ_RESTORE
+#endif
+static inline void reg32_modify_and(volatile uint32_t *reg, uint32_t value)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *reg &= value;
+        REG_LOCAL_IRQ_RESTORE;
+}
+static inline void reg32_modify_or(volatile uint32_t *reg, uint32_t value)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *reg |= value;
+        REG_LOCAL_IRQ_RESTORE;
+}
+static inline void reg32_modify_mask(volatile uint32_t *reg, uint32_t mask,
+                                     uint32_t value)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *reg = (*reg & mask) | value;
+        REG_LOCAL_IRQ_RESTORE;
+}
+static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
+{
+        *reg = value;
+}
+#endif /* CSP_REG_H */
diff --git a/arch/arm/mach-bcmring/include/csp/secHw.h b/arch/arm/mach-bcmring/include/csp/secHw.h
new file mode 100644
index 000000000000..b9d7e0732dfc
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/secHw.h
@@ -0,0 +1,65 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    secHw.h
+*
+*  @brief   Definitions for accessing low level security features
+*
+*/
+/****************************************************************************/
+#ifndef SECHW_H
+#define SECHW_H
+typedef void (*secHw_FUNC_t) (void);
+typedef enum {
+        secHw_MODE_SECURE = 0x0,        /* Switches processor into secure mode */
+        secHw_MODE_NONSECURE = 0x1      /* Switches processor into non-secure mode */
+} secHw_MODE;
+/****************************************************************************/
+/**
+*  @brief   Requesting to execute the function in secure mode
+*
+*  This function requests the given function to run in secure mode
+*
+*/
+/****************************************************************************/
+void secHw_RunSecure(secHw_FUNC_t       /* Function to run in secure mode */
+    );
+/****************************************************************************/
+/**
+*  @brief   Sets the  mode
+*
+*  his function sets the processor mode (secure/non-secure)
+*
+*/
+/****************************************************************************/
+void secHw_SetMode(secHw_MODE   /* Processor mode */
+    );
+/****************************************************************************/
+/**
+*  @brief   Get the current mode
+*
+*  This function retieves the processor mode (secure/non-secure)
+*
+*/
+/****************************************************************************/
+void secHw_GetMode(secHw_MODE *);
+#endif /* SECHW_H */
diff --git a/arch/arm/mach-bcmring/include/csp/stdint.h b/arch/arm/mach-bcmring/include/csp/stdint.h
new file mode 100644
index 000000000000..3a8718bbf700
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/stdint.h
@@ -0,0 +1,30 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CSP_STDINT_H
+#define CSP_STDINT_H
+/* ---- Include Files ---------------------------------------------------- */
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /* CSP_STDINT_H */
diff --git a/arch/arm/mach-bcmring/include/csp/string.h b/arch/arm/mach-bcmring/include/csp/string.h
new file mode 100644
index 000000000000..ad9e4005f141
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/string.h
@@ -0,0 +1,34 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CSP_STRING_H
+#define CSP_STRING_H
+/* ---- Include Files ---------------------------------------------------- */
+#ifdef __KERNEL__
+   #include <linux/string.h>
+#else
+   #include <string.h>
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /* CSP_STRING_H */
diff --git a/arch/arm/mach-bcmring/include/csp/tmrHw.h b/arch/arm/mach-bcmring/include/csp/tmrHw.h
new file mode 100644
index 000000000000..f1236d00cb97
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/csp/tmrHw.h
@@ -0,0 +1,263 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    tmrHw.h
+*
+*  @brief   API definitions for low level Timer driver
+*
+*/
+/****************************************************************************/
+#ifndef _TMRHW_H
+#define _TMRHW_H
+#include <csp/stdint.h>
+typedef uint32_t tmrHw_ID_t;    /* Timer ID */
+typedef uint32_t tmrHw_COUNT_t; /* Timer count */
+typedef uint32_t tmrHw_INTERVAL_t;      /* Timer interval */
+typedef uint32_t tmrHw_RATE_t;  /* Timer event (count/interrupt) rate */
+typedef enum {
+        tmrHw_INTERRUPT_STATUS_SET,     /* Interrupted  */
+        tmrHw_INTERRUPT_STATUS_UNSET    /* No Interrupt */
+} tmrHw_INTERRUPT_STATUS_e;
+typedef enum {
+        tmrHw_CAPABILITY_CLOCK, /* Clock speed in HHz */
+        tmrHw_CAPABILITY_RESOLUTION     /* Timer resolution in bits */
+} tmrHw_CAPABILITY_e;
+/****************************************************************************/
+/**
+*  @brief   Get timer capability
+*
+*  This function returns various capabilities/attributes of a timer
+*
+*  @return  Numeric capability
+*
+*/
+/****************************************************************************/
+uint32_t tmrHw_getTimerCapability(tmrHw_ID_t timerId,   /*  [ IN ] Timer Id */
+                                  tmrHw_CAPABILITY_e capability /*  [ IN ] Timer capability */
+);
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer in terms of timer interrupt rate
+*
+*  This function initializes a periodic timer to generate specific number of
+*  timer interrupt per second
+*
+*  @return   On success: Effective timer frequency
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setPeriodicTimerRate(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                        tmrHw_RATE_t rate       /*  [ IN ] Number of timer interrupt per second */
+);
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt after
+*           certain time interval
+*
+*  This function initializes a periodic timer to generate timer interrupt
+*  after every time interval in milisecond
+*
+*  @return   On success: Effective interval set in mili-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setPeriodicTimerInterval(tmrHw_ID_t timerId,     /*  [ IN ] Timer Id */
+                                                tmrHw_INTERVAL_t msec   /*  [ IN ] Interval in mili-second */
+);
+/****************************************************************************/
+/**
+*  @brief   Configures a periodic timer to generate timer interrupt just once
+*           after certain time interval
+*
+*  This function initializes a periodic timer to generate a single ticks after
+*  certain time interval in milisecond
+*
+*  @return   On success: Effective interval set in mili-second
+*            On failure: 0
+*
+*/
+/****************************************************************************/
+tmrHw_INTERVAL_t tmrHw_setOneshotTimerInterval(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                               tmrHw_INTERVAL_t msec    /*  [ IN ] Interval in mili-second */
+);
+/****************************************************************************/
+/**
+*  @brief   Configures a timer to run as a free running timer
+*
+*  This function initializes a timer to run as a free running timer
+*
+*  @return   Timer resolution (count / sec)
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_setFreeRunningTimer(tmrHw_ID_t timerId,      /*  [ IN ] Timer Id */
+                                       uint32_t divider /*  [ IN ] Dividing the clock frequency */
+) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Starts a timer
+*
+*  This function starts a preconfigured timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*/
+/****************************************************************************/
+int tmrHw_startTimer(tmrHw_ID_t timerId /*  [ IN ] Timer id */
+) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Stops a timer
+*
+*  This function stops a running timer
+*
+*  @return  -1     - On Failure
+*            0     - On Success
+*/
+/****************************************************************************/
+int tmrHw_stopTimer(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+);
+/****************************************************************************/
+/**
+*  @brief   Gets current timer count
+*
+*  This function returns the current timer value
+*
+*  @return  Current downcounting timer value
+*
+*/
+/****************************************************************************/
+tmrHw_COUNT_t tmrHw_GetCurrentCount(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Gets timer count rate
+*
+*  This function returns the number of counts per second
+*
+*  @return  Count rate
+*
+*/
+/****************************************************************************/
+tmrHw_RATE_t tmrHw_getCountRate(tmrHw_ID_t timerId      /*  [ IN ] Timer id */
+) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Enables timer interrupt
+*
+*  This function enables the timer interrupt
+*
+*  @return   N/A
+*
+*/
+/****************************************************************************/
+void tmrHw_enableInterrupt(tmrHw_ID_t timerId   /*  [ IN ] Timer id */
+);
+/****************************************************************************/
+/**
+*  @brief   Disables timer interrupt
+*
+*  This function disable the timer interrupt
+*
+*  @return   N/A
+*/
+/****************************************************************************/
+void tmrHw_disableInterrupt(tmrHw_ID_t timerId  /*  [ IN ] Timer id */
+);
+/****************************************************************************/
+/**
+*  @brief   Clears the interrupt
+*
+*  This function clears the timer interrupt
+*
+*  @return   N/A
+*
+*  @note
+*     Must be called under the context of ISR
+*/
+/****************************************************************************/
+void tmrHw_clearInterrupt(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+);
+/****************************************************************************/
+/**
+*  @brief   Gets the interrupt status
+*
+*  This function returns timer interrupt status
+*
+*  @return   Interrupt status
+*/
+/****************************************************************************/
+tmrHw_INTERRUPT_STATUS_e tmrHw_getInterruptStatus(tmrHw_ID_t timerId    /*  [ IN ] Timer id */
+);
+/****************************************************************************/
+/**
+*  @brief   Indentifies a timer causing interrupt
+*
+*  This functions returns a timer causing interrupt
+*
+*  @return  0xFFFFFFFF   : No timer causing an interrupt
+*           ! 0xFFFFFFFF : timer causing an interrupt
+*  @note
+*     tmrHw_clearIntrrupt() must be called with a valid timer id after calling this function
+*/
+/****************************************************************************/
+tmrHw_ID_t tmrHw_getInterruptSource(void);
+/****************************************************************************/
+/**
+*  @brief   Displays specific timer registers
+*
+*
+*  @return  void
+*
+*/
+/****************************************************************************/
+void tmrHw_printDebugInfo(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                          int (*fpPrint) (const char *, ...)    /*  [ IN ] Print callback function */
+);
+/****************************************************************************/
+/**
+*  @brief   Use a timer to perform a busy wait delay for a number of usecs.
+*
+*  @return   N/A
+*/
+/****************************************************************************/
+void tmrHw_udelay(tmrHw_ID_t timerId,   /*  [ IN ] Timer id */
+                  unsigned long usecs   /*  [ IN ] usec to delay */
+) __attribute__ ((section(".aramtext")));
+#endif /* _TMRHW_H */
diff --git a/arch/arm/mach-bcmring/include/mach/clkdev.h b/arch/arm/mach-bcmring/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap.h b/arch/arm/mach-bcmring/include/mach/csp/cap.h
new file mode 100644
index 000000000000..30fa2d540630
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap.h
@@ -0,0 +1,63 @@
+/*****************************************************************************
+* Copyright 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CAP_H
+#define CAP_H
+/* ---- Include Files ---------------------------------------------------- */
+/* ---- Public Constants and Types --------------------------------------- */
+typedef enum {
+        CAP_NOT_PRESENT = 0,
+        CAP_PRESENT
+} CAP_RC_T;
+typedef enum {
+        CAP_VPM,
+        CAP_ETH_PHY,
+        CAP_ETH_GMII,
+        CAP_ETH_SGMII,
+        CAP_USB,
+        CAP_TSC,
+        CAP_EHSS,
+        CAP_SDIO,
+        CAP_UARTB,
+        CAP_KEYPAD,
+        CAP_CLCD,
+        CAP_GE,
+        CAP_LEDM,
+        CAP_BBL,
+        CAP_VDEC,
+        CAP_PIF,
+        CAP_APM,
+        CAP_SPU,
+        CAP_PKA,
+        CAP_RNG,
+} CAP_CAPABILITY_T;
+typedef enum {
+        CAP_LCD_WVGA = 0,
+        CAP_LCD_VGA = 0x1,
+        CAP_LCD_WQVGA = 0x2,
+        CAP_LCD_QVGA = 0x3
+} CAP_LCD_RES_T;
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index);
+static inline uint32_t cap_getMaxArmSpeedHz(void);
+static inline uint32_t cap_getMaxVpmSpeedHz(void);
+static inline CAP_LCD_RES_T cap_getMaxLcdRes(void);
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
new file mode 100644
index 000000000000..933ce68ed90b
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/cap_inline.h
@@ -0,0 +1,409 @@
+/*****************************************************************************
+* Copyright 2009 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CAP_INLINE_H
+#define CAP_INLINE_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/csp/cap.h>
+#include <cfg_global.h>
+/* ---- Public Constants and Types --------------------------------------- */
+#define CAP_CONFIG0_VPM_DIS          0x00000001
+#define CAP_CONFIG0_ETH_PHY0_DIS     0x00000002
+#define CAP_CONFIG0_ETH_PHY1_DIS     0x00000004
+#define CAP_CONFIG0_ETH_GMII0_DIS    0x00000008
+#define CAP_CONFIG0_ETH_GMII1_DIS    0x00000010
+#define CAP_CONFIG0_ETH_SGMII0_DIS   0x00000020
+#define CAP_CONFIG0_ETH_SGMII1_DIS   0x00000040
+#define CAP_CONFIG0_USB0_DIS         0x00000080
+#define CAP_CONFIG0_USB1_DIS         0x00000100
+#define CAP_CONFIG0_TSC_DIS          0x00000200
+#define CAP_CONFIG0_EHSS0_DIS        0x00000400
+#define CAP_CONFIG0_EHSS1_DIS        0x00000800
+#define CAP_CONFIG0_SDIO0_DIS        0x00001000
+#define CAP_CONFIG0_SDIO1_DIS        0x00002000
+#define CAP_CONFIG0_UARTB_DIS        0x00004000
+#define CAP_CONFIG0_KEYPAD_DIS       0x00008000
+#define CAP_CONFIG0_CLCD_DIS         0x00010000
+#define CAP_CONFIG0_GE_DIS           0x00020000
+#define CAP_CONFIG0_LEDM_DIS         0x00040000
+#define CAP_CONFIG0_BBL_DIS          0x00080000
+#define CAP_CONFIG0_VDEC_DIS         0x00100000
+#define CAP_CONFIG0_PIF_DIS          0x00200000
+#define CAP_CONFIG0_RESERVED1_DIS    0x00400000
+#define CAP_CONFIG0_RESERVED2_DIS    0x00800000
+#define CAP_CONFIG1_APMA_DIS         0x00000001
+#define CAP_CONFIG1_APMB_DIS         0x00000002
+#define CAP_CONFIG1_APMC_DIS         0x00000004
+#define CAP_CONFIG1_CLCD_RES_MASK    0x00000600
+#define CAP_CONFIG1_CLCD_RES_SHIFT   9
+#define CAP_CONFIG1_CLCD_RES_WVGA    (CAP_LCD_WVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+#define CAP_CONFIG1_CLCD_RES_VGA     (CAP_LCD_VGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+#define CAP_CONFIG1_CLCD_RES_WQVGA   (CAP_LCD_WQVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+#define CAP_CONFIG1_CLCD_RES_QVGA    (CAP_LCD_QVGA << CAP_CONFIG1_CLCD_RES_SHIFT)
+#define CAP_CONFIG2_SPU_DIS          0x00000010
+#define CAP_CONFIG2_PKA_DIS          0x00000020
+#define CAP_CONFIG2_RNG_DIS          0x00000080
+#if   (CFG_GLOBAL_CHIP == BCM11107)
+#define capConfig0 0
+#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
+#define capConfig2 0
+#define CAP_APM_MAX_NUM_CHANS 3
+#elif (CFG_GLOBAL_CHIP == FPGA11107)
+#define capConfig0 0
+#define capConfig1 CAP_CONFIG1_CLCD_RES_WVGA
+#define capConfig2 0
+#define CAP_APM_MAX_NUM_CHANS 3
+#elif (CFG_GLOBAL_CHIP == BCM11109)
+#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
+#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
+#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
+#define CAP_APM_MAX_NUM_CHANS 2
+#elif (CFG_GLOBAL_CHIP == BCM11170)
+#define capConfig0 (CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_USB0_DIS | CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_CLCD_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
+#define capConfig1 (CAP_CONFIG1_APMC_DIS | CAP_CONFIG1_CLCD_RES_WQVGA)
+#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
+#define CAP_APM_MAX_NUM_CHANS 2
+#elif (CFG_GLOBAL_CHIP == BCM11110)
+#define capConfig0 (CAP_CONFIG0_USB1_DIS | CAP_CONFIG0_TSC_DIS | CAP_CONFIG0_EHSS1_DIS | CAP_CONFIG0_SDIO0_DIS | CAP_CONFIG0_SDIO1_DIS | CAP_CONFIG0_UARTB_DIS | CAP_CONFIG0_GE_DIS | CAP_CONFIG0_BBL_DIS | CAP_CONFIG0_VDEC_DIS)
+#define capConfig1 CAP_CONFIG1_APMC_DIS
+#define capConfig2 (CAP_CONFIG2_SPU_DIS | CAP_CONFIG2_PKA_DIS)
+#define CAP_APM_MAX_NUM_CHANS 2
+#elif (CFG_GLOBAL_CHIP == BCM11211)
+#define capConfig0 (CAP_CONFIG0_ETH_PHY0_DIS | CAP_CONFIG0_ETH_GMII0_DIS | CAP_CONFIG0_ETH_GMII1_DIS | CAP_CONFIG0_ETH_SGMII0_DIS | CAP_CONFIG0_ETH_SGMII1_DIS | CAP_CONFIG0_CLCD_DIS)
+#define capConfig1 CAP_CONFIG1_APMC_DIS
+#define capConfig2 0
+#define CAP_APM_MAX_NUM_CHANS 2
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
+#define CAP_HW_CFG_ARM_CLK_HZ 500000000
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+#define CAP_HW_CFG_ARM_CLK_HZ 300000000
+#elif (CFG_GLOBAL_CHIP == BCM11211)
+#define CAP_HW_CFG_ARM_CLK_HZ 666666666
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
+#define CAP_HW_CFG_VPM_CLK_HZ 333333333
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+#define CAP_HW_CFG_VPM_CLK_HZ 200000000
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+/****************************************************************************
+*  cap_isPresent -
+*
+*  PURPOSE:
+*     Determines if the chip has a certain capability present
+*
+*  PARAMETERS:
+*     capability - type of capability to determine if present
+*
+*  RETURNS:
+*     CAP_PRESENT or CAP_NOT_PRESENT
+****************************************************************************/
+static inline CAP_RC_T cap_isPresent(CAP_CAPABILITY_T capability, int index)
+{
+        CAP_RC_T returnVal = CAP_NOT_PRESENT;
+        switch (capability) {
+        case CAP_VPM:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_VPM_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_ETH_PHY:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_PHY1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_ETH_GMII:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_GMII1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_ETH_SGMII:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_ETH_SGMII1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_USB:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_USB0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_USB1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_TSC:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_TSC_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_EHSS:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_EHSS0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_EHSS1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_SDIO:
+                {
+                        if ((index == 0)
+                            && (!(capConfig0 & CAP_CONFIG0_SDIO0_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig0 & CAP_CONFIG0_SDIO1_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_UARTB:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_UARTB_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_KEYPAD:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_KEYPAD_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_CLCD:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_CLCD_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_GE:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_GE_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_LEDM:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_LEDM_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_BBL:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_BBL_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_VDEC:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_VDEC_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_PIF:
+                {
+                        if (!(capConfig0 & CAP_CONFIG0_PIF_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_APM:
+                {
+                        if ((index == 0)
+                            && (!(capConfig1 & CAP_CONFIG1_APMA_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 1)
+                            && (!(capConfig1 & CAP_CONFIG1_APMB_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                        if ((index == 2)
+                            && (!(capConfig1 & CAP_CONFIG1_APMC_DIS))) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_SPU:
+                {
+                        if (!(capConfig2 & CAP_CONFIG2_SPU_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_PKA:
+                {
+                        if (!(capConfig2 & CAP_CONFIG2_PKA_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        case CAP_RNG:
+                {
+                        if (!(capConfig2 & CAP_CONFIG2_RNG_DIS)) {
+                                returnVal = CAP_PRESENT;
+                        }
+                }
+                break;
+        default:
+                {
+                }
+                break;
+        }
+        return returnVal;
+}
+/****************************************************************************
+*  cap_getMaxArmSpeedHz -
+*
+*  PURPOSE:
+*     Determines the maximum speed of the ARM CPU
+*
+*  PARAMETERS:
+*     none
+*
+*  RETURNS:
+*     clock speed in Hz that the ARM processor is able to run at
+****************************************************************************/
+static inline uint32_t cap_getMaxArmSpeedHz(void)
+{
+#if   ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == FPGA11107))
+        return 500000000;
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+        return 300000000;
+#elif (CFG_GLOBAL_CHIP == BCM11211)
+        return 666666666;
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+}
+/****************************************************************************
+*  cap_getMaxVpmSpeedHz -
+*
+*  PURPOSE:
+*     Determines the maximum speed of the VPM
+*
+*  PARAMETERS:
+*     none
+*
+*  RETURNS:
+*     clock speed in Hz that the VPM is able to run at
+****************************************************************************/
+static inline uint32_t cap_getMaxVpmSpeedHz(void)
+{
+#if ((CFG_GLOBAL_CHIP == BCM11107) || (CFG_GLOBAL_CHIP == BCM11211) || (CFG_GLOBAL_CHIP == FPGA11107))
+        return 333333333;
+#elif ((CFG_GLOBAL_CHIP == BCM11109) || (CFG_GLOBAL_CHIP == BCM11170) || (CFG_GLOBAL_CHIP == BCM11110))
+        return 200000000;
+#else
+#error CFG_GLOBAL_CHIP type capabilities not defined
+#endif
+}
+/****************************************************************************
+*  cap_getMaxLcdRes -
+*
+*  PURPOSE:
+*     Determines the maximum LCD resolution capabilities
+*
+*  PARAMETERS:
+*     none
+*
+*  RETURNS:
+*   CAP_LCD_WVGA, CAP_LCD_VGA, CAP_LCD_WQVGA or CAP_LCD_QVGA
+*
+****************************************************************************/
+static inline CAP_LCD_RES_T cap_getMaxLcdRes(void)
+{
+        return (CAP_LCD_RES_T)
+                ((capConfig1 & CAP_CONFIG1_CLCD_RES_MASK) >>
+                 CAP_CONFIG1_CLCD_RES_SHIFT);
+}
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
new file mode 100644
index 000000000000..70eaea866cfe
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_def.h
@@ -0,0 +1,1123 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CHIPC_DEF_H
+#define CHIPC_DEF_H
+/* ---- Include Files ----------------------------------------------------- */
+#include <csp/stdint.h>
+#include <csp/errno.h>
+#include <csp/reg.h>
+#include <mach/csp/chipcHw_reg.h>
+/* ---- Public Constants and Types ---------------------------------------- */
+/* Set 1 to configure DDR/VPM phase alignment by HW */
+#define chipcHw_DDR_HW_PHASE_ALIGN    0
+#define chipcHw_VPM_HW_PHASE_ALIGN    0
+typedef uint32_t chipcHw_freq;
+/* Configurable miscellaneous clocks */
+typedef enum {
+        chipcHw_CLOCK_DDR,      /* DDR PHY Clock */
+        chipcHw_CLOCK_ARM,      /* ARM Clock */
+        chipcHw_CLOCK_ESW,      /* Ethernet Switch Clock */
+        chipcHw_CLOCK_VPM,      /* VPM Clock */
+        chipcHw_CLOCK_ESW125,   /* Ethernet MII Clock */
+        chipcHw_CLOCK_UART,     /* UART Clock */
+        chipcHw_CLOCK_SDIO0,    /* SDIO 0 Clock */
+        chipcHw_CLOCK_SDIO1,    /* SDIO 1 Clock */
+        chipcHw_CLOCK_SPI,      /* SPI Clock */
+        chipcHw_CLOCK_ETM,      /* ARM ETM Clock */
+        chipcHw_CLOCK_BUS,      /* BUS Clock */
+        chipcHw_CLOCK_OTP,      /* OTP Clock */
+        chipcHw_CLOCK_I2C,      /* I2C Host Clock */
+        chipcHw_CLOCK_I2S0,     /* I2S 0 Host Clock */
+        chipcHw_CLOCK_RTBUS,    /* DDR PHY Configuration Clock */
+        chipcHw_CLOCK_APM100,   /* APM100 Clock */
+        chipcHw_CLOCK_TSC,      /* Touch screen Clock */
+        chipcHw_CLOCK_LED,      /* LED Clock */
+        chipcHw_CLOCK_USB,      /* USB Clock */
+        chipcHw_CLOCK_LCD,      /* LCD CLock */
+        chipcHw_CLOCK_APM,      /* APM Clock */
+        chipcHw_CLOCK_I2S1,     /* I2S 1 Host Clock */
+} chipcHw_CLOCK_e;
+/* System booting strap options */
+typedef enum {
+        chipcHw_BOOT_DEVICE_UART = chipcHw_STRAPS_BOOT_DEVICE_UART,
+        chipcHw_BOOT_DEVICE_SERIAL_FLASH =
+            chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH,
+        chipcHw_BOOT_DEVICE_NOR_FLASH_16 =
+            chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16,
+        chipcHw_BOOT_DEVICE_NAND_FLASH_8 =
+            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8,
+        chipcHw_BOOT_DEVICE_NAND_FLASH_16 =
+            chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16
+} chipcHw_BOOT_DEVICE_e;
+/* System booting modes */
+typedef enum {
+        chipcHw_BOOT_MODE_NORMAL = chipcHw_STRAPS_BOOT_MODE_NORMAL,
+        chipcHw_BOOT_MODE_DBG_SW = chipcHw_STRAPS_BOOT_MODE_DBG_SW,
+        chipcHw_BOOT_MODE_DBG_BOOT = chipcHw_STRAPS_BOOT_MODE_DBG_BOOT,
+        chipcHw_BOOT_MODE_NORMAL_QUIET = chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET
+} chipcHw_BOOT_MODE_e;
+/* NAND Flash page size strap options */
+typedef enum {
+        chipcHw_NAND_PAGESIZE_512 = chipcHw_STRAPS_NAND_PAGESIZE_512,
+        chipcHw_NAND_PAGESIZE_2048 = chipcHw_STRAPS_NAND_PAGESIZE_2048,
+        chipcHw_NAND_PAGESIZE_4096 = chipcHw_STRAPS_NAND_PAGESIZE_4096,
+        chipcHw_NAND_PAGESIZE_EXT = chipcHw_STRAPS_NAND_PAGESIZE_EXT
+} chipcHw_NAND_PAGESIZE_e;
+/* GPIO Pin function */
+typedef enum {
+        chipcHw_GPIO_FUNCTION_KEYPAD = chipcHw_REG_GPIO_MUX_KEYPAD,
+        chipcHw_GPIO_FUNCTION_I2CH = chipcHw_REG_GPIO_MUX_I2CH,
+        chipcHw_GPIO_FUNCTION_SPI = chipcHw_REG_GPIO_MUX_SPI,
+        chipcHw_GPIO_FUNCTION_UART = chipcHw_REG_GPIO_MUX_UART,
+        chipcHw_GPIO_FUNCTION_LEDMTXP = chipcHw_REG_GPIO_MUX_LEDMTXP,
+        chipcHw_GPIO_FUNCTION_LEDMTXS = chipcHw_REG_GPIO_MUX_LEDMTXS,
+        chipcHw_GPIO_FUNCTION_SDIO0 = chipcHw_REG_GPIO_MUX_SDIO0,
+        chipcHw_GPIO_FUNCTION_SDIO1 = chipcHw_REG_GPIO_MUX_SDIO1,
+        chipcHw_GPIO_FUNCTION_PCM = chipcHw_REG_GPIO_MUX_PCM,
+        chipcHw_GPIO_FUNCTION_I2S = chipcHw_REG_GPIO_MUX_I2S,
+        chipcHw_GPIO_FUNCTION_ETM = chipcHw_REG_GPIO_MUX_ETM,
+        chipcHw_GPIO_FUNCTION_DEBUG = chipcHw_REG_GPIO_MUX_DEBUG,
+        chipcHw_GPIO_FUNCTION_MISC = chipcHw_REG_GPIO_MUX_MISC,
+        chipcHw_GPIO_FUNCTION_GPIO = chipcHw_REG_GPIO_MUX_GPIO
+} chipcHw_GPIO_FUNCTION_e;
+/* PIN Output slew rate */
+typedef enum {
+        chipcHw_PIN_SLEW_RATE_HIGH = chipcHw_REG_SLEW_RATE_HIGH,
+        chipcHw_PIN_SLEW_RATE_NORMAL = chipcHw_REG_SLEW_RATE_NORMAL
+} chipcHw_PIN_SLEW_RATE_e;
+/* PIN Current drive strength */
+typedef enum {
+        chipcHw_PIN_CURRENT_STRENGTH_2mA = chipcHw_REG_CURRENT_STRENGTH_2mA,
+        chipcHw_PIN_CURRENT_STRENGTH_4mA = chipcHw_REG_CURRENT_STRENGTH_4mA,
+        chipcHw_PIN_CURRENT_STRENGTH_6mA = chipcHw_REG_CURRENT_STRENGTH_6mA,
+        chipcHw_PIN_CURRENT_STRENGTH_8mA = chipcHw_REG_CURRENT_STRENGTH_8mA,
+        chipcHw_PIN_CURRENT_STRENGTH_10mA = chipcHw_REG_CURRENT_STRENGTH_10mA,
+        chipcHw_PIN_CURRENT_STRENGTH_12mA = chipcHw_REG_CURRENT_STRENGTH_12mA
+} chipcHw_PIN_CURRENT_STRENGTH_e;
+/* PIN Pull up register settings */
+typedef enum {
+        chipcHw_PIN_PULL_NONE = chipcHw_REG_PULL_NONE,
+        chipcHw_PIN_PULL_UP = chipcHw_REG_PULL_UP,
+        chipcHw_PIN_PULL_DOWN = chipcHw_REG_PULL_DOWN
+} chipcHw_PIN_PULL_e;
+/* PIN input type settings */
+typedef enum {
+        chipcHw_PIN_INPUTTYPE_CMOS = chipcHw_REG_INPUTTYPE_CMOS,
+        chipcHw_PIN_INPUTTYPE_ST = chipcHw_REG_INPUTTYPE_ST
+} chipcHw_PIN_INPUTTYPE_e;
+/* Allow/Disalow the support of spread spectrum  */
+typedef enum {
+        chipcHw_SPREAD_SPECTRUM_DISALLOW,       /* Spread spectrum support is not allowed */
+        chipcHw_SPREAD_SPECTRUM_ALLOW   /* Spread spectrum support is allowed */
+} chipcHw_SPREAD_SPECTRUM_e;
+typedef struct {
+        chipcHw_SPREAD_SPECTRUM_e ssSupport;    /* Allow/Disalow to support spread spectrum.
+                                                   If supported, call chipcHw_enableSpreadSpectrum ()
+                                                   to activate the spread spectrum with desired spread. */
+        uint32_t pllVcoFreqHz;  /* PLL VCO frequency in Hz */
+        uint32_t pll2VcoFreqHz; /* PLL2 VCO frequency in Hz */
+        uint32_t busClockFreqHz;        /* Bus clock frequency in Hz */
+        uint32_t armBusRatio;   /* ARM clock : Bus clock */
+        uint32_t vpmBusRatio;   /* VPM clock : Bus clock */
+        uint32_t ddrBusRatio;   /* DDR clock : Bus clock */
+} chipcHw_INIT_PARAM_t;
+/* CHIP revision number */
+typedef enum {
+        chipcHw_REV_NUMBER_A0 = chipcHw_REG_REV_A0,
+        chipcHw_REV_NUMBER_B0 = chipcHw_REG_REV_B0
+} chipcHw_REV_NUMBER_e;
+typedef enum {
+        chipcHw_VPM_HW_PHASE_INTR_DISABLE = chipcHw_REG_VPM_INTR_DISABLE,
+        chipcHw_VPM_HW_PHASE_INTR_FAST = chipcHw_REG_VPM_INTR_FAST,
+        chipcHw_VPM_HW_PHASE_INTR_MEDIUM = chipcHw_REG_VPM_INTR_MEDIUM,
+        chipcHw_VPM_HW_PHASE_INTR_SLOW = chipcHw_REG_VPM_INTR_SLOW
+} chipcHw_VPM_HW_PHASE_INTR_e;
+typedef enum {
+        chipcHw_DDR_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for DDR phase align condition */
+        chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for DDR phase align condition */
+        chipcHw_DDR_HW_PHASE_MARGIN_WIDE        /*  Wider margin for DDR phase align condition */
+} chipcHw_DDR_HW_PHASE_MARGIN_e;
+typedef enum {
+        chipcHw_VPM_HW_PHASE_MARGIN_STRICT,     /*  Strict margin for VPM phase align condition */
+        chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM,     /*  Medium margin for VPM phase align condition */
+        chipcHw_VPM_HW_PHASE_MARGIN_WIDE        /*  Wider margin for VPM phase align condition */
+} chipcHw_VPM_HW_PHASE_MARGIN_e;
+#define chipcHw_XTAL_FREQ_Hz                    25000000        /* Reference clock frequency in Hz */
+/* Programable pin defines */
+#define chipcHw_PIN_GPIO(n)                     ((((n) >= 0) && ((n) < (chipcHw_GPIO_COUNT))) ? (n) : 0xFFFFFFFF)
+                                                                             /* GPIO pin 0 - 60 */
+#define chipcHw_PIN_UARTTXD                     (chipcHw_GPIO_COUNT + 0)        /* UART Transmit */
+#define chipcHw_PIN_NVI_A                       (chipcHw_GPIO_COUNT + 1)        /* NVI Interface */
+#define chipcHw_PIN_NVI_D                       (chipcHw_GPIO_COUNT + 2)        /* NVI Interface */
+#define chipcHw_PIN_NVI_OEB                     (chipcHw_GPIO_COUNT + 3)        /* NVI Interface */
+#define chipcHw_PIN_NVI_WEB                     (chipcHw_GPIO_COUNT + 4)        /* NVI Interface */
+#define chipcHw_PIN_NVI_CS                      (chipcHw_GPIO_COUNT + 5)        /* NVI Interface */
+#define chipcHw_PIN_NVI_NAND_CSB                (chipcHw_GPIO_COUNT + 6)        /* NVI Interface */
+#define chipcHw_PIN_NVI_FLASHWP                 (chipcHw_GPIO_COUNT + 7)        /* NVI Interface */
+#define chipcHw_PIN_NVI_NAND_RDYB               (chipcHw_GPIO_COUNT + 8)        /* NVI Interface */
+#define chipcHw_PIN_CL_DATA_0_17                (chipcHw_GPIO_COUNT + 9)        /* LCD Data 0 - 17 */
+#define chipcHw_PIN_CL_DATA_18_20               (chipcHw_GPIO_COUNT + 10)       /* LCD Data 18 - 20 */
+#define chipcHw_PIN_CL_DATA_21_23               (chipcHw_GPIO_COUNT + 11)       /* LCD Data 21 - 23 */
+#define chipcHw_PIN_CL_POWER                    (chipcHw_GPIO_COUNT + 12)       /* LCD Power */
+#define chipcHw_PIN_CL_ACK                      (chipcHw_GPIO_COUNT + 13)       /* LCD Ack */
+#define chipcHw_PIN_CL_FP                       (chipcHw_GPIO_COUNT + 14)       /* LCD FP */
+#define chipcHw_PIN_CL_LP                       (chipcHw_GPIO_COUNT + 15)       /* LCD LP */
+#define chipcHw_PIN_UARTRXD                     (chipcHw_GPIO_COUNT + 16)       /* UART Receive */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+/****************************************************************************/
+/**
+*  @brief  Initializes the clock module
+*
+*/
+/****************************************************************************/
+void chipcHw_Init(chipcHw_INIT_PARAM_t *initParam       /*  [ IN ] Misc chip initialization parameter */
+    ) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief  Enables the PLL1
+*
+*  This function enables the PLL1
+*
+*/
+/****************************************************************************/
+void chipcHw_pll1Enable(uint32_t vcoFreqHz,     /*  [ IN ] VCO frequency in Hz */
+                        chipcHw_SPREAD_SPECTRUM_e ssSupport     /*  [ IN ] SS status */
+    ) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief  Enables the PLL2
+*
+*  This function enables the PLL2
+*
+*/
+/****************************************************************************/
+void chipcHw_pll2Enable(uint32_t vcoFreqHz      /*  [ IN ] VCO frequency in Hz */
+    ) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL1
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll1Disable(void);
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL2
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll2Disable(void);
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in KHz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_getClockFrequency(chipcHw_CLOCK_e clock    /*  [ IN ] Configurable clock */
+    ) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Set clock fequency for miscellaneous configurable clocks
+*
+*  This function sets clock frequency
+*
+*  @return  Configured clock frequency in Hz
+*
+*/
+/****************************************************************************/
+chipcHw_freq chipcHw_setClockFrequency(chipcHw_CLOCK_e clock,   /*  [ IN ] Configurable clock */
+                                       uint32_t freq    /*  [ IN ] Clock frequency in Hz */
+    ) __attribute__ ((section(".aramtext")));
+/****************************************************************************/
+/**
+*  @brief   Set VPM clock in sync with BUS clock
+*
+*  This function does the phase adjustment between VPM and BUS clock
+*
+*  @return >= 0 : On success ( # of adjustment required )
+*            -1 : On failure
+*/
+/****************************************************************************/
+int chipcHw_vpmPhaseAlign(void);
+/****************************************************************************/
+/**
+*  @brief   Enables core a clock of a certain device
+*
+*  This function enables a core clock
+*
+*  @return  void
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock /*  [ IN ] Configurable clock */
+    );
+/****************************************************************************/
+/**
+*  @brief   Disabled a core clock of a certain device
+*
+*  This function disables a core clock
+*
+*  @return  void
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock        /*  [ IN ] Configurable clock */
+    );
+/****************************************************************************/
+/**
+*  @brief   Enables bypass clock of a certain device
+*
+*  This function enables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock      /*  [ IN ] Configurable clock */
+    );
+/****************************************************************************/
+/**
+*  @brief   Disabled bypass clock of a certain device
+*
+*  This function disables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock     /*  [ IN ] Configurable clock */
+    );
+/****************************************************************************/
+/**
+*  @brief   Get Numeric Chip ID
+*
+*  This function returns Chip ID that includes the revison number
+*
+*  @return  Complete numeric Chip ID
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipId(void);
+/****************************************************************************/
+/**
+*  @brief   Get Chip Product ID
+*
+*  This function returns Chip Product ID
+*
+*  @return  Chip Product ID
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipProductId(void);
+/****************************************************************************/
+/**
+*  @brief   Get revision number
+*
+*  This function returns revision number of the chip
+*
+*  @return  Revision number
+*/
+/****************************************************************************/
+static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void);
+/****************************************************************************/
+/**
+*  @brief   Enables bus interface clock
+*
+*  Enables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockEnable(uint32_t mask        /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief   Disables bus interface clock
+*
+*  Disables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockDisable(uint32_t mask       /*  [ IN ] Bit map of type  chipcHw_REG_BUS_CLOCK_XXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief   Enables various audio channels
+*
+*  Enables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelEnable(uint32_t mask     /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief   Disables various audio channels
+*
+*  Disables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelDisable(uint32_t mask    /*  [ IN ] Bit map of type  chipcHw_REG_AUDIO_CHANNEL_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief    Soft resets devices
+*
+*  Soft resets various devices
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
+*/
+/****************************************************************************/
+static inline void chipcHw_softReset(uint64_t mask      /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
+    );
+static inline void chipcHw_softResetDisable(uint64_t mask       /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
+    );
+static inline void chipcHw_softResetEnable(uint64_t mask        /*  [ IN ] Bit map of type chipcHw_REG_SOFT_RESET_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief    Configures misc CHIP functionality
+*
+*  Configures CHIP functionality
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_miscControl(uint32_t mask    /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
+    );
+static inline void chipcHw_miscControlDisable(uint32_t mask     /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
+    );
+static inline void chipcHw_miscControlEnable(uint32_t mask      /*  [ IN ] Bit map of type chipcHw_REG_MISC_CTRL_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief    Set OTP options
+*
+*  Set OTP options
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_OTP_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setOTPOption(uint64_t mask   /*  [ IN ] Bit map of type chipcHw_REG_OTP_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief    Get sticky bits
+*
+*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getStickyBits(void);
+/****************************************************************************/
+/**
+*  @brief    Set sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setStickyBits(uint32_t mask  /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief    Clear sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_clearStickyBits(uint32_t mask        /*  [ IN ] Bit map of type chipcHw_REG_STICKY_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief    Get software override strap options
+*
+*  Retrieves software override strap options
+*
+*  @return   Software override strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getSoftStraps(void);
+/****************************************************************************/
+/**
+*  @brief    Set software override strap options
+*
+*  set software override strap options
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setSoftStraps(uint32_t strapOptions);
+/****************************************************************************/
+/**
+*  @brief    Get pin strap options
+*
+*  Retrieves pin strap options
+*
+*  @return   Pin strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getPinStraps(void);
+/****************************************************************************/
+/**
+*  @brief    Get valid pin strap options
+*
+*  Retrieves valid pin strap options
+*
+*  @return   valid Pin strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getValidStraps(void);
+/****************************************************************************/
+/**
+*  @brief    Initialize valid pin strap options
+*
+*  Retrieves valid pin strap options by copying HW strap options to soft register
+*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_initValidStraps(void);
+/****************************************************************************/
+/**
+*  @brief   Get status (enabled/disabled) of bus interface clock
+*
+*  This function returns the status of devices' bus interface clock
+*
+*  @return  Bus interface clock
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getBusInterfaceClockStatus(void);
+/****************************************************************************/
+/**
+*  @brief   Get boot device
+*
+*  This function returns the device type used in booting the system
+*
+*  @return  Boot device of type chipcHw_BOOT_DEVICE_e
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void);
+/****************************************************************************/
+/**
+*  @brief   Get boot mode
+*
+*  This function returns the way the system was booted
+*
+*  @return  Boot mode of type chipcHw_BOOT_MODE_e
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void);
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash page size
+*
+*  This function returns the NAND device page size
+*
+*  @return  Boot NAND device page size
+*
+*/
+/****************************************************************************/
+static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void);
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash address cycle configuration
+*
+*  This function returns the NAND flash address cycle configuration
+*
+*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
+*
+*/
+/****************************************************************************/
+static inline int chipcHw_getNandExtraCycle(void);
+/****************************************************************************/
+/**
+*  @brief   Activates PIF interface
+*
+*  This function activates PIF interface by taking control of LCD pins
+*
+*  @note
+*       When activated, LCD pins will be defined as follows for PIF operation
+*
+*       CLD[17:0]  = pif_data[17:0]
+*       CLD[23:18] = pif_address[5:0]
+*       CLPOWER    = pif_wr_str
+*       CLCP       = pif_rd_str
+*       CLAC       = pif_hat1
+*       CLFP       = pif_hrdy1
+*       CLLP       = pif_hat2
+*       GPIO[42]   = pif_hrdy2
+*
+*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_activatePifInterface(void);
+/****************************************************************************/
+/**
+*  @brief   Activates LCD interface
+*
+*  This function activates LCD interface
+*
+*  @note
+*       When activated, LCD pins will be defined as follows
+*
+*       CLD[17:0]  = LCD data
+*       CLD[23:18] = LCD data
+*       CLPOWER    = LCD power
+*       CLCP       =
+*       CLAC       = LCD ack
+*       CLFP       =
+*       CLLP       =
+*/
+/****************************************************************************/
+static inline void chipcHw_activateLcdInterface(void);
+/****************************************************************************/
+/**
+*  @brief   Deactivates PIF/LCD interface
+*
+*  This function deactivates PIF/LCD interface
+*
+*  @note
+*       When deactivated LCD pins will be in rti-stated
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_deactivatePifLcdInterface(void);
+/****************************************************************************/
+/**
+*  @brief   Get to know the configuration of GPIO pin
+*
+*/
+/****************************************************************************/
+static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin        /* GPIO Pin number */
+    );
+/****************************************************************************/
+/**
+*  @brief   Configure GPIO pin function
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setGpioPinFunction(int pin,  /* GPIO Pin number */
+                                              chipcHw_GPIO_FUNCTION_e func      /* Configuration function */
+    );
+/****************************************************************************/
+/**
+*  @brief   Set Pin slew rate
+*
+*  This function sets the slew of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinSlewRate(uint32_t pin, /* Pin of type chipcHw_PIN_XXXXX */
+                                          chipcHw_PIN_SLEW_RATE_e slewRate      /* Pin slew rate */
+    );
+/****************************************************************************/
+/**
+*  @brief   Set Pin output drive current
+*
+*  This function sets output drive current of individual pin
+*
+*  Note: Avoid the use of the word 'current' since linux headers define this
+*        to be the current task.
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinOutputCurrent(uint32_t pin,    /* Pin of type chipcHw_PIN_XXXXX */
+                                               chipcHw_PIN_CURRENT_STRENGTH_e curr      /* Pin current rating */
+    );
+/****************************************************************************/
+/**
+*  @brief   Set Pin pullup register
+*
+*  This function sets pullup register of individual  pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinPullup(uint32_t pin,   /* Pin of type chipcHw_PIN_XXXXX */
+                                        chipcHw_PIN_PULL_e pullup       /* Pullup register settings */
+    );
+/****************************************************************************/
+/**
+*  @brief   Set Pin input type
+*
+*  This function sets input type of individual Pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinInputType(uint32_t pin,        /* Pin of type chipcHw_PIN_XXXXX */
+                                           chipcHw_PIN_INPUTTYPE_e inputType    /* Pin input type */
+    );
+/****************************************************************************/
+/**
+*  @brief   Retrieves a string representation of the mux setting for a pin.
+*
+*  @return  Pointer to a character string.
+*/
+/****************************************************************************/
+const char *chipcHw_getGpioPinFunctionStr(int pin);
+/****************************************************************************/
+/**  @brief issue warmReset
+ */
+/****************************************************************************/
+void chipcHw_reset(uint32_t mask);
+/****************************************************************************/
+/**  @brief clock reconfigure
+ */
+/****************************************************************************/
+void chipcHw_clockReconfig(uint32_t busHz, uint32_t armRatio, uint32_t vpmRatio,
+                           uint32_t ddrRatio);
+/****************************************************************************/
+/**
+*  @brief   Enable Spread Spectrum
+*
+*  @note chipcHw_Init() must be called earlier
+*/
+/****************************************************************************/
+static inline void chipcHw_enableSpreadSpectrum(void);
+/****************************************************************************/
+/**
+*  @brief   Disable Spread Spectrum
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_disableSpreadSpectrum(void);
+/****************************************************************************/
+/**  @brief Checks if software strap is enabled
+ *
+ *   @return 1 : When enable
+ *           0 : When disable
+ */
+/****************************************************************************/
+static inline int chipcHw_isSoftwareStrapsEnable(void);
+/****************************************************************************/
+/**  @brief Enable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsEnable(void);
+/****************************************************************************/
+/**  @brief Disable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsDisable(void);
+/****************************************************************************/
+/**  @brief PLL test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestEnable(void);
+/****************************************************************************/
+/**  @brief PLL2 test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestEnable(void);
+/****************************************************************************/
+/**  @brief PLL test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestDisable(void);
+/****************************************************************************/
+/**  @brief PLL2 test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestDisable(void);
+/****************************************************************************/
+/**  @brief Get PLL test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPllTestEnable(void);
+/****************************************************************************/
+/**  @brief Get PLL2 test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPll2TestEnable(void);
+/****************************************************************************/
+/**  @brief PLL test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestSelect(uint32_t val);
+/****************************************************************************/
+/**  @brief PLL2 test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestSelect(uint32_t val);
+/****************************************************************************/
+/**  @brief Get PLL test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPllTestSelected(void);
+/****************************************************************************/
+/**  @brief Get PLL2 test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPll2TestSelected(void);
+/****************************************************************************/
+/**
+*  @brief   Enables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptEnable(void);
+/****************************************************************************/
+/**
+*  @brief   Disables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptDisable(void);
+/****************************************************************************/
+/**
+*  @brief   Set VPM SW phase alignment interrupt mode
+*
+*  This function sets VPM phase alignment interrupt
+*
+*/
+/****************************************************************************/
+static inline void
+chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode);
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignEnable(void);
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignDisable(void);
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignEnable(void);
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignDisable(void);
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignEnable(void);
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignDisable(void);
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignEnable(void);
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignDisable(void);
+/****************************************************************************/
+/**
+*  @brief   Set DDR phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin        /* Margin alinging DDR  phase */
+    );
+/****************************************************************************/
+/**
+*  @brief   Set VPM phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin        /* Margin alinging VPM  phase */
+    );
+/****************************************************************************/
+/**
+*  @brief   Checks DDR phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isDdrHwPhaseAligned(void);
+/****************************************************************************/
+/**
+*  @brief   Checks VPM phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isVpmHwPhaseAligned(void);
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void);
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void);
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrPhaseControl(void);
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmPhaseControl(void);
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a DDR phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
+    );
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a VPM phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle     /* Timeout in bus cycle */
+    );
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void);
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void);
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void);
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void);
+/****************************************************************************/
+/**
+*  @brief   Clear DDR phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void);
+/****************************************************************************/
+/**
+*  @brief   Clear VPM phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void);
+/* ---- Private Constants and Types -------------------------------------- */
+#endif /* CHIPC_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
new file mode 100644
index 000000000000..c78833acb37a
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_inline.h
@@ -0,0 +1,1673 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CHIPC_INLINE_H
+#define CHIPC_INLINE_H
+/* ---- Include Files ----------------------------------------------------- */
+#include <csp/errno.h>
+#include <csp/reg.h>
+#include <mach/csp/chipcHw_reg.h>
+#include <mach/csp/chipcHw_def.h>
+/* ---- Private Constants and Types --------------------------------------- */
+typedef enum {
+        chipcHw_OPTYPE_BYPASS,  /* Bypass operation */
+        chipcHw_OPTYPE_OUTPUT   /* Output operation */
+} chipcHw_OPTYPE_e;
+/* ---- Public Constants and Types ---------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------- */
+/* ---- Public Function Prototypes ---------------------------------------- */
+/* ---- Private Function Prototypes --------------------------------------- */
+static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
+                                    chipcHw_OPTYPE_e type, int mode);
+/****************************************************************************/
+/**
+*  @brief   Get Numeric Chip ID
+*
+*  This function returns Chip ID that includes the revison number
+*
+*  @return  Complete numeric Chip ID
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipId(void)
+{
+        return pChipcHw->ChipId;
+}
+/****************************************************************************/
+/**
+*  @brief   Enable Spread Spectrum
+*
+*  @note chipcHw_Init() must be called earlier
+*/
+/****************************************************************************/
+static inline void chipcHw_enableSpreadSpectrum(void)
+{
+        if ((pChipcHw->
+             PLLPreDivider & chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK) !=
+            chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER) {
+                ddrcReg_PHY_ADDR_CTL_REGP->ssCfg =
+                    (0xFFFF << ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT) |
+                    (ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK <<
+                     ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT);
+                ddrcReg_PHY_ADDR_CTL_REGP->ssCtl |=
+                    ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Disable Spread Spectrum
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_disableSpreadSpectrum(void)
+{
+        ddrcReg_PHY_ADDR_CTL_REGP->ssCtl &= ~ddrcReg_PHY_ADDR_SS_CTRL_ENABLE;
+}
+/****************************************************************************/
+/**
+*  @brief   Get Chip Product ID
+*
+*  This function returns Chip Product ID
+*
+*  @return  Chip Product ID
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getChipProductId(void)
+{
+        return (pChipcHw->
+                 ChipId & chipcHw_REG_CHIPID_BASE_MASK) >>
+                chipcHw_REG_CHIPID_BASE_SHIFT;
+}
+/****************************************************************************/
+/**
+*  @brief   Get revision number
+*
+*  This function returns revision number of the chip
+*
+*  @return  Revision number
+*/
+/****************************************************************************/
+static inline chipcHw_REV_NUMBER_e chipcHw_getChipRevisionNumber(void)
+{
+        return pChipcHw->ChipId & chipcHw_REG_CHIPID_REV_MASK;
+}
+/****************************************************************************/
+/**
+*  @brief   Enables bus interface clock
+*
+*  Enables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX for mask
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockEnable(uint32_t mask)
+{
+        reg32_modify_or(&pChipcHw->BusIntfClock, mask);
+}
+/****************************************************************************/
+/**
+*  @brief   Disables bus interface clock
+*
+*  Disables  bus interface clock of various device
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_BUS_CLOCK_XXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_busInterfaceClockDisable(uint32_t mask)
+{
+        reg32_modify_and(&pChipcHw->BusIntfClock, ~mask);
+}
+/****************************************************************************/
+/**
+*  @brief   Get status (enabled/disabled) of bus interface clock
+*
+*  This function returns the status of devices' bus interface clock
+*
+*  @return  Bus interface clock
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getBusInterfaceClockStatus(void)
+{
+        return pChipcHw->BusIntfClock;
+}
+/****************************************************************************/
+/**
+*  @brief   Enables various audio channels
+*
+*  Enables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelEnable(uint32_t mask)
+{
+        reg32_modify_or(&pChipcHw->AudioEnable, mask);
+}
+/****************************************************************************/
+/**
+*  @brief   Disables various audio channels
+*
+*  Disables audio channel
+*
+*  @return  void
+*
+*  @note    use chipcHw_REG_AUDIO_CHANNEL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_audioChannelDisable(uint32_t mask)
+{
+        reg32_modify_and(&pChipcHw->AudioEnable, ~mask);
+}
+/****************************************************************************/
+/**
+*  @brief    Soft resets devices
+*
+*  Soft resets various devices
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_SOFT_RESET_XXXXXX defines
+*/
+/****************************************************************************/
+static inline void chipcHw_softReset(uint64_t mask)
+{
+        chipcHw_softResetEnable(mask);
+        chipcHw_softResetDisable(mask);
+}
+static inline void chipcHw_softResetDisable(uint64_t mask)
+{
+        uint32_t ctrl1 = (uint32_t) mask;
+        uint32_t ctrl2 = (uint32_t) (mask >> 32);
+        /* Deassert module soft reset */
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->SoftReset1 ^= ctrl1;
+        pChipcHw->SoftReset2 ^= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+        REG_LOCAL_IRQ_RESTORE;
+}
+static inline void chipcHw_softResetEnable(uint64_t mask)
+{
+        uint32_t ctrl1 = (uint32_t) mask;
+        uint32_t ctrl2 = (uint32_t) (mask >> 32);
+        uint32_t unhold = 0;
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->SoftReset1 |= ctrl1;
+        /* Mask out unhold request bits */
+        pChipcHw->SoftReset2 |= (ctrl2 & (~chipcHw_REG_SOFT_RESET_UNHOLD_MASK));
+        /* Process unhold requests */
+        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD) {
+                unhold = chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD;
+        }
+        if (ctrl2 & chipcHw_REG_SOFT_RESET_VPM_UNHOLD) {
+                unhold |= chipcHw_REG_SOFT_RESET_VPM_HOLD;
+        }
+        if (ctrl2 & chipcHw_REG_SOFT_RESET_ARM_UNHOLD) {
+                unhold |= chipcHw_REG_SOFT_RESET_ARM_HOLD;
+        }
+        if (unhold) {
+                /* Make sure unhold request is effective */
+                pChipcHw->SoftReset1 &= ~unhold;
+        }
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief    Configures misc CHIP functionality
+*
+*  Configures CHIP functionality
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_MISC_CTRL_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_miscControl(uint32_t mask)
+{
+        reg32_write(&pChipcHw->MiscCtrl, mask);
+}
+static inline void chipcHw_miscControlDisable(uint32_t mask)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl, ~mask);
+}
+static inline void chipcHw_miscControlEnable(uint32_t mask)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl, mask);
+}
+/****************************************************************************/
+/**
+*  @brief    Set OTP options
+*
+*  Set OTP options
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_OTP_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setOTPOption(uint64_t mask)
+{
+        uint32_t ctrl1 = (uint32_t) mask;
+        uint32_t ctrl2 = (uint32_t) (mask >> 32);
+        reg32_modify_or(&pChipcHw->SoftOTP1, ctrl1);
+        reg32_modify_or(&pChipcHw->SoftOTP2, ctrl2);
+}
+/****************************************************************************/
+/**
+*  @brief    Get sticky bits
+*
+*  @return   Sticky bit options of type chipcHw_REG_STICKY_XXXXXX
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getStickyBits(void)
+{
+        return pChipcHw->Sticky;
+}
+/****************************************************************************/
+/**
+*  @brief    Set sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_setStickyBits(uint32_t mask)
+{
+        uint32_t bits = 0;
+        REG_LOCAL_IRQ_SAVE;
+        if (mask & chipcHw_REG_STICKY_POR_BROM) {
+                bits |= chipcHw_REG_STICKY_POR_BROM;
+        } else {
+                uint32_t sticky;
+                sticky = pChipcHw->Sticky;
+                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
+                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE) == 0) {
+                        bits |= chipcHw_REG_STICKY_BOOT_DONE;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_1) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_1;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_2) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_2;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_3) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_3;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_4) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_4;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_5) == 0) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_5;
+                }
+        }
+        pChipcHw->Sticky = bits;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief    Clear sticky bits
+*
+*  @return   void
+*
+*  @note     use chipcHw_REG_STICKY_XXXXXX
+*/
+/****************************************************************************/
+static inline void chipcHw_clearStickyBits(uint32_t mask)
+{
+        uint32_t bits = 0;
+        REG_LOCAL_IRQ_SAVE;
+        if (mask &
+            (chipcHw_REG_STICKY_BOOT_DONE | chipcHw_REG_STICKY_GENERAL_1 |
+             chipcHw_REG_STICKY_GENERAL_2 | chipcHw_REG_STICKY_GENERAL_3 |
+             chipcHw_REG_STICKY_GENERAL_4 | chipcHw_REG_STICKY_GENERAL_5)) {
+                uint32_t sticky = pChipcHw->Sticky;
+                if ((mask & chipcHw_REG_STICKY_BOOT_DONE)
+                    && (sticky & chipcHw_REG_STICKY_BOOT_DONE)) {
+                        bits = chipcHw_REG_STICKY_BOOT_DONE;
+                        mask &= ~chipcHw_REG_STICKY_BOOT_DONE;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_1)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_1)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_1;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_1;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_2)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_2)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_2;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_2;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_3)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_3)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_3;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_3;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_4)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_4)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_4;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_4;
+                }
+                if ((mask & chipcHw_REG_STICKY_GENERAL_5)
+                    && (sticky & chipcHw_REG_STICKY_GENERAL_5)) {
+                        bits |= chipcHw_REG_STICKY_GENERAL_5;
+                        mask &= ~chipcHw_REG_STICKY_GENERAL_5;
+                }
+        }
+        pChipcHw->Sticky = bits | mask;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief    Get software strap value
+*
+*  Retrieves software strap value
+*
+*  @return   Software strap value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getSoftStraps(void)
+{
+        return pChipcHw->SoftStraps;
+}
+/****************************************************************************/
+/**
+*  @brief    Set software override strap options
+*
+*  set software override strap options
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setSoftStraps(uint32_t strapOptions)
+{
+        reg32_write(&pChipcHw->SoftStraps, strapOptions);
+}
+/****************************************************************************/
+/**
+*  @brief   Get Pin Strap Options
+*
+*  This function returns the raw boot strap options
+*
+*  @return  strap options
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getPinStraps(void)
+{
+        return pChipcHw->PinStraps;
+}
+/****************************************************************************/
+/**
+*  @brief   Get Valid Strap Options
+*
+*  This function returns the valid raw boot strap options
+*
+*  @return  strap options
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getValidStraps(void)
+{
+        uint32_t softStraps;
+        /*
+         ** Always return the SoftStraps - bootROM calls chipcHw_initValidStraps
+         ** which copies HW straps to soft straps if there is no override
+         */
+        softStraps = chipcHw_getSoftStraps();
+        return softStraps;
+}
+/****************************************************************************/
+/**
+*  @brief    Initialize valid pin strap options
+*
+*  Retrieves valid pin strap options by copying HW strap options to soft register
+*  (if chipcHw_STRAPS_SOFT_OVERRIDE not set)
+*
+*  @return   nothing
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_initValidStraps(void)
+{
+        uint32_t softStraps;
+        REG_LOCAL_IRQ_SAVE;
+        softStraps = chipcHw_getSoftStraps();
+        if ((softStraps & chipcHw_STRAPS_SOFT_OVERRIDE) == 0) {
+                /* Copy HW straps to software straps */
+                chipcHw_setSoftStraps(chipcHw_getPinStraps());
+        }
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Get boot device
+*
+*  This function returns the device type used in booting the system
+*
+*  @return  Boot device of type chipcHw_BOOT_DEVICE
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_DEVICE_e chipcHw_getBootDevice(void)
+{
+        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_DEVICE_MASK;
+}
+/****************************************************************************/
+/**
+*  @brief   Get boot mode
+*
+*  This function returns the way the system was booted
+*
+*  @return  Boot mode of type chipcHw_BOOT_MODE
+*
+*/
+/****************************************************************************/
+static inline chipcHw_BOOT_MODE_e chipcHw_getBootMode(void)
+{
+        return chipcHw_getValidStraps() & chipcHw_STRAPS_BOOT_MODE_MASK;
+}
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash page size
+*
+*  This function returns the NAND device page size
+*
+*  @return  Boot NAND device page size
+*
+*/
+/****************************************************************************/
+static inline chipcHw_NAND_PAGESIZE_e chipcHw_getNandPageSize(void)
+{
+        return chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_PAGESIZE_MASK;
+}
+/****************************************************************************/
+/**
+*  @brief   Get NAND flash address cycle configuration
+*
+*  This function returns the NAND flash address cycle configuration
+*
+*  @return  0 = Do not extra address cycle, 1 = Add extra cycle
+*
+*/
+/****************************************************************************/
+static inline int chipcHw_getNandExtraCycle(void)
+{
+        if (chipcHw_getValidStraps() & chipcHw_STRAPS_NAND_EXTRA_CYCLE) {
+                return 1;
+        } else {
+                return 0;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Activates PIF interface
+*
+*  This function activates PIF interface by taking control of LCD pins
+*
+*  @note
+*       When activated, LCD pins will be defined as follows for PIF operation
+*
+*       CLD[17:0]  = pif_data[17:0]
+*       CLD[23:18] = pif_address[5:0]
+*       CLPOWER    = pif_wr_str
+*       CLCP       = pif_rd_str
+*       CLAC       = pif_hat1
+*       CLFP       = pif_hrdy1
+*       CLLP       = pif_hat2
+*       GPIO[42]   = pif_hrdy2
+*
+*       In PIF mode, "pif_hrdy2" overrides other shared function for GPIO[42] pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_activatePifInterface(void)
+{
+        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_PIF_PIN_ENABLE);
+}
+/****************************************************************************/
+/**
+*  @brief   Activates LCD interface
+*
+*  This function activates LCD interface
+*
+*  @note
+*       When activated, LCD pins will be defined as follows
+*
+*       CLD[17:0]  = LCD data
+*       CLD[23:18] = LCD data
+*       CLPOWER    = LCD power
+*       CLCP       =
+*       CLAC       = LCD ack
+*       CLFP       =
+*       CLLP       =
+*/
+/****************************************************************************/
+static inline void chipcHw_activateLcdInterface(void)
+{
+        reg32_write(&pChipcHw->LcdPifMode, chipcHw_REG_LCD_PIN_ENABLE);
+}
+/****************************************************************************/
+/**
+*  @brief   Deactivates PIF/LCD interface
+*
+*  This function deactivates PIF/LCD interface
+*
+*  @note
+*       When deactivated LCD pins will be in rti-stated
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_deactivatePifLcdInterface(void)
+{
+        reg32_write(&pChipcHw->LcdPifMode, 0);
+}
+/****************************************************************************/
+/**
+*  @brief   Select GE2
+*
+*  This function select GE2 as the graphic engine
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_selectGE2(void)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl, ~chipcHw_REG_MISC_CTRL_GE_SEL);
+}
+/****************************************************************************/
+/**
+*  @brief   Select GE3
+*
+*  This function select GE3 as the graphic engine
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_selectGE3(void)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl, chipcHw_REG_MISC_CTRL_GE_SEL);
+}
+/****************************************************************************/
+/**
+*  @brief   Get to know the configuration of GPIO pin
+*
+*/
+/****************************************************************************/
+static inline chipcHw_GPIO_FUNCTION_e chipcHw_getGpioPinFunction(int pin)
+{
+        return (*((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &
+                (chipcHw_REG_GPIO_MUX_MASK <<
+                 chipcHw_REG_GPIO_MUX_POSITION(pin))) >>
+            chipcHw_REG_GPIO_MUX_POSITION(pin);
+}
+/****************************************************************************/
+/**
+*  @brief   Configure GPIO pin function
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setGpioPinFunction(int pin,
+                                              chipcHw_GPIO_FUNCTION_e func)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) &=
+            ~(chipcHw_REG_GPIO_MUX_MASK << chipcHw_REG_GPIO_MUX_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_GPIO_MUX(pin)) |=
+            func << chipcHw_REG_GPIO_MUX_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Set Pin slew rate
+*
+*  This function sets the slew of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinSlewRate(uint32_t pin,
+                                          chipcHw_PIN_SLEW_RATE_e slewRate)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) &=
+            ~(chipcHw_REG_SLEW_RATE_MASK <<
+              chipcHw_REG_SLEW_RATE_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_SLEW_RATE(pin)) |=
+            (uint32_t) slewRate << chipcHw_REG_SLEW_RATE_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Set Pin output drive current
+*
+*  This function sets output drive current of individual pin
+*
+*  Note: Avoid the use of the word 'current' since linux headers define this
+*        to be the current task.
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinOutputCurrent(uint32_t pin,
+                                               chipcHw_PIN_CURRENT_STRENGTH_e
+                                               curr)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_CURRENT(pin)) &=
+            ~(chipcHw_REG_CURRENT_MASK << chipcHw_REG_CURRENT_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_CURRENT(pin)) |=
+            (uint32_t) curr << chipcHw_REG_CURRENT_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Set Pin pullup register
+*
+*  This function sets pullup register of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinPullup(uint32_t pin, chipcHw_PIN_PULL_e pullup)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_PULLUP(pin)) &=
+            ~(chipcHw_REG_PULLUP_MASK << chipcHw_REG_PULLUP_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_PULLUP(pin)) |=
+            (uint32_t) pullup << chipcHw_REG_PULLUP_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Set Pin input type
+*
+*  This function sets input type of individual pin
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setPinInputType(uint32_t pin,
+                                           chipcHw_PIN_INPUTTYPE_e inputType)
+{
+        REG_LOCAL_IRQ_SAVE;
+        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) &=
+            ~(chipcHw_REG_INPUTTYPE_MASK <<
+              chipcHw_REG_INPUTTYPE_POSITION(pin));
+        *((uint32_t *) chipcHw_REG_INPUTTYPE(pin)) |=
+            (uint32_t) inputType << chipcHw_REG_INPUTTYPE_POSITION(pin);
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Power up the USB PHY
+*
+*  This function powers up the USB PHY
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_powerUpUsbPhy(void)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl,
+                         chipcHw_REG_MISC_CTRL_USB_POWERON);
+}
+/****************************************************************************/
+/**
+*  @brief   Power down the USB PHY
+*
+*  This function powers down the USB PHY
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_powerDownUsbPhy(void)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl,
+                        chipcHw_REG_MISC_CTRL_USB_POWEROFF);
+}
+/****************************************************************************/
+/**
+*  @brief   Set the 2nd USB as host
+*
+*  This function sets the 2nd USB as host
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setUsbHost(void)
+{
+        reg32_modify_or(&pChipcHw->MiscCtrl,
+                        chipcHw_REG_MISC_CTRL_USB_MODE_HOST);
+}
+/****************************************************************************/
+/**
+*  @brief   Set the 2nd USB as device
+*
+*  This function sets the 2nd USB as device
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setUsbDevice(void)
+{
+        reg32_modify_and(&pChipcHw->MiscCtrl,
+                         chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE);
+}
+/****************************************************************************/
+/**
+*  @brief   Lower layer funtion to enable/disable a clock of a certain device
+*
+*  This function enables/disables a core clock
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_setClock(chipcHw_CLOCK_e clock,
+                                    chipcHw_OPTYPE_e type, int mode)
+{
+        volatile uint32_t *pPLLReg = (uint32_t *) 0x0;
+        volatile uint32_t *pClockCtrl = (uint32_t *) 0x0;
+        switch (clock) {
+        case chipcHw_CLOCK_DDR:
+                pPLLReg = &pChipcHw->DDRClock;
+                break;
+        case chipcHw_CLOCK_ARM:
+                pPLLReg = &pChipcHw->ARMClock;
+                break;
+        case chipcHw_CLOCK_ESW:
+                pPLLReg = &pChipcHw->ESWClock;
+                break;
+        case chipcHw_CLOCK_VPM:
+                pPLLReg = &pChipcHw->VPMClock;
+                break;
+        case chipcHw_CLOCK_ESW125:
+                pPLLReg = &pChipcHw->ESW125Clock;
+                break;
+        case chipcHw_CLOCK_UART:
+                pPLLReg = &pChipcHw->UARTClock;
+                break;
+        case chipcHw_CLOCK_SDIO0:
+                pPLLReg = &pChipcHw->SDIO0Clock;
+                break;
+        case chipcHw_CLOCK_SDIO1:
+                pPLLReg = &pChipcHw->SDIO1Clock;
+                break;
+        case chipcHw_CLOCK_SPI:
+                pPLLReg = &pChipcHw->SPIClock;
+                break;
+        case chipcHw_CLOCK_ETM:
+                pPLLReg = &pChipcHw->ETMClock;
+                break;
+        case chipcHw_CLOCK_USB:
+                pPLLReg = &pChipcHw->USBClock;
+                if (type == chipcHw_OPTYPE_OUTPUT) {
+                        if (mode) {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        } else {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        }
+                }
+                break;
+        case chipcHw_CLOCK_LCD:
+                pPLLReg = &pChipcHw->LCDClock;
+                if (type == chipcHw_OPTYPE_OUTPUT) {
+                        if (mode) {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        } else {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        }
+                }
+                break;
+        case chipcHw_CLOCK_APM:
+                pPLLReg = &pChipcHw->APMClock;
+                if (type == chipcHw_OPTYPE_OUTPUT) {
+                        if (mode) {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        } else {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_POWER_DOWN);
+                        }
+                }
+                break;
+        case chipcHw_CLOCK_BUS:
+                pClockCtrl = &pChipcHw->ACLKClock;
+                break;
+        case chipcHw_CLOCK_OTP:
+                pClockCtrl = &pChipcHw->OTPClock;
+                break;
+        case chipcHw_CLOCK_I2C:
+                pClockCtrl = &pChipcHw->I2CClock;
+                break;
+        case chipcHw_CLOCK_I2S0:
+                pClockCtrl = &pChipcHw->I2S0Clock;
+                break;
+        case chipcHw_CLOCK_RTBUS:
+                pClockCtrl = &pChipcHw->RTBUSClock;
+                break;
+        case chipcHw_CLOCK_APM100:
+                pClockCtrl = &pChipcHw->APM100Clock;
+                break;
+        case chipcHw_CLOCK_TSC:
+                pClockCtrl = &pChipcHw->TSCClock;
+                break;
+        case chipcHw_CLOCK_LED:
+                pClockCtrl = &pChipcHw->LEDClock;
+                break;
+        case chipcHw_CLOCK_I2S1:
+                pClockCtrl = &pChipcHw->I2S1Clock;
+                break;
+        }
+        if (pPLLReg) {
+                switch (type) {
+                case chipcHw_OPTYPE_OUTPUT:
+                        /* PLL clock output enable/disable */
+                        if (mode) {
+                                if (clock == chipcHw_CLOCK_DDR) {
+                                        /* DDR clock enable is inverted */
+                                        reg32_modify_and(pPLLReg,
+                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                } else {
+                                        reg32_modify_or(pPLLReg,
+                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                }
+                        } else {
+                                if (clock == chipcHw_CLOCK_DDR) {
+                                        /* DDR clock disable is inverted */
+                                        reg32_modify_or(pPLLReg,
+                                                        chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                } else {
+                                        reg32_modify_and(pPLLReg,
+                                                         ~chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE);
+                                }
+                        }
+                        break;
+                case chipcHw_OPTYPE_BYPASS:
+                        /* PLL clock bypass enable/disable */
+                        if (mode) {
+                                reg32_modify_or(pPLLReg,
+                                                chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                        } else {
+                                reg32_modify_and(pPLLReg,
+                                                 ~chipcHw_REG_PLL_CLOCK_BYPASS_SELECT);
+                        }
+                        break;
+                }
+        } else if (pClockCtrl) {
+                switch (type) {
+                case chipcHw_OPTYPE_OUTPUT:
+                        if (mode) {
+                                reg32_modify_or(pClockCtrl,
+                                                chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
+                        } else {
+                                reg32_modify_and(pClockCtrl,
+                                                 ~chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE);
+                        }
+                        break;
+                case chipcHw_OPTYPE_BYPASS:
+                        if (mode) {
+                                reg32_modify_or(pClockCtrl,
+                                                chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
+                        } else {
+                                reg32_modify_and(pClockCtrl,
+                                                 ~chipcHw_REG_DIV_CLOCK_BYPASS_SELECT);
+                        }
+                        break;
+                }
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Disables a core clock of a certain device
+*
+*  This function disables a core clock
+*
+*  @note    no change in power consumption
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockDisable(chipcHw_CLOCK_e clock)
+{
+        /* Disable output of the clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 0);
+}
+/****************************************************************************/
+/**
+*  @brief   Enable a core clock of a certain device
+*
+*  This function enables a core clock
+*
+*  @note    no change in power consumption
+*/
+/****************************************************************************/
+static inline void chipcHw_setClockEnable(chipcHw_CLOCK_e clock)
+{
+        /* Enable output of the clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_OUTPUT, 1);
+}
+/****************************************************************************/
+/**
+*  @brief   Enables bypass clock of a certain device
+*
+*  This function enables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockEnable(chipcHw_CLOCK_e clock)
+{
+        /* Enable bypass clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 1);
+}
+/****************************************************************************/
+/**
+*  @brief   Disabled bypass clock of a certain device
+*
+*  This function disables bypass clock
+*
+*  @note    Doesnot affect the bus interface clock
+*/
+/****************************************************************************/
+static inline void chipcHw_bypassClockDisable(chipcHw_CLOCK_e clock)
+{
+        /* Disable bypass clock */
+        chipcHw_setClock(clock, chipcHw_OPTYPE_BYPASS, 0);
+}
+/****************************************************************************/
+/**  @brief Checks if software strap is enabled
+ *
+ *   @return 1 : When enable
+ *           0 : When disable
+ */
+/****************************************************************************/
+static inline int chipcHw_isSoftwareStrapsEnable(void)
+{
+        return pChipcHw->SoftStraps & 0x00000001;
+}
+/****************************************************************************/
+/**  @brief Enable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsEnable(void)
+{
+        reg32_modify_or(&pChipcHw->SoftStraps, 0x00000001);
+}
+/****************************************************************************/
+/**  @brief Disable software strap
+ */
+/****************************************************************************/
+static inline void chipcHw_softwareStrapsDisable(void)
+{
+        reg32_modify_and(&pChipcHw->SoftStraps, (~0x00000001));
+}
+/****************************************************************************/
+/**  @brief PLL test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestEnable(void)
+{
+        reg32_modify_or(&pChipcHw->PLLConfig,
+                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+/****************************************************************************/
+/**  @brief PLL2 test enable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestEnable(void)
+{
+        reg32_modify_or(&pChipcHw->PLLConfig2,
+                        chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+/****************************************************************************/
+/**  @brief PLL test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestDisable(void)
+{
+        reg32_modify_and(&pChipcHw->PLLConfig,
+                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+/****************************************************************************/
+/**  @brief PLL2 test disable
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestDisable(void)
+{
+        reg32_modify_and(&pChipcHw->PLLConfig2,
+                         ~chipcHw_REG_PLL_CONFIG_TEST_ENABLE);
+}
+/****************************************************************************/
+/**  @brief Get PLL test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPllTestEnable(void)
+{
+        return pChipcHw->PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+}
+/****************************************************************************/
+/**  @brief Get PLL2 test status
+ */
+/****************************************************************************/
+static inline int chipcHw_isPll2TestEnable(void)
+{
+        return pChipcHw->PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_ENABLE;
+}
+/****************************************************************************/
+/**  @brief PLL test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pllTestSelect(uint32_t val)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
+        pChipcHw->PLLConfig |=
+            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**  @brief PLL2 test select
+ */
+/****************************************************************************/
+static inline void chipcHw_pll2TestSelect(uint32_t val)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig2 &= ~chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK;
+        pChipcHw->PLLConfig2 |=
+            (val) << chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**  @brief Get PLL test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPllTestSelected(void)
+{
+        return (uint8_t) ((pChipcHw->
+                           PLLConfig & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
+}
+/****************************************************************************/
+/**  @brief Get PLL2 test selected option
+ */
+/****************************************************************************/
+static inline uint8_t chipcHw_getPll2TestSelected(void)
+{
+        return (uint8_t) ((pChipcHw->
+                           PLLConfig2 & chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK)
+                          >> chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT);
+}
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL1
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll1Disable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief  Disable the PLL2
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_pll2Disable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->PLLConfig2 |= chipcHw_REG_PLL_CONFIG_POWER_DOWN;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Enables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->Spare1 |= chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Disables DDR SW phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrPhaseAlignInterruptDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Set VPM SW phase alignment interrupt mode
+*
+*  This function sets VPM phase alignment interrupt
+*/
+/****************************************************************************/
+static inline void
+chipcHw_vpmPhaseAlignInterruptMode(chipcHw_VPM_HW_PHASE_INTR_e mode)
+{
+        REG_LOCAL_IRQ_SAVE;
+        if (mode == chipcHw_VPM_HW_PHASE_INTR_DISABLE) {
+                pChipcHw->Spare1 &= ~chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
+        } else {
+                pChipcHw->Spare1 |= chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE;
+        }
+        pChipcHw->VPMPhaseCtrl2 =
+            (pChipcHw->
+             VPMPhaseCtrl2 & ~(chipcHw_REG_VPM_INTR_SELECT_MASK <<
+                               chipcHw_REG_VPM_INTR_SELECT_SHIFT)) | mode;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrSwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Enable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 |= chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Disable DDR phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl1 &= ~chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in software
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmSwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Enable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 |= chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Disable VPM phase alignment in hardware
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl1 &= ~chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Set DDR phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void
+chipcHw_setDdrHwPhaseAlignMargin(chipcHw_DDR_HW_PHASE_MARGIN_e margin)
+{
+        uint32_t ge = 0;
+        uint32_t le = 0;
+        switch (margin) {
+        case chipcHw_DDR_HW_PHASE_MARGIN_STRICT:
+                ge = 0x0F;
+                le = 0x0F;
+                break;
+        case chipcHw_DDR_HW_PHASE_MARGIN_MEDIUM:
+                ge = 0x03;
+                le = 0x3F;
+                break;
+        case chipcHw_DDR_HW_PHASE_MARGIN_WIDE:
+                ge = 0x01;
+                le = 0x7F;
+                break;
+        }
+        {
+                REG_LOCAL_IRQ_SAVE;
+                pChipcHw->DDRPhaseCtrl1 &=
+                    ~((chipcHw_REG_DDR_PHASE_VALUE_GE_MASK <<
+                       chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
+                      || (chipcHw_REG_DDR_PHASE_VALUE_LE_MASK <<
+                          chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
+                pChipcHw->DDRPhaseCtrl1 |=
+                    ((ge << chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT)
+                     || (le << chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT));
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Set VPM phase alignment margin in hardware
+*
+*/
+/****************************************************************************/
+static inline void
+chipcHw_setVpmHwPhaseAlignMargin(chipcHw_VPM_HW_PHASE_MARGIN_e margin)
+{
+        uint32_t ge = 0;
+        uint32_t le = 0;
+        switch (margin) {
+        case chipcHw_VPM_HW_PHASE_MARGIN_STRICT:
+                ge = 0x0F;
+                le = 0x0F;
+                break;
+        case chipcHw_VPM_HW_PHASE_MARGIN_MEDIUM:
+                ge = 0x03;
+                le = 0x3F;
+                break;
+        case chipcHw_VPM_HW_PHASE_MARGIN_WIDE:
+                ge = 0x01;
+                le = 0x7F;
+                break;
+        }
+        {
+                REG_LOCAL_IRQ_SAVE;
+                pChipcHw->VPMPhaseCtrl1 &=
+                    ~((chipcHw_REG_VPM_PHASE_VALUE_GE_MASK <<
+                       chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
+                      || (chipcHw_REG_VPM_PHASE_VALUE_LE_MASK <<
+                          chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
+                pChipcHw->VPMPhaseCtrl1 |=
+                    ((ge << chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT)
+                     || (le << chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT));
+                REG_LOCAL_IRQ_RESTORE;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief   Checks DDR phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isDdrHwPhaseAligned(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_ALIGNED) ? 1 : 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Checks VPM phase aligned status done by HW
+*
+*  @return  1: When aligned
+*           0: When not aligned
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_isVpmHwPhaseAligned(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_ALIGNED) ? 1 : 0;
+}
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrHwPhaseAlignStatus(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_STATUS_MASK) >>
+            chipcHw_REG_DDR_PHASE_STATUS_SHIFT;
+}
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase aligned status done by HW
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmHwPhaseAlignStatus(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_STATUS_MASK) >>
+            chipcHw_REG_VPM_PHASE_STATUS_SHIFT;
+}
+/****************************************************************************/
+/**
+*  @brief   Get DDR phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getDdrPhaseControl(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_DDR_PHASE_CTRL_MASK) >>
+            chipcHw_REG_DDR_PHASE_CTRL_SHIFT;
+}
+/****************************************************************************/
+/**
+*  @brief   Get VPM phase control value
+*
+*/
+/****************************************************************************/
+static inline uint32_t chipcHw_getVpmPhaseControl(void)
+{
+        return (pChipcHw->
+                PhaseAlignStatus & chipcHw_REG_VPM_PHASE_CTRL_MASK) >>
+            chipcHw_REG_VPM_PHASE_CTRL_SHIFT;
+}
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a DDR phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeout(uint32_t busCycle)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl2 &=
+            ~(chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK <<
+              chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT);
+        pChipcHw->DDRPhaseCtrl2 |=
+            (busCycle & chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK) <<
+            chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout count
+*
+*  @note    If HW fails to perform the phase alignment, it will trigger
+*           a VPM phase alignment timeout interrupt.
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeout(uint32_t busCycle)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl2 &=
+            ~(chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK <<
+              chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT);
+        pChipcHw->VPMPhaseCtrl2 |=
+            (busCycle & chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK) <<
+            chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Clear DDR phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        /* Clear timeout interrupt service bit */
+        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_INTR_SERVICED;
+        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_INTR_SERVICED;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   Clear VPM phase alignment timeout interrupt
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        /* Clear timeout interrupt service bit */
+        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_INTR_SERVICED;
+        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_INTR_SERVICED;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        chipcHw_ddrHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
+        /* Enable timeout interrupt */
+        pChipcHw->DDRPhaseCtrl2 |= chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt enable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptEnable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        chipcHw_vpmHwPhaseAlignTimeoutInterruptClear(); /* Recommended */
+        /* Enable timeout interrupt */
+        pChipcHw->VPMPhaseCtrl2 |= chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   DDR phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_ddrHwPhaseAlignTimeoutInterruptDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->DDRPhaseCtrl2 &= ~chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+/****************************************************************************/
+/**
+*  @brief   VPM phase alignment timeout interrupt disable
+*
+*/
+/****************************************************************************/
+static inline void chipcHw_vpmHwPhaseAlignTimeoutInterruptDisable(void)
+{
+        REG_LOCAL_IRQ_SAVE;
+        pChipcHw->VPMPhaseCtrl2 &= ~chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE;
+        REG_LOCAL_IRQ_RESTORE;
+}
+#endif /* CHIPC_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
new file mode 100644
index 000000000000..b162448f613c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/chipcHw_reg.h
@@ -0,0 +1,530 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    chipcHw_reg.h
+*
+*  @brief   Definitions for low level chip control registers
+*
+*/
+/****************************************************************************/
+#ifndef CHIPCHW_REG_H
+#define CHIPCHW_REG_H
+#include <mach/csp/mm_io.h>
+#include <csp/reg.h>
+#include <mach/csp/ddrcReg.h>
+#define chipcHw_BASE_ADDRESS    MM_IO_BASE_CHIPC
+typedef struct {
+        uint32_t ChipId;        /* Chip ID */
+        uint32_t DDRClock;      /* PLL1 Channel 1 for DDR clock */
+        uint32_t ARMClock;      /* PLL1 Channel 2 for ARM clock */
+        uint32_t ESWClock;      /* PLL1 Channel 3 for ESW system clock */
+        uint32_t VPMClock;      /* PLL1 Channel 4 for VPM clock */
+        uint32_t ESW125Clock;   /* PLL1 Channel 5 for ESW 125MHz clock */
+        uint32_t UARTClock;     /* PLL1 Channel 6 for UART clock */
+        uint32_t SDIO0Clock;    /* PLL1 Channel 7 for SDIO 0 clock */
+        uint32_t SDIO1Clock;    /* PLL1 Channel 8 for SDIO 1 clock */
+        uint32_t SPIClock;      /* PLL1 Channel 9 for SPI master Clock  */
+        uint32_t ETMClock;      /* PLL1 Channel 10 for ARM ETM Clock  */
+        uint32_t ACLKClock;     /* ACLK Clock (Divider) */
+        uint32_t OTPClock;      /* OTP Clock  (Divider) */
+        uint32_t I2CClock;      /* I2C Clock (CK_13m) (Divider) */
+        uint32_t I2S0Clock;     /* I2S0 Clock (Divider) */
+        uint32_t RTBUSClock;    /* RTBUS (DDR PHY Config.) Clock (Divider) */
+        uint32_t pad1;
+        uint32_t APM100Clock;   /* APM 100MHz CLK Clock (Divider) */
+        uint32_t TSCClock;      /* TSC Clock (Divider) */
+        uint32_t LEDClock;      /* LED Clock (Divider) */
+        uint32_t USBClock;      /* PLL2 Channel 1 for USB clock */
+        uint32_t LCDClock;      /* PLL2 Channel 2 for LCD clock */
+        uint32_t APMClock;      /* PLL2 Channel 3 for APM 200 MHz clock */
+        uint32_t BusIntfClock;  /* Bus interface clock */
+        uint32_t PLLStatus;     /* PLL status register (PLL1) */
+        uint32_t PLLConfig;     /* PLL configuration register  (PLL1) */
+        uint32_t PLLPreDivider; /* PLL pre-divider control register (PLL1) */
+        uint32_t PLLDivider;    /* PLL divider control register (PLL1) */
+        uint32_t PLLControl1;   /* PLL analog control register #1 (PLL1) */
+        uint32_t PLLControl2;   /* PLL analog control register #2 (PLL1) */
+        uint32_t I2S1Clock;     /* I2S1 Clock  */
+        uint32_t AudioEnable;   /* Enable/ disable audio channel */
+        uint32_t SoftReset1;    /* Reset blocks */
+        uint32_t SoftReset2;    /* Reset blocks */
+        uint32_t Spare1;        /* Phase align interrupts */
+        uint32_t Sticky;        /* Sticky bits */
+        uint32_t MiscCtrl;      /* Misc. control */
+        uint32_t pad3[3];
+        uint32_t PLLStatus2;    /* PLL status register (PLL2) */
+        uint32_t PLLConfig2;    /* PLL configuration register  (PLL2) */
+        uint32_t PLLPreDivider2;        /* PLL pre-divider control register (PLL2) */
+        uint32_t PLLDivider2;   /* PLL divider control register (PLL2) */
+        uint32_t PLLControl12;  /* PLL analog control register #1 (PLL2) */
+        uint32_t PLLControl22;  /* PLL analog control register #2 (PLL2) */
+        uint32_t DDRPhaseCtrl1; /* DDR Clock Phase Alignment control1 */
+        uint32_t VPMPhaseCtrl1; /* VPM Clock Phase Alignment control1 */
+        uint32_t PhaseAlignStatus;      /* DDR/VPM Clock Phase Alignment Status */
+        uint32_t PhaseCtrlStatus;       /* DDR/VPM Clock HW DDR/VPM ph_ctrl and load_ch Status */
+        uint32_t DDRPhaseCtrl2; /* DDR Clock Phase Alignment control2 */
+        uint32_t VPMPhaseCtrl2; /* VPM Clock Phase Alignment control2 */
+        uint32_t pad4[9];
+        uint32_t SoftOTP1;      /* Software OTP control */
+        uint32_t SoftOTP2;      /* Software OTP control */
+        uint32_t SoftStraps;    /* Software strap */
+        uint32_t PinStraps;     /* Pin Straps */
+        uint32_t DiffOscCtrl;   /* Diff oscillator control */
+        uint32_t DiagsCtrl;     /* Diagnostic control */
+        uint32_t DiagsOutputCtrl;       /* Diagnostic output enable */
+        uint32_t DiagsReadBackCtrl;     /* Diagnostic read back control */
+        uint32_t LcdPifMode;    /* LCD/PIF Pin Sharing MUX Mode */
+        uint32_t GpioMux_0_7;   /* Pin Sharing MUX0 Control */
+        uint32_t GpioMux_8_15;  /* Pin Sharing MUX1 Control */
+        uint32_t GpioMux_16_23; /* Pin Sharing MUX2 Control */
+        uint32_t GpioMux_24_31; /* Pin Sharing MUX3 Control */
+        uint32_t GpioMux_32_39; /* Pin Sharing MUX4 Control */
+        uint32_t GpioMux_40_47; /* Pin Sharing MUX5 Control */
+        uint32_t GpioMux_48_55; /* Pin Sharing MUX6 Control */
+        uint32_t GpioMux_56_63; /* Pin Sharing MUX7 Control */
+        uint32_t GpioSR_0_7;    /* Slew rate for GPIO 0 - 7 */
+        uint32_t GpioSR_8_15;   /* Slew rate for GPIO 8 - 15 */
+        uint32_t GpioSR_16_23;  /* Slew rate for GPIO 16 - 23 */
+        uint32_t GpioSR_24_31;  /* Slew rate for GPIO 24 - 31 */
+        uint32_t GpioSR_32_39;  /* Slew rate for GPIO 32 - 39 */
+        uint32_t GpioSR_40_47;  /* Slew rate for GPIO 40 - 47 */
+        uint32_t GpioSR_48_55;  /* Slew rate for GPIO 48 - 55 */
+        uint32_t GpioSR_56_63;  /* Slew rate for GPIO 56 - 63 */
+        uint32_t MiscSR_0_7;    /* Slew rate for MISC 0 - 7 */
+        uint32_t MiscSR_8_15;   /* Slew rate for MISC 8 - 15 */
+        uint32_t GpioPull_0_15; /* Pull up registers for GPIO 0 - 15 */
+        uint32_t GpioPull_16_31;        /* Pull up registers for GPIO 16 - 31 */
+        uint32_t GpioPull_32_47;        /* Pull up registers for GPIO 32 - 47 */
+        uint32_t GpioPull_48_63;        /* Pull up registers for GPIO 48 - 63 */
+        uint32_t MiscPull_0_15; /* Pull up registers for MISC 0 - 15 */
+        uint32_t GpioInput_0_31;        /* Input type for GPIO 0 - 31 */
+        uint32_t GpioInput_32_63;       /* Input type for GPIO 32 - 63 */
+        uint32_t MiscInput_0_15;        /* Input type for MISC 0 - 16 */
+} chipcHw_REG_t;
+#define pChipcHw  ((volatile chipcHw_REG_t *) chipcHw_BASE_ADDRESS)
+#define pChipcPhysical  ((volatile chipcHw_REG_t *) MM_ADDR_IO_CHIPC)
+#define chipcHw_REG_CHIPID_BASE_MASK                    0xFFFFF000
+#define chipcHw_REG_CHIPID_BASE_SHIFT                   12
+#define chipcHw_REG_CHIPID_REV_MASK                     0x00000FFF
+#define chipcHw_REG_REV_A0                              0xA00
+#define chipcHw_REG_REV_B0                              0x0B0
+#define chipcHw_REG_PLL_STATUS_CONTROL_ENABLE           0x80000000      /* Allow controlling PLL registers */
+#define chipcHw_REG_PLL_STATUS_LOCKED                   0x00000001      /* PLL is settled */
+#define chipcHw_REG_PLL_CONFIG_D_RESET                  0x00000008      /* Digital reset */
+#define chipcHw_REG_PLL_CONFIG_A_RESET                  0x00000004      /* Analog reset */
+#define chipcHw_REG_PLL_CONFIG_BYPASS_ENABLE            0x00000020      /* Bypass enable */
+#define chipcHw_REG_PLL_CONFIG_OUTPUT_ENABLE            0x00000010      /* Output enable */
+#define chipcHw_REG_PLL_CONFIG_POWER_DOWN               0x00000001      /* Power down */
+#define chipcHw_REG_PLL_CONFIG_VCO_SPLIT_FREQ           1600000000      /* 1.6GHz VCO split frequency */
+#define chipcHw_REG_PLL_CONFIG_VCO_800_1600             0x00000000      /* VCO range 800-1600 MHz */
+#define chipcHw_REG_PLL_CONFIG_VCO_1601_3200            0x00000080      /* VCO range 1601-3200 MHz */
+#define chipcHw_REG_PLL_CONFIG_TEST_ENABLE              0x00010000      /* PLL test output enable */
+#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_MASK         0x003E0000      /* Mask to set test values */
+#define chipcHw_REG_PLL_CONFIG_TEST_SELECT_SHIFT        17
+#define chipcHw_REG_PLL_CLOCK_PHASE_COMP                0x00800000      /* Phase comparator output */
+#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_MASK         0x00300000      /* Clock to bus ratio mask */
+#define chipcHw_REG_PLL_CLOCK_TO_BUS_RATIO_SHIFT        20      /* Number of bits to be shifted */
+#define chipcHw_REG_PLL_CLOCK_POWER_DOWN                0x00080000      /* PLL channel power down */
+#define chipcHw_REG_PLL_CLOCK_SOURCE_GPIO               0x00040000      /* Use GPIO as source */
+#define chipcHw_REG_PLL_CLOCK_BYPASS_SELECT             0x00020000      /* Select bypass clock */
+#define chipcHw_REG_PLL_CLOCK_OUTPUT_ENABLE             0x00010000      /* Clock gated ON */
+#define chipcHw_REG_PLL_CLOCK_PHASE_UPDATE_ENABLE       0x00008000      /* Clock phase update enable */
+#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_SHIFT       8       /* Number of bits to be shifted */
+#define chipcHw_REG_PLL_CLOCK_PHASE_CONTROL_MASK        0x00003F00      /* Phase control mask */
+#define chipcHw_REG_PLL_CLOCK_MDIV_MASK                 0x000000FF      /* Clock post divider mask
+                                                                           00000000 = divide-by-256
+                                                                           00000001 = divide-by-1
+                                                                           00000010 = divide-by-2
+                                                                           00000011 = divide-by-3
+                                                                           00000100 = divide-by-4
+                                                                           00000101 = divide-by-5
+                                                                           00000110 = divide-by-6
+                                                                           .
+                                                                           .
+                                                                           11111011 = divide-by-251
+                                                                           11111100 = divide-by-252
+                                                                           11111101 = divide-by-253
+                                                                           11111110 = divide-by-254
+                                                                         */
+#define chipcHw_REG_DIV_CLOCK_SOURCE_OTHER              0x00040000      /* NON-PLL clock source select */
+#define chipcHw_REG_DIV_CLOCK_BYPASS_SELECT             0x00020000      /* NON-PLL clock bypass enable */
+#define chipcHw_REG_DIV_CLOCK_OUTPUT_ENABLE             0x00010000      /* NON-PLL clock output enable */
+#define chipcHw_REG_DIV_CLOCK_DIV_MASK                  0x000000FF      /* NON-PLL clock post-divide mask */
+#define chipcHw_REG_DIV_CLOCK_DIV_256                   0x00000000      /* NON-PLL clock post-divide by 256 */
+#define chipcHw_REG_PLL_PREDIVIDER_P1_SHIFT             0
+#define chipcHw_REG_PLL_PREDIVIDER_P2_SHIFT             4
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_SHIFT           8
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MASK            0x0001FF00
+#define chipcHw_REG_PLL_PREDIVIDER_POWER_DOWN           0x02000000
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASK       0x00700000      /* Divider mask */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_INTEGER    0x00000000      /* Integer-N Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_UNIT  0x00100000      /* MASH Sigma-Delta Modulator Unit Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_UNIT   0x00200000      /* MFB Sigma-Delta Modulator Unit Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MASH_1_8   0x00300000      /* MASH Sigma-Delta Modulator 1/8 Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_MODE_MFB_1_8    0x00400000      /* MFB Sigma-Delta Modulator 1/8 Mode */
+#define chipcHw_REG_PLL_PREDIVIDER_NDIV_i(vco)          ((vco) / chipcHw_XTAL_FREQ_Hz)
+#define chipcHw_REG_PLL_PREDIVIDER_P1                   1
+#define chipcHw_REG_PLL_PREDIVIDER_P2                   1
+#define chipcHw_REG_PLL_DIVIDER_M1DIV                   0x03000000
+#define chipcHw_REG_PLL_DIVIDER_FRAC                    0x00FFFFFF      /* Fractional divider */
+#define chipcHw_REG_PLL_DIVIDER_NDIV_f_SS               (0x00FFFFFF)    /* To attain spread with max frequency */
+#define chipcHw_REG_PLL_DIVIDER_NDIV_f                  0       /* ndiv_frac = chipcHw_REG_PLL_DIVIDER_NDIV_f /
+                                                                   chipcHw_REG_PLL_DIVIDER_FRAC
+                                                                   = 0, when SS is disable
+                                                                 */
+#define chipcHw_REG_PLL_DIVIDER_MDIV(vco, Hz)           ((chipcHw_divide((vco), (Hz)) > 255) ? 0 : chipcHw_divide((vco), (Hz)))
+#define chipcHw_REG_ACLKClock_CLK_DIV_MASK              0x3
+/* System booting strap options */
+#define chipcHw_STRAPS_SOFT_OVERRIDE                    0x00000001      /* Software Strap Override */
+#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_8         0x00000000      /* 8 bit NAND FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_NOR_FLASH_16         0x00000002      /* 16 bit NOR FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_SERIAL_FLASH         0x00000004      /* Serial FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_NAND_FLASH_16        0x00000006      /* 16 bit NAND FLASH Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_UART                 0x00000008      /* UART Boot */
+#define chipcHw_STRAPS_BOOT_DEVICE_MASK                 0x0000000E      /* Mask */
+/* System boot option */
+#define chipcHw_STRAPS_BOOT_OPTION_BROM                 0x00000000      /* Boot from Boot ROM */
+#define chipcHw_STRAPS_BOOT_OPTION_ARAM                 0x00000020      /* Boot from ARAM */
+#define chipcHw_STRAPS_BOOT_OPTION_NOR                  0x00000030      /* Boot from NOR flash */
+/* NAND Flash page size strap options */
+#define chipcHw_STRAPS_NAND_PAGESIZE_512                0x00000000      /* NAND FLASH page size of 512 bytes */
+#define chipcHw_STRAPS_NAND_PAGESIZE_2048               0x00000040      /* NAND FLASH page size of 2048 bytes */
+#define chipcHw_STRAPS_NAND_PAGESIZE_4096               0x00000080      /* NAND FLASH page size of 4096 bytes */
+#define chipcHw_STRAPS_NAND_PAGESIZE_EXT                0x000000C0      /* NAND FLASH page of extened size */
+#define chipcHw_STRAPS_NAND_PAGESIZE_MASK               0x000000C0      /* Mask */
+#define chipcHw_STRAPS_NAND_EXTRA_CYCLE                 0x00000400      /* NAND FLASH address cycle configuration */
+#define chipcHw_STRAPS_REBOOT_TO_UART                   0x00000800      /* Reboot to UART on error */
+/* Secure boot mode strap options */
+#define chipcHw_STRAPS_BOOT_MODE_NORMAL                 0x00000000      /* Normal Boot */
+#define chipcHw_STRAPS_BOOT_MODE_DBG_SW                 0x00000100      /* Software debugging Boot */
+#define chipcHw_STRAPS_BOOT_MODE_DBG_BOOT               0x00000200      /* Boot rom debugging Boot */
+#define chipcHw_STRAPS_BOOT_MODE_NORMAL_QUIET           0x00000300      /* Normal Boot (Quiet BootRom) */
+#define chipcHw_STRAPS_BOOT_MODE_MASK                   0x00000300      /* Mask */
+/* Slave Mode straps */
+#define chipcHw_STRAPS_I2CS                             0x02000000      /* I2C Slave  */
+#define chipcHw_STRAPS_SPIS                             0x01000000      /* SPI Slave  */
+/* Strap pin options */
+#define chipcHw_REG_SW_STRAPS                           ((pChipcHw->PinStraps & 0x0000FC00) >> 10)
+/* PIF/LCD pin sharing defines */
+#define chipcHw_REG_LCD_PIN_ENABLE                      0x00000001      /* LCD Controller is used and the pins have LCD functions */
+#define chipcHw_REG_PIF_PIN_ENABLE                      0x00000002      /* LCD pins are used to perform PIF functions  */
+#define chipcHw_GPIO_COUNT                              61      /* Number of GPIO pin accessible thorugh CHIPC */
+/* NOTE: Any changes to these constants will require a corresponding change to chipcHw_str.c */
+#define chipcHw_REG_GPIO_MUX_KEYPAD                     0x00000001      /* GPIO mux for Keypad */
+#define chipcHw_REG_GPIO_MUX_I2CH                       0x00000002      /* GPIO mux for I2CH */
+#define chipcHw_REG_GPIO_MUX_SPI                        0x00000003      /* GPIO mux for SPI */
+#define chipcHw_REG_GPIO_MUX_UART                       0x00000004      /* GPIO mux for UART */
+#define chipcHw_REG_GPIO_MUX_LEDMTXP                    0x00000005      /* GPIO mux for LEDMTXP */
+#define chipcHw_REG_GPIO_MUX_LEDMTXS                    0x00000006      /* GPIO mux for LEDMTXS */
+#define chipcHw_REG_GPIO_MUX_SDIO0                      0x00000007      /* GPIO mux for SDIO0 */
+#define chipcHw_REG_GPIO_MUX_SDIO1                      0x00000008      /* GPIO mux for SDIO1 */
+#define chipcHw_REG_GPIO_MUX_PCM                        0x00000009      /* GPIO mux for PCM */
+#define chipcHw_REG_GPIO_MUX_I2S                        0x0000000A      /* GPIO mux for I2S */
+#define chipcHw_REG_GPIO_MUX_ETM                        0x0000000B      /* GPIO mux for ETM */
+#define chipcHw_REG_GPIO_MUX_DEBUG                      0x0000000C      /* GPIO mux for DEBUG */
+#define chipcHw_REG_GPIO_MUX_MISC                       0x0000000D      /* GPIO mux for MISC */
+#define chipcHw_REG_GPIO_MUX_GPIO                       0x00000000      /* GPIO mux for GPIO */
+#define chipcHw_REG_GPIO_MUX(pin)                       (&pChipcHw->GpioMux_0_7 + ((pin) >> 3))
+#define chipcHw_REG_GPIO_MUX_POSITION(pin)              (((pin) & 0x00000007) << 2)
+#define chipcHw_REG_GPIO_MUX_MASK                       0x0000000F      /* Mask */
+#define chipcHw_REG_SLEW_RATE_HIGH                      0x00000000      /* High speed slew rate */
+#define chipcHw_REG_SLEW_RATE_NORMAL                    0x00000008      /* Normal slew rate */
+                                                        /* Pins beyond 42 are defined by skipping 8 bits within the register */
+#define chipcHw_REG_SLEW_RATE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
+#define chipcHw_REG_SLEW_RATE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
+#define chipcHw_REG_SLEW_RATE_MASK                      0x00000008      /* Mask */
+#define chipcHw_REG_CURRENT_STRENGTH_2mA                0x00000001      /* Current driving strength 2 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_4mA                0x00000002      /* Current driving strength 4 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_6mA                0x00000004      /* Current driving strength 6 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_8mA                0x00000005      /* Current driving strength 8 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_10mA               0x00000006      /* Current driving strength 10 milli ampere */
+#define chipcHw_REG_CURRENT_STRENGTH_12mA               0x00000007      /* Current driving strength 12 milli ampere */
+#define chipcHw_REG_CURRENT_MASK                        0x00000007      /* Mask */
+                                                        /* Pins beyond 42 are defined by skipping 8 bits */
+#define chipcHw_REG_CURRENT(pin)                        (((pin) > 42) ? (&pChipcHw->GpioSR_0_7 + (((pin) + 2) >> 3)) : (&pChipcHw->GpioSR_0_7 + ((pin) >> 3)))
+#define chipcHw_REG_CURRENT_POSITION(pin)               (((pin) > 42) ? ((((pin) + 2) & 0x00000007) << 2) : (((pin) & 0x00000007) << 2))
+#define chipcHw_REG_PULL_NONE                           0x00000000      /* No pull up register */
+#define chipcHw_REG_PULL_UP                             0x00000001      /* Pull up register enable */
+#define chipcHw_REG_PULL_DOWN                           0x00000002      /* Pull down register enable */
+#define chipcHw_REG_PULLUP_MASK                         0x00000003      /* Mask */
+                                                        /* Pins beyond 42 are defined by skipping 4 bits */
+#define chipcHw_REG_PULLUP(pin)                         (((pin) > 42) ? (&pChipcHw->GpioPull_0_15 + (((pin) + 2) >> 4)) : (&pChipcHw->GpioPull_0_15 + ((pin) >> 4)))
+#define chipcHw_REG_PULLUP_POSITION(pin)                (((pin) > 42) ? ((((pin) + 2) & 0x0000000F) << 1) : (((pin) & 0x0000000F) << 1))
+#define chipcHw_REG_INPUTTYPE_CMOS                      0x00000000      /* Normal CMOS logic */
+#define chipcHw_REG_INPUTTYPE_ST                        0x00000001      /* High speed Schmitt Trigger */
+#define chipcHw_REG_INPUTTYPE_MASK                      0x00000001      /* Mask */
+                                                        /* Pins beyond 42 are defined by skipping 2 bits */
+#define chipcHw_REG_INPUTTYPE(pin)                      (((pin) > 42) ? (&pChipcHw->GpioInput_0_31 + (((pin) + 2) >> 5)) : (&pChipcHw->GpioInput_0_31 + ((pin) >> 5)))
+#define chipcHw_REG_INPUTTYPE_POSITION(pin)             (((pin) > 42) ? ((((pin) + 2) & 0x0000001F)) : (((pin) & 0x0000001F)))
+/* Device connected to the bus clock */
+#define chipcHw_REG_BUS_CLOCK_ARM                       0x00000001      /* Bus interface clock for ARM */
+#define chipcHw_REG_BUS_CLOCK_VDEC                      0x00000002      /* Bus interface clock for VDEC */
+#define chipcHw_REG_BUS_CLOCK_ARAM                      0x00000004      /* Bus interface clock for ARAM */
+#define chipcHw_REG_BUS_CLOCK_HPM                       0x00000008      /* Bus interface clock for HPM */
+#define chipcHw_REG_BUS_CLOCK_DDRC                      0x00000010      /* Bus interface clock for DDRC */
+#define chipcHw_REG_BUS_CLOCK_DMAC0                     0x00000020      /* Bus interface clock for DMAC0 */
+#define chipcHw_REG_BUS_CLOCK_DMAC1                     0x00000040      /* Bus interface clock for DMAC1 */
+#define chipcHw_REG_BUS_CLOCK_NVI                       0x00000080      /* Bus interface clock for NVI */
+#define chipcHw_REG_BUS_CLOCK_ESW                       0x00000100      /* Bus interface clock for ESW */
+#define chipcHw_REG_BUS_CLOCK_GE                        0x00000200      /* Bus interface clock for GE */
+#define chipcHw_REG_BUS_CLOCK_I2CH                      0x00000400      /* Bus interface clock for I2CH */
+#define chipcHw_REG_BUS_CLOCK_I2S0                      0x00000800      /* Bus interface clock for I2S0 */
+#define chipcHw_REG_BUS_CLOCK_I2S1                      0x00001000      /* Bus interface clock for I2S1 */
+#define chipcHw_REG_BUS_CLOCK_VRAM                      0x00002000      /* Bus interface clock for VRAM */
+#define chipcHw_REG_BUS_CLOCK_CLCD                      0x00004000      /* Bus interface clock for CLCD */
+#define chipcHw_REG_BUS_CLOCK_LDK                       0x00008000      /* Bus interface clock for LDK */
+#define chipcHw_REG_BUS_CLOCK_LED                       0x00010000      /* Bus interface clock for LED */
+#define chipcHw_REG_BUS_CLOCK_OTP                       0x00020000      /* Bus interface clock for OTP */
+#define chipcHw_REG_BUS_CLOCK_PIF                       0x00040000      /* Bus interface clock for PIF */
+#define chipcHw_REG_BUS_CLOCK_SPU                       0x00080000      /* Bus interface clock for SPU */
+#define chipcHw_REG_BUS_CLOCK_SDIO0                     0x00100000      /* Bus interface clock for SDIO0 */
+#define chipcHw_REG_BUS_CLOCK_SDIO1                     0x00200000      /* Bus interface clock for SDIO1 */
+#define chipcHw_REG_BUS_CLOCK_SPIH                      0x00400000      /* Bus interface clock for SPIH */
+#define chipcHw_REG_BUS_CLOCK_SPIS                      0x00800000      /* Bus interface clock for SPIS */
+#define chipcHw_REG_BUS_CLOCK_UART0                     0x01000000      /* Bus interface clock for UART0 */
+#define chipcHw_REG_BUS_CLOCK_UART1                     0x02000000      /* Bus interface clock for UART1 */
+#define chipcHw_REG_BUS_CLOCK_BBL                       0x04000000      /* Bus interface clock for BBL */
+#define chipcHw_REG_BUS_CLOCK_I2CS                      0x08000000      /* Bus interface clock for I2CS */
+#define chipcHw_REG_BUS_CLOCK_USBH                      0x10000000      /* Bus interface clock for USB Host */
+#define chipcHw_REG_BUS_CLOCK_USBD                      0x20000000      /* Bus interface clock for USB Device */
+#define chipcHw_REG_BUS_CLOCK_BROM                      0x40000000      /* Bus interface clock for Boot ROM */
+#define chipcHw_REG_BUS_CLOCK_TSC                       0x80000000      /* Bus interface clock for Touch screen */
+/* Software resets defines */
+#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_HOLD          0x0000000080000000ULL   /* Reset Global VPM and hold */
+#define chipcHw_REG_SOFT_RESET_VPM_HOLD                 0x0000000040000000ULL   /* Reset VPM and hold */
+#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL               0x0000000020000000ULL   /* Reset Global VPM */
+#define chipcHw_REG_SOFT_RESET_VPM                      0x0000000010000000ULL   /* Reset VPM */
+#define chipcHw_REG_SOFT_RESET_KEYPAD                   0x0000000008000000ULL   /* Reset Key pad */
+#define chipcHw_REG_SOFT_RESET_LED                      0x0000000004000000ULL   /* Reset LED */
+#define chipcHw_REG_SOFT_RESET_SPU                      0x0000000002000000ULL   /* Reset SPU */
+#define chipcHw_REG_SOFT_RESET_RNG                      0x0000000001000000ULL   /* Reset RNG */
+#define chipcHw_REG_SOFT_RESET_PKA                      0x0000000000800000ULL   /* Reset PKA */
+#define chipcHw_REG_SOFT_RESET_LCD                      0x0000000000400000ULL   /* Reset LCD */
+#define chipcHw_REG_SOFT_RESET_PIF                      0x0000000000200000ULL   /* Reset PIF */
+#define chipcHw_REG_SOFT_RESET_I2CS                     0x0000000000100000ULL   /* Reset I2C Slave */
+#define chipcHw_REG_SOFT_RESET_I2CH                     0x0000000000080000ULL   /* Reset I2C Host */
+#define chipcHw_REG_SOFT_RESET_SDIO1                    0x0000000000040000ULL   /* Reset SDIO 1 */
+#define chipcHw_REG_SOFT_RESET_SDIO0                    0x0000000000020000ULL   /* Reset SDIO 0 */
+#define chipcHw_REG_SOFT_RESET_BBL                      0x0000000000010000ULL   /* Reset BBL */
+#define chipcHw_REG_SOFT_RESET_I2S1                     0x0000000000008000ULL   /* Reset I2S1 */
+#define chipcHw_REG_SOFT_RESET_I2S0                     0x0000000000004000ULL   /* Reset I2S0 */
+#define chipcHw_REG_SOFT_RESET_SPIS                     0x0000000000002000ULL   /* Reset SPI Slave */
+#define chipcHw_REG_SOFT_RESET_SPIH                     0x0000000000001000ULL   /* Reset SPI Host */
+#define chipcHw_REG_SOFT_RESET_GPIO1                    0x0000000000000800ULL   /* Reset GPIO block 1 */
+#define chipcHw_REG_SOFT_RESET_GPIO0                    0x0000000000000400ULL   /* Reset GPIO block 0 */
+#define chipcHw_REG_SOFT_RESET_UART1                    0x0000000000000200ULL   /* Reset UART 1 */
+#define chipcHw_REG_SOFT_RESET_UART0                    0x0000000000000100ULL   /* Reset UART 0 */
+#define chipcHw_REG_SOFT_RESET_NVI                      0x0000000000000080ULL   /* Reset NVI */
+#define chipcHw_REG_SOFT_RESET_WDOG                     0x0000000000000040ULL   /* Reset Watch dog */
+#define chipcHw_REG_SOFT_RESET_TMR                      0x0000000000000020ULL   /* Reset Timer */
+#define chipcHw_REG_SOFT_RESET_ETM                      0x0000000000000010ULL   /* Reset ETM */
+#define chipcHw_REG_SOFT_RESET_ARM_HOLD                 0x0000000000000008ULL   /* Reset ARM and HOLD */
+#define chipcHw_REG_SOFT_RESET_ARM                      0x0000000000000004ULL   /* Reset ARM */
+#define chipcHw_REG_SOFT_RESET_CHIP_WARM                0x0000000000000002ULL   /* Chip warm reset */
+#define chipcHw_REG_SOFT_RESET_CHIP_SOFT                0x0000000000000001ULL   /* Chip soft reset */
+#define chipcHw_REG_SOFT_RESET_VDEC                     0x0000100000000000ULL   /* Video decoder */
+#define chipcHw_REG_SOFT_RESET_GE                       0x0000080000000000ULL   /* Graphics engine */
+#define chipcHw_REG_SOFT_RESET_OTP                      0x0000040000000000ULL   /* Reset OTP */
+#define chipcHw_REG_SOFT_RESET_USB2                     0x0000020000000000ULL   /* Reset USB2 */
+#define chipcHw_REG_SOFT_RESET_USB1                     0x0000010000000000ULL   /* Reset USB 1 */
+#define chipcHw_REG_SOFT_RESET_USB                      0x0000008000000000ULL   /* Reset USB 1 and USB2 soft reset */
+#define chipcHw_REG_SOFT_RESET_ESW                      0x0000004000000000ULL   /* Reset Ethernet switch */
+#define chipcHw_REG_SOFT_RESET_ESWCLK                   0x0000002000000000ULL   /* Reset Ethernet switch clock */
+#define chipcHw_REG_SOFT_RESET_DDRPHY                   0x0000001000000000ULL   /* Reset DDR Physical */
+#define chipcHw_REG_SOFT_RESET_DDR                      0x0000000800000000ULL   /* Reset DDR Controller */
+#define chipcHw_REG_SOFT_RESET_TSC                      0x0000000400000000ULL   /* Reset Touch screen */
+#define chipcHw_REG_SOFT_RESET_PCM                      0x0000000200000000ULL   /* Reset PCM device */
+#define chipcHw_REG_SOFT_RESET_APM                      0x0000200100000000ULL   /* Reset APM device */
+#define chipcHw_REG_SOFT_RESET_VPM_GLOBAL_UNHOLD        0x8000000000000000ULL   /* Unhold Global VPM */
+#define chipcHw_REG_SOFT_RESET_VPM_UNHOLD               0x4000000000000000ULL   /* Unhold VPM */
+#define chipcHw_REG_SOFT_RESET_ARM_UNHOLD               0x2000000000000000ULL   /* Unhold ARM reset  */
+#define chipcHw_REG_SOFT_RESET_UNHOLD_MASK              0xF000000000000000ULL   /* Mask to handle unhold request */
+/* Audio channel control defines */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_ALL            0x00000001      /* Enable all audio channel */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_A              0x00000002      /* Enable channel A */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_B              0x00000004      /* Enable channel B */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_C              0x00000008      /* Enable channel C */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_NTP_CLOCK      0x00000010      /* Enable NTP clock */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM0_CLOCK     0x00000020      /* Enable PCM0 clock */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_PCM1_CLOCK     0x00000040      /* Enable PCM1 clock */
+#define chipcHw_REG_AUDIO_CHANNEL_ENABLE_APM_CLOCK      0x00000080      /* Enable APM clock */
+/* Misc. chip control defines */
+#define chipcHw_REG_MISC_CTRL_GE_SEL                    0x00040000      /* Select GE2/GE3 */
+#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S1 */
+#define chipcHw_REG_MISC_CTRL_I2S1_CLOCK_GPIO           0x00020000      /* Use external clock via GPIO pin 26 for I2S1 */
+#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_ONCHIP         0x00000000      /* Use on chip clock for I2S0 */
+#define chipcHw_REG_MISC_CTRL_I2S0_CLOCK_GPIO           0x00010000      /* Use external clock via GPIO pin 45 for I2S0 */
+#define chipcHw_REG_MISC_CTRL_ARM_CP15_DISABLE          0x00008000      /* Disable ARM CP15 bit */
+#define chipcHw_REG_MISC_CTRL_RTC_DISABLE               0x00000008      /* Disable RTC registers */
+#define chipcHw_REG_MISC_CTRL_BBRAM_DISABLE             0x00000004      /* Disable Battery Backed RAM */
+#define chipcHw_REG_MISC_CTRL_USB_MODE_HOST             0x00000002      /* Set USB as host */
+#define chipcHw_REG_MISC_CTRL_USB_MODE_DEVICE           0xFFFFFFFD      /* Set USB as device */
+#define chipcHw_REG_MISC_CTRL_USB_POWERON               0xFFFFFFFE      /* Power up USB */
+#define chipcHw_REG_MISC_CTRL_USB_POWEROFF              0x00000001      /* Power down USB */
+/* OTP configuration defines */
+#define chipcHw_REG_OTP_SECURITY_OFF                    0x0000020000000000ULL   /* Security support is OFF */
+#define chipcHw_REG_OTP_SPU_SLOW                        0x0000010000000000ULL   /* Limited SPU throughput */
+#define chipcHw_REG_OTP_LCD_SPEED                       0x0000000600000000ULL   /* Set VPM speed one */
+#define chipcHw_REG_OTP_VPM_SPEED_1                     0x0000000100000000ULL   /* Set VPM speed one */
+#define chipcHw_REG_OTP_VPM_SPEED_0                     0x0000000080000000ULL   /* Set VPM speed zero */
+#define chipcHw_REG_OTP_AXI_SPEED                       0x0000000060000000ULL   /* Set maximum AXI bus speed */
+#define chipcHw_REG_OTP_APM_DISABLE                     0x000000001F000000ULL   /* Disable APM */
+#define chipcHw_REG_OTP_PIF_DISABLE                     0x0000000000200000ULL   /* Disable PIF */
+#define chipcHw_REG_OTP_VDEC_DISABLE                    0x0000000000100000ULL   /* Disable Video decoder */
+#define chipcHw_REG_OTP_BBL_DISABLE                     0x0000000000080000ULL   /* Disable RTC and BBRAM */
+#define chipcHw_REG_OTP_LED_DISABLE                     0x0000000000040000ULL   /* Disable LED */
+#define chipcHw_REG_OTP_GE_DISABLE                      0x0000000000020000ULL   /* Disable Graphics Engine */
+#define chipcHw_REG_OTP_LCD_DISABLE                     0x0000000000010000ULL   /* Disable LCD */
+#define chipcHw_REG_OTP_KEYPAD_DISABLE                  0x0000000000008000ULL   /* Disable keypad */
+#define chipcHw_REG_OTP_UART_DISABLE                    0x0000000000004000ULL   /* Disable UART */
+#define chipcHw_REG_OTP_SDIOH_DISABLE                   0x0000000000003000ULL   /* Disable SDIO host */
+#define chipcHw_REG_OTP_HSS_DISABLE                     0x0000000000000C00ULL   /* Disable HSS */
+#define chipcHw_REG_OTP_TSC_DISABLE                     0x0000000000000200ULL   /* Disable touch screen */
+#define chipcHw_REG_OTP_USB_DISABLE                     0x0000000000000180ULL   /* Disable USB */
+#define chipcHw_REG_OTP_SGMII_DISABLE                   0x0000000000000060ULL   /* Disable SGMII */
+#define chipcHw_REG_OTP_ETH_DISABLE                     0x0000000000000018ULL   /* Disable gigabit ethernet */
+#define chipcHw_REG_OTP_ETH_PHY_DISABLE                 0x0000000000000006ULL   /* Disable ethernet PHY */
+#define chipcHw_REG_OTP_VPM_DISABLE                     0x0000000000000001ULL   /* Disable VPM */
+/* Sticky bit defines */
+#define chipcHw_REG_STICKY_BOOT_DONE                    0x00000001      /* Boot done */
+#define chipcHw_REG_STICKY_SOFT_RESET                   0x00000002      /* ARM soft reset */
+#define chipcHw_REG_STICKY_GENERAL_1                    0x00000004      /* General purpose bit 1 */
+#define chipcHw_REG_STICKY_GENERAL_2                    0x00000008      /* General purpose bit 2 */
+#define chipcHw_REG_STICKY_GENERAL_3                    0x00000010      /* General purpose bit 3 */
+#define chipcHw_REG_STICKY_GENERAL_4                    0x00000020      /* General purpose bit 4 */
+#define chipcHw_REG_STICKY_GENERAL_5                    0x00000040      /* General purpose bit 5 */
+#define chipcHw_REG_STICKY_POR_BROM                     0x00000080      /* Special sticky bit for security - set in BROM to avoid other modes being entered */
+#define chipcHw_REG_STICKY_ARM_RESET                    0x00000100      /* ARM reset */
+#define chipcHw_REG_STICKY_CHIP_SOFT_RESET              0x00000200      /* Chip soft reset */
+#define chipcHw_REG_STICKY_CHIP_WARM_RESET              0x00000400      /* Chip warm reset */
+#define chipcHw_REG_STICKY_WDOG_RESET                   0x00000800      /* Watchdog reset */
+#define chipcHw_REG_STICKY_OTP_RESET                    0x00001000      /* OTP reset */
+                                                        /* HW phase alignment defines *//* Spare1 register definitions */
+#define chipcHw_REG_SPARE1_DDR_PHASE_INTR_ENABLE        0x80000000      /* Enable DDR phase align panic interrupt */
+#define chipcHw_REG_SPARE1_VPM_PHASE_INTR_ENABLE        0x40000000      /* Enable VPM phase align panic interrupt */
+#define chipcHw_REG_SPARE1_VPM_BUS_ACCESS_ENABLE        0x00000002      /* Enable access to VPM using system BUS */
+#define chipcHw_REG_SPARE1_DDR_BUS_ACCESS_ENABLE        0x00000001      /* Enable access to DDR using system BUS */
+                                                        /* DDRPhaseCtrl1 register definitions */
+#define chipcHw_REG_DDR_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable DDR SW phase alignment */
+#define chipcHw_REG_DDR_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable DDR HW phase alignment */
+#define chipcHw_REG_DDR_PHASE_VALUE_GE_MASK             0x0000007F      /* DDR lower threshold for phase alignment */
+#define chipcHw_REG_DDR_PHASE_VALUE_GE_SHIFT            23
+#define chipcHw_REG_DDR_PHASE_VALUE_LE_MASK             0x0000007F      /* DDR upper threshold for phase alignment */
+#define chipcHw_REG_DDR_PHASE_VALUE_LE_SHIFT            16
+#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to run next DDR phase alignment */
+#define chipcHw_REG_DDR_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
+                                                        /* VPMPhaseCtrl1 register definitions */
+#define chipcHw_REG_VPM_SW_PHASE_CTRL_ENABLE            0x80000000      /* Enable VPM SW phase alignment */
+#define chipcHw_REG_VPM_HW_PHASE_CTRL_ENABLE            0x40000000      /* Enable VPM HW phase alignment */
+#define chipcHw_REG_VPM_PHASE_VALUE_GE_MASK             0x0000007F      /* VPM lower threshold for phase alignment */
+#define chipcHw_REG_VPM_PHASE_VALUE_GE_SHIFT            23
+#define chipcHw_REG_VPM_PHASE_VALUE_LE_MASK             0x0000007F      /* VPM upper threshold for phase alignment */
+#define chipcHw_REG_VPM_PHASE_VALUE_LE_SHIFT            16
+#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_MASK     0x0000FFFF      /* BUS Cycle to wait to complete the VPM phase alignment */
+#define chipcHw_REG_VPM_PHASE_ALIGN_WAIT_CYCLE_SHIFT    0
+                                                        /* PhaseAlignStatus register definitions */
+#define chipcHw_REG_DDR_TIMEOUT_INTR_STATUS             0x80000000      /* DDR time out interrupt status */
+#define chipcHw_REG_DDR_PHASE_STATUS_MASK               0x0000007F      /* DDR phase status value */
+#define chipcHw_REG_DDR_PHASE_STATUS_SHIFT              24
+#define chipcHw_REG_DDR_PHASE_ALIGNED                   0x00800000      /* DDR Phase aligned status */
+#define chipcHw_REG_DDR_LOAD                            0x00400000      /* Load DDR phase status */
+#define chipcHw_REG_DDR_PHASE_CTRL_MASK                 0x0000003F      /* DDR phase control value */
+#define chipcHw_REG_DDR_PHASE_CTRL_SHIFT                16
+#define chipcHw_REG_VPM_TIMEOUT_INTR_STATUS             0x80000000      /* VPM time out interrupt status */
+#define chipcHw_REG_VPM_PHASE_STATUS_MASK               0x0000007F      /* VPM phase status value */
+#define chipcHw_REG_VPM_PHASE_STATUS_SHIFT              8
+#define chipcHw_REG_VPM_PHASE_ALIGNED                   0x00000080      /* VPM Phase aligned status */
+#define chipcHw_REG_VPM_LOAD                            0x00000040      /* Load VPM phase status */
+#define chipcHw_REG_VPM_PHASE_CTRL_MASK                 0x0000003F      /* VPM phase control value */
+#define chipcHw_REG_VPM_PHASE_CTRL_SHIFT                0
+                                                        /* DDRPhaseCtrl2 register definitions */
+#define chipcHw_REG_DDR_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
+#define chipcHw_REG_DDR_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
+#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
+#define chipcHw_REG_DDR_LOAD_COUNT_PHASE_CTRL_SHIFT     20
+#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait to settle ph_ctrl and load_ch */
+#define chipcHw_REG_DDR_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
+#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for DDR HW phase alignment */
+#define chipcHw_REG_DDR_PHASE_TIMEOUT_COUNT_SHIFT       0
+                                                        /* VPMPhaseCtrl2 register definitions */
+#define chipcHw_REG_VPM_INTR_SELECT_MASK                0x00000003      /* Interrupt select */
+#define chipcHw_REG_VPM_INTR_SELECT_SHIFT               26
+#define chipcHw_REG_VPM_INTR_DISABLE                    0x00000000
+#define chipcHw_REG_VPM_INTR_FAST                       (0x1 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
+#define chipcHw_REG_VPM_INTR_MEDIUM                     (0x2 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
+#define chipcHw_REG_VPM_INTR_SLOW                       (0x3 << chipcHw_REG_VPM_INTR_SELECT_SHIFT)
+#define chipcHw_REG_VPM_INTR_SERVICED                   0x02000000      /* Acknowledge that interrupt was serviced */
+#define chipcHw_REG_VPM_TIMEOUT_INTR_ENABLE             0x01000000      /* Enable time out interrupt */
+#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_MASK      0x0000000F      /* Wait before toggling load_ch */
+#define chipcHw_REG_VPM_LOAD_COUNT_PHASE_CTRL_SHIFT     20
+#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_MASK      0x0000000F      /* Total wait cycle to settle ph_ctrl and load_ch */
+#define chipcHw_REG_VPM_TOTAL_LOAD_COUNT_CTRL_SHIFT     16
+#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_MASK        0x0000FFFF      /* Time out value for VPM HW phase alignment */
+#define chipcHw_REG_VPM_PHASE_TIMEOUT_COUNT_SHIFT       0
+#endif /* CHIPCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
new file mode 100644
index 000000000000..f1b68e26fa6d
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/ddrcReg.h
@@ -0,0 +1,872 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    ddrcReg.h
+*
+*  @brief   Register definitions for BCMRING DDR2 Controller and PHY
+*
+*/
+/****************************************************************************/
+#ifndef DDRC_REG_H
+#define DDRC_REG_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/reg.h>
+#include <csp/stdint.h>
+#include <mach/csp/mm_io.h>
+/* ---- Public Constants and Types --------------------------------------- */
+/*********************************************************************/
+/* DDR2 Controller (ARM PL341) register definitions */
+/*********************************************************************/
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 DDR2 configuration registers, offset 0x000 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+        typedef struct {
+                uint32_t memcStatus;
+                uint32_t memcCmd;
+                uint32_t directCmd;
+                uint32_t memoryCfg;
+                uint32_t refreshPrd;
+                uint32_t casLatency;
+                uint32_t writeLatency;
+                uint32_t tMrd;
+                uint32_t tRas;
+                uint32_t tRc;
+                uint32_t tRcd;
+                uint32_t tRfc;
+                uint32_t tRp;
+                uint32_t tRrd;
+                uint32_t tWr;
+                uint32_t tWtr;
+                uint32_t tXp;
+                uint32_t tXsr;
+                uint32_t tEsr;
+                uint32_t memoryCfg2;
+                uint32_t memoryCfg3;
+                uint32_t tFaw;
+        } ddrcReg_CTLR_MEMC_REG_t;
+#define ddrcReg_CTLR_MEMC_REG_OFFSET                    0x0000
+#define ddrcReg_CTLR_MEMC_REGP                          ((volatile ddrcReg_CTLR_MEMC_REG_t *)  (MM_IO_BASE_DDRC + ddrcReg_CTLR_MEMC_REG_OFFSET))
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_MEMC_STATUS_BANKS_MASK             (0x3 << 12)
+#define ddrcReg_CTLR_MEMC_STATUS_BANKS_4                (0x0 << 12)
+#define ddrcReg_CTLR_MEMC_STATUS_BANKS_8                (0x3 << 12)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_MASK          (0x3 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_0             (0x0 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_1             (0x1 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_2             (0x2 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_MONITORS_4             (0x3 << 10)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_MASK             (0x3 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_1                (0x0 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_2                (0x1 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_3                (0x2 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_CHIPS_4                (0x3 << 7)
+#define ddrcReg_CTLR_MEMC_STATUS_TYPE_MASK              (0x7 << 4)
+#define ddrcReg_CTLR_MEMC_STATUS_TYPE_DDR2              (0x5 << 4)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_MASK             (0x3 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_16               (0x0 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_32               (0x1 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_64               (0x2 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_WIDTH_128              (0x3 << 2)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_MASK             (0x3 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_CONFIG           (0x0 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_READY            (0x1 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_PAUSED           (0x2 << 0)
+#define ddrcReg_CTLR_MEMC_STATUS_STATE_LOWPWR           (0x3 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_MEMC_CMD_MASK                      (0x7 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_GO                        (0x0 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_SLEEP                     (0x1 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_WAKEUP                    (0x2 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_PAUSE                     (0x3 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_CONFIGURE                 (0x4 << 0)
+#define ddrcReg_CTLR_MEMC_CMD_ACTIVE_PAUSE              (0x7 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT              20
+#define ddrcReg_CTLR_DIRECT_CMD_CHIP_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_CHIP_SHIFT)
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_PRECHARGEALL       (0x0 << 18)
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_AUTOREFRESH        (0x1 << 18)
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_MODEREG            (0x2 << 18)
+#define ddrcReg_CTLR_DIRECT_CMD_TYPE_NOP                (0x3 << 18)
+#define ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT              16
+#define ddrcReg_CTLR_DIRECT_CMD_BANK_MASK               (0x3 << ddrcReg_CTLR_DIRECT_CMD_BANK_SHIFT)
+#define ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT              0
+#define ddrcReg_CTLR_DIRECT_CMD_ADDR_MASK               (0x1ffff << ddrcReg_CTLR_DIRECT_CMD_ADDR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_MASK           (0x3 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_1              (0x0 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_2              (0x1 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_3              (0x2 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_CHIP_CNT_4              (0x3 << 21)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_MASK           (0x7 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_3_0            (0x0 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_4_1            (0x1 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_5_2            (0x2 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_6_3            (0x3 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_7_4            (0x4 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_8_5            (0x5 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_9_6            (0x6 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_QOS_ARID_10_7           (0x7 << 18)
+#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_MASK          (0x7 << 15)
+#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_4             (0x2 << 15)
+#define ddrcReg_CTLR_MEMORY_CFG_BURST_LEN_8             (0x3 << 15)     /* @note Not supported in PL341 */
+#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_ENABLE          (0x1 << 13)
+#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT    7
+#define ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_MASK     (0x3f << ddrcReg_CTLR_MEMORY_CFG_PWRDOWN_CYCLES_SHIFT)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_MASK       (0x7 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_11         (0x0 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_12         (0x1 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_13         (0x2 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_14         (0x3 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_15         (0x4 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_ROW_BITS_16         (0x5 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_MASK       (0x7 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_9          (0x1 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_10         (0x2 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG_AXI_COL_BITS_11         (0x3 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_REFRESH_PRD_SHIFT                  0
+#define ddrcReg_CTLR_REFRESH_PRD_MASK                   (0x7fff << ddrcReg_CTLR_REFRESH_PRD_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_CAS_LATENCY_SHIFT                  1
+#define ddrcReg_CTLR_CAS_LATENCY_MASK                   (0x7 << ddrcReg_CTLR_CAS_LATENCY_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_WRITE_LATENCY_SHIFT                0
+#define ddrcReg_CTLR_WRITE_LATENCY_MASK                 (0x7 << ddrcReg_CTLR_WRITE_LATENCY_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_MRD_SHIFT                        0
+#define ddrcReg_CTLR_T_MRD_MASK                         (0x7f << ddrcReg_CTLR_T_MRD_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_RAS_SHIFT                        0
+#define ddrcReg_CTLR_T_RAS_MASK                         (0x1f << ddrcReg_CTLR_T_RAS_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_RC_SHIFT                         0
+#define ddrcReg_CTLR_T_RC_MASK                          (0x1f << ddrcReg_CTLR_T_RC_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT         8
+#define ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_MASK          (0x7 << ddrcReg_CTLR_T_RCD_SCHEDULE_DELAY_SHIFT)
+#define ddrcReg_CTLR_T_RCD_SHIFT                        0
+#define ddrcReg_CTLR_T_RCD_MASK                         (0x7 << ddrcReg_CTLR_T_RCD_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT         8
+#define ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_MASK          (0x7f << ddrcReg_CTLR_T_RFC_SCHEDULE_DELAY_SHIFT)
+#define ddrcReg_CTLR_T_RFC_SHIFT                        0
+#define ddrcReg_CTLR_T_RFC_MASK                         (0x7f << ddrcReg_CTLR_T_RFC_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT          8
+#define ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_MASK           (0x7 << ddrcReg_CTLR_T_RP_SCHEDULE_DELAY_SHIFT)
+#define ddrcReg_CTLR_T_RP_SHIFT                         0
+#define ddrcReg_CTLR_T_RP_MASK                          (0xf << ddrcReg_CTLR_T_RP_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_RRD_SHIFT                        0
+#define ddrcReg_CTLR_T_RRD_MASK                         (0xf << ddrcReg_CTLR_T_RRD_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_WR_SHIFT                         0
+#define ddrcReg_CTLR_T_WR_MASK                          (0x7 << ddrcReg_CTLR_T_WR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_WTR_SHIFT                        0
+#define ddrcReg_CTLR_T_WTR_MASK                         (0x7 << ddrcReg_CTLR_T_WTR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_XP_SHIFT                         0
+#define ddrcReg_CTLR_T_XP_MASK                          (0xff << ddrcReg_CTLR_T_XP_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_XSR_SHIFT                        0
+#define ddrcReg_CTLR_T_XSR_MASK                         (0xff << ddrcReg_CTLR_T_XSR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_ESR_SHIFT                        0
+#define ddrcReg_CTLR_T_ESR_MASK                         (0xff << ddrcReg_CTLR_T_ESR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_MASK             (0x3 << 6)
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_16BITS           (0 << 6)
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_32BITS           (1 << 6)
+#define ddrcReg_CTLR_MEMORY_CFG2_WIDTH_64BITS           (2 << 6)
+#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_MASK     (0x3 << 4)
+#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_2        (0 << 4)
+#define ddrcReg_CTLR_MEMORY_CFG2_AXI_BANK_BITS_3        (3 << 4)
+#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_LOW     (0 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG2_CKE_INIT_STATE_HIGH    (1 << 3)
+#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_LOW     (0 << 2)
+#define ddrcReg_CTLR_MEMORY_CFG2_DQM_INIT_STATE_HIGH    (1 << 2)
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_MASK               (0x3 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_ASYNC              (0 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_LE_M        (1 << 0)
+#define ddrcReg_CTLR_MEMORY_CFG2_CLK_SYNC_A_GT_M        (3 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT       0
+#define ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_MASK        (0x7 << ddrcReg_CTLR_MEMORY_CFG3_REFRESH_TO_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT         8
+#define ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_MASK          (0x1f << ddrcReg_CTLR_T_FAW_SCHEDULE_DELAY_SHIFT)
+#define ddrcReg_CTLR_T_FAW_PERIOD_SHIFT                 0
+#define ddrcReg_CTLR_T_FAW_PERIOD_MASK                  (0x1f << ddrcReg_CTLR_T_FAW_PERIOD_SHIFT)
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 AXI ID QOS configuration registers, offset 0x100 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+#define ddrcReg_CTLR_QOS_CNT                            16
+#define ddrcReg_CTLR_QOS_MAX                            (ddrcReg_CTLR_QOS_CNT - 1)
+        typedef struct {
+                uint32_t cfg[ddrcReg_CTLR_QOS_CNT];
+        } ddrcReg_CTLR_QOS_REG_t;
+#define ddrcReg_CTLR_QOS_REG_OFFSET                     0x100
+#define ddrcReg_CTLR_QOS_REGP                           ((volatile ddrcReg_CTLR_QOS_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_QOS_REG_OFFSET))
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_QOS_CFG_MAX_SHIFT                  2
+#define ddrcReg_CTLR_QOS_CFG_MAX_MASK                   (0xff << ddrcReg_CTLR_QOS_CFG_MAX_SHIFT)
+#define ddrcReg_CTLR_QOS_CFG_MIN_SHIFT                  1
+#define ddrcReg_CTLR_QOS_CFG_MIN_MASK                   (1 << ddrcReg_CTLR_QOS_CFG_MIN_SHIFT)
+#define ddrcReg_CTLR_QOS_CFG_ENABLE                     (1 << 0)
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 Memory chip configuration registers, offset 0x200 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+#define ddrcReg_CTLR_CHIP_CNT                           4
+#define ddrcReg_CTLR_CHIP_MAX                           (ddrcReg_CTLR_CHIP_CNT - 1)
+        typedef struct {
+                uint32_t cfg[ddrcReg_CTLR_CHIP_CNT];
+        } ddrcReg_CTLR_CHIP_REG_t;
+#define ddrcReg_CTLR_CHIP_REG_OFFSET                    0x200
+#define ddrcReg_CTLR_CHIP_REGP                          ((volatile ddrcReg_CTLR_CHIP_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_CHIP_REG_OFFSET))
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_MASK              (1 << 16)
+#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_ROW_BANK_COL      (0 << 16)
+#define ddrcReg_CTLR_CHIP_CFG_MEM_ORG_BANK_ROW_COL      (1 << 16)
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT      8
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_MASK       (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MATCH_SHIFT)
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT       0
+#define ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_MASK        (0xff << ddrcReg_CTLR_CHIP_CFG_AXI_ADDR_MASK_SHIFT)
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* ARM PL341 User configuration registers, offset 0x300 */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+#define ddrcReg_CTLR_USER_OUTPUT_CNT                    2
+        typedef struct {
+                uint32_t input;
+                uint32_t output[ddrcReg_CTLR_USER_OUTPUT_CNT];
+                uint32_t feature;
+        } ddrcReg_CTLR_USER_REG_t;
+#define ddrcReg_CTLR_USER_REG_OFFSET                    0x300
+#define ddrcReg_CTLR_USER_REGP                          ((volatile ddrcReg_CTLR_USER_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_USER_REG_OFFSET))
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT            0
+#define ddrcReg_CTLR_USER_INPUT_STATUS_MASK             (0xff << ddrcReg_CTLR_USER_INPUT_STATUS_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT              0
+#define ddrcReg_CTLR_USER_OUTPUT_CFG_MASK               (0xff << ddrcReg_CTLR_USER_OUTPUT_CFG_SHIFT)
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT      1
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_MASK       (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_BP134      (0 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301      (1 << ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_REGISTERED ddrcReg_CTLR_USER_OUTPUT_0_CFG_SYNC_BRIDGE_PL301
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_FEATURE_WRITE_BLOCK_DISABLE        (1 << 2)
+#define ddrcReg_CTLR_FEATURE_EARLY_BURST_RSP_DISABLE    (1 << 0)
+/*********************************************************************/
+/* Broadcom DDR23 PHY register definitions */
+/*********************************************************************/
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* Broadcom DDR23 PHY Address and Control register definitions */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+        typedef struct {
+                uint32_t revision;
+                uint32_t pmCtl;
+                 REG32_RSVD(0x0008, 0x0010);
+                uint32_t pllStatus;
+                uint32_t pllCfg;
+                uint32_t pllPreDiv;
+                uint32_t pllDiv;
+                uint32_t pllCtl1;
+                uint32_t pllCtl2;
+                uint32_t ssCtl;
+                uint32_t ssCfg;
+                uint32_t vdlStatic;
+                uint32_t vdlDynamic;
+                uint32_t padIdle;
+                uint32_t pvtComp;
+                uint32_t padDrive;
+                uint32_t clkRgltrCtl;
+        } ddrcReg_PHY_ADDR_CTL_REG_t;
+#define ddrcReg_PHY_ADDR_CTL_REG_OFFSET                 0x0400
+#define ddrcReg_PHY_ADDR_CTL_REGP                       ((volatile ddrcReg_PHY_ADDR_CTL_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_ADDR_CTL_REG_OFFSET))
+/* @todo These SS definitions are duplicates of ones below */
+#define ddrcReg_PHY_ADDR_SS_CTRL_ENABLE                 0x00000001
+#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_MASK     0xFFFF0000
+#define ddrcReg_PHY_ADDR_SS_CFG_CYCLE_PER_TICK_SHIFT    16
+#define ddrcReg_PHY_ADDR_SS_CFG_MIN_CYCLE_PER_TICK      10      /* Higher the value, lower the SS modulation frequency */
+#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_MASK     0x0000FFFF
+#define ddrcReg_PHY_ADDR_SS_CFG_NDIV_AMPLITUDE_SHIFT    0
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT       8
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MAJOR_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT       0
+#define ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_MASK        (0xff << ddrcReg_PHY_ADDR_CTL_REVISION_MINOR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_CLK_PM_CTL_DDR_CLK_DISABLE (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_STATUS_LOCKED          (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_DIV2_CLK_RESET     (1 << 31)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT     17
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_SEL_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_TEST_ENABLE        (1 << 16)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT     12
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PLL_CFG_BGAP_ADJ_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_VCO_RNG            (1 << 7)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CH1_PWRDWN         (1 << 6)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_BYPASS_ENABLE      (1 << 5)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_CLKOUT_ENABLE      (1 << 4)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_D_RESET            (1 << 3)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_A_RESET            (1 << 2)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CFG_PWRDWN             (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_DITHER_MFB     (1 << 26)
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_PWRDWN         (1 << 25)
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT     20
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_MODE_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT      8
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_MASK       (0x1ff << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_INT_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT       4
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P2_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT       0
+#define ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PLL_PRE_DIV_P1_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT           24
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_MASK            (0xff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_M1_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT         0
+#define ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_MASK          (0xffffff << ddrcReg_PHY_ADDR_CTL_PLL_DIV_FRAC_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT       30
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_MASK        (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_TESTA_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT     27
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XS_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT     24
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_MASK      (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_KVCO_XF_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT      22
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LPF_BW_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_LF_ORDER          (0x1 << 21)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT          19
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CN_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT          17
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RN_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT          15
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CP_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT          13
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_MASK           (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_CZ_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT          10
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_MASK           (0x7 << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_RZ_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT        5
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_MASK         (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICPX_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT     0
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_MASK      (0x1f << ddrcReg_PHY_ADDR_CTL_PLL_CTL1_ICP_OFF_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT    4
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_PTAP_ADJ_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT    2
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_MASK     (0x3 << ddrcReg_PHY_ADDR_CTL_PLL_CTL2_CTAP_ADJ_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_LOWCUR_ENABLE     (0x1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_PLL_CTL2_BIASIN_ENABLE     (0x1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_EN_ENABLE           (0x1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT  16
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_MASK   (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_CYC_PER_TICK_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT      0
+#define ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_MASK       (0xffff << ddrcReg_PHY_ADDR_CTL_PLL_SS_CFG_NDIV_AMP_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FORCE           (1 << 20)
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_ENABLE          (1 << 16)
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT      12
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_FALL_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT      8
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_MASK       (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_RISE_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT      0
+#define ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_MASK       (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_STATIC_OVR_STEP_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_ENABLE         (1 << 16)
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT     12
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_FALL_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT     8
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_MASK      (0x3 << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_RISE_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT     0
+#define ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_MASK      (0x3f << ddrcReg_PHY_ADDR_CTL_VDL_DYNAMIC_OVR_STEP_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_ENABLE            (1u << 31)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_RXENB_DISABLE     (1 << 8)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_IDDQ_DISABLE  (1 << 6)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_REB_DISABLE   (1 << 5)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CTL_OEB_DISABLE   (1 << 4)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_IDDQ_DISABLE  (1 << 2)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_REB_DISABLE   (1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_PAD_IDLE_CKE_OEB_DISABLE   (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_DONE           (1 << 30)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_DONE           (1 << 29)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_DONE       (1 << 28)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_AUTO_ENABLE    (1 << 27)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_SAMPLE_ENABLE     (1 << 26)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_OVR_ENABLE   (1 << 25)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_OVR_ENABLE     (1 << 24)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT          20
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_PD_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT          16
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_MASK           (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ND_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT     12
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_PD_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT     8
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_MASK      (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_ADDR_ND_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT       4
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_PD_SHIFT)
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT       0
+#define ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_MASK        (0xf << ddrcReg_PHY_ADDR_CTL_PVT_COMP_DQ_ND_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_RT60B            (1 << 4)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SEL_SSTL18       (1 << 3)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELTXDRV_CI      (1 << 2)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SELRXDRV         (1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_PAD_DRIVE_SLEW             (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_HALF     (1 << 1)
+#define ddrcReg_PHY_ADDR_CTL_CLK_RGLTR_CTL_PWR_OFF      (1 << 0)
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+/* Broadcom DDR23 PHY Byte Lane register definitions */
+/* -------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_CNT                       2
+#define ddrcReg_PHY_BYTE_LANE_MAX                       (ddrcReg_CTLR_BYTE_LANE_CNT - 1)
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT               8
+        typedef struct {
+                uint32_t revision;
+                uint32_t vdlCalibrate;
+                uint32_t vdlStatus;
+                 REG32_RSVD(0x000c, 0x0010);
+                uint32_t vdlOverride[ddrcReg_PHY_BYTE_LANE_VDL_OVR_CNT];
+                uint32_t readCtl;
+                uint32_t readStatus;
+                uint32_t readClear;
+                uint32_t padIdleCtl;
+                uint32_t padDriveCtl;
+                uint32_t padClkCtl;
+                uint32_t writeCtl;
+                uint32_t clkRegCtl;
+        } ddrcReg_PHY_BYTE_LANE_REG_t;
+/* There are 2 instances of the byte Lane registers, one for each byte lane. */
+#define ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET              0x0500
+#define ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET              0x0600
+#define ddrcReg_PHY_BYTE_LANE_1_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_1_REG_OFFSET))
+#define ddrcReg_PHY_BYTE_LANE_2_REGP                    ((volatile ddrcReg_PHY_BYTE_LANE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_PHY_BYTE_LANE_2_REG_OFFSET))
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT      8
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MAJOR_SHIFT)
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT      0
+#define ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_MASK       (0xff << ddrcReg_PHY_BYTE_LANE_REVISION_MINOR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_2CYCLE      (1 << 4)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_CLK_1CYCLE      (0 << 4)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_TEST            (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ALWAYS          (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_ONCE            (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_VDL_CALIB_FAST            (1 << 0)
+/* ----------------------------------------------------- */
+/* The byte lane VDL status calibTotal[9:0] is comprised of [9:4] step value, [3:2] fine fall */
+/* and [1:0] fine rise. Note that calibTotal[9:0] is located at bit 4 in the VDL status */
+/* register. The fine rise and fall are no longer used, so add some definitions for just */
+/* the step setting to simplify things. */
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT     8
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_MASK      (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_STEP_SHIFT)
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT    4
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_MASK     (0x3ff << ddrcReg_PHY_BYTE_LANE_VDL_STATUS_TOTAL_SHIFT)
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_LOCK           (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_VDL_STATUS_IDLE           (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_ENABLE            (1 << 16)
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT        12
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_FALL_SHIFT)
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT        8
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_MASK         (0x3 << ddrcReg_PHY_BYTE_LANE_VDL_OVR_RISE_SHIFT)
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT        0
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_MASK         (0x3f << ddrcReg_PHY_BYTE_LANE_VDL_OVR_STEP_SHIFT)
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_P     0
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_DQS_N     1
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_READ_EN        2
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_STATIC_WRITE_DQ_DQM   3
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_P    4
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_DQS_N    5
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_READ_EN       6
+#define ddrcReg_PHY_BYTE_LANE_VDL_OVR_IDX_DYNAMIC_WRITE_DQ_DQM  7
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT      8
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_MASK       (0x3 << ddrcReg_PHY_BYTE_LANE_READ_CTL_DELAY_SHIFT)
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ENABLE    (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_DQ_ODT_ADJUST    (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ENABLE    (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_READ_CTL_RD_ODT_ADJUST    (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT   0
+#define ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_MASK    (0xf << ddrcReg_PHY_BYTE_LANE_READ_STATUS_ERROR_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_READ_CLEAR_STATUS         (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_ENABLE                   (1u << 31)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_RXENB_DISABLE         (1 << 19)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_IDDQ_DISABLE          (1 << 18)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_REB_DISABLE           (1 << 17)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DM_OEB_DISABLE           (1 << 16)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_RXENB_DISABLE         (1 << 15)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_IDDQ_DISABLE          (1 << 14)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_REB_DISABLE           (1 << 13)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQ_OEB_DISABLE           (1 << 12)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_RXENB_DISABLE   (1 << 11)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_IDDQ_DISABLE    (1 << 10)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_REB_DISABLE     (1 << 9)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_READ_ENB_OEB_DISABLE     (1 << 8)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_RXENB_DISABLE        (1 << 7)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_IDDQ_DISABLE         (1 << 6)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_REB_DISABLE          (1 << 5)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_DQS_OEB_DISABLE          (1 << 4)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_RXENB_DISABLE        (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_IDDQ_DISABLE         (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_REB_DISABLE          (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_PAD_IDLE_CTL_CLK_OEB_DISABLE          (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B_DDR_READ_ENB      (1 << 5)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_RT60B                   (1 << 4)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SEL_SSTL18              (1 << 3)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELTXDRV_CI             (1 << 2)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SELRXDRV                (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_PAD_DRIVE_CTL_SLEW                    (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_PAD_CLK_CTL_DISABLE                   (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_WRITE_CTL_PREAMBLE_DDR3               (1 << 0)
+/* ----------------------------------------------------- */
+#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_HALF                  (1 << 1)
+#define ddrcReg_PHY_BYTE_LANE_CLK_REG_CTL_PWR_OFF                   (1 << 0)
+/*********************************************************************/
+/* ARM PL341 DDRC to Broadcom DDR23 PHY glue register definitions */
+/*********************************************************************/
+        typedef struct {
+                uint32_t cfg;
+                uint32_t actMonCnt;
+                uint32_t ctl;
+                uint32_t lbistCtl;
+                uint32_t lbistSeed;
+                uint32_t lbistStatus;
+                uint32_t tieOff;
+                uint32_t actMonClear;
+                uint32_t status;
+                uint32_t user;
+        } ddrcReg_CTLR_PHY_GLUE_REG_t;
+#define ddrcReg_CTLR_PHY_GLUE_OFFSET                            0x0700
+#define ddrcReg_CTLR_PHY_GLUE_REGP                              ((volatile ddrcReg_CTLR_PHY_GLUE_REG_t *) (MM_IO_BASE_DDRC + ddrcReg_CTLR_PHY_GLUE_OFFSET))
+/* ----------------------------------------------------- */
+/* DDR2 / AXI block phase alignment interrupt control */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT                     18
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_MASK                      (0x3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_OFF                       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_TIGHT                  (1 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_MEDIUM                 (2 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_INT_ON_LOOSE                  (3 << ddrcReg_CTLR_PHY_GLUE_CFG_INT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT              17
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_MASK               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_DIFFERENTIAL       (0 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_CMOS               (1 << ddrcReg_CTLR_PHY_GLUE_CFG_PLL_REFCLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT            16
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_MASK             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_DEEP             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW          (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_HW_FIXED_ALIGNMENT_DISABLED   ddrcReg_CTLR_PHY_GLUE_CFG_DIV2CLK_TREE_SHALLOW
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT             15
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_MASK              (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_BP134             (0 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301             (1 << ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_REGISTERED        ddrcReg_CTLR_PHY_GLUE_CFG_SYNC_BRIDGE_PL301
+/* Software control of PHY VDL updates from control register settings. Bit 13 enables the use of Bit 14. */
+/* If software control is not enabled, then updates occur when a refresh command is issued by the hardware */
+/* controller. If 2 chips selects are being used, then software control must be enabled. */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_LOAD    (1 << 14)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_VDL_UPDATE_SW_CTL_ENABLE  (1 << 13)
+/* Use these to bypass a pipeline stage. By default the ADDR is off but the BYTE LANE in / out are on. */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_ADDR_CTL_IN_BYPASS_PIPELINE_STAGE (1 << 12)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_IN_BYPASS_PIPELINE_STAGE (1 << 11)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_PHY_BYTE_LANE_OUT_BYPASS_PIPELINE_STAGE (1 << 10)
+/* Chip select count */
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT                  9
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_MASK                   (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_1                      (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_2                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CS_CNT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT                     8
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_ASYNC                     (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SYNC                      (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CLK_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT                7
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_CKE_INIT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT                6
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_LOW                  (0 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_HIGH                 (1 << ddrcReg_CTLR_PHY_GLUE_CFG_DQM_INIT_SHIFT)
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT             0
+#define ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_MASK              (0x7 << ddrcReg_CTLR_PHY_GLUE_CFG_CAS_LATENCY_SHIFT)
+/* ----------------------------------------------------- */
+#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT                0
+#define ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_MASK                 (0x7f << ddrcReg_CTLR_PHY_GLUE_STATUS_PHASE_SHIFT)
+/* ---- Public Function Prototypes --------------------------------------- */
+#ifdef __cplusplus
+}                               /* end extern "C" */
+#endif
+#endif                          /* DDRC_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
new file mode 100644
index 000000000000..375066ad0186
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_priv.h
@@ -0,0 +1,145 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    dmacHw_priv.h
+*
+*  @brief   Private Definitions for low level DMA driver
+*
+*/
+/****************************************************************************/
+#ifndef _DMACHW_PRIV_H
+#define _DMACHW_PRIV_H
+#include <csp/stdint.h>
+/* Data type for DMA Link List Item */
+typedef struct {
+        uint32_t sar;           /* Source Adress Register.
+                                   Address must be aligned to CTLx.SRC_TR_WIDTH.             */
+        uint32_t dar;           /* Destination Address Register.
+                                   Address must be aligned to CTLx.DST_TR_WIDTH.             */
+        uint32_t llpPhy;        /* LLP contains the physical address of the next descriptor for block chaining using linked lists.
+                                   Address MUST be aligned to a 32-bit boundary.             */
+        dmacHw_REG64_t ctl;     /* Control Register. 64 bits */
+        uint32_t sstat;         /* Source Status Register */
+        uint32_t dstat;         /* Destination Status Register */
+        uint32_t devCtl;        /* Device specific control information */
+        uint32_t llp;           /* LLP contains the virtual address of the next descriptor for block chaining using linked lists. */
+} dmacHw_DESC_t;
+/*
+ *  Descriptor ring pointers
+ */
+typedef struct {
+        int num;                /* Number of link items */
+        dmacHw_DESC_t *pHead;   /* Head of descriptor ring (for writing) */
+        dmacHw_DESC_t *pTail;   /* Tail of descriptor ring (for reading) */
+        dmacHw_DESC_t *pProg;   /* Descriptor to program the channel (for programming the channel register) */
+        dmacHw_DESC_t *pEnd;    /* End of current descriptor chain */
+        dmacHw_DESC_t *pFree;   /* Descriptor to free memory (freeing dynamic memory) */
+        uint32_t virt2PhyOffset;        /* Virtual to physical address offset for the descriptor ring */
+} dmacHw_DESC_RING_t;
+/*
+ *  DMA channel control block
+ */
+typedef struct {
+        uint32_t module;        /* DMA controller module (0-1) */
+        uint32_t channel;       /* DMA channel (0-7) */
+        volatile uint32_t varDataStarted;       /* Flag indicating variable data channel is enabled */
+        volatile uint32_t descUpdated;  /* Flag to indicate descriptor update is complete */
+        void *userData;         /* Channel specifc user data */
+} dmacHw_CBLK_t;
+#define dmacHw_ASSERT(a)                  if (!(a)) while (1)
+#define dmacHw_MAX_CHANNEL_COUNT          16
+#define dmacHw_FREE_USER_MEMORY           0xFFFFFFFF
+#define dmacHw_DESC_FREE                  dmacHw_REG_CTL_DONE
+#define dmacHw_DESC_INIT                  ((dmacHw_DESC_t *) 0xFFFFFFFF)
+#define dmacHw_MAX_BLOCKSIZE              4064
+#define dmacHw_GET_DESC_RING(addr)        (dmacHw_DESC_RING_t *)(addr)
+#define dmacHw_ADDRESS_MASK(byte)         ((byte) - 1)
+#define dmacHw_NEXT_DESC(rp, dp)           ((rp)->dp = (dmacHw_DESC_t *)(rp)->dp->llp)
+#define dmacHw_HANDLE_TO_CBLK(handle)     ((dmacHw_CBLK_t *) (handle))
+#define dmacHw_CBLK_TO_HANDLE(cblkp)      ((dmacHw_HANDLE_t) (cblkp))
+#define dmacHw_DST_IS_MEMORY(tt)          (((tt) ==  dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM) || ((tt) == dmacHw_TRANSFER_TYPE_MEM_TO_MEM)) ? 1 : 0
+/****************************************************************************/
+/**
+*  @brief   Get next available transaction width
+*
+*
+*  @return  On sucess  : Next avail able transaction width
+*           On failure : dmacHw_TRANSACTION_WIDTH_8
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static inline dmacHw_TRANSACTION_WIDTH_e dmacHw_GetNextTrWidth(dmacHw_TRANSACTION_WIDTH_e tw    /*   [ IN ] Current transaction width */
+    ) {
+        if (tw & dmacHw_REG_CTL_SRC_TR_WIDTH_MASK) {
+                return ((tw >> dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT) -
+                         1) << dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT;
+        } else if (tw & dmacHw_REG_CTL_DST_TR_WIDTH_MASK) {
+                return ((tw >> dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT) -
+                         1) << dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT;
+        }
+        /* Default return  */
+        return dmacHw_SRC_TRANSACTION_WIDTH_8;
+}
+/****************************************************************************/
+/**
+*  @brief   Get number of bytes per transaction
+*
+*  @return  Number of bytes per transaction
+*
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+static inline int dmacHw_GetTrWidthInBytes(dmacHw_TRANSACTION_WIDTH_e tw        /*   [ IN ]  Transaction width */
+    ) {
+        int width = 1;
+        switch (tw) {
+        case dmacHw_SRC_TRANSACTION_WIDTH_8:
+                width = 1;
+                break;
+        case dmacHw_SRC_TRANSACTION_WIDTH_16:
+        case dmacHw_DST_TRANSACTION_WIDTH_16:
+                width = 2;
+                break;
+        case dmacHw_SRC_TRANSACTION_WIDTH_32:
+        case dmacHw_DST_TRANSACTION_WIDTH_32:
+                width = 4;
+                break;
+        case dmacHw_SRC_TRANSACTION_WIDTH_64:
+        case dmacHw_DST_TRANSACTION_WIDTH_64:
+                width = 8;
+                break;
+        default:
+                dmacHw_ASSERT(0);
+        }
+        /* Default transaction width */
+        return width;
+}
+#endif /* _DMACHW_PRIV_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
new file mode 100644
index 000000000000..891cea87e333
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/dmacHw_reg.h
@@ -0,0 +1,406 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    dmacHw_reg.h
+*
+*  @brief   Definitions for low level DMA registers
+*
+*/
+/****************************************************************************/
+#ifndef _DMACHW_REG_H
+#define _DMACHW_REG_H
+#include <csp/stdint.h>
+#include <mach/csp/mm_io.h>
+/* Data type for 64 bit little endian register */
+typedef struct {
+        volatile uint32_t lo;   /* Lower 32 bit in little endian mode */
+        volatile uint32_t hi;   /* Upper 32 bit in little endian mode */
+} dmacHw_REG64_t;
+/* Data type representing DMA channel registers */
+typedef struct {
+        dmacHw_REG64_t ChannelSar;      /*  Source Adress Register. 64 bits (upper 32 bits are reserved)
+                                           Address must be aligned to CTLx.SRC_TR_WIDTH.
+                                         */
+        dmacHw_REG64_t ChannelDar;      /*  Destination Address Register.64 bits (upper 32 bits are reserved)
+                                           Address must be aligned to CTLx.DST_TR_WIDTH.
+                                         */
+        dmacHw_REG64_t ChannelLlp;      /*  Link List Pointer.64 bits (upper 32 bits are reserved)
+                                           LLP contains the pointer to the next LLI for block chaining using linked lists.
+                                           If LLPis set to 0x0, then transfers using linked lists are not enabled.
+                                           Address MUST be aligned to a 32-bit boundary.
+                                         */
+        dmacHw_REG64_t ChannelCtl;      /* Control Register. 64 bits */
+        dmacHw_REG64_t ChannelSstat;    /* Source Status Register */
+        dmacHw_REG64_t ChannelDstat;    /* Destination Status Register */
+        dmacHw_REG64_t ChannelSstatAddr;        /* Source Status Address Register */
+        dmacHw_REG64_t ChannelDstatAddr;        /* Destination Status Address Register */
+        dmacHw_REG64_t ChannelConfig;   /* Channel Configuration Register */
+        dmacHw_REG64_t SrcGather;       /* Source gather register */
+        dmacHw_REG64_t DstScatter;      /* Destination scatter register */
+} dmacHw_CH_REG_t;
+/* Data type for RAW interrupt status registers */
+typedef struct {
+        dmacHw_REG64_t RawTfr;  /* Raw Status for IntTfr Interrupt */
+        dmacHw_REG64_t RawBlock;        /* Raw Status for IntBlock Interrupt */
+        dmacHw_REG64_t RawSrcTran;      /* Raw Status for IntSrcTran Interrupt */
+        dmacHw_REG64_t RawDstTran;      /* Raw Status for IntDstTran Interrupt */
+        dmacHw_REG64_t RawErr;  /* Raw Status for IntErr Interrupt */
+} dmacHw_INT_RAW_t;
+/* Data type for interrupt status registers */
+typedef struct {
+        dmacHw_REG64_t StatusTfr;       /* Status for IntTfr Interrupt */
+        dmacHw_REG64_t StatusBlock;     /* Status for IntBlock Interrupt */
+        dmacHw_REG64_t StatusSrcTran;   /* Status for IntSrcTran Interrupt */
+        dmacHw_REG64_t StatusDstTran;   /* Status for IntDstTran Interrupt */
+        dmacHw_REG64_t StatusErr;       /* Status for IntErr Interrupt */
+} dmacHw_INT_STATUS_t;
+/* Data type for interrupt mask registers*/
+typedef struct {
+        dmacHw_REG64_t MaskTfr; /* Mask for IntTfr Interrupt */
+        dmacHw_REG64_t MaskBlock;       /* Mask for IntBlock Interrupt */
+        dmacHw_REG64_t MaskSrcTran;     /* Mask for IntSrcTran Interrupt */
+        dmacHw_REG64_t MaskDstTran;     /* Mask for IntDstTran Interrupt */
+        dmacHw_REG64_t MaskErr; /* Mask for IntErr Interrupt */
+} dmacHw_INT_MASK_t;
+/* Data type for interrupt clear registers */
+typedef struct {
+        dmacHw_REG64_t ClearTfr;        /* Clear for IntTfr Interrupt */
+        dmacHw_REG64_t ClearBlock;      /* Clear for IntBlock Interrupt */
+        dmacHw_REG64_t ClearSrcTran;    /* Clear for IntSrcTran Interrupt */
+        dmacHw_REG64_t ClearDstTran;    /* Clear for IntDstTran Interrupt */
+        dmacHw_REG64_t ClearErr;        /* Clear for IntErr Interrupt */
+        dmacHw_REG64_t StatusInt;       /* Status for each interrupt type */
+} dmacHw_INT_CLEAR_t;
+/* Data type for software handshaking registers */
+typedef struct {
+        dmacHw_REG64_t ReqSrcReg;       /* Source Software Transaction Request Register */
+        dmacHw_REG64_t ReqDstReg;       /* Destination Software Transaction Request Register */
+        dmacHw_REG64_t SglReqSrcReg;    /* Single Source Transaction Request Register */
+        dmacHw_REG64_t SglReqDstReg;    /* Single Destination Transaction Request Register */
+        dmacHw_REG64_t LstSrcReg;       /* Last Source Transaction Request Register */
+        dmacHw_REG64_t LstDstReg;       /* Last Destination Transaction Request Register */
+} dmacHw_SW_HANDSHAKE_t;
+/* Data type for misc. registers */
+typedef struct {
+        dmacHw_REG64_t DmaCfgReg;       /* DMA Configuration Register */
+        dmacHw_REG64_t ChEnReg; /* DMA Channel Enable Register */
+        dmacHw_REG64_t DmaIdReg;        /* DMA ID Register */
+        dmacHw_REG64_t DmaTestReg;      /* DMA Test Register */
+        dmacHw_REG64_t Reserved0;       /* Reserved */
+        dmacHw_REG64_t Reserved1;       /* Reserved */
+        dmacHw_REG64_t CompParm6;       /* Component Parameter 6 */
+        dmacHw_REG64_t CompParm5;       /* Component Parameter 5 */
+        dmacHw_REG64_t CompParm4;       /* Component Parameter 4 */
+        dmacHw_REG64_t CompParm3;       /* Component Parameter 3 */
+        dmacHw_REG64_t CompParm2;       /* Component Parameter 2 */
+        dmacHw_REG64_t CompParm1;       /* Component Parameter 1 */
+        dmacHw_REG64_t CompId;  /* Compoent ID */
+} dmacHw_MISC_t;
+/* Base registers */
+#define dmacHw_0_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA0       /* DMAC 0 module's base address */
+#define dmacHw_1_MODULE_BASE_ADDR        (char *) MM_IO_BASE_DMA1       /* DMAC 1 module's base address */
+extern uint32_t dmaChannelCount_0;
+extern uint32_t dmaChannelCount_1;
+/* Define channel specific registers */
+#define dmacHw_CHAN_BASE(module, chan)          ((dmacHw_CH_REG_t *) ((char *)((module) ? dmacHw_1_MODULE_BASE_ADDR : dmacHw_0_MODULE_BASE_ADDR) + ((chan) * sizeof(dmacHw_CH_REG_t))))
+/* Raw interrupt status registers */
+#define dmacHw_REG_INT_RAW_BASE(module)         ((char *)dmacHw_CHAN_BASE((module), ((module) ? dmaChannelCount_1 : dmaChannelCount_0)))
+#define dmacHw_REG_INT_RAW_TRAN(module)         (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawTfr.lo)
+#define dmacHw_REG_INT_RAW_BLOCK(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawBlock.lo)
+#define dmacHw_REG_INT_RAW_STRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawSrcTran.lo)
+#define dmacHw_REG_INT_RAW_DTRAN(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawDstTran.lo)
+#define dmacHw_REG_INT_RAW_ERROR(module)        (((dmacHw_INT_RAW_t *) dmacHw_REG_INT_RAW_BASE((module)))->RawErr.lo)
+/* Interrupt status registers */
+#define dmacHw_REG_INT_STAT_BASE(module)        ((char *)(dmacHw_REG_INT_RAW_BASE((module)) + sizeof(dmacHw_INT_RAW_t)))
+#define dmacHw_REG_INT_STAT_TRAN(module)        (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusTfr.lo)
+#define dmacHw_REG_INT_STAT_BLOCK(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusBlock.lo)
+#define dmacHw_REG_INT_STAT_STRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusSrcTran.lo)
+#define dmacHw_REG_INT_STAT_DTRAN(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusDstTran.lo)
+#define dmacHw_REG_INT_STAT_ERROR(module)       (((dmacHw_INT_STATUS_t *) dmacHw_REG_INT_STAT_BASE((module)))->StatusErr.lo)
+/* Interrupt status registers */
+#define dmacHw_REG_INT_MASK_BASE(module)        ((char *)(dmacHw_REG_INT_STAT_BASE((module)) + sizeof(dmacHw_INT_STATUS_t)))
+#define dmacHw_REG_INT_MASK_TRAN(module)        (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskTfr.lo)
+#define dmacHw_REG_INT_MASK_BLOCK(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskBlock.lo)
+#define dmacHw_REG_INT_MASK_STRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskSrcTran.lo)
+#define dmacHw_REG_INT_MASK_DTRAN(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskDstTran.lo)
+#define dmacHw_REG_INT_MASK_ERROR(module)       (((dmacHw_INT_MASK_t *) dmacHw_REG_INT_MASK_BASE((module)))->MaskErr.lo)
+/* Interrupt clear registers */
+#define dmacHw_REG_INT_CLEAR_BASE(module)       ((char *)(dmacHw_REG_INT_MASK_BASE((module)) + sizeof(dmacHw_INT_MASK_t)))
+#define dmacHw_REG_INT_CLEAR_TRAN(module)       (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearTfr.lo)
+#define dmacHw_REG_INT_CLEAR_BLOCK(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearBlock.lo)
+#define dmacHw_REG_INT_CLEAR_STRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearSrcTran.lo)
+#define dmacHw_REG_INT_CLEAR_DTRAN(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearDstTran.lo)
+#define dmacHw_REG_INT_CLEAR_ERROR(module)      (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->ClearErr.lo)
+#define dmacHw_REG_INT_STATUS(module)           (((dmacHw_INT_CLEAR_t *) dmacHw_REG_INT_CLEAR_BASE((module)))->StatusInt.lo)
+/* Software handshaking registers */
+#define dmacHw_REG_SW_HS_BASE(module)           ((char *)(dmacHw_REG_INT_CLEAR_BASE((module)) + sizeof(dmacHw_INT_CLEAR_t)))
+#define dmacHw_REG_SW_HS_SRC_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_REQ(module)        (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->ReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_SGL_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->SglReqDstReg.lo)
+#define dmacHw_REG_SW_HS_SRC_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstSrcReg.lo)
+#define dmacHw_REG_SW_HS_DST_LST_REQ(module)    (((dmacHw_SW_HANDSHAKE_t *) dmacHw_REG_SW_HS_BASE((module)))->LstDstReg.lo)
+/* Miscellaneous registers */
+#define dmacHw_REG_MISC_BASE(module)            ((char *)(dmacHw_REG_SW_HS_BASE((module)) + sizeof(dmacHw_SW_HANDSHAKE_t)))
+#define dmacHw_REG_MISC_CFG(module)             (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaCfgReg.lo)
+#define dmacHw_REG_MISC_CH_ENABLE(module)       (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->ChEnReg.lo)
+#define dmacHw_REG_MISC_ID(module)              (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaIdReg.lo)
+#define dmacHw_REG_MISC_TEST(module)            (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->DmaTestReg.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.lo)
+#define dmacHw_REG_MISC_COMP_PARAM1_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm1.hi)
+#define dmacHw_REG_MISC_COMP_PARAM2_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.lo)
+#define dmacHw_REG_MISC_COMP_PARAM2_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm2.hi)
+#define dmacHw_REG_MISC_COMP_PARAM3_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.lo)
+#define dmacHw_REG_MISC_COMP_PARAM3_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm3.hi)
+#define dmacHw_REG_MISC_COMP_PARAM4_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.lo)
+#define dmacHw_REG_MISC_COMP_PARAM4_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm4.hi)
+#define dmacHw_REG_MISC_COMP_PARAM5_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.lo)
+#define dmacHw_REG_MISC_COMP_PARAM5_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm5.hi)
+#define dmacHw_REG_MISC_COMP_PARAM6_LO(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.lo)
+#define dmacHw_REG_MISC_COMP_PARAM6_HI(module)  (((dmacHw_MISC_t *) dmacHw_REG_MISC_BASE((module)))->CompParm6.hi)
+/* Channel control registers */
+#define dmacHw_REG_SAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelSar.lo)
+#define dmacHw_REG_DAR(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelDar.lo)
+#define dmacHw_REG_LLP(module, chan)            (dmacHw_CHAN_BASE((module), (chan))->ChannelLlp.lo)
+#define dmacHw_REG_CTL_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.lo)
+#define dmacHw_REG_CTL_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelCtl.hi)
+#define dmacHw_REG_SSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelSstat.lo)
+#define dmacHw_REG_DSTAT(module, chan)          (dmacHw_CHAN_BASE((module), (chan))->ChannelDstat.lo)
+#define dmacHw_REG_SSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelSstatAddr.lo)
+#define dmacHw_REG_DSTATAR(module, chan)        (dmacHw_CHAN_BASE((module), (chan))->ChannelDstatAddr.lo)
+#define dmacHw_REG_CFG_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.lo)
+#define dmacHw_REG_CFG_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->ChannelConfig.hi)
+#define dmacHw_REG_SGR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.lo)
+#define dmacHw_REG_SGR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->SrcGather.hi)
+#define dmacHw_REG_DSR_LO(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.lo)
+#define dmacHw_REG_DSR_HI(module, chan)         (dmacHw_CHAN_BASE((module), (chan))->DstScatter.hi)
+#define INT_STATUS_MASK(channel)                (0x00000001 << (channel))
+#define CHANNEL_BUSY(mod, channel)              (dmacHw_REG_MISC_CH_ENABLE((mod)) & (0x00000001 << (channel)))
+/* Bit mask for REG_DMACx_CTL_LO */
+#define dmacHw_REG_CTL_INT_EN                       0x00000001  /* Channel interrupt enable */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_MASK            0x0000000E  /* Destination transaction width mask */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_SHIFT           1
+#define dmacHw_REG_CTL_DST_TR_WIDTH_8               0x00000000  /* Destination transaction width 8 bit */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_16              0x00000002  /* Destination transaction width 16 bit */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_32              0x00000004  /* Destination transaction width 32 bit */
+#define dmacHw_REG_CTL_DST_TR_WIDTH_64              0x00000006  /* Destination transaction width 64 bit */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_MASK            0x00000070  /* Source transaction width mask */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_SHIFT           4
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_8               0x00000000  /* Source transaction width 8 bit */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_16              0x00000010  /* Source transaction width 16 bit */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_32              0x00000020  /* Source transaction width 32 bit */
+#define dmacHw_REG_CTL_SRC_TR_WIDTH_64              0x00000030  /* Source transaction width 64 bit */
+#define dmacHw_REG_CTL_DS_ENABLE                    0x00040000  /* Destination scatter enable */
+#define dmacHw_REG_CTL_SG_ENABLE                    0x00020000  /* Source gather enable */
+#define dmacHw_REG_CTL_DINC_MASK                    0x00000180  /* Destination address inc/dec mask */
+#define dmacHw_REG_CTL_DINC_INC                     0x00000000  /* Destination address increment */
+#define dmacHw_REG_CTL_DINC_DEC                     0x00000080  /* Destination address decrement */
+#define dmacHw_REG_CTL_DINC_NC                      0x00000100  /* Destination address no change */
+#define dmacHw_REG_CTL_SINC_MASK                    0x00000600  /* Source address inc/dec mask */
+#define dmacHw_REG_CTL_SINC_INC                     0x00000000  /* Source address increment */
+#define dmacHw_REG_CTL_SINC_DEC                     0x00000200  /* Source address decrement */
+#define dmacHw_REG_CTL_SINC_NC                      0x00000400  /* Source address no change */
+#define dmacHw_REG_CTL_DST_MSIZE_MASK               0x00003800  /* Destination burst transaction length */
+#define dmacHw_REG_CTL_DST_MSIZE_0                  0x00000000  /* No Destination burst */
+#define dmacHw_REG_CTL_DST_MSIZE_4                  0x00000800  /* Destination burst transaction length 4 */
+#define dmacHw_REG_CTL_DST_MSIZE_8                  0x00001000  /* Destination burst transaction length 8 */
+#define dmacHw_REG_CTL_DST_MSIZE_16                 0x00001800  /* Destination burst transaction length 16 */
+#define dmacHw_REG_CTL_SRC_MSIZE_MASK               0x0001C000  /* Source burst transaction length */
+#define dmacHw_REG_CTL_SRC_MSIZE_0                  0x00000000  /* No Source burst */
+#define dmacHw_REG_CTL_SRC_MSIZE_4                  0x00004000  /* Source burst transaction length 4 */
+#define dmacHw_REG_CTL_SRC_MSIZE_8                  0x00008000  /* Source burst transaction length 8 */
+#define dmacHw_REG_CTL_SRC_MSIZE_16                 0x0000C000  /* Source burst transaction length 16 */
+#define dmacHw_REG_CTL_TTFC_MASK                    0x00700000  /* Transfer type and flow controller */
+#define dmacHw_REG_CTL_TTFC_MM_DMAC                 0x00000000  /* Memory to Memory with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_MP_DMAC                 0x00100000  /* Memory to Peripheral with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_PM_DMAC                 0x00200000  /* Peripheral to Memory with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_PP_DMAC                 0x00300000  /* Peripheral to Peripheral with DMAC as flow controller */
+#define dmacHw_REG_CTL_TTFC_PM_PERI                 0x00400000  /* Peripheral to Memory with Peripheral as flow controller */
+#define dmacHw_REG_CTL_TTFC_PP_SPERI                0x00500000  /* Peripheral to Peripheral with Source Peripheral as flow controller */
+#define dmacHw_REG_CTL_TTFC_MP_PERI                 0x00600000  /* Memory to Peripheral with Peripheral as flow controller */
+#define dmacHw_REG_CTL_TTFC_PP_DPERI                0x00700000  /* Peripheral to Peripheral with Destination Peripheral as flow controller */
+#define dmacHw_REG_CTL_DMS_MASK                     0x01800000  /* Destination AHB master interface */
+#define dmacHw_REG_CTL_DMS_1                        0x00000000  /* Destination AHB master interface 1 */
+#define dmacHw_REG_CTL_DMS_2                        0x00800000  /* Destination AHB master interface 2 */
+#define dmacHw_REG_CTL_SMS_MASK                     0x06000000  /* Source AHB master interface */
+#define dmacHw_REG_CTL_SMS_1                        0x00000000  /* Source AHB master interface 1 */
+#define dmacHw_REG_CTL_SMS_2                        0x02000000  /* Source AHB master interface 2 */
+#define dmacHw_REG_CTL_LLP_DST_EN                   0x08000000  /* Block chaining enable for destination side */
+#define dmacHw_REG_CTL_LLP_SRC_EN                   0x10000000  /* Block chaining enable for source side */
+/* Bit mask for REG_DMACx_CTL_HI */
+#define dmacHw_REG_CTL_BLOCK_TS_MASK                0x00000FFF  /* Block transfer size */
+#define dmacHw_REG_CTL_DONE                         0x00001000  /* Block trasnfer done */
+/* Bit mask for REG_DMACx_CFG_LO */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_SHIFT                  5  /* Channel priority shift */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_MASK          0x000000E0  /* Channel priority mask */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_0             0x00000000  /* Channel priority 0 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_1             0x00000020  /* Channel priority 1 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_2             0x00000040  /* Channel priority 2 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_3             0x00000060  /* Channel priority 3 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_4             0x00000080  /* Channel priority 4 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_5             0x000000A0  /* Channel priority 5 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_6             0x000000C0  /* Channel priority 6 */
+#define dmacHw_REG_CFG_LO_CH_PRIORITY_7             0x000000E0  /* Channel priority 7 */
+#define dmacHw_REG_CFG_LO_CH_SUSPEND                0x00000100  /* Channel suspend */
+#define dmacHw_REG_CFG_LO_CH_FIFO_EMPTY             0x00000200  /* Channel FIFO empty */
+#define dmacHw_REG_CFG_LO_DST_CH_SW_HS              0x00000400  /* Destination channel SW handshaking */
+#define dmacHw_REG_CFG_LO_SRC_CH_SW_HS              0x00000800  /* Source channel SW handshaking */
+#define dmacHw_REG_CFG_LO_CH_LOCK_MASK              0x00003000  /* Channel locking mask */
+#define dmacHw_REG_CFG_LO_CH_LOCK_DMA               0x00000000  /* Channel lock over the entire DMA transfer operation */
+#define dmacHw_REG_CFG_LO_CH_LOCK_BLOCK             0x00001000  /* Channel lock over the block transfer operation */
+#define dmacHw_REG_CFG_LO_CH_LOCK_TRANS             0x00002000  /* Channel lock over the transaction */
+#define dmacHw_REG_CFG_LO_CH_LOCK_ENABLE            0x00010000  /* Channel lock enable */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_MASK             0x0000C000  /* Bus locking mask */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_DMA              0x00000000  /* Bus lock over the entire DMA transfer operation */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_BLOCK            0x00004000  /* Bus lock over the block transfer operation */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_TRANS            0x00008000  /* Bus lock over the transaction */
+#define dmacHw_REG_CFG_LO_BUS_LOCK_ENABLE           0x00020000  /* Bus lock enable */
+#define dmacHw_REG_CFG_LO_DST_HS_POLARITY_LOW       0x00040000  /* Destination channel handshaking signal polarity low */
+#define dmacHw_REG_CFG_LO_SRC_HS_POLARITY_LOW       0x00080000  /* Source channel handshaking signal polarity low */
+#define dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK   0x3FF00000  /* Maximum AMBA burst length */
+#define dmacHw_REG_CFG_LO_AUTO_RELOAD_SRC           0x40000000  /* Source address auto reload */
+#define dmacHw_REG_CFG_LO_AUTO_RELOAD_DST           0x80000000  /* Destination address auto reload */
+/* Bit mask for REG_DMACx_CFG_HI */
+#define dmacHw_REG_CFG_HI_FC_DST_READY              0x00000001  /* Source transaction request is serviced when destination is ready */
+#define dmacHw_REG_CFG_HI_FIFO_ENOUGH               0x00000002  /* Initiate burst transaction when enough data in available in FIFO */
+#define dmacHw_REG_CFG_HI_AHB_HPROT_MASK            0x0000001C  /* AHB protection mask */
+#define dmacHw_REG_CFG_HI_AHB_HPROT_1               0x00000004  /* AHB protection 1 */
+#define dmacHw_REG_CFG_HI_AHB_HPROT_2               0x00000008  /* AHB protection 2 */
+#define dmacHw_REG_CFG_HI_AHB_HPROT_3               0x00000010  /* AHB protection 3 */
+#define dmacHw_REG_CFG_HI_UPDATE_DST_STAT           0x00000020  /* Destination status update enable */
+#define dmacHw_REG_CFG_HI_UPDATE_SRC_STAT           0x00000040  /* Source status update enable */
+#define dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK        0x00000780  /* Source peripheral hardware interface mask */
+#define dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK        0x00007800  /* Destination peripheral hardware interface mask */
+/* DMA Configuration Parameters */
+#define dmacHw_REG_COMP_PARAM_NUM_CHANNELS          0x00000700  /* Number of channels */
+#define dmacHw_REG_COMP_PARAM_NUM_INTERFACE         0x00001800  /* Number of master interface */
+#define dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE          0x0000000f  /* Maximum brust size */
+#define dmacHw_REG_COMP_PARAM_DATA_WIDTH            0x00006000  /* Data transfer width */
+/* Define GET/SET macros to program the registers */
+#define dmacHw_SET_SAR(module, channel, addr)          (dmacHw_REG_SAR((module), (channel)) = (uint32_t) (addr))
+#define dmacHw_SET_DAR(module, channel, addr)          (dmacHw_REG_DAR((module), (channel)) = (uint32_t) (addr))
+#define dmacHw_SET_LLP(module, channel, ptr)           (dmacHw_REG_LLP((module), (channel)) = (uint32_t) (ptr))
+#define dmacHw_GET_SSTAT(module, channel)              (dmacHw_REG_SSTAT((module), (channel)))
+#define dmacHw_GET_DSTAT(module, channel)              (dmacHw_REG_DSTAT((module), (channel)))
+#define dmacHw_SET_SSTATAR(module, channel, addr)      (dmacHw_REG_SSTATAR((module), (channel)) = (uint32_t) (addr))
+#define dmacHw_SET_DSTATAR(module, channel, addr)      (dmacHw_REG_DSTATAR((module), (channel)) = (uint32_t) (addr))
+#define dmacHw_SET_CONTROL_LO(module, channel, ctl)    (dmacHw_REG_CTL_LO((module), (channel)) |= (ctl))
+#define dmacHw_RESET_CONTROL_LO(module, channel)       (dmacHw_REG_CTL_LO((module), (channel)) = 0)
+#define dmacHw_GET_CONTROL_LO(module, channel)         (dmacHw_REG_CTL_LO((module), (channel)))
+#define dmacHw_SET_CONTROL_HI(module, channel, ctl)    (dmacHw_REG_CTL_HI((module), (channel)) |= (ctl))
+#define dmacHw_RESET_CONTROL_HI(module, channel)       (dmacHw_REG_CTL_HI((module), (channel)) = 0)
+#define dmacHw_GET_CONTROL_HI(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)))
+#define dmacHw_GET_BLOCK_SIZE(module, channel)         (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_BLOCK_TS_MASK)
+#define dmacHw_DMA_COMPLETE(module, channel)           (dmacHw_REG_CTL_HI((module), (channel)) & dmacHw_REG_CTL_DONE)
+#define dmacHw_SET_CONFIG_LO(module, channel, cfg)     (dmacHw_REG_CFG_LO((module), (channel)) |= (cfg))
+#define dmacHw_RESET_CONFIG_LO(module, channel)        (dmacHw_REG_CFG_LO((module), (channel)) = 0)
+#define dmacHw_GET_CONFIG_LO(module, channel)          (dmacHw_REG_CFG_LO((module), (channel)))
+#define dmacHw_SET_AMBA_BUSRT_LEN(module, channel, len)    (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK)) | (((len) << 20) & dmacHw_REG_CFG_LO_MAX_AMBA_BURST_LEN_MASK))
+#define dmacHw_SET_CHANNEL_PRIORITY(module, channel, prio) (dmacHw_REG_CFG_LO((module), (channel)) = (dmacHw_REG_CFG_LO((module), (channel)) & ~(dmacHw_REG_CFG_LO_CH_PRIORITY_MASK)) | (prio))
+#define dmacHw_SET_AHB_HPROT(module, channel, protect)  (dmacHw_REG_CFG_HI(module, channel) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_AHB_HPROT_MASK)) | (protect))
+#define dmacHw_SET_CONFIG_HI(module, channel, cfg)      (dmacHw_REG_CFG_HI((module), (channel)) |= (cfg))
+#define dmacHw_RESET_CONFIG_HI(module, channel)         (dmacHw_REG_CFG_HI((module), (channel)) = 0)
+#define dmacHw_GET_CONFIG_HI(module, channel)           (dmacHw_REG_CFG_HI((module), (channel)))
+#define dmacHw_SET_SRC_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)) | (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK))
+#define dmacHw_SRC_PERI_INTF(intf)                      (((intf) << 7) & dmacHw_REG_CFG_HI_SRC_PERI_INTF_MASK)
+#define dmacHw_SET_DST_PERI_INTF(module, channel, intf) (dmacHw_REG_CFG_HI((module), (channel)) = (dmacHw_REG_CFG_HI((module), (channel)) & ~(dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)) | (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK))
+#define dmacHw_DST_PERI_INTF(intf)                      (((intf) << 11) & dmacHw_REG_CFG_HI_DST_PERI_INTF_MASK)
+#define dmacHw_DMA_START(module, channel)              (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+#define dmacHw_DMA_STOP(module, channel)               (dmacHw_REG_MISC_CH_ENABLE((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_DMA_ENABLE(module)                      (dmacHw_REG_MISC_CFG((module)) = 1)
+#define dmacHw_DMA_DISABLE(module)                     (dmacHw_REG_MISC_CFG((module)) = 0)
+#define dmacHw_TRAN_INT_ENABLE(module, channel)        (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+#define dmacHw_BLOCK_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+#define dmacHw_ERROR_INT_ENABLE(module, channel)       (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)) | (0x00000001 << (channel)))
+#define dmacHw_TRAN_INT_DISABLE(module, channel)       (dmacHw_REG_INT_MASK_TRAN((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_BLOCK_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_BLOCK((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_ERROR_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_ERROR((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_STRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_STRAN((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_DTRAN_INT_DISABLE(module, channel)      (dmacHw_REG_INT_MASK_DTRAN((module)) = (0x00000001 << ((channel) + 8)))
+#define dmacHw_TRAN_INT_CLEAR(module, channel)         (dmacHw_REG_INT_CLEAR_TRAN((module)) = (0x00000001 << (channel)))
+#define dmacHw_BLOCK_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_BLOCK((module)) = (0x00000001 << (channel)))
+#define dmacHw_ERROR_INT_CLEAR(module, channel)        (dmacHw_REG_INT_CLEAR_ERROR((module)) = (0x00000001 << (channel)))
+#define dmacHw_GET_NUM_CHANNEL(module)                 (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_CHANNELS) >> 8) + 1)
+#define dmacHw_GET_NUM_INTERFACE(module)               (((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_NUM_INTERFACE) >> 11) + 1)
+#define dmacHw_GET_MAX_BLOCK_SIZE(module, channel)     ((dmacHw_REG_MISC_COMP_PARAM1_LO((module)) >> (4 * (channel))) & dmacHw_REG_COMP_PARAM_MAX_BLK_SIZE)
+#define dmacHw_GET_CHANNEL_DATA_WIDTH(module, channel) ((dmacHw_REG_MISC_COMP_PARAM1_HI((module)) & dmacHw_REG_COMP_PARAM_DATA_WIDTH) >> 13)
+#endif /* _DMACHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
new file mode 100644
index 000000000000..cfa91bed9d34
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/hw_cfg.h
@@ -0,0 +1,73 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef CSP_HW_CFG_H
+#define CSP_HW_CFG_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <cfg_global.h>
+#include <mach/csp/cap_inline.h>
+#if defined(__KERNEL__)
+#include <mach/memory_settings.h>
+#else
+#include <hw_cfg.h>
+#endif
+/* Some items that can be defined externally, but will be set to default values */
+/* if they are not defined. */
+/*      HW_CFG_PLL_SPREAD_SPECTRUM_DISABLE   Default undefined and SS is enabled. */
+/*      HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
+/*      HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
+/*      HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
+/*      HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
+/*      HW_CFG_SDRAM_ADDR_BRC                Default undefined and Row-Bank-Col (RBC) addressing used. Define to use Bank-Row-Col (BRC). */
+/*      HW_CFG_SDRAM_CLK_ASYNC               Default undefined and DDR clock is synchronous with AXI BUS clock. Define for ASYNC mode. */
+#if defined(CFG_GLOBAL_CHIP)
+  #if (CFG_GLOBAL_CHIP == FPGA11107)
+     #define HW_CFG_BUS_CLK_HZ            5000000
+     #define HW_CFG_DDR_CTLR_CLK_HZ      10000000
+     #define HW_CFG_DDR_PHY_OMIT
+     #define HW_CFG_UART_CLK_HZ           7500000
+  #else
+     #define HW_CFG_PLL_VCO_HZ           2000000000
+     #define HW_CFG_PLL2_VCO_HZ          1800000000
+     #define HW_CFG_ARM_CLK_HZ            CAP_HW_CFG_ARM_CLK_HZ
+     #define HW_CFG_BUS_CLK_HZ            166666666
+     #define HW_CFG_DDR_CTLR_CLK_HZ       333333333
+     #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
+     #define HW_CFG_UART_CLK_HZ           142857142
+     #define HW_CFG_VPM_CLK_HZ            CAP_HW_CFG_VPM_CLK_HZ
+  #endif
+#else
+   #define HW_CFG_PLL_VCO_HZ           1800000000
+   #define HW_CFG_PLL2_VCO_HZ          1800000000
+   #define HW_CFG_ARM_CLK_HZ            450000000
+   #define HW_CFG_BUS_CLK_HZ            150000000
+   #define HW_CFG_DDR_CTLR_CLK_HZ       300000000
+   #define HW_CFG_DDR_PHY_CLK_HZ        (2 * HW_CFG_DDR_CTLR_CLK_HZ)
+   #define HW_CFG_UART_CLK_HZ           150000000
+   #define HW_CFG_VPM_CLK_HZ            300000000
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /* CSP_HW_CFG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
new file mode 100644
index 000000000000..e01fc4607c91
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/intcHw_reg.h
@@ -0,0 +1,246 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    intcHw_reg.h
+*
+*  @brief   platform specific interrupt controller bit assignments
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+#ifndef _INTCHW_REG_H
+#define _INTCHW_REG_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <csp/stdint.h>
+#include <csp/reg.h>
+#include <mach/csp/mm_io.h>
+/* ---- Public Constants and Types --------------------------------------- */
+#define INTCHW_NUM_IRQ_PER_INTC   32    /* Maximum number of interrupt controllers */
+#define INTCHW_NUM_INTC           3
+/* Defines for interrupt controllers. This simplifies and cleans up the function calls. */
+#define INTCHW_INTC0    ((void *)MM_IO_BASE_INTC0)
+#define INTCHW_INTC1    ((void *)MM_IO_BASE_INTC1)
+#define INTCHW_SINTC    ((void *)MM_IO_BASE_SINTC)
+/* INTC0 - interrupt controller 0 */
+#define INTCHW_INTC0_PIF_BITNUM           31    /* Peripheral interface interrupt */
+#define INTCHW_INTC0_CLCD_BITNUM          30    /* LCD Controller interrupt */
+#define INTCHW_INTC0_GE_BITNUM            29    /* Graphic engine interrupt */
+#define INTCHW_INTC0_APM_BITNUM           28    /* Audio process module interrupt */
+#define INTCHW_INTC0_ESW_BITNUM           27    /* Ethernet switch interrupt */
+#define INTCHW_INTC0_SPIH_BITNUM          26    /* SPI host interrupt */
+#define INTCHW_INTC0_TIMER3_BITNUM        25    /* Timer3 interrupt */
+#define INTCHW_INTC0_TIMER2_BITNUM        24    /* Timer2 interrupt */
+#define INTCHW_INTC0_TIMER1_BITNUM        23    /* Timer1 interrupt */
+#define INTCHW_INTC0_TIMER0_BITNUM        22    /* Timer0 interrupt */
+#define INTCHW_INTC0_SDIOH1_BITNUM        21    /* SDIO1 host interrupt */
+#define INTCHW_INTC0_SDIOH0_BITNUM        20    /* SDIO0 host interrupt */
+#define INTCHW_INTC0_USBD_BITNUM          19    /* USB device interrupt */
+#define INTCHW_INTC0_USBH1_BITNUM         18    /* USB1 host interrupt */
+#define INTCHW_INTC0_USBHD2_BITNUM        17    /* USB host2/device2 interrupt */
+#define INTCHW_INTC0_VPM_BITNUM           16    /* Voice process module interrupt */
+#define INTCHW_INTC0_DMA1C7_BITNUM        15    /* DMA1 channel 7 interrupt */
+#define INTCHW_INTC0_DMA1C6_BITNUM        14    /* DMA1 channel 6 interrupt */
+#define INTCHW_INTC0_DMA1C5_BITNUM        13    /* DMA1 channel 5 interrupt */
+#define INTCHW_INTC0_DMA1C4_BITNUM        12    /* DMA1 channel 4 interrupt */
+#define INTCHW_INTC0_DMA1C3_BITNUM        11    /* DMA1 channel 3 interrupt */
+#define INTCHW_INTC0_DMA1C2_BITNUM        10    /* DMA1 channel 2 interrupt */
+#define INTCHW_INTC0_DMA1C1_BITNUM         9    /* DMA1 channel 1 interrupt */
+#define INTCHW_INTC0_DMA1C0_BITNUM         8    /* DMA1 channel 0 interrupt */
+#define INTCHW_INTC0_DMA0C7_BITNUM         7    /* DMA0 channel 7 interrupt */
+#define INTCHW_INTC0_DMA0C6_BITNUM         6    /* DMA0 channel 6 interrupt */
+#define INTCHW_INTC0_DMA0C5_BITNUM         5    /* DMA0 channel 5 interrupt */
+#define INTCHW_INTC0_DMA0C4_BITNUM         4    /* DMA0 channel 4 interrupt */
+#define INTCHW_INTC0_DMA0C3_BITNUM         3    /* DMA0 channel 3 interrupt */
+#define INTCHW_INTC0_DMA0C2_BITNUM         2    /* DMA0 channel 2 interrupt */
+#define INTCHW_INTC0_DMA0C1_BITNUM         1    /* DMA0 channel 1 interrupt */
+#define INTCHW_INTC0_DMA0C0_BITNUM         0    /* DMA0 channel 0 interrupt */
+#define INTCHW_INTC0_PIF                  (1<<INTCHW_INTC0_PIF_BITNUM)
+#define INTCHW_INTC0_CLCD                 (1<<INTCHW_INTC0_CLCD_BITNUM)
+#define INTCHW_INTC0_GE                   (1<<INTCHW_INTC0_GE_BITNUM)
+#define INTCHW_INTC0_APM                  (1<<INTCHW_INTC0_APM_BITNUM)
+#define INTCHW_INTC0_ESW                  (1<<INTCHW_INTC0_ESW_BITNUM)
+#define INTCHW_INTC0_SPIH                 (1<<INTCHW_INTC0_SPIH_BITNUM)
+#define INTCHW_INTC0_TIMER3               (1<<INTCHW_INTC0_TIMER3_BITNUM)
+#define INTCHW_INTC0_TIMER2               (1<<INTCHW_INTC0_TIMER2_BITNUM)
+#define INTCHW_INTC0_TIMER1               (1<<INTCHW_INTC0_TIMER1_BITNUM)
+#define INTCHW_INTC0_TIMER0               (1<<INTCHW_INTC0_TIMER0_BITNUM)
+#define INTCHW_INTC0_SDIOH1               (1<<INTCHW_INTC0_SDIOH1_BITNUM)
+#define INTCHW_INTC0_SDIOH0               (1<<INTCHW_INTC0_SDIOH0_BITNUM)
+#define INTCHW_INTC0_USBD                 (1<<INTCHW_INTC0_USBD_BITNUM)
+#define INTCHW_INTC0_USBH1                (1<<INTCHW_INTC0_USBH1_BITNUM)
+#define INTCHW_INTC0_USBHD2               (1<<INTCHW_INTC0_USBHD2_BITNUM)
+#define INTCHW_INTC0_VPM                  (1<<INTCHW_INTC0_VPM_BITNUM)
+#define INTCHW_INTC0_DMA1C7               (1<<INTCHW_INTC0_DMA1C7_BITNUM)
+#define INTCHW_INTC0_DMA1C6               (1<<INTCHW_INTC0_DMA1C6_BITNUM)
+#define INTCHW_INTC0_DMA1C5               (1<<INTCHW_INTC0_DMA1C5_BITNUM)
+#define INTCHW_INTC0_DMA1C4               (1<<INTCHW_INTC0_DMA1C4_BITNUM)
+#define INTCHW_INTC0_DMA1C3               (1<<INTCHW_INTC0_DMA1C3_BITNUM)
+#define INTCHW_INTC0_DMA1C2               (1<<INTCHW_INTC0_DMA1C2_BITNUM)
+#define INTCHW_INTC0_DMA1C1               (1<<INTCHW_INTC0_DMA1C1_BITNUM)
+#define INTCHW_INTC0_DMA1C0               (1<<INTCHW_INTC0_DMA1C0_BITNUM)
+#define INTCHW_INTC0_DMA0C7               (1<<INTCHW_INTC0_DMA0C7_BITNUM)
+#define INTCHW_INTC0_DMA0C6               (1<<INTCHW_INTC0_DMA0C6_BITNUM)
+#define INTCHW_INTC0_DMA0C5               (1<<INTCHW_INTC0_DMA0C5_BITNUM)
+#define INTCHW_INTC0_DMA0C4               (1<<INTCHW_INTC0_DMA0C4_BITNUM)
+#define INTCHW_INTC0_DMA0C3               (1<<INTCHW_INTC0_DMA0C3_BITNUM)
+#define INTCHW_INTC0_DMA0C2               (1<<INTCHW_INTC0_DMA0C2_BITNUM)
+#define INTCHW_INTC0_DMA0C1               (1<<INTCHW_INTC0_DMA0C1_BITNUM)
+#define INTCHW_INTC0_DMA0C0               (1<<INTCHW_INTC0_DMA0C0_BITNUM)
+/* INTC1 - interrupt controller 1 */
+#define INTCHW_INTC1_DDRVPMP_BITNUM       27    /* DDR and VPM PLL clock phase relationship interupt (Not for A0) */
+#define INTCHW_INTC1_DDRVPMT_BITNUM       26    /* DDR and VPM HW phase align timeout interrupt (Not for A0) */
+#define INTCHW_INTC1_DDRP_BITNUM          26    /* DDR and PLL clock phase relationship interupt (For A0 only)) */
+#define INTCHW_INTC1_RTC2_BITNUM          25    /* Real time clock tamper interrupt */
+#define INTCHW_INTC1_VDEC_BITNUM          24    /* Hantro Video Decoder interrupt */
+/* Bits 13-23 are non-secure versions of the corresponding secure bits in SINTC bits 0-10. */
+#define INTCHW_INTC1_SPUM_BITNUM          23    /* Secure process module interrupt */
+#define INTCHW_INTC1_RTC1_BITNUM          22    /* Real time clock one-shot interrupt */
+#define INTCHW_INTC1_RTC0_BITNUM          21    /* Real time clock periodic interrupt */
+#define INTCHW_INTC1_RNG_BITNUM           20    /* Random number generator interrupt */
+#define INTCHW_INTC1_FMPU_BITNUM          19    /* Flash memory parition unit interrupt */
+#define INTCHW_INTC1_VMPU_BITNUM          18    /* VRAM memory partition interrupt */
+#define INTCHW_INTC1_DMPU_BITNUM          17    /* DDR2 memory partition interrupt */
+#define INTCHW_INTC1_KEYC_BITNUM          16    /* Key pad controller interrupt */
+#define INTCHW_INTC1_TSC_BITNUM           15    /* Touch screen controller interrupt */
+#define INTCHW_INTC1_UART0_BITNUM         14    /* UART 0 */
+#define INTCHW_INTC1_WDOG_BITNUM          13    /* Watchdog timer interrupt */
+#define INTCHW_INTC1_UART1_BITNUM         12    /* UART 1 */
+#define INTCHW_INTC1_PMUIRQ_BITNUM        11    /* ARM performance monitor interrupt */
+#define INTCHW_INTC1_COMMRX_BITNUM        10    /* ARM DDC receive interrupt */
+#define INTCHW_INTC1_COMMTX_BITNUM         9    /* ARM DDC transmit interrupt */
+#define INTCHW_INTC1_FLASHC_BITNUM         8    /* Flash controller interrupt */
+#define INTCHW_INTC1_GPHY_BITNUM           7    /* Gigabit Phy interrupt */
+#define INTCHW_INTC1_SPIS_BITNUM           6    /* SPI slave interrupt */
+#define INTCHW_INTC1_I2CS_BITNUM           5    /* I2C slave interrupt */
+#define INTCHW_INTC1_I2CH_BITNUM           4    /* I2C host interrupt */
+#define INTCHW_INTC1_I2S1_BITNUM           3    /* I2S1 interrupt */
+#define INTCHW_INTC1_I2S0_BITNUM           2    /* I2S0 interrupt */
+#define INTCHW_INTC1_GPIO1_BITNUM          1    /* GPIO bit 64//32 combined interrupt */
+#define INTCHW_INTC1_GPIO0_BITNUM          0    /* GPIO bit 31//0 combined interrupt */
+#define INTCHW_INTC1_DDRVPMT              (1<<INTCHW_INTC1_DDRVPMT_BITNUM)
+#define INTCHW_INTC1_DDRVPMP              (1<<INTCHW_INTC1_DDRVPMP_BITNUM)
+#define INTCHW_INTC1_DDRP                 (1<<INTCHW_INTC1_DDRP_BITNUM)
+#define INTCHW_INTC1_VDEC                 (1<<INTCHW_INTC1_VDEC_BITNUM)
+#define INTCHW_INTC1_SPUM                 (1<<INTCHW_INTC1_SPUM_BITNUM)
+#define INTCHW_INTC1_RTC2                 (1<<INTCHW_INTC1_RTC2_BITNUM)
+#define INTCHW_INTC1_RTC1                 (1<<INTCHW_INTC1_RTC1_BITNUM)
+#define INTCHW_INTC1_RTC0                 (1<<INTCHW_INTC1_RTC0_BITNUM)
+#define INTCHW_INTC1_RNG                  (1<<INTCHW_INTC1_RNG_BITNUM)
+#define INTCHW_INTC1_FMPU                 (1<<INTCHW_INTC1_FMPU_BITNUM)
+#define INTCHW_INTC1_IMPU                 (1<<INTCHW_INTC1_IMPU_BITNUM)
+#define INTCHW_INTC1_DMPU                 (1<<INTCHW_INTC1_DMPU_BITNUM)
+#define INTCHW_INTC1_KEYC                 (1<<INTCHW_INTC1_KEYC_BITNUM)
+#define INTCHW_INTC1_TSC                  (1<<INTCHW_INTC1_TSC_BITNUM)
+#define INTCHW_INTC1_UART0                (1<<INTCHW_INTC1_UART0_BITNUM)
+#define INTCHW_INTC1_WDOG                 (1<<INTCHW_INTC1_WDOG_BITNUM)
+#define INTCHW_INTC1_UART1                (1<<INTCHW_INTC1_UART1_BITNUM)
+#define INTCHW_INTC1_PMUIRQ               (1<<INTCHW_INTC1_PMUIRQ_BITNUM)
+#define INTCHW_INTC1_COMMRX               (1<<INTCHW_INTC1_COMMRX_BITNUM)
+#define INTCHW_INTC1_COMMTX               (1<<INTCHW_INTC1_COMMTX_BITNUM)
+#define INTCHW_INTC1_FLASHC               (1<<INTCHW_INTC1_FLASHC_BITNUM)
+#define INTCHW_INTC1_GPHY                 (1<<INTCHW_INTC1_GPHY_BITNUM)
+#define INTCHW_INTC1_SPIS                 (1<<INTCHW_INTC1_SPIS_BITNUM)
+#define INTCHW_INTC1_I2CS                 (1<<INTCHW_INTC1_I2CS_BITNUM)
+#define INTCHW_INTC1_I2CH                 (1<<INTCHW_INTC1_I2CH_BITNUM)
+#define INTCHW_INTC1_I2S1                 (1<<INTCHW_INTC1_I2S1_BITNUM)
+#define INTCHW_INTC1_I2S0                 (1<<INTCHW_INTC1_I2S0_BITNUM)
+#define INTCHW_INTC1_GPIO1                (1<<INTCHW_INTC1_GPIO1_BITNUM)
+#define INTCHW_INTC1_GPIO0                (1<<INTCHW_INTC1_GPIO0_BITNUM)
+/* SINTC secure int controller */
+#define INTCHW_SINTC_RTC2_BITNUM          15    /* Real time clock tamper interrupt */
+#define INTCHW_SINTC_TIMER3_BITNUM        14    /* Secure timer3 interrupt */
+#define INTCHW_SINTC_TIMER2_BITNUM        13    /* Secure timer2 interrupt */
+#define INTCHW_SINTC_TIMER1_BITNUM        12    /* Secure timer1 interrupt */
+#define INTCHW_SINTC_TIMER0_BITNUM        11    /* Secure timer0 interrupt */
+#define INTCHW_SINTC_SPUM_BITNUM          10    /* Secure process module interrupt */
+#define INTCHW_SINTC_RTC1_BITNUM           9    /* Real time clock one-shot interrupt */
+#define INTCHW_SINTC_RTC0_BITNUM           8    /* Real time clock periodic interrupt */
+#define INTCHW_SINTC_RNG_BITNUM            7    /* Random number generator interrupt */
+#define INTCHW_SINTC_FMPU_BITNUM           6    /* Flash memory parition unit interrupt */
+#define INTCHW_SINTC_VMPU_BITNUM           5    /* VRAM memory partition interrupt */
+#define INTCHW_SINTC_DMPU_BITNUM           4    /* DDR2 memory partition interrupt */
+#define INTCHW_SINTC_KEYC_BITNUM           3    /* Key pad controller interrupt */
+#define INTCHW_SINTC_TSC_BITNUM            2    /* Touch screen controller interrupt */
+#define INTCHW_SINTC_UART0_BITNUM          1    /* UART0 interrupt */
+#define INTCHW_SINTC_WDOG_BITNUM           0    /* Watchdog timer interrupt */
+#define INTCHW_SINTC_TIMER3               (1<<INTCHW_SINTC_TIMER3_BITNUM)
+#define INTCHW_SINTC_TIMER2               (1<<INTCHW_SINTC_TIMER2_BITNUM)
+#define INTCHW_SINTC_TIMER1               (1<<INTCHW_SINTC_TIMER1_BITNUM)
+#define INTCHW_SINTC_TIMER0               (1<<INTCHW_SINTC_TIMER0_BITNUM)
+#define INTCHW_SINTC_SPUM                 (1<<INTCHW_SINTC_SPUM_BITNUM)
+#define INTCHW_SINTC_RTC2                 (1<<INTCHW_SINTC_RTC2_BITNUM)
+#define INTCHW_SINTC_RTC1                 (1<<INTCHW_SINTC_RTC1_BITNUM)
+#define INTCHW_SINTC_RTC0                 (1<<INTCHW_SINTC_RTC0_BITNUM)
+#define INTCHW_SINTC_RNG                  (1<<INTCHW_SINTC_RNG_BITNUM)
+#define INTCHW_SINTC_FMPU                 (1<<INTCHW_SINTC_FMPU_BITNUM)
+#define INTCHW_SINTC_IMPU                 (1<<INTCHW_SINTC_IMPU_BITNUM)
+#define INTCHW_SINTC_DMPU                 (1<<INTCHW_SINTC_DMPU_BITNUM)
+#define INTCHW_SINTC_KEYC                 (1<<INTCHW_SINTC_KEYC_BITNUM)
+#define INTCHW_SINTC_TSC                  (1<<INTCHW_SINTC_TSC_BITNUM)
+#define INTCHW_SINTC_UART0                (1<<INTCHW_SINTC_UART0_BITNUM)
+#define INTCHW_SINTC_WDOG                 (1<<INTCHW_SINTC_WDOG_BITNUM)
+/* PL192 Vectored Interrupt Controller (VIC) layout */
+#define INTCHW_IRQSTATUS      0x00      /* IRQ status register */
+#define INTCHW_FIQSTATUS      0x04      /* FIQ status register */
+#define INTCHW_RAWINTR        0x08      /* Raw Interrupt Status register */
+#define INTCHW_INTSELECT      0x0c      /* Interrupt Select Register */
+#define INTCHW_INTENABLE      0x10      /* Interrupt Enable Register */
+#define INTCHW_INTENCLEAR     0x14      /* Interrupt Enable Clear Register */
+#define INTCHW_SOFTINT        0x18      /* Soft Interrupt Register */
+#define INTCHW_SOFTINTCLEAR   0x1c      /* Soft Interrupt Clear Register */
+#define INTCHW_PROTECTION     0x20      /* Protection Enable Register */
+#define INTCHW_SWPRIOMASK     0x24      /* Software Priority Mask Register */
+#define INTCHW_PRIODAISY      0x28      /* Priority Daisy Chain Register */
+#define INTCHW_VECTADDR0      0x100     /* Vector Address Registers */
+#define INTCHW_VECTPRIO0      0x200     /* Vector Priority Registers 0-31 */
+#define INTCHW_ADDRESS        0xf00     /* Vector Address Register 0-31 */
+#define INTCHW_PID            0xfe0     /* Peripheral ID Register 0-3 */
+#define INTCHW_PCELLID        0xff0     /* PrimeCell ID Register 0-3 */
+/* Example Usage: intcHw_irq_enable(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
+/*                intcHw_irq_clear(INTCHW_INTC0, INTCHW_INTC0_TIMER0); */
+/*                uint32_t bits = intcHw_irq_status(INTCHW_INTC0); */
+/*                uint32_t bits = intcHw_irq_raw_status(INTCHW_INTC0); */
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+/* Clear one or more IRQ interrupts. */
+static inline void intcHw_irq_disable(void *basep, uint32_t mask)
+{
+        __REG32(basep + INTCHW_INTENCLEAR) = mask;
+}
+/* Enables one or more IRQ interrupts. */
+static inline void intcHw_irq_enable(void *basep, uint32_t mask)
+{
+        __REG32(basep + INTCHW_INTENABLE) = mask;
+}
+#endif /* _INTCHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
new file mode 100644
index 000000000000..86bb58d4f58c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_addr.h
@@ -0,0 +1,101 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    mm_addr.h
+*
+*  @brief   Memory Map address defintions
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+#ifndef _MM_ADDR_H
+#define _MM_ADDR_H
+/* ---- Include Files ---------------------------------------------------- */
+#if !defined(CSP_SIMULATION)
+#include <cfg_global.h>
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+/*  Memory Map address definitions */
+#define MM_ADDR_DDR                0x00000000
+#define MM_ADDR_IO_VPM_EXTMEM_RSVD 0x0F000000   /* 16 MB - Reserved external memory for VPM use */
+#define MM_ADDR_IO_FLASHC          0x20000000
+#define MM_ADDR_IO_BROM            0x30000000
+#define MM_ADDR_IO_ARAM            0x30100000   /* 64 KB - extra cycle latency - WS switch */
+#define MM_ADDR_IO_DMA0            0x30200000
+#define MM_ADDR_IO_DMA1            0x30300000
+#define MM_ADDR_IO_ESW             0x30400000
+#define MM_ADDR_IO_CLCD            0x30500000
+#define MM_ADDR_IO_PIF             0x30580000
+#define MM_ADDR_IO_APM             0x30600000
+#define MM_ADDR_IO_SPUM            0x30700000
+#define MM_ADDR_IO_VPM_PROG        0x30800000
+#define MM_ADDR_IO_VPM_DATA        0x30A00000
+#define MM_ADDR_IO_VRAM            0x40000000   /* 64 KB  - security block in front of it */
+#define MM_ADDR_IO_CHIPC           0x80000000
+#define MM_ADDR_IO_UMI             0x80001000
+#define MM_ADDR_IO_NAND            0x80001800
+#define MM_ADDR_IO_LEDM            0x80002000
+#define MM_ADDR_IO_PWM             0x80002040
+#define MM_ADDR_IO_VINTC           0x80003000
+#define MM_ADDR_IO_GPIO0           0x80004000
+#define MM_ADDR_IO_GPIO1           0x80004800
+#define MM_ADDR_IO_I2CS            0x80005000
+#define MM_ADDR_IO_SPIS            0x80006000
+#define MM_ADDR_IO_HPM             0x80007400
+#define MM_ADDR_IO_HPM_REMAP       0x80007800
+#define MM_ADDR_IO_TZPC            0x80008000
+#define MM_ADDR_IO_MPU             0x80009000
+#define MM_ADDR_IO_SPUMP           0x8000a000
+#define MM_ADDR_IO_PKA             0x8000b000
+#define MM_ADDR_IO_RNG             0x8000c000
+#define MM_ADDR_IO_KEYC            0x8000d000
+#define MM_ADDR_IO_BBL             0x8000e000
+#define MM_ADDR_IO_OTP             0x8000f000
+#define MM_ADDR_IO_I2S0            0x80010000
+#define MM_ADDR_IO_I2S1            0x80011000
+#define MM_ADDR_IO_UARTA           0x80012000
+#define MM_ADDR_IO_UARTB           0x80013000
+#define MM_ADDR_IO_I2CH            0x80014020
+#define MM_ADDR_IO_SPIH            0x80015000
+#define MM_ADDR_IO_TSC             0x80016000
+#define MM_ADDR_IO_TMR             0x80017000
+#define MM_ADDR_IO_WATCHDOG        0x80017800
+#define MM_ADDR_IO_ETM             0x80018000
+#define MM_ADDR_IO_DDRC            0x80019000
+#define MM_ADDR_IO_SINTC           0x80100000
+#define MM_ADDR_IO_INTC0           0x80200000
+#define MM_ADDR_IO_INTC1           0x80201000
+#define MM_ADDR_IO_GE              0x80300000
+#define MM_ADDR_IO_USB_CTLR0       0x80400000
+#define MM_ADDR_IO_USB_CTLR1       0x80410000
+#define MM_ADDR_IO_USB_PHY         0x80420000
+#define MM_ADDR_IO_SDIOH0          0x80500000
+#define MM_ADDR_IO_SDIOH1          0x80600000
+#define MM_ADDR_IO_VDEC            0x80700000
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /* _MM_ADDR_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/mm_io.h b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
new file mode 100644
index 000000000000..de92ec6a01aa
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/mm_io.h
@@ -0,0 +1,147 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    mm_io.h
+*
+*  @brief   Memory Map I/O definitions
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+#ifndef _MM_IO_H
+#define _MM_IO_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <mach/csp/mm_addr.h>
+#if !defined(CSP_SIMULATION)
+#include <cfg_global.h>
+#endif
+/* ---- Public Constants and Types --------------------------------------- */
+#if defined(CONFIG_MMU)
+/* This macro is referenced in <mach/io.h>
+ * Phys to Virtual 0xNyxxxxxx => 0xFNxxxxxx
+ * This macro is referenced in <asm/arch/io.h>
+ *
+ * Assume VPM address is the last x MB of memory.  For VPM, map to
+ * 0xf0000000 and up.
+ */
+#ifndef MM_IO_PHYS_TO_VIRT
+#ifdef __ASSEMBLY__
+#define MM_IO_PHYS_TO_VIRT(phys)       (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF))
+#else
+#define MM_IO_PHYS_TO_VIRT(phys)       (((phys) == MM_ADDR_IO_VPM_EXTMEM_RSVD) ? 0xF0000000 : \
+                        (0xF0000000 | (((phys) >> 4) & 0x0F000000) | ((phys) & 0xFFFFFF)))
+#endif
+#endif
+/* Virtual to Physical 0xFNxxxxxx => 0xN0xxxxxx */
+#ifndef MM_IO_VIRT_TO_PHYS
+#ifdef __ASSEMBLY__
+#define MM_IO_VIRT_TO_PHYS(virt)       ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF))
+#else
+#define MM_IO_VIRT_TO_PHYS(virt)       (((virt) == 0xF0000000) ? MM_ADDR_IO_VPM_EXTMEM_RSVD : \
+                        ((((virt) & 0x0F000000) << 4) | ((virt) & 0xFFFFFF)))
+#endif
+#endif
+#else
+#ifndef MM_IO_PHYS_TO_VIRT
+#define MM_IO_PHYS_TO_VIRT(phys)       (phys)
+#endif
+#ifndef MM_IO_VIRT_TO_PHYS
+#define MM_IO_VIRT_TO_PHYS(virt)       (virt)
+#endif
+#endif
+/* Registers in 0xExxxxxxx that should be moved to 0xFxxxxxxx */
+#define MM_IO_BASE_FLASHC              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_FLASHC)
+#define MM_IO_BASE_NAND                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_NAND)
+#define MM_IO_BASE_UMI                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UMI)
+#define MM_IO_START MM_ADDR_IO_FLASHC   /* Physical beginning of IO mapped memory */
+#define MM_IO_BASE  MM_IO_BASE_FLASHC   /* Virtual beginning of IO mapped memory */
+#define MM_IO_BASE_BROM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BROM)
+#define MM_IO_BASE_ARAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ARAM)
+#define MM_IO_BASE_DMA0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA0)
+#define MM_IO_BASE_DMA1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DMA1)
+#define MM_IO_BASE_ESW                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ESW)
+#define MM_IO_BASE_CLCD                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CLCD)
+#define MM_IO_BASE_PIF                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PIF)
+#define MM_IO_BASE_APM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_APM)
+#define MM_IO_BASE_SPUM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUM)
+#define MM_IO_BASE_VPM_PROG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_PROG)
+#define MM_IO_BASE_VPM_DATA            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_DATA)
+#define MM_IO_BASE_VRAM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VRAM)
+#define MM_IO_BASE_CHIPC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_CHIPC)
+#define MM_IO_BASE_DDRC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_DDRC)
+#define MM_IO_BASE_LEDM                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_LEDM)
+#define MM_IO_BASE_PWM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PWM)
+#define MM_IO_BASE_VINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VINTC)
+#define MM_IO_BASE_GPIO0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO0)
+#define MM_IO_BASE_GPIO1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GPIO1)
+#define MM_IO_BASE_TMR                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TMR)
+#define MM_IO_BASE_WATCHDOG            MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_WATCHDOG)
+#define MM_IO_BASE_ETM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_ETM)
+#define MM_IO_BASE_HPM                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM)
+#define MM_IO_BASE_HPM_REMAP           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_HPM_REMAP)
+#define MM_IO_BASE_TZPC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TZPC)
+#define MM_IO_BASE_MPU                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_MPU)
+#define MM_IO_BASE_SPUMP               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPUMP)
+#define MM_IO_BASE_PKA                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_PKA)
+#define MM_IO_BASE_RNG                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_RNG)
+#define MM_IO_BASE_KEYC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_KEYC)
+#define MM_IO_BASE_BBL                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_BBL)
+#define MM_IO_BASE_OTP                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_OTP)
+#define MM_IO_BASE_I2S0                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S0)
+#define MM_IO_BASE_I2S1                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2S1)
+#define MM_IO_BASE_UARTA               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTA)
+#define MM_IO_BASE_UARTB               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_UARTB)
+#define MM_IO_BASE_I2CH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CH)
+#define MM_IO_BASE_SPIH                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIH)
+#define MM_IO_BASE_TSC                 MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_TSC)
+#define MM_IO_BASE_I2CS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_I2CS)
+#define MM_IO_BASE_SPIS                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SPIS)
+#define MM_IO_BASE_SINTC               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SINTC)
+#define MM_IO_BASE_INTC0               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC0)
+#define MM_IO_BASE_INTC1               MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_INTC1)
+#define MM_IO_BASE_GE                  MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_GE)
+#define MM_IO_BASE_USB_CTLR0           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR0)
+#define MM_IO_BASE_USB_CTLR1           MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_CTLR1)
+#define MM_IO_BASE_USB_PHY             MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_USB_PHY)
+#define MM_IO_BASE_SDIOH0              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH0)
+#define MM_IO_BASE_SDIOH1              MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_SDIOH1)
+#define MM_IO_BASE_VDEC                MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VDEC)
+#define MM_IO_BASE_VPM_EXTMEM_RSVD     MM_IO_PHYS_TO_VIRT(MM_ADDR_IO_VPM_EXTMEM_RSVD)
+/* ---- Public Variable Externs ------------------------------------------ */
+/* ---- Public Function Prototypes --------------------------------------- */
+#endif /* _MM_IO_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
new file mode 100644
index 000000000000..d15f5f3ec2d8
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_def.h
@@ -0,0 +1,100 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    secHw_def.h
+*
+*  @brief   Definitions for configuring/testing secure blocks
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+#ifndef SECHW_DEF_H
+#define SECHW_DEF_H
+#include <mach/csp/mm_io.h>
+/* Bit mask for various secure device */
+#define secHw_BLK_MASK_CHIP_CONTROL     0x00000001
+#define secHw_BLK_MASK_KEY_SCAN         0x00000002
+#define secHw_BLK_MASK_TOUCH_SCREEN     0x00000004
+#define secHw_BLK_MASK_UART0            0x00000008
+#define secHw_BLK_MASK_UART1            0x00000010
+#define secHw_BLK_MASK_WATCHDOG         0x00000020
+#define secHw_BLK_MASK_SPUM             0x00000040
+#define secHw_BLK_MASK_DDR2             0x00000080
+#define secHw_BLK_MASK_EXT_MEM          0x00000100
+#define secHw_BLK_MASK_ESW              0x00000200
+#define secHw_BLK_MASK_SPU              0x00010000
+#define secHw_BLK_MASK_PKA              0x00020000
+#define secHw_BLK_MASK_RNG              0x00040000
+#define secHw_BLK_MASK_RTC              0x00080000
+#define secHw_BLK_MASK_OTP              0x00100000
+#define secHw_BLK_MASK_BOOT             0x00200000
+#define secHw_BLK_MASK_MPU              0x00400000
+#define secHw_BLK_MASK_TZCTRL           0x00800000
+#define secHw_BLK_MASK_INTR             0x01000000
+/* Trustzone register set */
+typedef struct {
+        volatile uint32_t status;       /* read only - reflects status of writes of 2 write registers */
+        volatile uint32_t setUnsecure;  /* write only. reads back as 0 */
+        volatile uint32_t setSecure;    /* write only. reads back as 0 */
+} secHw_TZREG_t;
+/* There are 2 register sets. The first is for the lower 16 bits, the 2nd */
+/* is for the higher 16 bits. */
+typedef enum {
+        secHw_IDX_LS = 0,
+        secHw_IDX_MS = 1,
+        secHw_IDX_NUM
+} secHw_IDX_e;
+typedef struct {
+        volatile secHw_TZREG_t reg[secHw_IDX_NUM];
+} secHw_REGS_t;
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a non-secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
+    );
+/****************************************************************************/
+/**
+*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
+*
+*/
+/****************************************************************************/
+static inline uint32_t secHw_getStatus(void);
+#include <mach/csp/secHw_inline.h>
+#endif /* SECHW_DEF_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
new file mode 100644
index 000000000000..9cd6a032ab71
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/secHw_inline.h
@@ -0,0 +1,79 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    secHw_inline.h
+*
+*  @brief   Definitions for configuring/testing secure blocks
+*
+*  @note
+*     None
+*/
+/****************************************************************************/
+#ifndef SECHW_INLINE_H
+#define SECHW_INLINE_H
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setSecure(uint32_t mask        /*  mask of type secHw_BLK_MASK_XXXXXX */
+    ) {
+        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        if (mask & 0x0000FFFF) {
+                regp->reg[secHw_IDX_LS].setSecure = mask & 0x0000FFFF;
+        }
+        if (mask & 0xFFFF0000) {
+                regp->reg[secHw_IDX_MS].setSecure = mask >> 16;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief  Configures a device as a non-secure device
+*
+*/
+/****************************************************************************/
+static inline void secHw_setUnsecure(uint32_t mask      /*  mask of type secHw_BLK_MASK_XXXXXX */
+    ) {
+        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        if (mask & 0x0000FFFF) {
+                regp->reg[secHw_IDX_LS].setUnsecure = mask & 0x0000FFFF;
+        }
+        if (mask & 0xFFFF0000) {
+                regp->reg[secHw_IDX_MS].setUnsecure = mask >> 16;
+        }
+}
+/****************************************************************************/
+/**
+*  @brief  Get the trustzone status for all components. 1 = non-secure, 0 = secure
+*
+*/
+/****************************************************************************/
+static inline uint32_t secHw_getStatus(void)
+{
+        secHw_REGS_t *regp = (secHw_REGS_t *) MM_IO_BASE_TZPC;
+        return (regp->reg[1].status << 16) + regp->reg[0].status;
+}
+#endif /* SECHW_INLINE_H */
diff --git a/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
new file mode 100644
index 000000000000..3080ac7239a1
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/csp/tmrHw_reg.h
@@ -0,0 +1,82 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*  @file    tmrHw_reg.h
+*
+*  @brief   Definitions for low level Timer registers
+*
+*/
+/****************************************************************************/
+#ifndef _TMRHW_REG_H
+#define _TMRHW_REG_H
+#include <mach/csp/mm_io.h>
+#include <mach/csp/hw_cfg.h>
+/* Base address */
+#define tmrHw_MODULE_BASE_ADDR          MM_IO_BASE_TMR
+/*
+This platform has four different timers running at different clock speed
+Timer one   (Timer ID 0) runs at  25 MHz
+Timer two   (Timer ID 1) runs at  25 MHz
+Timer three (Timer ID 2) runs at 150 MHz
+Timer four  (Timer ID 3) runs at 150 MHz
+*/
+#define tmrHw_LOW_FREQUENCY_MHZ         25      /* Always 25MHz from XTAL */
+#define tmrHw_LOW_FREQUENCY_HZ          25000000
+#if defined(CFG_GLOBAL_CHIP) && (CFG_GLOBAL_CHIP == FPGA11107)
+#define tmrHw_HIGH_FREQUENCY_MHZ        150     /* Always 150MHz for FPGA */
+#define tmrHw_HIGH_FREQUENCY_HZ         150000000
+#else
+#define tmrHw_HIGH_FREQUENCY_HZ         HW_CFG_BUS_CLK_HZ
+#define tmrHw_HIGH_FREQUENCY_MHZ        (HW_CFG_BUS_CLK_HZ / 1000000)
+#endif
+#define tmrHw_LOW_RESOLUTION_CLOCK      tmrHw_LOW_FREQUENCY_HZ
+#define tmrHw_HIGH_RESOLUTION_CLOCK     tmrHw_HIGH_FREQUENCY_HZ
+#define tmrHw_MAX_COUNT                 (0xFFFFFFFF)    /* maximum number of count a timer can count */
+#define tmrHw_TIMER_NUM_COUNT           (4)     /* Number of timer module supported */
+typedef struct {
+        uint32_t LoadValue;     /* Load value for timer */
+        uint32_t CurrentValue;  /* Current value for timer */
+        uint32_t Control;       /* Control register */
+        uint32_t InterruptClear;        /* Interrupt clear register */
+        uint32_t RawInterruptStatus;    /* Raw interrupt status */
+        uint32_t InterruptStatus;       /* Masked interrupt status */
+        uint32_t BackgroundLoad;        /* Background load value */
+        uint32_t padding;       /* Padding register */
+} tmrHw_REG_t;
+/* Control bot masks */
+#define tmrHw_CONTROL_TIMER_ENABLE            0x00000080
+#define tmrHw_CONTROL_PERIODIC                0x00000040
+#define tmrHw_CONTROL_INTERRUPT_ENABLE        0x00000020
+#define tmrHw_CONTROL_PRESCALE_MASK           0x0000000C
+#define tmrHw_CONTROL_PRESCALE_1              0x00000000
+#define tmrHw_CONTROL_PRESCALE_16             0x00000004
+#define tmrHw_CONTROL_PRESCALE_256            0x00000008
+#define tmrHw_CONTROL_32BIT                   0x00000002
+#define tmrHw_CONTROL_ONESHOT                 0x00000001
+#define tmrHw_CONTROL_FREE_RUNNING            0x00000000
+#define tmrHw_CONTROL_MODE_MASK               (tmrHw_CONTROL_PERIODIC | tmrHw_CONTROL_ONESHOT)
+#define pTmrHw ((volatile tmrHw_REG_t *)tmrHw_MODULE_BASE_ADDR)
+#endif /* _TMRHW_REG_H */
diff --git a/arch/arm/mach-bcmring/include/mach/dma.h b/arch/arm/mach-bcmring/include/mach/dma.h
new file mode 100644
index 000000000000..847980c85c88
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/dma.h
@@ -0,0 +1,826 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/****************************************************************************/
+/**
+*   @file   dma.h
+*
+*   @brief  API definitions for the linux DMA interface.
+*/
+/****************************************************************************/
+#if !defined(ASM_ARM_ARCH_BCMRING_DMA_H)
+#define ASM_ARM_ARCH_BCMRING_DMA_H
+/* ---- Include Files ---------------------------------------------------- */
+#include <linux/kernel.h>
+#include <linux/wait.h>
+#include <linux/semaphore.h>
+#include <csp/dmacHw.h>
+#include <mach/timer.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/vmalloc.h>
+#include <linux/pagemap.h>
+/* ---- Constants and Types ---------------------------------------------- */
+/* If DMA_DEBUG_TRACK_RESERVATION is set to a non-zero value, then the filename */
+/* and line number of the reservation request will be recorded in the channel table */
+#define DMA_DEBUG_TRACK_RESERVATION   1
+#define DMA_NUM_CONTROLLERS     2
+#define DMA_NUM_CHANNELS        8       /* per controller */
+typedef enum {
+        DMA_DEVICE_MEM_TO_MEM,  /* For memory to memory transfers */
+        DMA_DEVICE_I2S0_DEV_TO_MEM,
+        DMA_DEVICE_I2S0_MEM_TO_DEV,
+        DMA_DEVICE_I2S1_DEV_TO_MEM,
+        DMA_DEVICE_I2S1_MEM_TO_DEV,
+        DMA_DEVICE_APM_CODEC_A_DEV_TO_MEM,
+        DMA_DEVICE_APM_CODEC_A_MEM_TO_DEV,
+        DMA_DEVICE_APM_CODEC_B_DEV_TO_MEM,
+        DMA_DEVICE_APM_CODEC_B_MEM_TO_DEV,
+        DMA_DEVICE_APM_CODEC_C_DEV_TO_MEM,      /* Additional mic input for beam-forming */
+        DMA_DEVICE_APM_PCM0_DEV_TO_MEM,
+        DMA_DEVICE_APM_PCM0_MEM_TO_DEV,
+        DMA_DEVICE_APM_PCM1_DEV_TO_MEM,
+        DMA_DEVICE_APM_PCM1_MEM_TO_DEV,
+        DMA_DEVICE_SPUM_DEV_TO_MEM,
+        DMA_DEVICE_SPUM_MEM_TO_DEV,
+        DMA_DEVICE_SPIH_DEV_TO_MEM,
+        DMA_DEVICE_SPIH_MEM_TO_DEV,
+        DMA_DEVICE_UART_A_DEV_TO_MEM,
+        DMA_DEVICE_UART_A_MEM_TO_DEV,
+        DMA_DEVICE_UART_B_DEV_TO_MEM,
+        DMA_DEVICE_UART_B_MEM_TO_DEV,
+        DMA_DEVICE_PIF_MEM_TO_DEV,
+        DMA_DEVICE_PIF_DEV_TO_MEM,
+        DMA_DEVICE_ESW_DEV_TO_MEM,
+        DMA_DEVICE_ESW_MEM_TO_DEV,
+        DMA_DEVICE_VPM_MEM_TO_MEM,
+        DMA_DEVICE_CLCD_MEM_TO_MEM,
+        DMA_DEVICE_NAND_MEM_TO_MEM,
+        DMA_DEVICE_MEM_TO_VRAM,
+        DMA_DEVICE_VRAM_TO_MEM,
+        /* Add new entries before this line. */
+        DMA_NUM_DEVICE_ENTRIES,
+        DMA_DEVICE_NONE = 0xff, /* Special value to indicate that no device is currently assigned. */
+} DMA_Device_t;
+/****************************************************************************
+*
+*   The DMA_Handle_t is the primary object used by callers of the API.
+*
+*****************************************************************************/
+#define DMA_INVALID_HANDLE  ((DMA_Handle_t) -1)
+typedef int DMA_Handle_t;
+/****************************************************************************
+*
+*   The DMA_DescriptorRing_t contains a ring of descriptors which is used
+*   to point to regions of memory.
+*
+*****************************************************************************/
+typedef struct {
+        void *virtAddr;         /* Virtual Address of the descriptor ring */
+        dma_addr_t physAddr;    /* Physical address of the descriptor ring */
+        int descriptorsAllocated;       /* Number of descriptors allocated in the descriptor ring */
+        size_t bytesAllocated;  /* Number of bytes allocated in the descriptor ring */
+} DMA_DescriptorRing_t;
+/****************************************************************************
+*
+*   The DMA_MemType_t and DMA_MemMap_t are helper structures used to setup
+*   DMA chains from a variety of memory sources.
+*
+*****************************************************************************/
+#define DMA_MEM_MAP_MIN_SIZE    4096    /* Pages less than this size are better */
+                                        /* off not being DMA'd. */
+typedef enum {
+        DMA_MEM_TYPE_NONE,      /* Not a valid setting */
+        DMA_MEM_TYPE_VMALLOC,   /* Memory came from vmalloc call */
+        DMA_MEM_TYPE_KMALLOC,   /* Memory came from kmalloc call */
+        DMA_MEM_TYPE_DMA,       /* Memory came from dma_alloc_xxx call */
+        DMA_MEM_TYPE_USER,      /* Memory came from user space. */
+} DMA_MemType_t;
+/* A segment represents a physically and virtually contiguous chunk of memory. */
+/* i.e. each segment can be DMA'd */
+/* A user of the DMA code will add memory regions. Each region may need to be */
+/* represented by one or more segments. */
+typedef struct {
+        void *virtAddr;         /* Virtual address used for this segment */
+        dma_addr_t physAddr;    /* Physical address this segment maps to */
+        size_t numBytes;        /* Size of the segment, in bytes */
+} DMA_Segment_t;
+/* A region represents a virtually contiguous chunk of memory, which may be */
+/* made up of multiple segments. */
+typedef struct {
+        DMA_MemType_t memType;
+        void *virtAddr;
+        size_t numBytes;
+        /* Each region (virtually contiguous) consists of one or more segments. Each */
+        /* segment is virtually and physically contiguous. */
+        int numSegmentsUsed;
+        int numSegmentsAllocated;
+        DMA_Segment_t *segment;
+        /* When a region corresponds to user memory, we need to lock all of the pages */
+        /* down before we can figure out the physical addresses. The lockedPage array contains */
+        /* the pages that were locked, and which subsequently need to be unlocked once the */
+        /* memory is unmapped. */
+        unsigned numLockedPages;
+        struct page **lockedPages;
+} DMA_Region_t;
+typedef struct {
+        int inUse;              /* Is this mapping currently being used? */
+        struct semaphore lock;  /* Acquired when using this structure */
+        enum dma_data_direction dir;    /* Direction this transfer is intended for */
+        /* In the event that we're mapping user memory, we need to know which task */
+        /* the memory is for, so that we can obtain the correct mm locks. */
+        struct task_struct *userTask;
+        int numRegionsUsed;
+        int numRegionsAllocated;
+        DMA_Region_t *region;
+} DMA_MemMap_t;
+/****************************************************************************
+*
+*   The DMA_DeviceAttribute_t contains information which describes a
+*   particular DMA device (or peripheral).
+*
+*   It is anticipated that the arrary of DMA_DeviceAttribute_t's will be
+*   statically initialized.
+*
+*****************************************************************************/
+/* The device handler is called whenever a DMA operation completes. The reaon */
+/* for it to be called will be a bitmask with one or more of the following bits */
+/* set. */
+#define DMA_HANDLER_REASON_BLOCK_COMPLETE       dmacHw_INTERRUPT_STATUS_BLOCK
+#define DMA_HANDLER_REASON_TRANSFER_COMPLETE    dmacHw_INTERRUPT_STATUS_TRANS
+#define DMA_HANDLER_REASON_ERROR                dmacHw_INTERRUPT_STATUS_ERROR
+typedef void (*DMA_DeviceHandler_t) (DMA_Device_t dev, int reason,
+                                     void *userData);
+#define DMA_DEVICE_FLAG_ON_DMA0             0x00000001
+#define DMA_DEVICE_FLAG_ON_DMA1             0x00000002
+#define DMA_DEVICE_FLAG_PORT_PER_DMAC       0x00000004  /* If set, it means that the port used on DMAC0 is different from the port used on DMAC1 */
+#define DMA_DEVICE_FLAG_ALLOC_DMA1_FIRST    0x00000008  /* If set, allocate from DMA1 before allocating from DMA0 */
+#define DMA_DEVICE_FLAG_IS_DEDICATED        0x00000100
+#define DMA_DEVICE_FLAG_NO_ISR              0x00000200
+#define DMA_DEVICE_FLAG_ALLOW_LARGE_FIFO    0x00000400
+#define DMA_DEVICE_FLAG_IN_USE              0x00000800  /* If set, device is in use on a channel */
+/* Note: Some DMA devices can be used from multiple DMA Controllers. The bitmask is used to */
+/*       determine which DMA controllers a given device can be used from, and the interface */
+/*       array determeines the actual interface number to use for a given controller. */
+typedef struct {
+        uint32_t flags;         /* Bitmask of DMA_DEVICE_FLAG_xxx constants */
+        uint8_t dedicatedController;    /* Controller number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
+        uint8_t dedicatedChannel;       /* Channel number to use if DMA_DEVICE_FLAG_IS_DEDICATED is set. */
+        const char *name;       /* Will show up in the /proc entry */
+        uint32_t dmacPort[DMA_NUM_CONTROLLERS]; /* Specifies the port number when DMA_DEVICE_FLAG_PORT_PER_DMAC flag is set */
+        dmacHw_CONFIG_t config; /* Configuration to use when DMA'ing using this device */
+        void *userData;         /* Passed to the devHandler */
+        DMA_DeviceHandler_t devHandler; /* Called when DMA operations finish. */
+        timer_tick_count_t transferStartTime;   /* Time the current transfer was started */
+        /* The following statistical information will be collected and presented in a proc entry. */
+        /* Note: With a contiuous bandwidth of 1 Gb/sec, it would take 584 years to overflow */
+        /*       a 64 bit counter. */
+        uint64_t numTransfers;  /* Number of DMA transfers performed */
+        uint64_t transferTicks; /* Total time spent doing DMA transfers (measured in timer_tick_count_t's) */
+        uint64_t transferBytes; /* Total bytes transferred */
+        uint32_t timesBlocked;  /* Number of times a channel was unavailable */
+        uint32_t numBytes;      /* Last transfer size */
+        /* It's not possible to free memory which is allocated for the descriptors from within */
+        /* the ISR. So make the presumption that a given device will tend to use the */
+        /* same sized buffers over and over again, and we keep them around. */
+        DMA_DescriptorRing_t ring;      /* Ring of descriptors allocated for this device */
+        /* We stash away some of the information from the previous transfer. If back-to-back */
+        /* transfers are performed from the same buffer, then we don't have to keep re-initializing */
+        /* the descriptor buffers. */
+        uint32_t prevNumBytes;
+        dma_addr_t prevSrcData;
+        dma_addr_t prevDstData;
+} DMA_DeviceAttribute_t;
+/****************************************************************************
+*
+*   DMA_Channel_t, DMA_Controller_t, and DMA_State_t are really internal
+*   data structures and don't belong in this header file, but are included
+*   merely for discussion.
+*
+*   By the time this is implemented, these structures will be moved out into
+*   the appropriate C source file instead.
+*
+*****************************************************************************/
+/****************************************************************************
+*
+*   The DMA_Channel_t contains state information about each DMA channel. Some
+*   of the channels are dedicated. Non-dedicated channels are shared
+*   amongst the other devices.
+*
+*****************************************************************************/
+#define DMA_CHANNEL_FLAG_IN_USE         0x00000001
+#define DMA_CHANNEL_FLAG_IS_DEDICATED   0x00000002
+#define DMA_CHANNEL_FLAG_NO_ISR         0x00000004
+#define DMA_CHANNEL_FLAG_LARGE_FIFO     0x00000008
+typedef struct {
+        uint32_t flags;         /* bitmask of DMA_CHANNEL_FLAG_xxx constants */
+        DMA_Device_t devType;   /* Device this channel is currently reserved for */
+        DMA_Device_t lastDevType;       /* Device type that used this previously */
+        char name[20];          /* Name passed onto request_irq */
+#if (DMA_DEBUG_TRACK_RESERVATION)
+        const char *fileName;   /* Place where channel reservation took place */
+        int lineNum;            /* Place where channel reservation took place */
+#endif
+        dmacHw_HANDLE_t dmacHwHandle;   /* low level channel handle. */
+} DMA_Channel_t;
+/****************************************************************************
+*
+*   The DMA_Controller_t contains state information about each DMA controller.
+*
+*   The freeChannelQ is stored in the controller data structure rather than
+*   the channel data structure since several of the devices are accessible
+*   from multiple controllers, and there is no way to know which controller
+*   will become available first.
+*
+*****************************************************************************/
+typedef struct {
+        DMA_Channel_t channel[DMA_NUM_CHANNELS];
+} DMA_Controller_t;
+/****************************************************************************
+*
+*   The DMA_Global_t contains all of the global state information used by
+*   the DMA code.
+*
+*   Callers which need to allocate a shared channel will be queued up
+*   on the freeChannelQ until a channel becomes available.
+*
+*****************************************************************************/
+typedef struct {
+        struct semaphore lock;  /* acquired when manipulating table entries */
+        wait_queue_head_t freeChannelQ;
+        DMA_Controller_t controller[DMA_NUM_CONTROLLERS];
+} DMA_Global_t;
+/* ---- Variable Externs ------------------------------------------------- */
+extern DMA_DeviceAttribute_t DMA_gDeviceAttribute[DMA_NUM_DEVICE_ENTRIES];
+/* ---- Function Prototypes ---------------------------------------------- */
+#if defined(__KERNEL__)
+/****************************************************************************/
+/**
+*   Initializes the DMA module.
+*
+*   @return
+*       0       - Success
+*       < 0     - Error
+*/
+/****************************************************************************/
+int dma_init(void);
+#if (DMA_DEBUG_TRACK_RESERVATION)
+DMA_Handle_t dma_request_channel_dbg(DMA_Device_t dev, const char *fileName,
+                                     int lineNum);
+#define dma_request_channel(dev)  dma_request_channel_dbg(dev, __FILE__, __LINE__)
+#else
+/****************************************************************************/
+/**
+*   Reserves a channel for use with @a dev. If the device is setup to use
+*   a shared channel, then this function will block until a free channel
+*   becomes available.
+*
+*   @return
+*       >= 0    - A valid DMA Handle.
+*       -EBUSY  - Device is currently being used.
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+DMA_Handle_t dma_request_channel(DMA_Device_t dev       /* Device to use with the allocated channel. */
+    );
+#endif
+/****************************************************************************/
+/**
+*   Frees a previously allocated DMA Handle.
+*
+*   @return
+*        0      - DMA Handle was released successfully.
+*       -EINVAL - Invalid DMA handle
+*/
+/****************************************************************************/
+int dma_free_channel(DMA_Handle_t channel       /* DMA handle. */
+    );
+/****************************************************************************/
+/**
+*   Determines if a given device has been configured as using a shared
+*   channel.
+*
+*   @return boolean
+*       0           Device uses a dedicated channel
+*       non-zero    Device uses a shared channel
+*/
+/****************************************************************************/
+int dma_device_is_channel_shared(DMA_Device_t dev       /* Device to check. */
+    );
+/****************************************************************************/
+/**
+*   Allocates memory to hold a descriptor ring. The descriptor ring then
+*   needs to be populated by making one or more calls to
+*   dna_add_descriptors.
+*
+*   The returned descriptor ring will be automatically initialized.
+*
+*   @return
+*       0           Descriptor ring was allocated successfully
+*       -ENOMEM     Unable to allocate memory for the desired number of descriptors.
+*/
+/****************************************************************************/
+int dma_alloc_descriptor_ring(DMA_DescriptorRing_t *ring,       /* Descriptor ring to populate */
+                              int numDescriptors        /* Number of descriptors that need to be allocated. */
+    );
+/****************************************************************************/
+/**
+*   Releases the memory which was previously allocated for a descriptor ring.
+*/
+/****************************************************************************/
+void dma_free_descriptor_ring(DMA_DescriptorRing_t *ring        /* Descriptor to release */
+    );
+/****************************************************************************/
+/**
+*   Initializes a descriptor ring, so that descriptors can be added to it.
+*   Once a descriptor ring has been allocated, it may be reinitialized for
+*   use with additional/different regions of memory.
+*
+*   Note that if 7 descriptors are allocated, it's perfectly acceptable to
+*   initialize the ring with a smaller number of descriptors. The amount
+*   of memory allocated for the descriptor ring will not be reduced, and
+*   the descriptor ring may be reinitialized later
+*
+*   @return
+*       0           Descriptor ring was initialized successfully
+*       -ENOMEM     The descriptor which was passed in has insufficient space
+*                   to hold the desired number of descriptors.
+*/
+/****************************************************************************/
+int dma_init_descriptor_ring(DMA_DescriptorRing_t *ring,        /* Descriptor ring to initialize */
+                             int numDescriptors /* Number of descriptors to initialize. */
+    );
+/****************************************************************************/
+/**
+*   Determines the number of descriptors which would be required for a
+*   transfer of the indicated memory region.
+*
+*   This function also needs to know which DMA device this transfer will
+*   be destined for, so that the appropriate DMA configuration can be retrieved.
+*   DMA parameters such as transfer width, and whether this is a memory-to-memory
+*   or memory-to-peripheral, etc can all affect the actual number of descriptors
+*   required.
+*
+*   @return
+*       > 0     Returns the number of descriptors required for the indicated transfer
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_calculate_descriptor_count(DMA_Device_t device, /* DMA Device that this will be associated with */
+                                   dma_addr_t srcData,  /* Place to get data to write to device */
+                                   dma_addr_t dstData,  /* Pointer to device data address */
+                                   size_t numBytes      /* Number of bytes to transfer to the device */
+    );
+/****************************************************************************/
+/**
+*   Adds a region of memory to the descriptor ring. Note that it may take
+*   multiple descriptors for each region of memory. It is the callers
+*   responsibility to allocate a sufficiently large descriptor ring.
+*
+*   @return
+*       0       Descriptors were added successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_add_descriptors(DMA_DescriptorRing_t *ring,     /* Descriptor ring to add descriptors to */
+                        DMA_Device_t device,    /* DMA Device that descriptors are for */
+                        dma_addr_t srcData,     /* Place to get data (memory or device) */
+                        dma_addr_t dstData,     /* Place to put data (memory or device) */
+                        size_t numBytes /* Number of bytes to transfer to the device */
+    );
+/****************************************************************************/
+/**
+*   Sets the descriptor ring associated with a device.
+*
+*   Once set, the descriptor ring will be associated with the device, even
+*   across channel request/free calls. Passing in a NULL descriptor ring
+*   will release any descriptor ring currently associated with the device.
+*
+*   Note: If you call dma_transfer, or one of the other dma_alloc_ functions
+*         the descriptor ring may be released and reallocated.
+*
+*   Note: This function will release the descriptor memory for any current
+*         descriptor ring associated with this device.
+*/
+/****************************************************************************/
+int dma_set_device_descriptor_ring(DMA_Device_t device, /* Device to update the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Descriptor ring to add descriptors to */
+    );
+/****************************************************************************/
+/**
+*   Retrieves the descriptor ring associated with a device.
+*/
+/****************************************************************************/
+int dma_get_device_descriptor_ring(DMA_Device_t device, /* Device to retrieve the descriptor ring for. */
+                                   DMA_DescriptorRing_t *ring   /* Place to store retrieved ring */
+    );
+/****************************************************************************/
+/**
+*   Allocates buffers for the descriptors. This is normally done automatically
+*   but needs to be done explicitly when initiating a dma from interrupt
+*   context.
+*
+*   @return
+*       0       Descriptors were allocated successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_alloc_descriptors(DMA_Handle_t handle,  /* DMA Handle */
+                          dmacHw_TRANSFER_TYPE_e transferType,  /* Type of transfer being performed */
+                          dma_addr_t srcData,   /* Place to get data to write to device */
+                          dma_addr_t dstData,   /* Pointer to device data address */
+                          size_t numBytes       /* Number of bytes to transfer to the device */
+    );
+/****************************************************************************/
+/**
+*   Allocates and sets up descriptors for a double buffered circular buffer.
+*
+*   This is primarily intended to be used for things like the ingress samples
+*   from a microphone.
+*
+*   @return
+*       > 0     Number of descriptors actually allocated.
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*       -ENOMEM Memory exhausted
+*/
+/****************************************************************************/
+int dma_alloc_double_dst_descriptors(DMA_Handle_t handle,       /* DMA Handle */
+                                     dma_addr_t srcData,        /* Physical address of source data */
+                                     dma_addr_t dstData1,       /* Physical address of first destination buffer */
+                                     dma_addr_t dstData2,       /* Physical address of second destination buffer */
+                                     size_t numBytes    /* Number of bytes in each destination buffer */
+    );
+/****************************************************************************/
+/**
+*   Initializes a DMA_MemMap_t data structure
+*/
+/****************************************************************************/
+int dma_init_mem_map(DMA_MemMap_t *memMap       /* Stores state information about the map */
+    );
+/****************************************************************************/
+/**
+*   Releases any memory currently being held by a memory mapping structure.
+*/
+/****************************************************************************/
+int dma_term_mem_map(DMA_MemMap_t *memMap       /* Stores state information about the map */
+    );
+/****************************************************************************/
+/**
+*   Looks at a memory address and categorizes it.
+*
+*   @return One of the values from the DMA_MemType_t enumeration.
+*/
+/****************************************************************************/
+DMA_MemType_t dma_mem_type(void *addr);
+/****************************************************************************/
+/**
+*   Sets the process (aka userTask) associated with a mem map. This is
+*   required if user-mode segments will be added to the mapping.
+*/
+/****************************************************************************/
+static inline void dma_mem_map_set_user_task(DMA_MemMap_t *memMap,
+                                             struct task_struct *task)
+{
+        memMap->userTask = task;
+}
+/****************************************************************************/
+/**
+*   Looks at a memory address and determines if we support DMA'ing to/from
+*   that type of memory.
+*
+*   @return boolean -
+*               return value != 0 means dma supported
+*               return value == 0 means dma not supported
+*/
+/****************************************************************************/
+int dma_mem_supports_dma(void *addr);
+/****************************************************************************/
+/**
+*   Initializes a memory map for use. Since this function acquires a
+*   sempaphore within the memory map, it is VERY important that dma_unmap
+*   be called when you're finished using the map.
+*/
+/****************************************************************************/
+int dma_map_start(DMA_MemMap_t *memMap, /* Stores state information about the map */
+                  enum dma_data_direction dir   /* Direction that the mapping will be going */
+    );
+/****************************************************************************/
+/**
+*   Adds a segment of memory to a memory map.
+*
+*   @return     0 on success, error code otherwise.
+*/
+/****************************************************************************/
+int dma_map_add_region(DMA_MemMap_t *memMap,    /* Stores state information about the map */
+                       void *mem,       /* Virtual address that we want to get a map of */
+                       size_t numBytes  /* Number of bytes being mapped */
+    );
+/****************************************************************************/
+/**
+*   Creates a descriptor ring from a memory mapping.
+*
+*   @return 0 on sucess, error code otherwise.
+*/
+/****************************************************************************/
+int dma_map_create_descriptor_ring(DMA_Device_t dev,    /* DMA device (where the ring is stored) */
+                                   DMA_MemMap_t *memMap,        /* Memory map that will be used */
+                                   dma_addr_t devPhysAddr       /* Physical address of device */
+    );
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+int dma_map_mem(DMA_MemMap_t *memMap,   /* Stores state information about the map */
+                void *addr,     /* Virtual address that we want to get a map of */
+                size_t count,   /* Number of bytes being mapped */
+                enum dma_data_direction dir     /* Direction that the mapping will be going */
+    );
+/****************************************************************************/
+/**
+*   Maps in a memory region such that it can be used for performing a DMA.
+*
+*   @return
+*/
+/****************************************************************************/
+int dma_unmap(DMA_MemMap_t *memMap,     /* Stores state information about the map */
+              int dirtied       /* non-zero if any of the pages were modified */
+    );
+/****************************************************************************/
+/**
+*   Initiates a transfer when the descriptors have already been setup.
+*
+*   This is a special case, and normally, the dma_transfer_xxx functions should
+*   be used.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+int dma_start_transfer(DMA_Handle_t handle);
+/****************************************************************************/
+/**
+*   Stops a previously started DMA transfer.
+*
+*   @return
+*       0       Transfer was stopped successfully
+*       -ENODEV Invalid handle
+*/
+/****************************************************************************/
+int dma_stop_transfer(DMA_Handle_t handle);
+/****************************************************************************/
+/**
+*   Waits for a DMA to complete by polling. This function is only intended
+*   to be used for testing. Interrupts should be used for most DMA operations.
+*/
+/****************************************************************************/
+int dma_wait_transfer_done(DMA_Handle_t handle);
+/****************************************************************************/
+/**
+*   Initiates a DMA transfer
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*/
+/****************************************************************************/
+int dma_transfer(DMA_Handle_t handle,   /* DMA Handle */
+                 dmacHw_TRANSFER_TYPE_e transferType,   /* Type of transfer being performed */
+                 dma_addr_t srcData,    /* Place to get data to write to device */
+                 dma_addr_t dstData,    /* Pointer to device data address */
+                 size_t numBytes        /* Number of bytes to transfer to the device */
+    );
+/****************************************************************************/
+/**
+*   Initiates a transfer from memory to a device.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _DEV_TO_MEM and not _MEM_TO_DEV)
+*/
+/****************************************************************************/
+static inline int dma_transfer_to_device(DMA_Handle_t handle,   /* DMA Handle */
+                                         dma_addr_t srcData,    /* Place to get data to write to device (physical address) */
+                                         dma_addr_t dstData,    /* Pointer to device data address (physical address) */
+                                         size_t numBytes        /* Number of bytes to transfer to the device */
+    ) {
+        return dma_transfer(handle,
+                            dmacHw_TRANSFER_TYPE_MEM_TO_PERIPHERAL,
+                            srcData, dstData, numBytes);
+}
+/****************************************************************************/
+/**
+*   Initiates a transfer from a device to memory.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device is _MEM_TO_DEV and not _DEV_TO_MEM)
+*/
+/****************************************************************************/
+static inline int dma_transfer_from_device(DMA_Handle_t handle, /* DMA Handle */
+                                           dma_addr_t srcData,  /* Pointer to the device data address (physical address) */
+                                           dma_addr_t dstData,  /* Place to store data retrieved from the device (physical address) */
+                                           size_t numBytes      /* Number of bytes to retrieve from the device */
+    ) {
+        return dma_transfer(handle,
+                            dmacHw_TRANSFER_TYPE_PERIPHERAL_TO_MEM,
+                            srcData, dstData, numBytes);
+}
+/****************************************************************************/
+/**
+*   Initiates a memory to memory transfer.
+*
+*   @return
+*       0       Transfer was started successfully
+*       -EINVAL Invalid device type for this kind of transfer
+*               (i.e. the device wasn't DMA_DEVICE_MEM_TO_MEM)
+*/
+/****************************************************************************/
+static inline int dma_transfer_mem_to_mem(DMA_Handle_t handle,  /* DMA Handle */
+                                          dma_addr_t srcData,   /* Place to transfer data from (physical address) */
+                                          dma_addr_t dstData,   /* Place to transfer data to (physical address) */
+                                          size_t numBytes       /* Number of bytes to transfer */
+    ) {
+        return dma_transfer(handle,
+                            dmacHw_TRANSFER_TYPE_MEM_TO_MEM,
+                            srcData, dstData, numBytes);
+}
+/****************************************************************************/
+/**
+*   Set the callback function which will be called when a transfer completes.
+*   If a NULL callback function is set, then no callback will occur.
+*
+*   @note   @a devHandler will be called from IRQ context.
+*
+*   @return
+*       0       - Success
+*       -ENODEV - Device handed in is invalid.
+*/
+/****************************************************************************/
+int dma_set_device_handler(DMA_Device_t dev,    /* Device to set the callback for. */
+                           DMA_DeviceHandler_t devHandler,      /* Function to call when the DMA completes */
+                           void *userData       /* Pointer which will be passed to devHandler. */
+    );
+#endif
+#endif /* ASM_ARM_ARCH_BCMRING_DMA_H */
diff --git a/arch/arm/mach-bcmring/include/mach/entry-macro.S b/arch/arm/mach-bcmring/include/mach/entry-macro.S
new file mode 100644
index 000000000000..7d393ca010ac
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/entry-macro.S
@@ -0,0 +1,86 @@
+/*****************************************************************************
+* Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/*
+ *
+ * Low-level IRQ helper macros for BCMRing-based platforms
+ *
+ */
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+#include <mach/csp/mm_io.h>
+                .macro  disable_fiq
+                .endm
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =(MM_IO_BASE_INTC0)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #IRQ_INTC0_START
+                cmp     \irqstat, #0
+                bne     1001f
+                ldr     \base, =(MM_IO_BASE_INTC1)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #IRQ_INTC1_START
+                cmp     \irqstat, #0
+                bne     1001f
+                ldr     \base, =(MM_IO_BASE_SINTC)
+                ldr     \irqstat, [\base, #0]           @ get status
+                ldr     \irqnr, [\base, #0x10]          @ mask with enable register
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #0xffffffff             @ code meaning no interrupt bits set
+                cmp     \irqstat, #0
+                beq     1002f
+                mov     \irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
+1001:
+                movs    \tmp, \irqstat, lsl #16
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+                movs    \tmp, \irqstat, lsl #8
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #8
+                movs    \tmp, \irqstat, lsl #4
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #4
+                movs    \tmp, \irqstat, lsl #2
+                movne   \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #2
+                movs    \tmp, \irqstat, lsl #1
+                addeq   \irqnr, \irqnr, #1
+                orrs    \base, \base, #1
+1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
+                .endm
+                .macro  get_irqnr_preamble, base, tmp
+                .endm
+                .macro  arch_ret_to_user, tmp1, tmp2
+                .endm
+                .macro  irq_prio_table
+                .endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
new file mode 100644
index 000000000000..447eb340c611
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -0,0 +1,60 @@
+/*
+ *
+ *  This file contains the hardware definitions of the BCMRing.
+ *
+ *  Copyright (C) 1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+#include <asm/sizes.h>
+#include <mach/memory.h>
+#include <cfg_global.h>
+#include <mach/csp/mm_io.h>
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+#define RAM_START               PHYS_OFFSET
+#define RAM_SIZE                (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
+#define RAM_BASE                PAGE_OFFSET
+#define pcibios_assign_all_busses()     1
+/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
+/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
+#if defined(__KERNEL__)
+#define HW_DECLARE_SPINLOCK(name)  DEFINE_SPINLOCK(bcmring_##name##_reg_lock);
+#define HW_EXTERN_SPINLOCK(name)   extern spinlock_t bcmring_##name##_reg_lock;
+#define HW_IRQ_SAVE(name, val)     spin_lock_irqsave(&bcmring_##name##_reg_lock, (val))
+#define HW_IRQ_RESTORE(name, val)  spin_unlock_irqrestore(&bcmring_##name##_reg_lock, (val))
+#else
+#define HW_DECLARE_SPINLOCK(name)
+#define HW_EXTERN_SPINLOCK(name)
+#define HW_IRQ_SAVE(name, val)     {(void)(name); (void)(val); }
+#define HW_IRQ_RESTORE(name, val)  {(void)(name); (void)(val); }
+#endif
+#ifndef HW_IO_PHYS_TO_VIRT
+#define HW_IO_PHYS_TO_VIRT MM_IO_PHYS_TO_VIRT
+#endif
+#define HW_IO_VIRT_TO_PHYS MM_IO_VIRT_TO_PHYS
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/io.h b/arch/arm/mach-bcmring/include/mach/io.h
new file mode 100644
index 000000000000..4db0eff90357
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/io.h
@@ -0,0 +1,56 @@
+/*
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#include <mach/hardware.h>
+#define IO_SPACE_LIMIT 0xffffffff
+#define __io(a)         ((void __iomem *)HW_IO_PHYS_TO_VIRT(a))
+/* Do not enable mem_pci for a big endian arm architecture or unexpected byteswaps will */
+/* happen in readw/writew etc. */
+#define readb(c)        __raw_readb(c)
+#define readw(c)        __raw_readw(c)
+#define readl(c)        __raw_readl(c)
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+#define readsb(p, d, l)   __raw_readsb(p, d, l)
+#define readsw(p, d, l)   __raw_readsw(p, d, l)
+#define readsl(p, d, l)   __raw_readsl(p, d, l)
+#define writeb(v, c)     __raw_writeb(v, c)
+#define writew(v, c)     __raw_writew(v, c)
+#define writel(v, c)     __raw_writel(v, c)
+#define writesb(p, d, l)  __raw_writesb(p, d, l)
+#define writesw(p, d, l)  __raw_writesw(p, d, l)
+#define writesl(p, d, l)  __raw_writesl(p, d, l)
+#define memset_io(c, v, l)    _memset_io((c), (v), (l))
+#define memcpy_fromio(a, c, l)    _memcpy_fromio((a), (c), (l))
+#define memcpy_toio(c, a, l)  _memcpy_toio((c), (a), (l))
+#define eth_io_copy_and_sum(s, c, l, b) eth_copy_and_sum((s), (c), (l), (b))
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/irqs.h b/arch/arm/mach-bcmring/include/mach/irqs.h
new file mode 100644
index 000000000000..b279b825d4a7
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/irqs.h
@@ -0,0 +1,132 @@
+/*
+ *  Copyright (C) 2007 Broadcom
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#if !defined(ARCH_BCMRING_IRQS_H)
+#define ARCH_BCMRING_IRQS_H
+/* INTC0 - interrupt controller 0 */
+#define IRQ_INTC0_START     0
+#define IRQ_DMA0C0          0   /* DMA0 channel 0 interrupt */
+#define IRQ_DMA0C1          1   /* DMA0 channel 1 interrupt */
+#define IRQ_DMA0C2          2   /* DMA0 channel 2 interrupt */
+#define IRQ_DMA0C3          3   /* DMA0 channel 3 interrupt */
+#define IRQ_DMA0C4          4   /* DMA0 channel 4 interrupt */
+#define IRQ_DMA0C5          5   /* DMA0 channel 5 interrupt */
+#define IRQ_DMA0C6          6   /* DMA0 channel 6 interrupt */
+#define IRQ_DMA0C7          7   /* DMA0 channel 7 interrupt */
+#define IRQ_DMA1C0          8   /* DMA1 channel 0 interrupt */
+#define IRQ_DMA1C1          9   /* DMA1 channel 1 interrupt */
+#define IRQ_DMA1C2         10   /* DMA1 channel 2 interrupt */
+#define IRQ_DMA1C3         11   /* DMA1 channel 3 interrupt */
+#define IRQ_DMA1C4         12   /* DMA1 channel 4 interrupt */
+#define IRQ_DMA1C5         13   /* DMA1 channel 5 interrupt */
+#define IRQ_DMA1C6         14   /* DMA1 channel 6 interrupt */
+#define IRQ_DMA1C7         15   /* DMA1 channel 7 interrupt */
+#define IRQ_VPM            16   /* Voice process module interrupt */
+#define IRQ_USBHD2         17   /* USB host2/device2 interrupt */
+#define IRQ_USBH1          18   /* USB1 host interrupt */
+#define IRQ_USBD           19   /* USB device interrupt */
+#define IRQ_SDIOH0         20   /* SDIO0 host interrupt */
+#define IRQ_SDIOH1         21   /* SDIO1 host interrupt */
+#define IRQ_TIMER0         22   /* Timer0 interrupt */
+#define IRQ_TIMER1         23   /* Timer1 interrupt */
+#define IRQ_TIMER2         24   /* Timer2 interrupt */
+#define IRQ_TIMER3         25   /* Timer3 interrupt */
+#define IRQ_SPIH           26   /* SPI host interrupt */
+#define IRQ_ESW            27   /* Ethernet switch interrupt */
+#define IRQ_APM            28   /* Audio process module interrupt */
+#define IRQ_GE             29   /* Graphic engine interrupt */
+#define IRQ_CLCD           30   /* LCD Controller interrupt */
+#define IRQ_PIF            31   /* Peripheral interface interrupt */
+#define IRQ_INTC0_END      31
+/* INTC1 - interrupt controller 1 */
+#define IRQ_INTC1_START    32
+#define IRQ_GPIO0          32   /*  0 GPIO bit 31//0 combined interrupt */
+#define IRQ_GPIO1          33   /*  1 GPIO bit 64//32 combined interrupt */
+#define IRQ_I2S0           34   /*  2 I2S0 interrupt */
+#define IRQ_I2S1           35   /*  3 I2S1 interrupt */
+#define IRQ_I2CH           36   /*  4 I2C host interrupt */
+#define IRQ_I2CS           37   /*  5 I2C slave interrupt */
+#define IRQ_SPIS           38   /*  6 SPI slave interrupt */
+#define IRQ_GPHY           39   /*  7 Gigabit Phy interrupt */
+#define IRQ_FLASHC         40   /*  8 Flash controller interrupt */
+#define IRQ_COMMTX         41   /*  9 ARM DDC transmit interrupt */
+#define IRQ_COMMRX         42   /* 10 ARM DDC receive interrupt */
+#define IRQ_PMUIRQ         43   /* 11 ARM performance monitor interrupt */
+#define IRQ_UARTB          44   /* 12 UARTB */
+#define IRQ_WATCHDOG       45   /* 13 Watchdog timer interrupt */
+#define IRQ_UARTA          46   /* 14 UARTA */
+#define IRQ_TSC            47   /* 15 Touch screen controller interrupt */
+#define IRQ_KEYC           48   /* 16 Key pad controller interrupt */
+#define IRQ_DMPU           49   /* 17 DDR2 memory partition interrupt */
+#define IRQ_VMPU           50   /* 18 VRAM memory partition interrupt */
+#define IRQ_FMPU           51   /* 19 Flash memory parition unit interrupt */
+#define IRQ_RNG            52   /* 20 Random number generator interrupt */
+#define IRQ_RTC0           53   /* 21 Real time clock periodic interrupt */
+#define IRQ_RTC1           54   /* 22 Real time clock one-shot interrupt */
+#define IRQ_SPUM           55   /* 23 Secure process module interrupt */
+#define IRQ_VDEC           56   /* 24 Hantro video decoder interrupt */
+#define IRQ_RTC2           57   /* 25 Real time clock tamper interrupt */
+#define IRQ_DDRP           58   /* 26 DDR Panic interrupt */
+#define IRQ_INTC1_END      58
+/* SINTC secure int controller */
+#define IRQ_SINTC_START    59
+#define IRQ_SEC_WATCHDOG   59   /*  0 Watchdog timer interrupt */
+#define IRQ_SEC_UARTA      60   /*  1 UARTA interrupt */
+#define IRQ_SEC_TSC        61   /*  2 Touch screen controller interrupt */
+#define IRQ_SEC_KEYC       62   /*  3 Key pad controller interrupt */
+#define IRQ_SEC_DMPU       63   /*  4 DDR2 memory partition interrupt */
+#define IRQ_SEC_VMPU       64   /*  5 VRAM memory partition interrupt */
+#define IRQ_SEC_FMPU       65   /*  6 Flash memory parition unit interrupt */
+#define IRQ_SEC_RNG        66   /*  7 Random number generator interrupt */
+#define IRQ_SEC_RTC0       67   /*  8 Real time clock periodic interrupt */
+#define IRQ_SEC_RTC1       68   /*  9 Real time clock one-shot interrupt */
+#define IRQ_SEC_SPUM       69   /* 10 Secure process module interrupt */
+#define IRQ_SEC_TIMER0     70   /* 11 Secure timer0 interrupt */
+#define IRQ_SEC_TIMER1     71   /* 12 Secure timer1 interrupt */
+#define IRQ_SEC_TIMER2     72   /* 13 Secure timer2 interrupt */
+#define IRQ_SEC_TIMER3     73   /* 14 Secure timer3 interrupt */
+#define IRQ_SEC_RTC2       74   /* 15 Real time clock tamper interrupt */
+#define IRQ_SINTC_END      74
+/* Note: there are 3 INTC registers of 32 bits each. So internal IRQs could go from 0-95 */
+/*       Since IRQs are typically viewed in decimal, we start the gpio based IRQs off at 100 */
+/*       to make the mapping easy for humans to decipher. */
+#define IRQ_GPIO_0                  100
+#define NUM_INTERNAL_IRQS          (IRQ_SINTC_END+1)
+/* I couldn't get the gpioHw_reg.h file to be included cleanly, so I hardcoded it */
+/* define NUM_GPIO_IRQS               GPIOHW_TOTAL_NUM_PINS */
+#define NUM_GPIO_IRQS               62
+#define NR_IRQS                     (IRQ_GPIO_0 + NUM_GPIO_IRQS)
+#define IRQ_UNKNOWN                 -1
+/* Tune these bits to preclude noisy or unsupported interrupt sources as required. */
+#define IRQ_INTC0_VALID_MASK        0xffffffff
+#define IRQ_INTC1_VALID_MASK        0x07ffffff
+#define IRQ_SINTC_VALID_MASK        0x0000ffff
+#endif /* ARCH_BCMRING_IRQS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h
new file mode 100644
index 000000000000..114f942bb4f3
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory.h
@@ -0,0 +1,33 @@
+/*****************************************************************************
+* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#include <cfg_global.h>
+/*
+ * Physical vs virtual RAM address space conversion.  These are
+ * private definitions which should NOT be used outside memory.h
+ * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
+ */
+#define PHYS_OFFSET CFG_GLOBAL_RAM_BASE
+/*
+ * Maximum DMA memory allowed is 14M
+ */
+#define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M)
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/memory_settings.h b/arch/arm/mach-bcmring/include/mach/memory_settings.h
new file mode 100644
index 000000000000..ce5cd16f2ac4
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/memory_settings.h
@@ -0,0 +1,67 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#ifndef MEMORY_SETTINGS_H
+#define MEMORY_SETTINGS_H
+/* ---- Include Files ---------------------------------------- */
+/* ---- Constants and Types ---------------------------------- */
+/* Memory devices */
+/* NAND Flash timing for 166 MHz setting */
+#define HW_CFG_NAND_tBTA  (5 << 16)     /* Bus turnaround cycle (n)        0-7  (30 ns) */
+#define HW_CFG_NAND_tWP   (4 << 11)     /* Write pulse width cycle (n+1)   0-31 (25 ns) */
+#define HW_CFG_NAND_tWR   (1 << 9)      /* Write recovery cycle (n+1)      0-3  (10 ns) */
+#define HW_CFG_NAND_tAS   (0 << 7)      /* Write address setup cycle (n+1) 0-3  ( 0 ns) */
+#define HW_CFG_NAND_tOE   (3 << 5)      /* Output enable delay cycle (n)   0-3  (15 ns) */
+#define HW_CFG_NAND_tRC   (7 << 0)      /* Read access cycle (n+2)         0-31 (50 ns) */
+#define HW_CFG_NAND_TCR (HW_CFG_NAND_tBTA \
+        | HW_CFG_NAND_tWP  \
+        | HW_CFG_NAND_tWR  \
+        | HW_CFG_NAND_tAS  \
+        | HW_CFG_NAND_tOE  \
+        | HW_CFG_NAND_tRC)
+/* NOR Flash timing for 166 MHz setting */
+#define HW_CFG_NOR_TPRC_TWLC (0 << 19)  /* Page read access cycle / Burst write latency (n+2 / n+1) (max 25ns) */
+#define HW_CFG_NOR_TBTA      (0 << 16)  /* Bus turnaround cycle (n)                                 (DNA)      */
+#define HW_CFG_NOR_TWP       (6 << 11)  /* Write pulse width cycle (n+1)                            (35ns)     */
+#define HW_CFG_NOR_TWR       (0 << 9)   /* Write recovery cycle (n+1)                               (0ns)      */
+#define HW_CFG_NOR_TAS       (0 << 7)   /* Write address setup cycle (n+1)                          (0ns)      */
+#define HW_CFG_NOR_TOE       (0 << 5)   /* Output enable delay cycle (n)                            (max 25ns) */
+#define HW_CFG_NOR_TRC_TLC   (0x10 << 0)        /* Read access cycle / Burst read latency (n+2 / n+1)       (100ns)    */
+#define HW_CFG_FLASH0_TCR (HW_CFG_NOR_TPRC_TWLC \
+        | HW_CFG_NOR_TBTA      \
+        | HW_CFG_NOR_TWP       \
+        | HW_CFG_NOR_TWR       \
+        | HW_CFG_NOR_TAS       \
+        | HW_CFG_NOR_TOE       \
+        | HW_CFG_NOR_TRC_TLC)
+#define HW_CFG_FLASH1_TCR    HW_CFG_FLASH0_TCR
+#define HW_CFG_FLASH2_TCR    HW_CFG_FLASH0_TCR
+/* SDRAM Settings */
+/* #define HW_CFG_SDRAM_CAS_LATENCY        5    Default 5, Values [3..6] */
+/* #define HW_CFG_SDRAM_CHIP_SELECT_CNT    1    Default 1, Vaules [1..2] */
+/* #define HW_CFG_SDRAM_SPEED_GRADE        667  Default 667, Values [400,533,667,800] */
+/* #define HW_CFG_SDRAM_WIDTH_BITS         16   Default 16, Vaules [8,16] */
+#define HW_CFG_SDRAM_SIZE_BYTES         0x10000000      /* Total memory, not per device size */
+/* ---- Variable Externs ------------------------------------- */
+/* ---- Function Prototypes ---------------------------------- */
+#endif /* MEMORY_SETTINGS_H */
diff --git a/arch/arm/mach-bcmring/include/mach/system.h b/arch/arm/mach-bcmring/include/mach/system.h
new file mode 100644
index 000000000000..cdbf93c694a6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/system.h
@@ -0,0 +1,54 @@
+/*
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <mach/csp/chipcHw_inline.h>
+extern int bcmring_arch_warm_reboot;
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode, char *cmd)
+{
+        printk("arch_reset:%c %x\n", mode, bcmring_arch_warm_reboot);
+        if (mode == 'h') {
+                /* Reboot configured in proc entry */
+                if (bcmring_arch_warm_reboot) {
+                        printk("warm reset\n");
+                        /* Issue Warm reset (do not reset ethernet switch, keep alive) */
+                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_WARM);
+                } else {
+                        /* Force reset of everything */
+                        printk("force reset\n");
+                        chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+                }
+        } else {
+                /* Force reset of everything */
+                printk("force reset\n");
+                chipcHw_reset(chipcHw_REG_SOFT_RESET_CHIP_SOFT);
+        }
+}
+#endif
diff --git a/arch/arm/mach-bcmring/include/mach/timer.h b/arch/arm/mach-bcmring/include/mach/timer.h
new file mode 100644
index 000000000000..5a94bbb032b6
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/timer.h
@@ -0,0 +1,77 @@
+/*****************************************************************************
+* Copyright 2004 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+/*
+*
+*****************************************************************************
+*
+*  timer.h
+*
+*  PURPOSE:
+*
+*
+*
+*  NOTES:
+*
+*****************************************************************************/
+#if !defined(BCM_LINUX_TIMER_H)
+#define BCM_LINUX_TIMER_H
+#if defined(__KERNEL__)
+/* ---- Include Files ---------------------------------------------------- */
+/* ---- Constants and Types ---------------------------------------------- */
+typedef unsigned int timer_tick_count_t;
+typedef unsigned int timer_tick_rate_t;
+typedef unsigned int timer_msec_t;
+/* ---- Variable Externs ------------------------------------------------- */
+/* ---- Function Prototypes ---------------------------------------------- */
+/****************************************************************************
+*
+*  timer_get_tick_count
+*
+*
+***************************************************************************/
+timer_tick_count_t timer_get_tick_count(void);
+/****************************************************************************
+*
+*  timer_get_tick_rate
+*
+*
+***************************************************************************/
+timer_tick_rate_t timer_get_tick_rate(void);
+/****************************************************************************
+*
+*  timer_get_msec
+*
+*
+***************************************************************************/
+timer_msec_t timer_get_msec(void);
+/****************************************************************************
+*
+*  timer_ticks_to_msec
+*
+*
+***************************************************************************/
+timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks);
+#endif /* __KERNEL__ */
+#endif /* BCM_LINUX_TIMER_H */
diff --git a/arch/arm/mach-bcmring/include/mach/timex.h b/arch/arm/mach-bcmring/include/mach/timex.h
new file mode 100644
index 000000000000..40d033ec5892
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ *
+ *  Integrator architecture timex specifications
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/*
+ * Specifies the number of ticks per second
+ */
+#define CLOCK_TICK_RATE         100000 /* REG_SMT_TICKS_PER_SEC */
diff --git a/arch/arm/mach-bcmring/include/mach/uncompress.h b/arch/arm/mach-bcmring/include/mach/uncompress.h
new file mode 100644
index 000000000000..9c9821b77977
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/uncompress.h
@@ -0,0 +1,43 @@
+/*****************************************************************************
+* Copyright 2005 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <mach/csp/mm_addr.h>
+#define BCMRING_UART_0_DR (*(volatile unsigned int *)MM_ADDR_IO_UARTA)
+#define BCMRING_UART_0_FR (*(volatile unsigned int *)(MM_ADDR_IO_UARTA + 0x18))
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+        /* Send out UARTA */
+        while (BCMRING_UART_0_FR & (1 << 5))
+                ;
+        BCMRING_UART_0_DR = c;
+}
+static inline void flush(void)
+{
+        /* Wait for the tx fifo to be empty */
+        while ((BCMRING_UART_0_FR & (1 << 7)) == 0)
+                ;
+        /* Wait for the final character to be sent on the txd line */
+        while (BCMRING_UART_0_FR & (1 << 3))
+                ;
+}
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-bcmring/include/mach/vmalloc.h b/arch/arm/mach-bcmring/include/mach/vmalloc.h
new file mode 100644
index 000000000000..35e2ead8395c
--- /dev/null
+++ b/arch/arm/mach-bcmring/include/mach/vmalloc.h
@@ -0,0 +1,25 @@
+/*
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/*
+ * Move VMALLOC_END to 0xf0000000 so that the vm space can range from
+ * 0xe0000000 to 0xefffffff. This gives us 256 MB of vm space and handles
+ * larger physical memory designs better.
+ */
+#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
new file mode 100644
index 000000000000..dc1c4939b0ce
--- /dev/null
+++ b/arch/arm/mach-bcmring/irq.c
@@ -0,0 +1,127 @@
+/*
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/init.h>
+#include <linux/stddef.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/version.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/irq.h>
+#include <mach/csp/intcHw_reg.h>
+#include <mach/csp/mm_io.h>
+static void bcmring_mask_irq0(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC0_START),
+               MM_IO_BASE_INTC0 + INTCHW_INTENCLEAR);
+}
+static void bcmring_unmask_irq0(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC0_START),
+               MM_IO_BASE_INTC0 + INTCHW_INTENABLE);
+}
+static void bcmring_mask_irq1(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC1_START),
+               MM_IO_BASE_INTC1 + INTCHW_INTENCLEAR);
+}
+static void bcmring_unmask_irq1(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_INTC1_START),
+               MM_IO_BASE_INTC1 + INTCHW_INTENABLE);
+}
+static void bcmring_mask_irq2(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_SINTC_START),
+               MM_IO_BASE_SINTC + INTCHW_INTENCLEAR);
+}
+static void bcmring_unmask_irq2(unsigned int irq)
+{
+        writel(1 << (irq - IRQ_SINTC_START),
+               MM_IO_BASE_SINTC + INTCHW_INTENABLE);
+}
+static struct irq_chip bcmring_irq0_chip = {
+        .typename = "ARM-INTC0",
+        .ack = bcmring_mask_irq0,
+        .mask = bcmring_mask_irq0,      /* mask a specific interrupt, blocking its delivery. */
+        .unmask = bcmring_unmask_irq0,  /* unmaks an interrupt */
+};
+static struct irq_chip bcmring_irq1_chip = {
+        .typename = "ARM-INTC1",
+        .ack = bcmring_mask_irq1,
+        .mask = bcmring_mask_irq1,
+        .unmask = bcmring_unmask_irq1,
+};
+static struct irq_chip bcmring_irq2_chip = {
+        .typename = "ARM-SINTC",
+        .ack = bcmring_mask_irq2,
+        .mask = bcmring_mask_irq2,
+        .unmask = bcmring_unmask_irq2,
+};
+static void vic_init(void __iomem *base, struct irq_chip *chip,
+                     unsigned int irq_start, unsigned int vic_sources)
+{
+        unsigned int i;
+        for (i = 0; i < 32; i++) {
+                unsigned int irq = irq_start + i;
+                set_irq_chip(irq, chip);
+                set_irq_chip_data(irq, base);
+                if (vic_sources & (1 << i)) {
+                        set_irq_handler(irq, handle_level_irq);
+                        set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
+                }
+        }
+        writel(0, base + INTCHW_INTSELECT);
+        writel(0, base + INTCHW_INTENABLE);
+        writel(~0, base + INTCHW_INTENCLEAR);
+        writel(0, base + INTCHW_IRQSTATUS);
+        writel(~0, base + INTCHW_SOFTINTCLEAR);
+}
+void __init bcmring_init_irq(void)
+{
+        vic_init((void __iomem *)MM_IO_BASE_INTC0, &bcmring_irq0_chip,
+                 IRQ_INTC0_START, IRQ_INTC0_VALID_MASK);
+        vic_init((void __iomem *)MM_IO_BASE_INTC1, &bcmring_irq1_chip,
+                 IRQ_INTC1_START, IRQ_INTC1_VALID_MASK);
+        vic_init((void __iomem *)MM_IO_BASE_SINTC, &bcmring_irq2_chip,
+                 IRQ_SINTC_START, IRQ_SINTC_VALID_MASK);
+        /* special cases */
+        if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
+                set_irq_handler(IRQ_GPIO0, handle_simple_irq);
+        }
+        if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
+                set_irq_handler(IRQ_GPIO1, handle_simple_irq);
+        }
+}
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
new file mode 100644
index 000000000000..0f1c37e4523a
--- /dev/null
+++ b/arch/arm/mach-bcmring/mm.c
@@ -0,0 +1,56 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include <mach/csp/mm_io.h>
+#define IO_DESC(va, sz) { .virtual = va, \
+        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
+        .length = sz, \
+        .type = MT_DEVICE }
+#define MEM_DESC(va, sz) { .virtual = va, \
+        .pfn = __phys_to_pfn(HW_IO_VIRT_TO_PHYS(va)), \
+        .length = sz, \
+        .type = MT_MEMORY }
+static struct map_desc bcmring_io_desc[] __initdata = {
+        IO_DESC(MM_IO_BASE_NAND, SZ_64K),       /* phys:0x28000000-0x28000FFF  virt:0xE8000000-0xE8000FFF  size:0x00010000 */
+        IO_DESC(MM_IO_BASE_UMI, SZ_64K),        /* phys:0x2C000000-0x2C000FFF  virt:0xEC000000-0xEC000FFF  size:0x00010000 */
+        IO_DESC(MM_IO_BASE_BROM, SZ_64K),       /* phys:0x30000000-0x3000FFFF  virt:0xF3000000-0xF300FFFF  size:0x00010000 */
+        MEM_DESC(MM_IO_BASE_ARAM, SZ_1M),       /* phys:0x31000000-0x31FFFFFF  virt:0xF3100000-0xF31FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_DMA0, SZ_1M),        /* phys:0x32000000-0x32FFFFFF  virt:0xF3200000-0xF32FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_DMA1, SZ_1M),        /* phys:0x33000000-0x33FFFFFF  virt:0xF3300000-0xF33FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_ESW, SZ_1M), /* phys:0x34000000-0x34FFFFFF  virt:0xF3400000-0xF34FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_CLCD, SZ_1M),        /* phys:0x35000000-0x35FFFFFF  virt:0xF3500000-0xF35FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_APM, SZ_1M), /* phys:0x36000000-0x36FFFFFF  virt:0xF3600000-0xF36FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_SPUM, SZ_1M),        /* phys:0x37000000-0x37FFFFFF  virt:0xF3700000-0xF37FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_VPM_PROG, SZ_1M),    /* phys:0x38000000-0x38FFFFFF  virt:0xF3800000-0xF38FFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_VPM_DATA, SZ_1M),    /* phys:0x3A000000-0x3AFFFFFF  virt:0xF3A00000-0xF3AFFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_VRAM, SZ_64K),       /* phys:0x40000000-0x4000FFFF  virt:0xF4000000-0xF400FFFF  size:0x00010000 */
+        IO_DESC(MM_IO_BASE_CHIPC, SZ_16M),      /* phys:0x80000000-0x80FFFFFF  virt:0xF8000000-0xF8FFFFFF  size:0x01000000 */
+        IO_DESC(MM_IO_BASE_VPM_EXTMEM_RSVD,
+                SZ_16M),        /* phys:0x0F000000-0x0FFFFFFF  virt:0xF0000000-0xF0FFFFFF  size:0x01000000 */
+};
+void __init bcmring_map_io(void)
+{
+        iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
+}
diff --git a/arch/arm/mach-bcmring/timer.c b/arch/arm/mach-bcmring/timer.c
new file mode 100644
index 000000000000..2d415d2a8e68
--- /dev/null
+++ b/arch/arm/mach-bcmring/timer.c
@@ -0,0 +1,62 @@
+/*****************************************************************************
+* Copyright 2003 - 2008 Broadcom Corporation.  All rights reserved.
+*
+* Unless you and Broadcom execute a separate written software license
+* agreement governing use of this software, this software is licensed to you
+* under the terms of the GNU General Public License version 2, available at
+* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
+*
+* Notwithstanding the above, under no circumstances may you combine this
+* software in any way with any other Broadcom software provided under a
+* license other than the GPL, without Broadcom's express prior written
+* consent.
+*****************************************************************************/
+#include <linux/version.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <csp/tmrHw.h>
+#include <mach/timer.h>
+/* The core.c file initializes timers 1 and 3 as a linux clocksource. */
+/* The real time clock should probably be the real linux clocksource. */
+/* In the meantime, this file should agree with core.c as to the */
+/* profiling timer. If the clocksource is moved to rtc later, then */
+/* we can init the profiling timer here instead. */
+/* Timer 1 provides 25MHz resolution syncrhonized to scheduling and APM timing */
+/* Timer 3 provides bus freqeuncy sychronized to ACLK, but spread spectrum will */
+/* affect synchronization with scheduling and APM timing. */
+#define PROF_TIMER 1
+timer_tick_rate_t timer_get_tick_rate(void)
+{
+        return tmrHw_getCountRate(PROF_TIMER);
+}
+timer_tick_count_t timer_get_tick_count(void)
+{
+        return tmrHw_GetCurrentCount(PROF_TIMER);       /* change downcounter to upcounter */
+}
+timer_msec_t timer_ticks_to_msec(timer_tick_count_t ticks)
+{
+        static int tickRateMsec;
+        if (tickRateMsec == 0) {
+                tickRateMsec = timer_get_tick_rate() / 1000;
+        }
+        return ticks / tickRateMsec;
+}
+timer_msec_t timer_get_msec(void)
+{
+        return timer_ticks_to_msec(timer_get_tick_count());
+}
+EXPORT_SYMBOL(timer_get_tick_count);
+EXPORT_SYMBOL(timer_ticks_to_msec);
+EXPORT_SYMBOL(timer_get_tick_rate);
+EXPORT_SYMBOL(timer_get_msec);
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 3fbd9b0fbe24..caf6d5154aec 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -12,18 +12,15 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
+#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 static struct physmap_flash_data adssphere_flash_data = {
        .width          = 4,
 };
diff --git a/arch/arm/mach-ep93xx/clock.c b/arch/arm/mach-ep93xx/clock.c
index 6c4c1633ed12..3dd0e2a23095 100644
--- a/arch/arm/mach-ep93xx/clock.c
+++ b/arch/arm/mach-ep93xx/clock.c
@@ -22,48 +22,39 @@
 #include <mach/hardware.h>
-/*
- * The EP93xx has two external crystal oscillators.  To generate the
- * required high-frequency clocks, the processor uses two phase-locked-
- * loops (PLLs) to multiply the incoming external clock signal to much
- * higher frequencies that are then divided down by programmable dividers
- * to produce the needed clocks.  The PLLs operate independently of one
- * another.
- */
-#define EP93XX_EXT_CLK_RATE     14745600
-#define EP93XX_EXT_RTC_RATE     32768
 struct clk {
        unsigned long   rate;
        int             users;
        int             sw_locked;
-        u32             enable_reg;
+        void __iomem    *enable_reg;
        u32             enable_mask;
        unsigned long   (*get_rate)(struct clk *clk);
+        int             (*set_rate)(struct clk *clk, unsigned long rate);
 };
 static unsigned long get_uart_rate(struct clk *clk);
+static int set_keytchclk_rate(struct clk *clk, unsigned long rate);
 static struct clk clk_uart1 = {
        .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U1EN,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U1EN,
        .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart2 = {
        .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U2EN,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U2EN,
        .get_rate       = get_uart_rate,
 };
 static struct clk clk_uart3 = {
        .sw_locked      = 1,
-        .enable_reg     = EP93XX_SYSCON_DEVICE_CONFIG,
+        .enable_reg     = EP93XX_SYSCON_DEVCFG,
-        .enable_mask    = EP93XX_SYSCON_DEVICE_CONFIG_U3EN,
+        .enable_mask    = EP93XX_SYSCON_DEVCFG_U3EN,
        .get_rate       = get_uart_rate,
 };
 static struct clk clk_pll1;
@@ -75,6 +66,15 @@ static struct clk clk_usb_host = {
        .enable_reg     = EP93XX_SYSCON_PWRCNT,
        .enable_mask    = EP93XX_SYSCON_PWRCNT_USH_EN,
 };
+static struct clk clk_keypad = {
+        .sw_locked      = 1,
+        .enable_reg     = EP93XX_SYSCON_KEYTCHCLKDIV,
+        .enable_mask    = EP93XX_SYSCON_KEYTCHCLKDIV_KEN,
+        .set_rate       = set_keytchclk_rate,
+};
+static struct clk clk_pwm = {
+        .rate           = EP93XX_EXT_CLK_RATE,
+};
 /* DMA Clocks */
 static struct clk clk_m2p0 = {
@@ -130,27 +130,29 @@ static struct clk clk_m2m1 = {
        { .dev_id = dev, .con_id = con, .clk = ck }
 static struct clk_lookup clocks[] = {
-        INIT_CK("apb:uart1", NULL, &clk_uart1),
+        INIT_CK("apb:uart1",            NULL,           &clk_uart1),
-        INIT_CK("apb:uart2", NULL, &clk_uart2),
+        INIT_CK("apb:uart2",            NULL,           &clk_uart2),
-        INIT_CK("apb:uart3", NULL, &clk_uart3),
+        INIT_CK("apb:uart3",            NULL,           &clk_uart3),
-        INIT_CK(NULL, "pll1", &clk_pll1),
+        INIT_CK(NULL,                   "pll1",         &clk_pll1),
-        INIT_CK(NULL, "fclk", &clk_f),
+        INIT_CK(NULL,                   "fclk",         &clk_f),
-        INIT_CK(NULL, "hclk", &clk_h),
+        INIT_CK(NULL,                   "hclk",         &clk_h),
-        INIT_CK(NULL, "pclk", &clk_p),
+        INIT_CK(NULL,                   "pclk",         &clk_p),
-        INIT_CK(NULL, "pll2", &clk_pll2),
+        INIT_CK(NULL,                   "pll2",         &clk_pll2),
-        INIT_CK("ep93xx-ohci", NULL, &clk_usb_host),
+        INIT_CK("ep93xx-ohci",          NULL,           &clk_usb_host),
-        INIT_CK(NULL, "m2p0", &clk_m2p0),
+        INIT_CK("ep93xx-keypad",        NULL,           &clk_keypad),
-        INIT_CK(NULL, "m2p1", &clk_m2p1),
+        INIT_CK(NULL,                   "pwm_clk",      &clk_pwm),
-        INIT_CK(NULL, "m2p2", &clk_m2p2),
+        INIT_CK(NULL,                   "m2p0",         &clk_m2p0),
-        INIT_CK(NULL, "m2p3", &clk_m2p3),
+        INIT_CK(NULL,                   "m2p1",         &clk_m2p1),
-        INIT_CK(NULL, "m2p4", &clk_m2p4),
+        INIT_CK(NULL,                   "m2p2",         &clk_m2p2),
-        INIT_CK(NULL, "m2p5", &clk_m2p5),
+        INIT_CK(NULL,                   "m2p3",         &clk_m2p3),
-        INIT_CK(NULL, "m2p6", &clk_m2p6),
+        INIT_CK(NULL,                   "m2p4",         &clk_m2p4),
-        INIT_CK(NULL, "m2p7", &clk_m2p7),
+        INIT_CK(NULL,                   "m2p5",         &clk_m2p5),
-        INIT_CK(NULL, "m2p8", &clk_m2p8),
+        INIT_CK(NULL,                   "m2p6",         &clk_m2p6),
-        INIT_CK(NULL, "m2p9", &clk_m2p9),
+        INIT_CK(NULL,                   "m2p7",         &clk_m2p7),
-        INIT_CK(NULL, "m2m0", &clk_m2m0),
+        INIT_CK(NULL,                   "m2p8",         &clk_m2p8),
-        INIT_CK(NULL, "m2m1", &clk_m2m1),
+        INIT_CK(NULL,                   "m2p9",         &clk_m2p9),
+        INIT_CK(NULL,                   "m2m0",         &clk_m2m0),
+        INIT_CK(NULL,                   "m2m1",         &clk_m2m1),
 };
@@ -160,9 +162,11 @@ int clk_enable(struct clk *clk)
                u32 value;
                value = __raw_readl(clk->enable_reg);
+                value |= clk->enable_mask;
                if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
-                __raw_writel(value | clk->enable_mask, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
        }
        return 0;
@@ -175,9 +179,11 @@ void clk_disable(struct clk *clk)
                u32 value;
                value = __raw_readl(clk->enable_reg);
+                value &= ~clk->enable_mask;
                if (clk->sw_locked)
-                        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+                        ep93xx_syscon_swlocked_write(value, clk->enable_reg);
-                __raw_writel(value & ~clk->enable_mask, clk->enable_reg);
+                else
+                        __raw_writel(value, clk->enable_reg);
        }
 }
 EXPORT_SYMBOL(clk_disable);
@@ -202,6 +208,43 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
+static int set_keytchclk_rate(struct clk *clk, unsigned long rate)
+{
+        u32 val;
+        u32 div_bit;
+        val = __raw_readl(clk->enable_reg);
+        /*
+         * The Key Matrix and ADC clocks are configured using the same
+         * System Controller register.  The clock used will be either
+         * 1/4 or 1/16 the external clock rate depending on the
+         * EP93XX_SYSCON_KEYTCHCLKDIV_KDIV/EP93XX_SYSCON_KEYTCHCLKDIV_ADIV
+         * bit being set or cleared.
+         */
+        div_bit = clk->enable_mask >> 15;
+        if (rate == EP93XX_KEYTCHCLK_DIV4)
+                val |= div_bit;
+        else if (rate == EP93XX_KEYTCHCLK_DIV16)
+                val &= ~div_bit;
+        else
+                return -EINVAL;
+        ep93xx_syscon_swlocked_write(val, clk->enable_reg);
+        clk->rate = rate;
+        return 0;
+}
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+        if (clk->set_rate)
+                return clk->set_rate(clk, rate);
+        return -EINVAL;
+}
+EXPORT_SYMBOL(clk_set_rate);
 static char fclk_divisors[] = { 1, 2, 4, 8, 16, 1, 1, 1 };
 static char hclk_divisors[] = { 1, 2, 4, 5, 6, 8, 16, 32 };
diff --git a/arch/arm/mach-ep93xx/core.c b/arch/arm/mach-ep93xx/core.c
index 204dc5cbd0b8..16b92c37ec99 100644
--- a/arch/arm/mach-ep93xx/core.c
+++ b/arch/arm/mach-ep93xx/core.c
@@ -16,40 +16,24 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/spinlock.h>
+#include <linux/platform_device.h>
-#include <linux/sched.h>
 #include <linux/interrupt.h>
-#include <linux/serial.h>
-#include <linux/tty.h>
-#include <linux/bitops.h>
-#include <linux/serial_8250.h>
-#include <linux/serial_core.h>
-#include <linux/device.h>
-#include <linux/mm.h>
 #include <linux/dma-mapping.h>
-#include <linux/time.h>
 #include <linux/timex.h>
-#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
 #include <linux/termios.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/serial.h>
-#include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/i2c-gpio.h>
-#include <asm/types.h>
-#include <asm/setup.h>
-#include <asm/memory.h>
 #include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/system.h>
-#include <asm/tlbflush.h>
-#include <asm/pgtable.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <asm/mach/irq.h>
-#include <mach/gpio.h>
 #include <asm/hardware/vic.h>
@@ -98,7 +82,7 @@ void __init ep93xx_map_io(void)
 */
 static unsigned int last_jiffy_time;
-#define TIMER4_TICKS_PER_JIFFY          ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
+#define TIMER4_TICKS_PER_JIFFY          DIV_ROUND_CLOSEST(CLOCK_TICK_RATE, HZ)
 static irqreturn_t ep93xx_timer_interrupt(int irq, void *dev_id)
 {
@@ -362,8 +346,8 @@ void __init ep93xx_init_irq(void)
 {
        int gpio_irq;
-        vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
+        vic_init(EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK, 0);
-        vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
+        vic_init(EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK, 0);
        for (gpio_irq = gpio_to_irq(0);
             gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
@@ -385,6 +369,47 @@ void __init ep93xx_init_irq(void)
 /*************************************************************************
+ * EP93xx System Controller Software Locked register handling
+ *************************************************************************/
+/*
+ * syscon_swlock prevents anything else from writing to the syscon
+ * block while a software locked register is being written.
+ */
+static DEFINE_SPINLOCK(syscon_swlock);
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&syscon_swlock, flags);
+        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+        __raw_writel(val, reg);
+        spin_unlock_irqrestore(&syscon_swlock, flags);
+}
+EXPORT_SYMBOL(ep93xx_syscon_swlocked_write);
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits)
+{
+        unsigned long flags;
+        unsigned int val;
+        spin_lock_irqsave(&syscon_swlock, flags);
+        val = __raw_readl(EP93XX_SYSCON_DEVCFG);
+        val |= set_bits;
+        val &= ~clear_bits;
+        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+        __raw_writel(val, EP93XX_SYSCON_DEVCFG);
+        spin_unlock_irqrestore(&syscon_swlock, flags);
+}
+EXPORT_SYMBOL(ep93xx_devcfg_set_clear);
+/*************************************************************************
 * EP93xx peripheral handling
 *************************************************************************/
 #define EP93XX_UART_MCR_OFFSET          (0x0100)
@@ -517,10 +542,8 @@ static struct platform_device ep93xx_eth_device = {
 void __init ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr)
 {
-        if (copy_addr) {
+        if (copy_addr)
-                memcpy(data->dev_addr,
+                memcpy_fromio(data->dev_addr, EP93XX_ETHERNET_BASE + 0x50, 6);
-                        (void *)(EP93XX_ETHERNET_BASE + 0x50), 6);
-        }
        ep93xx_eth_data = *data;
        platform_device_register(&ep93xx_eth_device);
@@ -546,19 +569,125 @@ void __init ep93xx_register_i2c(struct i2c_board_info *devices, int num)
        platform_device_register(&ep93xx_i2c_device);
 }
+/*************************************************************************
+ * EP93xx LEDs
+ *************************************************************************/
+static struct gpio_led ep93xx_led_pins[] = {
+        {
+                .name                   = "platform:grled",
+                .gpio                   = EP93XX_GPIO_LINE_GRLED,
+        }, {
+                .name                   = "platform:rdled",
+                .gpio                   = EP93XX_GPIO_LINE_RDLED,
+        },
+};
+static struct gpio_led_platform_data ep93xx_led_data = {
+        .num_leds       = ARRAY_SIZE(ep93xx_led_pins),
+        .leds           = ep93xx_led_pins,
+};
+static struct platform_device ep93xx_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &ep93xx_led_data,
+        },
+};
+/*************************************************************************
+ * EP93xx pwm peripheral handling
+ *************************************************************************/
+static struct resource ep93xx_pwm0_resource[] = {
+        {
+                .start  = EP93XX_PWM_PHYS_BASE,
+                .end    = EP93XX_PWM_PHYS_BASE + 0x10 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device ep93xx_pwm0_device = {
+        .name           = "ep93xx-pwm",
+        .id             = 0,
+        .num_resources  = ARRAY_SIZE(ep93xx_pwm0_resource),
+        .resource       = ep93xx_pwm0_resource,
+};
+static struct resource ep93xx_pwm1_resource[] = {
+        {
+                .start  = EP93XX_PWM_PHYS_BASE + 0x20,
+                .end    = EP93XX_PWM_PHYS_BASE + 0x30 - 1,
+                .flags  = IORESOURCE_MEM,
+        },
+};
+static struct platform_device ep93xx_pwm1_device = {
+        .name           = "ep93xx-pwm",
+        .id             = 1,
+        .num_resources  = ARRAY_SIZE(ep93xx_pwm1_resource),
+        .resource       = ep93xx_pwm1_resource,
+};
+void __init ep93xx_register_pwm(int pwm0, int pwm1)
+{
+        if (pwm0)
+                platform_device_register(&ep93xx_pwm0_device);
+        /* NOTE: EP9307 does not have PWMOUT1 (pin EGPIO14) */
+        if (pwm1)
+                platform_device_register(&ep93xx_pwm1_device);
+}
+int ep93xx_pwm_acquire_gpio(struct platform_device *pdev)
+{
+        int err;
+        if (pdev->id == 0) {
+                err = 0;
+        } else if (pdev->id == 1) {
+                err = gpio_request(EP93XX_GPIO_LINE_EGPIO14,
+                                   dev_name(&pdev->dev));
+                if (err)
+                        return err;
+                err = gpio_direction_output(EP93XX_GPIO_LINE_EGPIO14, 0);
+                if (err)
+                        goto fail;
+                /* PWM 1 output on EGPIO[14] */
+                ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_PONG);
+        } else {
+                err = -ENODEV;
+        }
+        return err;
+fail:
+        gpio_free(EP93XX_GPIO_LINE_EGPIO14);
+        return err;
+}
+EXPORT_SYMBOL(ep93xx_pwm_acquire_gpio);
+void ep93xx_pwm_release_gpio(struct platform_device *pdev)
+{
+        if (pdev->id == 1) {
+                gpio_direction_input(EP93XX_GPIO_LINE_EGPIO14);
+                gpio_free(EP93XX_GPIO_LINE_EGPIO14);
+                /* EGPIO[14] used for GPIO */
+                ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_PONG);
+        }
+}
+EXPORT_SYMBOL(ep93xx_pwm_release_gpio);
 extern void ep93xx_gpio_init(void);
 void __init ep93xx_init_devices(void)
 {
-        unsigned int v;
+        /* Disallow access to MaverickCrunch initially */
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_CPENA);
-        /*
-         * Disallow access to MaverickCrunch initially.
-         */
-        v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
-        v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
-        __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
        ep93xx_gpio_init();
@@ -568,4 +697,5 @@ void __init ep93xx_init_devices(void)
        platform_device_register(&ep93xx_rtc_device);
        platform_device_register(&ep93xx_ohci_device);
+        platform_device_register(&ep93xx_leds);
 }
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index e9e45b92457e..73145ae5d3fa 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -26,18 +26,16 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
 #include <linux/i2c.h>
+#include <linux/mtd/physmap.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 static struct physmap_flash_data edb93xx_flash_data;
 static struct resource edb93xx_flash_resource = {
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 3bad500b71b6..3da7ca816d19 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -12,18 +12,15 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/io.h>
+#include <linux/mtd/physmap.h>
-#include <linux/i2c.h>
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 static struct physmap_flash_data gesbc9312_flash_data = {
        .width          = 4,
 };
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 482cf3d2fbcd..1ea8871e03a9 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -17,15 +17,16 @@
 #include <linux/module.h>
 #include <linux/seq_file.h>
 #include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
-#include <mach/ep93xx-regs.h>
+#include <mach/hardware.h>
-#include <asm/gpio.h>
 struct ep93xx_gpio_chip {
        struct gpio_chip        chip;
-        unsigned int            data_reg;
+        void __iomem            *data_reg;
-        unsigned int            data_dir_reg;
+        void __iomem            *data_dir_reg;
 };
 #define to_ep93xx_gpio_chip(c) container_of(c, struct ep93xx_gpio_chip, chip)
@@ -111,15 +112,61 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 {
        struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
        u8 data_reg, data_dir_reg;
-        int i;
+        int gpio, i;
        data_reg = __raw_readb(ep93xx_chip->data_reg);
        data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
-        for (i = 0; i < chip->ngpio; i++)
+        gpio = ep93xx_chip->chip.base;
-                seq_printf(s, "GPIO %s%d: %s %s\n", chip->label, i,
+        for (i = 0; i < chip->ngpio; i++, gpio++) {
-                           (data_reg & (1 << i)) ? "set" : "clear",
+                int is_out = data_dir_reg & (1 << i);
-                           (data_dir_reg & (1 << i)) ? "out" : "in");
+                seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s",
+                                chip->label, i, gpio,
+                                gpiochip_is_requested(chip, i) ? : "",
+                                is_out ? "out" : "in ",
+                                (data_reg & (1 << i)) ? "hi" : "lo");
+                if (!is_out) {
+                        int irq = gpio_to_irq(gpio);
+                        struct irq_desc *desc = irq_desc + irq;
+                        if (irq >= 0 && desc->action) {
+                                char *trigger;
+                                switch (desc->status & IRQ_TYPE_SENSE_MASK) {
+                                case IRQ_TYPE_NONE:
+                                        trigger = "(default)";
+                                        break;
+                                case IRQ_TYPE_EDGE_FALLING:
+                                        trigger = "edge-falling";
+                                        break;
+                                case IRQ_TYPE_EDGE_RISING:
+                                        trigger = "edge-rising";
+                                        break;
+                                case IRQ_TYPE_EDGE_BOTH:
+                                        trigger = "edge-both";
+                                        break;
+                                case IRQ_TYPE_LEVEL_HIGH:
+                                        trigger = "level-high";
+                                        break;
+                                case IRQ_TYPE_LEVEL_LOW:
+                                        trigger = "level-low";
+                                        break;
+                                default:
+                                        trigger = "?trigger?";
+                                        break;
+                                }
+                                seq_printf(s, " irq-%d %s%s",
+                                                irq, trigger,
+                                                (desc->status & IRQ_WAKEUP)
+                                                        ? " wakeup" : "");
+                        }
+                }
+                seq_printf(s, "\n");
+        }
 }
 #define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio)                      \
diff --git a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
index 967c079180db..ea78e908fc82 100644
--- a/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
+++ b/arch/arm/mach-ep93xx/include/mach/ep93xx-regs.h
@@ -52,40 +52,43 @@
 #define EP93XX_AHB_VIRT_BASE            0xfef00000
 #define EP93XX_AHB_SIZE                 0x00100000
+#define EP93XX_AHB_IOMEM(x)             IOMEM(EP93XX_AHB_VIRT_BASE + (x))
 #define EP93XX_APB_PHYS_BASE            0x80800000
 #define EP93XX_APB_VIRT_BASE            0xfed00000
 #define EP93XX_APB_SIZE                 0x00200000
+#define EP93XX_APB_IOMEM(x)             IOMEM(EP93XX_APB_VIRT_BASE + (x))
 /* AHB peripherals */
-#define EP93XX_DMA_BASE                 ((void __iomem *)               \
+#define EP93XX_DMA_BASE                 EP93XX_AHB_IOMEM(0x00000000)
-                                         (EP93XX_AHB_VIRT_BASE + 0x00000000))
-#define EP93XX_ETHERNET_BASE            (EP93XX_AHB_VIRT_BASE + 0x00010000)
 #define EP93XX_ETHERNET_PHYS_BASE       (EP93XX_AHB_PHYS_BASE + 0x00010000)
+#define EP93XX_ETHERNET_BASE            EP93XX_AHB_IOMEM(0x00010000)
-#define EP93XX_USB_BASE                 (EP93XX_AHB_VIRT_BASE + 0x00020000)
 #define EP93XX_USB_PHYS_BASE            (EP93XX_AHB_PHYS_BASE + 0x00020000)
+#define EP93XX_USB_BASE                 EP93XX_AHB_IOMEM(0x00020000)
-#define EP93XX_RASTER_BASE              (EP93XX_AHB_VIRT_BASE + 0x00030000)
+#define EP93XX_RASTER_BASE              EP93XX_AHB_IOMEM(0x00030000)
-#define EP93XX_GRAPHICS_ACCEL_BASE      (EP93XX_AHB_VIRT_BASE + 0x00040000)
+#define EP93XX_GRAPHICS_ACCEL_BASE      EP93XX_AHB_IOMEM(0x00040000)
-#define EP93XX_SDRAM_CONTROLLER_BASE    (EP93XX_AHB_VIRT_BASE + 0x00060000)
+#define EP93XX_SDRAM_CONTROLLER_BASE    EP93XX_AHB_IOMEM(0x00060000)
-#define EP93XX_PCMCIA_CONTROLLER_BASE   (EP93XX_AHB_VIRT_BASE + 0x00080000)
+#define EP93XX_PCMCIA_CONTROLLER_BASE   EP93XX_AHB_IOMEM(0x00080000)
-#define EP93XX_BOOT_ROM_BASE            (EP93XX_AHB_VIRT_BASE + 0x00090000)
+#define EP93XX_BOOT_ROM_BASE            EP93XX_AHB_IOMEM(0x00090000)
-#define EP93XX_IDE_BASE                 (EP93XX_AHB_VIRT_BASE + 0x000a0000)
+#define EP93XX_IDE_BASE                 EP93XX_AHB_IOMEM(0x000a0000)
-#define EP93XX_VIC1_BASE                (EP93XX_AHB_VIRT_BASE + 0x000b0000)
+#define EP93XX_VIC1_BASE                EP93XX_AHB_IOMEM(0x000b0000)
-#define EP93XX_VIC2_BASE                (EP93XX_AHB_VIRT_BASE + 0x000c0000)
+#define EP93XX_VIC2_BASE                EP93XX_AHB_IOMEM(0x000c0000)
 /* APB peripherals */
-#define EP93XX_TIMER_BASE               (EP93XX_APB_VIRT_BASE + 0x00010000)
+#define EP93XX_TIMER_BASE               EP93XX_APB_IOMEM(0x00010000)
 #define EP93XX_TIMER_REG(x)             (EP93XX_TIMER_BASE + (x))
 #define EP93XX_TIMER1_LOAD              EP93XX_TIMER_REG(0x00)
 #define EP93XX_TIMER1_VALUE             EP93XX_TIMER_REG(0x04)
@@ -102,11 +105,11 @@
 #define EP93XX_TIMER3_CONTROL           EP93XX_TIMER_REG(0x88)
 #define EP93XX_TIMER3_CLEAR             EP93XX_TIMER_REG(0x8c)
-#define EP93XX_I2S_BASE                 (EP93XX_APB_VIRT_BASE + 0x00020000)
+#define EP93XX_I2S_BASE                 EP93XX_APB_IOMEM(0x00020000)
-#define EP93XX_SECURITY_BASE            (EP93XX_APB_VIRT_BASE + 0x00030000)
+#define EP93XX_SECURITY_BASE            EP93XX_APB_IOMEM(0x00030000)
-#define EP93XX_GPIO_BASE                (EP93XX_APB_VIRT_BASE + 0x00040000)
+#define EP93XX_GPIO_BASE                EP93XX_APB_IOMEM(0x00040000)
 #define EP93XX_GPIO_REG(x)              (EP93XX_GPIO_BASE + (x))
 #define EP93XX_GPIO_F_INT_TYPE1         EP93XX_GPIO_REG(0x4c)
 #define EP93XX_GPIO_F_INT_TYPE2         EP93XX_GPIO_REG(0x50)
@@ -124,32 +127,33 @@
 #define EP93XX_GPIO_B_INT_ENABLE        EP93XX_GPIO_REG(0xb8)
 #define EP93XX_GPIO_B_INT_STATUS        EP93XX_GPIO_REG(0xbc)
-#define EP93XX_AAC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00080000)
+#define EP93XX_AAC_BASE                 EP93XX_APB_IOMEM(0x00080000)
-#define EP93XX_SPI_BASE                 (EP93XX_APB_VIRT_BASE + 0x000a0000)
+#define EP93XX_SPI_BASE                 EP93XX_APB_IOMEM(0x000a0000)
-#define EP93XX_IRDA_BASE                (EP93XX_APB_VIRT_BASE + 0x000b0000)
+#define EP93XX_IRDA_BASE                EP93XX_APB_IOMEM(0x000b0000)
-#define EP93XX_UART1_BASE               (EP93XX_APB_VIRT_BASE + 0x000c0000)
 #define EP93XX_UART1_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000c0000)
+#define EP93XX_UART1_BASE               EP93XX_APB_IOMEM(0x000c0000)
-#define EP93XX_UART2_BASE               (EP93XX_APB_VIRT_BASE + 0x000d0000)
 #define EP93XX_UART2_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000d0000)
+#define EP93XX_UART2_BASE               EP93XX_APB_IOMEM(0x000d0000)
-#define EP93XX_UART3_BASE               (EP93XX_APB_VIRT_BASE + 0x000e0000)
 #define EP93XX_UART3_PHYS_BASE          (EP93XX_APB_PHYS_BASE + 0x000e0000)
+#define EP93XX_UART3_BASE               EP93XX_APB_IOMEM(0x000e0000)
-#define EP93XX_KEY_MATRIX_BASE          (EP93XX_APB_VIRT_BASE + 0x000f0000)
+#define EP93XX_KEY_MATRIX_BASE          EP93XX_APB_IOMEM(0x000f0000)
-#define EP93XX_ADC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00100000)
+#define EP93XX_ADC_BASE                 EP93XX_APB_IOMEM(0x00100000)
-#define EP93XX_TOUCHSCREEN_BASE         (EP93XX_APB_VIRT_BASE + 0x00100000)
+#define EP93XX_TOUCHSCREEN_BASE         EP93XX_APB_IOMEM(0x00100000)
-#define EP93XX_PWM_BASE                 (EP93XX_APB_VIRT_BASE + 0x00110000)
+#define EP93XX_PWM_PHYS_BASE            (EP93XX_APB_PHYS_BASE + 0x00110000)
+#define EP93XX_PWM_BASE                 EP93XX_APB_IOMEM(0x00110000)
-#define EP93XX_RTC_BASE                 (EP93XX_APB_VIRT_BASE + 0x00120000)
 #define EP93XX_RTC_PHYS_BASE            (EP93XX_APB_PHYS_BASE + 0x00120000)
+#define EP93XX_RTC_BASE                 EP93XX_APB_IOMEM(0x00120000)
-#define EP93XX_SYSCON_BASE              (EP93XX_APB_VIRT_BASE + 0x00130000)
+#define EP93XX_SYSCON_BASE              EP93XX_APB_IOMEM(0x00130000)
 #define EP93XX_SYSCON_REG(x)            (EP93XX_SYSCON_BASE + (x))
 #define EP93XX_SYSCON_POWER_STATE       EP93XX_SYSCON_REG(0x00)
 #define EP93XX_SYSCON_PWRCNT            EP93XX_SYSCON_REG(0x04)
@@ -172,14 +176,45 @@
 #define EP93XX_SYSCON_STANDBY           EP93XX_SYSCON_REG(0x0c)
 #define EP93XX_SYSCON_CLOCK_SET1        EP93XX_SYSCON_REG(0x20)
 #define EP93XX_SYSCON_CLOCK_SET2        EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_DEVICE_CONFIG     EP93XX_SYSCON_REG(0x80)
+#define EP93XX_SYSCON_DEVCFG            EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVICE_CONFIG_U3EN                (1<<24)
+#define EP93XX_SYSCON_DEVCFG_SWRST      (1<<31)
-#define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE       (1<<23)
+#define EP93XX_SYSCON_DEVCFG_D1ONG      (1<<30)
-#define EP93XX_SYSCON_DEVICE_CONFIG_U2EN                (1<<20)
+#define EP93XX_SYSCON_DEVCFG_D0ONG      (1<<29)
-#define EP93XX_SYSCON_DEVICE_CONFIG_U1EN                (1<<18)
+#define EP93XX_SYSCON_DEVCFG_IONU2      (1<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK       (1<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG       (1<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG       (1<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN       (1<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA      (1<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG      (1<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG      (1<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN       (1<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC       (1<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN       (1<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN        (1<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN      (1<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN      (1<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN      (1<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN      (1<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE     (1<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE     (1<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG       (1<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE     (1<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP   (1<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97  (1<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3    (1<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS        (1<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD      (1<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS       (1<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA      (1<<0)
+#define EP93XX_SYSCON_KEYTCHCLKDIV      EP93XX_SYSCON_REG(0x90)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN  (1<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
 #define EP93XX_SYSCON_SWLOCK            EP93XX_SYSCON_REG(0xc0)
-#define EP93XX_WATCHDOG_BASE            (EP93XX_APB_VIRT_BASE + 0x00140000)
+#define EP93XX_WATCHDOG_BASE            EP93XX_APB_IOMEM(0x00140000)
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 2866297310b7..349fa7cb72d5 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -4,12 +4,23 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
-#include "ep93xx-regs.h"
+#include <mach/ep93xx-regs.h>
+#include <mach/platform.h>
 #define pcibios_assign_all_busses()     0
-#include "platform.h"
+/*
+ * The EP93xx has two external crystal oscillators.  To generate the
+ * required high-frequency clocks, the processor uses two phase-locked-
+ * loops (PLLs) to multiply the incoming external clock signal to much
+ * higher frequencies that are then divided down by programmable dividers
+ * to produce the needed clocks.  The PLLs operate independently of one
+ * another.
+ */
+#define EP93XX_EXT_CLK_RATE     14745600
+#define EP93XX_EXT_RTC_RATE     32768
-#include "ts72xx.h"
+#define EP93XX_KEYTCHCLK_DIV4   (EP93XX_EXT_CLK_RATE / 4)
+#define EP93XX_KEYTCHCLK_DIV16  (EP93XX_EXT_CLK_RATE / 16)
 #endif
diff --git a/arch/arm/mach-ep93xx/include/mach/io.h b/arch/arm/mach-ep93xx/include/mach/io.h
index fd5f081cc8b7..cebcc1c53d63 100644
--- a/arch/arm/mach-ep93xx/include/mach/io.h
+++ b/arch/arm/mach-ep93xx/include/mach/io.h
@@ -1,8 +1,21 @@
 /*
 * arch/arm/mach-ep93xx/include/mach/io.h
 */
+#ifndef __ASM_MACH_IO_H
+#define __ASM_MACH_IO_H
 #define IO_SPACE_LIMIT          0xffffffff
-#define __io(p)         __typesafe_io(p)
+#define __io(p)                 __typesafe_io(p)
-#define __mem_pci(p)    (p)
+#define __mem_pci(p)            (p)
+/*
+ * A typesafe __io() variation for variable initialisers
+ */
+#ifdef __ASSEMBLER__
+#define IOMEM(p)                p
+#else
+#define IOMEM(p)                ((void __iomem __force *)(p))
+#endif
+#endif /* __ASM_MACH_IO_H */
diff --git a/arch/arm/mach-ep93xx/include/mach/platform.h b/arch/arm/mach-ep93xx/include/mach/platform.h
index 05f0f4f2f3ce..5f5fa6574d34 100644
--- a/arch/arm/mach-ep93xx/include/mach/platform.h
+++ b/arch/arm/mach-ep93xx/include/mach/platform.h
@@ -5,6 +5,7 @@
 #ifndef __ASSEMBLY__
 struct i2c_board_info;
+struct platform_device;
 struct ep93xx_eth_data
 {
@@ -15,8 +16,27 @@ struct ep93xx_eth_data
 void ep93xx_map_io(void);
 void ep93xx_init_irq(void);
 void ep93xx_init_time(unsigned long);
+/* EP93xx System Controller software locked register write */
+void ep93xx_syscon_swlocked_write(unsigned int val, void __iomem *reg);
+void ep93xx_devcfg_set_clear(unsigned int set_bits, unsigned int clear_bits);
+static inline void ep93xx_devcfg_set_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(bits, 0x00);
+}
+static inline void ep93xx_devcfg_clear_bits(unsigned int bits)
+{
+        ep93xx_devcfg_set_clear(0x00, bits);
+}
 void ep93xx_register_eth(struct ep93xx_eth_data *data, int copy_addr);
 void ep93xx_register_i2c(struct i2c_board_info *devices, int num);
+void ep93xx_register_pwm(int pwm0, int pwm1);
+int ep93xx_pwm_acquire_gpio(struct platform_device *pdev);
+void ep93xx_pwm_release_gpio(struct platform_device *pdev);
 void ep93xx_init_devices(void);
 extern struct sys_timer ep93xx_timer;
diff --git a/arch/arm/mach-ep93xx/include/mach/system.h b/arch/arm/mach-ep93xx/include/mach/system.h
index ed8f35e4f068..6d661fe9d66c 100644
--- a/arch/arm/mach-ep93xx/include/mach/system.h
+++ b/arch/arm/mach-ep93xx/include/mach/system.h
@@ -11,15 +11,13 @@ static inline void arch_idle(void)
 static inline void arch_reset(char mode, const char *cmd)
 {
-        u32 devicecfg;
        local_irq_disable();
-        devicecfg = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
+        /*
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+         * Set then clear the SWRST bit to initiate a software reset
-        __raw_writel(devicecfg | 0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
+         */
-        __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
+        ep93xx_devcfg_set_bits(EP93XX_SYSCON_DEVCFG_SWRST);
-        __raw_writel(devicecfg & ~0x80000000, EP93XX_SYSCON_DEVICE_CONFIG);
+        ep93xx_devcfg_clear_bits(EP93XX_SYSCON_DEVCFG_SWRST);
        while (1)
                ;
diff --git a/arch/arm/mach-ep93xx/include/mach/ts72xx.h b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
index 411734422c1d..3bd934e9a7f1 100644
--- a/arch/arm/mach-ep93xx/include/mach/ts72xx.h
+++ b/arch/arm/mach-ep93xx/include/mach/ts72xx.h
@@ -67,7 +67,6 @@
 #ifndef __ASSEMBLY__
-#include <linux/io.h>
 static inline int board_is_ts7200(void)
 {
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 15d6815d78c4..0a313e82fb74 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -9,21 +9,16 @@
 * published by the Free Software Foundation.
 */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
 #include <linux/kernel.h>
-#include <linux/mm.h>
+#include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/sched.h>
-#include <linux/io.h>
-#include <linux/i2c.h>
 #include <linux/mtd/physmap.h>
 #include <mach/hardware.h>
-#include <asm/mach/arch.h>
 #include <asm/mach-types.h>
+#include <asm/mach/arch.h>
 static struct ep93xx_eth_data micro9_eth_data = {
        .phy_id         = 0x1f,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index aaf1371412af..259f7822ba52 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -12,19 +12,18 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/mtd/physmap.h>
 #include <linux/platform_device.h>
-#include <linux/m48t86.h>
 #include <linux/io.h>
-#include <linux/i2c.h>
+#include <linux/m48t86.h>
+#include <linux/mtd/physmap.h>
 #include <mach/hardware.h>
+#include <mach/ts72xx.h>
 #include <asm/mach-types.h>
-#include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/mach/arch.h>
 static struct map_desc ts72xx_io_desc[] __initdata = {
        {
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
index 1251319ef9ae..d795642fad22 100644
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ b/arch/arm/mach-integrator/include/mach/hardware.h
@@ -36,8 +36,12 @@
 #define PCIO_BASE               PCI_IO_VADDR
 #define PCIMEM_BASE             PCI_MEMORY_VADDR
+#ifdef CONFIG_MMU
 /* macro to get at IO space when running virtually */
 #define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) 
+#else
+#define IO_ADDRESS(x) (x)
+#endif
 #define pcibios_assign_all_busses()     1
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4ac04055c2ea..2a318eba1b07 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -49,14 +49,14 @@
 #define INTCP_PA_CLCD_BASE              0xc0000000
-#define INTCP_VA_CIC_BASE               0xf1000040
+#define INTCP_VA_CIC_BASE               IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40
-#define INTCP_VA_PIC_BASE               0xf1400000
+#define INTCP_VA_PIC_BASE               IO_ADDRESS(INTEGRATOR_IC_BASE)
-#define INTCP_VA_SIC_BASE               0xfca00000
+#define INTCP_VA_SIC_BASE               IO_ADDRESS(0xca000000)
 #define INTCP_PA_ETH_BASE               0xc8000000
 #define INTCP_ETH_SIZE                  0x10
-#define INTCP_VA_CTRL_BASE              0xfcb00000
+#define INTCP_VA_CTRL_BASE              IO_ADDRESS(0xcb000000)
 #define INTCP_FLASHPROG                 0x04
 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
@@ -121,12 +121,12 @@ static struct map_desc intcp_io_desc[] __initdata = {
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = 0xfca00000,
+                .virtual        = IO_ADDRESS(0xca000000),
                .pfn            = __phys_to_pfn(0xca000000),
                .length         = SZ_4K,
                .type           = MT_DEVICE
        }, {
-                .virtual        = 0xfcb00000,
+                .virtual        = IO_ADDRESS(0xcb000000),
                .pfn            = __phys_to_pfn(0xcb000000),
                .length         = SZ_4K,
                .type           = MT_DEVICE
@@ -394,8 +394,8 @@ static struct platform_device *intcp_devs[] __initdata = {
 */
 static unsigned int mmc_status(struct device *dev)
 {
-        unsigned int status = readl(0xfca00004);
+        unsigned int status = readl(IO_ADDRESS(0xca000000) + 4);
-        writel(8, 0xfcb00008);
+        writel(8, IO_ADDRESS(0xcb000000) + 8);
        return status & 8;
 }
@@ -403,6 +403,8 @@ static unsigned int mmc_status(struct device *dev)
 static struct mmc_platform_data mmc_data = {
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
        .status         = mmc_status,
+        .gpio_wp        = -1,
+        .gpio_cd        = -1,
 };
 static struct amba_device mmc_device = {
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 1e93dfee7543..5083f03e9b5e 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -416,6 +416,7 @@ static struct clocksource clocksource_ixp4xx = {
 };
 unsigned long ixp4xx_timer_freq = FREQ;
+EXPORT_SYMBOL(ixp4xx_timer_freq);
 static int __init ixp4xx_clocksource_init(void)
 {
        clocksource_ixp4xx.mult =
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index 25100f7acf4c..0aca451b216d 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -38,6 +38,12 @@ config MACH_TS219
          Say 'Y' here if you want your kernel to support the
          QNAP TS-119 and TS-219 Turbo NAS devices.
+config MACH_OPENRD_BASE
+        bool "Marvell OpenRD Base Board"
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell OpenRD Base Board.
 endmenu
 endif
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 9dd680e964d6..80ab0ec90ee1 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_MACH_RD88F6281)		+= rd88f6281-setup.o
 obj-$(CONFIG_MACH_MV88F6281GTW_GE)      += mv88f6281gtw_ge-setup.o
 obj-$(CONFIG_MACH_SHEEVAPLUG)           += sheevaplug-setup.o
 obj-$(CONFIG_MACH_TS219)                += ts219-setup.o
+obj-$(CONFIG_MACH_OPENRD_BASE)          += openrd_base-setup.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 0f6919838011..0acb61f3c10b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -838,7 +838,8 @@ int __init kirkwood_find_tclk(void)
        u32 dev, rev;
        kirkwood_pcie_id(&dev, &rev);
-        if (dev == MV88F6281_DEV_ID && rev == MV88F6281_REV_A0)
+        if (dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
+                                        rev == MV88F6281_REV_A1))
                return 200000000;
        return 166666667;
@@ -872,6 +873,8 @@ static char * __init kirkwood_id(void)
                        return "MV88F6281-Z0";
                else if (rev == MV88F6281_REV_A0)
                        return "MV88F6281-A0";
+                else if (rev == MV88F6281_REV_A1)
+                        return "MV88F6281-A1";
                else
                        return "MV88F6281-Rev-Unsupported";
        } else if (dev == MV88F6192_DEV_ID) {
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 07af858814a0..54c132731d2d 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -101,6 +101,7 @@
 #define MV88F6281_DEV_ID        0x6281
 #define MV88F6281_REV_Z0        0
 #define MV88F6281_REV_A0        2
+#define MV88F6281_REV_A1        3
 #define MV88F6192_DEV_ID        0x6192
 #define MV88F6192_REV_Z0        0
diff --git a/arch/arm/mach-kirkwood/openrd_base-setup.c b/arch/arm/mach-kirkwood/openrd_base-setup.c
new file mode 100644
index 000000000000..947dfb8cd5b2
--- /dev/null
+++ b/arch/arm/mach-kirkwood/openrd_base-setup.c
@@ -0,0 +1,84 @@
+/*
+ * arch/arm/mach-kirkwood/openrd_base-setup.c
+ *
+ * Marvell OpenRD Base Board Setup
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/partitions.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/kirkwood.h>
+#include <plat/mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+static struct mtd_partition openrd_base_nand_parts[] = {
+        {
+                .name = "u-boot",
+                .offset = 0,
+                .size = SZ_1M
+        }, {
+                .name = "uImage",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = SZ_4M
+        }, {
+                .name = "root",
+                .offset = MTDPART_OFS_NXTBLK,
+                .size = MTDPART_SIZ_FULL
+        },
+};
+static struct mv643xx_eth_platform_data openrd_base_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+static struct mv_sata_platform_data openrd_base_sata_data = {
+        .n_ports        = 2,
+};
+static struct mvsdio_platform_data openrd_base_mvsdio_data = {
+        .gpio_card_detect = 29, /* MPP29 used as SD card detect */
+};
+static unsigned int openrd_base_mpp_config[] __initdata = {
+        MPP29_GPIO,
+        0
+};
+static void __init openrd_base_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_init();
+        kirkwood_mpp_conf(openrd_base_mpp_config);
+        kirkwood_uart0_init();
+        kirkwood_nand_init(ARRAY_AND_SIZE(openrd_base_nand_parts), 25);
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&openrd_base_ge00_data);
+        kirkwood_sata_init(&openrd_base_sata_data);
+        kirkwood_sdio_init(&openrd_base_mvsdio_data);
+}
+MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
+        /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
+        .phys_io        = KIRKWOOD_REGS_PHYS_BASE,
+        .io_pg_offst    = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x00000100,
+        .init_machine   = openrd_base_init,
+        .map_io         = kirkwood_map_io,
+        .init_irq       = kirkwood_init_irq,
+        .timer          = &kirkwood_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx1/clock.c b/arch/arm/mach-mx1/clock.c
index 0d0f306851d0..d1b588519ad2 100644
--- a/arch/arm/mach-mx1/clock.c
+++ b/arch/arm/mach-mx1/clock.c
@@ -18,11 +18,14 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/list.h>
 #include <linux/math64.h>
 #include <linux/err.h>
 #include <linux/clk.h>
 #include <linux/io.h>
+#include <asm/clkdev.h>
 #include <mach/clock.h>
 #include <mach/hardware.h>
 #include <mach/common.h>
@@ -94,7 +97,6 @@ static unsigned long clk16m_get_rate(struct clk *clk)
 }
 static struct clk clk16m = {
-        .name = "CLK16M",
        .get_rate = clk16m_get_rate,
        .enable = _clk_enable,
        .enable_reg = CCM_CSCR,
@@ -111,7 +113,6 @@ static unsigned long clk32_get_rate(struct clk *clk)
 }
 static struct clk clk32 = {
-        .name = "CLK32",
        .get_rate = clk32_get_rate,
 };
@@ -121,7 +122,6 @@ static unsigned long clk32_premult_get_rate(struct clk *clk)
 }
 static struct clk clk32_premult = {
-        .name = "CLK32_premultiplier",
        .parent = &clk32,
        .get_rate = clk32_premult_get_rate,
 };
@@ -156,7 +156,6 @@ static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
 }
 static struct clk prem_clk = {
-        .name = "prem_clk",
        .set_parent = prem_clk_set_parent,
 };
@@ -167,7 +166,6 @@ static unsigned long system_clk_get_rate(struct clk *clk)
 }
 static struct clk system_clk = {
-        .name = "system_clk",
        .parent = &prem_clk,
        .get_rate = system_clk_get_rate,
 };
@@ -179,7 +177,6 @@ static unsigned long mcu_clk_get_rate(struct clk *clk)
 }
 static struct clk mcu_clk = {
-        .name = "mcu_clk",
        .parent = &clk32_premult,
        .get_rate = mcu_clk_get_rate,
 };
@@ -195,7 +192,6 @@ static unsigned long fclk_get_rate(struct clk *clk)
 }
 static struct clk fclk = {
-        .name = "fclk",
        .parent = &mcu_clk,
        .get_rate = fclk_get_rate,
 };
@@ -238,7 +234,6 @@ static int hclk_set_rate(struct clk *clk, unsigned long rate)
 }
 static struct clk hclk = {
-        .name = "hclk",
        .parent = &system_clk,
        .get_rate = hclk_get_rate,
        .round_rate = hclk_round_rate,
@@ -280,7 +275,6 @@ static int clk48m_set_rate(struct clk *clk, unsigned long rate)
 }
 static struct clk clk48m = {
-        .name = "CLK48M",
        .parent = &system_clk,
        .get_rate = clk48m_get_rate,
        .round_rate = clk48m_round_rate,
@@ -400,21 +394,18 @@ static int perclk3_set_rate(struct clk *clk, unsigned long rate)
 static struct clk perclk[] = {
        {
-                .name = "perclk",
                .id = 0,
                .parent = &system_clk,
                .get_rate = perclk1_get_rate,
                .round_rate = perclk1_round_rate,
                .set_rate = perclk1_set_rate,
        }, {
-                .name = "perclk",
                .id = 1,
                .parent = &system_clk,
                .get_rate = perclk2_get_rate,
                .round_rate = perclk2_round_rate,
                .set_rate = perclk2_set_rate,
        }, {
-                .name = "perclk",
                .id = 2,
                .parent = &system_clk,
                .get_rate = perclk3_get_rate,
@@ -457,12 +448,10 @@ static int clko_set_parent(struct clk *clk, struct clk *parent)
 }
 static struct clk clko_clk = {
-        .name = "clko_clk",
        .set_parent = clko_set_parent,
 };
 static struct clk dma_clk = {
-        .name = "dma",
        .parent = &hclk,
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
@@ -473,7 +462,6 @@ static struct clk dma_clk = {
 };
 static struct clk csi_clk = {
-        .name = "csi_clk",
        .parent = &hclk,
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
@@ -484,7 +472,6 @@ static struct clk csi_clk = {
 };
 static struct clk mma_clk = {
-        .name = "mma_clk",
        .parent = &hclk,
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
@@ -495,7 +482,6 @@ static struct clk mma_clk = {
 };
 static struct clk usbd_clk = {
-        .name = "usbd_clk",
        .parent = &clk48m,
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
@@ -506,99 +492,85 @@ static struct clk usbd_clk = {
 };
 static struct clk gpt_clk = {
-        .name = "gpt_clk",
        .parent = &perclk[0],
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk uart_clk = {
-        .name = "uart",
        .parent = &perclk[0],
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk i2c_clk = {
-        .name = "i2c_clk",
        .parent = &hclk,
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk spi_clk = {
-        .name = "spi_clk",
        .parent = &perclk[1],
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk sdhc_clk = {
-        .name = "sdhc_clk",
        .parent = &perclk[1],
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk lcdc_clk = {
-        .name = "lcdc_clk",
        .parent = &perclk[1],
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk mshc_clk = {
-        .name = "mshc_clk",
        .parent = &hclk,
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk ssi_clk = {
-        .name = "ssi_clk",
        .parent = &perclk[2],
        .round_rate = _clk_parent_round_rate,
        .set_rate = _clk_parent_set_rate,
 };
 static struct clk rtc_clk = {
-        .name = "rtc_clk",
        .parent = &clk32,
 };
-static struct clk *mxc_clks[] = {
+#define _REGISTER_CLOCK(d, n, c) \
-        &clk16m,
+        { \
-        &clk32,
+                .dev_id = d, \
-        &clk32_premult,
+                .con_id = n, \
-        &prem_clk,
+                .clk = &c, \
-        &system_clk,
+        },
-        &mcu_clk,
+static struct clk_lookup lookups[] __initdata = {
-        &fclk,
+        _REGISTER_CLOCK(NULL, "dma", dma_clk)
-        &hclk,
+        _REGISTER_CLOCK("mx1-camera.0", NULL, csi_clk)
-        &clk48m,
+        _REGISTER_CLOCK(NULL, "mma", mma_clk)
-        &perclk[0],
+        _REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
-        &perclk[1],
+        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
-        &perclk[2],
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
-        &clko_clk,
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
-        &dma_clk,
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
-        &csi_clk,
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-        &mma_clk,
+        _REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
-        &usbd_clk,
+        _REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
-        &gpt_clk,
+        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
-        &uart_clk,
+        _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
-        &i2c_clk,
+        _REGISTER_CLOCK(NULL, "ssi", ssi_clk)
-        &spi_clk,
+        _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk)
-        &sdhc_clk,
-        &lcdc_clk,
-        &mshc_clk,
-        &ssi_clk,
-        &rtc_clk,
 };
 int __init mx1_clocks_init(unsigned long fref)
 {
-        struct clk **clkp;
        unsigned int reg;
+        int i;
        /* disable clocks we are able to */
        __raw_writel(0, SCM_GCCR);
@@ -620,13 +592,13 @@ int __init mx1_clocks_init(unsigned long fref)
        reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
        clko_clk.parent = (struct clk *)clko_clocks[reg];
-        for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
-                clk_register(*clkp);
+                clkdev_add(&lookups[i]);
        clk_enable(&hclk);
        clk_enable(&fclk);
-        mxc_timer_init(&gpt_clk);
+        mxc_timer_init(&gpt_clk, IO_ADDRESS(TIM1_BASE_ADDR), TIM1_INT);
        return 0;
 }
diff --git a/arch/arm/mach-mx1/devices.c b/arch/arm/mach-mx1/devices.c
index 76d1ffb48079..b6be29d1cb08 100644
--- a/arch/arm/mach-mx1/devices.c
+++ b/arch/arm/mach-mx1/devices.c
@@ -29,12 +29,11 @@
 #include "devices.h"
 static struct resource imx_csi_resources[] = {
-        [0] = {
+        {
                .start  = 0x00224000,
                .end    = 0x00224010,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = CSI_INT,
                .end    = CSI_INT,
                .flags  = IORESOURCE_IRQ,
@@ -55,12 +54,11 @@ struct platform_device imx_csi_device = {
 };
 static struct resource imx_i2c_resources[] = {
-        [0] = {
+        {
                .start  = 0x00217000,
                .end    = 0x00217010,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = I2C_INT,
                .end    = I2C_INT,
                .flags  = IORESOURCE_IRQ,
@@ -75,22 +73,19 @@ struct platform_device imx_i2c_device = {
 };
 static struct resource imx_uart1_resources[] = {
-        [0] = {
+        {
                .start  = UART1_BASE_ADDR,
                .end    = UART1_BASE_ADDR + 0xD0,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = UART1_MINT_RX,
                .end    = UART1_MINT_RX,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [2] = {
                .start  = UART1_MINT_TX,
                .end    = UART1_MINT_TX,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [3] = {
                .start  = UART1_MINT_RTS,
                .end    = UART1_MINT_RTS,
                .flags  = IORESOURCE_IRQ,
@@ -105,22 +100,19 @@ struct platform_device imx_uart1_device = {
 };
 static struct resource imx_uart2_resources[] = {
-        [0] = {
+        {
                .start  = UART2_BASE_ADDR,
                .end    = UART2_BASE_ADDR + 0xD0,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = UART2_MINT_RX,
                .end    = UART2_MINT_RX,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [2] = {
                .start  = UART2_MINT_TX,
                .end    = UART2_MINT_TX,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [3] = {
                .start  = UART2_MINT_RTS,
                .end    = UART2_MINT_RTS,
                .flags  = IORESOURCE_IRQ,
@@ -135,17 +127,15 @@ struct platform_device imx_uart2_device = {
 };
 static struct resource imx_rtc_resources[] = {
-        [0] = {
+        {
                .start  = 0x00204000,
                .end    = 0x00204024,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = RTC_INT,
                .end    = RTC_INT,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [2] = {
                .start  = RTC_SAMINT,
                .end    = RTC_SAMINT,
                .flags  = IORESOURCE_IRQ,
@@ -160,12 +150,11 @@ struct platform_device imx_rtc_device = {
 };
 static struct resource imx_wdt_resources[] = {
-        [0] = {
+        {
                .start  = 0x00201000,
                .end    = 0x00201008,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = WDT_INT,
                .end    = WDT_INT,
                .flags  = IORESOURCE_IRQ,
@@ -180,42 +169,35 @@ struct platform_device imx_wdt_device = {
 };
 static struct resource imx_usb_resources[] = {
-        [0] = {
+        {
                .start  = 0x00212000,
                .end    = 0x00212148,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = USBD_INT0,
                .end    = USBD_INT0,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [2] = {
                .start  = USBD_INT1,
                .end    = USBD_INT1,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [3] = {
                .start  = USBD_INT2,
                .end    = USBD_INT2,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [4] = {
                .start  = USBD_INT3,
                .end    = USBD_INT3,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [5] = {
                .start  = USBD_INT4,
                .end    = USBD_INT4,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [6] = {
                .start  = USBD_INT5,
                .end    = USBD_INT5,
                .flags  = IORESOURCE_IRQ,
-        },
+        }, {
-        [7] = {
                .start  = USBD_INT6,
                .end    = USBD_INT6,
                .flags  = IORESOURCE_IRQ,
@@ -231,29 +213,26 @@ struct platform_device imx_usb_device = {
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                .chip.label = "gpio-0",
                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
                .irq = GPIO_INT_PORTA,
-                .virtual_irq_start = MXC_GPIO_IRQ_START
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
+        }, {
-        [1] = {
                .chip.label = "gpio-1",
                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
                .irq = GPIO_INT_PORTB,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 32
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
+        }, {
-        [2] = {
                .chip.label = "gpio-2",
                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
                .irq = GPIO_INT_PORTC,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 64
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        },
+        }, {
-        [3] = {
                .chip.label = "gpio-3",
                .base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
                .irq = GPIO_INT_PORTD,
-                .virtual_irq_start = MXC_GPIO_IRQ_START + 96
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
        }
 };
diff --git a/arch/arm/mach-mx1/generic.c b/arch/arm/mach-mx1/generic.c
index 7622c9b38c97..7f9fc1034c08 100644
--- a/arch/arm/mach-mx1/generic.c
+++ b/arch/arm/mach-mx1/generic.c
@@ -41,6 +41,13 @@ static struct map_desc imx_io_desc[] __initdata = {
 void __init mx1_map_io(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX1);
+        mxc_arch_reset_init(IO_ADDRESS(WDT_BASE_ADDR));
        iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
 }
+void __init mx1_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
diff --git a/arch/arm/mach-mx1/mx1ads.c b/arch/arm/mach-mx1/mx1ads.c
index e5b0c0a83c3b..30f04e56fafe 100644
--- a/arch/arm/mach-mx1/mx1ads.c
+++ b/arch/arm/mach-mx1/mx1ads.c
@@ -104,12 +104,10 @@ static struct imxi2c_platform_data mx1ads_i2c_data = {
 static struct i2c_board_info mx1ads_i2c_devices[] = {
        {
-                I2C_BOARD_INFO("pcf857x", 0x22),
+                I2C_BOARD_INFO("pcf8575", 0x22),
-                .type = "pcf8575",
                .platform_data = &pcf857x_data[0],
        }, {
-                I2C_BOARD_INFO("pcf857x", 0x24),
+                I2C_BOARD_INFO("pcf8575", 0x24),
-                .type = "pcf8575",
                .platform_data = &pcf857x_data[1],
        },
 };
@@ -151,7 +149,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
        .timer          = &mx1ads_timer,
        .init_machine   = mx1ads_init,
 MACHINE_END
@@ -161,7 +159,7 @@ MACHINE_START(MXLADS, "Freescale MXLADS")
        .io_pg_offst    = (IMX_IO_BASE >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
        .timer          = &mx1ads_timer,
        .init_machine   = mx1ads_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx1/scb9328.c b/arch/arm/mach-mx1/scb9328.c
index 20e0b5bcdffc..325d98df6053 100644
--- a/arch/arm/mach-mx1/scb9328.c
+++ b/arch/arm/mach-mx1/scb9328.c
@@ -68,22 +68,20 @@ static struct dm9000_plat_data dm9000_platdata = {
 * to gain access to address latch registers and the data path.
 */
 static struct resource dm9000x_resources[] = {
-        [0] = {
+        {
                .name   = "address area",
                .start  = IMX_CS5_PHYS,
                .end    = IMX_CS5_PHYS + 1,
-                .flags  = IORESOURCE_MEM        /* address access */
+                .flags  = IORESOURCE_MEM,       /* address access */
-        },
+        }, {
-        [1] = {
                .name   = "data area",
                .start  = IMX_CS5_PHYS + 4,
                .end    = IMX_CS5_PHYS + 5,
-                .flags  = IORESOURCE_MEM        /* data access */
+                .flags  = IORESOURCE_MEM,       /* data access */
-        },
+        }, {
-        [2] = {
                .start  = IRQ_GPIOC(3),
                .end    = IRQ_GPIOC(3),
-                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL
+                .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
        },
 };
@@ -154,7 +152,7 @@ MACHINE_START(SCB9328, "Synertronixx scb9328")
        .io_pg_offst    = ((0xe0200000) >> 18) & 0xfffc,
        .boot_params    = 0x08000100,
        .map_io         = mx1_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx1_init_irq,
        .timer          = &scb9328_timer,
        .init_machine   = scb9328_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/Kconfig b/arch/arm/mach-mx2/Kconfig
index c77da586b71d..c8a2eac4d13c 100644
--- a/arch/arm/mach-mx2/Kconfig
+++ b/arch/arm/mach-mx2/Kconfig
@@ -53,6 +53,34 @@ config MACH_PCM970_BASEBOARD
 endchoice
+config MACH_EUKREA_CPUIMX27
+        bool "Eukrea CPUIMX27 module"
+        depends on MACH_MX27
+        help
+          Include support for Eukrea CPUIMX27 platform. This includes
+          specific configurations for the module and its peripherals.
+config MACH_EUKREA_CPUIMX27_USESDHC2
+        bool "CPUIMX27 integrates SDHC2 module"
+        depends on MACH_EUKREA_CPUIMX27
+        help
+          This adds support for the internal SDHC2 used on CPUIMX27 used
+          for wifi or eMMC.
+choice
+        prompt "Baseboard"
+        depends on MACH_EUKREA_CPUIMX27
+        default MACH_EUKREA_MBIMX27_BASEBOARD
+config MACH_EUKREA_MBIMX27_BASEBOARD
+        prompt "Eukrea MBIMX27 development board"
+        bool
+        help
+          This adds board specific devices that can be found on Eukrea's
+          MBIMX27 evaluation board.
+endchoice
 config MACH_MX27_3DS
        bool "MX27PDK platform"
        depends on MACH_MX27
@@ -67,4 +95,11 @@ config MACH_MX27LITE
          Include support for MX27 LITEKIT platform. This includes specific
          configurations for the board and its peripherals.
+config MACH_PCA100
+        bool "Phytec phyCARD-s (pca100)"
+        depends on MACH_MX27
+        help
+          Include support for phyCARD-s (aka pca100) platform. This
+          includes specific configurations for the module and its peripherals.
 endif
diff --git a/arch/arm/mach-mx2/Makefile b/arch/arm/mach-mx2/Makefile
index b9b1cca4e9bc..19560f045632 100644
--- a/arch/arm/mach-mx2/Makefile
+++ b/arch/arm/mach-mx2/Makefile
@@ -17,4 +17,7 @@ obj-$(CONFIG_MACH_PCM038) += pcm038.o
 obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
 obj-$(CONFIG_MACH_MX27_3DS) += mx27pdk.o
 obj-$(CONFIG_MACH_MX27LITE) += mx27lite.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX27) += eukrea_cpuimx27.o
+obj-$(CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD) += eukrea_mbimx27-baseboard.o
+obj-$(CONFIG_MACH_PCA100) += pca100.o
diff --git a/arch/arm/mach-mx2/clock_imx21.c b/arch/arm/mach-mx2/clock_imx21.c
index 0850fb88ec15..eede79855f4a 100644
--- a/arch/arm/mach-mx2/clock_imx21.c
+++ b/arch/arm/mach-mx2/clock_imx21.c
@@ -1004,6 +1004,6 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
        clk_enable(&uart_clk[0]);
 #endif
-        mxc_timer_init(&gpt_clk[0]);
+        mxc_timer_init(&gpt_clk[0], IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
        return 0;
 }
diff --git a/arch/arm/mach-mx2/clock_imx27.c b/arch/arm/mach-mx2/clock_imx27.c
index 2c971442f3f2..4089951acb47 100644
--- a/arch/arm/mach-mx2/clock_imx27.c
+++ b/arch/arm/mach-mx2/clock_imx27.c
@@ -643,7 +643,14 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "cspi3", cspi3_clk)
        _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
        _REGISTER_CLOCK(NULL, "csi", csi_clk)
-        _REGISTER_CLOCK(NULL, "usb", usb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk1)
        _REGISTER_CLOCK(NULL, "ssi1", ssi1_clk)
        _REGISTER_CLOCK(NULL, "ssi2", ssi2_clk)
        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
@@ -748,7 +755,7 @@ int __init mx27_clocks_init(unsigned long fref)
        clk_enable(&uart1_clk);
 #endif
-        mxc_timer_init(&gpt1_clk);
+        mxc_timer_init(&gpt1_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT1);
        return 0;
 }
diff --git a/arch/arm/mach-mx2/devices.c b/arch/arm/mach-mx2/devices.c
index a0f1b3674327..50199aff0143 100644
--- a/arch/arm/mach-mx2/devices.c
+++ b/arch/arm/mach-mx2/devices.c
@@ -40,45 +40,87 @@
 #include "devices.h"
 /*
- * Resource definition for the MXC IrDA
+ * SPI master controller
+ *
+ * - i.MX1: 2 channel (slighly different register setting)
+ * - i.MX21: 2 channel
+ * - i.MX27: 3 channel
 */
-static struct resource mxc_irda_resources[] = {
+static struct resource mxc_spi_resources0[] = {
-        [0] = {
+        {
-                .start   = UART3_BASE_ADDR,
+               .start = CSPI1_BASE_ADDR,
-                .end     = UART3_BASE_ADDR + SZ_4K - 1,
+               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
-                .flags   = IORESOURCE_MEM,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MXC_INT_CSPI1,
+               .end = MXC_INT_CSPI1,
+               .flags = IORESOURCE_IRQ,
        },
-        [1] = {
+};
-                .start   = MXC_INT_UART3,
-                .end     = MXC_INT_UART3,
+static struct resource mxc_spi_resources1[] = {
-                .flags   = IORESOURCE_IRQ,
+        {
+                .start = CSPI2_BASE_ADDR,
+                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI2,
+                .end = MXC_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
        },
 };
-/* Platform Data for MXC IrDA */
+#ifdef CONFIG_MACH_MX27
-struct platform_device mxc_irda_device = {
+static struct resource mxc_spi_resources2[] = {
-        .name = "mxc_irda",
+        {
+                .start = CSPI3_BASE_ADDR,
+                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI3,
+                .end = MXC_INT_CSPI3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+#endif
+struct platform_device mxc_spi_device0 = {
+        .name = "spi_imx",
        .id = 0,
-        .num_resources = ARRAY_SIZE(mxc_irda_resources),
+        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
-        .resource = mxc_irda_resources,
+        .resource = mxc_spi_resources0,
+};
+struct platform_device mxc_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
+        .resource = mxc_spi_resources1,
+};
+#ifdef CONFIG_MACH_MX27
+struct platform_device mxc_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
+        .resource = mxc_spi_resources2,
 };
+#endif
 /*
 * General Purpose Timer
- * - i.MX1: 2 timer (slighly different register handling)
+ * - i.MX21: 3 timers
- * - i.MX21: 3 timer
+ * - i.MX27: 6 timers
- * - i.MX27: 6 timer
 */
 /* We use gpt0 as system timer, so do not add a device for this one */
 static struct resource timer1_resources[] = {
-        [0] = {
+        {
                .start  = GPT2_BASE_ADDR,
                .end    = GPT2_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start   = MXC_INT_GPT2,
                .end     = MXC_INT_GPT2,
                .flags   = IORESOURCE_IRQ,
@@ -89,16 +131,15 @@ struct platform_device mxc_gpt1 = {
        .name = "imx_gpt",
        .id = 1,
        .num_resources = ARRAY_SIZE(timer1_resources),
-        .resource = timer1_resources
+        .resource = timer1_resources,
 };
 static struct resource timer2_resources[] = {
-        [0] = {
+        {
                .start  = GPT3_BASE_ADDR,
                .end    = GPT3_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start   = MXC_INT_GPT3,
                .end     = MXC_INT_GPT3,
                .flags   = IORESOURCE_IRQ,
@@ -109,17 +150,16 @@ struct platform_device mxc_gpt2 = {
        .name = "imx_gpt",
        .id = 2,
        .num_resources = ARRAY_SIZE(timer2_resources),
-        .resource = timer2_resources
+        .resource = timer2_resources,
 };
 #ifdef CONFIG_MACH_MX27
 static struct resource timer3_resources[] = {
-        [0] = {
+        {
                .start  = GPT4_BASE_ADDR,
                .end    = GPT4_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start   = MXC_INT_GPT4,
                .end     = MXC_INT_GPT4,
                .flags   = IORESOURCE_IRQ,
@@ -130,16 +170,15 @@ struct platform_device mxc_gpt3 = {
        .name = "imx_gpt",
        .id = 3,
        .num_resources = ARRAY_SIZE(timer3_resources),
-        .resource = timer3_resources
+        .resource = timer3_resources,
 };
 static struct resource timer4_resources[] = {
-        [0] = {
+        {
                .start  = GPT5_BASE_ADDR,
                .end    = GPT5_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start   = MXC_INT_GPT5,
                .end     = MXC_INT_GPT5,
                .flags   = IORESOURCE_IRQ,
@@ -150,16 +189,15 @@ struct platform_device mxc_gpt4 = {
        .name = "imx_gpt",
        .id = 4,
        .num_resources = ARRAY_SIZE(timer4_resources),
-        .resource = timer4_resources
+        .resource = timer4_resources,
 };
 static struct resource timer5_resources[] = {
-        [0] = {
+        {
                .start  = GPT6_BASE_ADDR,
                .end    = GPT6_BASE_ADDR + 0x17,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start   = MXC_INT_GPT6,
                .end     = MXC_INT_GPT6,
                .flags   = IORESOURCE_IRQ,
@@ -170,7 +208,7 @@ struct platform_device mxc_gpt5 = {
        .name = "imx_gpt",
        .id = 5,
        .num_resources = ARRAY_SIZE(timer5_resources),
-        .resource = timer5_resources
+        .resource = timer5_resources,
 };
 #endif
@@ -214,11 +252,11 @@ static struct resource mxc_nand_resources[] = {
        {
                .start  = NFC_BASE_ADDR,
                .end    = NFC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
        }, {
                .start  = MXC_INT_NANDFC,
                .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -240,8 +278,7 @@ static struct resource mxc_fb[] = {
                .start = LCDC_BASE_ADDR,
                .end   = LCDC_BASE_ADDR + 0xFFF,
                .flags = IORESOURCE_MEM,
-        },
+        }, {
-        {
                .start = MXC_INT_LCDC,
                .end   = MXC_INT_LCDC,
                .flags = IORESOURCE_IRQ,
@@ -264,11 +301,11 @@ static struct resource mxc_fec_resources[] = {
        {
                .start  = FEC_BASE_ADDR,
                .end    = FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
        }, {
                .start  = MXC_INT_FEC,
                .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -281,15 +318,14 @@ struct platform_device mxc_fec_device = {
 #endif
 static struct resource mxc_i2c_1_resources[] = {
-        [0] = {
+        {
                .start  = I2C_BASE_ADDR,
                .end    = I2C_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = MXC_INT_I2C,
                .end    = MXC_INT_I2C,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
        }
 };
@@ -297,20 +333,19 @@ struct platform_device mxc_i2c_device0 = {
        .name = "imx-i2c",
        .id = 0,
        .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
-        .resource = mxc_i2c_1_resources
+        .resource = mxc_i2c_1_resources,
 };
 #ifdef CONFIG_MACH_MX27
 static struct resource mxc_i2c_2_resources[] = {
-        [0] = {
+        {
                .start  = I2C2_BASE_ADDR,
                .end    = I2C2_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = MXC_INT_I2C2,
                .end    = MXC_INT_I2C2,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
        }
 };
@@ -318,17 +353,16 @@ struct platform_device mxc_i2c_device1 = {
        .name = "imx-i2c",
        .id = 1,
        .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
-        .resource = mxc_i2c_2_resources
+        .resource = mxc_i2c_2_resources,
 };
 #endif
 static struct resource mxc_pwm_resources[] = {
-        [0] = {
+        {
                .start  = PWM_BASE_ADDR,
                .end    = PWM_BASE_ADDR + 0x0fff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start   = MXC_INT_PWM,
                .end     = MXC_INT_PWM,
                .flags   = IORESOURCE_IRQ,
@@ -339,28 +373,26 @@ struct platform_device mxc_pwm_device = {
        .name = "mxc_pwm",
        .id = 0,
        .num_resources = ARRAY_SIZE(mxc_pwm_resources),
-        .resource = mxc_pwm_resources
+        .resource = mxc_pwm_resources,
 };
 /*
 * Resource definition for the MXC SDHC
 */
 static struct resource mxc_sdhc1_resources[] = {
-        [0] = {
+        {
-                        .start = SDHC1_BASE_ADDR,
+                .start = SDHC1_BASE_ADDR,
-                        .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
+                .end   = SDHC1_BASE_ADDR + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
+                .flags = IORESOURCE_MEM,
-                        },
+        }, {
-        [1] = {
+                .start = MXC_INT_SDHC1,
-                        .start = MXC_INT_SDHC1,
+                .end   = MXC_INT_SDHC1,
-                        .end   = MXC_INT_SDHC1,
+                .flags = IORESOURCE_IRQ,
-                        .flags = IORESOURCE_IRQ,
+        }, {
-                        },
+                .start  = DMA_REQ_SDHC1,
-        [2] = {
+                .end    = DMA_REQ_SDHC1,
-                        .start  = DMA_REQ_SDHC1,
+                .flags  = IORESOURCE_DMA,
-                        .end    = DMA_REQ_SDHC1,
+        },
-                        .flags  = IORESOURCE_DMA
-                },
 };
 static u64 mxc_sdhc1_dmamask = 0xffffffffUL;
@@ -377,21 +409,19 @@ struct platform_device mxc_sdhc_device0 = {
 };
 static struct resource mxc_sdhc2_resources[] = {
-        [0] = {
+        {
-                        .start = SDHC2_BASE_ADDR,
+                .start = SDHC2_BASE_ADDR,
-                        .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
+                .end   = SDHC2_BASE_ADDR + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
+                .flags = IORESOURCE_MEM,
-                        },
+        }, {
-        [1] = {
+                .start = MXC_INT_SDHC2,
-                        .start = MXC_INT_SDHC2,
+                .end   = MXC_INT_SDHC2,
-                        .end   = MXC_INT_SDHC2,
+                .flags = IORESOURCE_IRQ,
-                        .flags = IORESOURCE_IRQ,
+        }, {
-                        },
+                .start  = DMA_REQ_SDHC2,
-        [2] = {
+                .end    = DMA_REQ_SDHC2,
-                        .start  = DMA_REQ_SDHC2,
+                .flags  = IORESOURCE_DMA,
-                        .end    = DMA_REQ_SDHC2,
+        },
-                        .flags  = IORESOURCE_DMA
-                },
 };
 static u64 mxc_sdhc2_dmamask = 0xffffffffUL;
@@ -407,35 +437,123 @@ struct platform_device mxc_sdhc_device1 = {
       .resource       = mxc_sdhc2_resources,
 };
+#ifdef CONFIG_MACH_MX27
+static struct resource otg_resources[] = {
+        {
+                .start  = OTG_BASE_ADDR,
+                .end    = OTG_BASE_ADDR + 0x1ff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = MXC_INT_USB3,
+                .end    = MXC_INT_USB3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static u64 otg_dmamask = 0xffffffffUL;
+/* OTG gadget device */
+struct platform_device mxc_otg_udc_device = {
+        .name           = "fsl-usb2-udc",
+        .id             = -1,
+        .dev            = {
+                .dma_mask               = &otg_dmamask,
+                .coherent_dma_mask      = 0xffffffffUL,
+        },
+        .resource       = otg_resources,
+        .num_resources  = ARRAY_SIZE(otg_resources),
+};
+/* OTG host */
+struct platform_device mxc_otg_host = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = otg_resources,
+        .num_resources = ARRAY_SIZE(otg_resources),
+};
+/* USB host 1 */
+static u64 usbh1_dmamask = 0xffffffffUL;
+static struct resource mxc_usbh1_resources[] = {
+        {
+                .start = OTG_BASE_ADDR + 0x200,
+                .end = OTG_BASE_ADDR + 0x3ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB1,
+                .end = MXC_INT_USB1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_usbh1 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh1_dmamask,
+        },
+        .resource = mxc_usbh1_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+};
+/* USB host 2 */
+static u64 usbh2_dmamask = 0xffffffffUL;
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = OTG_BASE_ADDR + 0x400,
+                .end = OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB2,
+                .end = MXC_INT_USB2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 2,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+#endif
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                .chip.label = "gpio-0",
                .irq = MXC_INT_GPIO,
                .base = IO_ADDRESS(GPIO_BASE_ADDR),
                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
+        }, {
-        [1] = {
                .chip.label = "gpio-1",
                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
+        }, {
-        [2] = {
                .chip.label = "gpio-2",
                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
-        },
+        }, {
-        [3] = {
                .chip.label = "gpio-3",
                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
-        },
+        }, {
-        [4] = {
                .chip.label = "gpio-4",
                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x400),
                .virtual_irq_start = MXC_GPIO_IRQ_START + 128,
-        },
+        }, {
-        [5] = {
                .chip.label = "gpio-5",
                .base = IO_ADDRESS(GPIO_BASE_ADDR + 0x500),
                .virtual_irq_start = MXC_GPIO_IRQ_START + 160,
diff --git a/arch/arm/mach-mx2/devices.h b/arch/arm/mach-mx2/devices.h
index 049005bb6aa9..d315406d6725 100644
--- a/arch/arm/mach-mx2/devices.h
+++ b/arch/arm/mach-mx2/devices.h
@@ -4,7 +4,6 @@ extern struct platform_device mxc_gpt3;
 extern struct platform_device mxc_gpt4;
 extern struct platform_device mxc_gpt5;
 extern struct platform_device mxc_wdt;
-extern struct platform_device mxc_irda_device;
 extern struct platform_device mxc_uart_device0;
 extern struct platform_device mxc_uart_device1;
 extern struct platform_device mxc_uart_device2;
@@ -20,3 +19,11 @@ extern struct platform_device mxc_i2c_device0;
 extern struct platform_device mxc_i2c_device1;
 extern struct platform_device mxc_sdhc_device0;
 extern struct platform_device mxc_sdhc_device1;
+extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_otg_host;
+extern struct platform_device mxc_usbh1;
+extern struct platform_device mxc_usbh2;
+extern struct platform_device mxc_spi_device0;
+extern struct platform_device mxc_spi_device1;
+extern struct platform_device mxc_spi_device2;
diff --git a/arch/arm/mach-mx2/eukrea_cpuimx27.c b/arch/arm/mach-mx2/eukrea_cpuimx27.c
new file mode 100644
index 000000000000..7b187606682c
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_cpuimx27.c
@@ -0,0 +1,234 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm038.c which is :
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/i2c.h>
+#include <linux/io.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/board-eukrea_cpuimx27.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/i2c.h>
+#include <mach/iomux.h>
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+#include "devices.h"
+static int eukrea_cpuimx27_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* UART4 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* I2C1 */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        /* SDHC2 */
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        /* Quad UART's IRQ */
+        GPIO_PORTD | 22 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 23 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN,
+        GPIO_PORTD | 30 | GPIO_GPIO | GPIO_IN,
+#endif
+};
+static struct physmap_flash_data eukrea_cpuimx27_flash_data = {
+        .width = 2,
+};
+static struct resource eukrea_cpuimx27_flash_resource = {
+        .start = 0xc0000000,
+        .end   = 0xc3ffffff,
+        .flags = IORESOURCE_MEM,
+};
+static struct platform_device eukrea_cpuimx27_nor_mtd_device = {
+        .name = "physmap-flash",
+        .id = 0,
+        .dev = {
+                .platform_data = &eukrea_cpuimx27_flash_data,
+        },
+        .num_resources = 1,
+        .resource = &eukrea_cpuimx27_flash_resource,
+};
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        }, {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+static struct mxc_nand_platform_data eukrea_cpuimx27_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+static struct platform_device *platform_devices[] __initdata = {
+        &eukrea_cpuimx27_nor_mtd_device,
+        &mxc_fec_device,
+};
+static struct imxi2c_platform_data eukrea_cpuimx27_i2c_1_data = {
+        .bitrate = 100000,
+};
+static struct i2c_board_info eukrea_cpuimx27_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("pcf8563", 0x51),
+        },
+};
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+static struct plat_serial8250_port serial_platform_data[] = {
+        {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x200000),
+                .irq = IRQ_GPIOB(23),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x400000),
+                .irq = IRQ_GPIOB(22),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x800000),
+                .irq = IRQ_GPIOB(27),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+                .mapbase = (unsigned long)(CS3_BASE_ADDR + 0x1000000),
+                .irq = IRQ_GPIOB(30),
+                .uartclk = 14745600,
+                .regshift = 1,
+                .iotype = UPIO_MEM,
+                .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
+        }, {
+        }
+};
+static struct platform_device serial_device = {
+        .name = "serial8250",
+        .id = 0,
+        .dev = {
+                .platform_data = serial_platform_data,
+        },
+};
+#endif
+static void __init eukrea_cpuimx27_init(void)
+{
+        mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
+                ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");
+        mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
+        mxc_register_device(&mxc_nand_device, &eukrea_cpuimx27_nand_board_info);
+        i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
+                                ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));
+        mxc_register_device(&mxc_i2c_device0, &eukrea_cpuimx27_i2c_1_data);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
+        /* SDHC2 can be used for Wifi */
+        mxc_register_device(&mxc_sdhc_device1, NULL);
+        /* in which case UART4 is also used for Bluetooth */
+        mxc_register_device(&mxc_uart_device3, &uart_pdata[1]);
+#endif
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+        platform_device_register(&serial_device);
+#endif
+#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
+        eukrea_mbimx27_baseboard_init();
+#endif
+}
+static void __init eukrea_cpuimx27_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+static struct sys_timer eukrea_cpuimx27_timer = {
+        .init = eukrea_cpuimx27_timer_init,
+};
+MACHINE_START(CPUIMX27, "EUKREA CPUIMX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mx27_init_irq,
+        .init_machine   = eukrea_cpuimx27_init,
+        .timer          = &eukrea_cpuimx27_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
new file mode 100644
index 000000000000..7382b6d27ee1
--- /dev/null
+++ b/arch/arm/mach-mx2/eukrea_mbimx27-baseboard.c
@@ -0,0 +1,249 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/ads7846.h>
+#include <asm/mach/arch.h>
+#include <mach/common.h>
+#include <mach/iomux.h>
+#include <mach/imxfb.h>
+#include <mach/hardware.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+#include "devices.h"
+static int eukrea_mbimx27_pins[] = {
+        /* UART2 */
+        PE3_PF_UART2_CTS,
+        PE4_PF_UART2_RTS,
+        PE6_PF_UART2_TXD,
+        PE7_PF_UART2_RXD,
+        /* UART3 */
+        PE8_PF_UART3_TXD,
+        PE9_PF_UART3_RXD,
+        PE10_PF_UART3_CTS,
+        PE11_PF_UART3_RTS,
+        /* UART4 */
+        PB26_AF_UART4_RTS,
+        PB28_AF_UART4_TXD,
+        PB29_AF_UART4_CTS,
+        PB31_AF_UART4_RXD,
+        /* SDHC1*/
+        PE18_PF_SD1_D0,
+        PE19_PF_SD1_D1,
+        PE20_PF_SD1_D2,
+        PE21_PF_SD1_D3,
+        PE22_PF_SD1_CMD,
+        PE23_PF_SD1_CLK,
+        /* display */
+        PA5_PF_LSCLK,
+        PA6_PF_LD0,
+        PA7_PF_LD1,
+        PA8_PF_LD2,
+        PA9_PF_LD3,
+        PA10_PF_LD4,
+        PA11_PF_LD5,
+        PA12_PF_LD6,
+        PA13_PF_LD7,
+        PA14_PF_LD8,
+        PA15_PF_LD9,
+        PA16_PF_LD10,
+        PA17_PF_LD11,
+        PA18_PF_LD12,
+        PA19_PF_LD13,
+        PA20_PF_LD14,
+        PA21_PF_LD15,
+        PA22_PF_LD16,
+        PA23_PF_LD17,
+        PA28_PF_HSYNC,
+        PA29_PF_VSYNC,
+        PA30_PF_CONTRAST,
+        PA31_PF_OE_ACD,
+        /* SPI1 */
+        PD28_PF_CSPI1_SS0,
+        PD29_PF_CSPI1_SCLK,
+        PD30_PF_CSPI1_MISO,
+        PD31_PF_CSPI1_MOSI,
+};
+static struct gpio_led gpio_leds[] = {
+        {
+                .name                   = "led1",
+                .default_trigger        = "heartbeat",
+                .active_low             = 1,
+                .gpio                   = GPIO_PORTF | 16,
+        },
+        {
+                .name                   = "led2",
+                .default_trigger        = "none",
+                .active_low             = 1,
+                .gpio                   = GPIO_PORTF | 19,
+        },
+        {
+                .name                   = "backlight",
+                .default_trigger        = "backlight",
+                .active_low             = 0,
+                .gpio                   = GPIO_PORTE | 5,
+        },
+};
+static struct gpio_led_platform_data gpio_led_info = {
+        .leds           = gpio_leds,
+        .num_leds       = ARRAY_SIZE(gpio_leds),
+};
+static struct platform_device leds_gpio = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data  = &gpio_led_info,
+        },
+};
+static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
+        {
+                .mode = {
+                        .name           = "CMO-QGVA",
+                        .refresh        = 60,
+                        .xres           = 320,
+                        .yres           = 240,
+                        .pixclock       = 156000,
+                        .hsync_len      = 30,
+                        .left_margin    = 38,
+                        .right_margin   = 20,
+                        .vsync_len      = 3,
+                        .upper_margin   = 15,
+                        .lower_margin   = 4,
+                },
+                .pcr            = 0xFAD08B80,
+                .bpp            = 16,
+        },
+};
+static struct imx_fb_platform_data eukrea_mbimx27_fb_data = {
+        .mode = eukrea_mbimx27_modes,
+        .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
+        .pwmr           = 0x00A903FF,
+        .lscr1          = 0x00120300,
+        .dmacr          = 0x00040060,
+};
+static struct imxuart_platform_data uart_pdata[] = {
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+        {
+                .flags = IMXUART_HAVE_RTSCTS,
+        },
+};
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+#define ADS7846_PENDOWN (GPIO_PORTD | 25)
+static void ads7846_dev_init(void)
+{
+        if (gpio_request(ADS7846_PENDOWN, "ADS7846 pendown") < 0) {
+                printk(KERN_ERR "can't get ads746 pen down GPIO\n");
+                return;
+        }
+        gpio_direction_input(ADS7846_PENDOWN);
+}
+static int ads7846_get_pendown_state(void)
+{
+        return !gpio_get_value(ADS7846_PENDOWN);
+}
+static struct ads7846_platform_data ads7846_config __initdata = {
+        .get_pendown_state      = ads7846_get_pendown_state,
+        .keep_vref_on           = 1,
+};
+static struct spi_board_info eukrea_mbimx27_spi_board_info[] __initdata = {
+        [0] = {
+                .modalias       = "ads7846",
+                .bus_num        = 0,
+                .chip_select    = 0,
+                .max_speed_hz   = 1500000,
+                .irq            = IRQ_GPIOD(25),
+                .platform_data  = &ads7846_config,
+                .mode           = SPI_MODE_2,
+        },
+};
+static int eukrea_mbimx27_spi_cs[] = {GPIO_PORTD | 28};
+static struct spi_imx_master eukrea_mbimx27_spi_0_data = {
+        .chipselect     = eukrea_mbimx27_spi_cs,
+        .num_chipselect = ARRAY_SIZE(eukrea_mbimx27_spi_cs),
+};
+#endif
+static struct platform_device *platform_devices[] __initdata = {
+        &leds_gpio,
+};
+/*
+ * system init for baseboard usage. Will be called by cpuimx27 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimx27_baseboard_init(void)
+{
+        mxc_gpio_setup_multiple_pins(eukrea_mbimx27_pins,
+                ARRAY_SIZE(eukrea_mbimx27_pins), "MBIMX27");
+        mxc_register_device(&mxc_uart_device1, &uart_pdata[0]);
+        mxc_register_device(&mxc_uart_device2, &uart_pdata[1]);
+        mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data);
+        mxc_register_device(&mxc_sdhc_device0, NULL);
+#if defined(CONFIG_TOUCHSCREEN_ADS7846)
+        || defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
+        /* SPI and ADS7846 Touchscreen controler init */
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTD | 25 | GPIO_GPIO | GPIO_IN);
+        mxc_register_device(&mxc_spi_device0, &eukrea_mbimx27_spi_0_data);
+        spi_register_board_info(eukrea_mbimx27_spi_board_info,
+                        ARRAY_SIZE(eukrea_mbimx27_spi_board_info));
+        ads7846_dev_init();
+#endif
+        /* Leds configuration */
+        mxc_gpio_mode(GPIO_PORTF | 16 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTF | 19 | GPIO_GPIO | GPIO_OUT);
+        /* Backlight */
+        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_OUT);
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
diff --git a/arch/arm/mach-mx2/generic.c b/arch/arm/mach-mx2/generic.c
index 169372f69d8f..ae8f759134d1 100644
--- a/arch/arm/mach-mx2/generic.c
+++ b/arch/arm/mach-mx2/generic.c
@@ -72,6 +72,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
 void __init mx21_map_io(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX21);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
@@ -79,7 +80,18 @@ void __init mx21_map_io(void)
 void __init mx27_map_io(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX27);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
+void __init mx27_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+void __init mx21_init_irq(void)
+{
+        mx27_init_irq();
+}
diff --git a/arch/arm/mach-mx2/mx21ads.c b/arch/arm/mach-mx2/mx21ads.c
index a5ee461cb405..cf5f77cbc2f1 100644
--- a/arch/arm/mach-mx2/mx21ads.c
+++ b/arch/arm/mach-mx2/mx21ads.c
@@ -164,25 +164,33 @@ static void mx21ads_fb_exit(struct platform_device *pdev)
 * Connected is a portrait Sharp-QVGA display
 * of type: LQ035Q7DB02
 */
-static struct imx_fb_platform_data mx21ads_fb_data = {
+static struct imx_fb_videomode mx21ads_modes[] = {
-        .pixclock       = 188679, /* in ps */
+        {
-        .xres           = 240,
+                .mode = {
-        .yres           = 320,
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
-        .bpp            = 16,
+                        .xres           = 240,
-        .hsync_len      = 2,
+                        .yres           = 320,
-        .left_margin    = 6,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
-        .right_margin   = 16,
+                        .hsync_len      = 2,
+                        .left_margin    = 6,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 8,
+                        .lower_margin   = 10,
+                },
+                .pcr            = 0xfb108bc7,
+                .bpp            = 16,
+        },
+};
-        .vsync_len      = 1,
+static struct imx_fb_platform_data mx21ads_fb_data = {
-        .upper_margin   = 8,
+        .mode = mx21ads_modes,
-        .lower_margin   = 10,
+        .num_modes = ARRAY_SIZE(mx21ads_modes),
-        .fixed_screen_cpu = 0,
-        .pcr            = 0xFB108BC7,
+        .pwmr           = 0x00a903ff,
-        .pwmr           = 0x00A901ff,
+        .lscr1          = 0x00120300,
-        .lscr1          = 0x00120300,
+        .dmacr          = 0x00020008,
-        .dmacr          = 0x00020008,
        .init = mx21ads_fb_init,
        .exit = mx21ads_fb_exit,
@@ -280,7 +288,7 @@ MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx21ads_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx21_init_irq,
        .init_machine   = mx21ads_board_init,
        .timer          = &mx21ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27ads.c b/arch/arm/mach-mx2/mx27ads.c
index 02daddac6995..83e412b713e6 100644
--- a/arch/arm/mach-mx2/mx27ads.c
+++ b/arch/arm/mach-mx2/mx27ads.c
@@ -183,20 +183,29 @@ void lcd_power(int on)
                __raw_writew(PBC_BCTRL1_LCDON, PBC_BCTRL1_CLEAR_REG);
 }
-static struct imx_fb_platform_data mx27ads_fb_data = {
+static struct imx_fb_videomode mx27ads_modes[] = {
-        .pixclock       = 188679,
+        {
-        .xres           = 240,
+                .mode = {
-        .yres           = 320,
+                        .name           = "Sharp-LQ035Q7",
+                        .refresh        = 60,
-        .bpp            = 16,
+                        .xres           = 240,
-        .hsync_len      = 1,
+                        .yres           = 320,
-        .left_margin    = 9,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
-        .right_margin   = 16,
+                        .hsync_len      = 1,
+                        .left_margin    = 9,
+                        .right_margin   = 16,
+                        .vsync_len      = 1,
+                        .upper_margin   = 7,
+                        .lower_margin   = 9,
+                },
+                .bpp            = 16,
+                .pcr            = 0xFB008BC0,
+        },
+};
-        .vsync_len      = 1,
+static struct imx_fb_platform_data mx27ads_fb_data = {
-        .upper_margin   = 7,
+        .mode = mx27ads_modes,
-        .lower_margin   = 9,
+        .num_modes = ARRAY_SIZE(mx27ads_modes),
-        .fixed_screen_cpu = 0,
        /*
         * - HSYNC active high
@@ -207,7 +216,6 @@ static struct imx_fb_platform_data mx27ads_fb_data = {
         * - data enable low active
         * - enable sharp mode
         */
-        .pcr            = 0xFB008BC0,
        .pwmr           = 0x00A903FF,
        .lscr1          = 0x00120300,
        .dmacr          = 0x00020010,
@@ -330,7 +338,7 @@ MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx27ads_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
        .init_machine   = mx27ads_board_init,
        .timer          = &mx27ads_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27lite.c b/arch/arm/mach-mx2/mx27lite.c
index 3ae11cb8c04b..82ea227ea0cf 100644
--- a/arch/arm/mach-mx2/mx27lite.c
+++ b/arch/arm/mach-mx2/mx27lite.c
@@ -89,7 +89,7 @@ MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
        .init_machine   = mx27lite_init,
        .timer          = &mx27lite_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/mx27pdk.c b/arch/arm/mach-mx2/mx27pdk.c
index 1d9238c7a6c3..6761d1b79e43 100644
--- a/arch/arm/mach-mx2/mx27pdk.c
+++ b/arch/arm/mach-mx2/mx27pdk.c
@@ -89,7 +89,7 @@ MACHINE_START(MX27_3DS, "Freescale MX27PDK")
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
        .init_machine   = mx27pdk_init,
        .timer          = &mx27pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/pca100.c b/arch/arm/mach-mx2/pca100.c
new file mode 100644
index 000000000000..fe5b165b88cc
--- /dev/null
+++ b/arch/arm/mach-mx2/pca100.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2009 Sascha Hauer (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/dma-mapping.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/eeprom.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux.h>
+#include <mach/i2c.h>
+#include <asm/mach/time.h>
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+#include <mach/spi.h>
+#endif
+#include <mach/imx-uart.h>
+#include <mach/mxc_nand.h>
+#include <mach/irqs.h>
+#include <mach/mmc.h>
+#include "devices.h"
+static int pca100_pins[] = {
+        /* UART1 */
+        PE12_PF_UART1_TXD,
+        PE13_PF_UART1_RXD,
+        PE14_PF_UART1_CTS,
+        PE15_PF_UART1_RTS,
+        /* SDHC */
+        PB4_PF_SD2_D0,
+        PB5_PF_SD2_D1,
+        PB6_PF_SD2_D2,
+        PB7_PF_SD2_D3,
+        PB8_PF_SD2_CMD,
+        PB9_PF_SD2_CLK,
+        /* FEC */
+        PD0_AIN_FEC_TXD0,
+        PD1_AIN_FEC_TXD1,
+        PD2_AIN_FEC_TXD2,
+        PD3_AIN_FEC_TXD3,
+        PD4_AOUT_FEC_RX_ER,
+        PD5_AOUT_FEC_RXD1,
+        PD6_AOUT_FEC_RXD2,
+        PD7_AOUT_FEC_RXD3,
+        PD8_AF_FEC_MDIO,
+        PD9_AIN_FEC_MDC,
+        PD10_AOUT_FEC_CRS,
+        PD11_AOUT_FEC_TX_CLK,
+        PD12_AOUT_FEC_RXD0,
+        PD13_AOUT_FEC_RX_DV,
+        PD14_AOUT_FEC_RX_CLK,
+        PD15_AOUT_FEC_COL,
+        PD16_AIN_FEC_TX_ER,
+        PF23_AIN_FEC_TX_EN,
+        /* SSI1 */
+        PC20_PF_SSI1_FS,
+        PC21_PF_SSI1_RXD,
+        PC22_PF_SSI1_TXD,
+        PC23_PF_SSI1_CLK,
+        /* onboard I2C */
+        PC5_PF_I2C2_SDA,
+        PC6_PF_I2C2_SCL,
+        /* external I2C */
+        PD17_PF_I2C_DATA,
+        PD18_PF_I2C_CLK,
+        /* SPI1 */
+        PD25_PF_CSPI1_RDY,
+        PD29_PF_CSPI1_SCLK,
+        PD30_PF_CSPI1_MISO,
+        PD31_PF_CSPI1_MOSI,
+};
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct mxc_nand_platform_data pca100_nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+static struct platform_device *platform_devices[] __initdata = {
+        &mxc_w1_master_device,
+        &mxc_fec_device,
+};
+static struct imxi2c_platform_data pca100_i2c_1_data = {
+        .bitrate = 100000,
+};
+static struct at24_platform_data board_eeprom = {
+        .byte_len = 4096,
+        .page_size = 32,
+        .flags = AT24_FLAG_ADDR16,
+};
+static struct i2c_board_info pca100_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+                .platform_data = &board_eeprom,
+        }, {
+                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                .type = "pcf8563"
+        }, {
+                I2C_BOARD_INFO("lm75", 0x4a),
+                .type = "lm75"
+        }
+};
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+static struct spi_eeprom at25320 = {
+        .name           = "at25320an",
+        .byte_len       = 4096,
+        .page_size      = 32,
+        .flags          = EE_ADDR2,
+};
+static struct spi_board_info pca100_spi_board_info[] __initdata = {
+        {
+                .modalias = "at25",
+                .max_speed_hz = 30000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &at25320,
+        },
+};
+static int pca100_spi_cs[] = {GPIO_PORTD + 28, GPIO_PORTD + 27};
+static struct spi_imx_master pca100_spi_0_data = {
+        .chipselect     = pca100_spi_cs,
+        .num_chipselect = ARRAY_SIZE(pca100_spi_cs),
+};
+#endif
+static int pca100_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+                void *data)
+{
+        int ret;
+        ret = request_irq(IRQ_GPIOC(29), detect_irq,
+                          IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+                          "imx-mmc-detect", data);
+        if (ret)
+                printk(KERN_ERR
+                        "pca100: Failed to reuest irq for sd/mmc detection\n");
+        return ret;
+}
+static void pca100_sdhc2_exit(struct device *dev, void *data)
+{
+        free_irq(IRQ_GPIOC(29), data);
+}
+static struct imxmmc_platform_data sdhc_pdata = {
+        .init = pca100_sdhc2_init,
+        .exit = pca100_sdhc2_exit,
+};
+static void __init pca100_init(void)
+{
+        int ret;
+        ret = mxc_gpio_setup_multiple_pins(pca100_pins,
+                        ARRAY_SIZE(pca100_pins), "PCA100");
+        if (ret)
+                printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_gpio_mode(GPIO_PORTC | 29 | GPIO_GPIO | GPIO_IN);
+        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+        mxc_register_device(&mxc_nand_device, &pca100_nand_board_info);
+        /* only the i2c master 1 is used on this CPU card */
+        i2c_register_board_info(1, pca100_i2c_devices,
+                                ARRAY_SIZE(pca100_i2c_devices));
+        mxc_register_device(&mxc_i2c_device1, &pca100_i2c_1_data);
+        mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);
+        mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_OUT);
+        /* GPIO0_IRQ */
+        mxc_gpio_mode(GPIO_PORTC | 31 | GPIO_GPIO | GPIO_IN);
+        /* GPIO1_IRQ */
+        mxc_gpio_mode(GPIO_PORTC | 25 | GPIO_GPIO | GPIO_IN);
+        /* GPIO2_IRQ */
+        mxc_gpio_mode(GPIO_PORTE | 5 | GPIO_GPIO | GPIO_IN);
+#if defined(CONFIG_SPI_IMX) || defined(CONFIG_SPI_IMX_MODULE)
+        spi_register_board_info(pca100_spi_board_info,
+                                ARRAY_SIZE(pca100_spi_board_info));
+        mxc_register_device(&mxc_spi_device0, &pca100_spi_0_data);
+#endif
+        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+}
+static void __init pca100_timer_init(void)
+{
+        mx27_clocks_init(26000000);
+}
+static struct sys_timer pca100_timer = {
+        .init = pca100_timer_init,
+};
+MACHINE_START(PCA100, "phyCARD-i.MX27")
+        .phys_io        = AIPI_BASE_ADDR,
+        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx27_map_io,
+        .init_irq       = mxc_init_irq,
+        .init_machine   = pca100_init,
+        .timer          = &pca100_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm038.c b/arch/arm/mach-mx2/pcm038.c
index a4628d004343..ee65dda584cf 100644
--- a/arch/arm/mach-mx2/pcm038.c
+++ b/arch/arm/mach-mx2/pcm038.c
@@ -186,17 +186,13 @@ static struct at24_platform_data board_eeprom = {
 };
 static struct i2c_board_info pcm038_i2c_devices[] = {
-        [0] = {
+        {
                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                .platform_data = &board_eeprom,
-        },
+        }, {
-        [1] = {
+                I2C_BOARD_INFO("pcf8563", 0x51),
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+        }, {
-                .type = "pcf8563"
-        },
-        [2] = {
                I2C_BOARD_INFO("lm75", 0x4a),
-                .type = "lm75"
        }
 };
@@ -220,6 +216,9 @@ static void __init pcm038_init(void)
        mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
+        /* PE18 for user-LED D40 */
+        mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);
        platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 #ifdef CONFIG_MACH_PCM970_BASEBOARD
@@ -241,7 +240,7 @@ MACHINE_START(PCM038, "phyCORE-i.MX27")
        .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx27_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx27_init_irq,
        .init_machine   = pcm038_init,
        .timer          = &pcm038_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx2/pcm970-baseboard.c b/arch/arm/mach-mx2/pcm970-baseboard.c
index 6a3acaf57dd4..c261f59b0b4c 100644
--- a/arch/arm/mach-mx2/pcm970-baseboard.c
+++ b/arch/arm/mach-mx2/pcm970-baseboard.c
@@ -19,6 +19,7 @@
 #include <linux/gpio.h>
 #include <linux/irq.h>
 #include <linux/platform_device.h>
+#include <linux/can/platform/sja1000.h>
 #include <asm/mach/arch.h>
@@ -125,40 +126,96 @@ static struct imxmmc_platform_data sdhc_pdata = {
        .exit = pcm970_sdhc2_exit,
 };
-/*
+static struct imx_fb_videomode pcm970_modes[] = {
- * Connected is a portrait Sharp-QVGA display
+        {
- * of type: LQ035Q7DH06
+                .mode = {
- */
+                        .name           = "Sharp-LQ035Q7",
-static struct imx_fb_platform_data pcm038_fb_data = {
+                        .refresh        = 60,
-        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .xres           = 240,
-        .xres           = 240,
+                        .yres           = 320,
-        .yres           = 320,
+                        .pixclock       = 188679, /* in ps (5.3MHz) */
+                        .hsync_len      = 7,
-        .bpp            = 16,
+                        .left_margin    = 5,
-        .hsync_len      = 7,
+                        .right_margin   = 16,
-        .left_margin    = 5,
+                        .vsync_len      = 1,
-        .right_margin   = 16,
+                        .upper_margin   = 7,
+                        .lower_margin   = 9,
+                },
+                /*
+                 * - HSYNC active high
+                 * - VSYNC active high
+                 * - clk notenabled while idle
+                 * - clock not inverted
+                 * - data not inverted
+                 * - data enable low active
+                 * - enable sharp mode
+                 */
+                .pcr            = 0xF00080C0,
+                .bpp            = 16,
+        }, {
+                .mode = {
+                        .name           = "TX090",
+                        .refresh        = 60,
+                        .xres           = 240,
+                        .yres           = 320,
+                        .pixclock       = 38255,
+                        .left_margin    = 144,
+                        .right_margin   = 0,
+                        .upper_margin   = 7,
+                        .lower_margin   = 40,
+                        .hsync_len      = 96,
+                        .vsync_len      = 1,
+                },
+                /*
+                 * - HSYNC active low (1 << 22)
+                 * - VSYNC active low (1 << 23)
+                 * - clk notenabled while idle
+                 * - clock not inverted
+                 * - data not inverted
+                 * - data enable low active
+                 * - enable sharp mode
+                 */
+                .pcr = 0xF0008080 | (1<<22) | (1<<23) | (1<<19),
+                .bpp = 32,
+        },
+};
-        .vsync_len      = 1,
+static struct imx_fb_platform_data pcm038_fb_data = {
-        .upper_margin   = 7,
+        .mode = pcm970_modes,
-        .lower_margin   = 9,
+        .num_modes = ARRAY_SIZE(pcm970_modes),
-        .fixed_screen_cpu = 0,
-        /*
-         * - HSYNC active high
-         * - VSYNC active high
-         * - clk notenabled while idle
-         * - clock not inverted
-         * - data not inverted
-         * - data enable low active
-         * - enable sharp mode
-         */
-        .pcr            = 0xFA0080C0,
        .pwmr           = 0x00A903FF,
        .lscr1          = 0x00120300,
        .dmacr          = 0x00020010,
 };
+static struct resource pcm970_sja1000_resources[] = {
+        {
+                .start   = CS4_BASE_ADDR,
+                .end     = CS4_BASE_ADDR + 0x100 - 1,
+                .flags   = IORESOURCE_MEM,
+        }, {
+                .start   = IRQ_GPIOE(19),
+                .end     = IRQ_GPIOE(19),
+                .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+        .clock          = 16000000 / 2,
+        .ocr            = 0x40 | 0x18,
+        .cdr            = 0x40,
+};
+static struct platform_device pcm970_sja1000 = {
+        .name = "sja1000_platform",
+        .dev = {
+                .platform_data = &pcm970_sja1000_platform_data,
+        },
+        .resource = pcm970_sja1000_resources,
+        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
 /*
 * system init for baseboard usage. Will be called by pcm038 init.
 *
@@ -172,4 +229,5 @@ void __init pcm970_baseboard_init(void)
        mxc_register_device(&mxc_fb_device, &pcm038_fb_data);
        mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata);
+        platform_device_register(&pcm970_sja1000);
 }
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
new file mode 100644
index 000000000000..cc28f56eae80
--- /dev/null
+++ b/arch/arm/mach-mx25/Kconfig
@@ -0,0 +1,9 @@
+if ARCH_MX25
+comment "MX25 platforms:"
+config MACH_MX25_3DS
+        select ARCH_MXC_IOMUX_V3
+        bool "Support MX25PDK (3DS) Platform"
+endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
new file mode 100644
index 000000000000..fe23836a9f3d
--- /dev/null
+++ b/arch/arm/mach-mx25/Makefile
@@ -0,0 +1,3 @@
+obj-y                           := mm.o devices.o
+obj-$(CONFIG_ARCH_MX25)         += clock.o
+obj-$(CONFIG_MACH_MX25_3DS)     += mx25pdk.o
diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot
new file mode 100644
index 000000000000..e1dd366f836b
--- /dev/null
+++ b/arch/arm/mach-mx25/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x80008000
+params_phys-y   := 0x80000100
+initrd_phys-y   := 0x80800000
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
new file mode 100644
index 000000000000..ef26951a5275
--- /dev/null
+++ b/arch/arm/mach-mx25/clock.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <asm/clkdev.h>
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/mx25.h>
+#define CRM_BASE        MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
+#define CCM_MPCTL       0x00
+#define CCM_UPCTL       0x04
+#define CCM_CCTL        0x08
+#define CCM_CGCR0       0x0C
+#define CCM_CGCR1       0x10
+#define CCM_CGCR2       0x14
+#define CCM_PCDR0       0x18
+#define CCM_PCDR1       0x1C
+#define CCM_PCDR2       0x20
+#define CCM_PCDR3       0x24
+#define CCM_RCSR        0x28
+#define CCM_CRDR        0x2C
+#define CCM_DCVR0       0x30
+#define CCM_DCVR1       0x34
+#define CCM_DCVR2       0x38
+#define CCM_DCVR3       0x3c
+#define CCM_LTR0        0x40
+#define CCM_LTR1        0x44
+#define CCM_LTR2        0x48
+#define CCM_LTR3        0x4c
+static unsigned long get_rate_mpll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
+        return mxc_decode_pll(mpctl, 24000000);
+}
+static unsigned long get_rate_upll(void)
+{
+        ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
+        return mxc_decode_pll(mpctl, 24000000);
+}
+unsigned long get_rate_arm(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        unsigned long rate = get_rate_mpll();
+        if (cctl & (1 << 14))
+                rate = (rate * 3) >> 1;
+        return rate / ((cctl >> 30) + 1);
+}
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+        unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
+        return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
+}
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+        return get_rate_ahb(NULL) >> 1;
+}
+static unsigned long get_rate_per(int per)
+{
+        unsigned long ofs = (per & 0x3) * 8;
+        unsigned long reg = per & ~0x3;
+        unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
+        unsigned long fref;
+        if (readl(CRM_BASE + 0x64) & (1 << per))
+                fref = get_rate_upll();
+        else
+                fref = get_rate_ipg(NULL);
+        return fref / (val + 1);
+}
+static unsigned long get_rate_uart(struct clk *clk)
+{
+        return get_rate_per(15);
+}
+static unsigned long get_rate_i2c(struct clk *clk)
+{
+        return get_rate_per(6);
+}
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+        return get_rate_per(8);
+}
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        return 48000000; /* FIXME */
+}
+static int clk_cgcr_enable(struct clk *clk)
+{
+        u32 reg;
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+        return 0;
+}
+static void clk_cgcr_disable(struct clk *clk)
+{
+        u32 reg;
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+#define DEFINE_CLOCK(name, i, er, es, gr, sr)           \
+        static struct clk name = {                      \
+                .id             = i,                    \
+                .enable_reg     = CRM_BASE + er,        \
+                .enable_shift   = es,                   \
+                .get_rate       = gr,                   \
+                .set_rate       = sr,                   \
+                .enable         = clk_cgcr_enable,      \
+                .disable        = clk_cgcr_disable,     \
+        }
+DEFINE_CLOCK(gpt_clk,    0, CCM_CGCR0,  5, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk,  0, CCM_CGCR1,  5, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk,  0, CCM_CGCR1,  6, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi3_clk,  0, CCM_CGCR1,  7, get_rate_ipg, NULL);
+DEFINE_CLOCK(uart1_clk,  0, CCM_CGCR2, 14, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk,  0, CCM_CGCR2, 15, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk,  0, CCM_CGCR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart4_clk,  0, CCM_CGCR2, 17, get_rate_uart, NULL);
+DEFINE_CLOCK(uart5_clk,  0, CCM_CGCR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(nfc_clk,    0, CCM_CGCR0,  8, get_rate_nfc, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL);
+DEFINE_CLOCK(pwm1_clk,   0, CCM_CGCR1, 31, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm2_clk,   0, CCM_CGCR2,  0, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm3_clk,   0, CCM_CGCR2,  1, get_rate_ipg, NULL);
+DEFINE_CLOCK(pwm4_clk,   0, CCM_CGCR2,  2, get_rate_ipg, NULL);
+DEFINE_CLOCK(kpp_clk,    0, CCM_CGCR1, 28, get_rate_ipg, NULL);
+DEFINE_CLOCK(tsc_clk,    0, CCM_CGCR2, 13, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c_clk,    0, CCM_CGCR0,  6, get_rate_i2c, NULL);
+#define _REGISTER_CLOCK(d, n, c)        \
+        {                               \
+                .dev_id = d,            \
+                .con_id = n,            \
+                .clk = &c,              \
+        },
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+        _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+        _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+        _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
+        _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
+        _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
+        _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
+        _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
+        _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
+        _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
+        _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
+};
+int __init mx25_clocks_init(unsigned long fref)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+        mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
+        return 0;
+}
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
new file mode 100644
index 000000000000..eb12de1da42d
--- /dev/null
+++ b/arch/arm/mach-mx25/devices.c
@@ -0,0 +1,402 @@
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <mach/mx25.h>
+#include <mach/irqs.h>
+static struct resource uart0[] = {
+        {
+                .start = 0x43f90000,
+                .end = 0x43f93fff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 45,
+                .end = 45,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+static struct resource uart1[] = {
+        {
+                .start = 0x43f94000,
+                .end = 0x43f97fff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 32,
+                .end = 32,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+static struct resource uart2[] = {
+        {
+                .start = 0x5000c000,
+                .end = 0x5000ffff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 18,
+                .end = 18,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+static struct resource uart3[] = {
+        {
+                .start = 0x50008000,
+                .end = 0x5000bfff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 5,
+                .end = 5,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device3 = {
+        .name = "imx-uart",
+        .id = 3,
+        .resource = uart3,
+        .num_resources = ARRAY_SIZE(uart3),
+};
+static struct resource uart4[] = {
+        {
+                .start = 0x5002c000,
+                .end = 0x5002ffff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 40,
+                .end = 40,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device4 = {
+        .name = "imx-uart",
+        .id = 4,
+        .resource = uart4,
+        .num_resources = ARRAY_SIZE(uart4),
+};
+#define MX25_OTG_BASE_ADDR 0x53FF4000
+static u64 otg_dmamask = DMA_BIT_MASK(32);
+static struct resource mxc_otg_resources[] = {
+        {
+                .start = MX25_OTG_BASE_ADDR,
+                .end = MX25_OTG_BASE_ADDR + 0x1ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 37,
+                .end = 37,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_otg = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = mxc_otg_resources,
+        .num_resources = ARRAY_SIZE(mxc_otg_resources),
+};
+/* OTG gadget device */
+struct platform_device otg_udc_device = {
+        .name = "fsl-usb2-udc",
+        .id   = -1,
+        .dev  = {
+                .dma_mask          = &otg_dmamask,
+                .coherent_dma_mask = 0xffffffff,
+        },
+        .resource = mxc_otg_resources,
+        .num_resources = ARRAY_SIZE(mxc_otg_resources),
+};
+static u64 usbh2_dmamask = DMA_BIT_MASK(32);
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = MX25_OTG_BASE_ADDR + 0x400,
+                .end = MX25_OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = 35,
+                .end = 35,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+static struct resource mxc_spi_resources0[] = {
+        {
+               .start = 0x43fa4000,
+               .end = 0x43fa7fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 14,
+               .end = 14,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_spi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources0),
+        .resource = mxc_spi_resources0,
+};
+static struct resource mxc_spi_resources1[] = {
+        {
+               .start = 0x50010000,
+               .end = 0x50013fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 13,
+               .end = 13,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources1),
+        .resource = mxc_spi_resources1,
+};
+static struct resource mxc_spi_resources2[] = {
+        {
+               .start = 0x50004000,
+               .end = 0x50007fff,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = 0,
+               .end = 0,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_spi_resources2),
+        .resource = mxc_spi_resources2,
+};
+static struct resource mxc_pwm_resources0[] = {
+        {
+                .start  = 0x53fe0000,
+                .end    = 0x53fe3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 26,
+                .end     = 26,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_pwm_device0 = {
+        .name = "mxc_pwm",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources0),
+        .resource = mxc_pwm_resources0,
+};
+static struct resource mxc_pwm_resources1[] = {
+        {
+                .start  = 0x53fa0000,
+                .end    = 0x53fa3fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 36,
+                .end     = 36,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_pwm_device1 = {
+        .name = "mxc_pwm",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources1),
+        .resource = mxc_pwm_resources1,
+};
+static struct resource mxc_pwm_resources2[] = {
+        {
+                .start  = 0x53fa8000,
+                .end    = 0x53fabfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 41,
+                .end     = 41,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_pwm_device2 = {
+        .name = "mxc_pwm",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources2),
+        .resource = mxc_pwm_resources2,
+};
+static struct resource mxc_keypad_resources[] = {
+        {
+                .start  = 0x43fa8000,
+                .end    = 0x43fabfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 24,
+                .end     = 24,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_keypad_device = {
+        .name = "mxc-keypad",
+        .id = -1,
+        .num_resources = ARRAY_SIZE(mxc_keypad_resources),
+        .resource = mxc_keypad_resources,
+};
+static struct resource mxc_pwm_resources3[] = {
+        {
+                .start  = 0x53fc8000,
+                .end    = 0x53fcbfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start   = 42,
+                .end     = 42,
+                .flags   = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_pwm_device3 = {
+        .name = "mxc_pwm",
+        .id = 3,
+        .num_resources = ARRAY_SIZE(mxc_pwm_resources3),
+        .resource = mxc_pwm_resources3,
+};
+static struct resource mxc_i2c_1_resources[] = {
+        {
+                .start  = 0x43f80000,
+                .end    = 0x43f83fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 3,
+                .end    = 3,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_i2c_device0 = {
+        .name = "imx-i2c",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_i2c_1_resources),
+        .resource = mxc_i2c_1_resources,
+};
+static struct resource mxc_i2c_2_resources[] = {
+        {
+                .start  = 0x43f98000,
+                .end    = 0x43f9bfff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 4,
+                .end    = 4,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_i2c_device1 = {
+        .name = "imx-i2c",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_i2c_2_resources),
+        .resource = mxc_i2c_2_resources,
+};
+static struct resource mxc_i2c_3_resources[] = {
+        {
+                .start  = 0x43f84000,
+                .end    = 0x43f87fff,
+                .flags  = IORESOURCE_MEM,
+        }, {
+                .start  = 10,
+                .end    = 10,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+struct platform_device mxc_i2c_device2 = {
+        .name = "imx-i2c",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(mxc_i2c_3_resources),
+        .resource = mxc_i2c_3_resources,
+};
+static struct mxc_gpio_port imx_gpio_ports[] = {
+        {
+                .chip.label = "gpio-0",
+                .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
+                .irq = 52,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        }, {
+                .chip.label = "gpio-1",
+                .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
+                .irq = 51,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        }, {
+                .chip.label = "gpio-2",
+                .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
+                .irq = 16,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        }, {
+                .chip.label = "gpio-3",
+                .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
+                .irq = 23,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+        }
+};
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
+}
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
new file mode 100644
index 000000000000..fe6bf88ad1dd
--- /dev/null
+++ b/arch/arm/mach-mx25/devices.h
@@ -0,0 +1,19 @@
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+extern struct platform_device mxc_uart_device3;
+extern struct platform_device mxc_uart_device4;
+extern struct platform_device mxc_otg;
+extern struct platform_device otg_udc_device;
+extern struct platform_device mxc_usbh2;
+extern struct platform_device mxc_spi_device0;
+extern struct platform_device mxc_spi_device1;
+extern struct platform_device mxc_spi_device2;
+extern struct platform_device mxc_pwm_device0;
+extern struct platform_device mxc_pwm_device1;
+extern struct platform_device mxc_pwm_device2;
+extern struct platform_device mxc_pwm_device3;
+extern struct platform_device mxc_keypad_device;
+extern struct platform_device mxc_i2c_device0;
+extern struct platform_device mxc_i2c_device1;
+extern struct platform_device mxc_i2c_device2;
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-mx25/mm.c
new file mode 100644
index 000000000000..a7e587ff3e9e
--- /dev/null
+++ b/arch/arm/mach-mx25/mm.c
@@ -0,0 +1,76 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/mx25.h>
+#include <mach/iomux-v3.h>
+/*
+ * This table defines static virtual address mappings for I/O regions.
+ * These are the mappings common across all MX3 boards.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = MX25_AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AVIC_BASE_ADDR),
+                .length         = MX25_AVIC_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = MX25_AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
+                .length         = MX25_AIPS1_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        }, {
+                .virtual        = MX25_AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
+                .length         = MX25_AIPS2_SIZE,
+                .type           = MT_DEVICE_NONSHARED
+        },
+};
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx25_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MX25);
+        mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+void __init mx25_init_irq(void)
+{
+        mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT);
+}
diff --git a/arch/arm/mach-mx25/mx25pdk.c b/arch/arm/mach-mx25/mx25pdk.c
new file mode 100644
index 000000000000..92aa4fd19d99
--- /dev/null
+++ b/arch/arm/mach-mx25/mx25pdk.c
@@ -0,0 +1,58 @@
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/platform_device.h>
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/imx-uart.h>
+#include <mach/mx25.h>
+#include <mach/mxc_nand.h>
+#include "devices.h"
+#include <mach/iomux-v3.h>
+static struct imxuart_platform_data uart_pdata = {
+        .flags = IMXUART_HAVE_RTSCTS,
+};
+static struct mxc_nand_platform_data nand_board_info = {
+        .width = 1,
+        .hw_ecc = 1,
+};
+static void __init mx25pdk_init(void)
+{
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_usbh2, NULL);
+        mxc_register_device(&mxc_nand_device, &nand_board_info);
+}
+static void __init mx25pdk_timer_init(void)
+{
+        mx25_clocks_init(26000000);
+}
+static struct sys_timer mx25pdk_timer = {
+        .init   = mx25pdk_timer_init,
+};
+MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
+        /* Maintainer: Freescale Semiconductor, Inc. */
+        .phys_io        = MX25_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MX25_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mx25_map_io,
+        .init_irq       = mx25_init_irq,
+        .init_machine   = mx25pdk_init,
+        .timer          = &mx25pdk_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx3/armadillo5x0.c b/arch/arm/mach-mx3/armadillo5x0.c
index ee331fd6b1bd..776c0ee1b3cd 100644
--- a/arch/arm/mach-mx3/armadillo5x0.c
+++ b/arch/arm/mach-mx3/armadillo5x0.c
@@ -352,7 +352,7 @@ MACHINE_START(ARMADILLO5X0, "Armadillo-500")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x00000100,
        .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
        .timer          = &armadillo5x0_timer,
        .init_machine   = armadillo5x0_init,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 577ee83d1f60..fe5c4217322e 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -273,6 +273,19 @@ static unsigned long get_rate_csi(struct clk *clk)
        return rate / get_3_3_div((pdr2 >> 16) & 0x3f);
 }
+static unsigned long get_rate_otg(struct clk *clk)
+{
+        unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+        unsigned long rate;
+        if (pdr4 & (1 << 9))
+                rate = get_rate_arm();
+        else
+                rate = get_rate_ppll();
+        return rate / get_3_3_div((pdr4 >> 22) & 0x3f);
+}
 static unsigned long get_rate_ipg_per(struct clk *clk)
 {
        unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
@@ -365,7 +378,7 @@ DEFINE_CLOCK(ssi2_clk,   1, CCM_CGR2, 14, get_rate_ssi, NULL);
 DEFINE_CLOCK(uart1_clk,  0, CCM_CGR2, 16, get_rate_uart, NULL);
 DEFINE_CLOCK(uart2_clk,  1, CCM_CGR2, 18, get_rate_uart, NULL);
 DEFINE_CLOCK(uart3_clk,  2, CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, NULL, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
 DEFINE_CLOCK(wdog_clk,   0, CCM_CGR2, 24, NULL, NULL);
 DEFINE_CLOCK(max_clk,    0, CCM_CGR2, 26, NULL, NULL);
 DEFINE_CLOCK(admux_clk,  0, CCM_CGR2, 30, NULL, NULL);
@@ -426,7 +439,10 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
        _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
        _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
-        _REGISTER_CLOCK(NULL, "usbotg", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
        _REGISTER_CLOCK("mxc_wdt.0", NULL, wdog_clk)
        _REGISTER_CLOCK(NULL, "max", max_clk)
        _REGISTER_CLOCK(NULL, "admux", admux_clk)
@@ -456,7 +472,7 @@ int __init mx35_clocks_init()
        __raw_writel((3 << 26) | ll, CCM_BASE + CCM_CGR2);
        __raw_writel(0, CCM_BASE + CCM_CGR3);
-        mxc_timer_init(&gpt_clk);
+        mxc_timer_init(&gpt_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
        return 0;
 }
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index 8b14239724c9..06bd6180bfc3 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -29,6 +29,7 @@
 #include <mach/clock.h>
 #include <mach/hardware.h>
+#include <mach/mx31.h>
 #include <mach/common.h>
 #include "crm_regs.h"
@@ -402,6 +403,11 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
        return ckih_rate;
 }
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
 static struct clk ckih_clk = {
        .get_rate = clk_ckih_get_rate,
 };
@@ -508,6 +514,7 @@ DEFINE_CLOCK(usb_clk1,    0, NULL,          0, usb_get_rate, NULL, &usb_pll_clk)
 DEFINE_CLOCK(nfc_clk,     0, NULL,          0, nfc_get_rate, NULL, &ahb_clk);
 DEFINE_CLOCK(scc_clk,     0, NULL,          0, NULL, NULL, &ipg_clk);
 DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(ckil_clk,    0, NULL,          0, clk_ckil_get_rate, NULL, NULL);
 #define _REGISTER_CLOCK(d, n, c) \
        { \
@@ -518,9 +525,9 @@ DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
 static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "emi", emi_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-        _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
+        _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
        _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
        _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
        _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
@@ -531,6 +538,12 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
        _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
        _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
+        _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
        _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
        _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
@@ -559,6 +572,7 @@ static struct clk_lookup lookups[] = {
        _REGISTER_CLOCK(NULL, "iim", iim_clk)
        _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
        _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
+        _REGISTER_CLOCK("mxc_rtc", NULL, ckil_clk)
 };
 int __init mx31_clocks_init(unsigned long fref)
@@ -609,7 +623,7 @@ int __init mx31_clocks_init(unsigned long fref)
                __raw_writel(reg, MXC_CCM_PMCR1);
        }
-        mxc_timer_init(&ipg_clk);
+        mxc_timer_init(&ipg_clk, IO_ADDRESS(GPT1_BASE_ADDR), MXC_INT_GPT);
        return 0;
 }
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index 9e87e08fb121..8a577f367250 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -129,19 +129,17 @@ struct platform_device mxc_uart_device4 = {
 /* GPIO port description */
 static struct mxc_gpio_port imx_gpio_ports[] = {
-        [0] = {
+        {
                .chip.label = "gpio-0",
                .base = IO_ADDRESS(GPIO1_BASE_ADDR),
                .irq = MXC_INT_GPIO1,
                .virtual_irq_start = MXC_GPIO_IRQ_START,
-        },
+        }, {
-        [1] = {
                .chip.label = "gpio-1",
                .base = IO_ADDRESS(GPIO2_BASE_ADDR),
                .irq = MXC_INT_GPIO2,
                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
-        },
+        }, {
-        [2] = {
                .chip.label = "gpio-2",
                .base = IO_ADDRESS(GPIO3_BASE_ADDR),
                .irq = MXC_INT_GPIO3,
@@ -173,11 +171,11 @@ static struct resource mxc_nand_resources[] = {
        {
                .start  = 0, /* runtime dependent */
                .end    = 0,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
        }, {
                .start  = MXC_INT_NANDFC,
                .end    = MXC_INT_NANDFC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -193,8 +191,7 @@ static struct resource mxc_i2c0_resources[] = {
                .start = I2C_BASE_ADDR,
                .end = I2C_BASE_ADDR + SZ_4K - 1,
                .flags = IORESOURCE_MEM,
-        },
+        }, {
-        {
                .start = MXC_INT_I2C,
                .end = MXC_INT_I2C,
                .flags = IORESOURCE_IRQ,
@@ -213,8 +210,7 @@ static struct resource mxc_i2c1_resources[] = {
                .start = I2C2_BASE_ADDR,
                .end = I2C2_BASE_ADDR + SZ_4K - 1,
                .flags = IORESOURCE_MEM,
-        },
+        }, {
-        {
                .start = MXC_INT_I2C2,
                .end = MXC_INT_I2C2,
                .flags = IORESOURCE_IRQ,
@@ -233,8 +229,7 @@ static struct resource mxc_i2c2_resources[] = {
                .start = I2C3_BASE_ADDR,
                .end = I2C3_BASE_ADDR + SZ_4K - 1,
                .flags = IORESOURCE_MEM,
-        },
+        }, {
-        {
                .start = MXC_INT_I2C3,
                .end = MXC_INT_I2C3,
                .flags = IORESOURCE_IRQ,
@@ -371,8 +366,8 @@ struct platform_device mx3_camera = {
 static struct resource otg_resources[] = {
        {
-                .start  = OTG_BASE_ADDR,
+                .start  = MX31_OTG_BASE_ADDR,
-                .end    = OTG_BASE_ADDR + 0x1ff,
+                .end    = MX31_OTG_BASE_ADDR + 0x1ff,
                .flags  = IORESOURCE_MEM,
        }, {
                .start  = MXC_INT_USB3,
@@ -395,16 +390,142 @@ struct platform_device mxc_otg_udc_device = {
        .num_resources  = ARRAY_SIZE(otg_resources),
 };
+/* OTG host */
+struct platform_device mxc_otg_host = {
+        .name = "mxc-ehci",
+        .id = 0,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &otg_dmamask,
+        },
+        .resource = otg_resources,
+        .num_resources = ARRAY_SIZE(otg_resources),
+};
+/* USB host 1 */
+static u64 usbh1_dmamask = ~(u32)0;
+static struct resource mxc_usbh1_resources[] = {
+        {
+                .start = MX31_OTG_BASE_ADDR + 0x200,
+                .end = MX31_OTG_BASE_ADDR + 0x3ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB1,
+                .end = MXC_INT_USB1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_usbh1 = {
+        .name = "mxc-ehci",
+        .id = 1,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh1_dmamask,
+        },
+        .resource = mxc_usbh1_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
+};
+/* USB host 2 */
+static u64 usbh2_dmamask = ~(u32)0;
+static struct resource mxc_usbh2_resources[] = {
+        {
+                .start = MX31_OTG_BASE_ADDR + 0x400,
+                .end = MX31_OTG_BASE_ADDR + 0x5ff,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_USB2,
+                .end = MXC_INT_USB2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_usbh2 = {
+        .name = "mxc-ehci",
+        .id = 2,
+        .dev = {
+                .coherent_dma_mask = 0xffffffff,
+                .dma_mask = &usbh2_dmamask,
+        },
+        .resource = mxc_usbh2_resources,
+        .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
+};
+/*
+ * SPI master controller
+ * 3 channels
+ */
+static struct resource imx_spi_0_resources[] = {
+        {
+               .start = CSPI1_BASE_ADDR,
+               .end = CSPI1_BASE_ADDR + SZ_4K - 1,
+               .flags = IORESOURCE_MEM,
+        }, {
+               .start = MXC_INT_CSPI1,
+               .end = MXC_INT_CSPI1,
+               .flags = IORESOURCE_IRQ,
+        },
+};
+static struct resource imx_spi_1_resources[] = {
+        {
+                .start = CSPI2_BASE_ADDR,
+                .end = CSPI2_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI2,
+                .end = MXC_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct resource imx_spi_2_resources[] = {
+        {
+                .start = CSPI3_BASE_ADDR,
+                .end = CSPI3_BASE_ADDR + SZ_4K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC_INT_CSPI3,
+                .end = MXC_INT_CSPI3,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device imx_spi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(imx_spi_0_resources),
+        .resource = imx_spi_0_resources,
+};
+struct platform_device imx_spi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(imx_spi_1_resources),
+        .resource = imx_spi_1_resources,
+};
+struct platform_device imx_spi_device2 = {
+        .name = "spi_imx",
+        .id = 2,
+        .num_resources = ARRAY_SIZE(imx_spi_2_resources),
+        .resource = imx_spi_2_resources,
+};
 #ifdef CONFIG_ARCH_MX35
 static struct resource mxc_fec_resources[] = {
        {
                .start  = MXC_FEC_BASE_ADDR,
                .end    = MXC_FEC_BASE_ADDR + 0xfff,
-                .flags  = IORESOURCE_MEM
+                .flags  = IORESOURCE_MEM,
        }, {
                .start  = MXC_INT_FEC,
                .end    = MXC_INT_FEC,
-                .flags  = IORESOURCE_IRQ
+                .flags  = IORESOURCE_IRQ,
        },
 };
@@ -426,6 +547,14 @@ static int mx3_devices_init(void)
        if (cpu_is_mx35()) {
                mxc_nand_resources[0].start = MX35_NFC_BASE_ADDR;
                mxc_nand_resources[0].end = MX35_NFC_BASE_ADDR + 0xfff;
+                otg_resources[0].start = MX35_OTG_BASE_ADDR;
+                otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
+                otg_resources[1].start = MXC_INT_USBOTG;
+                otg_resources[1].end = MXC_INT_USBOTG;
+                mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
+                mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
+                mxc_usbh1_resources[1].start = MXC_INT_USBHS;
+                mxc_usbh1_resources[1].end = MXC_INT_USBHS;
        }
        return 0;
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index ffd494ddd4ac..79f2be45d139 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -16,5 +16,11 @@ extern struct platform_device mxc_fec_device;
 extern struct platform_device mxcsdhc_device0;
 extern struct platform_device mxcsdhc_device1;
 extern struct platform_device mxc_otg_udc_device;
+extern struct platform_device mxc_otg_host;
+extern struct platform_device mxc_usbh1;
+extern struct platform_device mxc_usbh2;
 extern struct platform_device mxc_rnga_device;
+extern struct platform_device imx_spi_device0;
+extern struct platform_device imx_spi_device1;
+extern struct platform_device imx_spi_device2;
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index 1f5fdd456cb9..ad5a1122d765 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -30,6 +30,7 @@
 #include <mach/common.h>
 #include <mach/hardware.h>
+#include <mach/iomux-v3.h>
 /*!
 * @file mm.c
@@ -75,6 +76,7 @@ static struct map_desc mxc_io_desc[] __initdata = {
 void __init mx31_map_io(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX31);
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
@@ -82,10 +84,22 @@ void __init mx31_map_io(void)
 void __init mx35_map_io(void)
 {
        mxc_set_cpu_type(MXC_CPU_MX35);
+        mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
+        mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
 }
+void __init mx31_init_irq(void)
+{
+        mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
+}
+void __init mx35_init_irq(void)
+{
+        mx31_init_irq();
+}
 #ifdef CONFIG_CACHE_L2X0
 static int mxc_init_l2x0(void)
 {
diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c
index 30e2767a78ae..0497c152be18 100644
--- a/arch/arm/mach-mx3/mx31ads.c
+++ b/arch/arm/mach-mx3/mx31ads.c
@@ -517,7 +517,7 @@ static void __init mx31ads_map_io(void)
 static void __init mx31ads_init_irq(void)
 {
-        mxc_init_irq();
+        mx31_init_irq();
        mx31ads_init_expio();
 }
diff --git a/arch/arm/mach-mx3/mx31lilly.c b/arch/arm/mach-mx3/mx31lilly.c
index 6ab2f163cb95..423025150f6f 100644
--- a/arch/arm/mach-mx3/mx31lilly.c
+++ b/arch/arm/mach-mx3/mx31lilly.c
@@ -148,7 +148,7 @@ MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
        .init_machine   = mx31lilly_board_init,
        .timer          = &mx31lilly_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31lite.c b/arch/arm/mach-mx3/mx31lite.c
index 86fe70fa3e13..a8d57decdfdb 100644
--- a/arch/arm/mach-mx3/mx31lite.c
+++ b/arch/arm/mach-mx3/mx31lite.c
@@ -71,12 +71,11 @@ static struct smsc911x_platform_config smsc911x_config = {
 };
 static struct resource smsc911x_resources[] = {
-        [0] = {
+        {
                .start          = CS4_BASE_ADDR,
                .end            = CS4_BASE_ADDR + 0x100,
                .flags          = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start          = IOMUX_TO_IRQ(MX31_PIN_SFS6),
                .end            = IOMUX_TO_IRQ(MX31_PIN_SFS6),
                .flags          = IORESOURCE_IRQ,
@@ -162,7 +161,7 @@ MACHINE_START(MX31LITE, "LogicPD MX31 LITEKIT")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx31lite_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &mx31lite_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index b48581e7dedd..5592cdb8d0ad 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -16,7 +16,6 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -40,18 +39,6 @@ static unsigned int devboard_pins[] = {
        MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
        MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
        MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
-        /* USB OTG */
-        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
-        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
-        MX31_PIN_USB_OC__GPIO1_30,
 };
 static struct imxuart_platform_data uart_pdata = {
@@ -111,33 +98,6 @@ static struct imxmmc_platform_data sdhc2_pdata = {
        .exit   = devboard_sdhc2_exit,
 };
-static struct fsl_usb2_platform_data usb_pdata = {
-        .operating_mode = FSL_USB2_DR_DEVICE,
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
-static void devboard_usbotg_init(void)
-{
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
-        gpio_request(OTG_EN_B, "usb-udc-en");
-        gpio_direction_output(OTG_EN_B, 0);
-}
 /*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
@@ -151,7 +111,4 @@ void __init mx31moboard_devboard_init(void)
        mxc_register_device(&mxc_uart_device1, &uart_pdata);
        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
-        devboard_usbotg_init();
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 901fb0166c0e..2bfaffb344f0 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -16,7 +16,6 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
-#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
@@ -48,18 +47,8 @@ static unsigned int marxbot_pins[] = {
        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
        MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
        MX31_PIN_TXD2__GPIO1_28,
-        /* USB OTG */
+        /* dsPIC resets */
-        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
-        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
-        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
-        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
-        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
-        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
-        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
-        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
-        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
-        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
-        MX31_PIN_USB_OC__GPIO1_30,
 };
 #define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
@@ -115,31 +104,20 @@ static struct imxmmc_platform_data sdhc2_pdata = {
        .exit   = marxbot_sdhc2_exit,
 };
-static struct fsl_usb2_platform_data usb_pdata = {
+#define TRSLAT_RST_B    IOMUX_TO_GPIO(MX31_PIN_STXD5)
-        .operating_mode = FSL_USB2_DR_DEVICE,
+#define DSPICS_RST_B    IOMUX_TO_GPIO(MX31_PIN_SRXD5)
-        .phy_mode       = FSL_USB2_PHY_ULPI,
-};
-#define OTG_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST)
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
-static void marxbot_usbotg_init(void)
+static void dspics_resets_init(void)
 {
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, OTG_PAD_CFG);
+        if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, OTG_PAD_CFG);
+                gpio_direction_output(TRSLAT_RST_B, 1);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, OTG_PAD_CFG);
+                gpio_export(TRSLAT_RST_B, false);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, OTG_PAD_CFG);
+        }
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, OTG_PAD_CFG);
+        if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, OTG_PAD_CFG);
+                gpio_direction_output(DSPICS_RST_B, 1);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, OTG_PAD_CFG);
+                gpio_export(DSPICS_RST_B, false);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, OTG_PAD_CFG);
+        }
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, OTG_PAD_CFG);
-        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, OTG_PAD_CFG);
-        gpio_request(OTG_EN_B, "usb-udc-en");
-        gpio_direction_output(OTG_EN_B, 0);
 }
 /*
@@ -152,8 +130,7 @@ void __init mx31moboard_marxbot_init(void)
        mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
                "marxbot");
-        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
+        dspics_resets_init();
-        marxbot_usbotg_init();
+        mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata);
-        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
 }
diff --git a/arch/arm/mach-mx3/mx31moboard.c b/arch/arm/mach-mx3/mx31moboard.c
index 2a2da4739ecf..9243de54041a 100644
--- a/arch/arm/mach-mx3/mx31moboard.c
+++ b/arch/arm/mach-mx3/mx31moboard.c
@@ -16,9 +16,12 @@
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
+#include <linux/delay.h>
+#include <linux/fsl_devices.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
 #include <linux/interrupt.h>
+#include <linux/leds.h>
 #include <linux/memory.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/partitions.h>
@@ -36,6 +39,7 @@
 #include <mach/iomux-mx3.h>
 #include <mach/i2c.h>
 #include <mach/mmc.h>
+#include <mach/mx31.h>
 #include "devices.h"
@@ -55,6 +59,26 @@ static unsigned int moboard_pins[] = {
        MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
        MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
        MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
+        /* USB reset */
+        MX31_PIN_GPIO1_0__GPIO1_0,
+        /* USB OTG */
+        MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+        MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+        MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+        MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+        MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+        MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+        MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+        MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+        MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+        MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
+        MX31_PIN_USB_OC__GPIO1_30,
+        /* LEDs */
+        MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
+        MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
+        /* SEL */
+        MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
+        MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
 };
 static struct physmap_flash_data mx31moboard_flash_data = {
@@ -142,8 +166,109 @@ static struct imxmmc_platform_data sdhc1_pdata = {
        .exit   = moboard_sdhc1_exit,
 };
+/*
+ * this pin is dedicated for all mx31moboard systems, so we do it here
+ */
+#define USB_RESET_B     IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
+static void usb_xcvr_reset(void)
+{
+        gpio_request(USB_RESET_B, "usb-reset");
+        gpio_direction_output(USB_RESET_B, 0);
+        mdelay(1);
+        gpio_set_value(USB_RESET_B, 1);
+}
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+                        PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+static void moboard_usbotg_init(void)
+{
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+        mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+        gpio_request(OTG_EN_B, "usb-udc-en");
+        gpio_direction_output(OTG_EN_B, 0);
+}
+static struct fsl_usb2_platform_data usb_pdata = {
+        .operating_mode = FSL_USB2_DR_DEVICE,
+        .phy_mode       = FSL_USB2_PHY_ULPI,
+};
+static struct gpio_led mx31moboard_leds[] = {
+        {
+                .name   = "coreboard-led-0:red:running",
+                .default_trigger = "heartbeat",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
+        }, {
+                .name   = "coreboard-led-1:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_STX0),
+        }, {
+                .name   = "coreboard-led-2:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SRX0),
+        }, {
+                .name   = "coreboard-led-3:red",
+                .gpio   = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
+        },
+};
+static struct gpio_led_platform_data mx31moboard_led_pdata = {
+        .num_leds       = ARRAY_SIZE(mx31moboard_leds),
+        .leds           = mx31moboard_leds,
+};
+static struct platform_device mx31moboard_leds_device = {
+        .name   = "leds-gpio",
+        .id     = -1,
+        .dev    = {
+                .platform_data = &mx31moboard_led_pdata,
+        },
+};
+#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
+#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
+#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
+#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
+static void mx31moboard_init_sel_gpios(void)
+{
+        if (!gpio_request(SEL0, "sel0")) {
+                gpio_direction_input(SEL0);
+                gpio_export(SEL0, true);
+        }
+        if (!gpio_request(SEL1, "sel1")) {
+                gpio_direction_input(SEL1);
+                gpio_export(SEL1, true);
+        }
+        if (!gpio_request(SEL2, "sel2")) {
+                gpio_direction_input(SEL2);
+                gpio_export(SEL2, true);
+        }
+        if (!gpio_request(SEL3, "sel3")) {
+                gpio_direction_input(SEL3);
+                gpio_export(SEL3, true);
+        }
+}
 static struct platform_device *devices[] __initdata = {
        &mx31moboard_flash,
+        &mx31moboard_leds_device,
 };
 static int mx31moboard_baseboard;
@@ -162,11 +287,18 @@ static void __init mxc_board_init(void)
        mxc_register_device(&mxc_uart_device0, &uart_pdata);
        mxc_register_device(&mxc_uart_device4, &uart_pdata);
+        mx31moboard_init_sel_gpios();
        mxc_register_device(&mxc_i2c_device0, &moboard_i2c0_pdata);
        mxc_register_device(&mxc_i2c_device1, &moboard_i2c1_pdata);
        mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata);
+        usb_xcvr_reset();
+        moboard_usbotg_init();
+        mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
        switch (mx31moboard_baseboard) {
        case MX31NOBOARD:
                break;
@@ -197,7 +329,7 @@ MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &mx31moboard_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx31pdk.c b/arch/arm/mach-mx3/mx31pdk.c
index c19838d2e369..0f7a2f06bc2d 100644
--- a/arch/arm/mach-mx3/mx31pdk.c
+++ b/arch/arm/mach-mx3/mx31pdk.c
@@ -265,7 +265,7 @@ MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx31pdk_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &mx31pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/mx35pdk.c b/arch/arm/mach-mx3/mx35pdk.c
index 6d15374414b9..6ff186e46ceb 100644
--- a/arch/arm/mach-mx3/mx35pdk.c
+++ b/arch/arm/mach-mx3/mx35pdk.c
@@ -98,7 +98,7 @@ MACHINE_START(MX35_3DS, "Freescale MX35PDK")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx35_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx35_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &mx35pdk_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm037.c b/arch/arm/mach-mx3/pcm037.c
index 840cfda341d0..6cbaabedf386 100644
--- a/arch/arm/mach-mx3/pcm037.c
+++ b/arch/arm/mach-mx3/pcm037.c
@@ -32,6 +32,7 @@
 #include <linux/spi/spi.h>
 #include <linux/irq.h>
 #include <linux/fsl_devices.h>
+#include <linux/can/platform/sja1000.h>
 #include <media/soc_camera.h>
@@ -169,6 +170,8 @@ static unsigned int pcm037_pins[] = {
        MX31_PIN_CSI_MCLK__CSI_MCLK,
        MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
        MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+        /* GPIO */
+        IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
 };
 static struct physmap_flash_data pcm037_flash_data = {
@@ -244,12 +247,11 @@ static struct imxuart_platform_data uart_pdata = {
 };
 static struct resource smsc911x_resources[] = {
-        [0] = {
+        {
                .start          = CS1_BASE_ADDR + 0x300,
                .end            = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
                .flags          = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start          = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                .end            = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
                .flags          = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
@@ -339,8 +341,7 @@ static struct i2c_board_info pcm037_i2c_devices[] = {
                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                .platform_data = &board_eeprom,
        }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                I2C_BOARD_INFO("pcf8563", 0x51),
-                .type = "pcf8563",
        }
 };
@@ -515,6 +516,33 @@ static struct mx3fb_platform_data mx3fb_pdata = {
        .num_modes      = ARRAY_SIZE(fb_modedb),
 };
+static struct resource pcm970_sja1000_resources[] = {
+        {
+                .start   = CS5_BASE_ADDR,
+                .end     = CS5_BASE_ADDR + 0x100 - 1,
+                .flags   = IORESOURCE_MEM,
+        }, {
+                .start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                .end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+                .flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+        },
+};
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+        .clock          = 16000000 / 2,
+        .ocr            = 0x40 | 0x18,
+        .cdr            = 0x40,
+};
+static struct platform_device pcm970_sja1000 = {
+        .name = "sja1000_platform",
+        .dev = {
+                .platform_data = &pcm970_sja1000_platform_data,
+        },
+        .resource = pcm970_sja1000_resources,
+        .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
 /*
 * Board specific initialization.
 */
@@ -575,6 +603,8 @@ static void __init mxc_board_init(void)
        if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
                mxc_register_device(&mx3_camera, &camera_pdata);
+        platform_device_register(&pcm970_sja1000);
 }
 static void __init pcm037_timer_init(void)
@@ -592,7 +622,7 @@ MACHINE_START(PCM037, "Phytec Phycore pcm037")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &pcm037_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/pcm043.c b/arch/arm/mach-mx3/pcm043.c
index 8d27c324abf2..e18a224671fa 100644
--- a/arch/arm/mach-mx3/pcm043.c
+++ b/arch/arm/mach-mx3/pcm043.c
@@ -133,8 +133,7 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
                I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
                .platform_data = &board_eeprom,
        }, {
-                I2C_BOARD_INFO("rtc-pcf8563", 0x51),
+                I2C_BOARD_INFO("pcf8563", 0x51),
-                .type = "pcf8563",
        }
 };
 #endif
@@ -203,7 +202,8 @@ static struct pad_desc pcm043_pads[] = {
        MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
        MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
        MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
-        MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
+        /* gpio */
+        MX35_PAD_ATA_CS0__GPIO2_6,
 };
 /*
@@ -245,7 +245,7 @@ MACHINE_START(PCM043, "Phytec Phycore pcm043")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx35_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx35_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &pcm043_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mx3/qong.c b/arch/arm/mach-mx3/qong.c
index 82b31c4ab11f..044511f1b9a9 100644
--- a/arch/arm/mach-mx3/qong.c
+++ b/arch/arm/mach-mx3/qong.c
@@ -81,13 +81,12 @@ static inline void mxc_init_imx_uart(void)
 }
 static struct resource dnet_resources[] = {
-        [0] = {
+        {
                .name   = "dnet-memory",
                .start  = QONG_DNET_BASEADDR,
                .end    = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
                .flags  = IORESOURCE_MEM,
-        },
+        }, {
-        [1] = {
                .start  = QONG_FPGA_IRQ,
                .end    = QONG_FPGA_IRQ,
                .flags  = IORESOURCE_IRQ,
@@ -280,7 +279,7 @@ MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
        .io_pg_offst    = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
        .boot_params    = PHYS_OFFSET + 0x100,
        .map_io         = mx31_map_io,
-        .init_irq       = mxc_init_irq,
+        .init_irq       = mx31_init_irq,
        .init_machine   = mxc_board_init,
        .timer          = &qong_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
new file mode 100644
index 000000000000..8e5fa38ebb67
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Kconfig
@@ -0,0 +1,11 @@
+if ARCH_MXC91231
+comment "MXC91231 platforms:"
+config MACH_MAGX_ZN5
+        bool "Support Motorola Zn5 GSM phone"
+        default n
+        help
+          Include support for Motorola Zn5 GSM phone.
+endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
new file mode 100644
index 000000000000..011d5e197125
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile
@@ -0,0 +1,2 @@
+obj-y   := mm.o clock.o devices.o system.o iomux.o
+obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
new file mode 100644
index 000000000000..9939a19d99a1
--- /dev/null
+++ b/arch/arm/mach-mxc91231/Makefile.boot
@@ -0,0 +1,3 @@
+   zreladdr-y   := 0x90008000
+params_phys-y   := 0x90000100
+initrd_phys-y   := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
new file mode 100644
index 000000000000..ecfa37fef8ad
--- /dev/null
+++ b/arch/arm/mach-mxc91231/clock.c
@@ -0,0 +1,642 @@
+#include <linux/clk.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/clkdev.h>
+#include <asm/bug.h>
+#include <asm/div64.h>
+#include "crm_regs.h"
+#define CRM_SMALL_DIVIDER(base, name) \
+        crm_small_divider(base, \
+                          base ## _ ## name ## _OFFSET, \
+                          base ## _ ## name ## _MASK)
+#define CRM_1DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 1)
+#define CRM_16DIVIDER(base, name) \
+        crm_divider(base, \
+                    base ## _ ## name ## _OFFSET, \
+                    base ## _ ## name ## _MASK, 16)
+static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
+{
+        static const u32 crm_small_dividers[] = {
+                2, 3, 4, 5, 6, 8, 10, 12
+        };
+        u8 idx;
+        idx = (__raw_readl(reg) & mask) >> offset;
+        if (idx > 7)
+                return 1;
+        return crm_small_dividers[idx];
+}
+static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
+{
+        u32 div;
+        div = (__raw_readl(reg) & mask) >> offset;
+        return div ? div : z;
+}
+static int _clk_1bit_enable(struct clk *clk)
+{
+        u32 reg;
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 1 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+        return 0;
+}
+static void _clk_1bit_disable(struct clk *clk)
+{
+        u32 reg;
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(1 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+static int _clk_3bit_enable(struct clk *clk)
+{
+        u32 reg;
+        reg = __raw_readl(clk->enable_reg);
+        reg |= 0x7 << clk->enable_shift;
+        __raw_writel(reg, clk->enable_reg);
+        return 0;
+}
+static void _clk_3bit_disable(struct clk *clk)
+{
+        u32 reg;
+        reg = __raw_readl(clk->enable_reg);
+        reg &= ~(0x7 << clk->enable_shift);
+        __raw_writel(reg, clk->enable_reg);
+}
+static unsigned long ckih_rate;
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+        return ckih_rate;
+}
+static struct clk ckih_clk = {
+        .get_rate = clk_ckih_get_rate,
+};
+static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
+{
+        return 2 * clk_get_rate(clk->parent);
+}
+static struct clk ckih_x2_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ckih_x2_get_rate,
+};
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+        return CKIL_CLK_FREQ;
+}
+static struct clk ckil_clk = {
+        .get_rate = clk_ckil_get_rate,
+};
+/* plls stuff */
+static struct clk mcu_pll_clk;
+static struct clk dsp_pll_clk;
+static struct clk usb_pll_clk;
+static struct clk *pll_clk(u8 sel)
+{
+        switch (sel) {
+        case 0:
+                return &mcu_pll_clk;
+        case 1:
+                return &dsp_pll_clk;
+        case 2:
+                return &usb_pll_clk;
+        }
+        BUG();
+}
+static void __iomem *pll_base(struct clk *clk)
+{
+        if (clk == &mcu_pll_clk)
+                return MXC_PLL0_BASE;
+        else if (clk == &dsp_pll_clk)
+                return MXC_PLL1_BASE;
+        else if (clk == &usb_pll_clk)
+                return MXC_PLL2_BASE;
+        BUG();
+}
+static unsigned long clk_pll_get_rate(struct clk *clk)
+{
+        const void __iomem *pllbase;
+        unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
+        long mfn, mfn_abs, mfd, pdf;
+        s64 temp;
+        pllbase = pll_base(clk);
+        pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
+        if (pll_hfsm == 0) {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
+        } else {
+                dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
+                dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
+                dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
+        }
+        pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
+        mfi = (mfi <= 5) ? 5 : mfi;
+        mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
+        mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
+        mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
+        if (mfn < 0)
+                mfn_abs = -mfn;
+        else
+                mfn_abs = mfn;
+/* XXX: actually this asumes that ckih is fed to pll, but spec says
+ * that ckih_x2 is also possible. need to check this out.
+ */
+        ref_clk = clk_get_rate(&ckih_clk);
+        ref_clk *= 2;
+        ref_clk /= pdf + 1;
+        temp = (u64) ref_clk * mfn_abs;
+        do_div(temp, mfd);
+        if (mfn < 0)
+                temp = -temp;
+        temp += ref_clk * mfi;
+        return temp;
+}
+static int clk_pll_enable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+        do {
+                reg = __raw_readl(ctl);
+        } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
+        return 0;
+}
+static void clk_pll_disable(struct clk *clk)
+{
+        void __iomem *ctl;
+        u32 reg;
+        ctl = pll_base(clk);
+        reg = __raw_readl(ctl);
+        reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
+        __raw_writel(reg, ctl);
+}
+static struct clk mcu_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+static struct clk dsp_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+static struct clk usb_pll_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_pll_get_rate,
+        .enable = clk_pll_enable,
+        .disable = clk_pll_disable,
+};
+/* plls stuff end */
+/* ap_ref_clk stuff */
+static struct clk ap_ref_clk;
+static unsigned long clk_ap_ref_get_rate(struct clk *clk)
+{
+        u32 ascsr, acsr;
+        u8 ap_pat_ref_div_2, ap_isel, acs, ads;
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        /* 0 for ckih, 1 for ckih*2 */
+        ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
+        /* reg divider */
+        ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
+        /* undocumented, 1 for disabling divider */
+        ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
+        /* 0 for pat_ref, 1 for divider out */
+        acs = acsr & MXC_CRMAP_ACSR_ACS;
+        if (acs & !ads)
+                /* use divided clock */
+                return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
+        return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
+}
+static struct clk ap_ref_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_ap_ref_get_rate,
+};
+/* ap_ref_clk stuff end */
+/* ap_pre_dfs_clk stuff */
+static struct clk ap_pre_dfs_clk;
+static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
+{
+        u32 acsr, ascsr;
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_APSEL_OFFSET;
+                return clk_get_rate(pll_clk(sel)) /
+                        CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
+        }
+        return clk_get_rate(&ap_ref_clk);
+}
+static struct clk ap_pre_dfs_clk = {
+        .get_rate = clk_ap_pre_dfs_get_rate,
+};
+/* ap_pre_dfs_clk stuff end */
+/* usb_clk stuff */
+static struct clk usb_clk;
+static struct clk *clk_usb_parent(struct clk *clk)
+{
+        u32 acsr, ascsr;
+        acsr = __raw_readl(MXC_CRMAP_ACSR);
+        ascsr = __raw_readl(MXC_CRMAP_ASCSR);
+        if (acsr & MXC_CRMAP_ACSR_ACS) {
+                u8 sel;
+                sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
+                        MXC_CRMAP_ASCSR_USBSEL_OFFSET;
+                return pll_clk(sel);
+        }
+        return &ap_ref_clk;
+}
+static unsigned long clk_usb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
+}
+static struct clk usb_clk = {
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
+        .get_rate = clk_usb_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* usb_clk stuff end */
+static unsigned long clk_ipg_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
+}
+static unsigned long clk_ahb_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
+}
+static struct clk ipg_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ipg_get_rate,
+};
+static struct clk ahb_clk = {
+        .parent = &ap_pre_dfs_clk,
+        .get_rate = clk_ahb_get_rate,
+};
+/* perclk_clk stuff */
+static struct clk perclk_clk;
+static unsigned long clk_perclk_get_rate(struct clk *clk)
+{
+        u32 acder2;
+        acder2 = __raw_readl(MXC_CRMAP_ACDER2);
+        if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
+                return 2 * clk_get_rate(clk->parent);
+        return clk_get_rate(clk->parent);
+}
+static struct clk perclk_clk = {
+        .parent = &ckih_clk,
+        .get_rate = clk_perclk_get_rate,
+};
+/* perclk_clk stuff end */
+/* uart_clk stuff */
+static struct clk uart_clk[];
+static unsigned long clk_uart_get_rate(struct clk *clk)
+{
+        u32 div;
+        switch (clk->id) {
+        case 0:
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
+                break;
+        case 2:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
+                break;
+        default:
+                BUG();
+        }
+        return clk_get_rate(clk->parent) / div;
+}
+static struct clk uart_clk[] = {
+        {
+                .id = 0,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 1,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        }, {
+                .id = 2,
+                .parent = &perclk_clk,
+                .enable_reg = MXC_CRMAP_APRA,
+                .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
+                .get_rate = clk_uart_get_rate,
+                .enable = _clk_1bit_enable,
+                .disable = _clk_1bit_disable,
+        },
+};
+/* uart_clk stuff end */
+/* sdhc_clk stuff */
+static struct clk nfc_clk;
+static unsigned long clk_nfc_get_rate(struct clk *clk)
+{
+        return clk_get_rate(clk->parent) /
+                CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
+}
+static struct clk nfc_clk = {
+        .parent = &ahb_clk,
+        .enable_reg = MXC_CRMAP_ACDER2,
+        .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
+        .get_rate = clk_nfc_get_rate,
+        .enable = _clk_1bit_enable,
+        .disable = _clk_1bit_disable,
+};
+/* sdhc_clk stuff end */
+/* sdhc_clk stuff */
+static struct clk sdhc_clk[];
+static struct clk *clk_sdhc_parent(struct clk *clk)
+{
+        u32 aprb;
+        u8 sel;
+        u32 mask;
+        int offset;
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
+                break;
+        case 1:
+                mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
+                offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
+                break;
+        default:
+                BUG();
+        }
+        sel = (aprb & mask) >> offset;
+        switch (sel) {
+        case 0:
+                return &ckih_clk;
+        case 1:
+                return &ckih_x2_clk;
+        }
+        return &usb_clk;
+}
+static unsigned long clk_sdhc_get_rate(struct clk *clk)
+{
+        u32 div;
+        switch (clk->id) {
+        case 0:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
+                break;
+        case 1:
+                div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
+                break;
+        default:
+                BUG();
+        }
+        return clk_get_rate(clk->parent) / div;
+}
+static int clk_sdhc_enable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+        return 0;
+}
+static void clk_sdhc_disable(struct clk *clk)
+{
+        u32 amlpmre1, aprb;
+        amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
+        aprb = __raw_readl(MXC_CRMAP_APRB);
+        switch (clk->id) {
+        case 0:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
+                break;
+        case 1:
+                amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
+                aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
+                break;
+        }
+        __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
+        __raw_writel(aprb, MXC_CRMAP_APRB);
+}
+static struct clk sdhc_clk[] = {
+        {
+                .id = 0,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        }, {
+                .id = 1,
+                .get_rate = clk_sdhc_get_rate,
+                .enable = clk_sdhc_enable,
+                .disable = clk_sdhc_disable,
+        },
+};
+/* sdhc_clk stuff end */
+/* wdog_clk stuff */
+static struct clk wdog_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRD,
+                .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* wdog_clk stuff end */
+/* gpt_clk stuff */
+static struct clk gpt_clk = {
+        .parent = &ipg_clk,
+        .enable_reg = MXC_CRMAP_AMLPMRC,
+        .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
+        .enable = _clk_3bit_enable,
+        .disable = _clk_3bit_disable,
+};
+/* gpt_clk stuff end */
+/* cspi_clk stuff */
+static struct clk cspi_clk[] = {
+        {
+                .id = 0,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE2,
+                .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        }, {
+                .id = 1,
+                .parent = &ipg_clk,
+                .enable_reg = MXC_CRMAP_AMLPMRE1,
+                .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
+                .enable = _clk_3bit_enable,
+                .disable = _clk_3bit_disable,
+        },
+};
+/* cspi_clk stuff end */
+#define _REGISTER_CLOCK(d, n, c) \
+        { \
+                .dev_id = d, \
+                .con_id = n, \
+                .clk = &c, \
+        },
+static struct clk_lookup lookups[] = {
+        _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
+        _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
+        _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
+        _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
+        _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
+        _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
+        _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
+        _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
+};
+int __init mxc91231_clocks_init(unsigned long fref)
+{
+        void __iomem *gpt_base;
+        int i;
+        ckih_rate = fref;
+        usb_clk.parent = clk_usb_parent(&usb_clk);
+        sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
+        sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
+        for (i = 0; i < ARRAY_SIZE(lookups); i++)
+                clkdev_add(&lookups[i]);
+        gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
+        mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
+        return 0;
+}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
new file mode 100644
index 000000000000..ce4f59058189
--- /dev/null
+++ b/arch/arm/mach-mxc91231/crm_regs.h
@@ -0,0 +1,399 @@
+/*
+ * Copyright 2006 Freescale Semiconductor, Inc.
+ * Copyright 2006-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
+#define CKIL_CLK_FREQ                   32768
+#define MXC_CRM_AP_BASE                 MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
+#define MXC_CRM_COM_BASE                MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
+#define MXC_DSM_BASE                    MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
+#define MXC_PLL0_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
+#define MXC_PLL1_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
+#define MXC_PLL2_BASE                   MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
+#define MXC_CLKCTL_BASE                 MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
+/* PLL Register Offsets */
+#define MXC_PLL_DP_CTL                  0x00
+#define MXC_PLL_DP_CONFIG               0x04
+#define MXC_PLL_DP_OP                   0x08
+#define MXC_PLL_DP_MFD                  0x0C
+#define MXC_PLL_DP_MFN                  0x10
+#define MXC_PLL_DP_HFS_OP               0x1C
+#define MXC_PLL_DP_HFS_MFD              0x20
+#define MXC_PLL_DP_HFS_MFN              0x24
+/* PLL Register Bit definitions */
+#define MXC_PLL_DP_CTL_DPDCK0_2_EN      0x1000
+#define MXC_PLL_DP_CTL_ADE              0x800
+#define MXC_PLL_DP_CTL_REF_CLK_DIV      0x400
+#define MXC_PLL_DP_CTL_HFSM             0x80
+#define MXC_PLL_DP_CTL_PRE              0x40
+#define MXC_PLL_DP_CTL_UPEN             0x20
+#define MXC_PLL_DP_CTL_RST              0x10
+#define MXC_PLL_DP_CTL_RCP              0x8
+#define MXC_PLL_DP_CTL_PLM              0x4
+#define MXC_PLL_DP_CTL_BRM0             0x2
+#define MXC_PLL_DP_CTL_LRF              0x1
+#define MXC_PLL_DP_OP_MFI_OFFSET        4
+#define MXC_PLL_DP_OP_MFI_MASK          0xF
+#define MXC_PLL_DP_OP_PDF_OFFSET        0
+#define MXC_PLL_DP_OP_PDF_MASK          0xF
+#define MXC_PLL_DP_MFD_OFFSET           0
+#define MXC_PLL_DP_MFD_MASK             0x7FFFFFF
+#define MXC_PLL_DP_MFN_OFFSET           0
+#define MXC_PLL_DP_MFN_MASK             0x7FFFFFF
+/* CRM AP Register Offsets */
+#define MXC_CRMAP_ASCSR                 (MXC_CRM_AP_BASE + 0x00)
+#define MXC_CRMAP_ACDR                  (MXC_CRM_AP_BASE + 0x04)
+#define MXC_CRMAP_ACDER1                (MXC_CRM_AP_BASE + 0x08)
+#define MXC_CRMAP_ACDER2                (MXC_CRM_AP_BASE + 0x0C)
+#define MXC_CRMAP_ACGCR                 (MXC_CRM_AP_BASE + 0x10)
+#define MXC_CRMAP_ACCGCR                (MXC_CRM_AP_BASE + 0x14)
+#define MXC_CRMAP_AMLPMRA               (MXC_CRM_AP_BASE + 0x18)
+#define MXC_CRMAP_AMLPMRB               (MXC_CRM_AP_BASE + 0x1C)
+#define MXC_CRMAP_AMLPMRC               (MXC_CRM_AP_BASE + 0x20)
+#define MXC_CRMAP_AMLPMRD               (MXC_CRM_AP_BASE + 0x24)
+#define MXC_CRMAP_AMLPMRE1              (MXC_CRM_AP_BASE + 0x28)
+#define MXC_CRMAP_AMLPMRE2              (MXC_CRM_AP_BASE + 0x2C)
+#define MXC_CRMAP_AMLPMRF               (MXC_CRM_AP_BASE + 0x30)
+#define MXC_CRMAP_AMLPMRG               (MXC_CRM_AP_BASE + 0x34)
+#define MXC_CRMAP_APGCR                 (MXC_CRM_AP_BASE + 0x38)
+#define MXC_CRMAP_ACSR                  (MXC_CRM_AP_BASE + 0x3C)
+#define MXC_CRMAP_ADCR                  (MXC_CRM_AP_BASE + 0x40)
+#define MXC_CRMAP_ACR                   (MXC_CRM_AP_BASE + 0x44)
+#define MXC_CRMAP_AMCR                  (MXC_CRM_AP_BASE + 0x48)
+#define MXC_CRMAP_APCR                  (MXC_CRM_AP_BASE + 0x4C)
+#define MXC_CRMAP_AMORA                 (MXC_CRM_AP_BASE + 0x50)
+#define MXC_CRMAP_AMORB                 (MXC_CRM_AP_BASE + 0x54)
+#define MXC_CRMAP_AGPR                  (MXC_CRM_AP_BASE + 0x58)
+#define MXC_CRMAP_APRA                  (MXC_CRM_AP_BASE + 0x5C)
+#define MXC_CRMAP_APRB                  (MXC_CRM_AP_BASE + 0x60)
+#define MXC_CRMAP_APOR                  (MXC_CRM_AP_BASE + 0x64)
+#define MXC_CRMAP_ADFMR                 (MXC_CRM_AP_BASE + 0x68)
+/* CRM AP Register Bit definitions */
+#define MXC_CRMAP_ASCSR_CRS                     0x10000
+#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET       15
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2          0x8000
+#define MXC_CRMAP_ASCSR_USBSEL_OFFSET           13
+#define MXC_CRMAP_ASCSR_USBSEL_MASK             (0x3 << 13)
+#define MXC_CRMAP_ASCSR_CSISEL_OFFSET           11
+#define MXC_CRMAP_ASCSR_CSISEL_MASK             (0x3 << 11)
+#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET          7
+#define MXC_CRMAP_ASCSR_SSI2SEL_MASK            (0x3 << 7)
+#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET          5
+#define MXC_CRMAP_ASCSR_SSI1SEL_MASK            (0x3 << 5)
+#define MXC_CRMAP_ASCSR_APSEL_OFFSET            3
+#define MXC_CRMAP_ASCSR_APSEL_MASK              (0x3 << 3)
+#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET       2
+#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1          0x4
+#define MXC_CRMAP_ASCSR_APISEL                  0x1
+#define MXC_CRMAP_ACDR_ARMDIV_OFFSET            8
+#define MXC_CRMAP_ACDR_ARMDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACDR_AHBDIV_OFFSET            4
+#define MXC_CRMAP_ACDR_AHBDIV_MASK              (0xF << 4)
+#define MXC_CRMAP_ACDR_IPDIV_OFFSET             0
+#define MXC_CRMAP_ACDR_IPDIV_MASK               0xF
+#define MXC_CRMAP_ACDER1_CSIEN_OFFSET           30
+#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET          24
+#define MXC_CRMAP_ACDER1_CSIDIV_MASK            (0x3F << 24)
+#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET          14
+#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET         8
+#define MXC_CRMAP_ACDER1_SSI2DIV_MASK           (0x3F << 8)
+#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET          6
+#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET         0
+#define MXC_CRMAP_ACDER1_SSI1DIV_MASK           0x3F
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET    24
+#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK      (0x7 << 24)
+#define MXC_CRMAP_ACDER2_NFCEN_OFFSET           20
+#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET          16
+#define MXC_CRMAP_ACDER2_NFCDIV_MASK            (0xF << 16)
+#define MXC_CRMAP_ACDER2_USBEN_OFFSET           12
+#define MXC_CRMAP_ACDER2_USBDIV_OFFSET          8
+#define MXC_CRMAP_ACDER2_USBDIV_MASK            (0xF << 8)
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET       5
+#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK         (0x3 << 5)
+#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET         0
+#define MXC_CRMAP_ACDER2_BAUDDIV_MASK           0xF
+#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET         22
+#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET         19
+#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET         12
+#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET         9
+#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET         6
+#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET         3
+#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET         0
+#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK           0x7
+#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET         28
+#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET         22
+#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET         16
+#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET         12
+#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET         9
+#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET         6
+#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET         3
+#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET         0
+#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK           0x7
+#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET         22
+#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET         12
+#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET         9
+#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET         6
+#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET         0
+#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK           0x7
+#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET        28
+#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK          (0x7 << 28)
+#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET        25
+#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK          (0x7 << 25)
+#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET        22
+#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK          (0x7 << 22)
+#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET        19
+#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK          (0x7 << 19)
+#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET        16
+#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK          (0x7 << 16)
+#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET        12
+#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK          (0x7 << 12)
+#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET        9
+#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK          (0x7 << 9)
+#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET        6
+#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK          (0x7 << 6)
+#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET        3
+#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK          (0x7 << 3)
+#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK          0x7
+#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET        0
+#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK          0x7
+#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET         19
+#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET         16
+#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET         9
+#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET         6
+#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET         3
+#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET         0
+#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK           (0x7 << 0)
+#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET         28
+#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK           (0x7 << 28)
+#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET         22
+#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK           (0x7 << 22)
+#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET         19
+#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK           (0x7 << 19)
+#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET         16
+#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK           (0x7 << 16)
+#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET         12
+#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK           (0x7 << 12)
+#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET         9
+#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK           (0x7 << 9)
+#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET         6
+#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK           (0x7 << 6)
+#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET         3
+#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK           (0x7 << 3)
+#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET         0
+#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK           0x7
+#define MXC_CRMAP_AGPR_IPUPAD_OFFSET            20
+#define MXC_CRMAP_AGPR_IPUPAD_MASK              (0x7 << 20)
+#define MXC_CRMAP_APRA_EL1TEN_OFFSET            29
+#define MXC_CRMAP_APRA_SIMEN_OFFSET             24
+#define MXC_CRMAP_APRA_UART3DIV_OFFSET          17
+#define MXC_CRMAP_APRA_UART3DIV_MASK            (0xF << 17)
+#define MXC_CRMAP_APRA_UART3EN_OFFSET           16
+#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
+#define MXC_CRMAP_APRA_MQSPIEN_OFFSET           13
+#define MXC_CRMAP_APRA_UART2EN_OFFSET           8
+#define MXC_CRMAP_APRA_UART1EN_OFFSET           0
+#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET        13
+#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK          (0x7 << 13)
+#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET         9
+#define MXC_CRMAP_APRB_SDHC2_DIV_MASK           (0xF << 9)
+#define MXC_CRMAP_APRB_SDHC2EN_OFFSET           8
+#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET        5
+#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK          (0x7 << 5)
+#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET         1
+#define MXC_CRMAP_APRB_SDHC1_DIV_MASK           (0xF << 1)
+#define MXC_CRMAP_APRB_SDHC1EN_OFFSET           0
+#define MXC_CRMAP_ACSR_ADS_OFFSET               8
+#define MXC_CRMAP_ACSR_ADS                      (0x1 << 8)
+#define MXC_CRMAP_ACSR_ACS                      0x1
+#define MXC_CRMAP_ADCR_LFDF_0                   (0x0 << 8)
+#define MXC_CRMAP_ADCR_LFDF_2                   (0x1 << 8)
+#define MXC_CRMAP_ADCR_LFDF_4                   (0x2 << 8)
+#define MXC_CRMAP_ADCR_LFDF_8                   (0x3 << 8)
+#define MXC_CRMAP_ADCR_LFDF_OFFSET              8
+#define MXC_CRMAP_ADCR_LFDF_MASK                (0x3 << 8)
+#define MXC_CRMAP_ADCR_ALT_PLL                  0x80
+#define MXC_CRMAP_ADCR_DFS_DIVEN                0x20
+#define MXC_CRMAP_ADCR_DIV_BYP                  0x2
+#define MXC_CRMAP_ADCR_VSTAT                    0x8
+#define MXC_CRMAP_ADCR_TSTAT                    0x10
+#define MXC_CRMAP_ADCR_DVFS_VCTRL               0x10
+#define MXC_CRMAP_ADCR_CLK_ON                   0x40
+#define MXC_CRMAP_ADFMR_FC_OFFSET               16
+#define MXC_CRMAP_ADFMR_FC_MASK                 (0x1F << 16)
+#define MXC_CRMAP_ADFMR_MF_OFFSET               1
+#define MXC_CRMAP_ADFMR_MF_MASK                 (0x3FF << 1)
+#define MXC_CRMAP_ADFMR_DFM_CLK_READY           0x1
+#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN            0x8000
+#define MXC_CRMAP_ACR_CKOHS_HIGH                (1 << 18)
+#define MXC_CRMAP_ACR_CKOS_HIGH                 (1 << 16)
+#define MXC_CRMAP_ACR_CKOHS_MASK                (0x7 << 12)
+#define MXC_CRMAP_ACR_CKOHD                     (1 << 11)
+#define MXC_CRMAP_ACR_CKOHDIV_MASK              (0xF << 8)
+#define MXC_CRMAP_ACR_CKOHDIV_OFFSET            8
+#define MXC_CRMAP_ACR_CKOD                      (1 << 7)
+#define MXC_CRMAP_ACR_CKOS_MASK                 (0x7 << 4)
+/* AP Warm reset */
+#define MXC_CRMAP_AMCR_SW_AP                    (1 << 14)
+/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
+#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT          0x00000001
+#define MXC_CRMAP_ACGCR_ACG0_STOP               0x00000003
+#define MXC_CRMAP_ACGCR_ACG0_RUN                0x00000007
+#define MXC_CRMAP_ACGCR_ACG0_DISABLED           0x00000000
+#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT          0x00000008
+#define MXC_CRMAP_ACGCR_ACG1_STOP               0x00000018
+#define MXC_CRMAP_ACGCR_ACG1_RUN                0x00000038
+#define MXC_CRMAP_ACGCR_ACG1_DISABLED           0x00000000
+#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT          0x00000040
+#define MXC_CRMAP_ACGCR_ACG2_STOP               0x000000C0
+#define MXC_CRMAP_ACGCR_ACG2_RUN                0x000001C0
+#define MXC_CRMAP_ACGCR_ACG2_DISABLED           0x00000000
+#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT          0x00000200
+#define MXC_CRMAP_ACGCR_ACG3_STOP               0x00000600
+#define MXC_CRMAP_ACGCR_ACG3_RUN                0x00000E00
+#define MXC_CRMAP_ACGCR_ACG3_DISABLED           0x00000000
+#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT          0x00001000
+#define MXC_CRMAP_ACGCR_ACG4_STOP               0x00003000
+#define MXC_CRMAP_ACGCR_ACG4_RUN                0x00007000
+#define MXC_CRMAP_ACGCR_ACG4_DISABLED           0x00000000
+#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT          0x00010000
+#define MXC_CRMAP_ACGCR_ACG5_STOP               0x00030000
+#define MXC_CRMAP_ACGCR_ACG5_RUN                0x00070000
+#define MXC_CRMAP_ACGCR_ACG5_DISABLED           0x00000000
+#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT          0x00080000
+#define MXC_CRMAP_ACGCR_ACG6_STOP               0x00180000
+#define MXC_CRMAP_ACGCR_ACG6_RUN                0x00380000
+#define MXC_CRMAP_ACGCR_ACG6_DISABLED           0x00000000
+#define NUM_GATE_CTRL                           6
+/* CRM COM Register Offsets */
+#define MXC_CRMCOM_CSCR                         (MXC_CRM_COM_BASE + 0x0C)
+#define MXC_CRMCOM_CCCR                         (MXC_CRM_COM_BASE + 0x10)
+/* CRM COM Bit Definitions */
+#define MXC_CRMCOM_CSCR_PPD1                    0x08000000
+#define MXC_CRMCOM_CSCR_CKOHSEL                 (1 << 18)
+#define MXC_CRMCOM_CSCR_CKOSEL                  (1 << 17)
+#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET           8
+#define MXC_CRMCOM_CCCR_CC_DIV_MASK             (0x1F << 8)
+#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET           0
+#define MXC_CRMCOM_CCCR_CC_SEL_MASK             0x3
+/* DSM Register Offsets */
+#define MXC_DSM_SLEEP_TIME                      (MXC_DSM_BASE + 0x0c)
+#define MXC_DSM_CONTROL0                        (MXC_DSM_BASE + 0x20)
+#define MXC_DSM_CONTROL1                        (MXC_DSM_BASE + 0x24)
+#define MXC_DSM_CTREN                           (MXC_DSM_BASE + 0x28)
+#define MXC_DSM_WARM_PER                        (MXC_DSM_BASE + 0x40)
+#define MXC_DSM_LOCK_PER                        (MXC_DSM_BASE + 0x44)
+#define MXC_DSM_MGPER                           (MXC_DSM_BASE + 0x4c)
+#define MXC_DSM_CRM_CONTROL                     (MXC_DSM_BASE + 0x50)
+/* Bit definitions of various registers in DSM */
+#define MXC_DSM_CRM_CTRL_DVFS_BYP               0x00000008
+#define MXC_DSM_CRM_CTRL_DVFS_VCTRL             0x00000004
+#define MXC_DSM_CRM_CTRL_LPMD1                  0x00000002
+#define MXC_DSM_CRM_CTRL_LPMD0                  0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE         0x00000000
+#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE         0x00000001
+#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE          0x00000003
+#define MXC_DSM_CONTROL0_STBY_COMMIT_EN         0x00000200
+#define MXC_DSM_CONTROL0_MSTR_EN                0x00000001
+#define MXC_DSM_CONTROL0_RESTART                0x00000010
+/* Counter Block reset */
+#define MXC_DSM_CONTROL1_CB_RST                 0x00000002
+/* State Machine reset */
+#define MXC_DSM_CONTROL1_SM_RST                 0x00000004
+/* Bit needed to reset counter block */
+#define MXC_CONTROL1_RST_CNT32                  0x00000008
+#define MXC_DSM_CONTROL1_RST_CNT32_EN           0x00000800
+#define MXC_DSM_CONTROL1_SLEEP                  0x00000100
+#define MXC_DSM_CONTROL1_WAKEUP_DISABLE         0x00004000
+#define MXC_DSM_CTREN_CNT32                     0x00000001
+/* Magic Fix enable bit */
+#define MXC_DSM_MGPER_EN_MGFX                   0x80000000
+#define MXC_DSM_MGPER_PER_MASK                  0x000003FF
+#define MXC_DSM_MGPER_PER(n)                    (MXC_DSM_MGPER_PER_MASK & n)
+/* Address offsets of the CLKCTL registers */
+#define MXC_CLKCTL_GP_CTRL      (MXC_CLKCTL_BASE + 0x00)
+#define MXC_CLKCTL_GP_SER       (MXC_CLKCTL_BASE + 0x04)
+#define MXC_CLKCTL_GP_CER       (MXC_CLKCTL_BASE + 0x08)
+#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
new file mode 100644
index 000000000000..353bd977b393
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor,
+ * Boston, MA  02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/serial.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/imx-uart.h>
+static struct resource uart0[] = {
+        {
+                .start = MXC91231_UART1_BASE_ADDR,
+                .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART1_RX,
+                .end = MXC91231_INT_UART1_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_TX,
+                .end = MXC91231_INT_UART1_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART1_MINT,
+                .end = MXC91231_INT_UART1_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device0 = {
+        .name = "imx-uart",
+        .id = 0,
+        .resource = uart0,
+        .num_resources = ARRAY_SIZE(uart0),
+};
+static struct resource uart1[] = {
+        {
+                .start = MXC91231_UART2_BASE_ADDR,
+                .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART2_RX,
+                .end = MXC91231_INT_UART2_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_TX,
+                .end = MXC91231_INT_UART2_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART2_MINT,
+                .end = MXC91231_INT_UART2_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device1 = {
+        .name = "imx-uart",
+        .id = 1,
+        .resource = uart1,
+        .num_resources = ARRAY_SIZE(uart1),
+};
+static struct resource uart2[] = {
+        {
+                .start = MXC91231_UART3_BASE_ADDR,
+                .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_UART3_RX,
+                .end = MXC91231_INT_UART3_RX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_TX,
+                .end = MXC91231_INT_UART3_TX,
+                .flags = IORESOURCE_IRQ,
+        }, {
+                .start = MXC91231_INT_UART3_MINT,
+                .end = MXC91231_INT_UART3_MINT,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_uart_device2 = {
+        .name = "imx-uart",
+        .id = 2,
+        .resource = uart2,
+        .num_resources = ARRAY_SIZE(uart2),
+};
+/* GPIO port description */
+static struct mxc_gpio_port mxc_gpio_ports[] = {
+        [0] = {
+                .chip.label = "gpio-0",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO1,
+                .virtual_irq_start = MXC_GPIO_IRQ_START,
+        },
+        [1] = {
+                .chip.label = "gpio-1",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO2,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
+        },
+        [2] = {
+                .chip.label = "gpio-2",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO3,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
+        },
+        [3] = {
+                .chip.label = "gpio-3",
+                .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
+                .irq = MXC91231_INT_GPIO4,
+                .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
+        },
+};
+int __init mxc_register_gpios(void)
+{
+        return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
+}
+static struct resource mxc_nand_resources[] = {
+        {
+                .start  = MXC91231_NFC_BASE_ADDR,
+                .end    = MXC91231_NFC_BASE_ADDR + 0xfff,
+                .flags  = IORESOURCE_MEM
+        }, {
+                .start  = MXC91231_INT_NANDFC,
+                .end    = MXC91231_INT_NANDFC,
+                .flags  = IORESOURCE_IRQ
+        },
+};
+struct platform_device mxc_nand_device = {
+        .name = "mxc_nand",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_nand_resources),
+        .resource = mxc_nand_resources,
+};
+static struct resource mxc_sdhc0_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC1_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC1,
+                .end = MXC91231_INT_MMC_SDHC1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+static struct resource mxc_sdhc1_resources[] = {
+        {
+                .start = MXC91231_MMC_SDHC2_BASE_ADDR,
+                .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_MMC_SDHC2,
+                .end = MXC91231_INT_MMC_SDHC2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_sdhc_device0 = {
+        .name = "mxc-mmc",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
+        .resource = mxc_sdhc0_resources,
+};
+struct platform_device mxc_sdhc_device1 = {
+        .name = "mxc-mmc",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
+        .resource = mxc_sdhc1_resources,
+};
+static struct resource mxc_cspi0_resources[] = {
+        {
+                .start = MXC91231_CSPI1_BASE_ADDR,
+                .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI1,
+                .end = MXC91231_INT_CSPI1,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_cspi_device0 = {
+        .name = "spi_imx",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
+        .resource = mxc_cspi0_resources,
+};
+static struct resource mxc_cspi1_resources[] = {
+        {
+                .start = MXC91231_CSPI2_BASE_ADDR,
+                .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = MXC91231_INT_CSPI2,
+                .end = MXC91231_INT_CSPI2,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device mxc_cspi_device1 = {
+        .name = "spi_imx",
+        .id = 1,
+        .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
+        .resource = mxc_cspi1_resources,
+};
+static struct resource mxc_wdog0_resources[] = {
+        {
+                .start = MXC91231_WDOG1_BASE_ADDR,
+                .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
+                .flags = IORESOURCE_MEM,
+        },
+};
+struct platform_device mxc_wdog_device0 = {
+        .name = "mxc-wdt",
+        .id = 0,
+        .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
+        .resource = mxc_wdog0_resources,
+};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
new file mode 100644
index 000000000000..72a2136ce27d
--- /dev/null
+++ b/arch/arm/mach-mxc91231/devices.h
@@ -0,0 +1,13 @@
+extern struct platform_device mxc_uart_device0;
+extern struct platform_device mxc_uart_device1;
+extern struct platform_device mxc_uart_device2;
+extern struct platform_device mxc_nand_device;
+extern struct platform_device mxc_sdhc_device0;
+extern struct platform_device mxc_sdhc_device1;
+extern struct platform_device mxc_cspi_device0;
+extern struct platform_device mxc_cspi_device1;
+extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
new file mode 100644
index 000000000000..405d9b19d891
--- /dev/null
+++ b/arch/arm/mach-mxc91231/iomux.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+#include <mach/iomux-mxc91231.h>
+/*
+ * IOMUX register (base) addresses
+ */
+#define IOMUX_AP_BASE           MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
+#define IOMUX_COM_BASE          MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
+#define IOMUXSW_AP_MUX_CTL      (IOMUX_AP_BASE + 0x000)
+#define IOMUXSW_SP_MUX_CTL      (IOMUX_COM_BASE + 0x000)
+#define IOMUXSW_PAD_CTL         (IOMUX_COM_BASE + 0x200)
+#define IOMUXINT_OBS1           (IOMUX_AP_BASE + 0x600)
+#define IOMUXINT_OBS2           (IOMUX_AP_BASE + 0x004)
+static DEFINE_SPINLOCK(gpio_mux_lock);
+#define NB_PORTS                        ((PIN_MAX + 32) / 32)
+#define PIN_GLOBAL_NUM(pin) \
+        (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
+         ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 +            \
+         ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
+unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
+/*
+ * set the mode for a IOMUX pin.
+ */
+int mxc_iomux_mode(const unsigned int pin_mode)
+{
+        u32 side, field, l, mode, ret = 0;
+        void __iomem *reg;
+        side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
+        switch (side) {
+        case MUX_SIDE_AP:
+                reg = IOMUXSW_AP_MUX_CTL;
+                break;
+        case MUX_SIDE_SP:
+                reg = IOMUXSW_SP_MUX_CTL;
+                break;
+        default:
+                return -EINVAL;
+        }
+        reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
+        field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
+        mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
+        spin_lock(&gpio_mux_lock);
+        l = __raw_readl(reg);
+        l &= ~(0xff << (field * 8));
+        l |= mode << (field * 8);
+        __raw_writel(l, reg);
+        spin_unlock(&gpio_mux_lock);
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_mode);
+/*
+ * This function configures the pad value for a IOMUX pin.
+ */
+void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
+{
+        u32 padgrp, field, l;
+        void __iomem *reg;
+        padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
+        reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
+        field = (pin + 2) % 3;
+        pr_debug("%s: reg offset = 0x%x, field = %d\n",
+                        __func__, (pin + 2) / 3, field);
+        spin_lock(&gpio_mux_lock);
+        l = __raw_readl(reg);
+        l &= ~(0x1ff << (field * 10));
+        l |= config << (field * 10);
+        __raw_writel(l, reg);
+        spin_unlock(&gpio_mux_lock);
+}
+EXPORT_SYMBOL(mxc_iomux_set_pad);
+/*
+ * allocs a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ */
+int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label)
+{
+        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
+        if (pad >= (PIN_MAX + 1)) {
+                printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
+                        pad, label ? label : "?");
+                return -EINVAL;
+        }
+        if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
+                printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
+                        pad, label ? label : "?");
+                return -EBUSY;
+        }
+        mxc_iomux_mode(pin_mode);
+        return 0;
+}
+EXPORT_SYMBOL(mxc_iomux_alloc_pin);
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label)
+{
+        unsigned int *p = pin_list;
+        int i;
+        int ret = -EINVAL;
+        for (i = 0; i < count; i++) {
+                ret = mxc_iomux_alloc_pin(*p, label);
+                if (ret)
+                        goto setup_error;
+                p++;
+        }
+        return 0;
+setup_error:
+        mxc_iomux_release_multiple_pins(pin_list, i);
+        return ret;
+}
+EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
+void mxc_iomux_release_pin(const unsigned int pin_mode)
+{
+        unsigned pad = PIN_GLOBAL_NUM(pin_mode);
+        if (pad < (PIN_MAX + 1))
+                clear_bit(pad, mxc_pin_alloc_map);
+}
+EXPORT_SYMBOL(mxc_iomux_release_pin);
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
+{
+        unsigned int *p = pin_list;
+        int i;
+        for (i = 0; i < count; i++) {
+                mxc_iomux_release_pin(*p);
+                p++;
+        }
+}
+EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
new file mode 100644
index 000000000000..7dbe4ca12efd
--- /dev/null
+++ b/arch/arm/mach-mxc91231/magx-zn5.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+#include <linux/irq.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <asm/mach-types.h>
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mxc91231.h>
+#include <mach/mmc.h>
+#include <mach/imx-uart.h>
+#include "devices.h"
+static struct imxuart_platform_data uart_pdata = {
+};
+static struct imxmmc_platform_data sdhc_pdata = {
+};
+static void __init zn5_init(void)
+{
+        pm_power_off = mxc91231_power_off;
+        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
+        mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
+        mxc_register_device(&mxc_uart_device1, &uart_pdata);
+        mxc_register_device(&mxc_uart_device0, &uart_pdata);
+        mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
+        mxc_register_device(&mxc_wdog_device0, NULL);
+        return;
+}
+static void __init zn5_timer_init(void)
+{
+        mxc91231_clocks_init(26000000); /* 26mhz ckih */
+}
+struct sys_timer zn5_timer = {
+        .init = zn5_timer_init,
+};
+MACHINE_START(MAGX_ZN5, "Motorola Zn5")
+        .phys_io        = MXC91231_AIPS1_BASE_ADDR,
+        .io_pg_offst    = ((MXC91231_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
+        .boot_params    = PHYS_OFFSET + 0x100,
+        .map_io         = mxc91231_map_io,
+        .init_irq       = mxc91231_init_irq,
+        .timer          = &zn5_timer,
+        .init_machine   = zn5_init,
+MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
new file mode 100644
index 000000000000..6becda3ff331
--- /dev/null
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -0,0 +1,94 @@
+/*
+ *  Copyright (C) 1999,2000 Arm Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *  Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - add MXC specific definitions
+ *  Copyright 2006 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+/*
+ * This structure defines the MXC memory map.
+ */
+static struct map_desc mxc_io_desc[] __initdata = {
+        {
+                .virtual        = MXC91231_L2CC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR),
+                .length         = MXC91231_L2CC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_X_MEMC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR),
+                .length         = MXC91231_X_MEMC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_ROMP_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
+                .length         = MXC91231_ROMP_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AVIC_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
+                .length         = MXC91231_AVIC_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
+                .length         = MXC91231_AIPS1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA0_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
+                .length         = MXC91231_SPBA0_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_SPBA1_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
+                .length         = MXC91231_SPBA1_SIZE,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = MXC91231_AIPS2_BASE_ADDR_VIRT,
+                .pfn            = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
+                .length         = MXC91231_AIPS2_SIZE,
+                .type           = MT_DEVICE,
+        },
+};
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory map for
+ * the IO modules.
+ */
+void __init mxc91231_map_io(void)
+{
+        mxc_set_cpu_type(MXC_CPU_MXC91231);
+        iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
+}
+void __init mxc91231_init_irq(void)
+{
+        mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
+}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
new file mode 100644
index 000000000000..736f7efd874a
--- /dev/null
+++ b/arch/arm/mach-mxc91231/system.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This file is released under the GPLv2 or later.
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/proc-fns.h>
+#include <mach/hardware.h>
+#include "crm_regs.h"
+#define WDOG_WCR                MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
+#define WDOG_WCR_OUT_ENABLE     (1 << 6)
+#define WDOG_WCR_ASSERT         (1 << 5)
+void mxc91231_power_off(void)
+{
+        u16 wcr;
+        wcr = __raw_readw(WDOG_WCR);
+        wcr |= WDOG_WCR_OUT_ENABLE;
+        wcr &= ~WDOG_WCR_ASSERT;
+        __raw_writew(wcr, WDOG_WCR);
+}
+void mxc91231_arch_reset(char mode, const char *cmd)
+{
+        u32 amcr;
+        /* Reset the AP using CRM */
+        amcr = __raw_readl(MXC_CRMAP_AMCR);
+        amcr &= ~MXC_CRMAP_AMCR_SW_AP;
+        __raw_writel(amcr, MXC_CRMAP_AMCR);
+        mdelay(10);
+        cpu_reset(0);
+}
+void mxc91231_prepare_idle(void)
+{
+        u32 crm_ctl;
+        /* Go to WAIT mode after WFI */
+        crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
+        crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
+        crm_ctl |=  MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
+        __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
+}
diff --git a/arch/arm/mach-netx/include/mach/entry-macro.S b/arch/arm/mach-netx/include/mach/entry-macro.S
index a1952a0feda6..844f1f9acbdf 100644
--- a/arch/arm/mach-netx/include/mach/entry-macro.S
+++ b/arch/arm/mach-netx/include/mach/entry-macro.S
@@ -24,15 +24,13 @@
                .endm
                .macro  get_irqnr_preamble, base, tmp
+                ldr     \base, =io_p2v(0x001ff000)
                .endm
                .macro  arch_ret_to_user, tmp1, tmp2
                .endm
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-                mov     \base, #io_p2v(0x00100000)
-                add     \base, \base, #0x000ff000
                ldr     \irqstat, [\base, #0]
                clz     \irqnr, \irqstat
                rsb     \irqnr, \irqnr, #31
diff --git a/arch/arm/mach-nomadik/Kconfig b/arch/arm/mach-nomadik/Kconfig
new file mode 100644
index 000000000000..2a02b49c40f0
--- /dev/null
+++ b/arch/arm/mach-nomadik/Kconfig
@@ -0,0 +1,21 @@
+if ARCH_NOMADIK
+menu "Nomadik boards"
+config MACH_NOMADIK_8815NHK
+        bool "ST 8815 Nomadik Hardware Kit (evaluation board)"
+        select NOMADIK_8815
+endmenu
+config NOMADIK_8815
+        bool
+config I2C_BITBANG_8815NHK
+        tristate "Driver for bit-bang busses found on the 8815 NHK"
+        depends on I2C && MACH_NOMADIK_8815NHK
+        select I2C_ALGOBIT
+        default y
+endif
diff --git a/arch/arm/mach-nomadik/Makefile b/arch/arm/mach-nomadik/Makefile
new file mode 100644
index 000000000000..412040982a40
--- /dev/null
+++ b/arch/arm/mach-nomadik/Makefile
@@ -0,0 +1,19 @@
+#
+# Makefile for the linux kernel.
+#
+# Note! Dependencies are done automagically by 'make dep', which also
+# removes any old dependencies. DON'T put your own dependencies here
+# unless it's something special (ie not a .c file).
+# Object file lists.
+obj-y                   += clock.o timer.o gpio.o
+# Cpu revision
+obj-$(CONFIG_NOMADIK_8815) += cpu-8815.o
+# Specific board support
+obj-$(CONFIG_MACH_NOMADIK_8815NHK) += board-nhk8815.o
+# Nomadik extra devices
+obj-$(CONFIG_I2C_BITBANG_8815NHK) += i2c-8815nhk.o
diff --git a/arch/arm/mach-nomadik/Makefile.boot b/arch/arm/mach-nomadik/Makefile.boot
new file mode 100644
index 000000000000..c7e75acfe6c9
--- /dev/null
+++ b/arch/arm/mach-nomadik/Makefile.boot
@@ -0,0 +1,4 @@
+   zreladdr-y   := 0x00008000
+params_phys-y   := 0x00000100
+initrd_phys-y   := 0x00800000
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
new file mode 100644
index 000000000000..79bdea943eb4
--- /dev/null
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -0,0 +1,111 @@
+/*
+ *  linux/arch/arm/mach-nomadik/board-8815nhk.c
+ *
+ *  Copyright (C) STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ *
+ *  NHK15 board specifc driver definition
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/amba/bus.h>
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/setup.h>
+#include "clock.h"
+#define __MEM_4K_RESOURCE(x) \
+        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+static struct amba_device uart0_device = {
+        .dev = { .init_name = "uart0" },
+        __MEM_4K_RESOURCE(NOMADIK_UART0_BASE),
+        .irq = {IRQ_UART0, NO_IRQ},
+};
+static struct amba_device uart1_device = {
+        .dev = { .init_name = "uart1" },
+        __MEM_4K_RESOURCE(NOMADIK_UART1_BASE),
+        .irq = {IRQ_UART1, NO_IRQ},
+};
+static struct amba_device *amba_devs[] __initdata = {
+        &uart0_device,
+        &uart1_device,
+};
+/* We have a fixed clock alone, by now */
+static struct clk nhk8815_clk_48 = {
+        .rate = 48*1000*1000,
+};
+static struct resource nhk8815_eth_resources[] = {
+        {
+                .name = "smc91x-regs",
+                .start = 0x34000000 + 0x300,
+                .end = 0x34000000 + SZ_64K - 1,
+                .flags = IORESOURCE_MEM,
+        }, {
+                .start = NOMADIK_GPIO_TO_IRQ(115),
+                .end = NOMADIK_GPIO_TO_IRQ(115),
+                .flags = IORESOURCE_IRQ | IRQF_TRIGGER_RISING,
+        }
+};
+static struct platform_device nhk8815_eth_device = {
+        .name = "smc91x",
+        .resource = nhk8815_eth_resources,
+        .num_resources = ARRAY_SIZE(nhk8815_eth_resources),
+};
+static int __init nhk8815_eth_init(void)
+{
+        int gpio_nr = 115; /* hardwired in the board */
+        int err;
+        err = gpio_request(gpio_nr, "eth_irq");
+        if (!err) err = nmk_gpio_set_mode(gpio_nr, NMK_GPIO_ALT_GPIO);
+        if (!err) err = gpio_direction_input(gpio_nr);
+        if (err)
+                pr_err("Error %i in %s\n", err, __func__);
+        return err;
+}
+device_initcall(nhk8815_eth_init);
+static struct platform_device *nhk8815_platform_devices[] __initdata = {
+        &nhk8815_eth_device,
+        /* will add more devices */
+};
+static void __init nhk8815_platform_init(void)
+{
+        int i;
+        cpu8815_platform_init();
+        platform_add_devices(nhk8815_platform_devices,
+                             ARRAY_SIZE(nhk8815_platform_devices));
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
+                nmdk_clk_create(&nhk8815_clk_48, amba_devs[i]->dev.init_name);
+                amba_device_register(amba_devs[i], &iomem_resource);
+        }
+}
+MACHINE_START(NOMADIK, "NHK8815")
+        /* Maintainer: ST MicroElectronics */
+        .phys_io        = NOMADIK_UART0_BASE,
+        .io_pg_offst    = (IO_ADDRESS(NOMADIK_UART0_BASE) >> 18) & 0xfffc,
+        .boot_params    = 0x100,
+        .map_io         = cpu8815_map_io,
+        .init_irq       = cpu8815_init_irq,
+        .timer          = &nomadik_timer,
+        .init_machine   = nhk8815_platform_init,
+MACHINE_END
diff --git a/arch/arm/mach-nomadik/clock.c b/arch/arm/mach-nomadik/clock.c
new file mode 100644
index 000000000000..9f92502a0083
--- /dev/null
+++ b/arch/arm/mach-nomadik/clock.c
@@ -0,0 +1,45 @@
+/*
+ *  linux/arch/arm/mach-nomadik/clock.c
+ *
+ *  Copyright (C) 2009 Alessandro Rubini
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <asm/clkdev.h>
+#include "clock.h"
+/*
+ * The nomadik board uses generic clocks, but the serial pl011 file
+ * calls clk_enable(), clk_disable(), clk_get_rate(), so we provide them
+ */
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return clk->rate;
+}
+EXPORT_SYMBOL(clk_get_rate);
+/* enable and disable do nothing */
+int clk_enable(struct clk *clk)
+{
+        return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+void clk_disable(struct clk *clk)
+{
+}
+EXPORT_SYMBOL(clk_disable);
+/* Create a clock structure with the given name */
+int nmdk_clk_create(struct clk *clk, const char *dev_id)
+{
+        struct clk_lookup *clkdev;
+        clkdev = clkdev_alloc(clk, NULL, dev_id);
+        if (!clkdev)
+                return -ENOMEM;
+        clkdev_add(clkdev);
+        return 0;
+}
diff --git a/arch/arm/mach-nomadik/clock.h b/arch/arm/mach-nomadik/clock.h
new file mode 100644
index 000000000000..235faec7f627
--- /dev/null
+++ b/arch/arm/mach-nomadik/clock.h
@@ -0,0 +1,14 @@
+/*
+ *  linux/arch/arm/mach-nomadik/clock.h
+ *
+ *  Copyright (C) 2009 Alessandro Rubini
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+struct clk {
+        unsigned long           rate;
+};
+extern int nmdk_clk_create(struct clk *clk, const char *dev_id);
diff --git a/arch/arm/mach-nomadik/cpu-8815.c b/arch/arm/mach-nomadik/cpu-8815.c
new file mode 100644
index 000000000000..f93c59634191
--- /dev/null
+++ b/arch/arm/mach-nomadik/cpu-8815.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright STMicroelectronics, 2007.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/vic.h>
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-l2x0.h>
+/* The 8815 has 4 GPIO blocks, let's register them immediately */
+static struct nmk_gpio_platform_data cpu8815_gpio[] = {
+        {
+                .name = "GPIO-0-31",
+                .first_gpio = 0,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(0),
+                .parent_irq = IRQ_GPIO0,
+        }, {
+                .name = "GPIO-32-63",
+                .first_gpio = 32,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(32),
+                .parent_irq = IRQ_GPIO1,
+        }, {
+                .name = "GPIO-64-95",
+                .first_gpio = 64,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(64),
+                .parent_irq = IRQ_GPIO2,
+        }, {
+                .name = "GPIO-96-127", /* 124..127 not routed to pin */
+                .first_gpio = 96,
+                .first_irq = NOMADIK_GPIO_TO_IRQ(96),
+                .parent_irq = IRQ_GPIO3,
+        }
+};
+#define __MEM_4K_RESOURCE(x) \
+        .res = {.start = (x), .end = (x) + SZ_4K - 1, .flags = IORESOURCE_MEM}
+static struct amba_device cpu8815_amba_gpio[] = {
+        {
+                .dev = {
+                        .init_name = "gpio0",
+                        .platform_data = cpu8815_gpio + 0,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO0_BASE),
+        }, {
+                .dev = {
+                        .init_name = "gpio1",
+                        .platform_data = cpu8815_gpio + 1,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO1_BASE),
+        }, {
+                .dev = {
+                        .init_name = "gpio2",
+                        .platform_data = cpu8815_gpio + 2,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO2_BASE),
+        }, {
+                .dev = {
+                        .init_name = "gpio3",
+                        .platform_data = cpu8815_gpio + 3,
+                },
+                __MEM_4K_RESOURCE(NOMADIK_GPIO3_BASE),
+        },
+};
+static struct amba_device *amba_devs[] __initdata = {
+        cpu8815_amba_gpio + 0,
+        cpu8815_amba_gpio + 1,
+        cpu8815_amba_gpio + 2,
+        cpu8815_amba_gpio + 3,
+};
+static int __init cpu8815_init(void)
+{
+        int i;
+        for (i = 0; i < ARRAY_SIZE(amba_devs); i++)
+                amba_device_register(amba_devs[i], &iomem_resource);
+        return 0;
+}
+arch_initcall(cpu8815_init);
+/* All SoC devices live in the same area (see hardware.h) */
+static struct map_desc nomadik_io_desc[] __initdata = {
+        {
+                .virtual =      NOMADIK_IO_VIRTUAL,
+                .pfn =          __phys_to_pfn(NOMADIK_IO_PHYSICAL),
+                .length =       NOMADIK_IO_SIZE,
+                .type =         MT_DEVICE,
+        }
+        /* static ram and secured ram may be added later */
+};
+void __init cpu8815_map_io(void)
+{
+        iotable_init(nomadik_io_desc, ARRAY_SIZE(nomadik_io_desc));
+}
+void __init cpu8815_init_irq(void)
+{
+        /* This modified VIC cell has two register blocks, at 0 and 0x20 */
+        vic_init(io_p2v(NOMADIK_IC_BASE + 0x00), IRQ_VIC_START +  0, ~0, 0);
+        vic_init(io_p2v(NOMADIK_IC_BASE + 0x20), IRQ_VIC_START + 32, ~0, 0);
+}
+/*
+ * This function is called from the board init ("init_machine").
+ */
+ void __init cpu8815_platform_init(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+        /* At full speed latency must be >=2, so 0x249 in low bits */
+        l2x0_init(io_p2v(NOMADIK_L2CC_BASE), 0x00730249, 0xfe000fff);
+#endif
+         return;
+}
diff --git a/arch/arm/mach-nomadik/gpio.c b/arch/arm/mach-nomadik/gpio.c
new file mode 100644
index 000000000000..9a09b2791e03
--- /dev/null
+++ b/arch/arm/mach-nomadik/gpio.c
@@ -0,0 +1,396 @@
+/*
+ * Generic GPIO driver for logic cells found in the Nomadik SoC
+ *
+ * Copyright (C) 2008,2009 STMicroelectronics
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/amba/bus.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <mach/hardware.h>
+#include <mach/gpio.h>
+/*
+ * The GPIO module in the Nomadik family of Systems-on-Chip is an
+ * AMBA device, managing 32 pins and alternate functions.  The logic block
+ * is currently only used in the Nomadik.
+ *
+ * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
+ */
+#define NMK_GPIO_PER_CHIP 32
+struct nmk_gpio_chip {
+        struct gpio_chip chip;
+        void __iomem *addr;
+        unsigned int parent_irq;
+        spinlock_t *lock;
+        /* Keep track of configured edges */
+        u32 edge_rising;
+        u32 edge_falling;
+};
+/* Mode functions */
+int nmk_gpio_set_mode(int gpio, int gpio_mode)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 afunc, bfunc, bit;
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+        bit = 1 << (gpio - nmk_chip->chip.base);
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit;
+        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit;
+        if (gpio_mode & NMK_GPIO_ALT_A)
+                afunc |= bit;
+        if (gpio_mode & NMK_GPIO_ALT_B)
+                bfunc |= bit;
+        writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
+        writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+        return 0;
+}
+EXPORT_SYMBOL(nmk_gpio_set_mode);
+int nmk_gpio_get_mode(int gpio)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        u32 afunc, bfunc, bit;
+        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        if (!nmk_chip)
+                return -EINVAL;
+        bit = 1 << (gpio - nmk_chip->chip.base);
+        afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit;
+        bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit;
+        return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0);
+}
+EXPORT_SYMBOL(nmk_gpio_get_mode);
+/* IRQ functions */
+static inline int nmk_gpio_get_bitmask(int gpio)
+{
+        return 1 << (gpio % 32);
+}
+static void nmk_gpio_irq_ack(unsigned int irq)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        if (!nmk_chip)
+                return;
+        writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC);
+}
+static void nmk_gpio_irq_mask(unsigned int irq)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 bitmask, reg;
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        bitmask = nmk_gpio_get_bitmask(gpio);
+        if (!nmk_chip)
+                return;
+        /* we must individually clear the two edges */
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        if (nmk_chip->edge_rising & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
+                reg &= ~bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_RWIMSC);
+        }
+        if (nmk_chip->edge_falling & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
+                reg &= ~bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_FWIMSC);
+        }
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+};
+static void nmk_gpio_irq_unmask(unsigned int irq)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 bitmask, reg;
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        bitmask = nmk_gpio_get_bitmask(gpio);
+        if (!nmk_chip)
+                return;
+        /* we must individually set the two edges */
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        if (nmk_chip->edge_rising & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_RWIMSC);
+                reg |= bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_RWIMSC);
+        }
+        if (nmk_chip->edge_falling & bitmask) {
+                reg = readl(nmk_chip->addr + NMK_GPIO_FWIMSC);
+                reg |= bitmask;
+                writel(reg, nmk_chip->addr + NMK_GPIO_FWIMSC);
+        }
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+}
+static int nmk_gpio_irq_set_type(unsigned int irq, unsigned int type)
+{
+        int gpio;
+        struct nmk_gpio_chip *nmk_chip;
+        unsigned long flags;
+        u32 bitmask;
+        gpio = NOMADIK_IRQ_TO_GPIO(irq);
+        nmk_chip = get_irq_chip_data(irq);
+        bitmask = nmk_gpio_get_bitmask(gpio);
+        if (!nmk_chip)
+                return -EINVAL;
+        if (type & IRQ_TYPE_LEVEL_HIGH)
+                return -EINVAL;
+        if (type & IRQ_TYPE_LEVEL_LOW)
+                return -EINVAL;
+        spin_lock_irqsave(&nmk_chip->lock, flags);
+        nmk_chip->edge_rising &= ~bitmask;
+        if (type & IRQ_TYPE_EDGE_RISING)
+                nmk_chip->edge_rising |= bitmask;
+        writel(nmk_chip->edge_rising, nmk_chip->addr + NMK_GPIO_RIMSC);
+        nmk_chip->edge_falling &= ~bitmask;
+        if (type & IRQ_TYPE_EDGE_FALLING)
+                nmk_chip->edge_falling |= bitmask;
+        writel(nmk_chip->edge_falling, nmk_chip->addr + NMK_GPIO_FIMSC);
+        spin_unlock_irqrestore(&nmk_chip->lock, flags);
+        nmk_gpio_irq_unmask(irq);
+        return 0;
+}
+static struct irq_chip nmk_gpio_irq_chip = {
+        .name           = "Nomadik-GPIO",
+        .ack            = nmk_gpio_irq_ack,
+        .mask           = nmk_gpio_irq_mask,
+        .unmask         = nmk_gpio_irq_unmask,
+        .set_type       = nmk_gpio_irq_set_type,
+};
+static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        struct irq_chip *host_chip;
+        unsigned int gpio_irq;
+        u32 pending;
+        unsigned int first_irq;
+        nmk_chip = get_irq_data(irq);
+        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
+        while ( (pending = readl(nmk_chip->addr + NMK_GPIO_IS)) ) {
+                gpio_irq = first_irq + __ffs(pending);
+                generic_handle_irq(gpio_irq);
+        }
+        if (0) {/* don't ack parent irq, as ack == disable */
+                host_chip = get_irq_chip(irq);
+                host_chip->ack(irq);
+        }
+}
+static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
+{
+        unsigned int first_irq;
+        int i;
+        first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
+        for (i = first_irq; i < first_irq + NMK_GPIO_PER_CHIP; i++) {
+                set_irq_chip(i, &nmk_gpio_irq_chip);
+                set_irq_handler(i, handle_edge_irq);
+                set_irq_flags(i, IRQF_VALID);
+                set_irq_chip_data(i, nmk_chip);
+        }
+        set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
+        set_irq_data(nmk_chip->parent_irq, nmk_chip);
+        return 0;
+}
+/* I/O Functions */
+static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC);
+        return 0;
+}
+static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset,
+                                int val)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS);
+        return 0;
+}
+static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        u32 bit = 1 << offset;
+        return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0;
+}
+static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset,
+                                int val)
+{
+        struct nmk_gpio_chip *nmk_chip =
+                container_of(chip, struct nmk_gpio_chip, chip);
+        u32 bit = 1 << offset;
+        if (val)
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATS);
+        else
+                writel(bit, nmk_chip->addr + NMK_GPIO_DATC);
+}
+/* This structure is replicated for each GPIO block allocated at probe time */
+static struct gpio_chip nmk_gpio_template = {
+        .direction_input        = nmk_gpio_make_input,
+        .get                    = nmk_gpio_get_input,
+        .direction_output       = nmk_gpio_make_output,
+        .set                    = nmk_gpio_set_output,
+        .ngpio                  = NMK_GPIO_PER_CHIP,
+        .can_sleep              = 0,
+};
+static int __init nmk_gpio_probe(struct amba_device *dev, struct amba_id *id)
+{
+        struct nmk_gpio_platform_data *pdata;
+        struct nmk_gpio_chip *nmk_chip;
+        struct gpio_chip *chip;
+        int ret;
+        pdata = dev->dev.platform_data;
+        ret = amba_request_regions(dev, pdata->name);
+        if (ret)
+                return ret;
+        nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL);
+        if (!nmk_chip) {
+                ret = -ENOMEM;
+                goto out_amba;
+        }
+        /*
+         * The virt address in nmk_chip->addr is in the nomadik register space,
+         * so we can simply convert the resource address, without remapping
+         */
+        nmk_chip->addr = io_p2v(dev->res.start);
+        nmk_chip->chip = nmk_gpio_template;
+        nmk_chip->parent_irq = pdata->parent_irq;
+        chip = &nmk_chip->chip;
+        chip->base = pdata->first_gpio;
+        chip->label = pdata->name;
+        chip->dev = &dev->dev;
+        chip->owner = THIS_MODULE;
+        ret = gpiochip_add(&nmk_chip->chip);
+        if (ret)
+                goto out_free;
+        amba_set_drvdata(dev, nmk_chip);
+        nmk_gpio_init_irq(nmk_chip);
+        dev_info(&dev->dev, "Bits %i-%i at address %p\n",
+                 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr);
+        return 0;
+ out_free:
+        kfree(nmk_chip);
+ out_amba:
+        amba_release_regions(dev);
+        dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret,
+                  pdata->first_gpio, pdata->first_gpio+31);
+        return ret;
+}
+static int nmk_gpio_remove(struct amba_device *dev)
+{
+        struct nmk_gpio_chip *nmk_chip;
+        nmk_chip = amba_get_drvdata(dev);
+        gpiochip_remove(&nmk_chip->chip);
+        kfree(nmk_chip);
+        amba_release_regions(dev);
+        return 0;
+}
+/* We have 0x1f080060 and 0x1f180060, accept both using the mask */
+static struct amba_id nmk_gpio_ids[] = {
+        {
+                .id     = 0x1f080060,
+                .mask   = 0xffefffff,
+        },
+        {0, 0},
+};
+static struct amba_driver nmk_gpio_driver = {
+        .drv = {
+                .owner = THIS_MODULE,
+                .name = "gpio",
+                },
+        .probe = nmk_gpio_probe,
+        .remove = nmk_gpio_remove,
+        .suspend = NULL, /* to be done */
+        .resume = NULL,
+        .id_table = nmk_gpio_ids,
+};
+static int __init nmk_gpio_init(void)
+{
+        return amba_driver_register(&nmk_gpio_driver);
+}
+arch_initcall(nmk_gpio_init);
+MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini");
+MODULE_DESCRIPTION("Nomadik GPIO Driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-nomadik/i2c-8815nhk.c b/arch/arm/mach-nomadik/i2c-8815nhk.c
new file mode 100644
index 000000000000..abfe25a08d6b
--- /dev/null
+++ b/arch/arm/mach-nomadik/i2c-8815nhk.c
@@ -0,0 +1,65 @@
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+#include <linux/i2c-gpio.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+/*
+ * There are two busses in the 8815NHK.
+ * They could, in theory, be driven by the hardware component, but we
+ * use bit-bang through GPIO by now, to keep things simple
+ */
+static struct i2c_gpio_platform_data nhk8815_i2c_data0 = {
+        /* keep defaults for timeouts; pins are push-pull bidirectional */
+        .scl_pin = 62,
+        .sda_pin = 63,
+};
+static struct i2c_gpio_platform_data nhk8815_i2c_data1 = {
+        /* keep defaults for timeouts; pins are push-pull bidirectional */
+        .scl_pin = 53,
+        .sda_pin = 54,
+};
+/* first bus: GPIO XX and YY */
+static struct platform_device nhk8815_i2c_dev0 = {
+        .name   = "i2c-gpio",
+        .id     = 0,
+        .dev    = {
+                .platform_data = &nhk8815_i2c_data0,
+        },
+};
+/* second bus: GPIO XX and YY */
+static struct platform_device nhk8815_i2c_dev1 = {
+        .name   = "i2c-gpio",
+        .id     = 1,
+        .dev    = {
+                .platform_data = &nhk8815_i2c_data1,
+        },
+};
+static int __init nhk8815_i2c_init(void)
+{
+        nmk_gpio_set_mode(nhk8815_i2c_data0.scl_pin, NMK_GPIO_ALT_GPIO);
+        nmk_gpio_set_mode(nhk8815_i2c_data0.sda_pin, NMK_GPIO_ALT_GPIO);
+        platform_device_register(&nhk8815_i2c_dev0);
+        nmk_gpio_set_mode(nhk8815_i2c_data1.scl_pin, NMK_GPIO_ALT_GPIO);
+        nmk_gpio_set_mode(nhk8815_i2c_data1.sda_pin, NMK_GPIO_ALT_GPIO);
+        platform_device_register(&nhk8815_i2c_dev1);
+        return 0;
+}
+static void __exit nhk8815_i2c_exit(void)
+{
+        platform_device_unregister(&nhk8815_i2c_dev0);
+        platform_device_unregister(&nhk8815_i2c_dev1);
+        return;
+}
+module_init(nhk8815_i2c_init);
+module_exit(nhk8815_i2c_exit);
diff --git a/arch/arm/mach-nomadik/include/mach/clkdev.h b/arch/arm/mach-nomadik/include/mach/clkdev.h
new file mode 100644
index 000000000000..04b37a89801c
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_MACH_CLKDEV_H
+#define __ASM_MACH_CLKDEV_H
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S
new file mode 100644
index 000000000000..e876990e1569
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x10000000        @ physical base address
+                movne   \rx, #0xf0000000        @ virtual base
+                add     \rx, \rx, #0x00100000
+                add     \rx, \rx, #0x000fb000
+                .endm
+#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-nomadik/include/mach/entry-macro.S b/arch/arm/mach-nomadik/include/mach/entry-macro.S
new file mode 100644
index 000000000000..49f1aa3bb420
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/entry-macro.S
@@ -0,0 +1,43 @@
+/*
+ * Low-level IRQ helper macros for Nomadik platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =IO_ADDRESS(NOMADIK_IC_BASE)
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        /* This stanza gets the irq mask from one of two status registers */
+        mov     \irqnr, #0
+        ldr     \irqstat, [\base, #VIC_REG_IRQSR0]      @ get masked status
+        cmp     \irqstat, #0
+        bne     1001f
+        add     \irqnr, \irqnr, #32
+        ldr     \irqstat, [\base, #VIC_REG_IRQSR1]      @ get masked status
+1001:   tst     \irqstat, #15
+        bne     1002f
+        add     \irqnr, \irqnr, #4
+        movs    \irqstat, \irqstat, lsr #4
+        bne     1001b
+1002:   tst     \irqstat, #1
+        bne     1003f
+        add     \irqnr, \irqnr, #1
+        movs    \irqstat, \irqstat, lsr #1
+        bne     1002b
+1003:   /* EQ will be set if no irqs pending */
+        .endm
diff --git a/arch/arm/mach-nomadik/include/mach/gpio.h b/arch/arm/mach-nomadik/include/mach/gpio.h
new file mode 100644
index 000000000000..61577c9f9a7d
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/gpio.h
@@ -0,0 +1,71 @@
+/*
+ * Structures and registers for GPIO access in the Nomadik SoC
+ *
+ * Copyright (C) 2008 STMicroelectronics
+ *     Author: Prafulla WADASKAR <prafulla.wadaskar@st.com>
+ * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+#include <asm-generic/gpio.h>
+/*
+ * These currently cause a function call to happen, they may be optimized
+ * if needed by adding cpu-specific defines to identify blocks
+ * (see mach-pxa/include/mach/gpio.h as an example using GPLR etc)
+ */
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+/*
+ * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
+ * the "gpio" namespace for generic and cross-machine functions
+ */
+/* Register in the logic block */
+#define NMK_GPIO_DAT    0x00
+#define NMK_GPIO_DATS   0x04
+#define NMK_GPIO_DATC   0x08
+#define NMK_GPIO_PDIS   0x0c
+#define NMK_GPIO_DIR    0x10
+#define NMK_GPIO_DIRS   0x14
+#define NMK_GPIO_DIRC   0x18
+#define NMK_GPIO_SLPC   0x1c
+#define NMK_GPIO_AFSLA  0x20
+#define NMK_GPIO_AFSLB  0x24
+#define NMK_GPIO_RIMSC  0x40
+#define NMK_GPIO_FIMSC  0x44
+#define NMK_GPIO_IS     0x48
+#define NMK_GPIO_IC     0x4c
+#define NMK_GPIO_RWIMSC 0x50
+#define NMK_GPIO_FWIMSC 0x54
+#define NMK_GPIO_WKS    0x58
+/* Alternate functions: function C is set in hw by setting both A and B */
+#define NMK_GPIO_ALT_GPIO       0
+#define NMK_GPIO_ALT_A  1
+#define NMK_GPIO_ALT_B  2
+#define NMK_GPIO_ALT_C  (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
+extern int nmk_gpio_set_mode(int gpio, int gpio_mode);
+extern int nmk_gpio_get_mode(int gpio);
+/*
+ * Platform data to register a block: only the initial gpio/irq number.
+ */
+struct nmk_gpio_platform_data {
+        char *name;
+        int first_gpio;
+        int first_irq;
+        int parent_irq;
+};
+#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-nomadik/include/mach/hardware.h b/arch/arm/mach-nomadik/include/mach/hardware.h
new file mode 100644
index 000000000000..6316dba3bfc8
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/hardware.h
@@ -0,0 +1,90 @@
+/*
+ * This file contains the hardware definitions of the Nomadik.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * YOU should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+/* Nomadik registers live from 0x1000.0000 to 0x1023.0000 -- currently */
+#define NOMADIK_IO_VIRTUAL      0xF0000000      /* VA of IO  */
+#define NOMADIK_IO_PHYSICAL     0x10000000      /* PA of IO */
+#define NOMADIK_IO_SIZE         0x00300000      /* 3MB for all regs */
+/* used in C code, so cast to proper type */
+#define io_p2v(x) ((void __iomem *)(x) \
+                        - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+#define io_v2p(x) ((unsigned long)(x) \
+                        - NOMADIK_IO_VIRTUAL + NOMADIK_IO_PHYSICAL)
+/* used in asm code, so no casts */
+#define IO_ADDRESS(x) ((x) - NOMADIK_IO_PHYSICAL + NOMADIK_IO_VIRTUAL)
+/*
+ *   Base address defination for Nomadik Onchip Logic Block
+ */
+#define NOMADIK_FSMC_BASE       0x10100000      /* FSMC registers */
+#define NOMADIK_SDRAMC_BASE     0x10110000      /* SDRAM Controller */
+#define NOMADIK_CLCDC_BASE      0x10120000      /* CLCD Controller */
+#define NOMADIK_MDIF_BASE       0x10120000      /* MDIF */
+#define NOMADIK_DMA0_BASE       0x10130000      /* DMA0 Controller */
+#define NOMADIK_IC_BASE         0x10140000      /* Vectored Irq Controller */
+#define NOMADIK_DMA1_BASE       0x10150000      /* DMA1 Controller */
+#define NOMADIK_USB_BASE        0x10170000      /* USB-OTG conf reg base */
+#define NOMADIK_CRYP_BASE       0x10180000      /* Crypto processor */
+#define NOMADIK_SHA1_BASE       0x10190000      /* SHA-1 Processor */
+#define NOMADIK_XTI_BASE        0x101A0000      /* XTI */
+#define NOMADIK_RNG_BASE        0x101B0000      /* Random number generator */
+#define NOMADIK_SRC_BASE        0x101E0000      /* SRC base */
+#define NOMADIK_WDOG_BASE       0x101E1000      /* Watchdog */
+#define NOMADIK_MTU0_BASE       0x101E2000      /* Multiple Timer 0 */
+#define NOMADIK_MTU1_BASE       0x101E3000      /* Multiple Timer 1 */
+#define NOMADIK_GPIO0_BASE      0x101E4000      /* GPIO0 */
+#define NOMADIK_GPIO1_BASE      0x101E5000      /* GPIO1 */
+#define NOMADIK_GPIO2_BASE      0x101E6000      /* GPIO2 */
+#define NOMADIK_GPIO3_BASE      0x101E7000      /* GPIO3 */
+#define NOMADIK_RTC_BASE        0x101E8000      /* Real Time Clock base */
+#define NOMADIK_PMU_BASE        0x101E9000      /* Power Management Unit */
+#define NOMADIK_OWM_BASE        0x101EA000      /* One wire master */
+#define NOMADIK_SCR_BASE        0x101EF000      /* Secure Control registers */
+#define NOMADIK_MSP2_BASE       0x101F0000      /* MSP 2 interface */
+#define NOMADIK_MSP1_BASE       0x101F1000      /* MSP 1 interface */
+#define NOMADIK_UART2_BASE      0x101F2000      /* UART 2 interface */
+#define NOMADIK_SSIRx_BASE      0x101F3000      /* SSI 8-ch rx interface */
+#define NOMADIK_SSITx_BASE      0x101F4000      /* SSI 8-ch tx interface */
+#define NOMADIK_MSHC_BASE       0x101F5000      /* Memory Stick(Pro) Host */
+#define NOMADIK_SDI_BASE        0x101F6000      /* SD-card/MM-Card */
+#define NOMADIK_I2C1_BASE       0x101F7000      /* I2C1 interface */
+#define NOMADIK_I2C0_BASE       0x101F8000      /* I2C0 interface */
+#define NOMADIK_MSP0_BASE       0x101F9000      /* MSP 0 interface  */
+#define NOMADIK_FIRDA_BASE      0x101FA000      /* FIrDA interface  */
+#define NOMADIK_UART1_BASE      0x101FB000      /* UART 1 interface */
+#define NOMADIK_SSP_BASE        0x101FC000      /* SSP interface  */
+#define NOMADIK_UART0_BASE      0x101FD000      /* UART 0 interface */
+#define NOMADIK_SGA_BASE        0x101FE000      /* SGA interface */
+#define NOMADIK_L2CC_BASE       0x10210000      /* L2 Cache controller */
+/* Other ranges, not for p2v/v2p */
+#define NOMADIK_BACKUP_RAM      0x80010000
+#define NOMADIK_EBROM           0x80000000      /* Embedded boot ROM */
+#define NOMADIK_HAMACV_DMEM_BASE 0xA0100000     /* HAMACV Data Memory Start */
+#define NOMADIK_HAMACV_DMEM_END 0xA01FFFFF      /* HAMACV Data Memory End */
+#define NOMADIK_HAMACA_DMEM     0xA0200000      /* HAMACA Data Memory Space */
+#define NOMADIK_FSMC_VA         IO_ADDRESS(NOMADIK_FSMC_BASE)
+#define NOMADIK_MTU0_VA         IO_ADDRESS(NOMADIK_MTU0_BASE)
+#define NOMADIK_MTU1_VA         IO_ADDRESS(NOMADIK_MTU1_BASE)
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-nomadik/include/mach/io.h b/arch/arm/mach-nomadik/include/mach/io.h
new file mode 100644
index 000000000000..2e1eca1b8243
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * arch/arm/mach-nomadik/include/mach/io.h   (copied from mach-sa1100)
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+#define IO_SPACE_LIMIT 0xffffffff
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)         __typesafe_io(a)
+#define __mem_pci(a)    (a)
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/irqs.h b/arch/arm/mach-nomadik/include/mach/irqs.h
new file mode 100644
index 000000000000..8faabc560398
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/irqs.h
@@ -0,0 +1,82 @@
+/*
+ *  mach-nomadik/include/mach/irqs.h
+ *
+ *  Copyright (C) ST Microelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+#include <mach/hardware.h>
+#define IRQ_VIC_START           0       /* first VIC interrupt is 0 */
+/*
+ * Interrupt numbers generic for all Nomadik Chip cuts
+ */
+#define IRQ_WATCHDOG                    0
+#define IRQ_SOFTINT                     1
+#define IRQ_CRYPTO                      2
+#define IRQ_OWM                         3
+#define IRQ_MTU0                        4
+#define IRQ_MTU1                        5
+#define IRQ_GPIO0                       6
+#define IRQ_GPIO1                       7
+#define IRQ_GPIO2                       8
+#define IRQ_GPIO3                       9
+#define IRQ_RTC_RTT                     10
+#define IRQ_SSP                         11
+#define IRQ_UART0                       12
+#define IRQ_DMA1                        13
+#define IRQ_CLCD_MDIF                   14
+#define IRQ_DMA0                        15
+#define IRQ_PWRFAIL                     16
+#define IRQ_UART1                       17
+#define IRQ_FIRDA                       18
+#define IRQ_MSP0                        19
+#define IRQ_I2C0                        20
+#define IRQ_I2C1                        21
+#define IRQ_SDMMC                       22
+#define IRQ_USBOTG                      23
+#define IRQ_SVA_IT0                     24
+#define IRQ_SVA_IT1                     25
+#define IRQ_SAA_IT0                     26
+#define IRQ_SAA_IT1                     27
+#define IRQ_UART2                       28
+#define IRQ_MSP2                        31
+#define IRQ_L2CC                        48
+#define IRQ_HPI                         49
+#define IRQ_SKE                         50
+#define IRQ_KP                          51
+#define IRQ_MEMST                       54
+#define IRQ_SGA_IT                      58
+#define IRQ_USBM                        60
+#define IRQ_MSP1                        62
+#define NOMADIK_SOC_NR_IRQS             64
+/* After chip-specific IRQ numbers we have the GPIO ones */
+#define NOMADIK_NR_GPIO                 128 /* last 4 not wired to pins */
+#define NOMADIK_GPIO_TO_IRQ(gpio)       ((gpio) + NOMADIK_SOC_NR_IRQS)
+#define NOMADIK_IRQ_TO_GPIO(irq)        ((irq) - NOMADIK_SOC_NR_IRQS)
+#define NR_IRQS                         NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+/* Following two are used by entry_macro.S, to access our dual-vic */
+#define VIC_REG_IRQSR0          0
+#define VIC_REG_IRQSR1          0x20
+#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-nomadik/include/mach/memory.h b/arch/arm/mach-nomadik/include/mach/memory.h
new file mode 100644
index 000000000000..1e5689d98ecd
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/memory.h
@@ -0,0 +1,28 @@
+/*
+ *  mach-nomadik/include/mach/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     UL(0x00000000)
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/mtu.h b/arch/arm/mach-nomadik/include/mach/mtu.h
new file mode 100644
index 000000000000..76da7f085330
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/mtu.h
@@ -0,0 +1,45 @@
+#ifndef __ASM_ARCH_MTU_H
+#define __ASM_ARCH_MTU_H
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
+#define MTU_RIS         0x04    /* Raw interrupt status */
+#define MTU_MIS         0x08    /* Masked interrupt status */
+#define MTU_ICR         0x0C    /* Interrupt clear register */
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
+#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
+#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
+#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
+/* bits for the control register */
+#define MTU_CRn_ENA             0x80
+#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK   0x0c
+#define MTU_CRn_PRESCALE_1              0x00
+#define MTU_CRn_PRESCALE_16             0x04
+#define MTU_CRn_PRESCALE_256            0x08
+#define MTU_CRn_32BITS          0x02
+#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR        0xff0
+#define MTU_ITOP        0xff4
+#define MTU_PERIPH_ID0  0xfe0
+#define MTU_PERIPH_ID1  0xfe4
+#define MTU_PERIPH_ID2  0xfe8
+#define MTU_PERIPH_ID3  0xfeC
+#define MTU_PCELL0      0xff0
+#define MTU_PCELL1      0xff4
+#define MTU_PCELL2      0xff8
+#define MTU_PCELL3      0xffC
+#endif /* __ASM_ARCH_MTU_H */
diff --git a/arch/arm/mach-nomadik/include/mach/setup.h b/arch/arm/mach-nomadik/include/mach/setup.h
new file mode 100644
index 000000000000..a4e468cf63da
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/setup.h
@@ -0,0 +1,22 @@
+/*
+ * These symbols are needed for board-specific files to call their
+ * own cpu-specific files
+ */
+#ifndef __ASM_ARCH_SETUP_H
+#define __ASM_ARCH_SETUP_H
+#include <asm/mach/time.h>
+#include <linux/init.h>
+#ifdef CONFIG_NOMADIK_8815
+extern void cpu8815_map_io(void);
+extern void cpu8815_platform_init(void);
+extern void cpu8815_init_irq(void);
+extern struct sys_timer nomadik_timer;
+#endif /* NOMADIK_8815 */
+#endif /*  __ASM_ARCH_SETUP_H */
diff --git a/arch/arm/mach-nomadik/include/mach/system.h b/arch/arm/mach-nomadik/include/mach/system.h
new file mode 100644
index 000000000000..7119f688116e
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/system.h
@@ -0,0 +1,45 @@
+/*
+ *  mach-nomadik/include/mach/system.h
+ *
+ *  Copyright (C) 2008 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/io.h>
+#include <mach/hardware.h>
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+static inline void arch_reset(char mode, const char *cmd)
+{
+        void __iomem *src_rstsr = io_p2v(NOMADIK_SRC_BASE + 0x18);
+        /* FIXME: use egpio when implemented */
+        /* Write anything to Reset status register */
+        writel(1, src_rstsr);
+}
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/timex.h b/arch/arm/mach-nomadik/include/mach/timex.h
new file mode 100644
index 000000000000..318b8896ce96
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/timex.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+#define CLOCK_TICK_RATE         2400000
+#endif
diff --git a/arch/arm/mach-nomadik/include/mach/uncompress.h b/arch/arm/mach-nomadik/include/mach/uncompress.h
new file mode 100644
index 000000000000..071003bc8456
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/uncompress.h
@@ -0,0 +1,63 @@
+/*
+ *  Copyright (C) 2008 STMicroelectronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+#include <asm/setup.h>
+#include <asm/io.h>
+#include <mach/hardware.h>
+/* we need the constants in amba/serial.h, but it refers to amba_device */
+struct amba_device;
+#include <linux/amba/serial.h>
+#define NOMADIK_UART_DR         0x101FB000
+#define NOMADIK_UART_LCRH       0x101FB02c
+#define NOMADIK_UART_CR         0x101FB030
+#define NOMADIK_UART_FR         0x101FB018
+static void putc(const char c)
+{
+        /* Do nothing if the UART is not enabled. */
+        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
+                return;
+        if (c == '\n')
+                putc('\r');
+        while (readb(NOMADIK_UART_FR) & UART01x_FR_TXFF)
+                barrier();
+        writeb(c, NOMADIK_UART_DR);
+}
+static void flush(void)
+{
+        if (!(readb(NOMADIK_UART_CR) & UART01x_CR_UARTEN))
+                return;
+        while (readb(NOMADIK_UART_FR) & UART01x_FR_BUSY)
+                barrier();
+}
+static inline void arch_decomp_setup(void)
+{
+}
+#define arch_decomp_wdog() /* nothing to do here */
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-nomadik/include/mach/vmalloc.h b/arch/arm/mach-nomadik/include/mach/vmalloc.h
new file mode 100644
index 000000000000..be12e31ea528
--- /dev/null
+++ b/arch/arm/mach-nomadik/include/mach/vmalloc.h
@@ -0,0 +1,2 @@
+#define VMALLOC_END       0xe8000000
diff --git a/arch/arm/mach-nomadik/timer.c b/arch/arm/mach-nomadik/timer.c
new file mode 100644
index 000000000000..d1738e7061d4
--- /dev/null
+++ b/arch/arm/mach-nomadik/timer.c
@@ -0,0 +1,164 @@
+/*
+ *  linux/arch/arm/mach-nomadik/timer.c
+ *
+ * Copyright (C) 2008 STMicroelectronics
+ * Copyright (C) 2009 Alessandro Rubini, somewhat based on at91sam926x
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/jiffies.h>
+#include <asm/mach/time.h>
+#include <mach/mtu.h>
+#define TIMER_CTRL      0x80    /* No divisor */
+#define TIMER_PERIODIC  0x40
+#define TIMER_SZ32BIT   0x02
+/* Initial value for SRC control register: all timers use MXTAL/8 source */
+#define SRC_CR_INIT_MASK        0x00007fff
+#define SRC_CR_INIT_VAL         0x2aaa8000
+static u32      nmdk_count;             /* accumulated count */
+static u32      nmdk_cycle;             /* write-once */
+static __iomem void *mtu_base;
+/*
+ * clocksource: the MTU device is a decrementing counters, so we negate
+ * the value being read.
+ */
+static cycle_t nmdk_read_timer(struct clocksource *cs)
+{
+        u32 count = readl(mtu_base + MTU_VAL(0));
+        return nmdk_count + nmdk_cycle - count;
+}
+static struct clocksource nmdk_clksrc = {
+        .name           = "mtu_0",
+        .rating         = 120,
+        .read           = nmdk_read_timer,
+        .shift          = 20,
+        .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+/*
+ * Clockevent device: currently only periodic mode is supported
+ */
+static void nmdk_clkevt_mode(enum clock_event_mode mode,
+                             struct clock_event_device *dev)
+{
+        unsigned long flags;
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* enable interrupts -- and count current value? */
+                raw_local_irq_save(flags);
+                writel(readl(mtu_base + MTU_IMSC) | 1, mtu_base + MTU_IMSC);
+                raw_local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                BUG(); /* Not supported, yet */
+                /* FALLTHROUGH */
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                /* disable irq */
+                raw_local_irq_save(flags);
+                writel(readl(mtu_base + MTU_IMSC) & ~1, mtu_base + MTU_IMSC);
+                raw_local_irq_restore(flags);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+static struct clock_event_device nmdk_clkevt = {
+        .name           = "mtu_0",
+        .features       = CLOCK_EVT_FEAT_PERIODIC,
+        .shift          = 32,
+        .rating         = 100,
+        .set_mode       = nmdk_clkevt_mode,
+};
+/*
+ * IRQ Handler for the timer 0 of the MTU block. The irq is not shared
+ * as we are the only users of mtu0 by now.
+ */
+static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
+{
+        /* ack: "interrupt clear register" */
+        writel( 1 << 0, mtu_base + MTU_ICR);
+        /* we can't count lost ticks, unfortunately */
+        nmdk_count += nmdk_cycle;
+        nmdk_clkevt.event_handler(&nmdk_clkevt);
+        return IRQ_HANDLED;
+}
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+static struct irqaction nmdk_timer_irq = {
+        .name           = "Nomadik Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = nmdk_timer_interrupt,
+};
+static void nmdk_timer_reset(void)
+{
+        u32 cr;
+        writel(0, mtu_base + MTU_CR(0)); /* off */
+        /* configure load and background-load, and fire it up */
+        writel(nmdk_cycle, mtu_base + MTU_LR(0));
+        writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
+        cr = MTU_CRn_PERIODIC | MTU_CRn_PRESCALE_1 | MTU_CRn_32BITS;
+        writel(cr, mtu_base + MTU_CR(0));
+        writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
+}
+static void __init nmdk_timer_init(void)
+{
+        u32 src_cr;
+        unsigned long rate;
+        int bits;
+        rate = CLOCK_TICK_RATE; /* 2.4MHz */
+        nmdk_cycle = (rate + HZ/2) / HZ;
+        /* Configure timer sources in "system reset controller" ctrl reg */
+        src_cr = readl(io_p2v(NOMADIK_SRC_BASE));
+        src_cr &= SRC_CR_INIT_MASK;
+        src_cr |= SRC_CR_INIT_VAL;
+        writel(src_cr, io_p2v(NOMADIK_SRC_BASE));
+        /* Save global pointer to mtu, used by functions above */
+        mtu_base = io_p2v(NOMADIK_MTU0_BASE);
+        /* Init the timer and register clocksource */
+        nmdk_timer_reset();
+        nmdk_clksrc.mult = clocksource_hz2mult(rate, nmdk_clksrc.shift);
+        bits =  8*sizeof(nmdk_count);
+        nmdk_clksrc.mask = CLOCKSOURCE_MASK(bits);
+        clocksource_register(&nmdk_clksrc);
+        /* Register irq and clockevents */
+        setup_irq(IRQ_MTU0, &nmdk_timer_irq);
+        nmdk_clkevt.mult = div_sc(rate, NSEC_PER_SEC, nmdk_clkevt.shift);
+        nmdk_clkevt.cpumask = cpumask_of(0);
+        clockevents_register_device(&nmdk_clkevt);
+}
+struct sys_timer nomadik_timer = {
+        .init           = nmdk_timer_init,
+};
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index b0c7402248f7..1b223076ceb7 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -39,7 +39,7 @@ static struct platform_device *sdp4430_devices[] __initdata = {
 };
 static struct omap_uart_config sdp4430_uart_config __initdata = {
-        .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2),
+        .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
 };
 static struct omap_lcd_config sdp4430_lcd_config __initdata = {
diff --git a/arch/arm/mach-omap2/mcbsp.c b/arch/arm/mach-omap2/mcbsp.c
index 99b6e1546311..a846aa1ebb4d 100644
--- a/arch/arm/mach-omap2/mcbsp.c
+++ b/arch/arm/mach-omap2/mcbsp.c
@@ -128,6 +128,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
                .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
        },
        {
                .phys_base      = OMAP34XX_MCBSP2_BASE,
@@ -136,6 +137,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
                .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x3FF,
        },
        {
                .phys_base      = OMAP34XX_MCBSP3_BASE,
@@ -144,6 +146,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
                .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
        },
        {
                .phys_base      = OMAP34XX_MCBSP4_BASE,
@@ -152,6 +155,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
                .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
        },
        {
                .phys_base      = OMAP34XX_MCBSP5_BASE,
@@ -160,6 +164,7 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
                .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
                .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
                .ops            = &omap2_mcbsp_ops,
+                .buffer_size    = 0x6F,
        },
 };
 #define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
@@ -168,6 +173,42 @@ static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
 #define OMAP34XX_MCBSP_PDATA_SZ         0
 #endif
+static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
+        {
+                .phys_base      = OMAP44XX_MCBSP1_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
+                .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP2_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
+                .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP3_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
+                .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+        {
+                .phys_base      = OMAP44XX_MCBSP4_BASE,
+                .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
+                .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
+                .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
+                .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
+                .ops            = &omap2_mcbsp_ops,
+        },
+};
+#define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
 static int __init omap2_mcbsp_init(void)
 {
        if (cpu_is_omap2420())
@@ -176,6 +217,8 @@ static int __init omap2_mcbsp_init(void)
                omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
        if (cpu_is_omap34xx())
                omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
+        if (cpu_is_omap44xx())
+                omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
        mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
                                                                GFP_KERNEL);
@@ -191,6 +234,9 @@ static int __init omap2_mcbsp_init(void)
        if (cpu_is_omap34xx())
                omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
                                                OMAP34XX_MCBSP_PDATA_SZ);
+        if (cpu_is_omap44xx())
+                omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
+                                                OMAP44XX_MCBSP_PDATA_SZ);
        return omap_mcbsp_init();
 }
diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c
index a7421a50410b..ce22344b94e7 100644
--- a/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@ -109,6 +109,16 @@ static struct plat_serial8250_port serial_platform_data2[] = {
                .regshift       = 2,
                .uartclk        = OMAP24XX_BASE_BAUD * 16,
        }, {
+#ifdef CONFIG_ARCH_OMAP4
+                .membase        = IO_ADDRESS(OMAP_UART4_BASE),
+                .mapbase        = OMAP_UART4_BASE,
+                .irq            = 70,
+                .flags          = UPF_BOOT_AUTOCONF,
+                .iotype         = UPIO_MEM,
+                .regshift       = 2,
+                .uartclk        = OMAP24XX_BASE_BAUD * 16,
+        }, {
+#endif
                .flags          = 0
        }
 };
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index 2c7035d8dcbf..c3d513cad5ac 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -89,6 +89,27 @@ config MACH_EDMINI_V2
          Say 'Y' here if you want your kernel to support the
          LaCie Ethernet Disk mini V2.
+config MACH_D2NET
+        bool "LaCie d2 Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie d2 Network NAS.
+config MACH_BIGDISK
+        bool "LaCie Big Disk Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie Big Disk Network NAS.
+config MACH_NET2BIG
+        bool "LaCie 2Big Network"
+        select I2C_BOARDINFO
+        help
+          Say 'Y' here if you want your kernel to support the
+          LaCie 2Big Network NAS.
 config MACH_MSS2
        bool "Maxtor Shared Storage II"
        help
diff --git a/arch/arm/mach-orion5x/Makefile b/arch/arm/mach-orion5x/Makefile
index edc38e2c856f..89772fcd65c7 100644
--- a/arch/arm/mach-orion5x/Makefile
+++ b/arch/arm/mach-orion5x/Makefile
@@ -12,6 +12,9 @@ obj-$(CONFIG_MACH_WRT350N_V2)	+= wrt350n-v2-setup.o
 obj-$(CONFIG_MACH_TS78XX)       += ts78xx-setup.o
 obj-$(CONFIG_MACH_MV2120)       += mv2120-setup.o
 obj-$(CONFIG_MACH_EDMINI_V2)    += edmini_v2-setup.o
+obj-$(CONFIG_MACH_D2NET)        += d2net-setup.o
+obj-$(CONFIG_MACH_BIGDISK)      += d2net-setup.o
+obj-$(CONFIG_MACH_NET2BIG)      += net2big-setup.o
 obj-$(CONFIG_MACH_MSS2)         += mss2-setup.o
 obj-$(CONFIG_MACH_WNR854T)      += wnr854t-setup.o
 obj-$(CONFIG_MACH_RD88F5181L_GE)        += rd88f5181l-ge-setup.o
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index d78731edebb6..1a5d6a0e2602 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -84,7 +84,8 @@ static int __init orion5x_cpu_win_can_remap(int win)
        orion5x_pcie_id(&dev, &rev);
        if ((dev == MV88F5281_DEV_ID && win < 4)
            || (dev == MV88F5182_DEV_ID && win < 2)
-            || (dev == MV88F5181_DEV_ID && win < 2))
+            || (dev == MV88F5181_DEV_ID && win < 2)
+            || (dev == MV88F6183_DEV_ID && win < 4))
                return 1;
        return 0;
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
new file mode 100644
index 000000000000..9d4bf763f25b
--- /dev/null
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -0,0 +1,365 @@
+/*
+ * arch/arm/mach-orion5x/d2net-setup.c
+ *
+ * LaCie d2Network and Big Disk Network NAS setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/pci.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/pci.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+/*****************************************************************************
+ * LaCie d2 Network Info
+ ****************************************************************************/
+/*
+ * 512KB NOR flash Device bus boot chip select
+ */
+#define D2NET_NOR_BOOT_BASE             0xfff80000
+#define D2NET_NOR_BOOT_SIZE             SZ_512K
+/*****************************************************************************
+ * 512KB NOR Flash on Boot Device
+ ****************************************************************************/
+/*
+ * TODO: Check write support on flash MX29LV400CBTC-70G
+ */
+static struct mtd_partition d2net_partitions[] = {
+        {
+                .name           = "Full512kb",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+static struct physmap_flash_data d2net_nor_flash_data = {
+        .width          = 1,
+        .parts          = d2net_partitions,
+        .nr_parts       = ARRAY_SIZE(d2net_partitions),
+};
+static struct resource d2net_nor_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+        .start                  = D2NET_NOR_BOOT_BASE,
+        .end                    = D2NET_NOR_BOOT_BASE
+                                        + D2NET_NOR_BOOT_SIZE - 1,
+};
+static struct platform_device d2net_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &d2net_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &d2net_nor_flash_resource,
+};
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+static struct mv643xx_eth_platform_data d2net_eth_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+/*
+ * i2c addr | chip         | description
+ * 0x32     | Ricoh 5C372b | RTC
+ * 0x3e     | GMT G762     | PWM fan controller
+ * 0x50     | HT24LC08     | eeprom (1kB)
+ *
+ * TODO: Add G762 support to the g760a driver.
+ */
+static struct i2c_board_info __initdata d2net_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rs5c372b", 0x32),
+        }, {
+                I2C_BOARD_INFO("24c08", 0x50),
+        },
+};
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data d2net_sata_data = {
+        .n_ports        = 2,
+};
+#define D2NET_GPIO_SATA0_POWER  3
+#define D2NET_GPIO_SATA1_POWER  12
+static void __init d2net_sata_power_init(void)
+{
+        int err;
+        err = gpio_request(D2NET_GPIO_SATA0_POWER, "SATA0 power");
+        if (err == 0) {
+                err = gpio_direction_output(D2NET_GPIO_SATA0_POWER, 1);
+                if (err)
+                        gpio_free(D2NET_GPIO_SATA0_POWER);
+        }
+        if (err)
+                pr_err("d2net: failed to configure SATA0 power GPIO\n");
+        err = gpio_request(D2NET_GPIO_SATA1_POWER, "SATA1 power");
+        if (err == 0) {
+                err = gpio_direction_output(D2NET_GPIO_SATA1_POWER, 1);
+                if (err)
+                        gpio_free(D2NET_GPIO_SATA1_POWER);
+        }
+        if (err)
+                pr_err("d2net: failed to configure SATA1 power GPIO\n");
+}
+/*****************************************************************************
+ * GPIO LED's
+ ****************************************************************************/
+/*
+ * The blue front LED is wired to the CPLD and can blink in relation with the
+ * SATA activity. This feature is disabled to make this LED compatible with
+ * the leds-gpio driver: MPP14 and MPP15 are configured to act like output
+ * GPIO's and have to stay in an active state. This is needed to set the blue
+ * LED in a "fix on" state regardless of the SATA activity.
+ *
+ * The following array detail the different LED registers and the combination
+ * of their possible values:
+ *
+ * led_off   | blink_ctrl | SATA active | LED state
+ *           |            |             |
+ *    1      |     x      |      x      |  off
+ *    0      |     0      |      0      |  off
+ *    0      |     1      |      0      |  blink (rate 300ms)
+ *    0      |     x      |      1      |  on
+ *
+ * Notes: The blue and the red front LED's can't be on at the same time.
+ *        Red LED have priority.
+ */
+#define D2NET_GPIO_RED_LED              6
+#define D2NET_GPIO_BLUE_LED_BLINK_CTRL  16
+#define D2NET_GPIO_BLUE_LED_OFF         23
+#define D2NET_GPIO_SATA0_ACT            14
+#define D2NET_GPIO_SATA1_ACT            15
+static struct gpio_led d2net_leds[] = {
+        {
+                .name = "d2net:blue:power",
+                .gpio = D2NET_GPIO_BLUE_LED_OFF,
+                .active_low = 1,
+        },
+        {
+                .name = "d2net:red:fail",
+                .gpio = D2NET_GPIO_RED_LED,
+        },
+};
+static struct gpio_led_platform_data d2net_led_data = {
+        .num_leds = ARRAY_SIZE(d2net_leds),
+        .leds = d2net_leds,
+};
+static struct platform_device d2net_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_led_data,
+        },
+};
+static void __init d2net_gpio_leds_init(void)
+{
+        /* Configure GPIO over MPP max number. */
+        orion_gpio_set_valid(D2NET_GPIO_BLUE_LED_OFF, 1);
+        if (gpio_request(D2NET_GPIO_SATA0_ACT, "LED SATA0 activity") != 0)
+                return;
+        if (gpio_direction_output(D2NET_GPIO_SATA0_ACT, 1) != 0)
+                goto err_free_1;
+        if (gpio_request(D2NET_GPIO_SATA1_ACT, "LED SATA1 activity") != 0)
+                goto err_free_1;
+        if (gpio_direction_output(D2NET_GPIO_SATA1_ACT, 1) != 0)
+                goto err_free_2;
+        platform_device_register(&d2net_gpio_leds);
+        return;
+err_free_2:
+        gpio_free(D2NET_GPIO_SATA1_ACT);
+err_free_1:
+        gpio_free(D2NET_GPIO_SATA0_ACT);
+        return;
+}
+/****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+#define D2NET_GPIO_PUSH_BUTTON          18
+#define D2NET_GPIO_POWER_SWITCH_ON      8
+#define D2NET_GPIO_POWER_SWITCH_OFF     9
+#define D2NET_SWITCH_POWER_ON           0x1
+#define D2NET_SWITCH_POWER_OFF          0x2
+static struct gpio_keys_button d2net_buttons[] = {
+        {
+                .type           = EV_SW,
+                .code           = D2NET_SWITCH_POWER_OFF,
+                .gpio           = D2NET_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Power rocker switch (auto|off)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_SW,
+                .code           = D2NET_SWITCH_POWER_ON,
+                .gpio           = D2NET_GPIO_POWER_SWITCH_ON,
+                .desc           = "Power rocker switch (on|auto)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_KEY,
+                .code           = KEY_POWER,
+                .gpio           = D2NET_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 0,
+        },
+};
+static struct gpio_keys_platform_data d2net_button_data = {
+        .buttons        = d2net_buttons,
+        .nbuttons       = ARRAY_SIZE(d2net_buttons),
+};
+static struct platform_device d2net_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &d2net_button_data,
+        },
+};
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },       /* Board ID (bit 0) */
+        {  1, MPP_GPIO },       /* Board ID (bit 1) */
+        {  2, MPP_GPIO },       /* Board ID (bit 2) */
+        {  3, MPP_GPIO },       /* SATA 0 power */
+        {  4, MPP_UNUSED },
+        {  5, MPP_GPIO },       /* Fan fail detection */
+        {  6, MPP_GPIO },       /* Red front LED */
+        {  7, MPP_UNUSED },
+        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
+        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
+        { 10, MPP_UNUSED },
+        { 11, MPP_UNUSED },
+        { 12, MPP_GPIO },       /* SATA 1 power */
+        { 13, MPP_UNUSED },
+        { 14, MPP_GPIO },       /* SATA 0 active */
+        { 15, MPP_GPIO },       /* SATA 1 active */
+        { 16, MPP_GPIO },       /* Blue front LED blink control */
+        { 17, MPP_UNUSED },
+        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
+        { 19, MPP_UNUSED },
+        { -1 }
+        /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
+        /* 23: Blue front LED off */
+        /* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
+};
+static void __init d2net_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+        orion5x_mpp_conf(d2net_mpp_modes);
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_eth_init(&d2net_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+        d2net_sata_power_init();
+        orion5x_sata_init(&d2net_sata_data);
+        orion5x_setup_dev_boot_win(D2NET_NOR_BOOT_BASE,
+                                D2NET_NOR_BOOT_SIZE);
+        platform_device_register(&d2net_nor_flash);
+        platform_device_register(&d2net_gpio_buttons);
+        d2net_gpio_leds_init();
+        pr_notice("d2net: Flash write are not yet supported.\n");
+        i2c_register_board_info(0, d2net_i2c_devices,
+                                ARRAY_SIZE(d2net_i2c_devices));
+}
+/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
+#ifdef CONFIG_MACH_D2NET
+MACHINE_START(D2NET, "LaCie d2 Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
+#ifdef CONFIG_MACH_BIGDISK
+MACHINE_START(BIGDISK, "LaCie Big Disk Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = d2net_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
new file mode 100644
index 000000000000..7bd6283476f9
--- /dev/null
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -0,0 +1,431 @@
+/*
+ * arch/arm/mach-orion5x/net2big-setup.c
+ *
+ * LaCie 2Big Network NAS setup
+ *
+ * Copyright (C) 2009 Simon Guinot <sguinot@lacie.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/leds.h>
+#include <linux/gpio_keys.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/ata_platform.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/orion5x.h>
+#include "common.h"
+#include "mpp.h"
+/*****************************************************************************
+ * LaCie 2Big Network Info
+ ****************************************************************************/
+/*
+ * 512KB NOR flash Device bus boot chip select
+ */
+#define NET2BIG_NOR_BOOT_BASE           0xfff80000
+#define NET2BIG_NOR_BOOT_SIZE           SZ_512K
+/*****************************************************************************
+ * 512KB NOR Flash on Boot Device
+ ****************************************************************************/
+/*
+ * TODO: Check write support on flash MX29LV400CBTC-70G
+ */
+static struct mtd_partition net2big_partitions[] = {
+        {
+                .name           = "Full512kb",
+                .size           = MTDPART_SIZ_FULL,
+                .offset         = 0x00000000,
+                .mask_flags     = MTD_WRITEABLE,
+        },
+};
+static struct physmap_flash_data net2big_nor_flash_data = {
+        .width          = 1,
+        .parts          = net2big_partitions,
+        .nr_parts       = ARRAY_SIZE(net2big_partitions),
+};
+static struct resource net2big_nor_flash_resource = {
+        .flags                  = IORESOURCE_MEM,
+        .start                  = NET2BIG_NOR_BOOT_BASE,
+        .end                    = NET2BIG_NOR_BOOT_BASE
+                                        + NET2BIG_NOR_BOOT_SIZE - 1,
+};
+static struct platform_device net2big_nor_flash = {
+        .name                   = "physmap-flash",
+        .id                     = 0,
+        .dev            = {
+                .platform_data  = &net2big_nor_flash_data,
+        },
+        .num_resources          = 1,
+        .resource               = &net2big_nor_flash_resource,
+};
+/*****************************************************************************
+ * Ethernet
+ ****************************************************************************/
+static struct mv643xx_eth_platform_data net2big_eth_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(8),
+};
+/*****************************************************************************
+ * I2C devices
+ ****************************************************************************/
+/*
+ * i2c addr | chip         | description
+ * 0x32     | Ricoh 5C372b | RTC
+ * 0x50     | HT24LC08     | eeprom (1kB)
+ */
+static struct i2c_board_info __initdata net2big_i2c_devices[] = {
+        {
+                I2C_BOARD_INFO("rs5c372b", 0x32),
+        }, {
+                I2C_BOARD_INFO("24c08", 0x50),
+        },
+};
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct mv_sata_platform_data net2big_sata_data = {
+        .n_ports        = 2,
+};
+#define NET2BIG_GPIO_SATA_POWER_REQ     19
+#define NET2BIG_GPIO_SATA0_POWER        23
+#define NET2BIG_GPIO_SATA1_POWER        25
+static void __init net2big_sata_power_init(void)
+{
+        int err;
+        /* Configure GPIOs over MPP max number. */
+        orion_gpio_set_valid(NET2BIG_GPIO_SATA0_POWER, 1);
+        orion_gpio_set_valid(NET2BIG_GPIO_SATA1_POWER, 1);
+        err = gpio_request(NET2BIG_GPIO_SATA0_POWER, "SATA0 power status");
+        if (err == 0) {
+                err = gpio_direction_input(NET2BIG_GPIO_SATA0_POWER);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA0_POWER);
+        }
+        if (err) {
+                pr_err("net2big: failed to setup SATA0 power GPIO\n");
+                return;
+        }
+        err = gpio_request(NET2BIG_GPIO_SATA1_POWER, "SATA1 power status");
+        if (err == 0) {
+                err = gpio_direction_input(NET2BIG_GPIO_SATA1_POWER);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA1_POWER);
+        }
+        if (err) {
+                pr_err("net2big: failed to setup SATA1 power GPIO\n");
+                goto err_free_1;
+        }
+        err = gpio_request(NET2BIG_GPIO_SATA_POWER_REQ, "SATA power request");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_SATA_POWER_REQ, 0);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA_POWER_REQ);
+        }
+        if (err) {
+                pr_err("net2big: failed to setup SATA power request GPIO\n");
+                goto err_free_2;
+        }
+        if (gpio_get_value(NET2BIG_GPIO_SATA0_POWER) &&
+                gpio_get_value(NET2BIG_GPIO_SATA1_POWER)) {
+                return;
+        }
+        /*
+         * SATA power up on both disk is done by pulling high the CPLD power
+         * request line. The 300ms delay is related to the CPLD clock and is
+         * needed to be sure that the CPLD has take into account the low line
+         * status.
+         */
+        msleep(300);
+        gpio_set_value(NET2BIG_GPIO_SATA_POWER_REQ, 1);
+        pr_info("net2big: power up SATA hard disks\n");
+        return;
+err_free_2:
+        gpio_free(NET2BIG_GPIO_SATA1_POWER);
+err_free_1:
+        gpio_free(NET2BIG_GPIO_SATA0_POWER);
+        return;
+}
+/*****************************************************************************
+ * GPIO LEDs
+ ****************************************************************************/
+/*
+ * The power front LEDs (blue and red) and SATA red LEDs are controlled via a
+ * single GPIO line and are compatible with the leds-gpio driver.
+ *
+ * The SATA blue LEDs have some hardware blink capabilities which are detailled
+ * in the following array:
+ *
+ * SATAx blue LED | SATAx activity | LED state
+ *                |                |
+ *       0        |       0        |  blink (rate 300ms)
+ *       1        |       0        |  off
+ *       ?        |       1        |  on
+ *
+ * Notes: The blue and the red front LED's can't be on at the same time.
+ *        Blue LED have priority.
+ */
+#define NET2BIG_GPIO_PWR_RED_LED        6
+#define NET2BIG_GPIO_PWR_BLUE_LED       16
+#define NET2BIG_GPIO_PWR_LED_BLINK_STOP 7
+#define NET2BIG_GPIO_SATA0_RED_LED      11
+#define NET2BIG_GPIO_SATA1_RED_LED      10
+#define NET2BIG_GPIO_SATA0_BLUE_LED     17
+#define NET2BIG_GPIO_SATA1_BLUE_LED     13
+static struct gpio_led net2big_leds[] = {
+        {
+                .name = "net2big:red:power",
+                .gpio = NET2BIG_GPIO_PWR_RED_LED,
+        },
+        {
+                .name = "net2big:blue:power",
+                .gpio = NET2BIG_GPIO_PWR_BLUE_LED,
+        },
+        {
+                .name = "net2big:red:sata0",
+                .gpio = NET2BIG_GPIO_SATA0_RED_LED,
+        },
+        {
+                .name = "net2big:red:sata1",
+                .gpio = NET2BIG_GPIO_SATA1_RED_LED,
+        },
+};
+static struct gpio_led_platform_data net2big_led_data = {
+        .num_leds = ARRAY_SIZE(net2big_leds),
+        .leds = net2big_leds,
+};
+static struct platform_device net2big_gpio_leds = {
+        .name           = "leds-gpio",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_led_data,
+        },
+};
+static void __init net2big_gpio_leds_init(void)
+{
+        int err;
+        /* Stop initial CPLD slow red/blue blinking on power LED. */
+        err = gpio_request(NET2BIG_GPIO_PWR_LED_BLINK_STOP,
+                           "Power LED blink stop");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_PWR_LED_BLINK_STOP, 1);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_PWR_LED_BLINK_STOP);
+        }
+        if (err)
+                pr_err("net2big: failed to setup power LED blink GPIO\n");
+        /*
+         * Configure SATA0 and SATA1 blue LEDs to blink in relation with the
+         * hard disk activity.
+         */
+        err = gpio_request(NET2BIG_GPIO_SATA0_BLUE_LED,
+                           "SATA0 blue LED control");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_SATA0_BLUE_LED, 1);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA0_BLUE_LED);
+        }
+        if (err)
+                pr_err("net2big: failed to setup SATA0 blue LED GPIO\n");
+        err = gpio_request(NET2BIG_GPIO_SATA1_BLUE_LED,
+                           "SATA1 blue LED control");
+        if (err == 0) {
+                err = gpio_direction_output(NET2BIG_GPIO_SATA1_BLUE_LED, 1);
+                if (err)
+                        gpio_free(NET2BIG_GPIO_SATA1_BLUE_LED);
+        }
+        if (err)
+                pr_err("net2big: failed to setup SATA1 blue LED GPIO\n");
+        platform_device_register(&net2big_gpio_leds);
+}
+/****************************************************************************
+ * GPIO keys
+ ****************************************************************************/
+#define NET2BIG_GPIO_PUSH_BUTTON        18
+#define NET2BIG_GPIO_POWER_SWITCH_ON    8
+#define NET2BIG_GPIO_POWER_SWITCH_OFF   9
+#define NET2BIG_SWITCH_POWER_ON         0x1
+#define NET2BIG_SWITCH_POWER_OFF        0x2
+static struct gpio_keys_button net2big_buttons[] = {
+        {
+                .type           = EV_SW,
+                .code           = NET2BIG_SWITCH_POWER_OFF,
+                .gpio           = NET2BIG_GPIO_POWER_SWITCH_OFF,
+                .desc           = "Power rocker switch (auto|off)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_SW,
+                .code           = NET2BIG_SWITCH_POWER_ON,
+                .gpio           = NET2BIG_GPIO_POWER_SWITCH_ON,
+                .desc           = "Power rocker switch (on|auto)",
+                .active_low     = 0,
+        },
+        {
+                .type           = EV_KEY,
+                .code           = KEY_POWER,
+                .gpio           = NET2BIG_GPIO_PUSH_BUTTON,
+                .desc           = "Front Push Button",
+                .active_low     = 0,
+        },
+};
+static struct gpio_keys_platform_data net2big_button_data = {
+        .buttons        = net2big_buttons,
+        .nbuttons       = ARRAY_SIZE(net2big_buttons),
+};
+static struct platform_device net2big_gpio_buttons = {
+        .name           = "gpio-keys",
+        .id             = -1,
+        .dev            = {
+                .platform_data  = &net2big_button_data,
+        },
+};
+/*****************************************************************************
+ * General Setup
+ ****************************************************************************/
+static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = {
+        {  0, MPP_GPIO },       /* Raid mode (bit 0) */
+        {  1, MPP_GPIO },       /* USB port 2 fuse (0 = Fail, 1 = Ok) */
+        {  2, MPP_GPIO },       /* Raid mode (bit 1) */
+        {  3, MPP_GPIO },       /* Board ID (bit 0) */
+        {  4, MPP_GPIO },       /* Fan activity (0 = Off, 1 = On) */
+        {  5, MPP_GPIO },       /* Fan fail detection */
+        {  6, MPP_GPIO },       /* Red front LED (0 = Off, 1 = On) */
+        {  7, MPP_GPIO },       /* Disable initial blinking on front LED */
+        {  8, MPP_GPIO },       /* Rear power switch (on|auto) */
+        {  9, MPP_GPIO },       /* Rear power switch (auto|off) */
+        { 10, MPP_GPIO },       /* SATA 1 red LED (0 = Off, 1 = On) */
+        { 11, MPP_GPIO },       /* SATA 0 red LED (0 = Off, 1 = On) */
+        { 12, MPP_GPIO },       /* Board ID (bit 1) */
+        { 13, MPP_GPIO },       /* SATA 1 blue LED blink control */
+        { 14, MPP_SATA_LED },
+        { 15, MPP_SATA_LED },
+        { 16, MPP_GPIO },       /* Blue front LED control */
+        { 17, MPP_GPIO },       /* SATA 0 blue LED blink control */
+        { 18, MPP_GPIO },       /* Front button (0 = Released, 1 = Pushed ) */
+        { 19, MPP_GPIO },       /* SATA{0,1} power On/Off request */
+        { -1 }
+        /* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
+        /* 23: SATA 0 power status */
+        /* 24: Board power off */
+        /* 25: SATA 1 power status */
+};
+#define NET2BIG_GPIO_POWER_OFF          24
+static void net2big_power_off(void)
+{
+        gpio_set_value(NET2BIG_GPIO_POWER_OFF, 1);
+}
+static void __init net2big_init(void)
+{
+        /*
+         * Setup basic Orion functions. Need to be called early.
+         */
+        orion5x_init();
+        orion5x_mpp_conf(net2big_mpp_modes);
+        /*
+         * Configure peripherals.
+         */
+        orion5x_ehci0_init();
+        orion5x_ehci1_init();
+        orion5x_eth_init(&net2big_eth_data);
+        orion5x_i2c_init();
+        orion5x_uart0_init();
+        orion5x_xor_init();
+        net2big_sata_power_init();
+        orion5x_sata_init(&net2big_sata_data);
+        orion5x_setup_dev_boot_win(NET2BIG_NOR_BOOT_BASE,
+                                   NET2BIG_NOR_BOOT_SIZE);
+        platform_device_register(&net2big_nor_flash);
+        platform_device_register(&net2big_gpio_buttons);
+        net2big_gpio_leds_init();
+        i2c_register_board_info(0, net2big_i2c_devices,
+                                ARRAY_SIZE(net2big_i2c_devices));
+        orion_gpio_set_valid(NET2BIG_GPIO_POWER_OFF, 1);
+        if (gpio_request(NET2BIG_GPIO_POWER_OFF, "power-off") == 0 &&
+            gpio_direction_output(NET2BIG_GPIO_POWER_OFF, 0) == 0)
+                pm_power_off = net2big_power_off;
+        else
+                pr_err("net2big: failed to configure power-off GPIO\n");
+        pr_notice("net2big: Flash writing is not yet supported.\n");
+}
+/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
+MACHINE_START(NET2BIG, "LaCie 2Big Network")
+        .phys_io        = ORION5X_REGS_PHYS_BASE,
+        .io_pg_offst    = ((ORION5X_REGS_VIRT_BASE) >> 18) & 0xFFFC,
+        .boot_params    = 0x00000100,
+        .init_machine   = net2big_init,
+        .map_io         = orion5x_map_io,
+        .init_irq       = orion5x_init_irq,
+        .timer          = &orion5x_timer,
+        .fixup          = tag_fixup_mem32,
+MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/audio.h b/arch/arm/mach-pxa/include/mach/audio.h
index 16eb02552d5d..a3449e35a6f5 100644
--- a/arch/arm/mach-pxa/include/mach/audio.h
+++ b/arch/arm/mach-pxa/include/mach/audio.h
@@ -3,10 +3,12 @@
 #include <sound/core.h>
 #include <sound/pcm.h>
+#include <sound/ac97_codec.h>
 /*
 * @reset_gpio: AC97 reset gpio (normally gpio113 or gpio95)
 *              a -1 value means no gpio will be used for reset
+ * @codec_pdata: AC97 codec platform_data
 * reset_gpio should only be specified for pxa27x CPUs where a silicon
 * bug prevents correct operation of the reset line. If not specified,
@@ -20,6 +22,7 @@ typedef struct {
        void (*resume)(void *);
        void *priv;
        int reset_gpio;
+        void *codec_pdata[AC97_BUS_MAX_DEVICES];
 } pxa2xx_audio_ops_t;
 extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h b/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
index d5a48a96dea7..7b4eadc6df3a 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x_keypad.h
@@ -2,9 +2,12 @@
 #define __ASM_ARCH_PXA27x_KEYPAD_H
 #include <linux/input.h>
+#include <linux/input/matrix_keypad.h>
 #define MAX_MATRIX_KEY_ROWS     (8)
 #define MAX_MATRIX_KEY_COLS     (8)
+#define MATRIX_ROW_SHIFT        (3)
+#define MAX_DIRECT_KEY_NUM      (8)
 /* pxa3xx keypad platform specific parameters
 *
@@ -33,7 +36,7 @@ struct pxa27x_keypad_platform_data {
        /* direct keys */
        int             direct_key_num;
-        unsigned int    direct_key_map[8];
+        unsigned int    direct_key_map[MAX_DIRECT_KEY_NUM];
        /* rotary encoders 0 */
        int             enable_rotary0;
@@ -51,8 +54,6 @@ struct pxa27x_keypad_platform_data {
        unsigned int    debounce_interval;
 };
-#define KEY(row, col, val)      (((row) << 28) | ((col) << 24) | (val))
 extern void pxa_set_keypad_info(struct pxa27x_keypad_platform_data *info);
 #endif /* __ASM_ARCH_PXA27x_KEYPAD_H */
diff --git a/arch/arm/mach-pxa/sharpsl_pm.c b/arch/arm/mach-pxa/sharpsl_pm.c
index 2546c066cd6e..629e05d1196e 100644
--- a/arch/arm/mach-pxa/sharpsl_pm.c
+++ b/arch/arm/mach-pxa/sharpsl_pm.c
@@ -678,8 +678,8 @@ static int corgi_enter_suspend(unsigned long alarm_time, unsigned int alarm_enab
                dev_dbg(sharpsl_pm.dev, "User triggered wakeup in offline charger.\n");
        }
-        if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) || (sharpsl_fatal_check() < 0) )
+        if ((!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_LOCK)) ||
-        {
+            (!sharpsl_pm.machinfo->read_devdata(SHARPSL_STATUS_FATAL))) {
                dev_err(sharpsl_pm.dev, "Fatal condition. Suspend.\n");
                corgi_goto_sleep(alarm_time, alarm_enable, state);
                return 1;
diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig
index d4cfa2145386..dfc9b0bc6eb2 100644
--- a/arch/arm/mach-realview/Kconfig
+++ b/arch/arm/mach-realview/Kconfig
@@ -75,7 +75,7 @@ config MACH_REALVIEW_PBX
 config REALVIEW_HIGH_PHYS_OFFSET
        bool "High physical base address for the RealView platform"
-        depends on !MACH_REALVIEW_PB1176
+        depends on MMU && !MACH_REALVIEW_PB1176
        default y
        help
          RealView boards other than PB1176 have the RAM available at
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index facbd49eec67..dc3519c50ab2 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -221,6 +221,9 @@ arch_initcall(realview_i2c_init);
 #define REALVIEW_SYSMCI (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_MCI_OFFSET)
+/*
+ * This is only used if GPIOLIB support is disabled
+ */
 static unsigned int realview_mmc_status(struct device *dev)
 {
        struct amba_device *adev = container_of(dev, struct amba_device, dev);
@@ -237,11 +240,15 @@ static unsigned int realview_mmc_status(struct device *dev)
 struct mmc_platform_data realview_mmc0_plat_data = {
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
        .status         = realview_mmc_status,
+        .gpio_wp        = 17,
+        .gpio_cd        = 16,
 };
 struct mmc_platform_data realview_mmc1_plat_data = {
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
        .status         = realview_mmc_status,
+        .gpio_wp        = 19,
+        .gpio_cd        = 18,
 };
 /*
diff --git a/arch/arm/mach-realview/include/mach/gpio.h b/arch/arm/mach-realview/include/mach/gpio.h
new file mode 100644
index 000000000000..94ff27678a46
--- /dev/null
+++ b/arch/arm/mach-realview/include/mach/gpio.h
@@ -0,0 +1,6 @@
+#include <asm-generic/gpio.h>
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
diff --git a/arch/arm/mach-realview/include/mach/hardware.h b/arch/arm/mach-realview/include/mach/hardware.h
index b42c14f89acb..8a638d15797f 100644
--- a/arch/arm/mach-realview/include/mach/hardware.h
+++ b/arch/arm/mach-realview/include/mach/hardware.h
@@ -25,6 +25,7 @@
 #include <asm/sizes.h>
 /* macro to get at IO space when running virtually */
+#ifdef CONFIG_MMU
 /*
 * Statically mapped addresses:
 *
@@ -33,6 +34,9 @@
 * 1fxx xxxx -> fexx xxxx
 */
 #define IO_ADDRESS(x)           (((x) & 0x03ffffff) + 0xfb000000)
+#else
+#define IO_ADDRESS(x)           (x)
+#endif
 #define __io_address(n)         __io(IO_ADDRESS(n))
 #endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index ac0e83f1cc3a..a88458b4799d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -20,6 +20,7 @@
 #include <mach/hardware.h>
 #include <asm/mach-types.h>
 #include <asm/localtimer.h>
+#include <asm/unified.h>
 #include <mach/board-eb.h>
 #include <mach/board-pb11mp.h>
@@ -137,26 +138,19 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 static void __init poke_milo(void)
 {
-        extern void secondary_startup(void);
        /* nobody is to be released from the pen yet */
        pen_release = -1;
        /*
-         * write the address of secondary startup into the system-wide
+         * Write the address of secondary startup into the system-wide flags
-         * flags register, then clear the bottom two bits, which is what
+         * register. The BootMonitor waits for this register to become
-         * BootMonitor is waiting for
+         * non-zero.
         */
-#if 1
 #define REALVIEW_SYS_FLAGSS_OFFSET 0x30
-        __raw_writel(virt_to_phys(realview_secondary_startup),
-                     __io_address(REALVIEW_SYS_BASE) +
-                     REALVIEW_SYS_FLAGSS_OFFSET);
 #define REALVIEW_SYS_FLAGSC_OFFSET 0x34
-        __raw_writel(3,
+        __raw_writel(BSYM(virt_to_phys(realview_secondary_startup)),
                     __io_address(REALVIEW_SYS_BASE) +
-                     REALVIEW_SYS_FLAGSC_OFFSET);
+                     REALVIEW_SYS_FLAGSS_OFFSET);
-#endif
        mb();
 }
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 8dfa44e08a94..abd13b448671 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -113,6 +114,21 @@ static void __init realview_eb_map_io(void)
                iotable_init(realview_eb11mp_io_desc, ARRAY_SIZE(realview_eb11mp_io_desc));
 }
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
 /*
 * RealView EB AMBA devices
 */
@@ -189,9 +205,9 @@ AMBA_DEVICE(clcd,  "dev:20",  EB_CLCD,  &clcd_plat_data);
 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 AMBA_DEVICE(wdog,  "dev:e1",  EB_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  EB_GPIO0, NULL);
+AMBA_DEVICE(gpio0, "dev:e4",  EB_GPIO0, &gpio0_plat_data);
-AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
+AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
-AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
+AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
 AMBA_DEVICE(rtc,   "dev:e8",  EB_RTC,   NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  EB_UART0, NULL);
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 25efe71a67c7..17fbb0e889b6 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -107,6 +108,21 @@ static void __init realview_pb1176_map_io(void)
        iotable_init(realview_pb1176_io_desc, ARRAY_SIZE(realview_pb1176_io_desc));
 }
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
 /*
 * RealView PB1176 AMBA devices
 */
@@ -164,9 +180,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PB1176_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PB1176_SMC,     NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PB1176_WATCHDOG,        NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PB1176_GPIO0,   NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB1176_GPIO0,   &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PB1176_RTC,     NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PB1176_UART0,   NULL);
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index dc4b16943907..fdd042b85f40 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -108,6 +109,21 @@ static void __init realview_pb11mp_map_io(void)
        iotable_init(realview_pb11mp_io_desc, ARRAY_SIZE(realview_pb11mp_io_desc));
 }
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
 /*
 * RealView PB11MPCore AMBA devices
 */
@@ -166,9 +182,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PB11MP_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PB11MP_SMC,     NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PB11MP_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PB11MP_GPIO0,   NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PB11MP_GPIO0,   &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PB11MP_RTC,     NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PB11MP_UART0,   NULL);
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index d6ac1eb86576..70bba9900d97 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 #include <asm/irq.h>
@@ -98,6 +99,21 @@ static void __init realview_pba8_map_io(void)
        iotable_init(realview_pba8_io_desc, ARRAY_SIZE(realview_pba8_io_desc));
 }
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
 /*
 * RealView PBA8Core AMBA devices
 */
@@ -156,9 +172,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PBA8_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PBA8_SMC,       NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PBA8_WATCHDOG, NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PBA8_GPIO0,     NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PBA8_GPIO0,     &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PBA8_RTC,       NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PBA8_UART0,     NULL);
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index ede2a57240a3..ce6c5d25fbef 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -22,6 +22,7 @@
 #include <linux/platform_device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 #include <asm/irq.h>
@@ -118,6 +119,21 @@ static void __init realview_pbx_map_io(void)
                iotable_init(realview_local_io_desc, ARRAY_SIZE(realview_local_io_desc));
 }
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = -1,
+};
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = -1,
+};
 /*
 * RealView PBXCore AMBA devices
 */
@@ -176,9 +192,9 @@ AMBA_DEVICE(uart3,	"fpga:09",	PBX_UART3,	NULL);
 AMBA_DEVICE(smc,        "dev:00",       PBX_SMC,        NULL);
 AMBA_DEVICE(sctl,       "dev:e0",       SCTL,           NULL);
 AMBA_DEVICE(wdog,       "dev:e1",       PBX_WATCHDOG,   NULL);
-AMBA_DEVICE(gpio0,      "dev:e4",       PBX_GPIO0,      NULL);
+AMBA_DEVICE(gpio0,      "dev:e4",       PBX_GPIO0,      &gpio0_plat_data);
-AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          NULL);
+AMBA_DEVICE(gpio1,      "dev:e5",       GPIO1,          &gpio1_plat_data);
-AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          NULL);
+AMBA_DEVICE(gpio2,      "dev:e6",       GPIO2,          &gpio2_plat_data);
 AMBA_DEVICE(rtc,        "dev:e8",       PBX_RTC,        NULL);
 AMBA_DEVICE(sci0,       "dev:f0",       SCI,            NULL);
 AMBA_DEVICE(uart0,      "dev:f1",       PBX_UART0,      NULL);
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 41bb65d5b91f..d8c023d4df30 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -12,6 +12,7 @@ config CPU_S3C2410
        select S3C2410_GPIO
        select CPU_LLSERIAL_S3C2410
        select S3C2410_PM if PM
+        select S3C2410_CPUFREQ if CPU_FREQ_S3C24XX
        help
          Support for S3C2410 and S3C2410A family from the S3C24XX line
          of Samsung Mobile CPUs.
@@ -45,6 +46,22 @@ config MACH_BAST_IDE
          Internal node for machines with an BAST style IDE
          interface
+# cpu frequency scaling support
+config S3C2410_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        select S3C2410_CPUFREQ_UTILS
+        help
+          CPU Frequency scaling support for S3C2410
+config S3C2410_PLLTABLE
+        bool
+        depends on S3C2410_CPUFREQ && CPU_FREQ_S3C24XX_PLL
+        default y
+        help
+          Select the PLL table for the S3C2410
 menu "S3C2410 Machines"
 config ARCH_SMDK2410
@@ -79,6 +96,7 @@ config MACH_N30
 config ARCH_BAST
        bool "Simtec Electronics BAST (EB2410ITX)"
        select CPU_S3C2410
+        select S3C2410_IOTIMING if S3C2410_CPUFREQ
        select PM_SIMTEC if PM
        select SIMTEC_NOR
        select MACH_BAST_IDE
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index fca02f82711c..2ab5ba4b266f 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_CPU_S3C2410_DMA)	+= dma.o
 obj-$(CONFIG_CPU_S3C2410_DMA)   += dma.o
 obj-$(CONFIG_S3C2410_PM)        += pm.o sleep.o
 obj-$(CONFIG_S3C2410_GPIO)      += gpio.o
+obj-$(CONFIG_S3C2410_CPUFREQ)   += cpu-freq.o
+obj-$(CONFIG_S3C2410_PLLTABLE)  += pll.o
 # Machine support
diff --git a/arch/arm/mach-s3c2410/cpu-freq.c b/arch/arm/mach-s3c2410/cpu-freq.c
new file mode 100644
index 000000000000..9d1186877d08
--- /dev/null
+++ b/arch/arm/mach-s3c2410/cpu-freq.c
@@ -0,0 +1,159 @@
+/* linux/arch/arm/mach-s3c2410/cpu-freq.c
+ *
+ * Copyright (c) 2006,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+/* Note, 2410A has an extra mode for 1:4:4 ratio, bit 2 of CLKDIV */
+static void s3c2410_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        u32 clkdiv = 0;
+        if (cfg->divs.h_divisor == 2)
+                clkdiv |= S3C2410_CLKDIVN_HDIVN;
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2410_CLKDIVN_PDIVN;
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+}
+static int s3c2410_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long hclk, fclk, pclk;
+        unsigned int hdiv, pdiv;
+        unsigned long hclk_max;
+        fclk = cfg->freq.fclk;
+        hclk_max = cfg->max.hclk;
+        cfg->freq.armclk = fclk;
+        s3c_freq_dbg("%s: fclk is %lu, max hclk %lu\n",
+                      __func__, fclk, hclk_max);
+        hdiv = (fclk > cfg->max.hclk) ? 2 : 1;
+        hclk = fclk / hdiv;
+        if (hclk > cfg->max.hclk) {
+                s3c_freq_dbg("%s: hclk too big\n", __func__);
+                return -EINVAL;
+        }
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+        pclk = hclk / pdiv;
+        if (pclk > cfg->max.pclk) {
+                s3c_freq_dbg("%s: pclk too big\n", __func__);
+                return -EINVAL;
+        }
+        pdiv *= hdiv;
+        /* record the result */
+        cfg->divs.p_divisor = pdiv;
+        cfg->divs.h_divisor = hdiv;
+        return 0      ;
+}
+static struct s3c_cpufreq_info s3c2410_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+        /* transition latency is about 5ms worst-case, so
+         * set 10ms to be sure */
+        .latency        = 10000000,
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 12,
+        .need_pll       = 1,
+        .name           = "s3c2410",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .resume_clocks  = s3c2410_setup_clocks,
+        .set_fvco       = s3c2410_set_fvco,
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2410_cpufreq_setdivs,
+        .calc_divs      = s3c2410_cpufreq_calcdivs,
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+static int s3c2410_cpufreq_add(struct sys_device *sysdev)
+{
+        return s3c_cpufreq_register(&s3c2410_cpufreq_info);
+}
+static struct sysdev_driver s3c2410_cpufreq_driver = {
+        .add            = s3c2410_cpufreq_add,
+};
+static int __init s3c2410_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2410_sysclass,
+                                      &s3c2410_cpufreq_driver);
+}
+arch_initcall(s3c2410_cpufreq_init);
+static int s3c2410a_cpufreq_add(struct sys_device *sysdev)
+{
+        /* alter the maximum freq settings for S3C2410A. If a board knows
+         * it only has a maximum of 200, then it should register its own
+         * limits. */
+        s3c2410_cpufreq_info.max.fclk = 266000000;
+        s3c2410_cpufreq_info.max.hclk = 133000000;
+        s3c2410_cpufreq_info.max.pclk =  66500000;
+        s3c2410_cpufreq_info.name = "s3c2410a";
+        return s3c2410_cpufreq_add(sysdev);
+}
+static struct sysdev_driver s3c2410a_cpufreq_driver = {
+        .add            = s3c2410a_cpufreq_add,
+};
+static int __init s3c2410a_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass,
+                                      &s3c2410a_cpufreq_driver);
+}
+arch_initcall(s3c2410a_cpufreq_init);
diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index dbf96e60d992..63b753f56c64 100644
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -164,6 +164,17 @@ static int __init s3c2410_dma_drvinit(void)
 }
 arch_initcall(s3c2410_dma_drvinit);
+static struct sysdev_driver s3c2410a_dma_driver = {
+        .add    = s3c2410_dma_add,
+};
+static int __init s3c2410a_dma_drvinit(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_dma_driver);
+}
+arch_initcall(s3c2410a_dma_drvinit);
 #endif
 #if defined(CONFIG_CPU_S3C2442)
diff --git a/arch/arm/mach-s3c2410/include/mach/irqs.h b/arch/arm/mach-s3c2410/include/mach/irqs.h
index 2a2384ffa7b1..6c12c6312ad8 100644
--- a/arch/arm/mach-s3c2410/include/mach/irqs.h
+++ b/arch/arm/mach-s3c2410/include/mach/irqs.h
@@ -164,6 +164,12 @@
 #define IRQ_S3CUART_TX3         IRQ_S3C2443_TX3
 #define IRQ_S3CUART_ERR3        IRQ_S3C2443_ERR3
+#ifdef CONFIG_CPU_S3C2440
+#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
+#else
+#define IRQ_S3C244x_AC97 IRQ_S3C2443_AC97
+#endif
 /* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
 #define FIQ_START               IRQ_EINT0
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index e99b212cb1ca..b049e61460b6 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -67,6 +67,13 @@
 #define S3C2443_PA_HSMMC   (0x4A800000)
 #define S3C2443_SZ_HSMMC   (256)
+/* S3C2412 memory and IO controls */
+#define S3C2412_PA_SSMC (0x4F000000)
+#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
+#define S3C2412_PA_EBI  (0x48800000)
+#define S3C2412_VA_EBI  S3C_ADDR_CPU(0x00010000)
 /* physical addresses of all the chip-select areas */
 #define S3C2410_CS0 (0x00000000)
@@ -103,5 +110,6 @@
 #define S3C_PA_UART         S3C24XX_PA_UART
 #define S3C_PA_USBHOST  S3C2410_PA_USBHOST
 #define S3C_PA_HSMMC0       S3C2443_PA_HSMMC
+#define S3C_PA_NAND         S3C24XX_PA_NAND
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index b278d0c45ccf..f6e8eec879c8 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -328,13 +328,15 @@
 #define S3C2410_GPD8_VD16       (0x02 << 16)
 #define S3C2400_GPD8_TOUT3      (0x02 << 16)
+#define S3C2440_GPD8_SPIMISO1   (0x03 << 16)
 #define S3C2410_GPD9_VD17       (0x02 << 18)
 #define S3C2400_GPD9_TCLK0      (0x02 << 18)
-#define S3C2410_GPD9_MASK       (0x03 << 18)
+#define S3C2440_GPD9_SPIMOSI1   (0x03 << 18)
 #define S3C2410_GPD10_VD18      (0x02 << 20)
 #define S3C2400_GPD10_nWAIT     (0x02 << 20)
+#define S3C2440_GPD10_SPICLK1   (0x03 << 20)
 #define S3C2410_GPD11_VD19      (0x02 << 22)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 57759804e2fa..7f7c52947963 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -73,6 +73,16 @@
 #define S3C2410_BWSCON_WS7              (1<<30)
 #define S3C2410_BWSCON_ST7              (1<<31)
+/* accesor functions for getting BANK(n) configuration. (n != 0) */
+#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf)
+#define S3C2410_BWSCON_DW8              (0)
+#define S3C2410_BWSCON_DW16             (1)
+#define S3C2410_BWSCON_DW32             (2)
+#define S3C2410_BWSCON_WS               (1 << 2)
+#define S3C2410_BWSCON_ST               (1 << 3)
 /* memory set (rom, ram) */
 #define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
 #define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
index a4bf27123170..fb6352515090 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2412-mem.h
@@ -14,9 +14,11 @@
 #ifndef __ASM_ARM_REGS_S3C2412_MEM
 #define __ASM_ARM_REGS_S3C2412_MEM
-#ifndef S3C2412_MEMREG
 #define S3C2412_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
-#endif
+#define S3C2412_EBIREG(x) (S3C2412_VA_EBI + (x))
+#define S3C2412_SSMCREG(x) (S3C2412_VA_SSMC + (x))
+#define S3C2412_SSMC(x, o) (S3C2412_SSMCREG((x * 0x20) + (o)))
 #define S3C2412_BANKCFG                 S3C2412_MEMREG(0x00)
 #define S3C2412_BANKCON1                S3C2412_MEMREG(0x04)
@@ -26,4 +28,21 @@
 #define S3C2412_REFRESH                 S3C2412_MEMREG(0x10)
 #define S3C2412_TIMEOUT                 S3C2412_MEMREG(0x14)
+/* EBI control registers */
+#define S3C2412_EBI_PR                  S3C2412_EBIREG(0x00)
+#define S3C2412_EBI_BANKCFG             S3C2412_EBIREG(0x04)
+/* SSMC control registers */
+#define S3C2412_SSMC_BANK(x)            S3C2412_SSMC(x, 0x00)
+#define S3C2412_SMIDCYR(x)              S3C2412_SSMC(x, 0x00)
+#define S3C2412_SMBWSTRD(x)             S3C2412_SSMC(x, 0x04)
+#define S3C2412_SMBWSTWRR(x)            S3C2412_SSMC(x, 0x08)
+#define S3C2412_SMBWSTOENR(x)           S3C2412_SSMC(x, 0x0C)
+#define S3C2412_SMBWSTWENR(x)           S3C2412_SSMC(x, 0x10)
+#define S3C2412_SMBCR(x)                S3C2412_SSMC(x, 0x14)
+#define S3C2412_SMBSR(x)                S3C2412_SSMC(x, 0x18)
+#define S3C2412_SMBWSTBRDR(x)           S3C2412_SSMC(x, 0x1C)
 #endif /*  __ASM_ARM_REGS_S3C2412_MEM */
diff --git a/arch/arm/mach-s3c2410/include/mach/spi.h b/arch/arm/mach-s3c2410/include/mach/spi.h
index 1d300fb112b1..193b39d654ed 100644
--- a/arch/arm/mach-s3c2410/include/mach/spi.h
+++ b/arch/arm/mach-s3c2410/include/mach/spi.h
@@ -30,4 +30,7 @@ extern void s3c24xx_spi_gpiocfg_bus0_gpe11_12_13(struct s3c2410_spi_info *spi,
 extern void s3c24xx_spi_gpiocfg_bus1_gpg5_6_7(struct s3c2410_spi_info *spi,
                                              int enable);
+extern void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
+                                               int enable);
 #endif /* __ASM_ARCH_SPI_H */
diff --git a/arch/arm/mach-s3c2410/irq.c b/arch/arm/mach-s3c2410/irq.c
index 92150399563b..5e2f35332056 100644
--- a/arch/arm/mach-s3c2410/irq.c
+++ b/arch/arm/mach-s3c2410/irq.c
@@ -39,9 +39,22 @@ static struct sysdev_driver s3c2410_irq_driver = {
        .resume         = s3c24xx_irq_resume,
 };
-static int s3c2410_irq_init(void)
+static int __init s3c2410_irq_init(void)
 {
        return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_irq_driver);
 }
 arch_initcall(s3c2410_irq_init);
+static struct sysdev_driver s3c2410a_irq_driver = {
+        .add            = s3c2410_irq_add,
+        .suspend        = s3c24xx_irq_suspend,
+        .resume         = s3c24xx_irq_resume,
+};
+static int __init s3c2410a_irq_init(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_irq_driver);
+}
+arch_initcall(s3c2410a_irq_init);
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index ce3baba2cd7f..647c9adb018f 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -45,6 +45,7 @@
 #include <mach/regs-mem.h>
 #include <mach/regs-lcd.h>
+#include <plat/hwmon.h>
 #include <plat/nand.h>
 #include <plat/iic.h>
 #include <mach/fb.h>
@@ -59,6 +60,7 @@
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
+#include <plat/cpu-freq.h>
 #include "usb-simtec.h"
 #include "nor-simtec.h"
@@ -547,7 +549,35 @@ static struct i2c_board_info bast_i2c_devs[] __initdata = {
        },
 };
+static struct s3c_hwmon_pdata bast_hwmon_info = {
+        /* LCD contrast (0-6.6V) */
+        .in[0] = &(struct s3c_hwmon_chcfg) {
+                .name           = "lcd-contrast",
+                .mult           = 3300,
+                .div            = 512,
+        },
+        /* LED current feedback */
+        .in[1] = &(struct s3c_hwmon_chcfg) {
+                .name           = "led-feedback",
+                .mult           = 3300,
+                .div            = 1024,
+        },
+        /* LCD feedback (0-6.6V) */
+        .in[2] = &(struct s3c_hwmon_chcfg) {
+                .name           = "lcd-feedback",
+                .mult           = 3300,
+                .div            = 512,
+        },
+        /* Vcore (1.8-2.0V), Vref 3.3V  */
+        .in[3] = &(struct s3c_hwmon_chcfg) {
+                .name           = "vcore",
+                .mult           = 3300,
+                .div            = 1024,
+        },
+};
 /* Standard BAST devices */
+// cat /sys/devices/platform/s3c24xx-adc/s3c-hwmon/in_0
 static struct platform_device *bast_devices[] __initdata = {
        &s3c_device_usb,
@@ -556,6 +586,8 @@ static struct platform_device *bast_devices[] __initdata = {
        &s3c_device_i2c0,
        &s3c_device_rtc,
        &s3c_device_nand,
+        &s3c_device_adc,
+        &s3c_device_hwmon,
        &bast_device_dm9k,
        &bast_device_asix,
        &bast_device_axpp,
@@ -570,6 +602,12 @@ static struct clk *bast_clocks[] __initdata = {
        &s3c24xx_uclk,
 };
+static struct s3c_cpufreq_board __initdata bast_cpufreq = {
+        .refresh        = 7800, /* 7.8usec */
+        .auto_io        = 1,
+        .need_io        = 1,
+};
 static void __init bast_map_io(void)
 {
        /* initialise the clocks */
@@ -588,6 +626,7 @@ static void __init bast_map_io(void)
        s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
        s3c_device_nand.dev.platform_data = &bast_nand_info;
+        s3c_device_hwmon.dev.platform_data = &bast_hwmon_info;
        s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
        s3c24xx_init_clocks(0);
@@ -608,6 +647,8 @@ static void __init bast_init(void)
        usb_simtec_init();
        nor_simtec_init();
+        s3c_cpufreq_setboard(&bast_cpufreq);
 }
 MACHINE_START(BAST, "Simtec-BAST")
diff --git a/arch/arm/mach-s3c2410/pll.c b/arch/arm/mach-s3c2410/pll.c
new file mode 100644
index 000000000000..f178c2fd9d85
--- /dev/null
+++ b/arch/arm/mach-s3c2410/pll.c
@@ -0,0 +1,95 @@
+/* arch/arm/mach-s3c2410/pll.c
+ *
+ * Copyright (c) 2006,2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2410 CPU PLL tables
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sysdev.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+static struct cpufreq_frequency_table pll_vals_12MHz[] = {
+    { .frequency = 34000000,  .index = PLLVAL(82, 2, 3),   },
+    { .frequency = 45000000,  .index = PLLVAL(82, 1, 3),   },
+    { .frequency = 51000000,  .index = PLLVAL(161, 3, 3),  },
+    { .frequency = 48000000,  .index = PLLVAL(120, 2, 3),  },
+    { .frequency = 56000000,  .index = PLLVAL(142, 2, 3),  },
+    { .frequency = 68000000,  .index = PLLVAL(82, 2, 2),   },
+    { .frequency = 79000000,  .index = PLLVAL(71, 1, 2),   },
+    { .frequency = 85000000,  .index = PLLVAL(105, 2, 2),  },
+    { .frequency = 90000000,  .index = PLLVAL(112, 2, 2),  },
+    { .frequency = 101000000, .index = PLLVAL(127, 2, 2),  },
+    { .frequency = 113000000, .index = PLLVAL(105, 1, 2),  },
+    { .frequency = 118000000, .index = PLLVAL(150, 2, 2),  },
+    { .frequency = 124000000, .index = PLLVAL(116, 1, 2),  },
+    { .frequency = 135000000, .index = PLLVAL(82, 2, 1),   },
+    { .frequency = 147000000, .index = PLLVAL(90, 2, 1),   },
+    { .frequency = 152000000, .index = PLLVAL(68, 1, 1),   },
+    { .frequency = 158000000, .index = PLLVAL(71, 1, 1),   },
+    { .frequency = 170000000, .index = PLLVAL(77, 1, 1),   },
+    { .frequency = 180000000, .index = PLLVAL(82, 1, 1),   },
+    { .frequency = 186000000, .index = PLLVAL(85, 1, 1),   },
+    { .frequency = 192000000, .index = PLLVAL(88, 1, 1),   },
+    { .frequency = 203000000, .index = PLLVAL(161, 3, 1),  },
+    /* 2410A extras */
+    { .frequency = 210000000, .index = PLLVAL(132, 2, 1),  },
+    { .frequency = 226000000, .index = PLLVAL(105, 1, 1),  },
+    { .frequency = 266000000, .index = PLLVAL(125, 1, 1),  },
+    { .frequency = 268000000, .index = PLLVAL(126, 1, 1),  },
+    { .frequency = 270000000, .index = PLLVAL(127, 1, 1),  },
+};
+static int s3c2410_plls_add(struct sys_device *dev)
+{
+        return s3c_plltab_register(pll_vals_12MHz, ARRAY_SIZE(pll_vals_12MHz));
+}
+static struct sysdev_driver s3c2410_plls_drv = {
+        .add    = s3c2410_plls_add,
+};
+static int __init s3c2410_pll_init(void)
+{
+        return sysdev_driver_register(&s3c2410_sysclass, &s3c2410_plls_drv);
+}
+arch_initcall(s3c2410_pll_init);
+static struct sysdev_driver s3c2410a_plls_drv = {
+        .add    = s3c2410_plls_add,
+};
+static int __init s3c2410a_pll_init(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_plls_drv);
+}
+arch_initcall(s3c2410a_pll_init);
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index 143e08a599d4..966119c8efee 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -119,6 +119,18 @@ static int __init s3c2410_pm_drvinit(void)
 }
 arch_initcall(s3c2410_pm_drvinit);
+static struct sysdev_driver s3c2410a_pm_driver = {
+        .add            = s3c2410_pm_add,
+        .resume         = s3c2410_pm_resume,
+};
+static int __init s3c2410a_pm_drvinit(void)
+{
+        return sysdev_driver_register(&s3c2410a_sysclass, &s3c2410a_pm_driver);
+}
+arch_initcall(s3c2410a_pm_drvinit);
 #endif
 #if defined(CONFIG_CPU_S3C2440)
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index feb141b1f915..91ba42f688ac 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -105,17 +105,33 @@ void __init_or_cpufreq s3c2410_setup_clocks(void)
        s3c24xx_setup_clocks(fclk, hclk, pclk);
 }
+/* fake ARMCLK for use with cpufreq, etc. */
+static struct clk s3c2410_armclk = {
+        .name   = "armclk",
+        .parent = &clk_f,
+        .id     = -1,
+};
 void __init s3c2410_init_clocks(int xtal)
 {
        s3c24xx_register_baseclocks(xtal);
        s3c2410_setup_clocks();
        s3c2410_baseclk_add();
+        s3c24xx_register_clock(&s3c2410_armclk);
 }
 struct sysdev_class s3c2410_sysclass = {
        .name = "s3c2410-core",
 };
+/* Note, we would have liked to name this s3c2410-core, but we cannot
+ * register two sysdev_class with the same name.
+ */
+struct sysdev_class s3c2410a_sysclass = {
+        .name = "s3c2410a-core",
+};
 static struct sys_device s3c2410_sysdev = {
        .cls            = &s3c2410_sysclass,
 };
@@ -133,9 +149,22 @@ static int __init s3c2410_core_init(void)
 core_initcall(s3c2410_core_init);
+static int __init s3c2410a_core_init(void)
+{
+        return sysdev_class_register(&s3c2410a_sysclass);
+}
+core_initcall(s3c2410a_core_init);
 int __init s3c2410_init(void)
 {
        printk("S3C2410: Initialising architecture\n");
        return sysdev_register(&s3c2410_sysdev);
 }
+int __init s3c2410a_init(void)
+{
+        s3c2410_sysdev.cls = &s3c2410a_sysclass;
+        return s3c2410_init();
+}
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index 63586ffd0ae7..35c1bde89cf2 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -32,6 +32,15 @@ config S3C2412_PM
        help
          Internal config node to apply S3C2412 power management
+# Note, the S3C2412 IOtiming support is in plat-s3c24xx
+config S3C2412_CPUFREQ
+        bool
+        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        select S3C2412_IOTIMING
+        default y
+        help
+          CPU Frequency scaling support for S3C2412 and S3C2413 SoC CPUs.
 menu "S3C2412 Machines"
diff --git a/arch/arm/mach-s3c2412/Makefile b/arch/arm/mach-s3c2412/Makefile
index 20918d5dc6a9..530ec46cbaea 100644
--- a/arch/arm/mach-s3c2412/Makefile
+++ b/arch/arm/mach-s3c2412/Makefile
@@ -15,6 +15,7 @@ obj-$(CONFIG_CPU_S3C2412)	+= clock.o
 obj-$(CONFIG_CPU_S3C2412)       += gpio.o
 obj-$(CONFIG_S3C2412_DMA)       += dma.o
 obj-$(CONFIG_S3C2412_PM)        += pm.o sleep.o
+obj-$(CONFIG_S3C2412_CPUFREQ)   += cpu-freq.o
 # Machine support
diff --git a/arch/arm/mach-s3c2412/cpu-freq.c b/arch/arm/mach-s3c2412/cpu-freq.c
new file mode 100644
index 000000000000..eb3ea1721335
--- /dev/null
+++ b/arch/arm/mach-s3c2412/cpu-freq.c
@@ -0,0 +1,257 @@
+/* linux/arch/arm/mach-s3c2412/cpu-freq.c
+ *
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412 CPU Frequency scalling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-s3c2412-mem.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+/* our clock resources. */
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+static int s3c2412_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv, armdiv, dvs;
+        unsigned long hclk, fclk, armclk, armdiv_clk;
+        unsigned long hclk_max;
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+        /* We can't run hclk above armclk as at the best we have to
+         * have armclk and hclk in dvs mode. */
+        if (hclk_max > armclk)
+                hclk_max = armclk;
+        s3c_freq_dbg("%s: fclk=%lu, armclk=%lu, hclk_max=%lu\n",
+                     __func__, fclk, armclk, hclk_max);
+        s3c_freq_dbg("%s: want f=%lu, arm=%lu, h=%lu, p=%lu\n",
+                     __func__, cfg->freq.fclk, cfg->freq.armclk,
+                     cfg->freq.hclk, cfg->freq.pclk);
+        armdiv = fclk / armclk;
+        if (armdiv < 1)
+                armdiv = 1;
+        if (armdiv > 2)
+                armdiv = 2;
+        cfg->divs.arm_divisor = armdiv;
+        armdiv_clk = fclk / armdiv;
+        hdiv = armdiv_clk / hclk_max;
+        if (hdiv < 1)
+                hdiv = 1;
+        cfg->freq.hclk = hclk = armdiv_clk / hdiv;
+        /* set dvs depending on whether we reached armclk or not. */
+        cfg->divs.dvs = dvs = armclk < armdiv_clk;
+        /* update the actual armclk we achieved. */
+        cfg->freq.armclk = dvs ? hclk : armdiv_clk;
+        s3c_freq_dbg("%s: armclk %lu, hclk %lu, armdiv %d, hdiv %d, dvs %d\n",
+                     __func__, armclk, hclk, armdiv, hdiv, cfg->divs.dvs);
+        if (hdiv > 4)
+                goto invalid;
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+        cfg->freq.pclk = hclk / pdiv;
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+        if (pdiv > 2)
+                goto invalid;
+        pdiv *= hdiv;
+        /* store the result, and then return */
+        cfg->divs.h_divisor = hdiv * armdiv;
+        cfg->divs.p_divisor = pdiv * armdiv;
+        return 0;
+ invalid:
+        return -EINVAL;
+}
+static void s3c2412_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv;
+        unsigned long olddiv;
+        olddiv = clkdiv = __raw_readl(S3C2410_CLKDIVN);
+        /* clear off current clock info */
+        clkdiv &= ~S3C2412_CLKDIVN_ARMDIVN;
+        clkdiv &= ~S3C2412_CLKDIVN_HDIVN_MASK;
+        clkdiv &= ~S3C2412_CLKDIVN_PDIVN;
+        if (cfg->divs.arm_divisor == 2)
+                clkdiv |= S3C2412_CLKDIVN_ARMDIVN;
+        clkdiv |= ((cfg->divs.h_divisor / cfg->divs.arm_divisor) - 1);
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2412_CLKDIVN_PDIVN;
+        s3c_freq_dbg("%s: div %08lx => %08lx\n", __func__, olddiv, clkdiv);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+static void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        unsigned long refresh;
+        s3c_freq_dbg("%s: refresh %u ns, hclk %lu\n", __func__,
+                     board->refresh, cfg->freq.hclk);
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * by 10 each to ensure that we do not overflow 32 bit numbers. This
+         * should work for HCLK up to 133MHz and refresh period up to 30usec.
+         */
+        refresh = (board->refresh / 10);
+        refresh *= (cfg->freq.hclk / 100);
+        refresh /= (1 * 1000 * 1000);   /* 10^6 */
+        s3c_freq_dbg("%s: setting refresh 0x%08lx\n", __func__, refresh);
+        __raw_writel(refresh, S3C2412_REFRESH);
+}
+/* set the default cpu frequency information, based on an 200MHz part
+ * as we have no other way of detecting the speed rating in software.
+ */
+static struct s3c_cpufreq_info s3c2412_cpufreq_info = {
+        .max            = {
+                .fclk   = 200000000,
+                .hclk   = 100000000,
+                .pclk   =  50000000,
+        },
+        .latency        = 5000000, /* 5ms */
+        .locktime_m     = 150,
+        .locktime_u     = 150,
+        .locktime_bits  = 16,
+        .name           = "s3c2412",
+        .set_refresh    = s3c2412_cpufreq_setrefresh,
+        .set_divs       = s3c2412_cpufreq_setdivs,
+        .calc_divs      = s3c2412_cpufreq_calcdivs,
+        .calc_iotiming  = s3c2412_iotiming_calc,
+        .set_iotiming   = s3c2412_iotiming_set,
+        .get_iotiming   = s3c2412_iotiming_get,
+        .resume_clocks  = s3c2412_setup_clocks,
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2412_iotiming_debugfs),
+};
+static int s3c2412_cpufreq_add(struct sys_device *sysdev)
+{
+        unsigned long fclk_rate;
+        hclk = clk_get(NULL, "hclk");
+        if (IS_ERR(hclk)) {
+                printk(KERN_ERR "%s: cannot find hclk clock\n", __func__);
+                return -ENOENT;
+        }
+        fclk = clk_get(NULL, "fclk");
+        if (IS_ERR(fclk)) {
+                printk(KERN_ERR "%s: cannot find fclk clock\n", __func__);
+                goto err_fclk;
+        }
+        fclk_rate = clk_get_rate(fclk);
+        if (fclk_rate > 200000000) {
+                printk(KERN_INFO
+                       "%s: fclk %ld MHz, assuming 266MHz capable part\n",
+                       __func__, fclk_rate / 1000000);
+                s3c2412_cpufreq_info.max.fclk = 266000000;
+                s3c2412_cpufreq_info.max.hclk = 133000000;
+                s3c2412_cpufreq_info.max.pclk =  66000000;
+        }
+        armclk = clk_get(NULL, "armclk");
+        if (IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: cannot find arm clock\n", __func__);
+                goto err_armclk;
+        }
+        xtal = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal)) {
+                printk(KERN_ERR "%s: cannot find xtal clock\n", __func__);
+                goto err_xtal;
+        }
+        return s3c_cpufreq_register(&s3c2412_cpufreq_info);
+err_xtal:
+        clk_put(armclk);
+err_armclk:
+        clk_put(fclk);
+err_fclk:
+        clk_put(hclk);
+        return -ENOENT;
+}
+static struct sysdev_driver s3c2412_cpufreq_driver = {
+        .add            = s3c2412_cpufreq_add,
+};
+static int s3c2412_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2412_sysclass,
+                                      &s3c2412_cpufreq_driver);
+}
+arch_initcall(s3c2412_cpufreq_init);
diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 5b5aba69ec3f..bef39f77729d 100644
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -69,6 +69,18 @@ static struct map_desc s3c2412_iodesc[] __initdata = {
        IODESC_ENT(CLKPWR),
        IODESC_ENT(TIMER),
        IODESC_ENT(WATCHDOG),
+        {
+                .virtual = (unsigned long)S3C2412_VA_SSMC,
+                .pfn     = __phys_to_pfn(S3C2412_PA_SSMC),
+                .length  = SZ_1M,
+                .type    = MT_DEVICE,
+        },
+        {
+                .virtual = (unsigned long)S3C2412_VA_EBI,
+                .pfn     = __phys_to_pfn(S3C2412_PA_EBI),
+                .length  = SZ_1M,
+                .type    = MT_DEVICE,
+        },
 };
 /* uart registration process */
diff --git a/arch/arm/mach-s3c2440/Kconfig b/arch/arm/mach-s3c2440/Kconfig
index 8cfeaec37306..8ae1b288f7fa 100644
--- a/arch/arm/mach-s3c2440/Kconfig
+++ b/arch/arm/mach-s3c2440/Kconfig
@@ -33,6 +33,7 @@ config MACH_ANUBIS
        select PM_SIMTEC if PM
        select HAVE_PATA_PLATFORM
        select S3C24XX_GPIO_EXTRA64
+        select S3C2440_XTAL_12000000
        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Simtec Electronics ANUBIS
@@ -44,6 +45,8 @@ config MACH_OSIRIS
        select S3C24XX_DCLK
        select PM_SIMTEC if PM
        select S3C24XX_GPIO_EXTRA128
+        select S3C2440_XTAL_12000000
+        select S3C2410_IOTIMING if S3C2440_CPUFREQ
        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Simtec IM2440D20 module, also
@@ -52,6 +55,7 @@ config MACH_OSIRIS
 config MACH_RX3715
        bool "HP iPAQ rx3715"
        select CPU_S3C2440
+        select S3C2440_XTAL_16934400
        select PM_H1940 if PM
        help
          Say Y here if you are using the HP iPAQ rx3715.
@@ -59,6 +63,7 @@ config MACH_RX3715
 config ARCH_S3C2440
        bool "SMDK2440"
        select CPU_S3C2440
+        select S3C2440_XTAL_16934400
        select MACH_SMDK
        select S3C_DEV_USB_HOST
        help
@@ -67,6 +72,7 @@ config ARCH_S3C2440
 config MACH_NEXCODER_2440
        bool "NexVision NEXCODER 2440 Light Board"
        select CPU_S3C2440
+        select S3C2440_XTAL_12000000
        select S3C_DEV_USB_HOST
        help
          Say Y here if you are using the Nex Vision NEXCODER 2440 Light Board
@@ -75,6 +81,7 @@ config SMDK2440_CPU2440
        bool "SMDK2440 with S3C2440 CPU module"
        depends on ARCH_S3C2440
        default y if ARCH_S3C2440
+        select S3C2440_XTAL_16934400
        select CPU_S3C2440
 config MACH_AT2440EVB
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index cba064b49a64..2105a41281a4 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -34,6 +34,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
+#include <plat/cpu-freq.h>
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 #include <mach/regs-mem.h>
@@ -351,6 +352,12 @@ static struct clk *osiris_clocks[] __initdata = {
        &s3c24xx_uclk,
 };
+static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
+        .refresh        = 7800, /* refresh period is 7.8usec */
+        .auto_io        = 1,
+        .need_io        = 1,
+};
 static void __init osiris_map_io(void)
 {
        unsigned long flags;
@@ -402,6 +409,8 @@ static void __init osiris_init(void)
        s3c_i2c0_set_platdata(NULL);
+        s3c_cpufreq_setboard(&osiris_cpufreq);
        i2c_register_board_info(0, osiris_i2c_devs,
                                ARRAY_SIZE(osiris_i2c_devs));
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
index a01132717e34..79e4d93ea2b6 100644
--- a/arch/arm/mach-s3c24a0/include/mach/map.h
+++ b/arch/arm/mach-s3c24a0/include/mach/map.h
@@ -81,5 +81,6 @@
 #define S3C_PA_UART             S3C24A0_PA_UART
 #define S3C_PA_IIC              S3C24A0_PA_IIC
+#define S3C_PA_NAND             S3C24XX_PA_NAND
 #endif /* __ASM_ARCH_24A0_MAP_H */
diff --git a/arch/arm/mach-s3c6400/include/mach/map.h b/arch/arm/mach-s3c6400/include/mach/map.h
index 5057d9948d35..fc8b223bad4f 100644
--- a/arch/arm/mach-s3c6400/include/mach/map.h
+++ b/arch/arm/mach-s3c6400/include/mach/map.h
@@ -38,18 +38,21 @@
 #define S3C_VA_UART2            S3C_VA_UARTx(2)
 #define S3C_VA_UART3            S3C_VA_UARTx(3)
+#define S3C64XX_PA_NAND         (0x70200000)
 #define S3C64XX_PA_FB           (0x77100000)
 #define S3C64XX_PA_USB_HSOTG    (0x7C000000)
 #define S3C64XX_PA_WATCHDOG     (0x7E004000)
 #define S3C64XX_PA_SYSCON       (0x7E00F000)
+#define S3C64XX_PA_AC97         (0x7F001000)
 #define S3C64XX_PA_IIS0         (0x7F002000)
 #define S3C64XX_PA_IIS1         (0x7F003000)
 #define S3C64XX_PA_TIMER        (0x7F006000)
 #define S3C64XX_PA_IIC0         (0x7F004000)
+#define S3C64XX_PA_IISV4        (0x7F00D000)
 #define S3C64XX_PA_IIC1         (0x7F00F000)
 #define S3C64XX_PA_GPIO         (0x7F008000)
-#define S3C64XX_VA_GPIO         S3C_ADDR(0x00500000)
+#define S3C64XX_VA_GPIO         S3C_ADDR_CPU(0x00000000)
 #define S3C64XX_SZ_GPIO         SZ_4K
 #define S3C64XX_PA_SDRAM        (0x50000000)
@@ -57,7 +60,7 @@
 #define S3C64XX_PA_VIC1         (0x71300000)
 #define S3C64XX_PA_MODEM        (0x74108000)
-#define S3C64XX_VA_MODEM        S3C_ADDR(0x00600000)
+#define S3C64XX_VA_MODEM        S3C_ADDR_CPU(0x00100000)
 #define S3C64XX_PA_USBHOST      (0x74300000)
@@ -72,6 +75,7 @@
 #define S3C_PA_HSMMC2           S3C64XX_PA_HSMMC2
 #define S3C_PA_IIC              S3C64XX_PA_IIC0
 #define S3C_PA_IIC1             S3C64XX_PA_IIC1
+#define S3C_PA_NAND             S3C64XX_PA_NAND
 #define S3C_PA_FB               S3C64XX_PA_FB
 #define S3C_PA_USBHOST          S3C64XX_PA_USBHOST
 #define S3C_PA_USB_HSOTG        S3C64XX_PA_USB_HSOTG
diff --git a/arch/arm/mach-s3c6400/s3c6400.c b/arch/arm/mach-s3c6400/s3c6400.c
index 1ece887d90bb..b42bdd0f2138 100644
--- a/arch/arm/mach-s3c6400/s3c6400.c
+++ b/arch/arm/mach-s3c6400/s3c6400.c
@@ -48,6 +48,8 @@ void __init s3c6400_map_io(void)
        /* the i2c devices are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
+        s3c_device_nand.name = "s3c6400-nand";
 }
 void __init s3c6400_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c6410/Kconfig b/arch/arm/mach-s3c6410/Kconfig
index e63aac7f4e5a..f9d0f09f9761 100644
--- a/arch/arm/mach-s3c6410/Kconfig
+++ b/arch/arm/mach-s3c6410/Kconfig
@@ -97,3 +97,13 @@ config MACH_NCP
        select S3C64XX_SETUP_I2C1
        help
          Machine support for the Samsung NCP
+config MACH_HMT
+        bool "Airgoo HMT"
+        select CPU_S3C6410
+        select S3C_DEV_FB
+        select S3C_DEV_USB_HOST
+        select S3C64XX_SETUP_FB_24BPP
+        select HAVE_PWM
+        help
+          Machine support for the Airgoo HMT
diff --git a/arch/arm/mach-s3c6410/Makefile b/arch/arm/mach-s3c6410/Makefile
index 6f9deac88612..3e48c3dbf973 100644
--- a/arch/arm/mach-s3c6410/Makefile
+++ b/arch/arm/mach-s3c6410/Makefile
@@ -23,5 +23,4 @@ obj-$(CONFIG_S3C6410_SETUP_SDHCI)	+= setup-sdhci.o
 obj-$(CONFIG_MACH_ANW6410)      += mach-anw6410.o
 obj-$(CONFIG_MACH_SMDK6410)     += mach-smdk6410.o
 obj-$(CONFIG_MACH_NCP)          += mach-ncp.o
+obj-$(CONFIG_MACH_HMT)          += mach-hmt.o
diff --git a/arch/arm/mach-s3c6410/cpu.c b/arch/arm/mach-s3c6410/cpu.c
index ade904de8895..9b67c663d9d8 100644
--- a/arch/arm/mach-s3c6410/cpu.c
+++ b/arch/arm/mach-s3c6410/cpu.c
@@ -62,6 +62,8 @@ void __init s3c6410_map_io(void)
        /* the i2c devices are directly compatible with s3c2440 */
        s3c_i2c0_setname("s3c2440-i2c");
        s3c_i2c1_setname("s3c2440-i2c");
+        s3c_device_nand.name = "s3c6400-nand";
 }
 void __init s3c6410_init_clocks(int xtal)
diff --git a/arch/arm/mach-s3c6410/mach-hmt.c b/arch/arm/mach-s3c6410/mach-hmt.c
new file mode 100644
index 000000000000..c5741056193f
--- /dev/null
+++ b/arch/arm/mach-s3c6410/mach-hmt.c
@@ -0,0 +1,276 @@
+/* mach-hmt.c - Platform code for Airgoo HMT
+ *
+ * Copyright 2009 Peter Korsgaard <jacmet@sunsite.dk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/leds.h>
+#include <linux/pwm_backlight.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/regs-fb.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <plat/regs-serial.h>
+#include <plat/iic.h>
+#include <plat/fb.h>
+#include <plat/nand.h>
+#include <plat/s3c6410.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#define UCON S3C2410_UCON_DEFAULT
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+static struct s3c2410_uartcfg hmt_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+};
+static int hmt_bl_init(struct device *dev)
+{
+        int ret;
+        ret = gpio_request(S3C64XX_GPB(4), "lcd backlight enable");
+        if (!ret)
+                ret = gpio_direction_output(S3C64XX_GPB(4), 0);
+        return ret;
+}
+static int hmt_bl_notify(int brightness)
+{
+        /*
+         * translate from CIELUV/CIELAB L*->brightness, E.G. from
+         * perceived luminance to light output. Assumes range 0..25600
+         */
+        if (brightness < 0x800) {
+                /* Y = Yn * L / 903.3 */
+                brightness = (100*256 * brightness + 231245/2) / 231245;
+        } else {
+                /* Y = Yn * ((L + 16) / 116 )^3 */
+                int t = (brightness*4 + 16*1024 + 58)/116;
+                brightness = 25 * ((t * t * t + 0x100000/2) / 0x100000);
+        }
+        gpio_set_value(S3C64XX_GPB(4), brightness);
+        return brightness;
+}
+static void hmt_bl_exit(struct device *dev)
+{
+        gpio_free(S3C64XX_GPB(4));
+}
+static struct platform_pwm_backlight_data hmt_backlight_data = {
+        .pwm_id         = 1,
+        .max_brightness = 100 * 256,
+        .dft_brightness = 40 * 256,
+        .pwm_period_ns  = 1000000000 / (100 * 256 * 20),
+        .init           = hmt_bl_init,
+        .notify         = hmt_bl_notify,
+        .exit           = hmt_bl_exit,
+};
+static struct platform_device hmt_backlight_device = {
+        .name           = "pwm-backlight",
+        .dev            = {
+                .parent = &s3c_device_timer[1].dev,
+                .platform_data = &hmt_backlight_data,
+        },
+};
+static struct s3c_fb_pd_win hmt_fb_win0 = {
+        .win_mode       = {
+                .pixclock       = 41094,
+                .left_margin    = 8,
+                .right_margin   = 13,
+                .upper_margin   = 7,
+                .lower_margin   = 5,
+                .hsync_len      = 3,
+                .vsync_len      = 1,
+                .xres           = 800,
+                .yres           = 480,
+        },
+        .max_bpp        = 32,
+        .default_bpp    = 16,
+};
+/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
+static struct s3c_fb_platdata hmt_lcd_pdata __initdata = {
+        .setup_gpio     = s3c64xx_fb_gpio_setup_24bpp,
+        .win[0]         = &hmt_fb_win0,
+        .vidcon0        = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+        .vidcon1        = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+static struct mtd_partition hmt_nand_part[] = {
+        [0] = {
+                .name   = "uboot",
+                .size   = SZ_512K,
+                .offset = 0,
+        },
+        [1] = {
+                .name   = "uboot-env1",
+                .size   = SZ_256K,
+                .offset = SZ_512K,
+        },
+        [2] = {
+                .name   = "uboot-env2",
+                .size   = SZ_256K,
+                .offset = SZ_512K + SZ_256K,
+        },
+        [3] = {
+                .name   = "kernel",
+                .size   = SZ_2M,
+                .offset = SZ_1M,
+        },
+        [4] = {
+                .name   = "rootfs",
+                .size   = MTDPART_SIZ_FULL,
+                .offset = SZ_1M + SZ_2M,
+        },
+};
+static struct s3c2410_nand_set hmt_nand_sets[] = {
+        [0] = {
+                .name           = "nand",
+                .nr_chips       = 1,
+                .nr_partitions  = ARRAY_SIZE(hmt_nand_part),
+                .partitions     = hmt_nand_part,
+        },
+};
+static struct s3c2410_platform_nand hmt_nand_info = {
+        .tacls          = 25,
+        .twrph0         = 55,
+        .twrph1         = 40,
+        .nr_sets        = ARRAY_SIZE(hmt_nand_sets),
+        .sets           = hmt_nand_sets,
+};
+static struct gpio_led hmt_leds[] = {
+        { /* left function keys */
+                .name                   = "left:blue",
+                .gpio                   = S3C64XX_GPO(12),
+                .default_trigger        = "default-on",
+        },
+        { /* right function keys - red */
+                .name                   = "right:red",
+                .gpio                   = S3C64XX_GPO(13),
+        },
+        { /* right function keys - green */
+                .name                   = "right:green",
+                .gpio                   = S3C64XX_GPO(14),
+        },
+        { /* right function keys - blue */
+                .name                   = "right:blue",
+                .gpio                   = S3C64XX_GPO(15),
+                .default_trigger        = "default-on",
+        },
+};
+static struct gpio_led_platform_data hmt_led_data = {
+        .num_leds = ARRAY_SIZE(hmt_leds),
+        .leds = hmt_leds,
+};
+static struct platform_device hmt_leds_device = {
+        .name                   = "leds-gpio",
+        .id                     = -1,
+        .dev.platform_data      = &hmt_led_data,
+};
+static struct map_desc hmt_iodesc[] = {};
+static struct platform_device *hmt_devices[] __initdata = {
+        &s3c_device_i2c0,
+        &s3c_device_nand,
+        &s3c_device_fb,
+        &s3c_device_usb,
+        &s3c_device_timer[1],
+        &hmt_backlight_device,
+        &hmt_leds_device,
+};
+static void __init hmt_map_io(void)
+{
+        s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
+}
+static void __init hmt_machine_init(void)
+{
+        s3c_i2c0_set_platdata(NULL);
+        s3c_fb_set_platdata(&hmt_lcd_pdata);
+        s3c_device_nand.dev.platform_data = &hmt_nand_info;
+        gpio_request(S3C64XX_GPC(7), "usb power");
+        gpio_direction_output(S3C64XX_GPC(7), 0);
+        gpio_request(S3C64XX_GPM(0), "usb power");
+        gpio_direction_output(S3C64XX_GPM(0), 1);
+        gpio_request(S3C64XX_GPK(7), "usb power");
+        gpio_direction_output(S3C64XX_GPK(7), 1);
+        gpio_request(S3C64XX_GPF(13), "usb power");
+        gpio_direction_output(S3C64XX_GPF(13), 1);
+        platform_add_devices(hmt_devices, ARRAY_SIZE(hmt_devices));
+}
+MACHINE_START(HMT, "Airgoo-HMT")
+        /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
+        .phys_io        = S3C_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S3C64XX_PA_SDRAM + 0x100,
+        .init_irq       = s3c6410_init_irq,
+        .map_io         = hmt_map_io,
+        .init_machine   = hmt_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c6410/mach-ncp.c b/arch/arm/mach-s3c6410/mach-ncp.c
index 6030636f8548..55e9bbfaf68b 100644
--- a/arch/arm/mach-s3c6410/mach-ncp.c
+++ b/arch/arm/mach-s3c6410/mach-ncp.c
@@ -79,7 +79,7 @@ static struct platform_device *ncp_devices[] __initdata = {
        &s3c_device_i2c0,
 };
-struct map_desc ncp_iodesc[] = {};
+static struct map_desc ncp_iodesc[] __initdata = {};
 static void __init ncp_map_io(void)
 {
diff --git a/arch/arm/mach-s3c6410/mach-smdk6410.c b/arch/arm/mach-s3c6410/mach-smdk6410.c
index bc9a7dea567f..ea51dbe76e3e 100644
--- a/arch/arm/mach-s3c6410/mach-smdk6410.c
+++ b/arch/arm/mach-s3c6410/mach-smdk6410.c
@@ -65,16 +65,30 @@ static struct s3c2410_uartcfg smdk6410_uartcfgs[] __initdata = {
        [0] = {
                .hwport      = 0,
                .flags       = 0,
-                .ucon        = 0x3c5,
+                .ucon        = UCON,
-                .ulcon       = 0x03,
+                .ulcon       = ULCON,
-                .ufcon       = 0x51,
+                .ufcon       = UFCON,
        },
        [1] = {
                .hwport      = 1,
                .flags       = 0,
-                .ucon        = 0x3c5,
+                .ucon        = UCON,
-                .ulcon       = 0x03,
+                .ulcon       = ULCON,
-                .ufcon       = 0x51,
+                .ufcon       = UFCON,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
+        },
+        [3] = {
+                .hwport      = 3,
+                .flags       = 0,
+                .ucon        = UCON,
+                .ulcon       = ULCON,
+                .ufcon       = UFCON,
        },
 };
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
new file mode 100644
index 000000000000..b1a4ba504416
--- /dev/null
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -0,0 +1,22 @@
+# arch/arm/mach-s5pc100/Kconfig
+#
+# Copyright 2009 Samsung Electronics Co.
+#       Byungho Min <bhmin@samsung.com>
+#
+# Licensed under GPLv2
+# Configuration options for the S5PC100 CPU
+config CPU_S5PC100
+        bool
+        select CPU_S5PC100_INIT
+        select CPU_S5PC100_CLOCK
+        help
+          Enable S5PC100 CPU support
+config MACH_SMDKC100
+        bool "SMDKC100"
+        select CPU_S5PC100
+        select S5PC1XX_SETUP_I2C1
+        help
+          Machine support for the Samsung SMDKC100
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
new file mode 100644
index 000000000000..afc89b381d7a
--- /dev/null
+++ b/arch/arm/mach-s5pc100/Makefile
@@ -0,0 +1,17 @@
+# arch/arm/mach-s5pc100/Makefile
+#
+# Copyright 2009 Samsung Electronics Co.
+#
+# Licensed under GPLv2
+obj-y                           :=
+obj-m                           :=
+obj-n                           :=
+obj-                            :=
+# Core support for S5PC100 system
+obj-$(CONFIG_CPU_S5PC100)       += cpu.o
+# machine support
+obj-$(CONFIG_MACH_SMDKC100)     += mach-smdkc100.o
diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
new file mode 100644
index 000000000000..ff90aa13bd67
--- /dev/null
+++ b/arch/arm/mach-s5pc100/Makefile.boot
@@ -0,0 +1,2 @@
+   zreladdr-y   := 0x20008000
+params_phys-y   := 0x20000100
diff --git a/arch/arm/mach-s5pc100/cpu.c b/arch/arm/mach-s5pc100/cpu.c
new file mode 100644
index 000000000000..0e718890da32
--- /dev/null
+++ b/arch/arm/mach-s5pc100/cpu.c
@@ -0,0 +1,97 @@
+/* linux/arch/arm/mach-s5pc100/cpu.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6410/cpu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+#include <plat/cpu-freq.h>
+#include <plat/regs-serial.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/sdhci.h>
+#include <plat/iic-core.h>
+#include <plat/s5pc100.h>
+/* Initial IO mappings */
+static struct map_desc s5pc100_iodesc[] __initdata = {
+};
+/* s5pc100_map_io
+ *
+ * register the standard cpu IO areas
+*/
+void __init s5pc100_map_io(void)
+{
+        iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
+        /* initialise device information early */
+}
+void __init s5pc100_init_clocks(int xtal)
+{
+        printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
+        s3c24xx_register_baseclocks(xtal);
+        s5pc1xx_register_clocks();
+        s5pc100_register_clocks();
+        s5pc100_setup_clocks();
+}
+void __init s5pc100_init_irq(void)
+{
+        u32 vic_valid[] = {~0, ~0, ~0};
+        /* VIC0, VIC1, and VIC2 are fully populated. */
+        s5pc1xx_init_irq(vic_valid, ARRAY_SIZE(vic_valid));
+}
+struct sysdev_class s5pc100_sysclass = {
+        .name   = "s5pc100-core",
+};
+static struct sys_device s5pc100_sysdev = {
+        .cls    = &s5pc100_sysclass,
+};
+static int __init s5pc100_core_init(void)
+{
+        return sysdev_class_register(&s5pc100_sysclass);
+}
+core_initcall(s5pc100_core_init);
+int __init s5pc100_init(void)
+{
+        printk(KERN_DEBUG "S5PC100: Initialising architecture\n");
+        return sysdev_register(&s5pc100_sysdev);
+}
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9d142ccf654b
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
+/* arch/arm/mach-s5pc100/include/mach/debug-macro.S
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ *
+ * Based on mach-s3c6400/include/mach/debug-macro.S
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* pull in the relevant register and map files. */
+#include <mach/map.h>
+#include <plat/regs-serial.h>
+        /* note, for the boot process to work we have to keep the UART
+         * virtual address aligned to an 1MiB boundary for the L1
+         * mapping the head code makes. We keep the UART virtual address
+         * aligned and add in the offset when we load the value here.
+         */
+        .macro addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1
+                ldreq   \rx, = S3C_PA_UART
+                ldrne   \rx, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
+                add     \rx, \rx, #(0x400 * CONFIG_DEBUG_S3C_UART)
+        .endm
+/* include the reset of the code which will do the work, we're only
+ * compiling for a single cpu processor type so the default of s3c2440
+ * will be fine with us.
+ */
+#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
new file mode 100644
index 000000000000..67131939e626
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
@@ -0,0 +1,50 @@
+/* arch/arm/mach-s5pc100/include/mach/entry-macro.S
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros for the Samsung S5PC1XX series
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+*/
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/irqs.h>
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =S3C_VA_VIC0
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        @ check the vic0
+        mov     \irqnr, # S3C_IRQ_OFFSET + 31
+        ldr     \irqstat, [ \base, # VIC_IRQ_STATUS ]
+        teq     \irqstat, #0
+        @ otherwise try vic1
+        addeq   \tmp, \base, #(S3C_VA_VIC1 - S3C_VA_VIC0)
+        addeq   \irqnr, \irqnr, #32
+        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+        teqeq   \irqstat, #0
+        @ otherwise try vic2
+        addeq   \tmp, \base, #(S3C_VA_VIC2 - S3C_VA_VIC0)
+        addeq   \irqnr, \irqnr, #32
+        ldreq   \irqstat, [ \tmp, # VIC_IRQ_STATUS ]
+        teqeq   \irqstat, #0
+        clzne   \irqstat, \irqstat
+        subne   \irqnr, \irqnr, \irqstat
+        .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio-core.h b/arch/arm/mach-s5pc100/include/mach/gpio-core.h
new file mode 100644
index 000000000000..ad28d8ec8a78
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/gpio-core.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-s5pc100/include/mach/gpio-core.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - GPIO core support
+ *
+ * Based on mach-s3c6400/include/mach/gpio-core.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_GPIO_CORE_H
+#define __ASM_ARCH_GPIO_CORE_H __FILE__
+/* currently we just include the platform support */
+#include <plat/gpio-core.h>
+#endif /* __ASM_ARCH_GPIO_CORE_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
new file mode 100644
index 000000000000..c74fc93d7d15
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/gpio.h
@@ -0,0 +1,146 @@
+/* arch/arm/mach-s5pc100/include/mach/gpio.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - GPIO lib support
+ *
+ * Base on mach-s3c6400/include/mach/gpio.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
+/* GPIO bank sizes */
+#define S5PC1XX_GPIO_A0_NR      (8)
+#define S5PC1XX_GPIO_A1_NR      (5)
+#define S5PC1XX_GPIO_B_NR       (8)
+#define S5PC1XX_GPIO_C_NR       (5)
+#define S5PC1XX_GPIO_D_NR       (7)
+#define S5PC1XX_GPIO_E0_NR      (8)
+#define S5PC1XX_GPIO_E1_NR      (6)
+#define S5PC1XX_GPIO_F0_NR      (8)
+#define S5PC1XX_GPIO_F1_NR      (8)
+#define S5PC1XX_GPIO_F2_NR      (8)
+#define S5PC1XX_GPIO_F3_NR      (4)
+#define S5PC1XX_GPIO_G0_NR      (8)
+#define S5PC1XX_GPIO_G1_NR      (3)
+#define S5PC1XX_GPIO_G2_NR      (7)
+#define S5PC1XX_GPIO_G3_NR      (7)
+#define S5PC1XX_GPIO_H0_NR      (8)
+#define S5PC1XX_GPIO_H1_NR      (8)
+#define S5PC1XX_GPIO_H2_NR      (8)
+#define S5PC1XX_GPIO_H3_NR      (8)
+#define S5PC1XX_GPIO_I_NR       (8)
+#define S5PC1XX_GPIO_J0_NR      (8)
+#define S5PC1XX_GPIO_J1_NR      (5)
+#define S5PC1XX_GPIO_J2_NR      (8)
+#define S5PC1XX_GPIO_J3_NR      (8)
+#define S5PC1XX_GPIO_J4_NR      (4)
+#define S5PC1XX_GPIO_K0_NR      (8)
+#define S5PC1XX_GPIO_K1_NR      (6)
+#define S5PC1XX_GPIO_K2_NR      (8)
+#define S5PC1XX_GPIO_K3_NR      (8)
+#define S5PC1XX_GPIO_MP00_NR    (8)
+#define S5PC1XX_GPIO_MP01_NR    (8)
+#define S5PC1XX_GPIO_MP02_NR    (8)
+#define S5PC1XX_GPIO_MP03_NR    (8)
+#define S5PC1XX_GPIO_MP04_NR    (5)
+/* GPIO bank numbes */
+/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
+ * space for debugging purposes so that any accidental
+ * change from one gpio bank to another can be caught.
+*/
+#define S5PC1XX_GPIO_NEXT(__gpio) \
+        ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
+enum s3c_gpio_number {
+        S5PC1XX_GPIO_A0_START   = 0,
+        S5PC1XX_GPIO_A1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A0),
+        S5PC1XX_GPIO_B_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_A1),
+        S5PC1XX_GPIO_C_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_B),
+        S5PC1XX_GPIO_D_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_C),
+        S5PC1XX_GPIO_E0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_D),
+        S5PC1XX_GPIO_E1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E0),
+        S5PC1XX_GPIO_F0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_E1),
+        S5PC1XX_GPIO_F1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F0),
+        S5PC1XX_GPIO_F2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F1),
+        S5PC1XX_GPIO_F3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F2),
+        S5PC1XX_GPIO_G0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_F3),
+        S5PC1XX_GPIO_G1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G0),
+        S5PC1XX_GPIO_G2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G1),
+        S5PC1XX_GPIO_G3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G2),
+        S5PC1XX_GPIO_H0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_G3),
+        S5PC1XX_GPIO_H1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H0),
+        S5PC1XX_GPIO_H2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H1),
+        S5PC1XX_GPIO_H3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H2),
+        S5PC1XX_GPIO_I_START    = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_H3),
+        S5PC1XX_GPIO_J0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_I),
+        S5PC1XX_GPIO_J1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J0),
+        S5PC1XX_GPIO_J2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J1),
+        S5PC1XX_GPIO_J3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J2),
+        S5PC1XX_GPIO_J4_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J3),
+        S5PC1XX_GPIO_K0_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_J4),
+        S5PC1XX_GPIO_K1_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K0),
+        S5PC1XX_GPIO_K2_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K1),
+        S5PC1XX_GPIO_K3_START   = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K2),
+        S5PC1XX_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_K3),
+        S5PC1XX_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP00),
+        S5PC1XX_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP01),
+        S5PC1XX_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP02),
+        S5PC1XX_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC1XX_GPIO_MP03),
+};
+/* S5PC1XX GPIO number definitions. */
+#define S5PC1XX_GPA0(_nr)       (S5PC1XX_GPIO_A0_START + (_nr))
+#define S5PC1XX_GPA1(_nr)       (S5PC1XX_GPIO_A1_START + (_nr))
+#define S5PC1XX_GPB(_nr)        (S5PC1XX_GPIO_B_START + (_nr))
+#define S5PC1XX_GPC(_nr)        (S5PC1XX_GPIO_C_START + (_nr))
+#define S5PC1XX_GPD(_nr)        (S5PC1XX_GPIO_D_START + (_nr))
+#define S5PC1XX_GPE0(_nr)       (S5PC1XX_GPIO_E0_START + (_nr))
+#define S5PC1XX_GPE1(_nr)       (S5PC1XX_GPIO_E1_START + (_nr))
+#define S5PC1XX_GPF0(_nr)       (S5PC1XX_GPIO_F0_START + (_nr))
+#define S5PC1XX_GPF1(_nr)       (S5PC1XX_GPIO_F1_START + (_nr))
+#define S5PC1XX_GPF2(_nr)       (S5PC1XX_GPIO_F2_START + (_nr))
+#define S5PC1XX_GPF3(_nr)       (S5PC1XX_GPIO_F3_START + (_nr))
+#define S5PC1XX_GPG0(_nr)       (S5PC1XX_GPIO_G0_START + (_nr))
+#define S5PC1XX_GPG1(_nr)       (S5PC1XX_GPIO_G1_START + (_nr))
+#define S5PC1XX_GPG2(_nr)       (S5PC1XX_GPIO_G2_START + (_nr))
+#define S5PC1XX_GPG3(_nr)       (S5PC1XX_GPIO_G3_START + (_nr))
+#define S5PC1XX_GPH0(_nr)       (S5PC1XX_GPIO_H0_START + (_nr))
+#define S5PC1XX_GPH1(_nr)       (S5PC1XX_GPIO_H1_START + (_nr))
+#define S5PC1XX_GPH2(_nr)       (S5PC1XX_GPIO_H2_START + (_nr))
+#define S5PC1XX_GPH3(_nr)       (S5PC1XX_GPIO_H3_START + (_nr))
+#define S5PC1XX_GPI(_nr)        (S5PC1XX_GPIO_I_START + (_nr))
+#define S5PC1XX_GPJ0(_nr)       (S5PC1XX_GPIO_J0_START + (_nr))
+#define S5PC1XX_GPJ1(_nr)       (S5PC1XX_GPIO_J1_START + (_nr))
+#define S5PC1XX_GPJ2(_nr)       (S5PC1XX_GPIO_J2_START + (_nr))
+#define S5PC1XX_GPJ3(_nr)       (S5PC1XX_GPIO_J3_START + (_nr))
+#define S5PC1XX_GPJ4(_nr)       (S5PC1XX_GPIO_J4_START + (_nr))
+#define S5PC1XX_GPK0(_nr)       (S5PC1XX_GPIO_K0_START + (_nr))
+#define S5PC1XX_GPK1(_nr)       (S5PC1XX_GPIO_K1_START + (_nr))
+#define S5PC1XX_GPK2(_nr)       (S5PC1XX_GPIO_K2_START + (_nr))
+#define S5PC1XX_GPK3(_nr)       (S5PC1XX_GPIO_K3_START + (_nr))
+#define S5PC1XX_MP00(_nr)       (S5PC1XX_GPIO_MP00_START + (_nr))
+#define S5PC1XX_MP01(_nr)       (S5PC1XX_GPIO_MP01_START + (_nr))
+#define S5PC1XX_MP02(_nr)       (S5PC1XX_GPIO_MP02_START + (_nr))
+#define S5PC1XX_MP03(_nr)       (S5PC1XX_GPIO_MP03_START + (_nr))
+#define S5PC1XX_MP04(_nr)       (S5PC1XX_GPIO_MP04_START + (_nr))
+/* the end of the S5PC1XX specific gpios */
+#define S5PC1XX_GPIO_END        (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#define S3C_GPIO_END            S5PC1XX_GPIO_END
+/* define the number of gpios we need to the one after the MP04() range */
+#define ARCH_NR_GPIOS   (S5PC1XX_MP04(S5PC1XX_GPIO_MP04_NR) + 1)
+#include <asm-generic/gpio.h>
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h
new file mode 100644
index 000000000000..6b38618c2fd9
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/hardware.h
@@ -0,0 +1,14 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - Hardware support
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H __FILE__
+/* currently nothing here, placeholder */
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
new file mode 100644
index 000000000000..622720dba289
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/irqs.h
@@ -0,0 +1,14 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - IRQ definitions
+ */
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+#include <plat/irqs.h>
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
new file mode 100644
index 000000000000..9e9f39130b2c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -0,0 +1,75 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/map.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/map.h
+ *
+ * S5PC1XX - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H __FILE__
+#include <plat/map-base.h>
+/* Chip ID */
+#define S5PC100_PA_CHIPID       (0xE0000000)
+#define S5PC1XX_PA_CHIPID       S5PC100_PA_CHIPID
+#define S5PC1XX_VA_CHIPID       S3C_VA_SYS
+/* System */
+#define S5PC100_PA_SYS          (0xE0100000)
+#define S5PC100_PA_CLK          (S5PC100_PA_SYS + 0x0)
+#define S5PC100_PA_PWR          (S5PC100_PA_SYS + 0x8000)
+#define S5PC1XX_PA_CLK          S5PC100_PA_CLK
+#define S5PC1XX_PA_PWR          S5PC100_PA_PWR
+#define S5PC1XX_VA_CLK          (S3C_VA_SYS + 0x10000)
+#define S5PC1XX_VA_PWR          (S3C_VA_SYS + 0x20000)
+/* Interrupt */
+#define S5PC100_PA_VIC          (0xE4000000)
+#define S5PC100_VA_VIC          S3C_VA_IRQ
+#define S5PC100_PA_VIC_OFFSET   0x100000
+#define S5PC100_VA_VIC_OFFSET   0x10000
+#define S5PC1XX_PA_VIC(x)       (S5PC100_PA_VIC + ((x) * S5PC100_PA_VIC_OFFSET))
+#define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+/* Timer */
+#define S5PC100_PA_TIMER        (0xEA000000)
+#define S5PC1XX_PA_TIMER        S5PC100_PA_TIMER
+#define S5PC1XX_VA_TIMER        S3C_VA_TIMER
+/* UART */
+#define S5PC100_PA_UART         (0xEC000000)
+#define S5PC1XX_PA_UART         S5PC100_PA_UART
+#define S5PC1XX_VA_UART         S3C_VA_UART
+/* IIC */
+#define S5PC100_PA_IIC          (0xEC100000)
+/* ETC */
+#define S5PC100_PA_SDRAM        (0x20000000)
+/* compatibility defines. */
+#define S3C_PA_UART             S5PC100_PA_UART
+#define S3C_PA_UART0            (S5PC100_PA_UART + 0x0)
+#define S3C_PA_UART1            (S5PC100_PA_UART + 0x400)
+#define S3C_PA_UART2            (S5PC100_PA_UART + 0x800)
+#define S3C_PA_UART3            (S5PC100_PA_UART + 0xC00)
+#define S3C_VA_UART0            (S3C_VA_UART + 0x0)
+#define S3C_VA_UART1            (S3C_VA_UART + 0x400)
+#define S3C_VA_UART2            (S3C_VA_UART + 0x800)
+#define S3C_VA_UART3            (S3C_VA_UART + 0xC00)
+#define S3C_UART_OFFSET         0x400
+#define S3C_VA_VIC0             (S3C_VA_IRQ + 0x0)
+#define S3C_VA_VIC1             (S3C_VA_IRQ + 0x10000)
+#define S3C_VA_VIC2             (S3C_VA_IRQ + 0x20000)
+#define S3C_PA_IIC              S5PC100_PA_IIC
+#endif /* __ASM_ARCH_C100_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h
new file mode 100644
index 000000000000..4b60d18179f7
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/memory.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s5pc100/include/mach/memory.h
+ *
+ * Copyright 2008 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on mach-s3c6400/include/mach/memory.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET             UL(0x20000000)
+#endif
diff --git a/arch/arm/mach-s5pc100/include/mach/pwm-clock.h b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
new file mode 100644
index 000000000000..b34d2f7aae52
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
@@ -0,0 +1,56 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/pwm-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - pwm clock and timer support
+ *
+ * Based on mach-s3c6400/include/mach/pwm-clock.h
+ */
+/**
+ * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
+ * @tcfg: The timer TCFG1 register bits shifted down to 0.
+ *
+ * Return true if the given configuration from TCFG1 is a TCLK instead
+ * any of the TDIV clocks.
+ */
+static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
+{
+        return tcfg >= S3C64XX_TCFG1_MUX_TCLK;
+}
+/**
+ * tcfg_to_divisor() - convert tcfg1 setting to a divisor
+ * @tcfg1: The tcfg1 setting, shifted down.
+ *
+ * Get the divisor value for the given tcfg1 setting. We assume the
+ * caller has already checked to see if this is not a TCLK source.
+ */
+static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
+{
+        return 1 << tcfg1;
+}
+/**
+ * pwm_tdiv_has_div1() - does the tdiv setting have a /1
+ *
+ * Return true if we have a /1 in the tdiv setting.
+ */
+static inline unsigned int pwm_tdiv_has_div1(void)
+{
+        return 1;
+}
+/**
+ * pwm_tdiv_div_bits() - calculate TCFG1 divisor value.
+ * @div: The divisor to calculate the bit information for.
+ *
+ * Turn a divisor into the necessary bit field for TCFG1.
+ */
+static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
+{
+        return ilog2(div);
+}
+#define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
new file mode 100644
index 000000000000..751ac15438c8
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
@@ -0,0 +1,24 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - IRQ register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_REGS_IRQ_H
+#define __ASM_ARCH_REGS_IRQ_H __FILE__
+#include <mach/map.h>
+#include <asm/hardware/vic.h>
+/* interrupt controller */
+#define S5PC1XX_VIC0REG(x)                      ((x) + S5PC1XX_VA_VIC(0))
+#define S5PC1XX_VIC1REG(x)                      ((x) + S5PC1XX_VA_VIC(1))
+#define S5PC1XX_VIC2REG(x)                      ((x) + S5PC1XX_VA_VIC(2))
+#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/system.h b/arch/arm/mach-s5pc100/include/mach/system.h
new file mode 100644
index 000000000000..e39014375470
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/system.h
@@ -0,0 +1,24 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/system.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - system implementation
+ *
+ * Based on mach-s3c6400/include/mach/system.h
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H __FILE__
+static void arch_idle(void)
+{
+        /* nothing here yet */
+}
+static void arch_reset(char mode, const char *cmd)
+{
+        /* nothing here yet */
+}
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/tick.h b/arch/arm/mach-s5pc100/include/mach/tick.h
new file mode 100644
index 000000000000..d3de0f3591ae
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/tick.h
@@ -0,0 +1,29 @@
+/* linux/arch/arm/mach-s5pc100/include/mach/tick.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S3C64XX - Timer tick support definitions
+ *
+ * Based on mach-s3c6400/include/mach/tick.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_TICK_H
+#define __ASM_ARCH_TICK_H __FILE__
+/* note, the timer interrutps turn up in 2 places, the vic and then
+ * the timer block. We take the VIC as the base at the moment.
+ */
+static inline u32 s3c24xx_ostimer_pending(void)
+{
+        u32 pend = __raw_readl(S3C_VA_VIC0 + VIC_RAW_STATUS);
+        return pend & 1 << (IRQ_TIMER4 - S5PC1XX_IRQ_VIC0(0));
+}
+#define TICK_MAX        (0xffffffff)
+#endif /* __ASM_ARCH_TICK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/uncompress.h b/arch/arm/mach-s5pc100/include/mach/uncompress.h
new file mode 100644
index 000000000000..01ccf535e76c
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/uncompress.h
@@ -0,0 +1,28 @@
+/* arch/arm/mach-s5pc100/include/mach/uncompress.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - uncompress code
+ *
+ * Based on mach-s3c6400/include/mach/uncompress.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+#include <mach/map.h>
+#include <plat/uncompress.h>
+static void arch_detect_cpu(void)
+{
+        /* we do not need to do any cpu detection here at the moment. */
+        fifo_mask = S3C2440_UFSTAT_TXMASK;
+        fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
+}
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
new file mode 100644
index 000000000000..214093cd7632
--- /dev/null
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -0,0 +1,103 @@
+/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ * Author: Byungho Min <bhmin@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/map.h>
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <plat/regs-serial.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/s5pc100.h>
+#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
+        [0] = {
+                .hwport      = 0,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [1] = {
+                .hwport      = 1,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [2] = {
+                .hwport      = 2,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+        [3] = {
+                .hwport      = 3,
+                .flags       = 0,
+                .ucon        = 0x3c5,
+                .ulcon       = 0x03,
+                .ufcon       = 0x51,
+        },
+};
+static struct map_desc smdkc100_iodesc[] = {};
+static struct platform_device *smdkc100_devices[] __initdata = {
+};
+static void __init smdkc100_map_io(void)
+{
+        s5pc1xx_init_io(smdkc100_iodesc, ARRAY_SIZE(smdkc100_iodesc));
+        s3c24xx_init_clocks(12000000);
+        s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
+}
+static void __init smdkc100_machine_init(void)
+{
+        platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
+}
+MACHINE_START(SMDKC100, "SMDKC100")
+        /* Maintainer: Byungho Min <bhmin@samsung.com> */
+        .phys_io        = S5PC1XX_PA_UART & 0xfff00000,
+        .io_pg_offst    = (((u32)S5PC1XX_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = S5PC100_PA_SDRAM + 0x100,
+        .init_irq       = s5pc100_init_irq,
+        .map_io         = smdkc100_map_io,
+        .init_machine   = smdkc100_machine_init,
+        .timer          = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-u300/mmc.c b/arch/arm/mach-u300/mmc.c
index 3138d3955c9e..585cc013639d 100644
--- a/arch/arm/mach-u300/mmc.c
+++ b/arch/arm/mach-u300/mmc.c
@@ -156,6 +156,8 @@ int __devinit mmc_init(struct amba_device *adev)
        mmci_card->mmc0_plat_data.ocr_mask = MMC_VDD_28_29;
        mmci_card->mmc0_plat_data.translate_vdd = mmc_translate_vdd;
        mmci_card->mmc0_plat_data.status = mmc_status;
+        mmci_card->mmc0_plat_data.gpio_wp = -1;
+        mmci_card->mmc0_plat_data.gpio_cd = -1;
        mmcsd_device->platform_data = (void *) &mmci_card->mmc0_plat_data;
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index 31093af7d052..975eae41ee66 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -26,6 +26,7 @@
 #include <linux/interrupt.h>
 #include <linux/amba/bus.h>
 #include <linux/amba/clcd.h>
+#include <linux/amba/pl061.h>
 #include <linux/clocksource.h>
 #include <linux/clockchips.h>
 #include <linux/cnt32_to_63.h>
@@ -371,6 +372,8 @@ unsigned int mmc_status(struct device *dev)
 static struct mmc_platform_data mmc0_plat_data = {
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
        .status         = mmc_status,
+        .gpio_wp        = -1,
+        .gpio_cd        = -1,
 };
 /*
@@ -705,6 +708,16 @@ static struct clcd_board clcd_plat_data = {
        .remove         = versatile_clcd_remove,
 };
+static struct pl061_platform_data gpio0_plat_data = {
+        .gpio_base      = 0,
+        .irq_base       = IRQ_GPIO0_START,
+};
+static struct pl061_platform_data gpio1_plat_data = {
+        .gpio_base      = 8,
+        .irq_base       = IRQ_GPIO1_START,
+};
 #define AACI_IRQ        { IRQ_AACI, NO_IRQ }
 #define AACI_DMA        { 0x80, 0x81 }
 #define MMCI0_IRQ       { IRQ_MMCI0A,IRQ_SIC_MMCI0B }
@@ -767,8 +780,8 @@ AMBA_DEVICE(clcd,  "dev:20",  CLCD,     &clcd_plat_data);
 AMBA_DEVICE(dmac,  "dev:30",  DMAC,     NULL);
 AMBA_DEVICE(sctl,  "dev:e0",  SCTL,     NULL);
 AMBA_DEVICE(wdog,  "dev:e1",  WATCHDOG, NULL);
-AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    NULL);
+AMBA_DEVICE(gpio0, "dev:e4",  GPIO0,    &gpio0_plat_data);
-AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    NULL);
+AMBA_DEVICE(gpio1, "dev:e5",  GPIO1,    &gpio1_plat_data);
 AMBA_DEVICE(rtc,   "dev:e8",  RTC,      NULL);
 AMBA_DEVICE(sci0,  "dev:f0",  SCI,      NULL);
 AMBA_DEVICE(uart0, "dev:f1",  UART0,    NULL);
diff --git a/arch/arm/mach-versatile/include/mach/gpio.h b/arch/arm/mach-versatile/include/mach/gpio.h
new file mode 100644
index 000000000000..94ff27678a46
--- /dev/null
+++ b/arch/arm/mach-versatile/include/mach/gpio.h
@@ -0,0 +1,6 @@
+#include <asm-generic/gpio.h>
+#define gpio_get_value  __gpio_get_value
+#define gpio_set_value  __gpio_set_value
+#define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
diff --git a/arch/arm/mach-versatile/include/mach/irqs.h b/arch/arm/mach-versatile/include/mach/irqs.h
index 9bfdb30e1f3f..bf44c61bd1f6 100644
--- a/arch/arm/mach-versatile/include/mach/irqs.h
+++ b/arch/arm/mach-versatile/include/mach/irqs.h
@@ -122,4 +122,13 @@
 #define IRQ_SIC_PCI3            (IRQ_SIC_START + SIC_INT_PCI3)
 #define IRQ_SIC_END             63
-#define NR_IRQS                 64
+#define IRQ_GPIO0_START         (IRQ_SIC_END + 1)
+#define IRQ_GPIO0_END           (IRQ_GPIO0_START + 31)
+#define IRQ_GPIO1_START         (IRQ_GPIO0_END + 1)
+#define IRQ_GPIO1_END           (IRQ_GPIO1_START + 31)
+#define IRQ_GPIO2_START         (IRQ_GPIO1_END + 1)
+#define IRQ_GPIO2_END           (IRQ_GPIO2_START + 31)
+#define IRQ_GPIO3_START         (IRQ_GPIO2_END + 1)
+#define IRQ_GPIO3_END           (IRQ_GPIO3_START + 31)
+#define NR_IRQS                 (IRQ_GPIO3_END + 1)
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index aa051c0884f8..9af8d8154df5 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -23,6 +23,7 @@
 #include <linux/device.h>
 #include <linux/sysdev.h>
 #include <linux/amba/bus.h>
+#include <linux/amba/pl061.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
@@ -43,6 +44,18 @@
 static struct mmc_platform_data mmc1_plat_data = {
        .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
        .status         = mmc_status,
+        .gpio_wp        = -1,
+        .gpio_cd        = -1,
+};
+static struct pl061_platform_data gpio2_plat_data = {
+        .gpio_base      = 16,
+        .irq_base       = IRQ_GPIO2_START,
+};
+static struct pl061_platform_data gpio3_plat_data = {
+        .gpio_base      = 24,
+        .irq_base       = IRQ_GPIO3_START,
 };
 #define UART3_IRQ       { IRQ_SIC_UART3, NO_IRQ }
@@ -70,8 +83,8 @@ AMBA_DEVICE(sci1,  "fpga:0a", SCI1,     NULL);
 AMBA_DEVICE(mmc1,  "fpga:0b", MMCI1,    &mmc1_plat_data);
 /* DevChip Primecells */
-AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    NULL);
+AMBA_DEVICE(gpio2, "dev:e6",  GPIO2,    &gpio2_plat_data);
-AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    NULL);
+AMBA_DEVICE(gpio3, "dev:e7",  GPIO3,    &gpio3_plat_data);
 static struct amba_device *amba_devs[] __initdata = {
        &uart3_device,
diff --git a/arch/arm/mach-w90x900/Kconfig b/arch/arm/mach-w90x900/Kconfig
index 8e4178fe5ec2..69bab32a8bc2 100644
--- a/arch/arm/mach-w90x900/Kconfig
+++ b/arch/arm/mach-w90x900/Kconfig
@@ -5,6 +5,16 @@ config CPU_W90P910
        help
          Support for W90P910 of Nuvoton W90X900 CPUs.
+config CPU_NUC950
+        bool
+        help
+          Support for NUCP950 of Nuvoton NUC900 CPUs.
+config CPU_NUC960
+        bool
+        help
+          Support for NUCP960 of Nuvoton NUC900 CPUs.
 menu "W90P910 Machines"
 config MACH_W90P910EVB
@@ -16,4 +26,24 @@ config MACH_W90P910EVB
 endmenu
+menu "NUC950 Machines"
+config MACH_W90P950EVB
+        bool "Nuvoton NUC950 Evaluation Board"
+        select CPU_NUC950
+        help
+           Say Y here if you are using the Nuvoton NUC950EVB
+endmenu
+menu "NUC960 Machines"
+config MACH_W90N960EVB
+        bool "Nuvoton NUC960 Evaluation Board"
+        select CPU_NUC960
+        help
+           Say Y here if you are using the Nuvoton NUC960EVB
+endmenu
 endif
diff --git a/arch/arm/mach-w90x900/Makefile b/arch/arm/mach-w90x900/Makefile
index d50c94f4dbdf..828c0326441e 100644
--- a/arch/arm/mach-w90x900/Makefile
+++ b/arch/arm/mach-w90x900/Makefile
@@ -4,12 +4,16 @@
 # Object file lists.
-obj-y                           := irq.o time.o mfp-w90p910.o gpio.o clock.o
+obj-y                           := irq.o time.o mfp.o gpio.o clock.o
+obj-y                           += clksel.o dev.o cpu.o
 # W90X900 CPU support files
-obj-$(CONFIG_CPU_W90P910)       += w90p910.o
+obj-$(CONFIG_CPU_W90P910)       += nuc910.o
+obj-$(CONFIG_CPU_NUC950)        += nuc950.o
+obj-$(CONFIG_CPU_NUC960)        += nuc960.o
 # machine support
-obj-$(CONFIG_MACH_W90P910EVB)   += mach-w90p910evb.o
+obj-$(CONFIG_MACH_W90P910EVB)   += mach-nuc910evb.o
+obj-$(CONFIG_MACH_W90P950EVB)   += mach-nuc950evb.o
+obj-$(CONFIG_MACH_W90N960EVB)   += mach-nuc960evb.o
diff --git a/arch/arm/mach-w90x900/clksel.c b/arch/arm/mach-w90x900/clksel.c
new file mode 100644
index 000000000000..3de4a5211c3b
--- /dev/null
+++ b/arch/arm/mach-w90x900/clksel.c
@@ -0,0 +1,91 @@
+/*
+ * linux/arch/arm/mach-w90x900/clksel.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/regs-clock.h>
+#define PLL0            0x00
+#define PLL1            0x01
+#define OTHER           0x02
+#define EXT             0x03
+#define MSOFFSET        0x0C
+#define ATAOFFSET       0x0a
+#define LCDOFFSET       0x06
+#define AUDOFFSET       0x04
+#define CPUOFFSET       0x00
+static DEFINE_MUTEX(clksel_sem);
+static void clock_source_select(const char *dev_id, unsigned int clkval)
+{
+        unsigned int clksel, offset;
+        clksel = __raw_readl(REG_CLKSEL);
+        if (strcmp(dev_id, "nuc900-ms") == 0)
+                offset = MSOFFSET;
+        else if (strcmp(dev_id, "nuc900-atapi") == 0)
+                offset = ATAOFFSET;
+        else if (strcmp(dev_id, "nuc900-lcd") == 0)
+                offset = LCDOFFSET;
+        else if (strcmp(dev_id, "nuc900-audio") == 0)
+                offset = AUDOFFSET;
+        else
+                offset = CPUOFFSET;
+        clksel &= ~(0x03 << offset);
+        clksel |= (clkval << offset);
+        __raw_writel(clksel, REG_CLKSEL);
+}
+void nuc900_clock_source(struct device *dev, unsigned char *src)
+{
+        unsigned int clkval;
+        const char *dev_id;
+        BUG_ON(!src);
+        clkval = 0;
+        mutex_lock(&clksel_sem);
+        if (dev)
+                dev_id = dev_name(dev);
+        else
+                dev_id = "cpufreq";
+        if (strcmp(src, "pll0") == 0)
+                clkval = PLL0;
+        else if (strcmp(src, "pll1") == 0)
+                clkval = PLL1;
+        else if (strcmp(src, "ext") == 0)
+                clkval = EXT;
+        else if (strcmp(src, "oth") == 0)
+                clkval = OTHER;
+        clock_source_select(dev_id, clkval);
+        mutex_unlock(&clksel_sem);
+}
+EXPORT_SYMBOL(nuc900_clock_source);
diff --git a/arch/arm/mach-w90x900/clock.c b/arch/arm/mach-w90x900/clock.c
index f420613cd395..b785994bab0a 100644
--- a/arch/arm/mach-w90x900/clock.c
+++ b/arch/arm/mach-w90x900/clock.c
@@ -25,6 +25,8 @@
 #include "clock.h"
+#define SUBCLK 0x24
 static DEFINE_SPINLOCK(clocks_lock);
 int clk_enable(struct clk *clk)
@@ -53,7 +55,13 @@ void clk_disable(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_disable);
-void w90x900_clk_enable(struct clk *clk, int enable)
+unsigned long clk_get_rate(struct clk *clk)
+{
+        return 15000000;
+}
+EXPORT_SYMBOL(clk_get_rate);
+void nuc900_clk_enable(struct clk *clk, int enable)
 {
        unsigned int clocks = clk->cken;
        unsigned long clken;
@@ -68,6 +76,22 @@ void w90x900_clk_enable(struct clk *clk, int enable)
        __raw_writel(clken, W90X900_VA_CLKPWR);
 }
+void nuc900_subclk_enable(struct clk *clk, int enable)
+{
+        unsigned int clocks = clk->cken;
+        unsigned long clken;
+        clken = __raw_readl(W90X900_VA_CLKPWR + SUBCLK);
+        if (enable)
+                clken |= clocks;
+        else
+                clken &= ~clocks;
+        __raw_writel(clken, W90X900_VA_CLKPWR + SUBCLK);
+}
 void clks_register(struct clk_lookup *clks, size_t num)
 {
        int i;
diff --git a/arch/arm/mach-w90x900/clock.h b/arch/arm/mach-w90x900/clock.h
index 4f27bda76d56..f5816a06eed6 100644
--- a/arch/arm/mach-w90x900/clock.h
+++ b/arch/arm/mach-w90x900/clock.h
@@ -12,7 +12,8 @@
 #include <asm/clkdev.h>
-void w90x900_clk_enable(struct clk *clk, int enable);
+void nuc900_clk_enable(struct clk *clk, int enable);
+void nuc900_subclk_enable(struct clk *clk, int enable);
 void clks_register(struct clk_lookup *clks, size_t num);
 struct clk {
@@ -23,10 +24,17 @@ struct clk {
 #define DEFINE_CLK(_name, _ctrlbit)                     \
 struct clk clk_##_name = {                              \
-                .enable = w90x900_clk_enable,           \
+                .enable = nuc900_clk_enable,            \
                .cken   = (1 << _ctrlbit),              \
        }
+#define DEFINE_SUBCLK(_name, _ctrlbit)                  \
+struct clk clk_##_name = {                              \
+                .enable = nuc900_subclk_enable, \
+                .cken   = (1 << _ctrlbit),              \
+        }
 #define DEF_CLKLOOK(_clk, _devname, _conname)           \
        {                                               \
                .clk            = _clk,                 \
diff --git a/arch/arm/mach-w90x900/cpu.c b/arch/arm/mach-w90x900/cpu.c
new file mode 100644
index 000000000000..921cef991bf0
--- /dev/null
+++ b/arch/arm/mach-w90x900/cpu.c
@@ -0,0 +1,212 @@
+/*
+ * linux/arch/arm/mach-w90x900/cpu.c
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC900 series cpu common support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/serial_8250.h>
+#include <linux/delay.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/irq.h>
+#include <mach/hardware.h>
+#include <mach/regs-serial.h>
+#include <mach/regs-clock.h>
+#include <mach/regs-ebi.h>
+#include "cpu.h"
+#include "clock.h"
+/* Initial IO mappings */
+static struct map_desc nuc900_iodesc[] __initdata = {
+        IODESC_ENT(IRQ),
+        IODESC_ENT(GCR),
+        IODESC_ENT(UART),
+        IODESC_ENT(TIMER),
+        IODESC_ENT(EBI),
+};
+/* Initial clock declarations. */
+static DEFINE_CLK(lcd, 0);
+static DEFINE_CLK(audio, 1);
+static DEFINE_CLK(fmi, 4);
+static DEFINE_SUBCLK(ms, 0);
+static DEFINE_SUBCLK(sd, 1);
+static DEFINE_CLK(dmac, 5);
+static DEFINE_CLK(atapi, 6);
+static DEFINE_CLK(emc, 7);
+static DEFINE_SUBCLK(rmii, 2);
+static DEFINE_CLK(usbd, 8);
+static DEFINE_CLK(usbh, 9);
+static DEFINE_CLK(g2d, 10);;
+static DEFINE_CLK(pwm, 18);
+static DEFINE_CLK(ps2, 24);
+static DEFINE_CLK(kpi, 25);
+static DEFINE_CLK(wdt, 26);
+static DEFINE_CLK(gdma, 27);
+static DEFINE_CLK(adc, 28);
+static DEFINE_CLK(usi, 29);
+static DEFINE_CLK(ext, 0);
+static struct clk_lookup nuc900_clkregs[] = {
+        DEF_CLKLOOK(&clk_lcd, "nuc900-lcd", NULL),
+        DEF_CLKLOOK(&clk_audio, "nuc900-audio", NULL),
+        DEF_CLKLOOK(&clk_fmi, "nuc900-fmi", NULL),
+        DEF_CLKLOOK(&clk_ms, "nuc900-fmi", "MS"),
+        DEF_CLKLOOK(&clk_sd, "nuc900-fmi", "SD"),
+        DEF_CLKLOOK(&clk_dmac, "nuc900-dmac", NULL),
+        DEF_CLKLOOK(&clk_atapi, "nuc900-atapi", NULL),
+        DEF_CLKLOOK(&clk_emc, "nuc900-emc", NULL),
+        DEF_CLKLOOK(&clk_rmii, "nuc900-emc", "RMII"),
+        DEF_CLKLOOK(&clk_usbd, "nuc900-usbd", NULL),
+        DEF_CLKLOOK(&clk_usbh, "nuc900-usbh", NULL),
+        DEF_CLKLOOK(&clk_g2d, "nuc900-g2d", NULL),
+        DEF_CLKLOOK(&clk_pwm, "nuc900-pwm", NULL),
+        DEF_CLKLOOK(&clk_ps2, "nuc900-ps2", NULL),
+        DEF_CLKLOOK(&clk_kpi, "nuc900-kpi", NULL),
+        DEF_CLKLOOK(&clk_wdt, "nuc900-wdt", NULL),
+        DEF_CLKLOOK(&clk_gdma, "nuc900-gdma", NULL),
+        DEF_CLKLOOK(&clk_adc, "nuc900-adc", NULL),
+        DEF_CLKLOOK(&clk_usi, "nuc900-spi", NULL),
+        DEF_CLKLOOK(&clk_ext, NULL, "ext"),
+};
+/* Initial serial platform data */
+struct plat_serial8250_port nuc900_uart_data[] = {
+        NUC900_8250PORT(UART0),
+};
+struct platform_device nuc900_serial_device = {
+        .name                   = "serial8250",
+        .id                     = PLAT8250_DEV_PLATFORM,
+        .dev                    = {
+                .platform_data  = nuc900_uart_data,
+        },
+};
+/*Set NUC900 series cpu frequence*/
+static int __init nuc900_set_clkval(unsigned int cpufreq)
+{
+        unsigned int pllclk, ahbclk, apbclk, val;
+        pllclk = 0;
+        ahbclk = 0;
+        apbclk = 0;
+        switch (cpufreq) {
+        case 66:
+                pllclk = PLL_66MHZ;
+                ahbclk = AHB_CPUCLK_1_1;
+                apbclk = APB_AHB_1_2;
+                break;
+        case 100:
+                pllclk = PLL_100MHZ;
+                ahbclk = AHB_CPUCLK_1_1;
+                apbclk = APB_AHB_1_2;
+                break;
+        case 120:
+                pllclk = PLL_120MHZ;
+                ahbclk = AHB_CPUCLK_1_2;
+                apbclk = APB_AHB_1_2;
+                break;
+        case 166:
+                pllclk = PLL_166MHZ;
+                ahbclk = AHB_CPUCLK_1_2;
+                apbclk = APB_AHB_1_2;
+                break;
+        case 200:
+                pllclk = PLL_200MHZ;
+                ahbclk = AHB_CPUCLK_1_2;
+                apbclk = APB_AHB_1_2;
+                break;
+        }
+        __raw_writel(pllclk, REG_PLLCON0);
+        val = __raw_readl(REG_CLKDIV);
+        val &= ~(0x03 << 24 | 0x03 << 26);
+        val |= (ahbclk << 24 | apbclk << 26);
+        __raw_writel(val, REG_CLKDIV);
+        return  0;
+}
+static int __init nuc900_set_cpufreq(char *str)
+{
+        unsigned long cpufreq, val;
+        if (!*str)
+                return 0;
+        strict_strtoul(str, 0, &cpufreq);
+        nuc900_clock_source(NULL, "ext");
+        nuc900_set_clkval(cpufreq);
+        mdelay(1);
+        val = __raw_readl(REG_CKSKEW);
+        val &= ~0xff;
+        val |= DEFAULTSKEW;
+        __raw_writel(val, REG_CKSKEW);
+        nuc900_clock_source(NULL, "pll0");
+        return 1;
+}
+__setup("cpufreq=", nuc900_set_cpufreq);
+/*Init NUC900 evb io*/
+void __init nuc900_map_io(struct map_desc *mach_desc, int mach_size)
+{
+        unsigned long idcode = 0x0;
+        iotable_init(mach_desc, mach_size);
+        iotable_init(nuc900_iodesc, ARRAY_SIZE(nuc900_iodesc));
+        idcode = __raw_readl(NUC900PDID);
+        if (idcode == NUC910_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC910\n", idcode);
+        else if (idcode == NUC920_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC920\n", idcode);
+        else if (idcode == NUC950_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC950\n", idcode);
+        else if (idcode == NUC960_CPUID)
+                printk(KERN_INFO "CPU type 0x%08lx is NUC960\n", idcode);
+}
+/*Init NUC900 clock*/
+void __init nuc900_init_clocks(void)
+{
+        clks_register(nuc900_clkregs, ARRAY_SIZE(nuc900_clkregs));
+}
diff --git a/arch/arm/mach-w90x900/cpu.h b/arch/arm/mach-w90x900/cpu.h
index 57b5dbabeb41..4d58ba164e25 100644
--- a/arch/arm/mach-w90x900/cpu.h
+++ b/arch/arm/mach-w90x900/cpu.h
@@ -6,7 +6,7 @@
 * Copyright (c) 2008 Nuvoton technology corporation
 * All rights reserved.
 *
- * Header file for W90X900 CPU support
+ * Header file for NUC900 CPU support
 *
 * Wan ZongShun <mcuos.com@gmail.com>
 *
@@ -24,29 +24,7 @@
       .type    = MT_DEVICE,                           \
 }
-/*Cpu identifier register*/
+#define NUC900_8250PORT(name)                                   \
-#define W90X900PDID     W90X900_VA_GCR
-#define W90P910_CPUID   0x02900910
-#define W90P920_CPUID   0x02900920
-#define W90P950_CPUID   0x02900950
-#define W90N960_CPUID   0x02900960
-struct w90x900_uartcfg;
-struct map_desc;
-struct sys_timer;
-/* core initialisation functions */
-extern void w90x900_init_irq(void);
-extern void w90p910_init_io(struct map_desc *mach_desc, int size);
-extern void w90p910_init_uarts(struct w90x900_uartcfg *cfg, int no);
-extern void w90p910_init_clocks(void);
-extern void w90p910_map_io(struct map_desc *mach_desc, int size);
-extern struct platform_device w90p910_serial_device;
-extern struct sys_timer w90x900_timer;
-#define W90X900_8250PORT(name)                                  \
 {                                                               \
        .membase        = name##_BA,                            \
        .mapbase        = name##_PA,                            \
@@ -56,3 +34,26 @@ extern struct sys_timer w90x900_timer;
        .iotype         = UPIO_MEM,                             \
        .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,    \
 }
+/*Cpu identifier register*/
+#define NUC900PDID      W90X900_VA_GCR
+#define NUC910_CPUID    0x02900910
+#define NUC920_CPUID    0x02900920
+#define NUC950_CPUID    0x02900950
+#define NUC960_CPUID    0x02900960
+/* extern file from cpu.c */
+extern void nuc900_clock_source(struct device *dev, unsigned char *src);
+extern void nuc900_init_clocks(void);
+extern void nuc900_map_io(struct map_desc *mach_desc, int mach_size);
+extern void nuc900_board_init(struct platform_device **device, int size);
+/* for either public between 910 and 920, or between 920 and 950 */
+extern struct platform_device nuc900_serial_device;
+extern struct platform_device nuc900_device_fmi;
+extern struct platform_device nuc900_device_kpi;
+extern struct platform_device nuc900_device_rtc;
+extern struct platform_device nuc900_device_ts;
diff --git a/arch/arm/mach-w90x900/dev.c b/arch/arm/mach-w90x900/dev.c
new file mode 100644
index 000000000000..2a6f98de48d2
--- /dev/null
+++ b/arch/arm/mach-w90x900/dev.c
@@ -0,0 +1,389 @@
+/*
+ * linux/arch/arm/mach-w90x900/dev.c
+ *
+ * Copyright (C) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/flash.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/irq.h>
+#include <asm/mach-types.h>
+#include <mach/regs-serial.h>
+#include <mach/map.h>
+#include "cpu.h"
+/*NUC900 evb norflash driver data */
+#define NUC900_FLASH_BASE       0xA0000000
+#define NUC900_FLASH_SIZE       0x400000
+#define SPIOFFSET               0x200
+#define SPIOREG_SIZE            0x100
+static struct mtd_partition nuc900_flash_partitions[] = {
+        {
+                .name   =       "NOR Partition 1 for kernel (960K)",
+                .size   =       0xF0000,
+                .offset =       0x10000,
+        },
+        {
+                .name   =       "NOR Partition 2 for image (1M)",
+                .size   =       0x100000,
+                .offset =       0x100000,
+        },
+        {
+                .name   =       "NOR Partition 3 for user (2M)",
+                .size   =       0x200000,
+                .offset =       0x00200000,
+        }
+};
+static struct physmap_flash_data nuc900_flash_data = {
+        .width          =       2,
+        .parts          =       nuc900_flash_partitions,
+        .nr_parts       =       ARRAY_SIZE(nuc900_flash_partitions),
+};
+static struct resource nuc900_flash_resources[] = {
+        {
+                .start  =       NUC900_FLASH_BASE,
+                .end    =       NUC900_FLASH_BASE + NUC900_FLASH_SIZE - 1,
+                .flags  =       IORESOURCE_MEM,
+        }
+};
+static struct platform_device nuc900_flash_device = {
+        .name           =       "physmap-flash",
+        .id             =       0,
+        .dev            = {
+                                .platform_data = &nuc900_flash_data,
+                        },
+        .resource       =       nuc900_flash_resources,
+        .num_resources  =       ARRAY_SIZE(nuc900_flash_resources),
+};
+/* USB EHCI Host Controller */
+static struct resource nuc900_usb_ehci_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBEHCIHOST,
+                .end   = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 nuc900_device_usb_ehci_dmamask = 0xffffffffUL;
+static struct platform_device nuc900_device_usb_ehci = {
+        .name             = "nuc900-ehci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(nuc900_usb_ehci_resource),
+        .resource         = nuc900_usb_ehci_resource,
+        .dev              = {
+                .dma_mask = &nuc900_device_usb_ehci_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+/* USB OHCI Host Controller */
+static struct resource nuc900_usb_ohci_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBOHCIHOST,
+                .end   = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBH,
+                .end   = IRQ_USBH,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 nuc900_device_usb_ohci_dmamask = 0xffffffffUL;
+static struct platform_device nuc900_device_usb_ohci = {
+        .name             = "nuc900-ohci",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(nuc900_usb_ohci_resource),
+        .resource         = nuc900_usb_ohci_resource,
+        .dev              = {
+                .dma_mask = &nuc900_device_usb_ohci_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+/* USB Device (Gadget)*/
+static struct resource nuc900_usbgadget_resource[] = {
+        [0] = {
+                .start = W90X900_PA_USBDEV,
+                .end   = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_USBD,
+                .end   = IRQ_USBD,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device nuc900_device_usbgadget = {
+        .name           = "nuc900-usbgadget",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_usbgadget_resource),
+        .resource       = nuc900_usbgadget_resource,
+};
+/* MAC device */
+static struct resource nuc900_emc_resource[] = {
+        [0] = {
+                .start = W90X900_PA_EMC,
+                .end   = W90X900_PA_EMC + W90X900_SZ_EMC - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_EMCTX,
+                .end   = IRQ_EMCTX,
+                .flags = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start = IRQ_EMCRX,
+                .end   = IRQ_EMCRX,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static u64 nuc900_device_emc_dmamask = 0xffffffffUL;
+static struct platform_device nuc900_device_emc = {
+        .name           = "nuc900-emc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_emc_resource),
+        .resource       = nuc900_emc_resource,
+        .dev              = {
+                .dma_mask = &nuc900_device_emc_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+/* SPI device */
+static struct resource nuc900_spi_resource[] = {
+        [0] = {
+                .start = W90X900_PA_I2C + SPIOFFSET,
+                .end   = W90X900_PA_I2C + SPIOFFSET + SPIOREG_SIZE - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_SSP,
+                .end   = IRQ_SSP,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device nuc900_device_spi = {
+        .name           = "nuc900-spi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_spi_resource),
+        .resource       = nuc900_spi_resource,
+};
+/* spi device, spi flash info */
+static struct mtd_partition nuc900_spi_flash_partitions[] = {
+        {
+                .name = "bootloader(spi)",
+                .size = 0x0100000,
+                .offset = 0,
+        },
+};
+static struct flash_platform_data nuc900_spi_flash_data = {
+        .name = "m25p80",
+        .parts =  nuc900_spi_flash_partitions,
+        .nr_parts = ARRAY_SIZE(nuc900_spi_flash_partitions),
+        .type = "w25x16",
+};
+static struct spi_board_info nuc900_spi_board_info[] __initdata = {
+        {
+                .modalias = "m25p80",
+                .max_speed_hz = 20000000,
+                .bus_num = 0,
+                .chip_select = 1,
+                .platform_data = &nuc900_spi_flash_data,
+                .mode = SPI_MODE_0,
+        },
+};
+/* WDT Device */
+static struct resource nuc900_wdt_resource[] = {
+        [0] = {
+                .start = W90X900_PA_TIMER,
+                .end   = W90X900_PA_TIMER + W90X900_SZ_TIMER - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_WDT,
+                .end   = IRQ_WDT,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+static struct platform_device nuc900_device_wdt = {
+        .name           = "nuc900-wdt",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_wdt_resource),
+        .resource       = nuc900_wdt_resource,
+};
+/*
+ * public device definition between 910 and 920, or 910
+ * and 950 or 950 and 960...,their dev platform register
+ * should be in specific file such as nuc950, nuc960 c
+ * files rather than the public dev.c file here. so the
+ * corresponding platform_device definition should not be
+ * static.
+*/
+/* RTC controller*/
+static struct resource nuc900_rtc_resource[] = {
+        [0] = {
+                .start = W90X900_PA_RTC,
+                .end   = W90X900_PA_RTC + 0xff,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_RTC,
+                .end   = IRQ_RTC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device nuc900_device_rtc = {
+        .name           = "nuc900-rtc",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_rtc_resource),
+        .resource       = nuc900_rtc_resource,
+};
+/*TouchScreen controller*/
+static struct resource nuc900_ts_resource[] = {
+        [0] = {
+                .start = W90X900_PA_ADC,
+                .end   = W90X900_PA_ADC + W90X900_SZ_ADC-1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_ADC,
+                .end   = IRQ_ADC,
+                .flags = IORESOURCE_IRQ,
+        },
+};
+struct platform_device nuc900_device_ts = {
+        .name           = "nuc900-ts",
+        .id             = -1,
+        .resource       = nuc900_ts_resource,
+        .num_resources  = ARRAY_SIZE(nuc900_ts_resource),
+};
+/* FMI Device */
+static struct resource nuc900_fmi_resource[] = {
+        [0] = {
+                .start = W90X900_PA_FMI,
+                .end   = W90X900_PA_FMI + W90X900_SZ_FMI - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_FMI,
+                .end   = IRQ_FMI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+struct platform_device nuc900_device_fmi = {
+        .name           = "nuc900-fmi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_fmi_resource),
+        .resource       = nuc900_fmi_resource,
+};
+/* KPI controller*/
+static struct resource nuc900_kpi_resource[] = {
+        [0] = {
+                .start = W90X900_PA_KPI,
+                .end   = W90X900_PA_KPI + W90X900_SZ_KPI - 1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_KPI,
+                .end   = IRQ_KPI,
+                .flags = IORESOURCE_IRQ,
+        }
+};
+struct platform_device nuc900_device_kpi = {
+        .name           = "nuc900-kpi",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(nuc900_kpi_resource),
+        .resource       = nuc900_kpi_resource,
+};
+/*Here should be your evb resourse,such as LCD*/
+static struct platform_device *nuc900_public_dev[] __initdata = {
+        &nuc900_serial_device,
+        &nuc900_flash_device,
+        &nuc900_device_usb_ehci,
+        &nuc900_device_usb_ohci,
+        &nuc900_device_usbgadget,
+        &nuc900_device_emc,
+        &nuc900_device_spi,
+        &nuc900_device_wdt,
+};
+/* Provide adding specific CPU platform devices API */
+void __init nuc900_board_init(struct platform_device **device, int size)
+{
+        platform_add_devices(device, size);
+        platform_add_devices(nuc900_public_dev, ARRAY_SIZE(nuc900_public_dev));
+        spi_register_board_info(nuc900_spi_board_info,
+                                        ARRAY_SIZE(nuc900_spi_board_info));
+}
diff --git a/arch/arm/mach-w90x900/gpio.c b/arch/arm/mach-w90x900/gpio.c
index c72e0dfa1825..ba05aec7ea4b 100644
--- a/arch/arm/mach-w90x900/gpio.c
+++ b/arch/arm/mach-w90x900/gpio.c
@@ -1,7 +1,7 @@
 /*
- * linux/arch/arm/mach-w90p910/gpio.c
+ * linux/arch/arm/mach-w90x900/gpio.c
 *
- * Generic w90p910 GPIO handling
+ * Generic nuc900 GPIO handling
 *
 *  Wan ZongShun <mcuos.com@gmail.com>
 *
@@ -30,31 +30,31 @@
 #define GPIO_IN                 (0x0C)
 #define GROUPINERV              (0x10)
 #define GPIO_GPIO(Nb)           (0x00000001 << (Nb))
-#define to_w90p910_gpio_chip(c) container_of(c, struct w90p910_gpio_chip, chip)
+#define to_nuc900_gpio_chip(c) container_of(c, struct nuc900_gpio_chip, chip)
-#define W90P910_GPIO_CHIP(name, base_gpio, nr_gpio)                     \
+#define NUC900_GPIO_CHIP(name, base_gpio, nr_gpio)                      \
        {                                                               \
                .chip = {                                               \
                        .label            = name,                       \
-                        .direction_input  = w90p910_dir_input,          \
+                        .direction_input  = nuc900_dir_input,           \
-                        .direction_output = w90p910_dir_output,         \
+                        .direction_output = nuc900_dir_output,          \
-                        .get              = w90p910_gpio_get,           \
+                        .get              = nuc900_gpio_get,            \
-                        .set              = w90p910_gpio_set,           \
+                        .set              = nuc900_gpio_set,            \
                        .base             = base_gpio,                  \
                        .ngpio            = nr_gpio,                    \
                }                                                       \
        }
-struct w90p910_gpio_chip {
+struct nuc900_gpio_chip {
        struct gpio_chip        chip;
        void __iomem            *regbase;       /* Base of group register*/
        spinlock_t              gpio_lock;
 };
-static int w90p910_gpio_get(struct gpio_chip *chip, unsigned offset)
+static int nuc900_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_IN;
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_IN;
        unsigned int regval;
        regval = __raw_readl(pio);
@@ -63,14 +63,14 @@ static int w90p910_gpio_get(struct gpio_chip *chip, unsigned offset)
        return (regval != 0);
 }
-static void w90p910_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+static void nuc900_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_OUT;
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_OUT;
        unsigned int regval;
        unsigned long flags;
-        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
        regval = __raw_readl(pio);
@@ -81,36 +81,36 @@ static void w90p910_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
        __raw_writel(regval, pio);
-        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
 }
-static int w90p910_dir_input(struct gpio_chip *chip, unsigned offset)
+static int nuc900_dir_input(struct gpio_chip *chip, unsigned offset)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR;
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
        unsigned int regval;
        unsigned long flags;
-        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
        regval = __raw_readl(pio);
        regval &= ~GPIO_GPIO(offset);
        __raw_writel(regval, pio);
-        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
        return 0;
 }
-static int w90p910_dir_output(struct gpio_chip *chip, unsigned offset, int val)
+static int nuc900_dir_output(struct gpio_chip *chip, unsigned offset, int val)
 {
-        struct w90p910_gpio_chip *w90p910_gpio = to_w90p910_gpio_chip(chip);
+        struct nuc900_gpio_chip *nuc900_gpio = to_nuc900_gpio_chip(chip);
-        void __iomem *outreg = w90p910_gpio->regbase + GPIO_OUT;
+        void __iomem *outreg = nuc900_gpio->regbase + GPIO_OUT;
-        void __iomem *pio = w90p910_gpio->regbase + GPIO_DIR;
+        void __iomem *pio = nuc900_gpio->regbase + GPIO_DIR;
        unsigned int regval;
        unsigned long flags;
-        spin_lock_irqsave(&w90p910_gpio->gpio_lock, flags);
+        spin_lock_irqsave(&nuc900_gpio->gpio_lock, flags);
        regval = __raw_readl(pio);
        regval |= GPIO_GPIO(offset);
@@ -125,28 +125,28 @@ static int w90p910_dir_output(struct gpio_chip *chip, unsigned offset, int val)
        __raw_writel(regval, outreg);
-        spin_unlock_irqrestore(&w90p910_gpio->gpio_lock, flags);
+        spin_unlock_irqrestore(&nuc900_gpio->gpio_lock, flags);
        return 0;
 }
-static struct w90p910_gpio_chip w90p910_gpio[] = {
+static struct nuc900_gpio_chip nuc900_gpio[] = {
-        W90P910_GPIO_CHIP("GROUPC", 0, 16),
+        NUC900_GPIO_CHIP("GROUPC", 0, 16),
-        W90P910_GPIO_CHIP("GROUPD", 16, 10),
+        NUC900_GPIO_CHIP("GROUPD", 16, 10),
-        W90P910_GPIO_CHIP("GROUPE", 26, 14),
+        NUC900_GPIO_CHIP("GROUPE", 26, 14),
-        W90P910_GPIO_CHIP("GROUPF", 40, 10),
+        NUC900_GPIO_CHIP("GROUPF", 40, 10),
-        W90P910_GPIO_CHIP("GROUPG", 50, 17),
+        NUC900_GPIO_CHIP("GROUPG", 50, 17),
-        W90P910_GPIO_CHIP("GROUPH", 67, 8),
+        NUC900_GPIO_CHIP("GROUPH", 67, 8),
-        W90P910_GPIO_CHIP("GROUPI", 75, 17),
+        NUC900_GPIO_CHIP("GROUPI", 75, 17),
 };
-void __init w90p910_init_gpio(int nr_group)
+void __init nuc900_init_gpio(int nr_group)
 {
        unsigned        i;
-        struct w90p910_gpio_chip *gpio_chip;
+        struct nuc900_gpio_chip *gpio_chip;
        for (i = 0; i < nr_group; i++) {
-                gpio_chip = &w90p910_gpio[i];
+                gpio_chip = &nuc900_gpio[i];
                spin_lock_init(&gpio_chip->gpio_lock);
                gpio_chip->regbase = GPIO_BASE + i * GROUPINERV;
                gpiochip_add(&gpio_chip->chip);
diff --git a/arch/arm/mach-w90x900/include/mach/regs-clock.h b/arch/arm/mach-w90x900/include/mach/regs-clock.h
index f10b6a8dc069..516d6b477b61 100644
--- a/arch/arm/mach-w90x900/include/mach/regs-clock.h
+++ b/arch/arm/mach-w90x900/include/mach/regs-clock.h
@@ -28,4 +28,26 @@
 #define REG_CLKEN1      (CLK_BA + 0x24)
 #define REG_CLKDIV1     (CLK_BA + 0x28)
+/* Define PLL freq setting */
+#define PLL_DISABLE             0x12B63
+#define PLL_66MHZ               0x2B63
+#define PLL_100MHZ              0x4F64
+#define PLL_120MHZ              0x4F63
+#define PLL_166MHZ              0x4124
+#define PLL_200MHZ              0x4F24
+/* Define AHB:CPUFREQ ratio */
+#define AHB_CPUCLK_1_1          0x00
+#define AHB_CPUCLK_1_2          0x01
+#define AHB_CPUCLK_1_4          0x02
+#define AHB_CPUCLK_1_8          0x03
+/* Define APB:AHB ratio */
+#define APB_AHB_1_2             0x01
+#define APB_AHB_1_4             0x02
+#define APB_AHB_1_8             0x03
+/* Define clock skew */
+#define DEFAULTSKEW             0x48
 #endif /*  __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-w90x900/include/mach/regs-ebi.h b/arch/arm/mach-w90x900/include/mach/regs-ebi.h
new file mode 100644
index 000000000000..b68455e7f88b
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/regs-ebi.h
@@ -0,0 +1,33 @@
+/*
+ * arch/arm/mach-w90x900/include/mach/regs-ebi.h
+ *
+ * Copyright (c) 2009 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+#ifndef __ASM_ARCH_REGS_EBI_H
+#define __ASM_ARCH_REGS_EBI_H
+/* EBI Control Registers */
+#define EBI_BA          W90X900_VA_EBI
+#define REG_EBICON      (EBI_BA + 0x00)
+#define REG_ROMCON      (EBI_BA + 0x04)
+#define REG_SDCONF0     (EBI_BA + 0x08)
+#define REG_SDCONF1     (EBI_BA + 0x0C)
+#define REG_SDTIME0     (EBI_BA + 0x10)
+#define REG_SDTIME1     (EBI_BA + 0x14)
+#define REG_EXT0CON     (EBI_BA + 0x18)
+#define REG_EXT1CON     (EBI_BA + 0x1C)
+#define REG_EXT2CON     (EBI_BA + 0x20)
+#define REG_EXT3CON     (EBI_BA + 0x24)
+#define REG_EXT4CON     (EBI_BA + 0x28)
+#define REG_CKSKEW      (EBI_BA + 0x2C)
+#endif /*  __ASM_ARCH_REGS_EBI_H */
diff --git a/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h b/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h
new file mode 100644
index 000000000000..556778e8ddaa
--- /dev/null
+++ b/arch/arm/mach-w90x900/include/mach/w90p910_keypad.h
@@ -0,0 +1,15 @@
+#ifndef __ASM_ARCH_W90P910_KEYPAD_H
+#define __ASM_ARCH_W90P910_KEYPAD_H
+#include <linux/input/matrix_keypad.h>
+extern void mfp_set_groupi(struct device *dev);
+struct w90p910_keypad_platform_data {
+        const struct matrix_keymap_data *keymap_data;
+        unsigned int    prescale;
+        unsigned int    debounce;
+};
+#endif /* __ASM_ARCH_W90P910_KEYPAD_H */
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
index 0b4fc194729c..0ce9d8e867eb 100644
--- a/arch/arm/mach-w90x900/irq.c
+++ b/arch/arm/mach-w90x900/irq.c
@@ -10,8 +10,7 @@
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
+ * the Free Software Foundation;version 2 of the License.
- * (at your option) any later version.
 *
 */
@@ -29,9 +28,114 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
-static void w90x900_irq_mask(unsigned int irq)
+struct group_irq {
+        unsigned long           gpen;
+        unsigned int            enabled;
+        void                    (*enable)(struct group_irq *, int enable);
+};
+static DEFINE_SPINLOCK(groupirq_lock);
+#define DEFINE_GROUP(_name, _ctrlbit, _num)                             \
+struct group_irq group_##_name = {                                      \
+                .enable         = nuc900_group_enable,                  \
+                .gpen           = ((1 << _num) - 1) << _ctrlbit,        \
+        }
+static void nuc900_group_enable(struct group_irq *gpirq, int enable);
+static DEFINE_GROUP(nirq0, 0, 4);
+static DEFINE_GROUP(nirq1, 4, 4);
+static DEFINE_GROUP(usbh, 8, 2);
+static DEFINE_GROUP(ottimer, 16, 3);
+static DEFINE_GROUP(gdma, 20, 2);
+static DEFINE_GROUP(sc, 24, 2);
+static DEFINE_GROUP(i2c, 26, 2);
+static DEFINE_GROUP(ps2, 28, 2);
+static int group_irq_enable(struct group_irq *group_irq)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&groupirq_lock, flags);
+        if (group_irq->enabled++ == 0)
+                (group_irq->enable)(group_irq, 1);
+        spin_unlock_irqrestore(&groupirq_lock, flags);
+        return 0;
+}
+static void group_irq_disable(struct group_irq *group_irq)
 {
+        unsigned long flags;
+        WARN_ON(group_irq->enabled == 0);
+        spin_lock_irqsave(&groupirq_lock, flags);
+        if (--group_irq->enabled == 0)
+                (group_irq->enable)(group_irq, 0);
+        spin_unlock_irqrestore(&groupirq_lock, flags);
+}
+static void nuc900_group_enable(struct group_irq *gpirq, int enable)
+{
+        unsigned int groupen = gpirq->gpen;
+        unsigned long regval;
+        regval = __raw_readl(REG_AIC_GEN);
+        if (enable)
+                regval |= groupen;
+        else
+                regval &= ~groupen;
+        __raw_writel(regval, REG_AIC_GEN);
+}
+static void nuc900_irq_mask(unsigned int irq)
+{
+        struct group_irq *group_irq;
+        group_irq = NULL;
        __raw_writel(1 << irq, REG_AIC_MDCR);
+        switch (irq) {
+        case IRQ_GROUP0:
+                group_irq = &group_nirq0;
+                break;
+        case IRQ_GROUP1:
+                group_irq = &group_nirq1;
+                break;
+        case IRQ_USBH:
+                group_irq = &group_usbh;
+                break;
+        case IRQ_T_INT_GROUP:
+                group_irq = &group_ottimer;
+                break;
+        case IRQ_GDMAGROUP:
+                group_irq = &group_gdma;
+                break;
+        case IRQ_SCGROUP:
+                group_irq = &group_sc;
+                break;
+        case IRQ_I2CGROUP:
+                group_irq = &group_i2c;
+                break;
+        case IRQ_P2SGROUP:
+                group_irq = &group_ps2;
+                break;
+        }
+        if (group_irq)
+                group_irq_disable(group_irq);
 }
 /*
@@ -39,37 +143,71 @@ static void w90x900_irq_mask(unsigned int irq)
 * to REG_AIC_EOSCR for ACK
 */
-static void w90x900_irq_ack(unsigned int irq)
+static void nuc900_irq_ack(unsigned int irq)
 {
        __raw_writel(0x01, REG_AIC_EOSCR);
 }
-static void w90x900_irq_unmask(unsigned int irq)
+static void nuc900_irq_unmask(unsigned int irq)
 {
-        unsigned long mask;
+        struct group_irq *group_irq;
+        group_irq = NULL;
-        if (irq == IRQ_T_INT_GROUP) {
-                mask = __raw_readl(REG_AIC_GEN);
-                __raw_writel(TIME_GROUP_IRQ | mask, REG_AIC_GEN);
-                __raw_writel(1 << IRQ_T_INT_GROUP, REG_AIC_MECR);
-        }
        __raw_writel(1 << irq, REG_AIC_MECR);
+        switch (irq) {
+        case IRQ_GROUP0:
+                group_irq = &group_nirq0;
+                break;
+        case IRQ_GROUP1:
+                group_irq = &group_nirq1;
+                break;
+        case IRQ_USBH:
+                group_irq = &group_usbh;
+                break;
+        case IRQ_T_INT_GROUP:
+                group_irq = &group_ottimer;
+                break;
+        case IRQ_GDMAGROUP:
+                group_irq = &group_gdma;
+                break;
+        case IRQ_SCGROUP:
+                group_irq = &group_sc;
+                break;
+        case IRQ_I2CGROUP:
+                group_irq = &group_i2c;
+                break;
+        case IRQ_P2SGROUP:
+                group_irq = &group_ps2;
+                break;
+        }
+        if (group_irq)
+                group_irq_enable(group_irq);
 }
-static struct irq_chip w90x900_irq_chip = {
+static struct irq_chip nuc900_irq_chip = {
-        .ack       = w90x900_irq_ack,
+        .ack       = nuc900_irq_ack,
-        .mask      = w90x900_irq_mask,
+        .mask      = nuc900_irq_mask,
-        .unmask    = w90x900_irq_unmask,
+        .unmask    = nuc900_irq_unmask,
 };
-void __init w90x900_init_irq(void)
+void __init nuc900_init_irq(void)
 {
        int irqno;
        __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
        for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) {
-                set_irq_chip(irqno, &w90x900_irq_chip);
+                set_irq_chip(irqno, &nuc900_irq_chip);
                set_irq_handler(irqno, handle_level_irq);
                set_irq_flags(irqno, IRQF_VALID);
        }
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c
new file mode 100644
index 000000000000..ec05bda946f3
--- /dev/null
+++ b/arch/arm/mach-w90x900/mach-nuc910evb.c
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc910evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+#include "nuc910.h"
+static void __init nuc910evb_map_io(void)
+{
+        nuc910_map_io();
+        nuc910_init_clocks();
+}
+static void __init nuc910evb_init(void)
+{
+        nuc910_board_init();
+}
+MACHINE_START(W90P910EVB, "W90P910EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = W90X900_PA_UART,
+        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc910evb_map_io,
+        .init_irq       = nuc900_init_irq,
+        .init_machine   = nuc910evb_init,
+        .timer          = &nuc900_timer,
+MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
new file mode 100644
index 000000000000..cef903bcccd1
--- /dev/null
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc950evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+#include "nuc950.h"
+static void __init nuc950evb_map_io(void)
+{
+        nuc950_map_io();
+        nuc950_init_clocks();
+}
+static void __init nuc950evb_init(void)
+{
+        nuc950_board_init();
+}
+MACHINE_START(W90P950EVB, "W90P950EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = W90X900_PA_UART,
+        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc950evb_map_io,
+        .init_irq       = nuc900_init_irq,
+        .init_machine   = nuc950evb_init,
+        .timer          = &nuc900_timer,
+MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c
new file mode 100644
index 000000000000..e3a46f19f2bc
--- /dev/null
+++ b/arch/arm/mach-w90x900/mach-nuc960evb.c
@@ -0,0 +1,44 @@
+/*
+ * linux/arch/arm/mach-w90x900/mach-nuc960evb.c
+ *
+ * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
+ *
+ * Copyright (C) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <mach/map.h>
+#include "nuc960.h"
+static void __init nuc960evb_map_io(void)
+{
+        nuc960_map_io();
+        nuc960_init_clocks();
+}
+static void __init nuc960evb_init(void)
+{
+        nuc960_board_init();
+}
+MACHINE_START(W90N960EVB, "W90N960EVB")
+        /* Maintainer: Wan ZongShun */
+        .phys_io        = W90X900_PA_UART,
+        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
+        .boot_params    = 0,
+        .map_io         = nuc960evb_map_io,
+        .init_irq       = nuc900_init_irq,
+        .init_machine   = nuc960evb_init,
+        .timer          = &nuc900_timer,
+MACHINE_END
diff --git a/arch/arm/mach-w90x900/mach-w90p910evb.c b/arch/arm/mach-w90x900/mach-w90p910evb.c
deleted file mode 100644
index 7a62bd348e80..000000000000
--- a/arch/arm/mach-w90x900/mach-w90p910evb.c
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * linux/arch/arm/mach-w90x900/mach-w90p910evb.c
- *
- * Based on mach-s3c2410/mach-smdk2410.c by Jonas Dietsche
- *
- * Copyright (C) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation;version 2 of the License.
- *
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/mach-types.h>
-#include <mach/regs-serial.h>
-#include <mach/map.h>
-#include "cpu.h"
-/*w90p910 evb norflash driver data */
-#define W90P910_FLASH_BASE      0xA0000000
-#define W90P910_FLASH_SIZE      0x400000
-static struct mtd_partition w90p910_flash_partitions[] = {
-        {
-                .name   =       "NOR Partition 1 for kernel (960K)",
-                .size   =       0xF0000,
-                .offset =       0x10000,
-        },
-        {
-                .name   =       "NOR Partition 2 for image (1M)",
-                .size   =       0x100000,
-                .offset =       0x100000,
-        },
-        {
-                .name   =       "NOR Partition 3 for user (2M)",
-                .size   =       0x200000,
-                .offset =       0x00200000,
-        }
-};
-static struct physmap_flash_data w90p910_flash_data = {
-        .width          =       2,
-        .parts          =       w90p910_flash_partitions,
-        .nr_parts       =       ARRAY_SIZE(w90p910_flash_partitions),
-};
-static struct resource w90p910_flash_resources[] = {
-        {
-                .start  =       W90P910_FLASH_BASE,
-                .end    =       W90P910_FLASH_BASE + W90P910_FLASH_SIZE - 1,
-                .flags  =       IORESOURCE_MEM,
-        }
-};
-static struct platform_device w90p910_flash_device = {
-        .name           =       "physmap-flash",
-        .id             =       0,
-        .dev            = {
-                                .platform_data = &w90p910_flash_data,
-                        },
-        .resource       =       w90p910_flash_resources,
-        .num_resources  =       ARRAY_SIZE(w90p910_flash_resources),
-};
-/* USB EHCI Host Controller */
-static struct resource w90x900_usb_ehci_resource[] = {
-        [0] = {
-                .start = W90X900_PA_USBEHCIHOST,
-                .end   = W90X900_PA_USBEHCIHOST + W90X900_SZ_USBEHCIHOST - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_USBH,
-                .end   = IRQ_USBH,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-static u64 w90x900_device_usb_ehci_dmamask = 0xffffffffUL;
-struct platform_device w90x900_device_usb_ehci = {
-        .name             = "w90x900-ehci",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(w90x900_usb_ehci_resource),
-        .resource         = w90x900_usb_ehci_resource,
-        .dev              = {
-                .dma_mask = &w90x900_device_usb_ehci_dmamask,
-                .coherent_dma_mask = 0xffffffffUL
-        }
-};
-EXPORT_SYMBOL(w90x900_device_usb_ehci);
-/* USB OHCI Host Controller */
-static struct resource w90x900_usb_ohci_resource[] = {
-        [0] = {
-                .start = W90X900_PA_USBOHCIHOST,
-                .end   = W90X900_PA_USBOHCIHOST + W90X900_SZ_USBOHCIHOST - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_USBH,
-                .end   = IRQ_USBH,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-static u64 w90x900_device_usb_ohci_dmamask = 0xffffffffUL;
-struct platform_device w90x900_device_usb_ohci = {
-        .name             = "w90x900-ohci",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(w90x900_usb_ohci_resource),
-        .resource         = w90x900_usb_ohci_resource,
-        .dev              = {
-                .dma_mask = &w90x900_device_usb_ohci_dmamask,
-                .coherent_dma_mask = 0xffffffffUL
-        }
-};
-EXPORT_SYMBOL(w90x900_device_usb_ohci);
-/*TouchScreen controller*/
-static struct resource w90x900_ts_resource[] = {
-        [0] = {
-                .start = W90X900_PA_ADC,
-                .end   = W90X900_PA_ADC + W90X900_SZ_ADC-1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_ADC,
-                .end   = IRQ_ADC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device w90x900_device_ts = {
-        .name           = "w90x900-ts",
-        .id             = -1,
-        .resource       = w90x900_ts_resource,
-        .num_resources  = ARRAY_SIZE(w90x900_ts_resource),
-};
-EXPORT_SYMBOL(w90x900_device_ts);
-/* RTC controller*/
-static struct resource w90x900_rtc_resource[] = {
-        [0] = {
-                .start = W90X900_PA_RTC,
-                .end   = W90X900_PA_RTC + 0xff,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_RTC,
-                .end   = IRQ_RTC,
-                .flags = IORESOURCE_IRQ,
-        },
-};
-struct platform_device w90x900_device_rtc = {
-        .name           = "w90x900-rtc",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(w90x900_rtc_resource),
-        .resource       = w90x900_rtc_resource,
-};
-EXPORT_SYMBOL(w90x900_device_rtc);
-/* KPI controller*/
-static struct resource w90x900_kpi_resource[] = {
-        [0] = {
-                .start = W90X900_PA_KPI,
-                .end   = W90X900_PA_KPI + W90X900_SZ_KPI - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_KPI,
-                .end   = IRQ_KPI,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-struct platform_device w90x900_device_kpi = {
-        .name           = "w90x900-kpi",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(w90x900_kpi_resource),
-        .resource       = w90x900_kpi_resource,
-};
-EXPORT_SYMBOL(w90x900_device_kpi);
-/* USB Device (Gadget)*/
-static struct resource w90x900_usbgadget_resource[] = {
-        [0] = {
-                .start = W90X900_PA_USBDEV,
-                .end   = W90X900_PA_USBDEV + W90X900_SZ_USBDEV - 1,
-                .flags = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start = IRQ_USBD,
-                .end   = IRQ_USBD,
-                .flags = IORESOURCE_IRQ,
-        }
-};
-struct platform_device w90x900_device_usbgadget = {
-        .name           = "w90x900-usbgadget",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(w90x900_usbgadget_resource),
-        .resource       = w90x900_usbgadget_resource,
-};
-EXPORT_SYMBOL(w90x900_device_usbgadget);
-static struct map_desc w90p910_iodesc[] __initdata = {
-};
-/*Here should be your evb resourse,such as LCD*/
-static struct platform_device *w90p910evb_dev[] __initdata = {
-        &w90p910_serial_device,
-        &w90p910_flash_device,
-        &w90x900_device_usb_ehci,
-        &w90x900_device_usb_ohci,
-        &w90x900_device_ts,
-        &w90x900_device_rtc,
-        &w90x900_device_kpi,
-        &w90x900_device_usbgadget,
-};
-static void __init w90p910evb_map_io(void)
-{
-        w90p910_map_io(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc));
-        w90p910_init_clocks();
-}
-static void __init w90p910evb_init(void)
-{
-        platform_add_devices(w90p910evb_dev, ARRAY_SIZE(w90p910evb_dev));
-}
-MACHINE_START(W90P910EVB, "W90P910EVB")
-        /* Maintainer: Wan ZongShun */
-        .phys_io        = W90X900_PA_UART,
-        .io_pg_offst    = (((u32)W90X900_VA_UART) >> 18) & 0xfffc,
-        .boot_params    = 0,
-        .map_io         = w90p910evb_map_io,
-        .init_irq       = w90x900_init_irq,
-        .init_machine   = w90p910evb_init,
-        .timer          = &w90x900_timer,
-MACHINE_END
diff --git a/arch/arm/mach-w90x900/mfp-w90p910.c b/arch/arm/mach-w90x900/mfp-w90p910.c
deleted file mode 100644
index a3520fefb5e7..000000000000
--- a/arch/arm/mach-w90x900/mfp-w90p910.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * linux/arch/arm/mach-w90x900/mfp-w90p910.c
- *
- * Copyright (c) 2008 Nuvoton technology corporation
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- */
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/list.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/string.h>
-#include <linux/clk.h>
-#include <linux/mutex.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#define REG_MFSEL       (W90X900_VA_GCR + 0xC)
-#define GPSELF          (0x01 << 1)
-#define GPSELC          (0x03 << 2)
-#define ENKPI           (0x02 << 2)
-#define ENNAND          (0x01 << 2)
-#define GPSELEI0        (0x01 << 26)
-#define GPSELEI1        (0x01 << 27)
-static DECLARE_MUTEX(mfp_sem);
-void mfp_set_groupf(struct device *dev)
-{
-        unsigned long mfpen;
-        const char *dev_id;
-        BUG_ON(!dev);
-        down(&mfp_sem);
-        dev_id = dev_name(dev);
-        mfpen = __raw_readl(REG_MFSEL);
-        if (strcmp(dev_id, "w90p910-emc") == 0)
-                mfpen |= GPSELF;/*enable mac*/
-        else
-                mfpen &= ~GPSELF;/*GPIOF[9:0]*/
-        __raw_writel(mfpen, REG_MFSEL);
-        up(&mfp_sem);
-}
-EXPORT_SYMBOL(mfp_set_groupf);
-void mfp_set_groupc(struct device *dev)
-{
-        unsigned long mfpen;
-        const char *dev_id;
-        BUG_ON(!dev);
-        down(&mfp_sem);
-        dev_id = dev_name(dev);
-        mfpen = __raw_readl(REG_MFSEL);
-        if (strcmp(dev_id, "w90p910-lcd") == 0)
-                mfpen |= GPSELC;/*enable lcd*/
-        else if (strcmp(dev_id, "w90p910-kpi") == 0) {
-                        mfpen &= (~GPSELC);/*enable kpi*/
-                        mfpen |= ENKPI;
-                } else if (strcmp(dev_id, "w90p910-nand") == 0) {
-                                mfpen &= (~GPSELC);/*enable nand*/
-                                mfpen |= ENNAND;
-                        } else
-                                mfpen &= (~GPSELC);/*GPIOC[14:0]*/
-        __raw_writel(mfpen, REG_MFSEL);
-        up(&mfp_sem);
-}
-EXPORT_SYMBOL(mfp_set_groupc);
-void mfp_set_groupi(struct device *dev, int gpio)
-{
-        unsigned long mfpen;
-        const char *dev_id;
-        BUG_ON(!dev);
-        down(&mfp_sem);
-        dev_id = dev_name(dev);
-        mfpen = __raw_readl(REG_MFSEL);
-        if (strcmp(dev_id, "w90p910-wdog") == 0)
-                mfpen |= GPSELEI1;/*enable wdog*/
-                else if (strcmp(dev_id, "w90p910-atapi") == 0)
-                        mfpen |= GPSELEI0;/*enable atapi*/
-        __raw_writel(mfpen, REG_MFSEL);
-        up(&mfp_sem);
-}
-EXPORT_SYMBOL(mfp_set_groupi);
diff --git a/arch/arm/mach-w90x900/mfp.c b/arch/arm/mach-w90x900/mfp.c
new file mode 100644
index 000000000000..a47dc9a708ee
--- /dev/null
+++ b/arch/arm/mach-w90x900/mfp.c
@@ -0,0 +1,158 @@
+/*
+ * linux/arch/arm/mach-w90x900/mfp.c
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/string.h>
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#define REG_MFSEL       (W90X900_VA_GCR + 0xC)
+#define GPSELF          (0x01 << 1)
+#define GPSELC          (0x03 << 2)
+#define ENKPI           (0x02 << 2)
+#define ENNAND          (0x01 << 2)
+#define GPSELEI0        (0x01 << 26)
+#define GPSELEI1        (0x01 << 27)
+#define GPIOG0TO1       (0x03 << 14)
+#define GPIOG2TO3       (0x03 << 16)
+#define ENSPI           (0x0a << 14)
+#define ENI2C0          (0x01 << 14)
+#define ENI2C1          (0x01 << 16)
+static DEFINE_MUTEX(mfp_mutex);
+void mfp_set_groupf(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+        BUG_ON(!dev);
+        mutex_lock(&mfp_mutex);
+        dev_id = dev_name(dev);
+        mfpen = __raw_readl(REG_MFSEL);
+        if (strcmp(dev_id, "nuc900-emc") == 0)
+                mfpen |= GPSELF;/*enable mac*/
+        else
+                mfpen &= ~GPSELF;/*GPIOF[9:0]*/
+        __raw_writel(mfpen, REG_MFSEL);
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupf);
+void mfp_set_groupc(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+        BUG_ON(!dev);
+        mutex_lock(&mfp_mutex);
+        dev_id = dev_name(dev);
+        mfpen = __raw_readl(REG_MFSEL);
+        if (strcmp(dev_id, "nuc900-lcd") == 0)
+                mfpen |= GPSELC;/*enable lcd*/
+        else if (strcmp(dev_id, "nuc900-kpi") == 0) {
+                mfpen &= (~GPSELC);/*enable kpi*/
+                mfpen |= ENKPI;
+        } else if (strcmp(dev_id, "nuc900-nand") == 0) {
+                mfpen &= (~GPSELC);/*enable nand*/
+                mfpen |= ENNAND;
+        } else
+                mfpen &= (~GPSELC);/*GPIOC[14:0]*/
+        __raw_writel(mfpen, REG_MFSEL);
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupc);
+void mfp_set_groupi(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+        BUG_ON(!dev);
+        mutex_lock(&mfp_mutex);
+        dev_id = dev_name(dev);
+        mfpen = __raw_readl(REG_MFSEL);
+        mfpen &= ~GPSELEI1;/*default gpio16*/
+        if (strcmp(dev_id, "nuc900-wdog") == 0)
+                mfpen |= GPSELEI1;/*enable wdog*/
+        else if (strcmp(dev_id, "nuc900-atapi") == 0)
+                mfpen |= GPSELEI0;/*enable atapi*/
+        else if (strcmp(dev_id, "nuc900-keypad") == 0)
+                mfpen &= ~GPSELEI0;/*enable keypad*/
+        __raw_writel(mfpen, REG_MFSEL);
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupi);
+void mfp_set_groupg(struct device *dev)
+{
+        unsigned long mfpen;
+        const char *dev_id;
+        BUG_ON(!dev);
+        mutex_lock(&mfp_mutex);
+        dev_id = dev_name(dev);
+        mfpen = __raw_readl(REG_MFSEL);
+        if (strcmp(dev_id, "nuc900-spi") == 0) {
+                mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);
+                mfpen |= ENSPI;/*enable spi*/
+        } else if (strcmp(dev_id, "nuc900-i2c0") == 0) {
+                mfpen &= ~(GPIOG0TO1);
+                mfpen |= ENI2C0;/*enable i2c0*/
+        } else if (strcmp(dev_id, "nuc900-i2c1") == 0) {
+                mfpen &= ~(GPIOG2TO3);
+                mfpen |= ENI2C1;/*enable i2c1*/
+        } else {
+                mfpen &= ~(GPIOG0TO1 | GPIOG2TO3);/*GPIOG[3:0]*/
+        }
+        __raw_writel(mfpen, REG_MFSEL);
+        mutex_unlock(&mfp_mutex);
+}
+EXPORT_SYMBOL(mfp_set_groupg);
diff --git a/arch/arm/mach-w90x900/nuc910.c b/arch/arm/mach-w90x900/nuc910.c
new file mode 100644
index 000000000000..656f03b3b629
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc910.c
@@ -0,0 +1,60 @@
+/*
+ * linux/arch/arm/mach-w90x900/nuc910.c
+ *
+ * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
+ *
+ * Copyright (c) 2009 Nuvoton corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC910 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include "cpu.h"
+#include "clock.h"
+/* define specific CPU platform device */
+static struct platform_device *nuc910_dev[] __initdata = {
+        &nuc900_device_ts,
+        &nuc900_device_rtc,
+};
+/* define specific CPU platform io map */
+static struct map_desc nuc910evb_iodesc[] __initdata = {
+        IODESC_ENT(USBEHCIHOST),
+        IODESC_ENT(USBOHCIHOST),
+        IODESC_ENT(KPI),
+        IODESC_ENT(USBDEV),
+        IODESC_ENT(ADC),
+};
+/*Init NUC910 evb io*/
+void __init nuc910_map_io(void)
+{
+        nuc900_map_io(nuc910evb_iodesc, ARRAY_SIZE(nuc910evb_iodesc));
+}
+/*Init NUC910 clock*/
+void __init nuc910_init_clocks(void)
+{
+        nuc900_init_clocks();
+}
+/*Init NUC910 board info*/
+void __init nuc910_board_init(void)
+{
+        nuc900_board_init(nuc910_dev, ARRAY_SIZE(nuc910_dev));
+}
diff --git a/arch/arm/mach-w90x900/nuc910.h b/arch/arm/mach-w90x900/nuc910.h
new file mode 100644
index 000000000000..83e9ba5fc26c
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc910.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-w90x900/nuc910.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC900 CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+struct map_desc;
+struct sys_timer;
+/* core initialisation functions */
+extern void nuc900_init_irq(void);
+extern struct sys_timer nuc900_timer;
+/* extern file from nuc910.c */
+extern void nuc910_board_init(void);
+extern void nuc910_init_clocks(void);
+extern void nuc910_map_io(void);
diff --git a/arch/arm/mach-w90x900/nuc950.c b/arch/arm/mach-w90x900/nuc950.c
new file mode 100644
index 000000000000..149508116d18
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc950.c
@@ -0,0 +1,54 @@
+/*
+ * linux/arch/arm/mach-w90x900/nuc950.c
+ *
+ * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC950 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include "cpu.h"
+/* define specific CPU platform device */
+static struct platform_device *nuc950_dev[] __initdata = {
+        &nuc900_device_kpi,
+        &nuc900_device_fmi,
+};
+/* define specific CPU platform io map */
+static struct map_desc nuc950evb_iodesc[] __initdata = {
+};
+/*Init NUC950 evb io*/
+void __init nuc950_map_io(void)
+{
+        nuc900_map_io(nuc950evb_iodesc, ARRAY_SIZE(nuc950evb_iodesc));
+}
+/*Init NUC950 clock*/
+void __init nuc950_init_clocks(void)
+{
+        nuc900_init_clocks();
+}
+/*Init NUC950 board info*/
+void __init nuc950_board_init(void)
+{
+        nuc900_board_init(nuc950_dev, ARRAY_SIZE(nuc950_dev));
+}
diff --git a/arch/arm/mach-w90x900/nuc950.h b/arch/arm/mach-w90x900/nuc950.h
new file mode 100644
index 000000000000..98a1148bc5ae
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc950.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-w90x900/nuc950.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC900 CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+struct map_desc;
+struct sys_timer;
+/* core initialisation functions */
+extern void nuc900_init_irq(void);
+extern struct sys_timer nuc900_timer;
+/* extern file from nuc950.c */
+extern void nuc950_board_init(void);
+extern void nuc950_init_clocks(void);
+extern void nuc950_map_io(void);
diff --git a/arch/arm/mach-w90x900/nuc960.c b/arch/arm/mach-w90x900/nuc960.c
new file mode 100644
index 000000000000..8851a3a27ce2
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc960.c
@@ -0,0 +1,54 @@
+/*
+ * linux/arch/arm/mach-w90x900/nuc960.c
+ *
+ * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
+ *
+ * Copyright (c) 2008 Nuvoton technology corporation.
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * NUC960 cpu support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation;version 2 of the License.
+ *
+ */
+#include <linux/platform_device.h>
+#include <asm/mach/map.h>
+#include <mach/hardware.h>
+#include "cpu.h"
+/* define specific CPU platform device */
+static struct platform_device *nuc960_dev[] __initdata = {
+        &nuc900_device_kpi,
+        &nuc900_device_fmi,
+};
+/* define specific CPU platform io map */
+static struct map_desc nuc960evb_iodesc[] __initdata = {
+};
+/*Init NUC960 evb io*/
+void __init nuc960_map_io(void)
+{
+        nuc900_map_io(nuc960evb_iodesc, ARRAY_SIZE(nuc960evb_iodesc));
+}
+/*Init NUC960 clock*/
+void __init nuc960_init_clocks(void)
+{
+        nuc900_init_clocks();
+}
+/*Init NUC960 board info*/
+void __init nuc960_board_init(void)
+{
+        nuc900_board_init(nuc960_dev, ARRAY_SIZE(nuc960_dev));
+}
diff --git a/arch/arm/mach-w90x900/nuc960.h b/arch/arm/mach-w90x900/nuc960.h
new file mode 100644
index 000000000000..f0c07cbe3a82
--- /dev/null
+++ b/arch/arm/mach-w90x900/nuc960.h
@@ -0,0 +1,28 @@
+/*
+ * arch/arm/mach-w90x900/nuc960.h
+ *
+ * Copyright (c) 2008 Nuvoton corporation
+ *
+ * Header file for NUC900 CPU support
+ *
+ * Wan ZongShun <mcuos.com@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+struct map_desc;
+struct sys_timer;
+/* core initialisation functions */
+extern void nuc900_init_irq(void);
+extern struct sys_timer nuc900_timer;
+/* extern file from nuc960.c */
+extern void nuc960_board_init(void);
+extern void nuc960_init_clocks(void);
+extern void nuc960_map_io(void);
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index bcc838f6b393..4128af870b41 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -3,7 +3,7 @@
 *
 * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
 *
- * Copyright (c) 2008 Nuvoton technology corporation
+ * Copyright (c) 2009 Nuvoton technology corporation
 * All rights reserved.
 *
 * Wan ZongShun <mcuos.com@gmail.com>
@@ -23,6 +23,8 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/leds.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
 #include <asm/mach-types.h>
 #include <asm/mach/irq.h>
@@ -31,49 +33,150 @@
 #include <mach/map.h>
 #include <mach/regs-timer.h>
-static unsigned long w90x900_gettimeoffset(void)
+#define RESETINT        0x1f
+#define PERIOD          (0x01 << 27)
+#define ONESHOT         (0x00 << 27)
+#define COUNTEN         (0x01 << 30)
+#define INTEN           (0x01 << 29)
+#define TICKS_PER_SEC   100
+#define PRESCALE        0x63 /* Divider = prescale + 1 */
+unsigned int timer0_load;
+static void nuc900_clockevent_setmode(enum clock_event_mode mode,
+                struct clock_event_device *clk)
 {
+        unsigned int val;
+        val = __raw_readl(REG_TCSR0);
+        val &= ~(0x03 << 27);
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                __raw_writel(timer0_load, REG_TICR0);
+                val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+        __raw_writel(val, REG_TCSR0);
+}
+static int nuc900_clockevent_setnextevent(unsigned long evt,
+                struct clock_event_device *clk)
+{
+        unsigned int val;
+        __raw_writel(evt, REG_TICR0);
+        val = __raw_readl(REG_TCSR0);
+        val |= (COUNTEN | INTEN | PRESCALE);
+        __raw_writel(val, REG_TCSR0);
        return 0;
 }
+static struct clock_event_device nuc900_clockevent_device = {
+        .name           = "nuc900-timer0",
+        .shift          = 32,
+        .features       = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode       = nuc900_clockevent_setmode,
+        .set_next_event = nuc900_clockevent_setnextevent,
+        .rating         = 300,
+};
 /*IRQ handler for the timer*/
-static irqreturn_t
+static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
-w90x900_timer_interrupt(int irq, void *dev_id)
 {
-        timer_tick();
+        struct clock_event_device *evt = &nuc900_clockevent_device;
        __raw_writel(0x01, REG_TISR); /* clear TIF0 */
+        evt->event_handler(evt);
        return IRQ_HANDLED;
 }
-static struct irqaction w90x900_timer_irq = {
+static struct irqaction nuc900_timer0_irq = {
-        .name           = "w90x900 Timer Tick",
+        .name           = "nuc900-timer0",
        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = w90x900_timer_interrupt,
+        .handler        = nuc900_timer0_interrupt,
 };
-/*Set up timer reg.*/
+static void __init nuc900_clockevents_init(unsigned int rate)
+{
+        nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
+                                        nuc900_clockevent_device.shift);
+        nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
+                                        &nuc900_clockevent_device);
+        nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
+                                        &nuc900_clockevent_device);
+        nuc900_clockevent_device.cpumask = cpumask_of(0);
-static void w90x900_timer_setup(void)
+        clockevents_register_device(&nuc900_clockevent_device);
+}
+static cycle_t nuc900_get_cycles(struct clocksource *cs)
 {
-        __raw_writel(0, REG_TCSR0);
+        return ~__raw_readl(REG_TDR1);
-        __raw_writel(0, REG_TCSR1);
-        __raw_writel(0, REG_TCSR2);
-        __raw_writel(0, REG_TCSR3);
-        __raw_writel(0, REG_TCSR4);
-        __raw_writel(0x1F, REG_TISR);
-        __raw_writel(15000000/(100 * 100), REG_TICR0);
-        __raw_writel(0x68000063, REG_TCSR0);
 }
-static void __init w90x900_timer_init(void)
+static struct clocksource clocksource_nuc900 = {
+        .name   = "nuc900-timer1",
+        .rating = 200,
+        .read   = nuc900_get_cycles,
+        .mask   = CLOCKSOURCE_MASK(32),
+        .shift  = 20,
+        .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+static void __init nuc900_clocksource_init(unsigned int rate)
 {
-        w90x900_timer_setup();
+        unsigned int val;
-        setup_irq(IRQ_TIMER0, &w90x900_timer_irq);
+        __raw_writel(0xffffffff, REG_TICR1);
+        val = __raw_readl(REG_TCSR1);
+        val |= (COUNTEN | PERIOD);
+        __raw_writel(val, REG_TCSR1);
+        clocksource_nuc900.mult =
+                clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
+        clocksource_register(&clocksource_nuc900);
+}
+static void __init nuc900_timer_init(void)
+{
+        struct clk *ck_ext = clk_get(NULL, "ext");
+        unsigned int    rate;
+        BUG_ON(IS_ERR(ck_ext));
+        rate = clk_get_rate(ck_ext);
+        clk_put(ck_ext);
+        rate = rate / (PRESCALE + 0x01);
+         /* set a known state */
+        __raw_writel(0x00, REG_TCSR0);
+        __raw_writel(0x00, REG_TCSR1);
+        __raw_writel(RESETINT, REG_TISR);
+        timer0_load = (rate / TICKS_PER_SEC);
+        setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
+        nuc900_clocksource_init(rate);
+        nuc900_clockevents_init(rate);
 }
-struct sys_timer w90x900_timer = {
+struct sys_timer nuc900_timer = {
-        .init           = w90x900_timer_init,
+        .init           = nuc900_timer_init,
-        .offset         = w90x900_gettimeoffset,
-        .resume         = w90x900_timer_setup
 };
diff --git a/arch/arm/mach-w90x900/w90p910.c b/arch/arm/mach-w90x900/w90p910.c
deleted file mode 100644
index 1c97e4930b7a..000000000000
--- a/arch/arm/mach-w90x900/w90p910.c
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * linux/arch/arm/mach-w90x900/w90p910.c
- *
- * Based on linux/arch/arm/plat-s3c24xx/s3c244x.c by Ben Dooks
- *
- * Copyright (c) 2008 Nuvoton technology corporation.
- *
- * Wan ZongShun <mcuos.com@gmail.com>
- *
- * W90P910 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;version 2 of the License.
- *
- */
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/interrupt.h>
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/io.h>
-#include <linux/serial_8250.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <asm/mach/irq.h>
-#include <asm/irq.h>
-#include <mach/hardware.h>
-#include <mach/regs-serial.h>
-#include "cpu.h"
-#include "clock.h"
-/* Initial IO mappings */
-static struct map_desc w90p910_iodesc[] __initdata = {
-        IODESC_ENT(IRQ),
-        IODESC_ENT(GCR),
-        IODESC_ENT(UART),
-        IODESC_ENT(TIMER),
-        IODESC_ENT(EBI),
-        IODESC_ENT(USBEHCIHOST),
-        IODESC_ENT(USBOHCIHOST),
-        IODESC_ENT(ADC),
-        IODESC_ENT(RTC),
-        IODESC_ENT(KPI),
-        IODESC_ENT(USBDEV),
-        /*IODESC_ENT(LCD),*/
-};
-/* Initial clock declarations. */
-static DEFINE_CLK(lcd, 0);
-static DEFINE_CLK(audio, 1);
-static DEFINE_CLK(fmi, 4);
-static DEFINE_CLK(dmac, 5);
-static DEFINE_CLK(atapi, 6);
-static DEFINE_CLK(emc, 7);
-static DEFINE_CLK(usbd, 8);
-static DEFINE_CLK(usbh, 9);
-static DEFINE_CLK(g2d, 10);;
-static DEFINE_CLK(pwm, 18);
-static DEFINE_CLK(ps2, 24);
-static DEFINE_CLK(kpi, 25);
-static DEFINE_CLK(wdt, 26);
-static DEFINE_CLK(gdma, 27);
-static DEFINE_CLK(adc, 28);
-static DEFINE_CLK(usi, 29);
-static struct clk_lookup w90p910_clkregs[] = {
-        DEF_CLKLOOK(&clk_lcd, "w90p910-lcd", NULL),
-        DEF_CLKLOOK(&clk_audio, "w90p910-audio", NULL),
-        DEF_CLKLOOK(&clk_fmi, "w90p910-fmi", NULL),
-        DEF_CLKLOOK(&clk_dmac, "w90p910-dmac", NULL),
-        DEF_CLKLOOK(&clk_atapi, "w90p910-atapi", NULL),
-        DEF_CLKLOOK(&clk_emc, "w90p910-emc", NULL),
-        DEF_CLKLOOK(&clk_usbd, "w90p910-usbd", NULL),
-        DEF_CLKLOOK(&clk_usbh, "w90p910-usbh", NULL),
-        DEF_CLKLOOK(&clk_g2d, "w90p910-g2d", NULL),
-        DEF_CLKLOOK(&clk_pwm, "w90p910-pwm", NULL),
-        DEF_CLKLOOK(&clk_ps2, "w90p910-ps2", NULL),
-        DEF_CLKLOOK(&clk_kpi, "w90p910-kpi", NULL),
-        DEF_CLKLOOK(&clk_wdt, "w90p910-wdt", NULL),
-        DEF_CLKLOOK(&clk_gdma, "w90p910-gdma", NULL),
-        DEF_CLKLOOK(&clk_adc, "w90p910-adc", NULL),
-        DEF_CLKLOOK(&clk_usi, "w90p910-usi", NULL),
-};
-/* Initial serial platform data */
-struct plat_serial8250_port w90p910_uart_data[] = {
-        W90X900_8250PORT(UART0),
-};
-struct platform_device w90p910_serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = w90p910_uart_data,
-        },
-};
-/*Init W90P910 evb io*/
-void __init w90p910_map_io(struct map_desc *mach_desc, int mach_size)
-{
-        unsigned long idcode = 0x0;
-        iotable_init(w90p910_iodesc, ARRAY_SIZE(w90p910_iodesc));
-        idcode = __raw_readl(W90X900PDID);
-        if (idcode != W90P910_CPUID)
-                printk(KERN_ERR "CPU type 0x%08lx is not W90P910\n", idcode);
-}
-/*Init W90P910 clock*/
-void __init w90p910_init_clocks(void)
-{
-        clks_register(w90p910_clkregs, ARRAY_SIZE(w90p910_clkregs));
-}
-static int __init w90p910_init_cpu(void)
-{
-        return 0;
-}
-static int __init w90x900_arch_init(void)
-{
-        return w90p910_init_cpu();
-}
-arch_initcall(w90x900_arch_init);
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 83c025e72ceb..5fe595aeba69 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -758,7 +758,7 @@ config CACHE_FEROCEON_L2_WRITETHROUGH
 config CACHE_L2X0
        bool "Enable the L2x0 outer cache controller"
        depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
-                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX
+                   REALVIEW_EB_A9MP || ARCH_MX35 || ARCH_MX31 || MACH_REALVIEW_PBX || ARCH_NOMADIK
        default y
        select OUTER_CACHE
        help
diff --git a/arch/arm/mm/alignment.c b/arch/arm/mm/alignment.c
index 03cd27d917b9..b270d6228fe2 100644
--- a/arch/arm/mm/alignment.c
+++ b/arch/arm/mm/alignment.c
@@ -159,7 +159,9 @@ union offset_union {
 #define __get8_unaligned_check(ins,val,addr,err)        \
        __asm__(                                        \
-        "1:     "ins"   %1, [%2], #1\n"                 \
+ ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+ THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+ THUMB( "       add     %2, %2, #1\n"   )               \
        "2:\n"                                          \
        "       .section .fixup,\"ax\"\n"               \
        "       .align  2\n"                            \
@@ -215,7 +217,9 @@ union offset_union {
        do {                                                    \
                unsigned int err = 0, v = val, a = addr;        \
                __asm__( FIRST_BYTE_16                          \
-                "1:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                "       mov     %1, %1, "NEXT_BYTE"\n"          \
                "2:     "ins"   %1, [%2]\n"                     \
                "3:\n"                                          \
@@ -245,11 +249,17 @@ union offset_union {
        do {                                                    \
                unsigned int err = 0, v = val, a = addr;        \
                __asm__( FIRST_BYTE_32                          \
-                "1:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "1:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "1:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                "       mov     %1, %1, "NEXT_BYTE"\n"          \
-                "2:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "2:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "2:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                "       mov     %1, %1, "NEXT_BYTE"\n"          \
-                "3:     "ins"   %1, [%2], #1\n"                 \
+         ARM(   "3:     "ins"   %1, [%2], #1\n" )               \
+         THUMB( "3:     "ins"   %1, [%2]\n"     )               \
+         THUMB( "       add     %2, %2, #1\n"   )               \
                "       mov     %1, %1, "NEXT_BYTE"\n"          \
                "4:     "ins"   %1, [%2]\n"                     \
                "5:\n"                                          \
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index be93ff02a98d..bda0ec31a4e2 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -21,7 +21,7 @@
 *
 *      Flush the whole D-cache.
 *
- *      Corrupted registers: r0-r5, r7, r9-r11
+ *      Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode)
 *
 *      - mm    - mm_struct describing address space
 */
@@ -51,8 +51,12 @@ loop1:
 loop2:
        mov     r9, r4                          @ create working copy of max way size
 loop3:
-        orr     r11, r10, r9, lsl r5            @ factor way and cache number into r11
+ ARM(   orr     r11, r10, r9, lsl r5    )       @ factor way and cache number into r11
-        orr     r11, r11, r7, lsl r2            @ factor index number into r11
+ THUMB( lsl     r6, r9, r5              )
+ THUMB( orr     r11, r10, r6            )       @ factor way and cache number into r11
+ ARM(   orr     r11, r11, r7, lsl r2    )       @ factor index number into r11
+ THUMB( lsl     r6, r7, r2              )
+ THUMB( orr     r11, r11, r6            )       @ factor index number into r11
        mcr     p15, 0, r11, c7, c14, 2         @ clean & invalidate by set/way
        subs    r9, r9, #1                      @ decrement the way
        bge     loop3
@@ -82,11 +86,13 @@ ENDPROC(v7_flush_dcache_all)
 *
 */
 ENTRY(v7_flush_kern_cache_all)
-        stmfd   sp!, {r4-r5, r7, r9-r11, lr}
+ ARM(   stmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( stmfd   sp!, {r4-r7, r9-r11, lr}        )
        bl      v7_flush_dcache_all
        mov     r0, #0
        mcr     p15, 0, r0, c7, c5, 0           @ I+BTB cache invalidate
-        ldmfd   sp!, {r4-r5, r7, r9-r11, lr}
+ ARM(   ldmfd   sp!, {r4-r5, r7, r9-r11, lr}    )
+ THUMB( ldmfd   sp!, {r4-r7, r9-r11, lr}        )
        mov     pc, lr
 ENDPROC(v7_flush_kern_cache_all)
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 510c179b0ac8..b30925fcbcdc 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -36,7 +36,34 @@
 #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT)
 #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+static u64 get_coherent_dma_mask(struct device *dev)
+{
+        u64 mask = ISA_DMA_THRESHOLD;
+        if (dev) {
+                mask = dev->coherent_dma_mask;
+                /*
+                 * Sanity check the DMA mask - it must be non-zero, and
+                 * must be able to be satisfied by a DMA allocation.
+                 */
+                if (mask == 0) {
+                        dev_warn(dev, "coherent DMA mask is unset\n");
+                        return 0;
+                }
+                if ((~mask) & ISA_DMA_THRESHOLD) {
+                        dev_warn(dev, "coherent DMA mask %#llx is smaller "
+                                 "than system GFP_DMA mask %#llx\n",
+                                 mask, (unsigned long long)ISA_DMA_THRESHOLD);
+                        return 0;
+                }
+        }
+        return mask;
+}
+#ifdef CONFIG_MMU
 /*
 * These are the page tables (2MB each) covering uncached, DMA consistent allocations
 */
@@ -152,7 +179,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
        struct page *page;
        struct arm_vm_region *c;
        unsigned long order;
-        u64 mask = ISA_DMA_THRESHOLD, limit;
+        u64 mask = get_coherent_dma_mask(dev);
+        u64 limit;
        if (!consistent_pte[0]) {
                printk(KERN_ERR "%s: not initialised\n", __func__);
@@ -160,25 +188,8 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
                return NULL;
        }
-        if (dev) {
+        if (!mask)
-                mask = dev->coherent_dma_mask;
+                goto no_page;
-                /*
-                 * Sanity check the DMA mask - it must be non-zero, and
-                 * must be able to be satisfied by a DMA allocation.
-                 */
-                if (mask == 0) {
-                        dev_warn(dev, "coherent DMA mask is unset\n");
-                        goto no_page;
-                }
-                if ((~mask) & ISA_DMA_THRESHOLD) {
-                        dev_warn(dev, "coherent DMA mask %#llx is smaller "
-                                 "than system GFP_DMA mask %#llx\n",
-                                 mask, (unsigned long long)ISA_DMA_THRESHOLD);
-                        goto no_page;
-                }
-        }
        /*
         * Sanity check the allocation size.
@@ -267,6 +278,31 @@ __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
        *handle = ~0;
        return NULL;
 }
+#else   /* !CONFIG_MMU */
+static void *
+__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp,
+            pgprot_t prot)
+{
+        void *virt;
+        u64 mask = get_coherent_dma_mask(dev);
+        if (!mask)
+                goto error;
+        if (mask != 0xffffffff)
+                gfp |= GFP_DMA;
+        virt = kmalloc(size, gfp);
+        if (!virt)
+                goto error;
+        *handle =  virt_to_dma(dev, virt);
+        return virt;
+error:
+        *handle = ~0;
+        return NULL;
+}
+#endif  /* CONFIG_MMU */
 /*
 * Allocate DMA-coherent memory space and return both the kernel remapped
@@ -311,9 +347,10 @@ EXPORT_SYMBOL(dma_alloc_writecombine);
 static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
                    void *cpu_addr, dma_addr_t dma_addr, size_t size)
 {
+        int ret = -ENXIO;
+#ifdef CONFIG_MMU
        unsigned long flags, user_size, kern_size;
        struct arm_vm_region *c;
-        int ret = -ENXIO;
        user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
@@ -334,6 +371,7 @@ static int dma_mmap(struct device *dev, struct vm_area_struct *vma,
                                              vma->vm_page_prot);
                }
        }
+#endif  /* CONFIG_MMU */
        return ret;
 }
@@ -358,6 +396,7 @@ EXPORT_SYMBOL(dma_mmap_writecombine);
 * free a page as defined by the above mapping.
 * Must not be called with IRQs disabled.
 */
+#ifdef CONFIG_MMU
 void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
 {
        struct arm_vm_region *c;
@@ -444,6 +483,14 @@ void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr
               __func__, cpu_addr);
        dump_stack();
 }
+#else   /* !CONFIG_MMU */
+void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle)
+{
+        if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
+                return;
+        kfree(cpu_addr);
+}
+#endif  /* CONFIG_MMU */
 EXPORT_SYMBOL(dma_free_coherent);
 /*
@@ -451,10 +498,12 @@ EXPORT_SYMBOL(dma_free_coherent);
 */
 static int __init consistent_init(void)
 {
+        int ret = 0;
+#ifdef CONFIG_MMU
        pgd_t *pgd;
        pmd_t *pmd;
        pte_t *pte;
-        int ret = 0, i = 0;
+        int i = 0;
        u32 base = CONSISTENT_BASE;
        do {
@@ -477,6 +526,7 @@ static int __init consistent_init(void)
                consistent_pte[i++] = pte;
                base += (1 << PGDIR_SHIFT);
        } while (base < CONSISTENT_END);
+#endif  /* !CONFIG_MMU */
        return ret;
 }
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 6fdcbb709827..cc8829d7e116 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -16,6 +16,8 @@
 #include <linux/kprobes.h>
 #include <linux/uaccess.h>
 #include <linux/page-flags.h>
+#include <linux/sched.h>
+#include <linux/highmem.h>
 #include <asm/system.h>
 #include <asm/pgtable.h>
@@ -23,6 +25,7 @@
 #include "fault.h"
+#ifdef CONFIG_MMU
 #ifdef CONFIG_KPROBES
 static inline int notify_page_fault(struct pt_regs *regs, unsigned int fsr)
@@ -97,6 +100,10 @@ void show_pte(struct mm_struct *mm, unsigned long addr)
        printk("\n");
 }
+#else                                   /* CONFIG_MMU */
+void show_pte(struct mm_struct *mm, unsigned long addr)
+{ }
+#endif                                  /* CONFIG_MMU */
 /*
 * Oops.  The kernel tried to access some page that wasn't present.
@@ -171,6 +178,7 @@ void do_bad_area(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
                __do_kernel_fault(mm, addr, fsr, regs);
 }
+#ifdef CONFIG_MMU
 #define VM_FAULT_BADMAP         0x010000
 #define VM_FAULT_BADACCESS      0x020000
@@ -322,6 +330,13 @@ no_context:
        __do_kernel_fault(mm, addr, fsr, regs);
        return 0;
 }
+#else                                   /* CONFIG_MMU */
+static int
+do_page_fault(unsigned long addr, unsigned int fsr, struct pt_regs *regs)
+{
+        return 0;
+}
+#endif                                  /* CONFIG_MMU */
 /*
 * First Level Translation Fault Handler
@@ -340,6 +355,7 @@ no_context:
 * interrupt or a critical region, and should only copy the information
 * from the master page table, nothing more.
 */
+#ifdef CONFIG_MMU
 static int __kprobes
 do_translation_fault(unsigned long addr, unsigned int fsr,
                     struct pt_regs *regs)
@@ -378,6 +394,14 @@ bad_area:
        do_bad_area(addr, fsr, regs);
        return 0;
 }
+#else                                   /* CONFIG_MMU */
+static int
+do_translation_fault(unsigned long addr, unsigned int fsr,
+                     struct pt_regs *regs)
+{
+        return 0;
+}
+#endif                                  /* CONFIG_MMU */
 /*
 * Some section permission faults need to be handled gracefully.
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index c07222eb5ce0..575f3ad722e7 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -144,7 +144,14 @@ void __flush_dcache_page(struct address_space *mapping, struct page *page)
         * page.  This ensures that data in the physical page is mutually
         * coherent with the kernels mapping.
         */
-        __cpuc_flush_dcache_page(page_address(page));
+#ifdef CONFIG_HIGHMEM
+        /*
+         * kmap_atomic() doesn't set the page virtual address, and
+         * kunmap_atomic() takes care of cache flushing already.
+         */
+        if (page_address(page))
+#endif
+                __cpuc_flush_dcache_page(page_address(page));
        /*
         * If this is a page cache page, and we have an aliasing VIPT cache,
diff --git a/arch/arm/mm/highmem.c b/arch/arm/mm/highmem.c
index a34954d9df7d..73cae57fa707 100644
--- a/arch/arm/mm/highmem.c
+++ b/arch/arm/mm/highmem.c
@@ -40,11 +40,16 @@ void *kmap_atomic(struct page *page, enum km_type type)
 {
        unsigned int idx;
        unsigned long vaddr;
+        void *kmap;
        pagefault_disable();
        if (!PageHighMem(page))
                return page_address(page);
+        kmap = kmap_high_get(page);
+        if (kmap)
+                return kmap;
        idx = type + KM_TYPE_NR * smp_processor_id();
        vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx);
 #ifdef CONFIG_DEBUG_HIGHMEM
@@ -80,6 +85,9 @@ void kunmap_atomic(void *kvaddr, enum km_type type)
 #else
                (void) idx;  /* to kill a warning */
 #endif
+        } else if (vaddr >= PKMAP_ADDR(0) && vaddr < PKMAP_ADDR(LAST_PKMAP)) {
+                /* this address was obtained through kmap_high_get() */
+                kunmap_high(pte_page(pkmap_page_table[PKMAP_NR(vaddr)]));
        }
        pagefault_enable();
 }
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 3a7279c1ce5e..ea36186f32c3 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -15,6 +15,7 @@
 #include <linux/mman.h>
 #include <linux/nodemask.h>
 #include <linux/initrd.h>
+#include <linux/sort.h>
 #include <linux/highmem.h>
 #include <asm/mach-types.h>
@@ -349,12 +350,43 @@ static void __init bootmem_free_node(int node, struct meminfo *mi)
        free_area_init_node(node, zone_size, min, zhole_size);
 }
+#ifndef CONFIG_SPARSEMEM
+int pfn_valid(unsigned long pfn)
+{
+        struct meminfo *mi = &meminfo;
+        unsigned int left = 0, right = mi->nr_banks;
+        do {
+                unsigned int mid = (right + left) / 2;
+                struct membank *bank = &mi->bank[mid];
+                if (pfn < bank_pfn_start(bank))
+                        right = mid;
+                else if (pfn >= bank_pfn_end(bank))
+                        left = mid + 1;
+                else
+                        return 1;
+        } while (left < right);
+        return 0;
+}
+EXPORT_SYMBOL(pfn_valid);
+#endif
+static int __init meminfo_cmp(const void *_a, const void *_b)
+{
+        const struct membank *a = _a, *b = _b;
+        long cmp = bank_pfn_start(a) - bank_pfn_start(b);
+        return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
+}
 void __init bootmem_init(void)
 {
        struct meminfo *mi = &meminfo;
        unsigned long min, max_low, max_high;
        int node, initrd_node;
+        sort(&mi->bank, mi->nr_banks, sizeof(mi->bank[0]), meminfo_cmp, NULL);
        /*
         * Locate which node contains the ramdisk image, if any.
         */
diff --git a/arch/arm/mm/nommu.c b/arch/arm/mm/nommu.c
index ad7bacc693b2..900811cc9130 100644
--- a/arch/arm/mm/nommu.c
+++ b/arch/arm/mm/nommu.c
@@ -12,6 +12,7 @@
 #include <asm/cacheflush.h>
 #include <asm/sections.h>
 #include <asm/page.h>
+#include <asm/setup.h>
 #include <asm/mach/arch.h>
 #include "mm.h"
diff --git a/arch/arm/mm/proc-macros.S b/arch/arm/mm/proc-macros.S
index 54b1f721dec8..7d63beaf9745 100644
--- a/arch/arm/mm/proc-macros.S
+++ b/arch/arm/mm/proc-macros.S
@@ -77,19 +77,15 @@
 * Sanity check the PTE configuration for the code below - which makes
 * certain assumptions about how these bits are layed out.
 */
+#ifdef CONFIG_MMU
 #if L_PTE_SHARED != PTE_EXT_SHARED
 #error PTE shared bit mismatch
 #endif
-#if L_PTE_BUFFERABLE != PTE_BUFFERABLE
-#error PTE bufferable bit mismatch
-#endif
-#if L_PTE_CACHEABLE != PTE_CACHEABLE
-#error PTE cacheable bit mismatch
-#endif
 #if (L_PTE_EXEC+L_PTE_USER+L_PTE_WRITE+L_PTE_DIRTY+L_PTE_YOUNG+\
     L_PTE_FILE+L_PTE_PRESENT) > L_PTE_SHARED
 #error Invalid Linux PTE bit settings
 #endif
+#endif  /* CONFIG_MMU */
 /*
 * The ARMv6 and ARMv7 set_pte_ext translation function.
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 180a08d03a03..f3fa1c32fe92 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -127,7 +127,9 @@ ENDPROC(cpu_v7_switch_mm)
 */
 ENTRY(cpu_v7_set_pte_ext)
 #ifdef CONFIG_MMU
-        str     r1, [r0], #-2048                @ linux version
+ ARM(   str     r1, [r0], #-2048        )       @ linux version
+ THUMB( str     r1, [r0]                )       @ linux version
+ THUMB( sub     r0, r0, #2048           )
        bic     r3, r1, #0x000003f0
        bic     r3, r3, #PTE_TYPE_MASK
@@ -232,7 +234,6 @@ __v7_setup:
        mcr     p15, 0, r4, c2, c0, 1           @ load TTB1
        mov     r10, #0x1f                      @ domains 0, 1 = manager
        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
-#endif
        /*
         * Memory region attributes with SCTLR.TRE=1
         *
@@ -265,6 +266,7 @@ __v7_setup:
        ldr     r6, =0x40e040e0                 @ NMRR
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
+#endif
        adr     r5, v7_crval
        ldmia   r5, {r5, r6}
 #ifdef CONFIG_CPU_ENDIAN_BE8
@@ -273,6 +275,7 @@ __v7_setup:
        mrc     p15, 0, r0, c1, c0, 0           @ read control register
        bic     r0, r0, r5                      @ clear bits them
        orr     r0, r0, r6                      @ set them
+ THUMB( orr     r0, r0, #1 << 30        )       @ Thumb exceptions
        mov     pc, lr                          @ return to head.S:__ret
 ENDPROC(__v7_setup)
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 8986b7412235..ca5c7c226341 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -9,6 +9,7 @@ choice
 config ARCH_MX1
        bool "MX1-based"
        select CPU_ARM920T
+        select COMMON_CLKDEV
        help
          This enables support for systems based on the Freescale i.MX1 family
@@ -19,6 +20,13 @@ config ARCH_MX2
        help
          This enables support for systems based on the Freescale i.MX2 family
+config ARCH_MX25
+        bool "MX25-based"
+        select CPU_ARM926T
+        select COMMON_CLKDEV
+        help
+          This enables support for systems based on the Freescale i.MX25 family
 config ARCH_MX3
        bool "MX3-based"
        select CPU_V6
@@ -26,11 +34,20 @@ config ARCH_MX3
        help
          This enables support for systems based on the Freescale i.MX3 family
+config ARCH_MXC91231
+        bool "MXC91231-based"
+        select CPU_V6
+        select COMMON_CLKDEV
+        help
+          This enables support for systems based on the Freescale MXC91231 family
 endchoice
 source "arch/arm/mach-mx1/Kconfig"
 source "arch/arm/mach-mx2/Kconfig"
 source "arch/arm/mach-mx3/Kconfig"
+source "arch/arm/mach-mx25/Kconfig"
+source "arch/arm/mach-mxc91231/Kconfig"
 endmenu
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index 92e13566cd4f..9e8fbd57495c 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -39,6 +39,7 @@
 #include <linux/string.h>
 #include <mach/clock.h>
+#include <mach/hardware.h>
 static LIST_HEAD(clocks);
 static DEFINE_MUTEX(clocks_mutex);
@@ -47,76 +48,6 @@ static DEFINE_MUTEX(clocks_mutex);
 * Standard clock functions defined in include/linux/clk.h
 *-------------------------------------------------------------------------*/
-/*
- * All the code inside #ifndef CONFIG_COMMON_CLKDEV can be removed once all
- * MXC architectures have switched to using clkdev.
- */
-#ifndef CONFIG_COMMON_CLKDEV
-/*
- * Retrieve a clock by name.
- *
- * Note that we first try to use device id on the bus
- * and clock name. If this fails, we try to use "<name>.<id>". If this fails,
- * we try to use clock name only.
- * The reference count to the clock's module owner ref count is incremented.
- */
-struct clk *clk_get(struct device *dev, const char *id)
-{
-        struct clk *p, *clk = ERR_PTR(-ENOENT);
-        int idno;
-        const char *str;
-        if (id == NULL)
-                return clk;
-        if (dev == NULL || dev->bus != &platform_bus_type)
-                idno = -1;
-        else
-                idno = to_platform_device(dev)->id;
-        mutex_lock(&clocks_mutex);
-        list_for_each_entry(p, &clocks, node) {
-                if (p->id == idno &&
-                    strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-        str = strrchr(id, '.');
-        if (str) {
-                int cnt = str - id;
-                str++;
-                idno = simple_strtol(str, NULL, 10);
-                list_for_each_entry(p, &clocks, node) {
-                        if (p->id == idno &&
-                            strlen(p->name) == cnt &&
-                            strncmp(id, p->name, cnt) == 0 &&
-                            try_module_get(p->owner)) {
-                                clk = p;
-                                goto found;
-                        }
-                }
-        }
-        list_for_each_entry(p, &clocks, node) {
-                if (strcmp(id, p->name) == 0 && try_module_get(p->owner)) {
-                        clk = p;
-                        goto found;
-                }
-        }
-        printk(KERN_WARNING "clk: Unable to get requested clock: %s\n", id);
-found:
-        mutex_unlock(&clocks_mutex);
-        return clk;
-}
-EXPORT_SYMBOL(clk_get);
-#endif
 static void __clk_disable(struct clk *clk)
 {
        if (clk == NULL || IS_ERR(clk))
@@ -193,16 +124,6 @@ unsigned long clk_get_rate(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_rate);
-#ifndef CONFIG_COMMON_CLKDEV
-/* Decrement the clock's module reference count */
-void clk_put(struct clk *clk)
-{
-        if (clk && !IS_ERR(clk))
-                module_put(clk->owner);
-}
-EXPORT_SYMBOL(clk_put);
-#endif
 /* Round the requested clock rate to the nearest supported
 * rate that is less than or equal to the requested rate.
 * This is dependent on the clock's current parent.
@@ -265,80 +186,6 @@ struct clk *clk_get_parent(struct clk *clk)
 }
 EXPORT_SYMBOL(clk_get_parent);
-#ifndef CONFIG_COMMON_CLKDEV
-/*
- * Add a new clock to the clock tree.
- */
-int clk_register(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return -EINVAL;
-        mutex_lock(&clocks_mutex);
-        list_add(&clk->node, &clocks);
-        mutex_unlock(&clocks_mutex);
-        return 0;
-}
-EXPORT_SYMBOL(clk_register);
-/* Remove a clock from the clock tree */
-void clk_unregister(struct clk *clk)
-{
-        if (clk == NULL || IS_ERR(clk))
-                return;
-        mutex_lock(&clocks_mutex);
-        list_del(&clk->node);
-        mutex_unlock(&clocks_mutex);
-}
-EXPORT_SYMBOL(clk_unregister);
-#ifdef CONFIG_PROC_FS
-static int mxc_clock_read_proc(char *page, char **start, off_t off,
-                                int count, int *eof, void *data)
-{
-        struct clk *clkp;
-        char *p = page;
-        int len;
-        list_for_each_entry(clkp, &clocks, node) {
-                p += sprintf(p, "%s-%d:\t\t%lu, %d", clkp->name, clkp->id,
-                                clk_get_rate(clkp), clkp->usecount);
-                if (clkp->parent)
-                        p += sprintf(p, ", %s-%d\n", clkp->parent->name,
-                                     clkp->parent->id);
-                else
-                        p += sprintf(p, "\n");
-        }
-        len = (p - page) - off;
-        if (len < 0)
-                len = 0;
-        *eof = (len <= count) ? 1 : 0;
-        *start = page + off;
-        return len;
-}
-static int __init mxc_setup_proc_entry(void)
-{
-        struct proc_dir_entry *res;
-        res = create_proc_read_entry("cpu/clocks", 0, NULL,
-                                     mxc_clock_read_proc, NULL);
-        if (!res) {
-                printk(KERN_ERR "Failed to create proc/cpu/clocks\n");
-                return -ENOMEM;
-        }
-        return 0;
-}
-late_initcall(mxc_setup_proc_entry);
-#endif /* CONFIG_PROC_FS */
-#endif
 /*
 * Get the resulting clock rate from a PLL register value and the input
 * frequency. PLLs with this register layout can at least be found on
@@ -363,12 +210,11 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
        mfn_abs = mfn;
-#if !defined CONFIG_ARCH_MX1 && !defined CONFIG_ARCH_MX21
+        /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
-        if (mfn >= 0x200) {
+         * 2's complements number
-                mfn |= 0xFFFFFE00;
+         */
-                mfn_abs = -mfn;
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
-        }
+                mfn_abs = 0x400 - mfn;
-#endif
        freq *= 2;
        freq /= pd + 1;
@@ -376,8 +222,10 @@ unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
        ll = (unsigned long long)freq * mfn_abs;
        do_div(ll, mfd + 1);
-        if (mfn < 0)
+        if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
                ll = -ll;
        ll = (freq * mfi) + ll;
        return ll;
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 7506d963be4b..cfc4a8b43e6a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -29,6 +29,23 @@
 static struct mxc_gpio_port *mxc_gpio_ports;
 static int gpio_table_size;
+#define cpu_is_mx1_mx2()        (cpu_is_mx1() || cpu_is_mx2())
+#define GPIO_DR         (cpu_is_mx1_mx2() ? 0x1c : 0x00)
+#define GPIO_GDIR       (cpu_is_mx1_mx2() ? 0x00 : 0x04)
+#define GPIO_PSR        (cpu_is_mx1_mx2() ? 0x24 : 0x08)
+#define GPIO_ICR1       (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
+#define GPIO_ICR2       (cpu_is_mx1_mx2() ? 0x2C : 0x10)
+#define GPIO_IMR        (cpu_is_mx1_mx2() ? 0x30 : 0x14)
+#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+#define GPIO_ISR        (cpu_is_mx1_mx2() ? 0x34 : 0x18)
+#define GPIO_INT_LOW_LEV        (cpu_is_mx1_mx2() ? 0x3 : 0x0)
+#define GPIO_INT_HIGH_LEV       (cpu_is_mx1_mx2() ? 0x2 : 0x1)
+#define GPIO_INT_RISE_EDGE      (cpu_is_mx1_mx2() ? 0x0 : 0x2)
+#define GPIO_INT_FALL_EDGE      (cpu_is_mx1_mx2() ? 0x1 : 0x3)
+#define GPIO_INT_NONE           0x4
 /* Note: This driver assumes 32 GPIOs are handled in one register */
 static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
@@ -162,7 +179,6 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
        }
 }
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
 /* MX1 and MX3 has one interrupt *per* gpio port */
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -174,9 +190,7 @@ static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
        mxc_gpio_irq_handler(port, irq_stat);
 }
-#endif
-#ifdef CONFIG_ARCH_MX2
 /* MX2 has one interrupt *for all* gpio ports */
 static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
@@ -195,7 +209,6 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
                        mxc_gpio_irq_handler(&port[i], irq_stat);
        }
 }
-#endif
 static struct irq_chip gpio_irq_chip = {
        .ack = gpio_ack_irq,
@@ -284,17 +297,18 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                /* its a serious configuration bug when it fails */
                BUG_ON( gpiochip_add(&port[i].chip) < 0 );
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
+                if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
-                /* setup one handler for each entry */
+                        /* setup one handler for each entry */
-                set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
+                        set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
-                set_irq_data(port[i].irq, &port[i]);
+                        set_irq_data(port[i].irq, &port[i]);
-#endif
+                }
+        }
+        if (cpu_is_mx2()) {
+                /* setup one handler for all GPIO interrupts */
+                set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+                set_irq_data(port[0].irq, port);
        }
-#ifdef CONFIG_ARCH_MX2
-        /* setup one handler for all GPIO interrupts */
-        set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-        set_irq_data(port[0].irq, port);
-#endif
        return 0;
 }
diff --git a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
index 8769e910e559..0376c133c9f4 100644
--- a/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
+++ b/arch/arm/plat-mxc/include/mach/board-armadillo5x0.h
@@ -12,11 +12,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
 #define __ASM_ARCH_MXC_BOARD_ARMADILLO5X0_H__
-#include <mach/hardware.h>
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
new file mode 100644
index 000000000000..a1fd5830af48
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/board-eukrea_cpuimx27.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2009 Eric Benard - eric@eukrea.com
+ *
+ * Based on board-pcm038.h which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+#define __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__
+#ifndef __ASSEMBLY__
+/*
+ * This CPU module needs a baseboard to work. After basic initializing
+ * its own devices, it calls baseboard's init function.
+ * TODO: Add your own baseboard init function and call it from
+ * inside eukrea_cpuimx27_init().
+ *
+ * This example here is for the development board. Refer
+ * eukrea_mbimx27-baseboard.c
+ */
+extern void eukrea_mbimx27_baseboard_init(void);
+#endif
+#endif /* __ASM_ARCH_MXC_BOARD_EUKREA_CPUIMX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx21ads.h b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
index 06701df74c42..0cf4fa29510c 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx21ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx21ads.h
@@ -15,12 +15,6 @@
 #define __ASM_ARCH_MXC_BOARD_MX21ADS_H__
 /*
- * MXC UART EVB board level configurations
- */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
-/*
 * Memory-mapped I/O on MX21ADS base board
 */
 #define MX21ADS_MMIO_BASE_ADDR   0xF5000000
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27ads.h b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
index d42f4e6116f8..7776d230327f 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27ads.h
@@ -26,12 +26,6 @@
                                MXC_MAX_VIRTUAL_INTS)
 /*
- * MXC UART EVB board level configurations
- */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPI_IO_ADDRESS(UART1_BASE_ADDR)
-/*
 * @name Memory Size parameters
 */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27lite.h b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
index a870f8ea2443..ea87551d2736 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27lite.h
@@ -11,9 +11,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX27LITE_H__
 #define __ASM_ARCH_MXC_BOARD_MX27LITE_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_MX27LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
index 552b55d714d8..fec1bcfa9164 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx27pdk.h
@@ -11,9 +11,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX27PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX27PDK_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_MX27PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31ads.h b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
index 06e6895f7f65..2cbfa35e82ff 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31ads.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31ads.h
@@ -114,9 +114,4 @@
 #define MXC_MAX_EXP_IO_LINES    16
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
index 78cf31e22e4d..eb5a5024622e 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lilly.h
@@ -22,11 +22,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
 #define __ASM_ARCH_MXC_BOARD_MX31LILLY_H__
-/* mandatory for CONFIG_LL_DEBUG */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
 #ifndef __ASSEMBLY__
 enum mx31lilly_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31lite.h b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
index 52fbdf2d6f26..8e64325d6905 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31lite.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31lite.h
@@ -11,8 +11,5 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
 #define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_MX31LITE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
index 303fd2434a21..d5be6b5a6acf 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31moboard.h
@@ -19,11 +19,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
 #define __ASM_ARCH_MXC_BOARD_MX31MOBOARD_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
 #ifndef __ASSEMBLY__
 enum mx31moboard_boards {
diff --git a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
index 519bab3eb28b..2bbd6ed17f50 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx31pdk.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 /* Definitions for components on the Debug board */
 /* Base address of CPLD controller on the Debug board */
diff --git a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
index 1111037d6d9d..383f1c04df06 100644
--- a/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
+++ b/arch/arm/plat-mxc/include/mach/board-mx35pdk.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_MX35PDK_H__
 #define __ASM_ARCH_MXC_BOARD_MX35PDK_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_MX35PDK_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm037.h b/arch/arm/plat-mxc/include/mach/board-pcm037.h
index f0a1fa1938a2..13411709b13a 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm037.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm037.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
 #define __ASM_ARCH_MXC_BOARD_PCM037_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm038.h b/arch/arm/plat-mxc/include/mach/board-pcm038.h
index 4fcd7499e092..410f9786ed22 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm038.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm038.h
@@ -19,11 +19,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
 #define __ASM_ARCH_MXC_BOARD_PCM038_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       (AIPI_BASE_ADDR_VIRT + 0x0A000)
 #ifndef __ASSEMBLY__
 /*
 * This CPU module needs a baseboard to work. After basic initializing
diff --git a/arch/arm/plat-mxc/include/mach/board-pcm043.h b/arch/arm/plat-mxc/include/mach/board-pcm043.h
index 15fbdf16abcd..1ac4e1682e5c 100644
--- a/arch/arm/plat-mxc/include/mach/board-pcm043.h
+++ b/arch/arm/plat-mxc/include/mach/board-pcm043.h
@@ -19,9 +19,4 @@
 #ifndef __ASM_ARCH_MXC_BOARD_PCM043_H__
 #define __ASM_ARCH_MXC_BOARD_PCM043_H__
-/* mandatory for CONFIG_LL_DEBUG */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif /* __ASM_ARCH_MXC_BOARD_PCM043_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/board-qong.h b/arch/arm/plat-mxc/include/mach/board-qong.h
index 04033ec637d2..6d88c7af4b23 100644
--- a/arch/arm/plat-mxc/include/mach/board-qong.h
+++ b/arch/arm/plat-mxc/include/mach/board-qong.h
@@ -11,11 +11,6 @@
 #ifndef __ASM_ARCH_MXC_BOARD_QONG_H__
 #define __ASM_ARCH_MXC_BOARD_QONG_H__
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 /* NOR FLASH */
 #define QONG_NOR_SIZE           (128*1024*1024)
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 02c3cd004db3..286cb9b0a25b 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -16,18 +16,33 @@ struct clk;
 extern void mx1_map_io(void);
 extern void mx21_map_io(void);
+extern void mx25_map_io(void);
 extern void mx27_map_io(void);
 extern void mx31_map_io(void);
 extern void mx35_map_io(void);
-extern void mxc_init_irq(void);
+extern void mxc91231_map_io(void);
-extern void mxc_timer_init(struct clk *timer_clk);
+extern void mxc_init_irq(void __iomem *);
+extern void mx1_init_irq(void);
+extern void mx21_init_irq(void);
+extern void mx25_init_irq(void);
+extern void mx27_init_irq(void);
+extern void mx31_init_irq(void);
+extern void mx35_init_irq(void);
+extern void mxc91231_init_irq(void);
+extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
 extern int mx1_clocks_init(unsigned long fref);
 extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
+extern int mx25_clocks_init(unsigned long fref);
 extern int mx27_clocks_init(unsigned long fref);
 extern int mx31_clocks_init(unsigned long fref);
 extern int mx35_clocks_init(void);
+extern int mxc91231_clocks_init(unsigned long fref);
 extern int mxc_register_gpios(void);
 extern int mxc_register_device(struct platform_device *pdev, void *data);
 extern void mxc_set_cpu_type(unsigned int type);
+extern void mxc_arch_reset_init(void __iomem *);
+extern void mxc91231_power_off(void);
+extern void mxc91231_arch_reset(int, const char *);
+extern void mxc91231_prepare_idle(void);
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index bbc5f6753cfb..15b2b148a105 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -11,52 +11,52 @@
 *
 */
-#include <mach/hardware.h>
+#ifdef CONFIG_ARCH_MX1
+#include <mach/mx1.h>
-#ifdef CONFIG_MACH_MX31ADS
+#define UART_PADDR      UART1_BASE_ADDR
-#include <mach/board-mx31ads.h>
+#define UART_VADDR      IO_ADDRESS(UART1_BASE_ADDR)
-#endif
-#ifdef CONFIG_MACH_PCM037
-#include <mach/board-pcm037.h>
-#endif
-#ifdef CONFIG_MACH_MX31LITE
-#include <mach/board-mx31lite.h>
-#endif
-#ifdef CONFIG_MACH_MX27ADS
-#include <mach/board-mx27ads.h>
-#endif
-#ifdef CONFIG_MACH_MX21ADS
-#include <mach/board-mx21ads.h>
 #endif
-#ifdef CONFIG_MACH_PCM038
-#include <mach/board-pcm038.h>
+#ifdef CONFIG_ARCH_MX25
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_MX31_3DS
+#include <mach/mx25.h>
-#include <mach/board-mx31pdk.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      MX25_AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_QONG
-#include <mach/board-qong.h>
+#ifdef CONFIG_ARCH_MX2
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_PCM043
+#include <mach/mx2x.h>
-#include <mach/board-pcm043.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      AIPI_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_MX27_3DS
-#include <mach/board-mx27pdk.h>
+#ifdef CONFIG_ARCH_MX3
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_ARMADILLO5X0
+#include <mach/mx3x.h>
-#include <mach/board-armadillo5x0.h>
+#define UART_PADDR      UART1_BASE_ADDR
+#define UART_VADDR      AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
 #endif
-#ifdef CONFIG_MACH_MX35_3DS
-#include <mach/board-mx35pdk.h>
+#ifdef CONFIG_ARCH_MXC91231
+#ifdef UART_PADDR
+#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
 #endif
-#ifdef CONFIG_MACH_MX27LITE
+#include <mach/mxc91231.h>
-#include <mach/board-mx27lite.h>
+#define UART_PADDR      MXC91231_UART2_BASE_ADDR
+#define UART_VADDR      MXC91231_AIPS1_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
 #endif
                .macro  addruart,rx
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1                 @ MMU enabled?
-                ldreq   \rx, =MXC_LL_UART_PADDR @ physical
+                ldreq   \rx, =UART_PADDR        @ physical
-                ldrne   \rx, =MXC_LL_UART_VADDR @ virtual
+                ldrne   \rx, =UART_VADDR        @ virtual
                .endm
                .macro  senduart,rd,rx
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index 5f01d60da845..7cf290efe768 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -18,7 +18,8 @@
        .endm
        .macro  get_irqnr_preamble, base, tmp
-        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+        ldr     \base, =avic_base
+        ldr     \base, [\base]
 #ifdef CONFIG_MXC_IRQ_PRIOR
        ldr     r4, [\base, #AVIC_NIMASK]
 #endif
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 42e4ee37ca1f..78db75475f69 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -42,6 +42,14 @@
 # include <mach/mx1.h>
 #endif
+#ifdef CONFIG_ARCH_MX25
+# include <mach/mx25.h>
+#endif
+#ifdef CONFIG_ARCH_MXC91231
+# include <mach/mxc91231.h>
+#endif
 #include <mach/mxc.h>
 #endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 9f0101157ec1..5263506b7ddf 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -2,6 +2,8 @@
 * This structure describes the machine which we are running on.
 */
+#include <linux/fb.h>
 #define PCR_TFT         (1 << 31)
 #define PCR_COLOR       (1 << 30)
 #define PCR_PBSIZ_1     (0 << 28)
@@ -13,7 +15,8 @@
 #define PCR_BPIX_4      (2 << 25)
 #define PCR_BPIX_8      (3 << 25)
 #define PCR_BPIX_12     (4 << 25)
-#define PCR_BPIX_16     (4 << 25)
+#define PCR_BPIX_16     (5 << 25)
+#define PCR_BPIX_18     (6 << 25)
 #define PCR_PIXPOL      (1 << 24)
 #define PCR_FLMPOL      (1 << 23)
 #define PCR_LPPOL       (1 << 22)
@@ -46,29 +49,21 @@
 #define DMACR_HM(x)     (((x) & 0xf) << 16)
 #define DMACR_TM(x)     ((x) & 0xf)
-struct imx_fb_platform_data {
+struct imx_fb_videomode {
-        u_long          pixclock;
+        struct fb_videomode mode;
+        u32 pcr;
-        u_short         xres;
+        unsigned char   bpp;
-        u_short         yres;
+};
-        u_int           nonstd;
-        u_char          bpp;
-        u_char          hsync_len;
-        u_char          left_margin;
-        u_char          right_margin;
-        u_char          vsync_len;
+struct imx_fb_platform_data {
-        u_char          upper_margin;
+        struct imx_fb_videomode *mode;
-        u_char          lower_margin;
+        int             num_modes;
-        u_char          sync;
        u_int           cmap_greyscale:1,
                        cmap_inverse:1,
                        cmap_static:1,
                        unused:29;
-        u_int           pcr;
        u_int           pwmr;
        u_int           lscr1;
        u_int           dmacr;
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
new file mode 100644
index 000000000000..810c47f56e77
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -0,0 +1,517 @@
+/*
+ * arch/arm/plat-mxc/include/mach/iomux-mx25.h
+ *
+ * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
+ *
+ * based on arch/arm/mach-mx25/mx25_pins.h
+ *    Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ * and
+ * arch/arm/plat-mxc/include/mach/iomux-mx35.h
+ *    Copyright (C, NO_PAD_CTRL) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#ifndef __IOMUX_MX25_H__
+#define __IOMUX_MX25_H__
+#include <mach/iomux-v3.h>
+#ifndef GPIO_PORTA
+#error Please include mach/iomux.h
+#endif
+/*
+ *
+ * @brief MX25 I/O Pin List
+ *
+ * @ingroup GPIO_MX25
+ */
+#ifndef __ASSEMBLY__
+/*
+ * IOMUX/PAD Bit field definitions
+ */
+#define MX25_PAD_A10__A10               IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A10__GPIO_4_0          IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A13__A13               IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A13__GPIO_4_1          IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A14__A14               IOMUX_PAD(0x230, 0x010, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A14__GPIO_2_0          IOMUX_PAD(0x230, 0x010, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A15__A15               IOMUX_PAD(0x234, 0x014, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A15__GPIO_2_1          IOMUX_PAD(0x234, 0x014, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A16__A16               IOMUX_PAD(0x000, 0x018, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A16__GPIO_2_2          IOMUX_PAD(0x000, 0x018, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A17__A17               IOMUX_PAD(0x238, 0x01c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A17__GPIO_2_3          IOMUX_PAD(0x238, 0x01c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A18__A18               IOMUX_PAD(0x23c, 0x020, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A18__GPIO_2_4          IOMUX_PAD(0x23c, 0x020, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A18__FEC_COL           IOMUX_PAD(0x23c, 0x020, 0x17, 0x504, 0, NO_PAD_CTL)
+#define MX25_PAD_A19__A19               IOMUX_PAD(0x240, 0x024, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A19__FEC_RX_ER         IOMUX_PAD(0x240, 0x024, 0x17, 0x518, 0, NO_PAD_CTL)
+#define MX25_PAD_A19__GPIO_2_5          IOMUX_PAD(0x240, 0x024, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A20__A20               IOMUX_PAD(0x244, 0x028, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A20__GPIO_2_6          IOMUX_PAD(0x244, 0x028, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A20__FEC_RDATA2        IOMUX_PAD(0x244, 0x028, 0x17, 0x50c, 0, NO_PAD_CTL)
+#define MX25_PAD_A21__A21               IOMUX_PAD(0x248, 0x02c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A21__GPIO_2_7          IOMUX_PAD(0x248, 0x02c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A21__FEC_RDATA3        IOMUX_PAD(0x248, 0x02c, 0x17, 0x510, 0, NO_PAD_CTL)
+#define MX25_PAD_A22__A22               IOMUX_PAD(0x000, 0x030, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A22__GPIO_2_8          IOMUX_PAD(0x000, 0x030, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A23__A23               IOMUX_PAD(0x24c, 0x034, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A23__GPIO_2_9          IOMUX_PAD(0x24c, 0x034, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A24__A24               IOMUX_PAD(0x250, 0x038, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A24__GPIO_2_10         IOMUX_PAD(0x250, 0x038, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A24__FEC_RX_CLK        IOMUX_PAD(0x250, 0x038, 0x17, 0x514, 0, NO_PAD_CTL)
+#define MX25_PAD_A25__A25               IOMUX_PAD(0x254, 0x03c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A25__GPIO_2_11         IOMUX_PAD(0x254, 0x03c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_A25__FEC_CRS           IOMUX_PAD(0x254, 0x03c, 0x17, 0x508, 0, NO_PAD_CTL)
+#define MX25_PAD_EB0__EB0               IOMUX_PAD(0x258, 0x040, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB0__AUD4_TXD          IOMUX_PAD(0x258, 0x040, 0x14, 0x464, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB0__GPIO_2_12         IOMUX_PAD(0x258, 0x040, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB1__EB1               IOMUX_PAD(0x25c, 0x044, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB1__AUD4_RXD          IOMUX_PAD(0x25c, 0x044, 0x14, 0x460, 0, NO_PAD_CTRL)
+#define MX25_PAD_EB1__GPIO_2_13         IOMUX_PAD(0x25c, 0x044, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE__OE                 IOMUX_PAD(0x260, 0x048, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE__AUD4_TXC           IOMUX_PAD(0x260, 0x048, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE__GPIO_2_14          IOMUX_PAD(0x260, 0x048, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS0__CS0               IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS0__GPIO_4_2          IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS1__CS1               IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS1__GPIO_4_3          IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__CS4               IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__UART5_CTS         IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__GPIO_3_20         IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__CS5               IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__UART5_RTS         IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__GPIO_3_21         IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NF_CE0__NF_CE0         IOMUX_PAD(0x26c, 0x05c, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_NF_CE0__GPIO_3_22      IOMUX_PAD(0x26c, 0x05c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_ECB__ECB               IOMUX_PAD(0x270, 0x060, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_ECB__UART5_TXD_MUX     IOMUX_PAD(0x270, 0x060, 0x13, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_ECB__GPIO_3_23         IOMUX_PAD(0x270, 0x060, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LBA__LBA               IOMUX_PAD(0x274, 0x064, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LBA__UART5_RXD_MUX     IOMUX_PAD(0x274, 0x064, 0x13, 0x578, 0, NO_PAD_CTRL)
+#define MX25_PAD_LBA__GPIO_3_24         IOMUX_PAD(0x274, 0x064, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BCLK__BCLK             IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BCLK__GPIO_4_4         IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RW__RW                 IOMUX_PAD(0x278, 0x06c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RW__AUD4_TXFS          IOMUX_PAD(0x278, 0x06c, 0x14, 0x474, 0, NO_PAD_CTRL)
+#define MX25_PAD_RW__GPIO_3_25          IOMUX_PAD(0x278, 0x06c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWE_B__NFWE_B         IOMUX_PAD(0x000, 0x070, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWE_B__GPIO_3_26      IOMUX_PAD(0x000, 0x070, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFRE_B__NFRE_B         IOMUX_PAD(0x000, 0x074, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFRE_B__GPIO_3_27      IOMUX_PAD(0x000, 0x074, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFALE__NFALE           IOMUX_PAD(0x000, 0x078, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFALE__GPIO_3_28       IOMUX_PAD(0x000, 0x078, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFCLE__NFCLE           IOMUX_PAD(0x000, 0x07c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFCLE__GPIO_3_29       IOMUX_PAD(0x000, 0x07c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWP_B__NFWP_B         IOMUX_PAD(0x000, 0x080, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFWP_B__GPIO_3_30      IOMUX_PAD(0x000, 0x080, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_NFRB__NFRB             IOMUX_PAD(0x27c, 0x084, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_NFRB__GPIO_3_31        IOMUX_PAD(0x27c, 0x084, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__D15               IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__LD16              IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D15__GPIO_4_5          IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__D14               IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__LD17              IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D14__GPIO_4_6          IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__D13               IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__LD18              IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D13__GPIO_4_7          IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D12__D12               IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D12__GPIO_4_8          IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D11__D11               IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D11__GPIO_4_9          IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D10__D10               IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D10__GPIO_4_10         IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D10__USBOTG_OC         IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_D9__D9                 IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D9__GPIO_4_11          IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D9__USBH2_PWR          IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_D8__D8                 IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D8__GPIO_4_12          IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D8__USBH2_OC           IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_D7__D7                 IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D7__GPIO_4_13          IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D6__D6                 IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D6__GPIO_4_14          IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D5__D5                 IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D5__GPIO_4_15          IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D4__D4                 IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D4__GPIO_4_16          IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D3__D3                 IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D3__GPIO_4_17          IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D2__D2                 IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D2__GPIO_4_18          IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D1__D1                 IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D1__GPIO_4_19          IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D0__D0                 IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_D0__GPIO_4_20          IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__LD0               IOMUX_PAD(0x2c0, 0x0c8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__CSI_D0            IOMUX_PAD(0x2c0, 0x0c8, 0x12, 0x488, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD0__GPIO_2_15         IOMUX_PAD(0x2c0, 0x0c8, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__LD1               IOMUX_PAD(0x2c4, 0x0cc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__CSI_D1            IOMUX_PAD(0x2c4, 0x0cc, 0x12, 0x48c, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD1__GPIO_2_16         IOMUX_PAD(0x2c4, 0x0cc, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__LD2               IOMUX_PAD(0x2c8, 0x0d0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD2__GPIO_2_17         IOMUX_PAD(0x2c8, 0x0d0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__LD3               IOMUX_PAD(0x2cc, 0x0d4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD3__GPIO_2_18         IOMUX_PAD(0x2cc, 0x0d4, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__LD4               IOMUX_PAD(0x2d0, 0x0d8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD4__GPIO_2_19         IOMUX_PAD(0x2d0, 0x0d8, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__LD5               IOMUX_PAD(0x2d4, 0x0dc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD5__GPIO_1_19         IOMUX_PAD(0x2d4, 0x0dc, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__LD6               IOMUX_PAD(0x2d8, 0x0e0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD6__GPIO_1_20         IOMUX_PAD(0x2d8, 0x0e0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__LD7               IOMUX_PAD(0x2dc, 0x0e4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD7__GPIO_1_21         IOMUX_PAD(0x2dc, 0x0e4, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__LD8               IOMUX_PAD(0x2e0, 0x0e8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD8__FEC_TX_ERR        IOMUX_PAD(0x2e0, 0x0e8, 0x15, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_LD9__LD9               IOMUX_PAD(0x2e4, 0x0ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD9__FEC_COL           IOMUX_PAD(0x2e4, 0x0ec, 0x15, 0x504, 1, NO_PAD_CTL)
+#define MX25_PAD_LD10__LD10             IOMUX_PAD(0x2e8, 0x0f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD10__FEC_RX_ER        IOMUX_PAD(0x2e8, 0x0f0, 0x15, 0x518, 1, NO_PAD_CTL)
+#define MX25_PAD_LD11__LD11             IOMUX_PAD(0x2ec, 0x0f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD11__FEC_RDATA2       IOMUX_PAD(0x2ec, 0x0f4, 0x15, 0x50c, 1, NO_PAD_CTL)
+#define MX25_PAD_LD12__LD12             IOMUX_PAD(0x2f0, 0x0f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD12__FEC_RDATA3       IOMUX_PAD(0x2f0, 0x0f8, 0x15, 0x510, 1, NO_PAD_CTL)
+#define MX25_PAD_LD13__LD13             IOMUX_PAD(0x2f4, 0x0fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD13__FEC_TDATA2       IOMUX_PAD(0x2f4, 0x0fc, 0x15, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_LD14__LD14             IOMUX_PAD(0x2f8, 0x100, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD14__FEC_TDATA3       IOMUX_PAD(0x2f8, 0x100, 0x15, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_LD15__LD15             IOMUX_PAD(0x2fc, 0x104, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LD15__FEC_RX_CLK       IOMUX_PAD(0x2fc, 0x104, 0x15, 0x514, 1, NO_PAD_CTL)
+#define MX25_PAD_HSYNC__HSYNC           IOMUX_PAD(0x300, 0x108, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_HSYNC__GPIO_1_22       IOMUX_PAD(0x300, 0x108, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSYNC__VSYNC           IOMUX_PAD(0x304, 0x10c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSYNC__GPIO_1_23       IOMUX_PAD(0x304, 0x10c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LSCLK__LSCLK           IOMUX_PAD(0x308, 0x110, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_LSCLK__GPIO_1_24       IOMUX_PAD(0x308, 0x110, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE_ACD__OE_ACD         IOMUX_PAD(0x30c, 0x114, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_OE_ACD__GPIO_1_25      IOMUX_PAD(0x30c, 0x114, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__CONTRAST     IOMUX_PAD(0x310, 0x118, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CONTRAST__FEC_CRS      IOMUX_PAD(0x310, 0x118, 0x15, 0x508, 1, NO_PAD_CTL)
+#define MX25_PAD_PWM__PWM               IOMUX_PAD(0x314, 0x11c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_PWM__GPIO_1_26         IOMUX_PAD(0x314, 0x11c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_PWM__USBH2_OC          IOMUX_PAD(0x314, 0x11c, 0x16, 0x580, 1, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_CSI_D2__CSI_D2         IOMUX_PAD(0x318, 0x120, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__UART5_RXD_MUX  IOMUX_PAD(0x318, 0x120, 0x11, 0x578, 1, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D2__GPIO_1_27      IOMUX_PAD(0x318, 0x120, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D3__CSI_D3         IOMUX_PAD(0x31c, 0x124, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D3__GPIO_1_28      IOMUX_PAD(0x31c, 0x124, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__CSI_D4         IOMUX_PAD(0x320, 0x128, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__UART5_RTS      IOMUX_PAD(0x320, 0x128, 0x11, 0x574, 1, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D4__GPIO_1_29      IOMUX_PAD(0x320, 0x128, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D5__CSI_D5         IOMUX_PAD(0x324, 0x12c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D5__GPIO_1_30      IOMUX_PAD(0x324, 0x12c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D6__CSI_D6         IOMUX_PAD(0x328, 0x130, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D6__GPIO_1_31      IOMUX_PAD(0x328, 0x130, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D7__CSI_D7         IOMUX_PAD(0x32c, 0x134, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D7__GPIO_1_6       IOMUX_PAD(0x32c, 0x134, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D8__CSI_D8         IOMUX_PAD(0x330, 0x138, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D8__GPIO_1_7       IOMUX_PAD(0x330, 0x138, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D9__CSI_D9         IOMUX_PAD(0x334, 0x13c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_D9__GPIO_4_21      IOMUX_PAD(0x334, 0x13c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_MCLK__CSI_MCLK     IOMUX_PAD(0x338, 0x140, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_MCLK__GPIO_1_8     IOMUX_PAD(0x338, 0x140, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_VSYNC__CSI_VSYNC   IOMUX_PAD(0x33c, 0x144, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_VSYNC__GPIO_1_9    IOMUX_PAD(0x33c, 0x144, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_HSYNC__CSI_HSYNC   IOMUX_PAD(0x340, 0x148, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_HSYNC__GPIO_1_10   IOMUX_PAD(0x340, 0x148, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK IOMUX_PAD(0x344, 0x14c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSI_PIXCLK__GPIO_1_11  IOMUX_PAD(0x344, 0x14c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_CLK__I2C1_CLK     IOMUX_PAD(0x348, 0x150, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_CLK__GPIO_1_12    IOMUX_PAD(0x348, 0x150, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_DAT__I2C1_DAT     IOMUX_PAD(0x34c, 0x154, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_I2C1_DAT__GPIO_1_13    IOMUX_PAD(0x34c, 0x154, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MOSI__CSPI1_MOSI IOMUX_PAD(0x350, 0x158, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MOSI__GPIO_1_14  IOMUX_PAD(0x350, 0x158, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MISO__CSPI1_MISO IOMUX_PAD(0x354, 0x15c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_MISO__GPIO_1_15  IOMUX_PAD(0x354, 0x15c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS0__CSPI1_SS0   IOMUX_PAD(0x358, 0x160, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS0__GPIO_1_16   IOMUX_PAD(0x358, 0x160, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS1__CSPI1_SS1   IOMUX_PAD(0x35c, 0x164, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SS1__GPIO_1_17   IOMUX_PAD(0x35c, 0x164, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SCLK__CSPI1_SCLK IOMUX_PAD(0x360, 0x168, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_SCLK__GPIO_1_18  IOMUX_PAD(0x360, 0x168, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CSPI1_RDY__CSPI1_RDY   IOMUX_PAD(0x364, 0x16c, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_CSPI1_RDY__GPIO_2_22   IOMUX_PAD(0x364, 0x16c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART1_RXD__UART1_RXD   IOMUX_PAD(0x368, 0x170, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN)
+#define MX25_PAD_UART1_RXD__GPIO_4_22   IOMUX_PAD(0x368, 0x170, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART1_TXD__UART1_TXD   IOMUX_PAD(0x36c, 0x174, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART1_TXD__GPIO_4_23   IOMUX_PAD(0x36c, 0x174, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART1_RTS__UART1_RTS   IOMUX_PAD(0x370, 0x178, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_UART1_RTS__CSI_D0      IOMUX_PAD(0x370, 0x178, 0x11, 0x488, 1, NO_PAD_CTRL)
+#define MX25_PAD_UART1_RTS__GPIO_4_24   IOMUX_PAD(0x370, 0x178, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART1_CTS__UART1_CTS   IOMUX_PAD(0x374, 0x17c, 0x10, 0, 0, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_UART1_CTS__CSI_D1      IOMUX_PAD(0x374, 0x17c, 0x11, 0x48c, 1, NO_PAD_CTRL)
+#define MX25_PAD_UART1_CTS__GPIO_4_25   IOMUX_PAD(0x374, 0x17c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RXD__UART2_RXD   IOMUX_PAD(0x378, 0x180, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RXD__GPIO_4_26   IOMUX_PAD(0x378, 0x180, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_TXD__UART2_TXD   IOMUX_PAD(0x37c, 0x184, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_TXD__GPIO_4_27   IOMUX_PAD(0x37c, 0x184, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RTS__UART2_RTS   IOMUX_PAD(0x380, 0x188, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_RTS__FEC_COL     IOMUX_PAD(0x380, 0x188, 0x12, 0x504, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_RTS__GPIO_4_28   IOMUX_PAD(0x380, 0x188, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_CTS__FEC_RX_ER   IOMUX_PAD(0x384, 0x18c, 0x12, 0x518, 2, NO_PAD_CTL)
+#define MX25_PAD_UART2_CTS__UART2_CTS   IOMUX_PAD(0x384, 0x18c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UART2_CTS__GPIO_4_29   IOMUX_PAD(0x384, 0x18c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_CMD__SD1_CMD       IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CMD__FEC_RDATA2    IOMUX_PAD(0x388, 0x190, 0x12, 0x50c, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CMD__GPIO_2_23     IOMUX_PAD(0x388, 0x190, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_CLK__SD1_CLK       IOMUX_PAD(0x38c, 0x194, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_CLK__FEC_RDATA3    IOMUX_PAD(0x38c, 0x194, 0x12, 0x510, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_CLK__GPIO_2_24     IOMUX_PAD(0x38c, 0x194, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA0__SD1_DATA0   IOMUX_PAD(0x390, 0x198, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA0__GPIO_2_25   IOMUX_PAD(0x390, 0x198, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA1__SD1_DATA1   IOMUX_PAD(0x394, 0x19c, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA1__AUD7_RXD    IOMUX_PAD(0x394, 0x19c, 0x13, 0x478, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA1__GPIO_2_26   IOMUX_PAD(0x394, 0x19c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA2__SD1_DATA2   IOMUX_PAD(0x398, 0x1a0, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA2__FEC_RX_CLK  IOMUX_PAD(0x398, 0x1a0, 0x15, 0x514, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA2__GPIO_2_27   IOMUX_PAD(0x398, 0x1a0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_SD1_DATA3__SD1_DATA3   IOMUX_PAD(0x39c, 0x1a4, 0x10, 0, 0, PAD_CTL_PUS_47K_UP)
+#define MX25_PAD_SD1_DATA3__FEC_CRS     IOMUX_PAD(0x39c, 0x1a4, 0x10, 0x508, 2, NO_PAD_CTL)
+#define MX25_PAD_SD1_DATA3__GPIO_2_28   IOMUX_PAD(0x39c, 0x1a4, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW0__KPP_ROW0     IOMUX_PAD(0x3a0, 0x1a8, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW0__GPIO_2_29    IOMUX_PAD(0x3a0, 0x1a8, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW1__KPP_ROW1     IOMUX_PAD(0x3a4, 0x1ac, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW1__GPIO_2_30    IOMUX_PAD(0x3a4, 0x1ac, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW2__KPP_ROW2     IOMUX_PAD(0x3a8, 0x1b0, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW2__CSI_D0       IOMUX_PAD(0x3a8, 0x1b0, 0x13, 0x488, 2, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW2__GPIO_2_31    IOMUX_PAD(0x3a8, 0x1b0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW3__KPP_ROW3     IOMUX_PAD(0x3ac, 0x1b4, 0x10, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_KPP_ROW3__CSI_LD1      IOMUX_PAD(0x3ac, 0x1b4, 0x13, 0x48c, 2, NO_PAD_CTRL)
+#define MX25_PAD_KPP_ROW3__GPIO_3_0     IOMUX_PAD(0x3ac, 0x1b4, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL0__KPP_COL0     IOMUX_PAD(0x3b0, 0x1b8, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL0__GPIO_3_1     IOMUX_PAD(0x3b0, 0x1b8, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL1__KPP_COL1     IOMUX_PAD(0x3b4, 0x1bc, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL1__GPIO_3_2     IOMUX_PAD(0x3b4, 0x1bc, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL2__KPP_COL2     IOMUX_PAD(0x3b8, 0x1c0, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL2__GPIO_3_3     IOMUX_PAD(0x3b8, 0x1c0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_KPP_COL3__KPP_COL3     IOMUX_PAD(0x3bc, 0x1c4, 0x10, 0, 0, PAD_CTL_PKE | PAD_CTL_ODE)
+#define MX25_PAD_KPP_COL3__GPIO_3_4     IOMUX_PAD(0x3bc, 0x1c4, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDC__FEC_MDC       IOMUX_PAD(0x3c0, 0x1c8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_MDC__AUD4_TXD      IOMUX_PAD(0x3c0, 0x1c8, 0x12, 0x464, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDC__GPIO_3_5      IOMUX_PAD(0x3c0, 0x1c8, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDIO__FEC_MDIO     IOMUX_PAD(0x3c4, 0x1cc, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_FEC_MDIO__AUD4_RXD     IOMUX_PAD(0x3c4, 0x1cc, 0x12, 0x460, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_MDIO__GPIO_3_6     IOMUX_PAD(0x3c4, 0x1cc, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_TDATA0__FEC_TDATA0 IOMUX_PAD(0x3c8, 0x1d0, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA0__GPIO_3_7   IOMUX_PAD(0x3c8, 0x1d0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_TDATA1__FEC_TDATA1 IOMUX_PAD(0x3cc, 0x1d4, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TDATA1__AUD4_TXFS  IOMUX_PAD(0x3cc, 0x1d4, 0x12, 0x474, 1, NO_PAD_CTRL)
+#define MX25_PAD_FEC_TDATA1__GPIO_3_8   IOMUX_PAD(0x3cc, 0x1d4, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_TX_EN__FEC_TX_EN   IOMUX_PAD(0x3d0, 0x1d8, 0x10, 0, 0, NO_PAD_CTL)
+#define MX25_PAD_FEC_TX_EN__GPIO_3_9    IOMUX_PAD(0x3d0, 0x1d8, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_RDATA0__FEC_RDATA0 IOMUX_PAD(0x3d4, 0x1dc, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA0__GPIO_3_10  IOMUX_PAD(0x3d4, 0x1dc, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 IOMUX_PAD(0x3d8, 0x1e0, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RDATA1__GPIO_3_11  IOMUX_PAD(0x3d8, 0x1e0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_RX_DV__FEC_RX_DV   IOMUX_PAD(0x3dc, 0x1e4, 0x10, 0, 0, PAD_CTL_PUS_100K_DOWN | NO_PAD_CTL)
+#define MX25_PAD_FEC_RX_DV__CAN2_RX     IOMUX_PAD(0x3dc, 0x1e4, 0x14, 0x484, 0, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_FEC_RX_DV__GPIO_3_12   IOMUX_PAD(0x3dc, 0x1e4, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_FEC_TX_CLK__FEC_TX_CLK IOMUX_PAD(0x3e0, 0x1e8, 0x10, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN)
+#define MX25_PAD_FEC_TX_CLK__GPIO_3_13  IOMUX_PAD(0x3e0, 0x1e8, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RTCK__RTCK             IOMUX_PAD(0x3e4, 0x1ec, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RTCK__OWIRE            IOMUX_PAD(0x3e4, 0x1ec, 0x11, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_RTCK__GPIO_3_14        IOMUX_PAD(0x3e4, 0x1ec, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_DE_B__DE_B             IOMUX_PAD(0x3ec, 0x1f0, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_DE_B__GPIO_2_20        IOMUX_PAD(0x3ec, 0x1f0, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_TDO__TDO               IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_A__GPIO_A         IOMUX_PAD(0x3f0, 0x1f4, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_A__CAN1_TX        IOMUX_PAD(0x3f0, 0x1f4, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_GPIO_A__USBOTG_PWR     IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
+#define MX25_PAD_GPIO_B__GPIO_B         IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_B__CAN1_RX        IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K)
+#define MX25_PAD_GPIO_B__USBOTG_OC      IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
+#define MX25_PAD_GPIO_C__GPIO_C         IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_C__CAN2_TX        IOMUX_PAD(0x3f8, 0x1fc, 0x16, 0, 0, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_GPIO_D__GPIO_D         IOMUX_PAD(0x3fc, 0x200, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_D__CAN2_RX        IOMUX_PAD(0x3fc, 0x200, 0x16, 0x484, 1, PAD_CTL_PUS_22K_UP)
+#define MX25_PAD_GPIO_E__GPIO_E         IOMUX_PAD(0x400, 0x204, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_E__AUD7_TXD       IOMUX_PAD(0x400, 0x204, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__GPIO_F         IOMUX_PAD(0x404, 0x208, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_GPIO_F__AUD7_TXC       IOMUX_PAD(0x404, 0x208, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK IOMUX_PAD(0x000, 0x20c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_EXT_ARMCLK__GPIO_3_15  IOMUX_PAD(0x000, 0x20c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK IOMUX_PAD(0x000, 0x210, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_UPLL_BYPCLK__GPIO_3_16 IOMUX_PAD(0x000, 0x210, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_REQ__VSTBY_REQ   IOMUX_PAD(0x408, 0x214, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_REQ__AUD7_TXFS   IOMUX_PAD(0x408, 0x214, 0x14, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_REQ__GPIO_3_17   IOMUX_PAD(0x408, 0x214, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_ACK__VSTBY_ACK   IOMUX_PAD(0x40c, 0x218, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_VSTBY_ACK__GPIO_3_18   IOMUX_PAD(0x40c, 0x218, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_POWER_FAIL__POWER_FAIL IOMUX_PAD(0x410, 0x21c, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_POWER_FAIL__AUD7_RXD   IOMUX_PAD(0x410, 0x21c, 0x14, 0x478, 1, NO_PAD_CTRL)
+#define MX25_PAD_POWER_FAIL__GPIO_3_19  IOMUX_PAD(0x410, 0x21c, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CLKO__CLKO             IOMUX_PAD(0x414, 0x220, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CLKO__GPIO_2_21        IOMUX_PAD(0x414, 0x220, 0x15, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE0__GPIO_4_30  IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_BOOT_MODE1__GPIO_4_31  IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_MISC       IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_FEC        IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_JTAG       IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_NFC        IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_CSI        IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_WEIM       IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_DDR        IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_CRM        IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_KPP        IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_SDHC1      IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_LCD        IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_UART       IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_NFC        IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_CSI        IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DSE_CSPI1      IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DDRTYPE        IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_SDHC1      IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CTL_GRP_DVS_LCD        IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL)
+#endif // __ASSEMBLY__
+#endif // __IOMUX_MX25_H__
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index 2eb182f73876..446f86763816 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -635,6 +635,19 @@ enum iomux_pins {
 #define MX31_PIN_USBOTG_DIR__USBOTG_DIR        IOMUX_MODE(MX31_PIN_USBOTG_DIR, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_NXT__USBOTG_NXT        IOMUX_MODE(MX31_PIN_USBOTG_NXT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USBOTG_STP__USBOTG_STP        IOMUX_MODE(MX31_PIN_USBOTG_STP, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_CSPI1_MOSI__USBH1_RXDM        IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_MISO__USBH1_RXDP        IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS0__USBH1_TXDM         IOMUX_MODE(MX31_PIN_CSPI1_SS0,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS1__USBH1_TXDP         IOMUX_MODE(MX31_PIN_CSPI1_SS1,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SS2__USBH1_RCV          IOMUX_MODE(MX31_PIN_CSPI1_SS2,  IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SCLK__USBH1_OEB         IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_CSPI1_SPI_RDY__USBH1_FS       IOMUX_MODE(MX31_PIN_CSPI1_SPI_RDY, IOMUX_CONFIG_ALT1)
+#define MX31_PIN_USBH2_DATA0__USBH2_DATA0      IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DATA1__USBH2_DATA1      IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_CLK__USBH2_CLK          IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_DIR__USBH2_DIR          IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_NXT__USBH2_NXT          IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_USBH2_STP__USBH2_STP          IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_USB_OC__GPIO1_30       IOMUX_MODE(MX31_PIN_USB_OC, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_I2C_DAT__I2C1_SDA      IOMUX_MODE(MX31_PIN_I2C_DAT, IOMUX_CONFIG_FUNC)
 #define MX31_PIN_I2C_CLK__I2C1_SCL      IOMUX_MODE(MX31_PIN_I2C_CLK, IOMUX_CONFIG_FUNC)
@@ -669,6 +682,18 @@ enum iomux_pins {
 #define MX31_PIN_GPIO3_0__GPIO3_0       IOMUX_MODE(MX31_PIN_GPIO3_0, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_GPIO3_1__GPIO3_1       IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO)
 #define MX31_PIN_TXD2__GPIO1_28         IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_GPIO1_0__GPIO1_0       IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SVEN0__GPIO2_0         IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STX0__GPIO2_1          IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRX0__GPIO2_2          IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SIMPD0__GPIO2_3        IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DTR_DCE1__GPIO2_8      IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DSR_DCE1__GPIO2_9      IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_RI_DCE1__GPIO2_10      IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_DCD_DCE1__GPIO2_11     IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_STXD5__GPIO1_21       IOMUX_MODE(MX31_PIN_STXD5, IOMUX_CONFIG_GPIO)
+#define MX31_PIN_SRXD5__GPIO1_22       IOMUX_MODE(MX31_PIN_SRXD5, IOMUX_CONFIG_GPIO)
 /*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
 * cspi1_ss1*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
new file mode 100644
index 000000000000..9f13061192c8
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __MACH_IOMUX_MXC91231_H__
+#define __MACH_IOMUX_MXC91231_H__
+/*
+ * various IOMUX output functions
+ */
+#define IOMUX_OCONFIG_GPIO (0 << 4)     /* used as GPIO */
+#define IOMUX_OCONFIG_FUNC (1 << 4)     /* used as function */
+#define IOMUX_OCONFIG_ALT1 (2 << 4)     /* used as alternate function 1 */
+#define IOMUX_OCONFIG_ALT2 (3 << 4)     /* used as alternate function 2 */
+#define IOMUX_OCONFIG_ALT3 (4 << 4)     /* used as alternate function 3 */
+#define IOMUX_OCONFIG_ALT4 (5 << 4)     /* used as alternate function 4 */
+#define IOMUX_OCONFIG_ALT5 (6 << 4)     /* used as alternate function 5 */
+#define IOMUX_OCONFIG_ALT6 (7 << 4)     /* used as alternate function 6 */
+#define IOMUX_ICONFIG_NONE  0           /* not configured for input */
+#define IOMUX_ICONFIG_GPIO  1           /* used as GPIO */
+#define IOMUX_ICONFIG_FUNC  2           /* used as function */
+#define IOMUX_ICONFIG_ALT1  4           /* used as alternate function 1 */
+#define IOMUX_ICONFIG_ALT2  8           /* used as alternate function 2 */
+#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
+#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
+#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
+#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
+/*
+ * setups a single pin:
+ *      - reserves the pin so that it is not claimed by another driver
+ *      - setups the iomux according to the configuration
+ *      - if the pin is configured as a GPIO, we claim it throug kernel gpiolib
+ */
+int mxc_iomux_alloc_pin(const unsigned int pin_mode, const char *label);
+/*
+ * setups mutliple pins
+ * convenient way to call the above function with tables
+ */
+int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
+                const char *label);
+/*
+ * releases a single pin:
+ *      - make it available for a future use by another driver
+ *      - frees the GPIO if the pin was configured as GPIO
+ *      - DOES NOT reconfigure the IOMUX in its reset state
+ */
+void mxc_iomux_release_pin(const unsigned int pin_mode);
+/*
+ * releases multiple pins
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count);
+#define MUX_SIDE_AP             (0)
+#define MUX_SIDE_SP             (1)
+#define MUX_SIDE_SHIFT          (26)
+#define MUX_SIDE_MASK           (0x1 << MUX_SIDE_SHIFT)
+#define MUX_GPIO_PORT_SHIFT     (23)
+#define MUX_GPIO_PORT_MASK      (0x7 << MUX_GPIO_PORT_SHIFT)
+#define MUX_GPIO_PIN_SHIFT      (20)
+#define MUX_GPIO_PIN_MASK       (0x1f << MUX_GPIO_PIN_SHIFT)
+#define MUX_REG_SHIFT           (15)
+#define MUX_REG_MASK            (0x1f << MUX_REG_SHIFT)
+#define MUX_FIELD_SHIFT         (13)
+#define MUX_FIELD_MASK          (0x3 << MUX_FIELD_SHIFT)
+#define MUX_PADGRP_SHIFT        (8)
+#define MUX_PADGRP_MASK         (0x1f << MUX_PADGRP_SHIFT)
+#define MUX_PIN_MASK            (0xffffff << 8)
+#define GPIO_PORT_MAX           (3)
+#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
+        (((side) << MUX_SIDE_SHIFT) |             \
+         (gport << MUX_GPIO_PORT_SHIFT) |               \
+         ((gpin) << MUX_GPIO_PIN_SHIFT) |               \
+         ((ctlreg) << MUX_REG_SHIFT) |          \
+         ((ctlfield) << MUX_FIELD_SHIFT) |              \
+         ((padgrp) << MUX_PADGRP_SHIFT))
+#define MUX_MODE_OUT_SHIFT      (4)
+#define MUX_MODE_IN_SHIFT       (0)
+#define MUX_MODE_SHIFT          (0)
+#define MUX_MODE_MASK           (0xff << MUX_MODE_SHIFT)
+#define IOMUX_MODE(pin, mode) \
+        (pin | (mode << MUX_MODE_SHIFT))
+enum iomux_pins {
+        /* AP Side pins */
+        MXC91231_PIN_AP_CLE             = IOMUX_PIN(0, 0,  0,  0, 0, 24),
+        MXC91231_PIN_AP_ALE             = IOMUX_PIN(0, 0,  1,  0, 1, 24),
+        MXC91231_PIN_AP_CE_B            = IOMUX_PIN(0, 0,  2,  0, 2, 24),
+        MXC91231_PIN_AP_RE_B            = IOMUX_PIN(0, 0,  3,  0, 3, 24),
+        MXC91231_PIN_AP_WE_B            = IOMUX_PIN(0, 0,  4,  1, 0, 24),
+        MXC91231_PIN_AP_WP_B            = IOMUX_PIN(0, 0,  5,  1, 1, 24),
+        MXC91231_PIN_AP_BSY_B           = IOMUX_PIN(0, 0,  6,  1, 2, 24),
+        MXC91231_PIN_AP_U1_TXD          = IOMUX_PIN(0, 0,  7,  1, 3, 28),
+        MXC91231_PIN_AP_U1_RXD          = IOMUX_PIN(0, 0,  8,  2, 0, 28),
+        MXC91231_PIN_AP_U1_RTS_B        = IOMUX_PIN(0, 0,  9,  2, 1, 28),
+        MXC91231_PIN_AP_U1_CTS_B        = IOMUX_PIN(0, 0, 10,  2, 2, 28),
+        MXC91231_PIN_AP_AD1_TXD         = IOMUX_PIN(0, 0, 11,  2, 3,  9),
+        MXC91231_PIN_AP_AD1_RXD         = IOMUX_PIN(0, 0, 12,  3, 0,  9),
+        MXC91231_PIN_AP_AD1_TXC         = IOMUX_PIN(0, 0, 13,  3, 1,  9),
+        MXC91231_PIN_AP_AD1_TXFS        = IOMUX_PIN(0, 0, 14,  3, 2,  9),
+        MXC91231_PIN_AP_AD2_TXD         = IOMUX_PIN(0, 0, 15,  3, 3,  9),
+        MXC91231_PIN_AP_AD2_RXD         = IOMUX_PIN(0, 0, 16,  4, 0,  9),
+        MXC91231_PIN_AP_AD2_TXC         = IOMUX_PIN(0, 0, 17,  4, 1,  9),
+        MXC91231_PIN_AP_AD2_TXFS        = IOMUX_PIN(0, 0, 18,  4, 2,  9),
+        MXC91231_PIN_AP_OWDAT           = IOMUX_PIN(0, 0, 19,  4, 3, 28),
+        MXC91231_PIN_AP_IPU_LD17        = IOMUX_PIN(0, 0, 20,  5, 0, 28),
+        MXC91231_PIN_AP_IPU_D3_VSYNC    = IOMUX_PIN(0, 0, 21,  5, 1, 28),
+        MXC91231_PIN_AP_IPU_D3_HSYNC    = IOMUX_PIN(0, 0, 22,  5, 2, 28),
+        MXC91231_PIN_AP_IPU_D3_CLK      = IOMUX_PIN(0, 0, 23,  5, 3, 28),
+        MXC91231_PIN_AP_IPU_D3_DRDY     = IOMUX_PIN(0, 0, 24,  6, 0, 28),
+        MXC91231_PIN_AP_IPU_D3_CONTR    = IOMUX_PIN(0, 0, 25,  6, 1, 28),
+        MXC91231_PIN_AP_IPU_D0_CS       = IOMUX_PIN(0, 0, 26,  6, 2, 28),
+        MXC91231_PIN_AP_IPU_LD16        = IOMUX_PIN(0, 0, 27,  6, 3, 28),
+        MXC91231_PIN_AP_IPU_D2_CS       = IOMUX_PIN(0, 0, 28,  7, 0, 28),
+        MXC91231_PIN_AP_IPU_PAR_RS      = IOMUX_PIN(0, 0, 29,  7, 1, 28),
+        MXC91231_PIN_AP_IPU_D3_PS       = IOMUX_PIN(0, 0, 30,  7, 2, 28),
+        MXC91231_PIN_AP_IPU_D3_CLS      = IOMUX_PIN(0, 0, 31,  7, 3, 28),
+        MXC91231_PIN_AP_IPU_RD          = IOMUX_PIN(0, 1,  0,  8, 0, 28),
+        MXC91231_PIN_AP_IPU_WR          = IOMUX_PIN(0, 1,  1,  8, 1, 28),
+        MXC91231_PIN_AP_IPU_LD0         = IOMUX_PIN(0, 7,  0,  8, 2, 28),
+        MXC91231_PIN_AP_IPU_LD1         = IOMUX_PIN(0, 7,  0,  8, 3, 28),
+        MXC91231_PIN_AP_IPU_LD2         = IOMUX_PIN(0, 7,  0,  9, 0, 28),
+        MXC91231_PIN_AP_IPU_LD3         = IOMUX_PIN(0, 1,  2,  9, 1, 28),
+        MXC91231_PIN_AP_IPU_LD4         = IOMUX_PIN(0, 1,  3,  9, 2, 28),
+        MXC91231_PIN_AP_IPU_LD5         = IOMUX_PIN(0, 1,  4,  9, 3, 28),
+        MXC91231_PIN_AP_IPU_LD6         = IOMUX_PIN(0, 1,  5, 10, 0, 28),
+        MXC91231_PIN_AP_IPU_LD7         = IOMUX_PIN(0, 1,  6, 10, 1, 28),
+        MXC91231_PIN_AP_IPU_LD8         = IOMUX_PIN(0, 1,  7, 10, 2, 28),
+        MXC91231_PIN_AP_IPU_LD9         = IOMUX_PIN(0, 1,  8, 10, 3, 28),
+        MXC91231_PIN_AP_IPU_LD10        = IOMUX_PIN(0, 1,  9, 11, 0, 28),
+        MXC91231_PIN_AP_IPU_LD11        = IOMUX_PIN(0, 1, 10, 11, 1, 28),
+        MXC91231_PIN_AP_IPU_LD12        = IOMUX_PIN(0, 1, 11, 11, 2, 28),
+        MXC91231_PIN_AP_IPU_LD13        = IOMUX_PIN(0, 1, 12, 11, 3, 28),
+        MXC91231_PIN_AP_IPU_LD14        = IOMUX_PIN(0, 1, 13, 12, 0, 28),
+        MXC91231_PIN_AP_IPU_LD15        = IOMUX_PIN(0, 1, 14, 12, 1, 28),
+        MXC91231_PIN_AP_KPROW4          = IOMUX_PIN(0, 7,  0, 12, 2, 10),
+        MXC91231_PIN_AP_KPROW5          = IOMUX_PIN(0, 1, 16, 12, 3, 10),
+        MXC91231_PIN_AP_GPIO_AP_B17     = IOMUX_PIN(0, 1, 17, 13, 0, 10),
+        MXC91231_PIN_AP_GPIO_AP_B18     = IOMUX_PIN(0, 1, 18, 13, 1, 10),
+        MXC91231_PIN_AP_KPCOL3          = IOMUX_PIN(0, 1, 19, 13, 2, 11),
+        MXC91231_PIN_AP_KPCOL4          = IOMUX_PIN(0, 1, 20, 13, 3, 11),
+        MXC91231_PIN_AP_KPCOL5          = IOMUX_PIN(0, 1, 21, 14, 0, 11),
+        MXC91231_PIN_AP_GPIO_AP_B22     = IOMUX_PIN(0, 1, 22, 14, 1, 11),
+        MXC91231_PIN_AP_GPIO_AP_B23     = IOMUX_PIN(0, 1, 23, 14, 2, 11),
+        MXC91231_PIN_AP_CSI_D0          = IOMUX_PIN(0, 1, 24, 14, 3, 21),
+        MXC91231_PIN_AP_CSI_D1          = IOMUX_PIN(0, 1, 25, 15, 0, 21),
+        MXC91231_PIN_AP_CSI_D2          = IOMUX_PIN(0, 1, 26, 15, 1, 21),
+        MXC91231_PIN_AP_CSI_D3          = IOMUX_PIN(0, 1, 27, 15, 2, 21),
+        MXC91231_PIN_AP_CSI_D4          = IOMUX_PIN(0, 1, 28, 15, 3, 21),
+        MXC91231_PIN_AP_CSI_D5          = IOMUX_PIN(0, 1, 29, 16, 0, 21),
+        MXC91231_PIN_AP_CSI_D6          = IOMUX_PIN(0, 1, 30, 16, 1, 21),
+        MXC91231_PIN_AP_CSI_D7          = IOMUX_PIN(0, 1, 31, 16, 2, 21),
+        MXC91231_PIN_AP_CSI_D8          = IOMUX_PIN(0, 2,  0, 16, 3, 21),
+        MXC91231_PIN_AP_CSI_D9          = IOMUX_PIN(0, 2,  1, 17, 0, 21),
+        MXC91231_PIN_AP_CSI_MCLK        = IOMUX_PIN(0, 2,  2, 17, 1, 21),
+        MXC91231_PIN_AP_CSI_VSYNC       = IOMUX_PIN(0, 2,  3, 17, 2, 21),
+        MXC91231_PIN_AP_CSI_HSYNC       = IOMUX_PIN(0, 2,  4, 17, 3, 21),
+        MXC91231_PIN_AP_CSI_PIXCLK      = IOMUX_PIN(0, 2,  5, 18, 0, 21),
+        MXC91231_PIN_AP_I2CLK           = IOMUX_PIN(0, 2,  6, 18, 1, 12),
+        MXC91231_PIN_AP_I2DAT           = IOMUX_PIN(0, 2,  7, 18, 2, 12),
+        MXC91231_PIN_AP_GPIO_AP_C8      = IOMUX_PIN(0, 2,  8, 18, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C9      = IOMUX_PIN(0, 2,  9, 19, 0,  9),
+        MXC91231_PIN_AP_GPIO_AP_C10     = IOMUX_PIN(0, 2, 10, 19, 1,  9),
+        MXC91231_PIN_AP_GPIO_AP_C11     = IOMUX_PIN(0, 2, 11, 19, 2,  9),
+        MXC91231_PIN_AP_GPIO_AP_C12     = IOMUX_PIN(0, 2, 12, 19, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C13     = IOMUX_PIN(0, 2, 13, 20, 0, 28),
+        MXC91231_PIN_AP_GPIO_AP_C14     = IOMUX_PIN(0, 2, 14, 20, 1, 28),
+        MXC91231_PIN_AP_GPIO_AP_C15     = IOMUX_PIN(0, 2, 15, 20, 2,  9),
+        MXC91231_PIN_AP_GPIO_AP_C16     = IOMUX_PIN(0, 2, 16, 20, 3,  9),
+        MXC91231_PIN_AP_GPIO_AP_C17     = IOMUX_PIN(0, 2, 17, 21, 0,  9),
+        MXC91231_PIN_AP_ED_INT0         = IOMUX_PIN(0, 2, 18, 21, 1, 22),
+        MXC91231_PIN_AP_ED_INT1         = IOMUX_PIN(0, 2, 19, 21, 2, 22),
+        MXC91231_PIN_AP_ED_INT2         = IOMUX_PIN(0, 2, 20, 21, 3, 22),
+        MXC91231_PIN_AP_ED_INT3         = IOMUX_PIN(0, 2, 21, 22, 0, 22),
+        MXC91231_PIN_AP_ED_INT4         = IOMUX_PIN(0, 2, 22, 22, 1, 23),
+        MXC91231_PIN_AP_ED_INT5         = IOMUX_PIN(0, 2, 23, 22, 2, 23),
+        MXC91231_PIN_AP_ED_INT6         = IOMUX_PIN(0, 2, 24, 22, 3, 23),
+        MXC91231_PIN_AP_ED_INT7         = IOMUX_PIN(0, 2, 25, 23, 0, 23),
+        MXC91231_PIN_AP_U2_DSR_B        = IOMUX_PIN(0, 2, 26, 23, 1, 28),
+        MXC91231_PIN_AP_U2_RI_B         = IOMUX_PIN(0, 2, 27, 23, 2, 28),
+        MXC91231_PIN_AP_U2_CTS_B        = IOMUX_PIN(0, 2, 28, 23, 3, 28),
+        MXC91231_PIN_AP_U2_DTR_B        = IOMUX_PIN(0, 2, 29, 24, 0, 28),
+        MXC91231_PIN_AP_KPROW0          = IOMUX_PIN(0, 7,  0, 24, 1, 10),
+        MXC91231_PIN_AP_KPROW1          = IOMUX_PIN(0, 1, 15, 24, 2, 10),
+        MXC91231_PIN_AP_KPROW2          = IOMUX_PIN(0, 7,  0, 24, 3, 10),
+        MXC91231_PIN_AP_KPROW3          = IOMUX_PIN(0, 7,  0, 25, 0, 10),
+        MXC91231_PIN_AP_KPCOL0          = IOMUX_PIN(0, 7,  0, 25, 1, 11),
+        MXC91231_PIN_AP_KPCOL1          = IOMUX_PIN(0, 7,  0, 25, 2, 11),
+        MXC91231_PIN_AP_KPCOL2          = IOMUX_PIN(0, 7,  0, 25, 3, 11),
+        /* Shared pins */
+        MXC91231_PIN_SP_U3_TXD          = IOMUX_PIN(1, 3,  0,  0, 0, 28),
+        MXC91231_PIN_SP_U3_RXD          = IOMUX_PIN(1, 3,  1,  0, 1, 28),
+        MXC91231_PIN_SP_U3_RTS_B        = IOMUX_PIN(1, 3,  2,  0, 2, 28),
+        MXC91231_PIN_SP_U3_CTS_B        = IOMUX_PIN(1, 3,  3,  0, 3, 28),
+        MXC91231_PIN_SP_USB_TXOE_B      = IOMUX_PIN(1, 3,  4,  1, 0, 28),
+        MXC91231_PIN_SP_USB_DAT_VP      = IOMUX_PIN(1, 3,  5,  1, 1, 28),
+        MXC91231_PIN_SP_USB_SE0_VM      = IOMUX_PIN(1, 3,  6,  1, 2, 28),
+        MXC91231_PIN_SP_USB_RXD         = IOMUX_PIN(1, 3,  7,  1, 3, 28),
+        MXC91231_PIN_SP_UH2_TXOE_B      = IOMUX_PIN(1, 3,  8,  2, 0, 28),
+        MXC91231_PIN_SP_UH2_SPEED       = IOMUX_PIN(1, 3,  9,  2, 1, 28),
+        MXC91231_PIN_SP_UH2_SUSPEN      = IOMUX_PIN(1, 3, 10,  2, 2, 28),
+        MXC91231_PIN_SP_UH2_TXDP        = IOMUX_PIN(1, 3, 11,  2, 3, 28),
+        MXC91231_PIN_SP_UH2_RXDP        = IOMUX_PIN(1, 3, 12,  3, 0, 28),
+        MXC91231_PIN_SP_UH2_RXDM        = IOMUX_PIN(1, 3, 13,  3, 1, 28),
+        MXC91231_PIN_SP_UH2_OVR         = IOMUX_PIN(1, 3, 14,  3, 2, 28),
+        MXC91231_PIN_SP_UH2_PWR         = IOMUX_PIN(1, 3, 15,  3, 3, 28),
+        MXC91231_PIN_SP_SD1_DAT0        = IOMUX_PIN(1, 3, 16,  4, 0, 25),
+        MXC91231_PIN_SP_SD1_DAT1        = IOMUX_PIN(1, 3, 17,  4, 1, 25),
+        MXC91231_PIN_SP_SD1_DAT2        = IOMUX_PIN(1, 3, 18,  4, 2, 25),
+        MXC91231_PIN_SP_SD1_DAT3        = IOMUX_PIN(1, 3, 19,  4, 3, 25),
+        MXC91231_PIN_SP_SD1_CMD         = IOMUX_PIN(1, 3, 20,  5, 0, 25),
+        MXC91231_PIN_SP_SD1_CLK         = IOMUX_PIN(1, 3, 21,  5, 1, 25),
+        MXC91231_PIN_SP_SD2_DAT0        = IOMUX_PIN(1, 3, 22,  5, 2, 26),
+        MXC91231_PIN_SP_SD2_DAT1        = IOMUX_PIN(1, 3, 23,  5, 3, 26),
+        MXC91231_PIN_SP_SD2_DAT2        = IOMUX_PIN(1, 3, 24,  6, 0, 26),
+        MXC91231_PIN_SP_SD2_DAT3        = IOMUX_PIN(1, 3, 25,  6, 1, 26),
+        MXC91231_PIN_SP_GPIO_SP_A26     = IOMUX_PIN(1, 3, 26,  6, 2, 28),
+        MXC91231_PIN_SP_SPI1_CLK        = IOMUX_PIN(1, 3, 27,  6, 3, 13),
+        MXC91231_PIN_SP_SPI1_MOSI       = IOMUX_PIN(1, 3, 28,  7, 0, 13),
+        MXC91231_PIN_SP_SPI1_MISO       = IOMUX_PIN(1, 3, 29,  7, 1, 13),
+        MXC91231_PIN_SP_SPI1_SS0        = IOMUX_PIN(1, 3, 30,  7, 2, 13),
+        MXC91231_PIN_SP_SPI1_SS1        = IOMUX_PIN(1, 3, 31,  7, 3, 13),
+        MXC91231_PIN_SP_SD2_CMD         = IOMUX_PIN(1, 7,  0,  8, 0, 26),
+        MXC91231_PIN_SP_SD2_CLK         = IOMUX_PIN(1, 7,  0,  8, 1, 26),
+        MXC91231_PIN_SP_SIM1_RST_B      = IOMUX_PIN(1, 2, 30,  8, 2, 28),
+        MXC91231_PIN_SP_SIM1_SVEN       = IOMUX_PIN(1, 7,  0,  8, 3, 28),
+        MXC91231_PIN_SP_SIM1_CLK        = IOMUX_PIN(1, 7,  0,  9, 0, 28),
+        MXC91231_PIN_SP_SIM1_TRXD       = IOMUX_PIN(1, 7,  0,  9, 1, 28),
+        MXC91231_PIN_SP_SIM1_PD         = IOMUX_PIN(1, 2, 31,  9, 2, 28),
+        MXC91231_PIN_SP_UH2_TXDM        = IOMUX_PIN(1, 7,  0,  9, 3, 28),
+        MXC91231_PIN_SP_UH2_RXD         = IOMUX_PIN(1, 7,  0, 10, 0, 28),
+};
+#define PIN_AP_MAX      (104)
+#define PIN_SP_MAX      (41)
+#define PIN_MAX         (PIN_AP_MAX + PIN_SP_MAX)
+/*
+ * Convenience values for use with mxc_iomux_mode()
+ *
+ * Format here is MXC91231_PIN_(pin name)__(function)
+ */
+#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
+#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
+#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
+#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
+        IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
+#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 7cd84547658f..a0fa40265468 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,28 +68,24 @@ struct pad_desc {
 /*
 * Use to set PAD control
 */
-#define PAD_CTL_DRIVE_VOLTAGE_3_3_V     0
-#define PAD_CTL_DRIVE_VOLTAGE_1_8_V     1
-#define PAD_CTL_NO_HYSTERESIS           0
+#define PAD_CTL_DVS                     (1 << 13)
-#define PAD_CTL_HYSTERESIS              1
+#define PAD_CTL_HYS                     (1 << 8)
-#define PAD_CTL_PULL_DISABLED           0x0
+#define PAD_CTL_PKE                     (1 << 7)
-#define PAD_CTL_PULL_KEEPER             0xa
+#define PAD_CTL_PUE                     (1 << 6)
-#define PAD_CTL_PULL_DOWN_100K          0xc
+#define PAD_CTL_PUS_100K_DOWN           (0 << 4)
-#define PAD_CTL_PULL_UP_47K             0xd
+#define PAD_CTL_PUS_47K_UP              (1 << 4)
-#define PAD_CTL_PULL_UP_100K            0xe
+#define PAD_CTL_PUS_100K_UP             (2 << 4)
-#define PAD_CTL_PULL_UP_22K             0xf
+#define PAD_CTL_PUS_22K_UP              (3 << 4)
-#define PAD_CTL_OUTPUT_CMOS             0
+#define PAD_CTL_ODE                     (1 << 3)
-#define PAD_CTL_OUTPUT_OPEN_DRAIN       1
-#define PAD_CTL_DRIVE_STRENGTH_NORM     0
+#define PAD_CTL_DSE_STANDARD            (0 << 1)
-#define PAD_CTL_DRIVE_STRENGTH_HIGH     1
+#define PAD_CTL_DSE_HIGH                (1 << 1)
-#define PAD_CTL_DRIVE_STRENGTH_MAX      2
+#define PAD_CTL_DSE_MAX                 (2 << 1)
-#define PAD_CTL_SLEW_RATE_SLOW          0
+#define PAD_CTL_SRE_FAST                (1 << 0)
-#define PAD_CTL_SLEW_RATE_FAST          1
 /*
 * setups a single pad:
@@ -117,5 +113,10 @@ void mxc_iomux_v3_release_pad(struct pad_desc *pad);
 */
 void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
+/*
+ * Initialise the iomux controller
+ */
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
 #endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
index 171f8adc1109..6d49f8ae3259 100644
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ b/arch/arm/plat-mxc/include/mach/iomux.h
@@ -49,6 +49,9 @@
 #ifdef CONFIG_ARCH_MX2
 # define GPIO_PORT_MAX  5
 #endif
+#ifdef CONFIG_ARCH_MX25
+# define GPIO_PORT_MAX  3
+#endif
 #ifndef GPIO_PORT_MAX
 # error "GPIO config port count unknown!"
@@ -107,6 +110,9 @@
 #include <mach/iomux-mx27.h>
 #endif
 #endif
+#ifdef CONFIG_ARCH_MX25
+#include <mach/iomux-mx25.h>
+#endif
 /* decode irq number to use with IMR(x), ISR(x) and friends */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 518a36504b88..ead9d592168d 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -24,6 +24,10 @@
 #define MXC_GPIO_IRQS           (32 * 6)
 #elif defined CONFIG_ARCH_MX3
 #define MXC_GPIO_IRQS           (32 * 3)
+#elif defined CONFIG_ARCH_MX25
+#define MXC_GPIO_IRQS           (32 * 4)
+#elif defined CONFIG_ARCH_MXC91231
+#define MXC_GPIO_IRQS           (32 * 4)
 #endif
 /*
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 6065e00176ed..d3afafdcc0e5 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -22,6 +22,10 @@
 #endif
 #elif defined CONFIG_ARCH_MX3
 #define PHYS_OFFSET             UL(0x80000000)
+#elif defined CONFIG_ARCH_MX25
+#define PHYS_OFFSET             UL(0x80000000)
+#elif defined CONFIG_ARCH_MXC91231
+#define PHYS_OFFSET             UL(0x90000000)
 #endif
 #if defined(CONFIG_MX1_VIDEO)
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 1000bf330bcd..1b2890a5c452 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -12,10 +12,6 @@
 #ifndef __ASM_ARCH_MXC_MX1_H__
 #define __ASM_ARCH_MXC_MX1_H__
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
 #include <mach/vmalloc.h>
 /*
@@ -138,20 +134,6 @@
 #define GPIO_INT_PORTD          62
 #define WDT_INT                 63
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x1C
-#define GPIO_GDIR               0x00
-#define GPIO_PSR                0x24
-#define GPIO_ICR1               0x28
-#define GPIO_ICR2               0x2C
-#define GPIO_IMR                0x30
-#define GPIO_ISR                0x34
-#define GPIO_INT_LOW_LEV        0x3
-#define GPIO_INT_HIGH_LEV       0x2
-#define GPIO_INT_RISE_EDGE      0x0
-#define GPIO_INT_FALL_EDGE      0x1
-#define GPIO_INT_NONE           0x4
 /* DMA */
 #define DMA_REQ_UART3_T         2
 #define DMA_REQ_UART3_R         3
@@ -179,8 +161,4 @@
 #define DMA_REQ_UART1_T         30
 #define DMA_REQ_UART1_R         31
-/* mandatory for CONFIG_DEBUG_LL */
-#define MXC_LL_UART_PADDR       UART1_BASE_ADDR
-#define MXC_LL_UART_VADDR       IO_ADDRESS(UART1_BASE_ADDR)
 #endif /*  __ASM_ARCH_MXC_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 8b070a041a99..21112c695ec5 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -25,11 +25,6 @@
 #ifndef __ASM_ARCH_MXC_MX21_H__
 #define __ASM_ARCH_MXC_MX21_H__
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
 /* Memory regions and CS */
 #define SDRAM_BASE_ADDR         0xC0000000
 #define CSD1_BASE_ADDR          0xC4000000
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
new file mode 100644
index 000000000000..ec64bd9a8ab1
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -0,0 +1,44 @@
+#ifndef __MACH_MX25_H__
+#define __MACH_MX25_H__
+#define MX25_AIPS1_BASE_ADDR            0x43F00000
+#define MX25_AIPS1_BASE_ADDR_VIRT       0xFC000000
+#define MX25_AIPS1_SIZE                 SZ_1M
+#define MX25_AIPS2_BASE_ADDR            0x53F00000
+#define MX25_AIPS2_BASE_ADDR_VIRT       0xFC200000
+#define MX25_AIPS2_SIZE                 SZ_1M
+#define MX25_AVIC_BASE_ADDR             0x68000000
+#define MX25_AVIC_BASE_ADDR_VIRT        0xFC400000
+#define MX25_AVIC_SIZE                  SZ_1M
+#define MX25_IOMUXC_BASE_ADDR           (MX25_AIPS1_BASE_ADDR + 0xac000)
+#define MX25_CRM_BASE_ADDR              (MX25_AIPS2_BASE_ADDR + 0x80000)
+#define MX25_GPT1_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0x90000)
+#define MX25_WDOG_BASE_ADDR             (MX25_AIPS2_BASE_ADDR + 0xdc000)
+#define MX25_GPIO1_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
+#define MX25_GPIO2_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
+#define MX25_GPIO3_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
+#define MX25_GPIO4_BASE_ADDR_VIRT       (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
+#define MX25_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
+#define MX25_AIPS2_IO_ADDRESS(x)  \
+        (((x) - MX25_AIPS2_BASE_ADDR) + MX25_AIPS2_BASE_ADDR_VIRT)
+#define MX25_AVIC_IO_ADDRESS(x)  \
+        (((x) - MX25_AVIC_BASE_ADDR) + MX25_AVIC_BASE_ADDR_VIRT)
+#define __in_range(addr, name)  ((addr) >= name##_BASE_ADDR && (addr) < name##_BASE_ADDR + name##_SIZE)
+#define MX25_IO_ADDRESS(x)                                      \
+        (void __force __iomem *)                                \
+        (__in_range(x, MX25_AIPS1) ? MX25_AIPS1_IO_ADDRESS(x) : \
+        __in_range(x, MX25_AIPS2) ? MX25_AIPS2_IO_ADDRESS(x) :  \
+        __in_range(x, MX25_AVIC) ? MX25_AVIC_IO_ADDRESS(x) :    \
+        0xDEADBEEF)
+#define UART1_BASE_ADDR                 0x43f90000
+#define UART2_BASE_ADDR                 0x43f94000
+#endif /* __MACH_MX25_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 6e93f2c0b7bb..dc3ad9aa952a 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -24,10 +24,6 @@
 #ifndef __ASM_ARCH_MXC_MX27_H__
 #define __ASM_ARCH_MXC_MX27_H__
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
 /* IRAM */
 #define IRAM_BASE_ADDR          0xFFFF4C00      /* internal ram */
@@ -120,7 +116,4 @@ extern int mx27_revision(void);
 /* Mandatory defines used globally */
-/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
-#define ARCH_NR_GPIOS           (192 + 16)
 #endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index fc40d3ab8c5b..db5d921e0fe6 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -23,10 +23,6 @@
 #ifndef __ASM_ARCH_MXC_MX2x_H__
 #define __ASM_ARCH_MXC_MX2x_H__
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
 /* The following addresses are common between i.MX21 and i.MX27 */
 /* Register offests */
@@ -154,20 +150,6 @@
 #define MXC_INT_GPIO            8
 #define MXC_INT_CSPI3           6
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x1C
-#define GPIO_GDIR               0x00
-#define GPIO_PSR                0x24
-#define GPIO_ICR1               0x28
-#define GPIO_ICR2               0x2C
-#define GPIO_IMR                0x30
-#define GPIO_ISR                0x34
-#define GPIO_INT_LOW_LEV        0x3
-#define GPIO_INT_HIGH_LEV       0x2
-#define GPIO_INT_RISE_EDGE      0x0
-#define GPIO_INT_FALL_EDGE      0x1
-#define GPIO_INT_NONE           0x4
 /* fixed DMA request numbers */
 #define DMA_REQ_CSI_RX          31
 #define DMA_REQ_CSI_STAT        30
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 0b06941b6139..14ac0dcc82f4 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -4,7 +4,7 @@
 #define MX31_IRAM_BASE_ADDR             0x1FFC0000      /* internal ram */
 #define MX31_IRAM_SIZE                  SZ_16K
-#define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
+#define MX31_OTG_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00088000)
 #define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
 #define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
 #define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6465fefb42e3..ab4cfec6c8ab 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -5,6 +5,7 @@
 #define MX35_IRAM_SIZE          SZ_128K
 #define MXC_FEC_BASE_ADDR       0x50038000
+#define MX35_OTG_BASE_ADDR      0x53ff4000
 #define MX35_NFC_BASE_ADDR      0xBB000000
 /*
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index b559a4bb5769..009f4440276b 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -11,10 +11,6 @@
 #ifndef __ASM_ARCH_MXC_MX31_H__
 #define __ASM_ARCH_MXC_MX31_H__
-#ifndef __ASM_ARCH_MXC_HARDWARE_H__
-#error "Do not include directly."
-#endif
 /*
 * MX31 memory map:
 *
@@ -263,25 +259,8 @@
 #define SYSTEM_REV_MIN          CHIP_REV_1_0
 #define SYSTEM_REV_NUM          3
-/* gpio and gpio based interrupt handling */
-#define GPIO_DR                 0x00
-#define GPIO_GDIR               0x04
-#define GPIO_PSR                0x08
-#define GPIO_ICR1               0x0C
-#define GPIO_ICR2               0x10
-#define GPIO_IMR                0x14
-#define GPIO_ISR                0x18
-#define GPIO_INT_LOW_LEV        0x0
-#define GPIO_INT_HIGH_LEV       0x1
-#define GPIO_INT_RISE_EDGE      0x2
-#define GPIO_INT_FALL_EDGE      0x3
-#define GPIO_INT_NONE           0x4
 /* Mandatory defines used globally */
-/* this CPU supports up to 96 GPIOs */
-#define ARCH_NR_GPIOS           96
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
 extern unsigned int system_rev;
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 5fa2a07f4eaf..51990536b845 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -26,9 +26,11 @@
 #define MXC_CPU_MX1             1
 #define MXC_CPU_MX21            21
+#define MXC_CPU_MX25            25
 #define MXC_CPU_MX27            27
 #define MXC_CPU_MX31            31
 #define MXC_CPU_MX35            35
+#define MXC_CPU_MXC91231        91231
 #ifndef __ASSEMBLY__
 extern unsigned int __mxc_cpu_type;
@@ -58,6 +60,18 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx21()          (0)
 #endif
+#ifdef CONFIG_ARCH_MX25
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MX25
+# endif
+# define cpu_is_mx25()          (mxc_cpu_type == MXC_CPU_MX25)
+#else
+# define cpu_is_mx25()          (0)
+#endif
 #ifdef CONFIG_MACH_MX27
 # ifdef mxc_cpu_type
 #  undef mxc_cpu_type
@@ -94,13 +108,25 @@ extern unsigned int __mxc_cpu_type;
 # define cpu_is_mx35()          (0)
 #endif
+#ifdef CONFIG_ARCH_MXC91231
+# ifdef mxc_cpu_type
+#  undef mxc_cpu_type
+#  define mxc_cpu_type __mxc_cpu_type
+# else
+#  define mxc_cpu_type MXC_CPU_MXC91231
+# endif
+# define cpu_is_mxc91231()      (mxc_cpu_type == MXC_CPU_MXC91231)
+#else
+# define cpu_is_mxc91231()      (0)
+#endif
 #if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
 #define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10)
 #define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x4)
 #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8)
 #endif
-#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35())
+#define cpu_is_mx3()    (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
 #define cpu_is_mx2()    (cpu_is_mx21() || cpu_is_mx27())
 #endif /*  __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
new file mode 100644
index 000000000000..81484d1ef232
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -0,0 +1,315 @@
+/*
+ *  Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
+ *    - Platform specific register memory map
+ *
+ *  Copyright 2005-2007 Motorola, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __MACH_MXC91231_H__
+#define __MACH_MXC91231_H__
+/*
+ * L2CC
+ */
+#define MXC91231_L2CC_BASE_ADDR         0x30000000
+#define MXC91231_L2CC_BASE_ADDR_VIRT    0xF9000000
+#define MXC91231_L2CC_SIZE              SZ_64K
+/*
+ * AIPS 1
+ */
+#define MXC91231_AIPS1_BASE_ADDR        0x43F00000
+#define MXC91231_AIPS1_BASE_ADDR_VIRT   0xFC000000
+#define MXC91231_AIPS1_SIZE             SZ_1M
+#define MXC91231_AIPS1_CTRL_BASE_ADDR   MXC91231_AIPS1_BASE_ADDR
+#define MXC91231_MAX_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x04000)
+#define MXC91231_EVTMON_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x08000)
+#define MXC91231_CLKCTL_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
+#define MXC91231_ETB_SLOT4_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x10000)
+#define MXC91231_ETB_SLOT5_BASE_ADDR    (MXC91231_AIPS1_BASE_ADDR + 0x14000)
+#define MXC91231_ECT_CTIO_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0x18000)
+#define MXC91231_I2C_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x80000)
+#define MXC91231_MU_BASE_ADDR           (MXC91231_AIPS1_BASE_ADDR + 0x88000)
+#define MXC91231_UART1_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x90000)
+#define MXC91231_UART2_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x94000)
+#define MXC91231_DSM_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0x98000)
+#define MXC91231_OWIRE_BASE_ADDR        (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
+#define MXC91231_SSI1_BASE_ADDR         (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
+#define MXC91231_KPP_BASE_ADDR          (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
+#define MXC91231_IOMUX_AP_BASE_ADDR     (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
+#define MXC91231_CTI_AP_BASE_ADDR       (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
+/*
+ * AIPS 2
+ */
+#define MXC91231_AIPS2_BASE_ADDR        0x53F00000
+#define MXC91231_AIPS2_BASE_ADDR_VIRT   0xFC100000
+#define MXC91231_AIPS2_SIZE             SZ_1M
+#define MXC91231_GEMK_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
+#define MXC91231_GPT1_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0x90000)
+#define MXC91231_EPIT1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0x94000)
+#define MXC91231_SCC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
+#define MXC91231_RNGA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
+#define MXC91231_IPU_CTRL_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
+#define MXC91231_AUDMUX_BASE_ADDR       (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
+#define MXC91231_EDIO_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
+#define MXC91231_GPIO1_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
+#define MXC91231_GPIO2_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
+#define MXC91231_SDMA_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
+#define MXC91231_RTC_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
+#define MXC91231_WDOG1_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
+#define MXC91231_PWM_BASE_ADDR          (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
+#define MXC91231_GPIO3_AP_BASE_ADDR     (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
+#define MXC91231_WDOG2_BASE_ADDR        (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
+#define MXC91231_RTIC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
+#define MXC91231_LPMC_BASE_ADDR         (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
+/*
+ * SPBA global module 0
+ */
+#define MXC91231_SPBA0_BASE_ADDR        0x50000000
+#define MXC91231_SPBA0_BASE_ADDR_VIRT   0xFC200000
+#define MXC91231_SPBA0_SIZE             SZ_1M
+#define MXC91231_MMC_SDHC1_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x04000)
+#define MXC91231_MMC_SDHC2_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x08000)
+#define MXC91231_UART3_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
+#define MXC91231_CSPI2_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x10000)
+#define MXC91231_SSI2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x14000)
+#define MXC91231_SIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x18000)
+#define MXC91231_IIM_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
+#define MXC91231_CTI_SDMA_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x20000)
+#define MXC91231_USBOTG_CTRL_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x24000)
+#define MXC91231_USBOTG_DATA_BASE_ADDR  (MXC91231_SPBA0_BASE_ADDR + 0x28000)
+#define MXC91231_CSPI1_BASE_ADDR        (MXC91231_SPBA0_BASE_ADDR + 0x30000)
+#define MXC91231_SPBA_CTRL_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
+#define MXC91231_IOMUX_COM_BASE_ADDR    (MXC91231_SPBA0_BASE_ADDR + 0x40000)
+#define MXC91231_CRM_COM_BASE_ADDR      (MXC91231_SPBA0_BASE_ADDR + 0x44000)
+#define MXC91231_CRM_AP_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x48000)
+#define MXC91231_PLL0_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
+#define MXC91231_PLL1_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x50000)
+#define MXC91231_PLL2_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x54000)
+#define MXC91231_GPIO4_SH_BASE_ADDR     (MXC91231_SPBA0_BASE_ADDR + 0x58000)
+#define MXC91231_HAC_BASE_ADDR          (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_SAHARA_BASE_ADDR       (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
+#define MXC91231_PLL3_BASE_ADDR         (MXC91231_SPBA0_BASE_ADDR + 0x60000)
+/*
+ * SPBA global module 1
+ */
+#define MXC91231_SPBA1_BASE_ADDR        0x52000000
+#define MXC91231_SPBA1_BASE_ADDR_VIRT   0xFC300000
+#define MXC91231_SPBA1_SIZE             SZ_1M
+#define MXC91231_MQSPI_BASE_ADDR        (MXC91231_SPBA1_BASE_ADDR + 0x34000)
+#define MXC91231_EL1T_BASE_ADDR         (MXC91231_SPBA1_BASE_ADDR + 0x38000)
+/*!
+ * Defines for SPBA modules
+ */
+#define MXC91231_SPBA_SDHC1             0x04
+#define MXC91231_SPBA_SDHC2             0x08
+#define MXC91231_SPBA_UART3             0x0C
+#define MXC91231_SPBA_CSPI2             0x10
+#define MXC91231_SPBA_SSI2              0x14
+#define MXC91231_SPBA_SIM               0x18
+#define MXC91231_SPBA_IIM               0x1C
+#define MXC91231_SPBA_CTI_SDMA          0x20
+#define MXC91231_SPBA_USBOTG_CTRL_REGS  0x24
+#define MXC91231_SPBA_USBOTG_DATA_REGS  0x28
+#define MXC91231_SPBA_CSPI1             0x30
+#define MXC91231_SPBA_MQSPI             0x34
+#define MXC91231_SPBA_EL1T              0x38
+#define MXC91231_SPBA_IOMUX             0x40
+#define MXC91231_SPBA_CRM_COM           0x44
+#define MXC91231_SPBA_CRM_AP            0x48
+#define MXC91231_SPBA_PLL0              0x4C
+#define MXC91231_SPBA_PLL1              0x50
+#define MXC91231_SPBA_PLL2              0x54
+#define MXC91231_SPBA_GPIO4             0x58
+#define MXC91231_SPBA_SAHARA            0x5C
+/*
+ * ROMP and AVIC
+ */
+#define MXC91231_ROMP_BASE_ADDR         0x60000000
+#define MXC91231_ROMP_BASE_ADDR_VIRT    0xFC400000
+#define MXC91231_ROMP_SIZE              SZ_64K
+#define MXC91231_AVIC_BASE_ADDR         0x68000000
+#define MXC91231_AVIC_BASE_ADDR_VIRT    0xFC410000
+#define MXC91231_AVIC_SIZE              SZ_64K
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define MXC91231_X_MEMC_BASE_ADDR       0xB8000000
+#define MXC91231_X_MEMC_BASE_ADDR_VIRT  0xFC420000
+#define MXC91231_X_MEMC_SIZE            SZ_64K
+#define MXC91231_NFC_BASE_ADDR          (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
+#define MXC91231_ESDCTL_BASE_ADDR       (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
+#define MXC91231_WEIM_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
+#define MXC91231_M3IF_BASE_ADDR         (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
+#define MXC91231_EMI_CTL_BASE_ADDR      (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
+/*
+ * Memory regions and CS
+ * CPLD is connected on CS4
+ * CS5 is TP1021 or it is not connected
+ * */
+#define MXC91231_FB_RAM_BASE_ADDR       0x78000000
+#define MXC91231_FB_RAM_SIZE            SZ_256K
+#define MXC91231_CSD0_BASE_ADDR         0x80000000
+#define MXC91231_CSD1_BASE_ADDR         0x90000000
+#define MXC91231_CS0_BASE_ADDR          0xA0000000
+#define MXC91231_CS1_BASE_ADDR          0xA8000000
+#define MXC91231_CS2_BASE_ADDR          0xB0000000
+#define MXC91231_CS3_BASE_ADDR          0xB2000000
+#define MXC91231_CS4_BASE_ADDR          0xB4000000
+#define MXC91231_CS5_BASE_ADDR          0xB6000000
+/* Is given address belongs to the specified memory region? */
+#define ADDRESS_IN_REGION(addr, start, size) \
+        (((addr) >= (start)) && ((addr) < (start)+(size)))
+/* Is given address belongs to the specified named `module'? */
+#define MXC91231_IS_MODULE(addr, module) \
+        ADDRESS_IN_REGION(addr, MXC91231_ ## module ## _BASE_ADDR, \
+                                MXC91231_ ## module ## _SIZE)
+/*
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define MXC91231_IO_ADDRESS(x) \
+        (void __iomem *) \
+        (MXC91231_IS_MODULE(x, L2CC) ? MXC91231_L2CC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS1) ? MXC91231_AIPS1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AIPS2) ? MXC91231_AIPS2_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA0) ? MXC91231_SPBA0_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, SPBA1) ? MXC91231_SPBA1_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, ROMP) ? MXC91231_ROMP_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, AVIC) ? MXC91231_AVIC_IO_ADDRESS(x) : \
+         MXC91231_IS_MODULE(x, X_MEMC) ? MXC91231_X_MEMC_IO_ADDRESS(x) : \
+         0xDEADBEEF)
+/*
+ * define the address mapping macros: in physical address order
+ */
+#define MXC91231_L2CC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_L2CC_BASE_ADDR) + MXC91231_L2CC_BASE_ADDR_VIRT)
+#define MXC91231_AIPS1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS1_BASE_ADDR) + MXC91231_AIPS1_BASE_ADDR_VIRT)
+#define MXC91231_SPBA0_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA0_BASE_ADDR) + MXC91231_SPBA0_BASE_ADDR_VIRT)
+#define MXC91231_SPBA1_IO_ADDRESS(x)  \
+        (((x) - MXC91231_SPBA1_BASE_ADDR) + MXC91231_SPBA1_BASE_ADDR_VIRT)
+#define MXC91231_AIPS2_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AIPS2_BASE_ADDR) + MXC91231_AIPS2_BASE_ADDR_VIRT)
+#define MXC91231_ROMP_IO_ADDRESS(x)  \
+        (((x) - MXC91231_ROMP_BASE_ADDR) + MXC91231_ROMP_BASE_ADDR_VIRT)
+#define MXC91231_AVIC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_AVIC_BASE_ADDR) + MXC91231_AVIC_BASE_ADDR_VIRT)
+#define MXC91231_X_MEMC_IO_ADDRESS(x)  \
+        (((x) - MXC91231_X_MEMC_BASE_ADDR) + MXC91231_X_MEMC_BASE_ADDR_VIRT)
+/*
+ * Interrupt numbers
+ */
+#define MXC91231_INT_GPIO3              0
+#define MXC91231_INT_EL1T_CI            1
+#define MXC91231_INT_EL1T_RFCI          2
+#define MXC91231_INT_EL1T_RFI           3
+#define MXC91231_INT_EL1T_MCU           4
+#define MXC91231_INT_EL1T_IPI           5
+#define MXC91231_INT_MU_GEN             6
+#define MXC91231_INT_GPIO4              7
+#define MXC91231_INT_MMC_SDHC2          8
+#define MXC91231_INT_MMC_SDHC1          9
+#define MXC91231_INT_I2C                10
+#define MXC91231_INT_SSI2               11
+#define MXC91231_INT_SSI1               12
+#define MXC91231_INT_CSPI2              13
+#define MXC91231_INT_CSPI1              14
+#define MXC91231_INT_RTIC               15
+#define MXC91231_INT_SAHARA             15
+#define MXC91231_INT_HAC                15
+#define MXC91231_INT_UART3_RX           16
+#define MXC91231_INT_UART3_TX           17
+#define MXC91231_INT_UART3_MINT         18
+#define MXC91231_INT_ECT                19
+#define MXC91231_INT_SIM_IPB            20
+#define MXC91231_INT_SIM_DATA           21
+#define MXC91231_INT_RNGA               22
+#define MXC91231_INT_DSM_AP             23
+#define MXC91231_INT_KPP                24
+#define MXC91231_INT_RTC                25
+#define MXC91231_INT_PWM                26
+#define MXC91231_INT_GEMK_AP            27
+#define MXC91231_INT_EPIT               28
+#define MXC91231_INT_GPT                29
+#define MXC91231_INT_UART2_RX           30
+#define MXC91231_INT_UART2_TX           31
+#define MXC91231_INT_UART2_MINT         32
+#define MXC91231_INT_NANDFC             33
+#define MXC91231_INT_SDMA               34
+#define MXC91231_INT_USB_WAKEUP         35
+#define MXC91231_INT_USB_SOF            36
+#define MXC91231_INT_PMU_EVTMON         37
+#define MXC91231_INT_USB_FUNC           38
+#define MXC91231_INT_USB_DMA            39
+#define MXC91231_INT_USB_CTRL           40
+#define MXC91231_INT_IPU_ERR            41
+#define MXC91231_INT_IPU_SYN            42
+#define MXC91231_INT_UART1_RX           43
+#define MXC91231_INT_UART1_TX           44
+#define MXC91231_INT_UART1_MINT         45
+#define MXC91231_INT_IIM                46
+#define MXC91231_INT_MU_RX_OR           47
+#define MXC91231_INT_MU_TX_OR           48
+#define MXC91231_INT_SCC_SCM            49
+#define MXC91231_INT_SCC_SMN            50
+#define MXC91231_INT_GPIO2              51
+#define MXC91231_INT_GPIO1              52
+#define MXC91231_INT_MQSPI1             53
+#define MXC91231_INT_MQSPI2             54
+#define MXC91231_INT_WDOG2              55
+#define MXC91231_INT_EXT_INT7           56
+#define MXC91231_INT_EXT_INT6           57
+#define MXC91231_INT_EXT_INT5           58
+#define MXC91231_INT_EXT_INT4           59
+#define MXC91231_INT_EXT_INT3           60
+#define MXC91231_INT_EXT_INT2           61
+#define MXC91231_INT_EXT_INT1           62
+#define MXC91231_INT_EXT_INT0           63
+#define MXC91231_MAX_INT_LINES          63
+#define MXC91231_MAX_EXT_LINES          8
+#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index e56241af870e..ef00199568de 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -21,8 +21,18 @@
 #ifndef __ASM_ARCH_MXC_SYSTEM_H__
 #define __ASM_ARCH_MXC_SYSTEM_H__
+#include <mach/hardware.h>
+#include <mach/common.h>
 static inline void arch_idle(void)
 {
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                /* Need this to set DSM low-power mode */
+                mxc91231_prepare_idle();
+        }
+#endif
        cpu_do_idle();
 }
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 07b4a73c9d2f..527a6c24788e 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,6 +26,10 @@
 #define CLOCK_TICK_RATE         13300000
 #elif defined CONFIG_ARCH_MX3
 #define CLOCK_TICK_RATE         16625000
+#elif defined CONFIG_ARCH_MX25
+#define CLOCK_TICK_RATE         16000000
+#elif defined CONFIG_ARCH_MXC91231
+#define CLOCK_TICK_RATE         13000000
 #endif
 #endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index de6fe0365982..082a3908256b 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -26,8 +26,11 @@
 #define __MXC_BOOT_UNCOMPRESS
 #include <mach/hardware.h>
+#include <asm/mach-types.h>
-#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+static unsigned long uart_base;
+#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
 #define USR2 0x98
 #define USR2_TXFE (1<<14)
@@ -46,19 +49,10 @@
 static void putc(int ch)
 {
-        static unsigned long serial_port = 0;
+        if (!uart_base)
+                return;
-        if (unlikely(serial_port == 0)) {
+        if (!(UART(UCR1) & UCR1_UARTEN))
-                do {
+                return;
-                        serial_port = UART1_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        serial_port = UART2_BASE_ADDR;
-                        if (UART(UCR1) & UCR1_UARTEN)
-                                break;
-                        return;
-                } while (0);
-        }
        while (!(UART(USR2) & USR2_TXFE))
                barrier();
@@ -68,11 +62,49 @@ static void putc(int ch)
 #define flush() do { } while (0)
-/*
+#define MX1_UART1_BASE_ADDR     0x00206000
- * nothing to do
+#define MX25_UART1_BASE_ADDR    0x43f90000
- */
+#define MX2X_UART1_BASE_ADDR    0x1000a000
-#define arch_decomp_setup()
+#define MX3X_UART1_BASE_ADDR    0x43F90000
+#define MX3X_UART2_BASE_ADDR    0x43F94000
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        switch (arch_id) {
+        case MACH_TYPE_MX1ADS:
+        case MACH_TYPE_SCB9328:
+                uart_base = MX1_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX25_3DS:
+                uart_base = MX25_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_IMX27LITE:
+        case MACH_TYPE_MX27_3DS:
+        case MACH_TYPE_MX27ADS:
+        case MACH_TYPE_PCM038:
+        case MACH_TYPE_MX21ADS:
+                uart_base = MX2X_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MX31LITE:
+        case MACH_TYPE_ARMADILLO5X0:
+        case MACH_TYPE_MX31MOBOARD:
+        case MACH_TYPE_QONG:
+        case MACH_TYPE_MX31_3DS:
+        case MACH_TYPE_PCM037:
+        case MACH_TYPE_MX31ADS:
+        case MACH_TYPE_MX35_3DS:
+        case MACH_TYPE_PCM043:
+                uart_base = MX3X_UART1_BASE_ADDR;
+                break;
+        case MACH_TYPE_MAGX_ZN5:
+                uart_base = MX3X_UART2_BASE_ADDR;
+                break;
+        default:
+                break;
+        }
+}
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
 #define arch_decomp_wdog()
 #endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index 77a078f9513f..851ca99bf1b1 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -29,7 +29,7 @@
 #include <asm/mach/map.h>
 #include <mach/iomux-v3.h>
-#define IOMUX_BASE      IO_ADDRESS(IOMUXC_BASE_ADDR)
+static void __iomem *base;
 static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
@@ -45,14 +45,14 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
        if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
                return -EBUSY;
        if (pad->mux_ctrl_ofs)
-                __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs);
+                __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
        if (pad->select_input_ofs)
                __raw_writel(pad->select_input,
-                                IOMUX_BASE + pad->select_input_ofs);
+                                base + pad->select_input_ofs);
-        if (!(pad->pad_ctrl & NO_PAD_CTRL))
+        if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
-                __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs);
+                __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
        return 0;
 }
 EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
@@ -96,3 +96,8 @@ void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
        }
 }
 EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
+void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
+{
+        base = iomux_v3_base;
+}
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/irq.c
index 8aee76304f8f..778ddfe57d89 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/irq.c
@@ -44,7 +44,7 @@
 #define AVIC_FIPNDH             0x60    /* fast int pending high */
 #define AVIC_FIPNDL             0x64    /* fast int pending low */
-static void __iomem *avic_base;
+void __iomem *avic_base;
 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -113,11 +113,11 @@ static struct irq_chip mxc_avic_chip = {
 * interrupts. It registers the interrupt enable and disable functions
 * to the kernel for each interrupt source.
 */
-void __init mxc_init_irq(void)
+void __init mxc_init_irq(void __iomem *irqbase)
 {
        int i;
-        avic_base = IO_ADDRESS(AVIC_BASE_ADDR);
+        avic_base = irqbase;
        /* put the AVIC into the reset value with
         * all interrupts disabled
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index ae34198a79dd..5cdbd605ac05 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -32,6 +32,7 @@
 #define MX3_PWMPR                 0x10    /* PWM Period Register */
 #define MX3_PWMCR_PRESCALER(x)    (((x - 1) & 0xFFF) << 4)
 #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
+#define MX3_PWMCR_CLKSRC_IPG      (1 << 16)
 #define MX3_PWMCR_EN              (1 << 0)
@@ -55,9 +56,11 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
        if (pwm == NULL || period_ns == 0 || duty_ns > period_ns)
                return -EINVAL;
-        if (cpu_is_mx27() || cpu_is_mx3()) {
+        if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx25()) {
                unsigned long long c;
                unsigned long period_cycles, duty_cycles, prescale;
+                u32 cr;
                c = clk_get_rate(pwm->clk);
                c = c * period_ns;
                do_div(c, 1000000000);
@@ -72,9 +75,15 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns)
                writel(duty_cycles, pwm->mmio_base + MX3_PWMSAR);
                writel(period_cycles, pwm->mmio_base + MX3_PWMPR);
-                writel(MX3_PWMCR_PRESCALER(prescale - 1) |
-                        MX3_PWMCR_CLKSRC_IPG_HIGH | MX3_PWMCR_EN,
+                cr = MX3_PWMCR_PRESCALER(prescale) | MX3_PWMCR_EN;
-                        pwm->mmio_base + MX3_PWMCR);
+                if (cpu_is_mx25())
+                        cr |= MX3_PWMCR_CLKSRC_IPG;
+                else
+                        cr |= MX3_PWMCR_CLKSRC_IPG_HIGH;
+                writel(cr, pwm->mmio_base + MX3_PWMCR);
        } else if (cpu_is_mx1() || cpu_is_mx21()) {
                /* The PWM subsystem allows for exact frequencies. However,
                 * I cannot connect a scope on my device to the PWM line and
@@ -118,6 +127,8 @@ EXPORT_SYMBOL(pwm_enable);
 void pwm_disable(struct pwm_device *pwm)
 {
+        writel(0, pwm->mmio_base + MX3_PWMCR);
        if (pwm->clk_enabled) {
                clk_disable(pwm->clk);
                pwm->clk_enabled = 0;
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 79c37577c916..97f42799fa58 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -27,32 +27,38 @@
 #include <linux/delay.h>
 #include <mach/hardware.h>
+#include <mach/common.h>
 #include <asm/proc-fns.h>
 #include <asm/system.h>
-#ifdef CONFIG_ARCH_MX1
+static void __iomem *wdog_base;
-#define WDOG_WCR_REG            IO_ADDRESS(WDT_BASE_ADDR)
-#define WDOG_WCR_ENABLE         (1 << 0)
-#else
-#define WDOG_WCR_REG            IO_ADDRESS(WDOG_BASE_ADDR)
-#define WDOG_WCR_ENABLE         (1 << 2)
-#endif
 /*
 * Reset the system. It is called by machine_restart().
 */
 void arch_reset(char mode, const char *cmd)
 {
-        if (!cpu_is_mx1()) {
+        unsigned int wcr_enable;
+#ifdef CONFIG_ARCH_MXC91231
+        if (cpu_is_mxc91231()) {
+                mxc91231_arch_reset(mode, cmd);
+                return;
+        }
+#endif
+        if (cpu_is_mx1()) {
+                wcr_enable = (1 << 0);
+        } else {
                struct clk *clk;
                clk = clk_get_sys("imx-wdt.0", NULL);
                if (!IS_ERR(clk))
                        clk_enable(clk);
+                wcr_enable = (1 << 2);
        }
        /* Assert SRS signal */
-        __raw_writew(WDOG_WCR_ENABLE, WDOG_WCR_REG);
+        __raw_writew(wcr_enable, wdog_base);
        /* wait for reset to assert... */
        mdelay(500);
@@ -65,3 +71,8 @@ void arch_reset(char mode, const char *cmd)
        /* we'll take a jump through zero as a poor second */
        cpu_reset(0);
 }
+void mxc_arch_reset_init(void __iomem *base)
+{
+        wdog_base = base;
+}
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 88fb3a57e029..844567ee35fe 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -47,7 +47,7 @@
 #define MX2_TSTAT_CAPT          (1 << 1)
 #define MX2_TSTAT_COMP          (1 << 0)
-/* MX31, MX35 */
+/* MX31, MX35, MX25, MXC91231 */
 #define MX3_TCTL_WAITEN         (1 << 3)
 #define MX3_TCTL_CLK_IPG        (1 << 6)
 #define MX3_TCTL_FRR            (1 << 9)
@@ -66,7 +66,7 @@ static inline void gpt_irq_disable(void)
 {
        unsigned int tmp;
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                __raw_writel(0, timer_base + MX3_IR);
        else {
                tmp = __raw_readl(timer_base + MXC_TCTL);
@@ -76,7 +76,7 @@ static inline void gpt_irq_disable(void)
 static inline void gpt_irq_enable(void)
 {
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                __raw_writel(1<<0, timer_base + MX3_IR);
        else {
                __raw_writel(__raw_readl(timer_base + MXC_TCTL) | MX1_2_TCTL_IRQEN,
@@ -90,7 +90,7 @@ static void gpt_irq_acknowledge(void)
                __raw_writel(0, timer_base + MX1_2_TSTAT);
        if (cpu_is_mx2())
                __raw_writel(MX2_TSTAT_CAPT | MX2_TSTAT_COMP, timer_base + MX1_2_TSTAT);
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                __raw_writel(MX3_TSTAT_OF1, timer_base + MX3_TSTAT);
 }
@@ -117,7 +117,7 @@ static int __init mxc_clocksource_init(struct clk *timer_clk)
 {
        unsigned int c = clk_get_rate(timer_clk);
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                clocksource_mxc.read = mx3_get_cycles;
        clocksource_mxc.mult = clocksource_hz2mult(c,
@@ -180,7 +180,7 @@ static void mxc_set_mode(enum clock_event_mode mode,
        if (mode != clockevent_mode) {
                /* Set event time into far-far future */
-                if (cpu_is_mx3())
+                if (cpu_is_mx3() || cpu_is_mx25())
                        __raw_writel(__raw_readl(timer_base + MX3_TCN) - 3,
                                        timer_base + MX3_TCMP);
                else
@@ -233,7 +233,7 @@ static irqreturn_t mxc_timer_interrupt(int irq, void *dev_id)
        struct clock_event_device *evt = &clockevent_mxc;
        uint32_t tstat;
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                tstat = __raw_readl(timer_base + MX3_TSTAT);
        else
                tstat = __raw_readl(timer_base + MX1_2_TSTAT);
@@ -264,7 +264,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 {
        unsigned int c = clk_get_rate(timer_clk);
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                clockevent_mxc.set_next_event = mx3_set_next_event;
        clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
@@ -281,30 +281,13 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
        return 0;
 }
-void __init mxc_timer_init(struct clk *timer_clk)
+void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
        uint32_t tctl_val;
-        int irq;
        clk_enable(timer_clk);
-        if (cpu_is_mx1()) {
+        timer_base = base;
-#ifdef CONFIG_ARCH_MX1
-                timer_base = IO_ADDRESS(TIM1_BASE_ADDR);
-                irq = TIM1_INT;
-#endif
-        } else if (cpu_is_mx2()) {
-#ifdef CONFIG_ARCH_MX2
-                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
-                irq = MXC_INT_GPT1;
-#endif
-        } else if (cpu_is_mx3()) {
-#ifdef CONFIG_ARCH_MX3
-                timer_base = IO_ADDRESS(GPT1_BASE_ADDR);
-                irq = MXC_INT_GPT;
-#endif
-        } else
-                BUG();
        /*
         * Initialise to a known state (all timers off, and timing reset)
@@ -313,7 +296,7 @@ void __init mxc_timer_init(struct clk *timer_clk)
        __raw_writel(0, timer_base + MXC_TCTL);
        __raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
-        if (cpu_is_mx3())
+        if (cpu_is_mx3() || cpu_is_mx25())
                tctl_val = MX3_TCTL_CLK_IPG | MX3_TCTL_FRR | MX3_TCTL_WAITEN | MXC_TCTL_TEN;
        else
                tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
diff --git a/arch/arm/plat-omap/debug-leds.c b/arch/arm/plat-omap/debug-leds.c
index be4eefda4767..9395898dd49a 100644
--- a/arch/arm/plat-omap/debug-leds.c
+++ b/arch/arm/plat-omap/debug-leds.c
@@ -281,24 +281,27 @@ static int /* __init */ fpga_probe(struct platform_device *pdev)
        return 0;
 }
-static int fpga_suspend_late(struct platform_device *pdev, pm_message_t mesg)
+static int fpga_suspend_noirq(struct device *dev)
 {
        __raw_writew(~0, &fpga->leds);
        return 0;
 }
-static int fpga_resume_early(struct platform_device *pdev)
+static int fpga_resume_noirq(struct device *dev)
 {
        __raw_writew(~hw_led_state, &fpga->leds);
        return 0;
 }
+static struct dev_pm_ops fpga_dev_pm_ops = {
+        .suspend_noirq = fpga_suspend_noirq,
+        .resume_noirq = fpga_resume_noirq,
+};
 static struct platform_driver led_driver = {
        .driver.name    = "omap_dbg_led",
+        .driver.pm      = &fpga_dev_pm_ops,
        .probe          = fpga_probe,
-        .suspend_late   = fpga_suspend_late,
-        .resume_early   = fpga_resume_early,
 };
 static int __init fpga_init(void)
diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
index e3ac94f09006..9b00f4cbc903 100644
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -1127,6 +1127,11 @@ int omap_dma_running(void)
 void omap_dma_link_lch(int lch_head, int lch_queue)
 {
        if (omap_dma_in_1510_mode()) {
+                if (lch_head == lch_queue) {
+                        dma_write(dma_read(CCR(lch_head)) | (3 << 8),
+                                                                CCR(lch_head));
+                        return;
+                }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
                BUG();
                return;
@@ -1149,6 +1154,11 @@ EXPORT_SYMBOL(omap_dma_link_lch);
 void omap_dma_unlink_lch(int lch_head, int lch_queue)
 {
        if (omap_dma_in_1510_mode()) {
+                if (lch_head == lch_queue) {
+                        dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
+                                                                CCR(lch_head));
+                        return;
+                }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
                BUG();
                return;
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 9298bc0ab171..176c86e5531d 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -138,6 +138,32 @@
 #define OMAP24XX_GPIO_CLEARDATAOUT      0x0090
 #define OMAP24XX_GPIO_SETDATAOUT        0x0094
+#define OMAP4_GPIO_REVISION             0x0000
+#define OMAP4_GPIO_SYSCONFIG            0x0010
+#define OMAP4_GPIO_EOI                  0x0020
+#define OMAP4_GPIO_IRQSTATUSRAW0        0x0024
+#define OMAP4_GPIO_IRQSTATUSRAW1        0x0028
+#define OMAP4_GPIO_IRQSTATUS0           0x002c
+#define OMAP4_GPIO_IRQSTATUS1           0x0030
+#define OMAP4_GPIO_IRQSTATUSSET0        0x0034
+#define OMAP4_GPIO_IRQSTATUSSET1        0x0038
+#define OMAP4_GPIO_IRQSTATUSCLR0        0x003c
+#define OMAP4_GPIO_IRQSTATUSCLR1        0x0040
+#define OMAP4_GPIO_IRQWAKEN0            0x0044
+#define OMAP4_GPIO_IRQWAKEN1            0x0048
+#define OMAP4_GPIO_SYSSTATUS            0x0104
+#define OMAP4_GPIO_CTRL                 0x0130
+#define OMAP4_GPIO_OE                   0x0134
+#define OMAP4_GPIO_DATAIN               0x0138
+#define OMAP4_GPIO_DATAOUT              0x013c
+#define OMAP4_GPIO_LEVELDETECT0         0x0140
+#define OMAP4_GPIO_LEVELDETECT1         0x0144
+#define OMAP4_GPIO_RISINGDETECT         0x0148
+#define OMAP4_GPIO_FALLINGDETECT        0x014c
+#define OMAP4_GPIO_DEBOUNCENABLE        0x0150
+#define OMAP4_GPIO_DEBOUNCINGTIME       0x0154
+#define OMAP4_GPIO_CLEARDATAOUT         0x0190
+#define OMAP4_GPIO_SETDATAOUT           0x0194
 /*
 * omap34xx specific GPIO registers
 */
@@ -386,12 +412,16 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
                reg += OMAP850_GPIO_DIR_CONTROL;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_OE;
                break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_OE;
+                break;
+#endif
        default:
                WARN_ON(1);
                return;
@@ -459,8 +489,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                        l &= ~(1 << gpio);
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                if (enable)
                        reg += OMAP24XX_GPIO_SETDATAOUT;
@@ -469,6 +498,15 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
                l = 1 << gpio;
                break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP4_GPIO_SETDATAOUT;
+                else
+                        reg += OMAP4_GPIO_CLEARDATAOUT;
+                l = 1 << gpio;
+                break;
+#endif
        default:
                WARN_ON(1);
                return;
@@ -509,12 +547,16 @@ static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
                reg += OMAP850_GPIO_DATA_INPUT;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_DATAIN;
                break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_DATAIN;
+                break;
+#endif
        default:
                return -EINVAL;
        }
@@ -589,7 +631,11 @@ void omap_set_gpio_debounce(int gpio, int enable)
        bank = get_gpio_bank(gpio);
        reg = bank->base;
+#ifdef CONFIG_ARCH_OMAP4
+        reg += OMAP4_GPIO_DEBOUNCENABLE;
+#else
        reg += OMAP24XX_GPIO_DEBOUNCE_EN;
+#endif
        spin_lock_irqsave(&bank->lock, flags);
        val = __raw_readl(reg);
@@ -626,7 +672,11 @@ void omap_set_gpio_debounce_time(int gpio, int enc_time)
        reg = bank->base;
        enc_time &= 0xff;
+#ifdef CONFIG_ARCH_OMAP4
+        reg += OMAP4_GPIO_DEBOUNCINGTIME;
+#else
        reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
+#endif
        __raw_writel(enc_time, reg);
 }
 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
@@ -638,23 +688,46 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
 {
        void __iomem *base = bank->base;
        u32 gpio_bit = 1 << gpio;
+        u32 val;
-        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+        if (cpu_is_omap44xx()) {
-                trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
-        MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
-                trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
-        MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
-                trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
-        MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
-                trigger & IRQ_TYPE_EDGE_FALLING);
+                MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        } else {
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_LOW);
+                MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
+                        trigger & IRQ_TYPE_LEVEL_HIGH);
+                MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_RISING);
+                MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
+                        trigger & IRQ_TYPE_EDGE_FALLING);
+        }
        if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
-                if (trigger != 0)
+                if (cpu_is_omap44xx()) {
-                        __raw_writel(1 << gpio, bank->base
+                        if (trigger != 0)
+                                __raw_writel(1 << gpio, bank->base+
+                                                OMAP4_GPIO_IRQWAKEN0);
+                        else {
+                                val = __raw_readl(bank->base +
+                                                        OMAP4_GPIO_IRQWAKEN0);
+                                __raw_writel(val & (~(1 << gpio)), bank->base +
+                                                         OMAP4_GPIO_IRQWAKEN0);
+                        }
+                } else {
+                        if (trigger != 0)
+                                __raw_writel(1 << gpio, bank->base
                                        + OMAP24XX_GPIO_SETWKUENA);
-                else
+                        else
-                        __raw_writel(1 << gpio, bank->base
+                                __raw_writel(1 << gpio, bank->base
                                        + OMAP24XX_GPIO_CLEARWKUENA);
+                }
        } else {
                if (trigger != 0)
                        bank->enabled_non_wakeup_gpios |= gpio_bit;
@@ -662,9 +735,15 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
        }
-        bank->level_mask =
+        if (cpu_is_omap44xx()) {
-                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+                bank->level_mask =
-                __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
+        } else {
+                bank->level_mask =
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+                        __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+        }
 }
 #endif
@@ -828,12 +907,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
                reg += OMAP850_GPIO_INT_STATUS;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_IRQSTATUS1;
                break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_IRQSTATUS0;
+                break;
+#endif
        default:
                WARN_ON(1);
                return;
@@ -843,12 +926,16 @@ static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
        /* Workaround for clearing DSP GPIO interrupts to allow retention */
 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
-        if (cpu_is_omap24xx() || cpu_is_omap34xx())
+#endif
+#if defined(CONFIG_ARCH_OMAP4)
+        reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
+#endif
+        if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                __raw_writel(gpio_mask, reg);
        /* Flush posted write for the irq status to avoid spurious interrupts */
        __raw_readl(reg);
-#endif
+        }
 }
 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@ -898,13 +985,18 @@ static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
                inv = 1;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_IRQENABLE1;
                mask = 0xffffffff;
                break;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        case METHOD_GPIO_24XX:
+                reg += OMAP4_GPIO_IRQSTATUSSET0;
+                mask = 0xffffffff;
+                break;
+#endif
        default:
                WARN_ON(1);
                return 0;
@@ -972,8 +1064,7 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                        l |= gpio_mask;
                break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                defined(CONFIG_ARCH_OMAP4)
        case METHOD_GPIO_24XX:
                if (enable)
                        reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@ -982,6 +1073,15 @@ static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enab
                l = gpio_mask;
                break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+        case METHOD_GPIO_24XX:
+                if (enable)
+                        reg += OMAP4_GPIO_IRQSTATUSSET0;
+                else
+                        reg += OMAP4_GPIO_IRQSTATUSCLR0;
+                l = gpio_mask;
+                break;
+#endif
        default:
                WARN_ON(1);
                return;
@@ -1157,11 +1257,14 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
        if (bank->method == METHOD_GPIO_850)
                isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                                defined(CONFIG_ARCH_OMAP4)
        if (bank->method == METHOD_GPIO_24XX)
                isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
 #endif
+#if defined(CONFIG_ARCH_OMAP4)
+        if (bank->method == METHOD_GPIO_24XX)
+                isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
+#endif
        while(1) {
                u32 isr_saved, level_mask = 0;
                u32 enabled;
@@ -1315,8 +1418,9 @@ static struct irq_chip mpuio_irq_chip = {
 #include <linux/platform_device.h>
-static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
+static int omap_mpuio_suspend_noirq(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
        struct gpio_bank        *bank = platform_get_drvdata(pdev);
        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
        unsigned long           flags;
@@ -1329,8 +1433,9 @@ static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t me
        return 0;
 }
-static int omap_mpuio_resume_early(struct platform_device *pdev)
+static int omap_mpuio_resume_noirq(struct device *dev)
 {
+        struct platform_device *pdev = to_platform_device(dev);
        struct gpio_bank        *bank = platform_get_drvdata(pdev);
        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
        unsigned long           flags;
@@ -1342,14 +1447,18 @@ static int omap_mpuio_resume_early(struct platform_device *pdev)
        return 0;
 }
+static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
+        .suspend_noirq = omap_mpuio_suspend_noirq,
+        .resume_noirq = omap_mpuio_resume_noirq,
+};
 /* use platform_driver for this, now that there's no longer any
 * point to sys_device (other than not disturbing old code).
 */
 static struct platform_driver omap_mpuio_driver = {
-        .suspend_late   = omap_mpuio_suspend_late,
-        .resume_early   = omap_mpuio_resume_early,
        .driver         = {
                .name   = "mpuio",
+                .pm     = &omap_mpuio_dev_pm_ops,
        },
 };
@@ -1638,7 +1747,7 @@ static int __init _omap_gpio_init(void)
                gpio_bank_count = OMAP34XX_NR_GPIOS;
                gpio_bank = gpio_bank_44xx;
-                rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
+                rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
                printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
                        (rev >> 4) & 0x0f, rev & 0x0f);
        }
@@ -1672,7 +1781,16 @@ static int __init _omap_gpio_init(void)
                        static const u32 non_wakeup_gpios[] = {
                                0xe203ffc0, 0x08700040
                        };
+                if (cpu_is_omap44xx()) {
+                        __raw_writel(0xffffffff, bank->base +
+                                                OMAP4_GPIO_IRQSTATUSCLR0);
+                        __raw_writew(0x0015, bank->base +
+                                                OMAP4_GPIO_SYSCONFIG);
+                        __raw_writel(0x00000000, bank->base +
+                                                 OMAP4_GPIO_DEBOUNCENABLE);
+                        /* Initialize interface clock ungated, module enabled */
+                        __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
+                } else {
                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
                        __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
@@ -1680,12 +1798,12 @@ static int __init _omap_gpio_init(void)
                        /* Initialize interface clock ungated, module enabled */
                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
+                }
                        if (i < ARRAY_SIZE(non_wakeup_gpios))
                                bank->non_wakeup_gpios = non_wakeup_gpios[i];
                        gpio_count = 32;
                }
 #endif
                /* REVISIT eventually switch from OMAP-specific gpio structs
                 * over to the generic ones
                 */
@@ -1771,14 +1889,20 @@ static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                        break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                                defined(CONFIG_ARCH_OMAP4)
                case METHOD_GPIO_24XX:
                        wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                        break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_24XX:
+                        wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
                default:
                        continue;
                }
@@ -1813,13 +1937,18 @@ static int omap_gpio_resume(struct sys_device *dev)
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                        break;
 #endif
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        defined(CONFIG_ARCH_OMAP4)
                case METHOD_GPIO_24XX:
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                        break;
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                case METHOD_GPIO_24XX:
+                        wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
+                        break;
+#endif
                default:
                        continue;
                }
@@ -1863,21 +1992,29 @@ void omap2_gpio_prepare_for_retention(void)
                if (!(bank->enabled_non_wakeup_gpios))
                        continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                                defined(CONFIG_ARCH_OMAP4)
                bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
                l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                bank->saved_datain = __raw_readl(bank->base +
+                                                        OMAP4_GPIO_DATAIN);
+                l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
+                l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
+#endif
                bank->saved_fallingdetect = l1;
                bank->saved_risingdetect = l2;
                l1 &= ~bank->enabled_non_wakeup_gpios;
                l2 &= ~bank->enabled_non_wakeup_gpios;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        defined(CONFIG_ARCH_OMAP4)
                __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
+                __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
+#endif
                c++;
        }
        if (!c) {
@@ -1899,27 +2036,29 @@ void omap2_gpio_resume_after_retention(void)
                if (!(bank->enabled_non_wakeup_gpios))
                        continue;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        defined(CONFIG_ARCH_OMAP4)
                __raw_writel(bank->saved_fallingdetect,
                                 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                __raw_writel(bank->saved_risingdetect,
                                 bank->base + OMAP24XX_GPIO_RISINGDETECT);
+                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
+#endif
+#ifdef CONFIG_ARCH_OMAP4
+                __raw_writel(bank->saved_fallingdetect,
+                                 bank->base + OMAP4_GPIO_FALLINGDETECT);
+                __raw_writel(bank->saved_risingdetect,
+                                 bank->base + OMAP4_GPIO_RISINGDETECT);
+                l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
 #endif
                /* Check if any of the non-wakeup interrupt GPIOs have changed
                 * state.  If so, generate an IRQ by software.  This is
                 * horribly racy, but it's the best we can do to work around
                 * this silicon bug. */
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
-                        defined(CONFIG_ARCH_OMAP4)
-                l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
-#endif
                l ^= bank->saved_datain;
                l &= bank->non_wakeup_gpios;
                if (l) {
                        u32 old0, old1;
-#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
-                        defined(CONFIG_ARCH_OMAP4)
                        old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                        old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
                        __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
@@ -1927,6 +2066,20 @@ void omap2_gpio_resume_after_retention(void)
                        __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                        __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 #endif
+#ifdef CONFIG_ARCH_OMAP4
+                        old0 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        old1 = __raw_readl(bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                        __raw_writel(old0 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        __raw_writel(old1 | l, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+                        __raw_writel(old0, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT0);
+                        __raw_writel(old1, bank->base +
+                                                OMAP4_GPIO_LEVELDETECT1);
+#endif
                }
        }
diff --git a/arch/arm/plat-omap/include/mach/dma.h b/arch/arm/plat-omap/include/mach/dma.h
index 7b939cc01962..72f680b7180d 100644
--- a/arch/arm/plat-omap/include/mach/dma.h
+++ b/arch/arm/plat-omap/include/mach/dma.h
@@ -122,6 +122,11 @@
 #define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
 #define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
+/* Additional registers available on OMAP4 */
+#define OMAP_DMA4_CDP(n)                (0x60 * (n) + 0xd0)
+#define OMAP_DMA4_CNDP(n)               (0x60 * (n) + 0xd4)
+#define OMAP_DMA4_CCDN(n)               (0x60 * (n) + 0xd8)
 /* Dummy defines to keep multi-omap compiles happy */
 #define OMAP1_DMA_REVISION              0
 #define OMAP1_DMA_IRQSTATUS_L0          0
@@ -311,6 +316,89 @@
 #define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
 #define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
+/* DMA request lines for 44xx */
+#define OMAP44XX_DMA_DSS_DISPC_REQ      6       /* S_DMA_5 */
+#define OMAP44XX_DMA_SYS_REQ2           7       /* S_DMA_6 */
+#define OMAP44XX_DMA_ISS_REQ1           9       /* S_DMA_8 */
+#define OMAP44XX_DMA_ISS_REQ2           10      /* S_DMA_9 */
+#define OMAP44XX_DMA_ISS_REQ3           12      /* S_DMA_11 */
+#define OMAP44XX_DMA_ISS_REQ4           13      /* S_DMA_12 */
+#define OMAP44XX_DMA_DSS_RFBI_REQ       14      /* S_DMA_13 */
+#define OMAP44XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
+#define OMAP44XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
+#define OMAP44XX_DMA_MCBSP2_TX          17      /* S_DMA_16 */
+#define OMAP44XX_DMA_MCBSP2_RX          18      /* S_DMA_17 */
+#define OMAP44XX_DMA_MCBSP3_TX          19      /* S_DMA_18 */
+#define OMAP44XX_DMA_MCBSP3_RX          20      /* S_DMA_19 */
+#define OMAP44XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
+#define OMAP44XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
+#define OMAP44XX_DMA_I2C3_TX            25      /* S_DMA_24 */
+#define OMAP44XX_DMA_I2C3_RX            26      /* S_DMA_25 */
+#define OMAP44XX_DMA_I2C1_TX            27      /* S_DMA_26 */
+#define OMAP44XX_DMA_I2C1_RX            28      /* S_DMA_27 */
+#define OMAP44XX_DMA_I2C2_TX            29      /* S_DMA_28 */
+#define OMAP44XX_DMA_I2C2_RX            30      /* S_DMA_29 */
+#define OMAP44XX_DMA_MCBSP4_TX          31      /* S_DMA_30 */
+#define OMAP44XX_DMA_MCBSP4_RX          32      /* S_DMA_31 */
+#define OMAP44XX_DMA_MCBSP1_TX          33      /* S_DMA_32 */
+#define OMAP44XX_DMA_MCBSP1_RX          34      /* S_DMA_33 */
+#define OMAP44XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
+#define OMAP44XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
+#define OMAP44XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
+#define OMAP44XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
+#define OMAP44XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
+#define OMAP44XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
+#define OMAP44XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
+#define OMAP44XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
+#define OMAP44XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
+#define OMAP44XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
+#define OMAP44XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
+#define OMAP44XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
+#define OMAP44XX_DMA_MMC2_TX            47      /* S_DMA_46 */
+#define OMAP44XX_DMA_MMC2_RX            48      /* S_DMA_47 */
+#define OMAP44XX_DMA_UART1_TX           49      /* S_DMA_48 */
+#define OMAP44XX_DMA_UART1_RX           50      /* S_DMA_49 */
+#define OMAP44XX_DMA_UART2_TX           51      /* S_DMA_50 */
+#define OMAP44XX_DMA_UART2_RX           52      /* S_DMA_51 */
+#define OMAP44XX_DMA_UART3_TX           53      /* S_DMA_52 */
+#define OMAP44XX_DMA_UART3_RX           54      /* S_DMA_53 */
+#define OMAP44XX_DMA_UART4_TX           55      /* S_DMA_54 */
+#define OMAP44XX_DMA_UART4_RX           56      /* S_DMA_55 */
+#define OMAP44XX_DMA_MMC4_TX            57      /* S_DMA_56 */
+#define OMAP44XX_DMA_MMC4_RX            58      /* S_DMA_57 */
+#define OMAP44XX_DMA_MMC5_TX            59      /* S_DMA_58 */
+#define OMAP44XX_DMA_MMC5_RX            60      /* S_DMA_59 */
+#define OMAP44XX_DMA_MMC1_TX            61      /* S_DMA_60 */
+#define OMAP44XX_DMA_MMC1_RX            62      /* S_DMA_61 */
+#define OMAP44XX_DMA_SYS_REQ3           64      /* S_DMA_63 */
+#define OMAP44XX_DMA_MCPDM_UP           65      /* S_DMA_64 */
+#define OMAP44XX_DMA_MCPDM_DL           66      /* S_DMA_65 */
+#define OMAP44XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
+#define OMAP44XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ0      72      /* S_DMA_71 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ1      73      /* S_DMA_72 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ2      74      /* S_DMA_73 */
+#define OMAP44XX_DMA_DSS_DSI1_REQ3      75      /* S_DMA_74 */
+#define OMAP44XX_DMA_DSS_HDMI_REQ       76      /* S_DMA_75 */
+#define OMAP44XX_DMA_MMC3_TX            77      /* S_DMA_76 */
+#define OMAP44XX_DMA_MMC3_RX            78      /* S_DMA_77 */
+#define OMAP44XX_DMA_USIM_TX            79      /* S_DMA_78 */
+#define OMAP44XX_DMA_USIM_RX            80      /* S_DMA_79 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ0      81      /* S_DMA_80 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ1      82      /* S_DMA_81 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ2      83      /* S_DMA_82 */
+#define OMAP44XX_DMA_DSS_DSI2_REQ3      84      /* S_DMA_83 */
+#define OMAP44XX_DMA_ABE_REQ0           101     /* S_DMA_100 */
+#define OMAP44XX_DMA_ABE_REQ1           102     /* S_DMA_101 */
+#define OMAP44XX_DMA_ABE_REQ2           103     /* S_DMA_102 */
+#define OMAP44XX_DMA_ABE_REQ3           104     /* S_DMA_103 */
+#define OMAP44XX_DMA_ABE_REQ4           105     /* S_DMA_104 */
+#define OMAP44XX_DMA_ABE_REQ5           106     /* S_DMA_105 */
+#define OMAP44XX_DMA_ABE_REQ6           107     /* S_DMA_106 */
+#define OMAP44XX_DMA_ABE_REQ7           108     /* S_DMA_107 */
+#define OMAP44XX_DMA_I2C4_TX            124     /* S_DMA_123 */
+#define OMAP44XX_DMA_I2C4_RX            125     /* S_DMA_124 */
 /*----------------------------------------------------------------------------*/
 /* Hardware registers for LCD DMA */
diff --git a/arch/arm/plat-omap/include/mach/mcbsp.h b/arch/arm/plat-omap/include/mach/mcbsp.h
index bb154ea76769..e0d6eca222cc 100644
--- a/arch/arm/plat-omap/include/mach/mcbsp.h
+++ b/arch/arm/plat-omap/include/mach/mcbsp.h
@@ -53,6 +53,11 @@
 #define OMAP34XX_MCBSP4_BASE    0x49026000
 #define OMAP34XX_MCBSP5_BASE    0x48096000
+#define OMAP44XX_MCBSP1_BASE    0x49022000
+#define OMAP44XX_MCBSP2_BASE    0x49024000
+#define OMAP44XX_MCBSP3_BASE    0x49026000
+#define OMAP44XX_MCBSP4_BASE    0x48074000
 #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
 #define OMAP_MCBSP_REG_DRR2     0x00
@@ -98,7 +103,8 @@
 #define AUDIO_DMA_TX            OMAP_DMA_MCBSP1_TX
 #define AUDIO_DMA_RX            OMAP_DMA_MCBSP1_RX
-#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
+#elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
+        defined(CONFIG_ARCH_OMAP4)
 #define OMAP_MCBSP_REG_DRR2     0x00
 #define OMAP_MCBSP_REG_DRR1     0x04
@@ -134,6 +140,11 @@
 #define OMAP_MCBSP_REG_XCERG    0x74
 #define OMAP_MCBSP_REG_XCERH    0x78
 #define OMAP_MCBSP_REG_SYSCON   0x8C
+#define OMAP_MCBSP_REG_THRSH2   0x90
+#define OMAP_MCBSP_REG_THRSH1   0x94
+#define OMAP_MCBSP_REG_IRQST    0xA0
+#define OMAP_MCBSP_REG_IRQEN    0xA4
+#define OMAP_MCBSP_REG_WAKEUPEN 0xA8
 #define OMAP_MCBSP_REG_XCCR     0xAC
 #define OMAP_MCBSP_REG_RCCR     0xB0
@@ -249,8 +260,27 @@
 #define RDISABLE                0x0001
 /********************** McBSP SYSCONFIG bit definitions ********************/
+#define CLOCKACTIVITY(value)    ((value)<<8)
+#define SIDLEMODE(value)        ((value)<<3)
+#define ENAWAKEUP               0x0004
 #define SOFTRST                 0x0002
+/********************** McBSP DMA operating modes **************************/
+#define MCBSP_DMA_MODE_ELEMENT          0
+#define MCBSP_DMA_MODE_THRESHOLD        1
+#define MCBSP_DMA_MODE_FRAME            2
+/********************** McBSP WAKEUPEN bit definitions *********************/
+#define XEMPTYEOFEN             0x4000
+#define XRDYEN                  0x0400
+#define XEOFEN                  0x0200
+#define XFSXEN                  0x0100
+#define XSYNCERREN              0x0080
+#define RRDYEN                  0x0008
+#define REOFEN                  0x0004
+#define RFSREN                  0x0002
+#define RSYNCERREN              0x0001
 /* we don't do multichannel for now */
 struct omap_mcbsp_reg_cfg {
        u16 spcr2;
@@ -344,6 +374,9 @@ struct omap_mcbsp_platform_data {
        u8 dma_rx_sync, dma_tx_sync;
        u16 rx_irq, tx_irq;
        struct omap_mcbsp_ops *ops;
+#ifdef CONFIG_ARCH_OMAP34XX
+        u16 buffer_size;
+#endif
 };
 struct omap_mcbsp {
@@ -377,6 +410,11 @@ struct omap_mcbsp {
        struct omap_mcbsp_platform_data *pdata;
        struct clk *iclk;
        struct clk *fclk;
+#ifdef CONFIG_ARCH_OMAP34XX
+        int dma_op_mode;
+        u16 max_tx_thres;
+        u16 max_rx_thres;
+#endif
 };
 extern struct omap_mcbsp **mcbsp_ptr;
 extern int omap_mcbsp_count;
@@ -385,10 +423,25 @@ int omap_mcbsp_init(void);
 void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
                                        int size);
 void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
+#ifdef CONFIG_ARCH_OMAP34XX
+void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
+void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
+u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
+u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
+int omap_mcbsp_get_dma_op_mode(unsigned int id);
+#else
+static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
+{ }
+static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
+{ }
+static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
+static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
+static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
+#endif
 int omap_mcbsp_request(unsigned int id);
 void omap_mcbsp_free(unsigned int id);
-void omap_mcbsp_start(unsigned int id);
+void omap_mcbsp_start(unsigned int id, int tx, int rx);
-void omap_mcbsp_stop(unsigned int id);
+void omap_mcbsp_stop(unsigned int id, int tx, int rx);
 void omap_mcbsp_xmit_word(unsigned int id, u32 word);
 u32 omap_mcbsp_recv_word(unsigned int id);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index efa0e0111f38..88ac9768f1c1 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -191,13 +191,177 @@ void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg *config)
        OMAP_MCBSP_WRITE(io_base, MCR2, config->mcr2);
        OMAP_MCBSP_WRITE(io_base, MCR1, config->mcr1);
        OMAP_MCBSP_WRITE(io_base, PCR0, config->pcr0);
-        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+        if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                OMAP_MCBSP_WRITE(io_base, XCCR, config->xccr);
                OMAP_MCBSP_WRITE(io_base, RCCR, config->rccr);
        }
 }
 EXPORT_SYMBOL(omap_mcbsp_config);
+#ifdef CONFIG_ARCH_OMAP34XX
+/*
+ * omap_mcbsp_set_tx_threshold configures how to deal
+ * with transmit threshold. the threshold value and handler can be
+ * configure in here.
+ */
+void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
+{
+        struct omap_mcbsp *mcbsp;
+        void __iomem *io_base;
+        if (!cpu_is_omap34xx())
+                return;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        io_base = mcbsp->io_base;
+        OMAP_MCBSP_WRITE(io_base, THRSH2, threshold);
+}
+EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold);
+/*
+ * omap_mcbsp_set_rx_threshold configures how to deal
+ * with receive threshold. the threshold value and handler can be
+ * configure in here.
+ */
+void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
+{
+        struct omap_mcbsp *mcbsp;
+        void __iomem *io_base;
+        if (!cpu_is_omap34xx())
+                return;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        io_base = mcbsp->io_base;
+        OMAP_MCBSP_WRITE(io_base, THRSH1, threshold);
+}
+EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold);
+/*
+ * omap_mcbsp_get_max_tx_thres just return the current configured
+ * maximum threshold for transmission
+ */
+u16 omap_mcbsp_get_max_tx_threshold(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        return mcbsp->max_tx_thres;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold);
+/*
+ * omap_mcbsp_get_max_rx_thres just return the current configured
+ * maximum threshold for reception
+ */
+u16 omap_mcbsp_get_max_rx_threshold(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        return mcbsp->max_rx_thres;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold);
+/*
+ * omap_mcbsp_get_dma_op_mode just return the current configured
+ * operating mode for the mcbsp channel
+ */
+int omap_mcbsp_get_dma_op_mode(unsigned int id)
+{
+        struct omap_mcbsp *mcbsp;
+        int dma_op_mode;
+        if (!omap_mcbsp_check_valid_id(id)) {
+                printk(KERN_ERR "%s: Invalid id (%u)\n", __func__, id + 1);
+                return -ENODEV;
+        }
+        mcbsp = id_to_mcbsp_ptr(id);
+        spin_lock_irq(&mcbsp->lock);
+        dma_op_mode = mcbsp->dma_op_mode;
+        spin_unlock_irq(&mcbsp->lock);
+        return dma_op_mode;
+}
+EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode);
+static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp)
+{
+        /*
+         * Enable wakup behavior, smart idle and all wakeups
+         * REVISIT: some wakeups may be unnecessary
+         */
+        if (cpu_is_omap34xx()) {
+                u16 syscon;
+                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
+                spin_lock_irq(&mcbsp->lock);
+                if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
+                        syscon |= (ENAWAKEUP | SIDLEMODE(0x02) |
+                                        CLOCKACTIVITY(0x02));
+                        OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN,
+                                        XRDYEN | RRDYEN);
+                } else {
+                        syscon |= SIDLEMODE(0x01);
+                }
+                spin_unlock_irq(&mcbsp->lock);
+                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+        }
+}
+static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp)
+{
+        /*
+         * Disable wakup behavior, smart idle and all wakeups
+         */
+        if (cpu_is_omap34xx()) {
+                u16 syscon;
+                syscon = OMAP_MCBSP_READ(mcbsp->io_base, SYSCON);
+                syscon &= ~(ENAWAKEUP | SIDLEMODE(0x03) | CLOCKACTIVITY(0x03));
+                /*
+                 * HW bug workaround - If no_idle mode is taken, we need to
+                 * go to smart_idle before going to always_idle, or the
+                 * device will not hit retention anymore.
+                 */
+                syscon |= SIDLEMODE(0x02);
+                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                syscon &= ~(SIDLEMODE(0x03));
+                OMAP_MCBSP_WRITE(mcbsp->io_base, SYSCON, syscon);
+                OMAP_MCBSP_WRITE(mcbsp->io_base, WAKEUPEN, 0);
+        }
+}
+#else
+static inline void omap34xx_mcbsp_request(struct omap_mcbsp *mcbsp) {}
+static inline void omap34xx_mcbsp_free(struct omap_mcbsp *mcbsp) {}
+#endif
 /*
 * We can choose between IRQ based or polled IO.
 * This needs to be called before omap_mcbsp_request().
@@ -257,6 +421,9 @@ int omap_mcbsp_request(unsigned int id)
        clk_enable(mcbsp->iclk);
        clk_enable(mcbsp->fclk);
+        /* Do procedure specific to omap34xx arch, if applicable */
+        omap34xx_mcbsp_request(mcbsp);
        /*
         * Make sure that transmitter, receiver and sample-rate generator are
         * not running before activating IRQs.
@@ -305,6 +472,9 @@ void omap_mcbsp_free(unsigned int id)
        if (mcbsp->pdata && mcbsp->pdata->ops && mcbsp->pdata->ops->free)
                mcbsp->pdata->ops->free(id);
+        /* Do procedure specific to omap34xx arch, if applicable */
+        omap34xx_mcbsp_free(mcbsp);
        clk_disable(mcbsp->fclk);
        clk_disable(mcbsp->iclk);
@@ -328,14 +498,15 @@ void omap_mcbsp_free(unsigned int id)
 EXPORT_SYMBOL(omap_mcbsp_free);
 /*
- * Here we start the McBSP, by enabling the sample
+ * Here we start the McBSP, by enabling transmitter, receiver or both.
- * generator, both transmitter and receivers,
+ * If no transmitter or receiver is active prior calling, then sample-rate
- * and the frame sync.
+ * generator and frame sync are started.
 */
-void omap_mcbsp_start(unsigned int id)
+void omap_mcbsp_start(unsigned int id, int tx, int rx)
 {
        struct omap_mcbsp *mcbsp;
        void __iomem *io_base;
+        int idle;
        u16 w;
        if (!omap_mcbsp_check_valid_id(id)) {
@@ -348,32 +519,58 @@ void omap_mcbsp_start(unsigned int id)
        mcbsp->rx_word_length = (OMAP_MCBSP_READ(io_base, RCR1) >> 5) & 0x7;
        mcbsp->tx_word_length = (OMAP_MCBSP_READ(io_base, XCR1) >> 5) & 0x7;
-        /* Start the sample generator */
+        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
+                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+        if (idle) {
+                /* Start the sample generator */
+                w = OMAP_MCBSP_READ(io_base, SPCR2);
+                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 6));
+        }
        /* Enable transmitter and receiver */
+        tx &= 1;
        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | 1);
+        OMAP_MCBSP_WRITE(io_base, SPCR2, w | tx);
+        rx &= 1;
        w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w | 1);
+        OMAP_MCBSP_WRITE(io_base, SPCR1, w | rx);
-        udelay(100);
+        /*
+         * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
+         * REVISIT: 100us may give enough time for two CLKSRG, however
+         * due to some unknown PM related, clock gating etc. reason it
+         * is now at 500us.
+         */
+        udelay(500);
-        /* Start frame sync */
+        if (idle) {
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
+                /* Start frame sync */
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+                w = OMAP_MCBSP_READ(io_base, SPCR2);
+                OMAP_MCBSP_WRITE(io_base, SPCR2, w | (1 << 7));
+        }
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+                /* Release the transmitter and receiver */
+                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w &= ~(tx ? XDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, XCCR, w);
+                w = OMAP_MCBSP_READ(io_base, RCCR);
+                w &= ~(rx ? RDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+        }
        /* Dump McBSP Regs */
        omap_mcbsp_dump_reg(id);
 }
 EXPORT_SYMBOL(omap_mcbsp_start);
-void omap_mcbsp_stop(unsigned int id)
+void omap_mcbsp_stop(unsigned int id, int tx, int rx)
 {
        struct omap_mcbsp *mcbsp;
        void __iomem *io_base;
+        int idle;
        u16 w;
        if (!omap_mcbsp_check_valid_id(id)) {
@@ -385,16 +582,33 @@ void omap_mcbsp_stop(unsigned int id)
        io_base = mcbsp->io_base;
        /* Reset transmitter */
+        tx &= 1;
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+                w = OMAP_MCBSP_READ(io_base, XCCR);
+                w |= (tx ? XDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, XCCR, w);
+        }
        w = OMAP_MCBSP_READ(io_base, SPCR2);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1));
+        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~tx);
        /* Reset receiver */
+        rx &= 1;
+        if (cpu_is_omap2430() || cpu_is_omap34xx()) {
+                w = OMAP_MCBSP_READ(io_base, RCCR);
+                w |= (tx ? RDISABLE : 0);
+                OMAP_MCBSP_WRITE(io_base, RCCR, w);
+        }
        w = OMAP_MCBSP_READ(io_base, SPCR1);
-        OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~(1));
+        OMAP_MCBSP_WRITE(io_base, SPCR1, w & ~rx);
-        /* Reset the sample rate generator */
+        idle = !((OMAP_MCBSP_READ(io_base, SPCR2) |
-        w = OMAP_MCBSP_READ(io_base, SPCR2);
+                  OMAP_MCBSP_READ(io_base, SPCR1)) & 1);
-        OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+        if (idle) {
+                /* Reset the sample rate generator */
+                w = OMAP_MCBSP_READ(io_base, SPCR2);
+                OMAP_MCBSP_WRITE(io_base, SPCR2, w & ~(1 << 6));
+        }
 }
 EXPORT_SYMBOL(omap_mcbsp_stop);
@@ -883,6 +1097,149 @@ void omap_mcbsp_set_spi_mode(unsigned int id,
 }
 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
+#ifdef CONFIG_ARCH_OMAP34XX
+#define max_thres(m)                    (mcbsp->pdata->buffer_size)
+#define valid_threshold(m, val)         ((val) <= max_thres(m))
+#define THRESHOLD_PROP_BUILDER(prop)                                    \
+static ssize_t prop##_show(struct device *dev,                          \
+                        struct device_attribute *attr, char *buf)       \
+{                                                                       \
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
+                                                                        \
+        return sprintf(buf, "%u\n", mcbsp->prop);                       \
+}                                                                       \
+                                                                        \
+static ssize_t prop##_store(struct device *dev,                         \
+                                struct device_attribute *attr,          \
+                                const char *buf, size_t size)           \
+{                                                                       \
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);                \
+        unsigned long val;                                              \
+        int status;                                                     \
+                                                                        \
+        status = strict_strtoul(buf, 0, &val);                          \
+        if (status)                                                     \
+                return status;                                          \
+                                                                        \
+        if (!valid_threshold(mcbsp, val))                               \
+                return -EDOM;                                           \
+                                                                        \
+        mcbsp->prop = val;                                              \
+        return size;                                                    \
+}                                                                       \
+                                                                        \
+static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
+THRESHOLD_PROP_BUILDER(max_tx_thres);
+THRESHOLD_PROP_BUILDER(max_rx_thres);
+static const char *dma_op_modes[] = {
+        "element", "threshold", "frame",
+};
+static ssize_t dma_op_mode_show(struct device *dev,
+                        struct device_attribute *attr, char *buf)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        int dma_op_mode, i = 0;
+        ssize_t len = 0;
+        const char * const *s;
+        spin_lock_irq(&mcbsp->lock);
+        dma_op_mode = mcbsp->dma_op_mode;
+        spin_unlock_irq(&mcbsp->lock);
+        for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++) {
+                if (dma_op_mode == i)
+                        len += sprintf(buf + len, "[%s] ", *s);
+                else
+                        len += sprintf(buf + len, "%s ", *s);
+        }
+        len += sprintf(buf + len, "\n");
+        return len;
+}
+static ssize_t dma_op_mode_store(struct device *dev,
+                                struct device_attribute *attr,
+                                const char *buf, size_t size)
+{
+        struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
+        const char * const *s;
+        int i = 0;
+        for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
+                if (sysfs_streq(buf, *s))
+                        break;
+        if (i == ARRAY_SIZE(dma_op_modes))
+                return -EINVAL;
+        spin_lock_irq(&mcbsp->lock);
+        if (!mcbsp->free) {
+                size = -EBUSY;
+                goto unlock;
+        }
+        mcbsp->dma_op_mode = i;
+unlock:
+        spin_unlock_irq(&mcbsp->lock);
+        return size;
+}
+static DEVICE_ATTR(dma_op_mode, 0644, dma_op_mode_show, dma_op_mode_store);
+static const struct attribute *additional_attrs[] = {
+        &dev_attr_max_tx_thres.attr,
+        &dev_attr_max_rx_thres.attr,
+        &dev_attr_dma_op_mode.attr,
+        NULL,
+};
+static const struct attribute_group additional_attr_group = {
+        .attrs = (struct attribute **)additional_attrs,
+};
+static inline int __devinit omap_additional_add(struct device *dev)
+{
+        return sysfs_create_group(&dev->kobj, &additional_attr_group);
+}
+static inline void __devexit omap_additional_remove(struct device *dev)
+{
+        sysfs_remove_group(&dev->kobj, &additional_attr_group);
+}
+static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp)
+{
+        mcbsp->dma_op_mode = MCBSP_DMA_MODE_ELEMENT;
+        if (cpu_is_omap34xx()) {
+                mcbsp->max_tx_thres = max_thres(mcbsp);
+                mcbsp->max_rx_thres = max_thres(mcbsp);
+                /*
+                 * REVISIT: Set dmap_op_mode to THRESHOLD as default
+                 * for mcbsp2 instances.
+                 */
+                if (omap_additional_add(mcbsp->dev))
+                        dev_warn(mcbsp->dev,
+                                "Unable to create additional controls\n");
+        } else {
+                mcbsp->max_tx_thres = -EINVAL;
+                mcbsp->max_rx_thres = -EINVAL;
+        }
+}
+static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp)
+{
+        if (cpu_is_omap34xx())
+                omap_additional_remove(mcbsp->dev);
+}
+#else
+static inline void __devinit omap34xx_device_init(struct omap_mcbsp *mcbsp) {}
+static inline void __devexit omap34xx_device_exit(struct omap_mcbsp *mcbsp) {}
+#endif /* CONFIG_ARCH_OMAP34XX */
 /*
 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
 * 730 has only 2 McBSP, and both of them are MPU peripherals.
@@ -953,6 +1310,10 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
        mcbsp->dev = &pdev->dev;
        mcbsp_ptr[id] = mcbsp;
        platform_set_drvdata(pdev, mcbsp);
+        /* Initialize mcbsp properties for OMAP34XX if needed / applicable */
+        omap34xx_device_init(mcbsp);
        return 0;
 err_fclk:
@@ -976,6 +1337,8 @@ static int __devexit omap_mcbsp_remove(struct platform_device *pdev)
                                mcbsp->pdata->ops->free)
                        mcbsp->pdata->ops->free(mcbsp->id);
+                omap34xx_device_exit(mcbsp);
                clk_disable(mcbsp->fclk);
                clk_disable(mcbsp->iclk);
                clk_put(mcbsp->fclk);
diff --git a/arch/arm/plat-s3c/Kconfig b/arch/arm/plat-s3c/Kconfig
index 935c7558469b..8931c5f0e46b 100644
--- a/arch/arm/plat-s3c/Kconfig
+++ b/arch/arm/plat-s3c/Kconfig
@@ -198,4 +198,9 @@ config S3C_DEV_USB_HSOTG
        help
          Compile in platform device definition for USB high-speed OtG
+config S3C_DEV_NAND
+        bool
+        help
+          Compile in platform device definition for NAND controller
 endif
diff --git a/arch/arm/plat-s3c/Makefile b/arch/arm/plat-s3c/Makefile
index 0761766b1833..3c09109e9e84 100644
--- a/arch/arm/plat-s3c/Makefile
+++ b/arch/arm/plat-s3c/Makefile
@@ -28,13 +28,17 @@ obj-$(CONFIG_PM)		+= pm.o
 obj-$(CONFIG_PM)                += pm-gpio.o
 obj-$(CONFIG_S3C2410_PM_CHECK)  += pm-check.o
+# PWM support
+obj-$(CONFIG_HAVE_PWM)          += pwm.o
 # devices
 obj-$(CONFIG_S3C_DEV_HSMMC)     += dev-hsmmc.o
 obj-$(CONFIG_S3C_DEV_HSMMC1)    += dev-hsmmc1.o
 obj-y                           += dev-i2c0.o
 obj-$(CONFIG_S3C_DEV_I2C1)      += dev-i2c1.o
-obj-$(CONFIG_SND_S3C64XX_SOC_I2S)       += dev-audio.o
 obj-$(CONFIG_S3C_DEV_FB)        += dev-fb.o
 obj-$(CONFIG_S3C_DEV_USB_HOST)  += dev-usb.o
 obj-$(CONFIG_S3C_DEV_USB_HSOTG) += dev-usb-hsotg.o
+obj-$(CONFIG_S3C_DEV_NAND)      += dev-nand.o
diff --git a/arch/arm/plat-s3c/dev-nand.c b/arch/arm/plat-s3c/dev-nand.c
new file mode 100644
index 000000000000..4e5323732434
--- /dev/null
+++ b/arch/arm/plat-s3c/dev-nand.c
@@ -0,0 +1,30 @@
+/*
+ * S3C series device definition for nand device
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <mach/map.h>
+#include <plat/devs.h>
+static struct resource s3c_nand_resource[] = {
+        [0] = {
+                .start = S3C_PA_NAND,
+                .end   = S3C_PA_NAND + SZ_1M,
+                .flags = IORESOURCE_MEM,
+        }
+};
+struct platform_device s3c_device_nand = {
+        .name             = "s3c2410-nand",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_nand_resource),
+        .resource         = s3c_nand_resource,
+};
+EXPORT_SYMBOL(s3c_device_nand);
diff --git a/arch/arm/plat-s3c/include/plat/adc.h b/arch/arm/plat-s3c/include/plat/adc.h
index d847bd476b6c..5f3b1cd53b90 100644
--- a/arch/arm/plat-s3c/include/plat/adc.h
+++ b/arch/arm/plat-s3c/include/plat/adc.h
@@ -19,10 +19,14 @@ struct s3c_adc_client;
 extern int s3c_adc_start(struct s3c_adc_client *client,
                         unsigned int channel, unsigned int nr_samples);
+extern int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch);
 extern struct s3c_adc_client *
        s3c_adc_register(struct platform_device *pdev,
-                         void (*select)(unsigned selected),
+                         void (*select)(struct s3c_adc_client *client,
-                         void (*conv)(unsigned d0, unsigned d1,
+                                        unsigned selected),
+                         void (*conv)(struct s3c_adc_client *client,
+                                      unsigned d0, unsigned d1,
                                      unsigned *samples_left),
                         unsigned int is_ts);
diff --git a/arch/arm/plat-s3c/include/plat/audio-simtec.h b/arch/arm/plat-s3c/include/plat/audio-simtec.h
new file mode 100644
index 000000000000..0f440b9168db
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/audio-simtec.h
@@ -0,0 +1,37 @@
+/* arch/arm/plat-s3c/include/plat/audio-simtec.h
+ *
+ * Copyright 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Simtec Audio support.
+*/
+/**
+ * struct s3c24xx_audio_simtec_pdata - platform data for simtec audio
+ * @use_mpllin: Select codec clock from MPLLin
+ * @output_cdclk: Need to output CDCLK to the codec
+ * @have_mic: Set if we have a MIC socket
+ * @have_lout: Set if we have a LineOut socket
+ * @amp_gpio: GPIO pin to enable the AMP
+ * @amp_gain: Option GPIO to control AMP gain
+ */
+struct s3c24xx_audio_simtec_pdata {
+        unsigned int    use_mpllin:1;
+        unsigned int    output_cdclk:1;
+        unsigned int    have_mic:1;
+        unsigned int    have_lout:1;
+        int             amp_gpio;
+        int             amp_gain[2];
+        void    (*startup)(void);
+};
+extern int simtec_audio_add(const char *codec_name,
+                            struct s3c24xx_audio_simtec_pdata *pdata);
diff --git a/arch/arm/plat-s3c/include/plat/cpu-freq.h b/arch/arm/plat-s3c/include/plat/cpu-freq.h
index c86a13307e90..7b982b7f28cd 100644
--- a/arch/arm/plat-s3c/include/plat/cpu-freq.h
+++ b/arch/arm/plat-s3c/include/plat/cpu-freq.h
@@ -17,6 +17,21 @@ struct s3c_cpufreq_info;
 struct s3c_cpufreq_board;
 struct s3c_iotimings;
+/**
+ * struct s3c_freq - frequency information (mainly for core drivers)
+ * @fclk: The FCLK frequency in Hz.
+ * @armclk: The ARMCLK frequency in Hz.
+ * @hclk_tns: HCLK cycle time in 10ths of nano-seconds.
+ * @hclk: The HCLK frequency in Hz.
+ * @pclk: The PCLK frequency in Hz.
+ *
+ * This contains the frequency information about the current configuration
+ * mainly for the core drivers to ensure we do not end up passing about
+ * a large number of parameters.
+ *
+ * The @hclk_tns field is a useful cache for the parts of the drivers that
+ * need to calculate IO timings and suchlike.
+ */
 struct s3c_freq {
        unsigned long   fclk;
        unsigned long   armclk;
@@ -25,48 +40,84 @@ struct s3c_freq {
        unsigned long   pclk;
 };
-/* wrapper 'struct cpufreq_freqs' so that any drivers receiving the
+/**
+ * struct s3c_cpufreq_freqs - s3c cpufreq notification information.
+ * @freqs: The cpufreq setting information.
+ * @old: The old clock settings.
+ * @new: The new clock settings.
+ * @pll_changing: Set if the PLL is changing.
+ *
+ * Wrapper 'struct cpufreq_freqs' so that any drivers receiving the
 * notification can use this information that is not provided by just
 * having the core frequency alone.
+ *
+ * The pll_changing flag is used to indicate if the PLL itself is
+ * being set during this change. This is important as the clocks
+ * will temporarily be set to the XTAL clock during this time, so
+ * drivers may want to close down their output during this time.
+ *
+ * Note, this is not being used by any current drivers and therefore
+ * may be removed in the future.
 */
 struct s3c_cpufreq_freqs {
        struct cpufreq_freqs    freqs;
        struct s3c_freq         old;
        struct s3c_freq         new;
+        unsigned int            pll_changing:1;
 };
 #define to_s3c_cpufreq(_cf) container_of(_cf, struct s3c_cpufreq_freqs, freqs)
+/**
+ * struct s3c_clkdivs - clock divisor information
+ * @p_divisor: Divisor from FCLK to PCLK.
+ * @h_divisor: Divisor from FCLK to HCLK.
+ * @arm_divisor: Divisor from FCLK to ARMCLK (not all CPUs).
+ * @dvs: Non-zero if using DVS mode for ARMCLK.
+ *
+ * Divisor settings for the core clocks.
+ */
 struct s3c_clkdivs {
-        int             p_divisor;      /* fclk / pclk */
+        int             p_divisor;
-        int             h_divisor;      /* fclk / hclk */
+        int             h_divisor;
-        int             arm_divisor;    /* not all cpus have this. */
+        int             arm_divisor;
-        unsigned char   dvs;            /* using dvs mode to arm. */
+        unsigned char   dvs;
 };
 #define PLLVAL(_m, _p, _s) (((_m) << 12) | ((_p) << 4) | (_s))
+/**
+ * struct s3c_pllval - PLL value entry.
+ * @freq: The frequency for this entry in Hz.
+ * @pll_reg: The PLL register setting for this PLL value.
+ */
 struct s3c_pllval {
        unsigned long           freq;
        unsigned long           pll_reg;
 };
-struct s3c_cpufreq_config {
+/**
-        struct s3c_freq         freq;
+ * struct s3c_cpufreq_board - per-board cpu frequency informatin
-        struct s3c_pllval       pll;
+ * @refresh: The SDRAM refresh period in nanoseconds.
-        struct s3c_clkdivs      divs;
+ * @auto_io: Set if the IO timing settings should be generated from the
-        struct s3c_cpufreq_info *info;  /* for core, not drivers */
+ *      initialisation time hardware registers.
-        struct s3c_cpufreq_board *board;
+ * @need_io: Set if the board has external IO on any of the chipselect
-};
+ *      lines that will require the hardware timing registers to be
+ *      updated on a clock change.
-/* s3c_cpufreq_board
+ * @max: The maxium frequency limits for the system. Any field that
+ *      is left at zero will use the CPU's settings.
+ *
+ * This contains the board specific settings that affect how the CPU
+ * drivers chose settings. These include the memory refresh and IO
+ * timing information.
 *
- * per-board configuraton information, such as memory refresh and
+ * Registration depends on the driver being used, the ARMCLK only
- * how to initialise IO timings.
+ * implementation does not currently need this but the older style
+ * driver requires this to be available.
 */
 struct s3c_cpufreq_board {
-        unsigned int    refresh;        /* refresh period in ns */
+        unsigned int    refresh;
        unsigned int    auto_io:1;      /* automatically init io timings. */
        unsigned int    need_io:1;      /* set if needs io timing support. */
diff --git a/arch/arm/plat-s3c/include/plat/cpu.h b/arch/arm/plat-s3c/include/plat/cpu.h
index be541cbba070..fbc3d498e02e 100644
--- a/arch/arm/plat-s3c/include/plat/cpu.h
+++ b/arch/arm/plat-s3c/include/plat/cpu.h
@@ -65,6 +65,7 @@ extern struct sys_timer s3c24xx_timer;
 /* system device classes */
 extern struct sysdev_class s3c2410_sysclass;
+extern struct sysdev_class s3c2410a_sysclass;
 extern struct sysdev_class s3c2412_sysclass;
 extern struct sysdev_class s3c2440_sysclass;
 extern struct sysdev_class s3c2442_sysclass;
diff --git a/arch/arm/plat-s3c/include/plat/devs.h b/arch/arm/plat-s3c/include/plat/devs.h
index 2e170827e0b0..0f540ea1e999 100644
--- a/arch/arm/plat-s3c/include/plat/devs.h
+++ b/arch/arm/plat-s3c/include/plat/devs.h
@@ -46,6 +46,8 @@ extern struct platform_device s3c_device_hsmmc2;
 extern struct platform_device s3c_device_spi0;
 extern struct platform_device s3c_device_spi1;
+extern struct platform_device s3c_device_hwmon;
 extern struct platform_device s3c_device_nand;
 extern struct platform_device s3c_device_usbgadget;
@@ -56,5 +58,6 @@ extern struct platform_device s3c_device_usb_hsotg;
 #ifdef CONFIG_CPU_S3C2440
 extern struct platform_device s3c_device_camif;
+extern struct platform_device s3c_device_ac97;
 #endif
diff --git a/arch/arm/plat-s3c/include/plat/hwmon.h b/arch/arm/plat-s3c/include/plat/hwmon.h
new file mode 100644
index 000000000000..1ba88ea0aa31
--- /dev/null
+++ b/arch/arm/plat-s3c/include/plat/hwmon.h
@@ -0,0 +1,41 @@
+/* linux/arch/arm/plat-s3c/include/plat/hwmon.h
+ *
+ * Copyright 2005 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      http://armlinux.simtec.co.uk/
+ *
+ * S3C - HWMon interface for ADC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_ADC_HWMON_H
+#define __ASM_ARCH_ADC_HWMON_H __FILE__
+/**
+ * s3c_hwmon_chcfg - channel configuration
+ * @name: The name to give this channel.
+ * @mult: Multiply the ADC value read by this.
+ * @div: Divide the value from the ADC by this.
+ *
+ * The value read from the ADC is converted to a value that
+ * hwmon expects (mV) by result = (value_read * @mult) / @div.
+ */
+struct s3c_hwmon_chcfg {
+        const char      *name;
+        unsigned int    mult;
+        unsigned int    div;
+};
+/**
+ * s3c_hwmon_pdata - HWMON platform data
+ * @in: One configuration for each possible channel used.
+ */
+struct s3c_hwmon_pdata {
+        struct s3c_hwmon_chcfg  *in[8];
+};
+#endif /* __ASM_ARCH_ADC_HWMON_H */
diff --git a/arch/arm/plat-s3c/include/plat/map-base.h b/arch/arm/plat-s3c/include/plat/map-base.h
index b84289d32a54..250be311c85b 100644
--- a/arch/arm/plat-s3c/include/plat/map-base.h
+++ b/arch/arm/plat-s3c/include/plat/map-base.h
@@ -32,9 +32,15 @@
 #define S3C_VA_IRQ      S3C_ADDR(0x00000000)    /* irq controller(s) */
 #define S3C_VA_SYS      S3C_ADDR(0x00100000)    /* system control */
-#define S3C_VA_MEM      S3C_ADDR(0x00200000)    /* system control */
+#define S3C_VA_MEM      S3C_ADDR(0x00200000)    /* memory control */
 #define S3C_VA_TIMER    S3C_ADDR(0x00300000)    /* timer block */
 #define S3C_VA_WATCHDOG S3C_ADDR(0x00400000)    /* watchdog */
 #define S3C_VA_UART     S3C_ADDR(0x01000000)    /* UART */
+/* This is used for the CPU specific mappings that may be needed, so that
+ * they do not need to directly used S3C_ADDR() and thus make it easier to
+ * modify the space for mapping.
+ */
+#define S3C_ADDR_CPU(x) S3C_ADDR(0x00500000 + (x))
 #endif /* __ASM_PLAT_MAP_H */
diff --git a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h b/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h
index 0fad7571030e..07659dad1748 100644
--- a/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h
+++ b/arch/arm/plat-s3c/include/plat/regs-s3c2412-iis.h
@@ -33,6 +33,11 @@
 #define S3C2412_IISCON_RXDMA_ACTIVE     (1 << 1)
 #define S3C2412_IISCON_IIS_ACTIVE       (1 << 0)
+#define S3C64XX_IISMOD_BLC_16BIT        (0 << 13)
+#define S3C64XX_IISMOD_BLC_8BIT         (1 << 13)
+#define S3C64XX_IISMOD_BLC_24BIT        (2 << 13)
+#define S3C64XX_IISMOD_BLC_MASK         (3 << 13)
 #define S3C64XX_IISMOD_IMS_PCLK         (0 << 10)
 #define S3C64XX_IISMOD_IMS_SYSMUX       (1 << 10)
diff --git a/arch/arm/plat-s3c24xx/pwm.c b/arch/arm/plat-s3c/pwm.c
index 82a6d4de02a3..4fdc5b307fd2 100644
--- a/arch/arm/plat-s3c24xx/pwm.c
+++ b/arch/arm/plat-s3c/pwm.c
@@ -1,10 +1,10 @@
-/* arch/arm/plat-s3c24xx/pwm.c
+/* arch/arm/plat-s3c/pwm.c
 *
 * Copyright (c) 2007 Ben Dooks
 * Copyright (c) 2008 Simtec Electronics
 *      Ben Dooks <ben@simtec.co.uk>, <ben-linux@fluff.org>
 *
- * S3C24XX PWM device core
+ * S3C series PWM device core
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
@@ -20,6 +20,7 @@
 #include <linux/pwm.h>
 #include <mach/irqs.h>
+#include <mach/map.h>
 #include <plat/devs.h>
 #include <plat/regs-timer.h>
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index 5b0bc914f58e..9c7aca489643 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -10,6 +10,7 @@ config PLAT_S3C24XX
        default y
        select NO_IOPORT
        select ARCH_REQUIRE_GPIOLIB
+        select S3C_DEVICE_NAND
        help
          Base platform code for any Samsung S3C24XX device
@@ -34,6 +35,40 @@ config CPU_S3C244X
        help
          Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
+config S3C2440_CPUFREQ
+        bool "S3C2440/S3C2442 CPU Frequency scaling support"
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2440 || CPU_S3C2442)
+        select S3C2410_CPUFREQ_UTILS
+        default y
+        help
+          CPU Frequency scaling support for S3C2440 and S3C2442 SoC CPUs.
+config S3C2440_XTAL_12000000
+        bool
+        help
+          Indicate that the build needs to support 12MHz system
+          crystal.
+config S3C2440_XTAL_16934400
+        bool
+        help
+          Indicate that the build needs to support 16.9344MHz system
+          crystal.
+config S3C2440_PLL_12000000
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_12000000
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 12MHz crystals.
+config S3C2440_PLL_16934400
+        bool
+        depends on S3C2440_CPUFREQ && S3C2440_XTAL_16934400
+        default y if CPU_FREQ_S3C24XX_PLL
+        help
+          PLL tables for S3C2440 or S3C2442 CPUs with 16.934MHz crystals.
 config S3C24XX_PWM
        bool "PWM device support"
        select HAVE_PWM
@@ -105,8 +140,39 @@ config S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7
          SPI GPIO configuration code for BUS 1 when connected to
          GPG5, GPG6 and GPG7.
+config S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10
+        bool
+        help
+          SPI GPIO configuration code for BUS 1 when connected to
+          GPD8, GPD9 and GPD10.
 # common code for s3c24xx based machines, such as the SMDKs.
+# cpu frequency items common between s3c2410 and s3c2440/s3c2442
+config S3C2410_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select io timing code that is common to the s3c2410
+          and s3c2440/s3c2442 cpu frequency support.
+config S3C2410_CPUFREQ_UTILS
+        bool
+        depends on CPU_FREQ_S3C24XX
+        help
+          Internal node to select timing code that is common to the s3c2410
+          and s3c2440/s3c244 cpu frequency support.
+# cpu frequency support common to s3c2412, s3c2413 and s3c2442
+config S3C2412_IOTIMING
+        bool
+        depends on CPU_FREQ_S3C24XX && (CPU_S3C2412 || CPU_S3C2443)
+        help
+          Intel node to select io timing code that is common to the s3c2412
+          and the s3c2443.
 config MACH_SMDK
        bool
        help
diff --git a/arch/arm/plat-s3c24xx/Makefile b/arch/arm/plat-s3c24xx/Makefile
index 579a165c2827..7780d2dd833a 100644
--- a/arch/arm/plat-s3c24xx/Makefile
+++ b/arch/arm/plat-s3c24xx/Makefile
@@ -20,19 +20,28 @@ obj-y				+= gpiolib.o
 obj-y                           += clock.o
 obj-$(CONFIG_S3C24XX_DCLK)      += clock-dclk.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX)  += cpu-freq.o
+obj-$(CONFIG_CPU_FREQ_S3C24XX_DEBUGFS) += cpu-freq-debugfs.o
 # Architecture dependant builds
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x-irq.o
 obj-$(CONFIG_CPU_S3C244X)       += s3c244x-clock.o
+obj-$(CONFIG_S3C2440_CPUFREQ)   += s3c2440-cpufreq.o
+obj-$(CONFIG_S3C2440_PLL_12000000) += s3c2440-pll-12000000.o
+obj-$(CONFIG_S3C2440_PLL_16934400) += s3c2440-pll-16934400.o
 obj-$(CONFIG_PM_SIMTEC)         += pm-simtec.o
 obj-$(CONFIG_PM)                += pm.o
 obj-$(CONFIG_PM)                += irq-pm.o
 obj-$(CONFIG_PM)                += sleep.o
-obj-$(CONFIG_S3C24XX_PWM)       += pwm.o
 obj-$(CONFIG_S3C2410_CLOCK)     += s3c2410-clock.o
 obj-$(CONFIG_S3C2410_DMA)       += dma.o
 obj-$(CONFIG_S3C24XX_ADC)       += adc.o
+obj-$(CONFIG_S3C2410_IOTIMING)  += s3c2410-iotiming.o
+obj-$(CONFIG_S3C2412_IOTIMING)  += s3c2412-iotiming.o
+obj-$(CONFIG_S3C2410_CPUFREQ_UTILS) += s3c2410-cpufreq-utils.o
 # device specific setup and/or initialisation
 obj-$(CONFIG_ARCH_S3C2410)      += setup-i2c.o
@@ -41,6 +50,7 @@ obj-$(CONFIG_ARCH_S3C2410)	+= setup-i2c.o
 obj-$(CONFIG_S3C24XX_SPI_BUS0_GPE11_GPE12_GPE13) += spi-bus0-gpe11_12_13.o
 obj-$(CONFIG_S3C24XX_SPI_BUS1_GPG5_GPG6_GPG7)    += spi-bus1-gpg5_6_7.o
+obj-$(CONFIG_S3C24XX_SPI_BUS1_GPD8_GPD9_GPD10)   += spi-bus1-gpd8_9_10.o
 # machine common support
diff --git a/arch/arm/plat-s3c24xx/adc.c b/arch/arm/plat-s3c24xx/adc.c
index ee1baf11ad9e..11117a7ba911 100644
--- a/arch/arm/plat-s3c24xx/adc.c
+++ b/arch/arm/plat-s3c24xx/adc.c
@@ -39,13 +39,16 @@
 struct s3c_adc_client {
        struct platform_device  *pdev;
        struct list_head         pend;
+        wait_queue_head_t       *wait;
        unsigned int             nr_samples;
+        int                      result;
        unsigned char            is_ts;
        unsigned char            channel;
-        void    (*select_cb)(unsigned selected);
+        void    (*select_cb)(struct s3c_adc_client *c, unsigned selected);
-        void    (*convert_cb)(unsigned val1, unsigned val2,
+        void    (*convert_cb)(struct s3c_adc_client *c,
+                              unsigned val1, unsigned val2,
                              unsigned *samples_left);
 };
@@ -81,7 +84,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
 {
        unsigned con = readl(adc->regs + S3C2410_ADCCON);
-        client->select_cb(1);
+        client->select_cb(client, 1);
        con &= ~S3C2410_ADCCON_MUXMASK;
        con &= ~S3C2410_ADCCON_STDBM;
@@ -153,25 +156,61 @@ int s3c_adc_start(struct s3c_adc_client *client,
 }
 EXPORT_SYMBOL_GPL(s3c_adc_start);
-static void s3c_adc_default_select(unsigned select)
+static void s3c_convert_done(struct s3c_adc_client *client,
+                             unsigned v, unsigned u, unsigned *left)
+{
+        client->result = v;
+        wake_up(client->wait);
+}
+int s3c_adc_read(struct s3c_adc_client *client, unsigned int ch)
+{
+        DECLARE_WAIT_QUEUE_HEAD_ONSTACK(wake);
+        int ret;
+        client->convert_cb = s3c_convert_done;
+        client->wait = &wake;
+        client->result = -1;
+        ret = s3c_adc_start(client, ch, 1);
+        if (ret < 0)
+                goto err;
+        ret = wait_event_timeout(wake, client->result >= 0, HZ / 2);
+        if (client->result < 0) {
+                ret = -ETIMEDOUT;
+                goto err;
+        }
+        client->convert_cb = NULL;
+        return client->result;
+err:
+        return ret;
+}
+EXPORT_SYMBOL_GPL(s3c_adc_convert);
+static void s3c_adc_default_select(struct s3c_adc_client *client,
+                                   unsigned select)
 {
 }
 struct s3c_adc_client *s3c_adc_register(struct platform_device *pdev,
-                                        void (*select)(unsigned int selected),
+                                        void (*select)(struct s3c_adc_client *client,
-                                        void (*conv)(unsigned d0, unsigned d1,
+                                                       unsigned int selected),
+                                        void (*conv)(struct s3c_adc_client *client,
+                                                     unsigned d0, unsigned d1,
                                                     unsigned *samples_left),
                                        unsigned int is_ts)
 {
        struct s3c_adc_client *client;
        WARN_ON(!pdev);
-        WARN_ON(!conv);
        if (!select)
                select = s3c_adc_default_select;
-        if (!conv || !pdev)
+        if (!pdev)
                return ERR_PTR(-EINVAL);
        client = kzalloc(sizeof(struct s3c_adc_client), GFP_KERNEL);
@@ -230,16 +269,19 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
        adc_dbg(adc, "read %d: 0x%04x, 0x%04x\n", client->nr_samples, data0, data1);
        client->nr_samples--;
-        (client->convert_cb)(data0 & 0x3ff, data1 & 0x3ff, &client->nr_samples);
+        if (client->convert_cb)
+                (client->convert_cb)(client, data0 & 0x3ff, data1 & 0x3ff,
+                                     &client->nr_samples);
        if (client->nr_samples > 0) {
                /* fire another conversion for this */
-                client->select_cb(1);
+                client->select_cb(client, 1);
                s3c_adc_convert(adc);
        } else {
                local_irq_save(flags);
-                (client->select_cb)(0);
+                (client->select_cb)(client, 0);
                adc->cur = NULL;
                s3c_adc_try(adc);
diff --git a/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
new file mode 100644
index 000000000000..a9276667c2fb
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
@@ -0,0 +1,199 @@
+/* linux/arch/arm/plat-s3c24xx/cpu-freq-debugfs.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - debugfs status support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/err.h>
+#include <plat/cpu-freq-core.h>
+static struct dentry *dbgfs_root;
+static struct dentry *dbgfs_file_io;
+static struct dentry *dbgfs_file_info;
+static struct dentry *dbgfs_file_board;
+#define print_ns(x) ((x) / 10), ((x) % 10)
+static void show_max(struct seq_file *seq, struct s3c_freq *f)
+{
+        seq_printf(seq, "MAX: F=%lu, H=%lu, P=%lu, A=%lu\n",
+                   f->fclk, f->hclk, f->pclk, f->armclk);
+}
+static int board_show(struct seq_file *seq, void *p)
+{
+        struct s3c_cpufreq_config *cfg;
+        struct s3c_cpufreq_board *brd;
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+        brd = cfg->board;
+        if (!brd) {
+                seq_printf(seq, "no board definition set?\n");
+                return 0;
+        }
+        seq_printf(seq, "SDRAM refresh %u ns\n", brd->refresh);
+        seq_printf(seq, "auto_io=%u\n", brd->auto_io);
+        seq_printf(seq, "need_io=%u\n", brd->need_io);
+        show_max(seq, &brd->max);
+        return 0;
+}
+static int fops_board_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, board_show, NULL);
+}
+static const struct file_operations fops_board = {
+        .open           = fops_board_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+static int info_show(struct seq_file *seq, void *p)
+{
+        struct s3c_cpufreq_config *cfg;
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+        seq_printf(seq, "  FCLK %ld Hz\n", cfg->freq.fclk);
+        seq_printf(seq, "  HCLK %ld Hz (%lu.%lu ns)\n",
+                   cfg->freq.hclk, print_ns(cfg->freq.hclk_tns));
+        seq_printf(seq, "  PCLK %ld Hz\n", cfg->freq.hclk);
+        seq_printf(seq, "ARMCLK %ld Hz\n", cfg->freq.armclk);
+        seq_printf(seq, "\n");
+        show_max(seq, &cfg->max);
+        seq_printf(seq, "Divisors: P=%d, H=%d, A=%d, dvs=%s\n",
+                   cfg->divs.h_divisor, cfg->divs.p_divisor,
+                   cfg->divs.arm_divisor, cfg->divs.dvs ? "on" : "off");
+        seq_printf(seq, "\n");
+        seq_printf(seq, "lock_pll=%u\n", cfg->lock_pll);
+        return 0;
+}
+static int fops_info_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, info_show, NULL);
+}
+static const struct file_operations fops_info = {
+        .open           = fops_info_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+static int io_show(struct seq_file *seq, void *p)
+{
+        void (*show_bank)(struct seq_file *, struct s3c_cpufreq_config *, union s3c_iobank *);
+        struct s3c_cpufreq_config *cfg;
+        struct s3c_iotimings *iot;
+        union s3c_iobank *iob;
+        int bank;
+        cfg = s3c_cpufreq_getconfig();
+        if (!cfg) {
+                seq_printf(seq, "no configuration registered\n");
+                return 0;
+        }
+        show_bank = cfg->info->debug_io_show;
+        if (!show_bank) {
+                seq_printf(seq, "no code to show bank timing\n");
+                return 0;
+        }
+        iot = s3c_cpufreq_getiotimings();
+        if (!iot) {
+                seq_printf(seq, "no io timings registered\n");
+                return 0;
+        }
+        seq_printf(seq, "hclk period is %lu.%lu ns\n", print_ns(cfg->freq.hclk_tns));
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                iob = &iot->bank[bank];
+                seq_printf(seq, "bank %d: ", bank);
+                if (!iob->io_2410) {
+                        seq_printf(seq, "nothing set\n");
+                        continue;
+                }
+                show_bank(seq, cfg, iob);
+        }
+        return 0;
+}
+static int fops_io_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, io_show, NULL);
+}
+static const struct file_operations fops_io = {
+        .open           = fops_io_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+        .owner          = THIS_MODULE,
+};
+static int __init s3c_freq_debugfs_init(void)
+{
+        dbgfs_root = debugfs_create_dir("s3c-cpufreq", NULL);
+        if (IS_ERR(dbgfs_root)) {
+                printk(KERN_ERR "%s: error creating debugfs root\n", __func__);
+                return PTR_ERR(dbgfs_root);
+        }
+        dbgfs_file_io = debugfs_create_file("io-timing", S_IRUGO, dbgfs_root,
+                                            NULL, &fops_io);
+        dbgfs_file_info = debugfs_create_file("info", S_IRUGO, dbgfs_root,
+                                              NULL, &fops_info);
+        dbgfs_file_board = debugfs_create_file("board", S_IRUGO, dbgfs_root,
+                                               NULL, &fops_board);
+        return 0;
+}
+late_initcall(s3c_freq_debugfs_init);
diff --git a/arch/arm/plat-s3c24xx/cpu-freq.c b/arch/arm/plat-s3c24xx/cpu-freq.c
new file mode 100644
index 000000000000..4f1b789a1173
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/cpu-freq.c
@@ -0,0 +1,716 @@
+/* linux/arch/arm/plat-s3c24xx/cpu-freq.c
+ *
+ * Copyright (c) 2006,2007,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/cpu.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/sysdev.h>
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <plat/cpu.h>
+#include <plat/clock.h>
+#include <plat/cpu-freq-core.h>
+#include <mach/regs-clock.h>
+/* note, cpufreq support deals in kHz, no Hz */
+static struct cpufreq_driver s3c24xx_driver;
+static struct s3c_cpufreq_config cpu_cur;
+static struct s3c_iotimings s3c24xx_iotiming;
+static struct cpufreq_frequency_table *pll_reg;
+static unsigned int last_target = ~0;
+static unsigned int ftab_size;
+static struct cpufreq_frequency_table *ftab;
+static struct clk *_clk_mpll;
+static struct clk *_clk_xtal;
+static struct clk *clk_fclk;
+static struct clk *clk_hclk;
+static struct clk *clk_pclk;
+static struct clk *clk_arm;
+#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
+struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void)
+{
+        return &cpu_cur;
+}
+struct s3c_iotimings *s3c_cpufreq_getiotimings(void)
+{
+        return &s3c24xx_iotiming;
+}
+#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUGFS */
+static void s3c_cpufreq_getcur(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long fclk, pclk, hclk, armclk;
+        cfg->freq.fclk = fclk = clk_get_rate(clk_fclk);
+        cfg->freq.hclk = hclk = clk_get_rate(clk_hclk);
+        cfg->freq.pclk = pclk = clk_get_rate(clk_pclk);
+        cfg->freq.armclk = armclk = clk_get_rate(clk_arm);
+        cfg->pll.index = __raw_readl(S3C2410_MPLLCON);
+        cfg->pll.frequency = fclk;
+        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
+        cfg->divs.h_divisor = fclk / hclk;
+        cfg->divs.p_divisor = fclk / pclk;
+}
+static inline void s3c_cpufreq_calc(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long pll = cfg->pll.frequency;
+        cfg->freq.fclk = pll;
+        cfg->freq.hclk = pll / cfg->divs.h_divisor;
+        cfg->freq.pclk = pll / cfg->divs.p_divisor;
+        /* convert hclk into 10ths of nanoseconds for io calcs */
+        cfg->freq.hclk_tns = 1000000000 / (cfg->freq.hclk / 10);
+}
+static inline int closer(unsigned int target, unsigned int n, unsigned int c)
+{
+        int diff_cur = abs(target - c);
+        int diff_new = abs(target - n);
+        return (diff_new < diff_cur);
+}
+static void s3c_cpufreq_show(const char *pfx,
+                                 struct s3c_cpufreq_config *cfg)
+{
+        s3c_freq_dbg("%s: Fvco=%u, F=%lu, A=%lu, H=%lu (%u), P=%lu (%u)\n",
+                     pfx, cfg->pll.frequency, cfg->freq.fclk, cfg->freq.armclk,
+                     cfg->freq.hclk, cfg->divs.h_divisor,
+                     cfg->freq.pclk, cfg->divs.p_divisor);
+}
+/* functions to wrapper the driver info calls to do the cpu specific work */
+static void s3c_cpufreq_setio(struct s3c_cpufreq_config *cfg)
+{
+        if (cfg->info->set_iotiming)
+                (cfg->info->set_iotiming)(cfg, &s3c24xx_iotiming);
+}
+static int s3c_cpufreq_calcio(struct s3c_cpufreq_config *cfg)
+{
+        if (cfg->info->calc_iotiming)
+                return (cfg->info->calc_iotiming)(cfg, &s3c24xx_iotiming);
+        return 0;
+}
+static void s3c_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_refresh)(cfg);
+}
+static void s3c_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_divs)(cfg);
+}
+static int s3c_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        return (cfg->info->calc_divs)(cfg);
+}
+static void s3c_cpufreq_setfvco(struct s3c_cpufreq_config *cfg)
+{
+        (cfg->info->set_fvco)(cfg);
+}
+static inline void s3c_cpufreq_resume_clocks(void)
+{
+        cpu_cur.info->resume_clocks();
+}
+static inline void s3c_cpufreq_updateclk(struct clk *clk,
+                                         unsigned int freq)
+{
+        clk_set_rate(clk, freq);
+}
+static int s3c_cpufreq_settarget(struct cpufreq_policy *policy,
+                                 unsigned int target_freq,
+                                 struct cpufreq_frequency_table *pll)
+{
+        struct s3c_cpufreq_freqs freqs;
+        struct s3c_cpufreq_config cpu_new;
+        unsigned long flags;
+        cpu_new = cpu_cur;  /* copy new from current */
+        s3c_cpufreq_show("cur", &cpu_cur);
+        /* TODO - check for DMA currently outstanding */
+        cpu_new.pll = pll ? *pll : cpu_cur.pll;
+        if (pll)
+                freqs.pll_changing = 1;
+        /* update our frequencies */
+        cpu_new.freq.armclk = target_freq;
+        cpu_new.freq.fclk = cpu_new.pll.frequency;
+        if (s3c_cpufreq_calcdivs(&cpu_new) < 0) {
+                printk(KERN_ERR "no divisors for %d\n", target_freq);
+                goto err_notpossible;
+        }
+        s3c_freq_dbg("%s: got divs\n", __func__);
+        s3c_cpufreq_calc(&cpu_new);
+        s3c_freq_dbg("%s: calculated frequencies for new\n", __func__);
+        if (cpu_new.freq.hclk != cpu_cur.freq.hclk) {
+                if (s3c_cpufreq_calcio(&cpu_new) < 0) {
+                        printk(KERN_ERR "%s: no IO timings\n", __func__);
+                        goto err_notpossible;
+                }
+        }
+        s3c_cpufreq_show("new", &cpu_new);
+        /* setup our cpufreq parameters */
+        freqs.old = cpu_cur.freq;
+        freqs.new = cpu_new.freq;
+        freqs.freqs.cpu = 0;
+        freqs.freqs.old = cpu_cur.freq.armclk / 1000;
+        freqs.freqs.new = cpu_new.freq.armclk / 1000;
+        /* update f/h/p clock settings before we issue the change
+         * notification, so that drivers do not need to do anything
+         * special if they want to recalculate on CPUFREQ_PRECHANGE. */
+        s3c_cpufreq_updateclk(_clk_mpll, cpu_new.pll.frequency);
+        s3c_cpufreq_updateclk(clk_fclk, cpu_new.freq.fclk);
+        s3c_cpufreq_updateclk(clk_hclk, cpu_new.freq.hclk);
+        s3c_cpufreq_updateclk(clk_pclk, cpu_new.freq.pclk);
+        /* start the frequency change */
+        if (policy)
+                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_PRECHANGE);
+        /* If hclk is staying the same, then we do not need to
+         * re-write the IO or the refresh timings whilst we are changing
+         * speed. */
+        local_irq_save(flags);
+        /* is our memory clock slowing down? */
+        if (cpu_new.freq.hclk < cpu_cur.freq.hclk) {
+                s3c_cpufreq_setrefresh(&cpu_new);
+                s3c_cpufreq_setio(&cpu_new);
+        }
+        if (cpu_new.freq.fclk == cpu_cur.freq.fclk) {
+                /* not changing PLL, just set the divisors */
+                s3c_cpufreq_setdivs(&cpu_new);
+        } else {
+                if (cpu_new.freq.fclk < cpu_cur.freq.fclk) {
+                        /* slow the cpu down, then set divisors */
+                        s3c_cpufreq_setfvco(&cpu_new);
+                        s3c_cpufreq_setdivs(&cpu_new);
+                } else {
+                        /* set the divisors, then speed up */
+                        s3c_cpufreq_setdivs(&cpu_new);
+                        s3c_cpufreq_setfvco(&cpu_new);
+                }
+        }
+        /* did our memory clock speed up */
+        if (cpu_new.freq.hclk > cpu_cur.freq.hclk) {
+                s3c_cpufreq_setrefresh(&cpu_new);
+                s3c_cpufreq_setio(&cpu_new);
+        }
+        /* update our current settings */
+        cpu_cur = cpu_new;
+        local_irq_restore(flags);
+        /* notify everyone we've done this */
+        if (policy)
+                cpufreq_notify_transition(&freqs.freqs, CPUFREQ_POSTCHANGE);
+        s3c_freq_dbg("%s: finished\n", __func__);
+        return 0;
+ err_notpossible:
+        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
+        return -EINVAL;
+}
+/* s3c_cpufreq_target
+ *
+ * called by the cpufreq core to adjust the frequency that the CPU
+ * is currently running at.
+ */
+static int s3c_cpufreq_target(struct cpufreq_policy *policy,
+                              unsigned int target_freq,
+                              unsigned int relation)
+{
+        struct cpufreq_frequency_table *pll;
+        unsigned int index;
+        /* avoid repeated calls which cause a needless amout of duplicated
+         * logging output (and CPU time as the calculation process is
+         * done) */
+        if (target_freq == last_target)
+                return 0;
+        last_target = target_freq;
+        s3c_freq_dbg("%s: policy %p, target %u, relation %u\n",
+                     __func__, policy, target_freq, relation);
+        if (ftab) {
+                if (cpufreq_frequency_table_target(policy, ftab,
+                                                   target_freq, relation,
+                                                   &index)) {
+                        s3c_freq_dbg("%s: table failed\n", __func__);
+                        return -EINVAL;
+                }
+                s3c_freq_dbg("%s: adjust %d to entry %d (%u)\n", __func__,
+                             target_freq, index, ftab[index].frequency);
+                target_freq = ftab[index].frequency;
+        }
+        target_freq *= 1000;  /* convert target to Hz */
+        /* find the settings for our new frequency */
+        if (!pll_reg || cpu_cur.lock_pll) {
+                /* either we've not got any PLL values, or we've locked
+                 * to the current one. */
+                pll = NULL;
+        } else {
+                struct cpufreq_policy tmp_policy;
+                int ret;
+                /* we keep the cpu pll table in Hz, to ensure we get an
+                 * accurate value for the PLL output. */
+                tmp_policy.min = policy->min * 1000;
+                tmp_policy.max = policy->max * 1000;
+                tmp_policy.cpu = policy->cpu;
+                /* cpufreq_frequency_table_target uses a pointer to 'index'
+                 * which is the number of the table entry, not the value of
+                 * the table entry's index field. */
+                ret = cpufreq_frequency_table_target(&tmp_policy, pll_reg,
+                                                     target_freq, relation,
+                                                     &index);
+                if (ret < 0) {
+                        printk(KERN_ERR "%s: no PLL available\n", __func__);
+                        goto err_notpossible;
+                }
+                pll = pll_reg + index;
+                s3c_freq_dbg("%s: target %u => %u\n",
+                             __func__, target_freq, pll->frequency);
+                target_freq = pll->frequency;
+        }
+        return s3c_cpufreq_settarget(policy, target_freq, pll);
+ err_notpossible:
+        printk(KERN_ERR "no compatible settings for %d\n", target_freq);
+        return -EINVAL;
+}
+static unsigned int s3c_cpufreq_get(unsigned int cpu)
+{
+        return clk_get_rate(clk_arm) / 1000;
+}
+struct clk *s3c_cpufreq_clk_get(struct device *dev, const char *name)
+{
+        struct clk *clk;
+        clk = clk_get(dev, name);
+        if (IS_ERR(clk))
+                printk(KERN_ERR "cpufreq: failed to get clock '%s'\n", name);
+        return clk;
+}
+static int s3c_cpufreq_init(struct cpufreq_policy *policy)
+{
+        printk(KERN_INFO "%s: initialising policy %p\n", __func__, policy);
+        if (policy->cpu != 0)
+                return -EINVAL;
+        policy->cur = s3c_cpufreq_get(0);
+        policy->min = policy->cpuinfo.min_freq = 0;
+        policy->max = policy->cpuinfo.max_freq = cpu_cur.info->max.fclk / 1000;
+        policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+        /* feed the latency information from the cpu driver */
+        policy->cpuinfo.transition_latency = cpu_cur.info->latency;
+        if (ftab)
+                cpufreq_frequency_table_cpuinfo(policy, ftab);
+        return 0;
+}
+static __init int s3c_cpufreq_initclks(void)
+{
+        _clk_mpll = s3c_cpufreq_clk_get(NULL, "mpll");
+        _clk_xtal = s3c_cpufreq_clk_get(NULL, "xtal");
+        clk_fclk = s3c_cpufreq_clk_get(NULL, "fclk");
+        clk_hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+        clk_pclk = s3c_cpufreq_clk_get(NULL, "pclk");
+        clk_arm = s3c_cpufreq_clk_get(NULL, "armclk");
+        if (IS_ERR(clk_fclk) || IS_ERR(clk_hclk) || IS_ERR(clk_pclk) ||
+            IS_ERR(_clk_mpll) || IS_ERR(clk_arm) || IS_ERR(_clk_xtal)) {
+                printk(KERN_ERR "%s: could not get clock(s)\n", __func__);
+                return -ENOENT;
+        }
+        printk(KERN_INFO "%s: clocks f=%lu,h=%lu,p=%lu,a=%lu\n", __func__,
+               clk_get_rate(clk_fclk) / 1000,
+               clk_get_rate(clk_hclk) / 1000,
+               clk_get_rate(clk_pclk) / 1000,
+               clk_get_rate(clk_arm) / 1000);
+        return 0;
+}
+static int s3c_cpufreq_verify(struct cpufreq_policy *policy)
+{
+        if (policy->cpu != 0)
+                return -EINVAL;
+        return 0;
+}
+#ifdef CONFIG_PM
+static struct cpufreq_frequency_table suspend_pll;
+static unsigned int suspend_freq;
+static int s3c_cpufreq_suspend(struct cpufreq_policy *policy, pm_message_t pmsg)
+{
+        suspend_pll.frequency = clk_get_rate(_clk_mpll);
+        suspend_pll.index = __raw_readl(S3C2410_MPLLCON);
+        suspend_freq = s3c_cpufreq_get(0) * 1000;
+        return 0;
+}
+static int s3c_cpufreq_resume(struct cpufreq_policy *policy)
+{
+        int ret;
+        s3c_freq_dbg("%s: resuming with policy %p\n", __func__, policy);
+        last_target = ~0;       /* invalidate last_target setting */
+        /* first, find out what speed we resumed at. */
+        s3c_cpufreq_resume_clocks();
+        /* whilst we will be called later on, we try and re-set the
+         * cpu frequencies as soon as possible so that we do not end
+         * up resuming devices and then immediatley having to re-set
+         * a number of settings once these devices have restarted.
+         *
+         * as a note, it is expected devices are not used until they
+         * have been un-suspended and at that time they should have
+         * used the updated clock settings.
+         */
+        ret = s3c_cpufreq_settarget(NULL, suspend_freq, &suspend_pll);
+        if (ret) {
+                printk(KERN_ERR "%s: failed to reset pll/freq\n", __func__);
+                return ret;
+        }
+        return 0;
+}
+#else
+#define s3c_cpufreq_resume NULL
+#define s3c_cpufreq_suspend NULL
+#endif
+static struct cpufreq_driver s3c24xx_driver = {
+        .flags          = CPUFREQ_STICKY,
+        .verify         = s3c_cpufreq_verify,
+        .target         = s3c_cpufreq_target,
+        .get            = s3c_cpufreq_get,
+        .init           = s3c_cpufreq_init,
+        .suspend        = s3c_cpufreq_suspend,
+        .resume         = s3c_cpufreq_resume,
+        .name           = "s3c24xx",
+};
+int __init s3c_cpufreq_register(struct s3c_cpufreq_info *info)
+{
+        if (!info || !info->name) {
+                printk(KERN_ERR "%s: failed to pass valid information\n",
+                       __func__);
+                return -EINVAL;
+        }
+        printk(KERN_INFO "S3C24XX CPU Frequency driver, %s cpu support\n",
+               info->name);
+        /* check our driver info has valid data */
+        BUG_ON(info->set_refresh == NULL);
+        BUG_ON(info->set_divs == NULL);
+        BUG_ON(info->calc_divs == NULL);
+        /* info->set_fvco is optional, depending on whether there
+         * is a need to set the clock code. */
+        cpu_cur.info = info;
+        /* Note, driver registering should probably update locktime */
+        return 0;
+}
+int __init s3c_cpufreq_setboard(struct s3c_cpufreq_board *board)
+{
+        struct s3c_cpufreq_board *ours;
+        if (!board) {
+                printk(KERN_INFO "%s: no board data\n", __func__);
+                return -EINVAL;
+        }
+        /* Copy the board information so that each board can make this
+         * initdata. */
+        ours = kzalloc(sizeof(struct s3c_cpufreq_board), GFP_KERNEL);
+        if (ours == NULL) {
+                printk(KERN_ERR "%s: no memory\n", __func__);
+                return -ENOMEM;
+        }
+        *ours = *board;
+        cpu_cur.board = ours;
+        return 0;
+}
+int __init s3c_cpufreq_auto_io(void)
+{
+        int ret;
+        if (!cpu_cur.info->get_iotiming) {
+                printk(KERN_ERR "%s: get_iotiming undefined\n", __func__);
+                return -ENOENT;
+        }
+        printk(KERN_INFO "%s: working out IO settings\n", __func__);
+        ret = (cpu_cur.info->get_iotiming)(&cpu_cur, &s3c24xx_iotiming);
+        if (ret)
+                printk(KERN_ERR "%s: failed to get timings\n", __func__);
+        return ret;
+}
+/* if one or is zero, then return the other, otherwise return the min */
+#define do_min(_a, _b) ((_a) == 0 ? (_b) : (_b) == 0 ? (_a) : min(_a, _b))
+/**
+ * s3c_cpufreq_freq_min - find the minimum settings for the given freq.
+ * @dst: The destination structure
+ * @a: One argument.
+ * @b: The other argument.
+ *
+ * Create a minimum of each frequency entry in the 'struct s3c_freq',
+ * unless the entry is zero when it is ignored and the non-zero argument
+ * used.
+ */
+static void s3c_cpufreq_freq_min(struct s3c_freq *dst,
+                                 struct s3c_freq *a, struct s3c_freq *b)
+{
+        dst->fclk = do_min(a->fclk, b->fclk);
+        dst->hclk = do_min(a->hclk, b->hclk);
+        dst->pclk = do_min(a->pclk, b->pclk);
+        dst->armclk = do_min(a->armclk, b->armclk);
+}
+static inline u32 calc_locktime(u32 freq, u32 time_us)
+{
+        u32 result;
+        result = freq * time_us;
+        result = DIV_ROUND_UP(result, 1000 * 1000);
+        return result;
+}
+static void s3c_cpufreq_update_loctkime(void)
+{
+        unsigned int bits = cpu_cur.info->locktime_bits;
+        u32 rate = (u32)clk_get_rate(_clk_xtal);
+        u32 val;
+        if (bits == 0) {
+                WARN_ON(1);
+                return;
+        }
+        val = calc_locktime(rate, cpu_cur.info->locktime_u) << bits;
+        val |= calc_locktime(rate, cpu_cur.info->locktime_m);
+        printk(KERN_INFO "%s: new locktime is 0x%08x\n", __func__, val);
+        __raw_writel(val, S3C2410_LOCKTIME);
+}
+static int s3c_cpufreq_build_freq(void)
+{
+        int size, ret;
+        if (!cpu_cur.info->calc_freqtable)
+                return -EINVAL;
+        kfree(ftab);
+        ftab = NULL;
+        size = cpu_cur.info->calc_freqtable(&cpu_cur, NULL, 0);
+        size++;
+        ftab = kmalloc(sizeof(struct cpufreq_frequency_table) * size, GFP_KERNEL);
+        if (!ftab) {
+                printk(KERN_ERR "%s: no memory for tables\n", __func__);
+                return -ENOMEM;
+        }
+        ftab_size = size;
+        ret = cpu_cur.info->calc_freqtable(&cpu_cur, ftab, size);
+        s3c_cpufreq_addfreq(ftab, ret, size, CPUFREQ_TABLE_END);
+        return 0;
+}
+static int __init s3c_cpufreq_initcall(void)
+{
+        int ret = 0;
+        if (cpu_cur.info && cpu_cur.board) {
+                ret = s3c_cpufreq_initclks();
+                if (ret)
+                        goto out;
+                /* get current settings */
+                s3c_cpufreq_getcur(&cpu_cur);
+                s3c_cpufreq_show("cur", &cpu_cur);
+                if (cpu_cur.board->auto_io) {
+                        ret = s3c_cpufreq_auto_io();
+                        if (ret) {
+                                printk(KERN_ERR "%s: failed to get io timing\n",
+                                       __func__);
+                                goto out;
+                        }
+                }
+                if (cpu_cur.board->need_io && !cpu_cur.info->set_iotiming) {
+                        printk(KERN_ERR "%s: no IO support registered\n",
+                               __func__);
+                        ret = -EINVAL;
+                        goto out;
+                }
+                if (!cpu_cur.info->need_pll)
+                        cpu_cur.lock_pll = 1;
+                s3c_cpufreq_update_loctkime();
+                s3c_cpufreq_freq_min(&cpu_cur.max, &cpu_cur.board->max,
+                                     &cpu_cur.info->max);
+                if (cpu_cur.info->calc_freqtable)
+                        s3c_cpufreq_build_freq();
+                ret = cpufreq_register_driver(&s3c24xx_driver);
+        }
+ out:
+        return ret;
+}
+late_initcall(s3c_cpufreq_initcall);
+/**
+ * s3c_plltab_register - register CPU PLL table.
+ * @plls: The list of PLL entries.
+ * @plls_no: The size of the PLL entries @plls.
+ *
+ * Register the given set of PLLs with the system.
+ */
+int __init s3c_plltab_register(struct cpufreq_frequency_table *plls,
+                               unsigned int plls_no)
+{
+        struct cpufreq_frequency_table *vals;
+        unsigned int size;
+        size = sizeof(struct cpufreq_frequency_table) * (plls_no + 1);
+        vals = kmalloc(size, GFP_KERNEL);
+        if (vals) {
+                memcpy(vals, plls, size);
+                pll_reg = vals;
+                /* write a terminating entry, we don't store it in the
+                 * table that is stored in the kernel */
+                vals += plls_no;
+                vals->frequency = CPUFREQ_TABLE_END;
+                printk(KERN_INFO "cpufreq: %d PLL entries\n", plls_no);
+        } else
+                printk(KERN_ERR "cpufreq: no memory for PLL tables\n");
+        return vals ? 0 : -ENOMEM;
+}
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 1932b7e0da15..5447e60f3936 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -81,7 +81,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                .map_io         = s3c2410_map_io,
                .init_clocks    = s3c2410_init_clocks,
                .init_uarts     = s3c2410_init_uarts,
-                .init           = s3c2410_init,
+                .init           = s3c2410a_init,
                .name           = name_s3c2410a
        },
        {
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 4eb378c89a39..f52a92ce8dda 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -26,6 +26,8 @@
 #include <asm/mach/irq.h>
 #include <mach/fb.h>
 #include <mach/hardware.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
 #include <asm/irq.h>
 #include <plat/regs-serial.h>
@@ -180,25 +182,6 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
        }
 }
-/* NAND Controller */
-static struct resource s3c_nand_resource[] = {
-        [0] = {
-                .start = S3C24XX_PA_NAND,
-                .end   = S3C24XX_PA_NAND + S3C24XX_SZ_NAND - 1,
-                .flags = IORESOURCE_MEM,
-        }
-};
-struct platform_device s3c_device_nand = {
-        .name             = "s3c2410-nand",
-        .id               = -1,
-        .num_resources    = ARRAY_SIZE(s3c_nand_resource),
-        .resource         = s3c_nand_resource,
-};
-EXPORT_SYMBOL(s3c_device_nand);
 /* USB Device (Gadget)*/
 static struct resource s3c_usbgadget_resource[] = {
@@ -348,7 +331,7 @@ struct platform_device s3c_device_adc = {
 /* HWMON */
 struct platform_device s3c_device_hwmon = {
-        .name           = "s3c24xx-hwmon",
+        .name           = "s3c-hwmon",
        .id             = -1,
        .dev.parent     = &s3c_device_adc.dev,
 };
@@ -473,4 +456,52 @@ struct platform_device s3c_device_camif = {
 EXPORT_SYMBOL(s3c_device_camif);
+/* AC97 */
+static struct resource s3c_ac97_resource[] = {
+        [0] = {
+                .start = S3C2440_PA_AC97,
+                .end   = S3C2440_PA_AC97 + S3C2440_SZ_AC97 -1,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start = IRQ_S3C244x_AC97,
+                .end   = IRQ_S3C244x_AC97,
+                .flags = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .name  = "PCM out",
+                .start = DMACH_PCM_OUT,
+                .end   = DMACH_PCM_OUT,
+                .flags = IORESOURCE_DMA,
+        },
+        [3] = {
+                .name  = "PCM in",
+                .start = DMACH_PCM_IN,
+                .end   = DMACH_PCM_IN,
+                .flags = IORESOURCE_DMA,
+        },
+        [4] = {
+                .name  = "Mic in",
+                .start = DMACH_MIC_IN,
+                .end   = DMACH_MIC_IN,
+                .flags = IORESOURCE_DMA,
+        },
+};
+static u64 s3c_device_ac97_dmamask = 0xffffffffUL;
+struct platform_device s3c_device_ac97 = {
+        .name             = "s3c-ac97",
+        .id               = -1,
+        .num_resources    = ARRAY_SIZE(s3c_ac97_resource),
+        .resource         = s3c_ac97_resource,
+        .dev              = {
+                .dma_mask = &s3c_device_ac97_dmamask,
+                .coherent_dma_mask = 0xffffffffUL
+        }
+};
+EXPORT_SYMBOL(s3c_device_ac97);
 #endif // CONFIG_CPU_S32440
diff --git a/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
new file mode 100644
index 000000000000..efeb025affc7
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/cpu-freq-core.h
@@ -0,0 +1,282 @@
+/* arch/arm/plat-s3c/include/plat/cpu-freq.h
+ *
+ * Copyright (c) 2006,2007,2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C CPU frequency scaling support - core support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <plat/cpu-freq.h>
+struct seq_file;
+#define MAX_BANKS (8)
+#define S3C2412_MAX_IO  (8)
+/**
+ * struct s3c2410_iobank_timing - IO bank timings for S3C2410 style timings
+ * @bankcon: The cached version of settings in this structure.
+ * @tacp:
+ * @tacs: Time from address valid to nCS asserted.
+ * @tcos: Time from nCS asserted to nOE or nWE asserted.
+ * @tacc: Time that nOE or nWE is asserted.
+ * @tcoh: Time nCS is held after nOE or nWE are released.
+ * @tcah: Time address is held for after
+ * @nwait_en: Whether nWAIT is enabled for this bank.
+ *
+ * This structure represents the IO timings for a S3C2410 style IO bank
+ * used by the CPU frequency support if it needs to change the settings
+ * of the IO.
+ */
+struct s3c2410_iobank_timing {
+        unsigned long   bankcon;
+        unsigned int    tacp;
+        unsigned int    tacs;
+        unsigned int    tcos;
+        unsigned int    tacc;
+        unsigned int    tcoh;           /* nCS hold afrer nOE/nWE */
+        unsigned int    tcah;           /* Address hold after nCS */
+        unsigned char   nwait_en;       /* nWait enabled for bank. */
+};
+/**
+ * struct s3c2412_iobank_timing - io timings for PL092 (S3C2412) style IO
+ * @idcy: The idle cycle time between transactions.
+ * @wstrd: nCS release to end of read cycle.
+ * @wstwr: nCS release to end of write cycle.
+ * @wstoen: nCS assertion to nOE assertion time.
+ * @wstwen: nCS assertion to nWE assertion time.
+ * @wstbrd: Burst ready delay.
+ * @smbidcyr: Register cache for smbidcyr value.
+ * @smbwstrd: Register cache for smbwstrd value.
+ * @smbwstwr: Register cache for smbwstwr value.
+ * @smbwstoen: Register cache for smbwstoen value.
+ * @smbwstwen: Register cache for smbwstwen value.
+ * @smbwstbrd: Register cache for smbwstbrd value.
+ *
+ * Timing information for a IO bank on an S3C2412 or similar system which
+ * uses a PL093 block.
+ */
+struct s3c2412_iobank_timing {
+        unsigned int    idcy;
+        unsigned int    wstrd;
+        unsigned int    wstwr;
+        unsigned int    wstoen;
+        unsigned int    wstwen;
+        unsigned int    wstbrd;
+        /* register cache */
+        unsigned char   smbidcyr;
+        unsigned char   smbwstrd;
+        unsigned char   smbwstwr;
+        unsigned char   smbwstoen;
+        unsigned char   smbwstwen;
+        unsigned char   smbwstbrd;
+};
+union s3c_iobank {
+        struct s3c2410_iobank_timing    *io_2410;
+        struct s3c2412_iobank_timing    *io_2412;
+};
+/**
+ * struct s3c_iotimings - Chip IO timings holder
+ * @bank: The timings for each IO bank.
+ */
+struct s3c_iotimings {
+        union s3c_iobank        bank[MAX_BANKS];
+};
+/**
+ * struct s3c_plltab - PLL table information.
+ * @vals: List of PLL values.
+ * @size: Size of the PLL table @vals.
+ */
+struct s3c_plltab {
+        struct s3c_pllval       *vals;
+        int                      size;
+};
+/**
+ * struct s3c_cpufreq_config - current cpu frequency configuration
+ * @freq: The current settings for the core clocks.
+ * @max: Maxium settings, derived from core, board and user settings.
+ * @pll: The PLL table entry for the current PLL settings.
+ * @divs: The divisor settings for the core clocks.
+ * @info: The current core driver information.
+ * @board: The information for the board we are running on.
+ * @lock_pll: Set if the PLL settings cannot be changed.
+ *
+ * This is for the core drivers that need to know information about
+ * the current settings and values. It should not be needed by any
+ * device drivers.
+*/
+struct s3c_cpufreq_config {
+        struct s3c_freq         freq;
+        struct s3c_freq         max;
+        struct cpufreq_frequency_table pll;
+        struct s3c_clkdivs      divs;
+        struct s3c_cpufreq_info *info;  /* for core, not drivers */
+        struct s3c_cpufreq_board *board;
+        unsigned int    lock_pll:1;
+};
+/**
+ * struct s3c_cpufreq_info - Information for the CPU frequency driver.
+ * @name: The name of this implementation.
+ * @max: The maximum frequencies for the system.
+ * @latency: Transition latency to give to cpufreq.
+ * @locktime_m: The lock-time in uS for the MPLL.
+ * @locktime_u: The lock-time in uS for the UPLL.
+ * @locttime_bits: The number of bits each LOCKTIME field.
+ * @need_pll: Set if this driver needs to change the PLL values to acheive
+ *      any frequency changes. This is really only need by devices like the
+ *      S3C2410 where there is no or limited divider between the PLL and the
+ *      ARMCLK.
+ * @resume_clocks: Update the clocks on resume.
+ * @get_iotiming: Get the current IO timing data, mainly for use at start.
+ * @set_iotiming: Update the IO timings from the cached copies calculated
+ *      from the @calc_iotiming entry when changing the frequency.
+ * @calc_iotiming: Calculate and update the cached copies of the IO timings
+ *      from the newly calculated frequencies.
+ * @calc_freqtable: Calculate (fill in) the given frequency table from the
+ *      current frequency configuration. If the table passed in is NULL,
+ *      then the return is the number of elements to be filled for allocation
+ *      of the table.
+ * @set_refresh: Set the memory refresh configuration.
+ * @set_fvco: Set the PLL frequencies.
+ * @set_divs: Update the clock divisors.
+ * @calc_divs: Calculate the clock divisors.
+ */
+struct s3c_cpufreq_info {
+        const char              *name;
+        struct s3c_freq         max;
+        unsigned int            latency;
+        unsigned int            locktime_m;
+        unsigned int            locktime_u;
+        unsigned char           locktime_bits;
+        unsigned int            need_pll:1;
+        /* driver routines */
+        void            (*resume_clocks)(void);
+        int             (*get_iotiming)(struct s3c_cpufreq_config *cfg,
+                                        struct s3c_iotimings *timings);
+        void            (*set_iotiming)(struct s3c_cpufreq_config *cfg,
+                                        struct s3c_iotimings *timings);
+        int             (*calc_iotiming)(struct s3c_cpufreq_config *cfg,
+                                         struct s3c_iotimings *timings);
+        int             (*calc_freqtable)(struct s3c_cpufreq_config *cfg,
+                                          struct cpufreq_frequency_table *t,
+                                          size_t table_size);
+        void            (*debug_io_show)(struct seq_file *seq,
+                                         struct s3c_cpufreq_config *cfg,
+                                         union s3c_iobank *iob);
+        void            (*set_refresh)(struct s3c_cpufreq_config *cfg);
+        void            (*set_fvco)(struct s3c_cpufreq_config *cfg);
+        void            (*set_divs)(struct s3c_cpufreq_config *cfg);
+        int             (*calc_divs)(struct s3c_cpufreq_config *cfg);
+};
+extern int s3c_cpufreq_register(struct s3c_cpufreq_info *info);
+extern int s3c_plltab_register(struct cpufreq_frequency_table *plls, unsigned int plls_no);
+/* exports and utilities for debugfs */
+extern struct s3c_cpufreq_config *s3c_cpufreq_getconfig(void);
+extern struct s3c_iotimings *s3c_cpufreq_getiotimings(void);
+extern void s3c2410_iotiming_debugfs(struct seq_file *seq,
+                                     struct s3c_cpufreq_config *cfg,
+                                     union s3c_iobank *iob);
+extern void s3c2412_iotiming_debugfs(struct seq_file *seq,
+                                     struct s3c_cpufreq_config *cfg,
+                                     union s3c_iobank *iob);
+#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUGFS
+#define s3c_cpufreq_debugfs_call(x) x
+#else
+#define s3c_cpufreq_debugfs_call(x) NULL
+#endif
+/* Useful utility functions. */
+extern struct clk *s3c_cpufreq_clk_get(struct device *, const char *);
+/* S3C2410 and compatible exported functions */
+extern void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg);
+extern int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+extern int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
+                                struct s3c_iotimings *timings);
+extern void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+extern void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg);
+/* S3C2412 compatible routines */
+extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
+                                struct s3c_iotimings *timings);
+extern int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
+                                struct s3c_iotimings *timings);
+extern int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+extern void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
+                                 struct s3c_iotimings *iot);
+#ifdef CONFIG_CPU_FREQ_S3C24XX_DEBUG
+#define s3c_freq_dbg(x...) printk(KERN_INFO x)
+#else
+#define s3c_freq_dbg(x...) do { if (0) printk(x); } while (0)
+#endif /* CONFIG_CPU_FREQ_S3C24XX_DEBUG */
+#ifdef CONFIG_CPU_FREQ_S3C24XX_IODEBUG
+#define s3c_freq_iodbg(x...) printk(KERN_INFO x)
+#else
+#define s3c_freq_iodbg(x...) do { if (0) printk(x); } while (0)
+#endif /* CONFIG_CPU_FREQ_S3C24XX_IODEBUG */
+static inline int s3c_cpufreq_addfreq(struct cpufreq_frequency_table *table,
+                                      int index, size_t table_size,
+                                      unsigned int freq)
+{
+        if (index < 0)
+                return index;
+        if (table) {
+                if (index >= table_size)
+                        return -ENOMEM;
+                s3c_freq_dbg("%s: { %d = %u kHz }\n",
+                             __func__, index, freq);
+                table[index].index = index;
+                table[index].frequency = freq;
+        }
+        return index + 1;
+}
diff --git a/arch/arm/plat-s3c24xx/include/plat/fiq.h b/arch/arm/plat-s3c24xx/include/plat/fiq.h
new file mode 100644
index 000000000000..8521b8372c5f
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/plat/fiq.h
@@ -0,0 +1,13 @@
+/* linux/include/asm-arm/plat-s3c24xx/fiq.h
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Header file for S3C24XX CPU FIQ support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+extern int s3c24xx_set_fiq(unsigned int irq, bool on);
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
index a9ac9e29759e..b6deeef8f663 100644
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
+++ b/arch/arm/plat-s3c24xx/include/plat/s3c2410.h
@@ -14,6 +14,7 @@
 #ifdef CONFIG_CPU_S3C2410
 extern  int s3c2410_init(void);
+extern  int s3c2410a_init(void);
 extern void s3c2410_map_io(void);
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 958737775ad2..d02f5f02045e 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -493,6 +493,38 @@ s3c_irq_demux_extint4t7(unsigned int irq,
        }
 }
+#ifdef CONFIG_FIQ
+/**
+ * s3c24xx_set_fiq - set the FIQ routing
+ * @irq: IRQ number to route to FIQ on processor.
+ * @on: Whether to route @irq to the FIQ, or to remove the FIQ routing.
+ *
+ * Change the state of the IRQ to FIQ routing depending on @irq and @on. If
+ * @on is true, the @irq is checked to see if it can be routed and the
+ * interrupt controller updated to route the IRQ. If @on is false, the FIQ
+ * routing is cleared, regardless of which @irq is specified.
+ */
+int s3c24xx_set_fiq(unsigned int irq, bool on)
+{
+        u32 intmod;
+        unsigned offs;
+        if (on) {
+                offs = irq - FIQ_START;
+                if (offs > 31)
+                        return -EINVAL;
+                intmod = 1 << offs;
+        } else {
+                intmod = 0;
+        }
+        __raw_writel(intmod, S3C2410_INTMOD);
+        return 0;
+}
+#endif
 /* s3c24xx_init_irq
 *
 * Initialise S3C2410 IRQ system
@@ -505,6 +537,10 @@ void __init s3c24xx_init_irq(void)
        int irqno;
        int i;
+#ifdef CONFIG_FIQ
+        init_FIQ();
+#endif
        irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
        /* first, clear all interrupts pending... */
diff --git a/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
new file mode 100644
index 000000000000..43ea80190d87
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
@@ -0,0 +1,64 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2410-cpufreq-utils.c
+ *
+ * Copyright (c) 2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - utils for S3C2410/S3C2440/S3C2442
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu-freq-core.h>
+/**
+ * s3c2410_cpufreq_setrefresh - set SDRAM refresh value
+ * @cfg: The frequency configuration
+ *
+ * Set the SDRAM refresh value appropriately for the configured
+ * frequency.
+ */
+void s3c2410_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        unsigned long refresh;
+        unsigned long refval;
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * down to ensure that we do not overflow 32 bit numbers.
+         *
+         * This should work for HCLK up to 133MHz and refresh period up
+         * to 30usec.
+         */
+        refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
+        refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
+        refresh = (1 << 11) + 1 - refresh;
+        s3c_freq_dbg("%s: refresh value %lu\n", __func__, refresh);
+        refval = __raw_readl(S3C2410_REFRESH);
+        refval &= ~((1 << 12) - 1);
+        refval |= refresh;
+        __raw_writel(refval, S3C2410_REFRESH);
+}
+/**
+ * s3c2410_set_fvco - set the PLL value
+ * @cfg: The frequency configuration
+ */
+void s3c2410_set_fvco(struct s3c_cpufreq_config *cfg)
+{
+        __raw_writel(cfg->pll.index, S3C2410_MPLLCON);
+}
diff --git a/arch/arm/plat-s3c24xx/s3c2410-iotiming.c b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
new file mode 100644
index 000000000000..d0a3a145cd4d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
@@ -0,0 +1,477 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2410-iotiming.c
+ *
+ * Copyright (c) 2006,2008,2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX CPU Frequency scaling - IO timing for S3C2410/S3C2440/S3C2442
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/cpufreq.h>
+#include <linux/seq_file.h>
+#include <linux/io.h>
+#include <mach/map.h>
+#include <mach/regs-mem.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu-freq-core.h>
+#define print_ns(x) ((x) / 10), ((x) % 10)
+/**
+ * s3c2410_print_timing - print bank timing data for debug purposes
+ * @pfx: The prefix to put on the output
+ * @timings: The timing inforamtion to print.
+*/
+static void s3c2410_print_timing(const char *pfx,
+                                 struct s3c_iotimings *timings)
+{
+        struct s3c2410_iobank_timing *bt;
+        int bank;
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = timings->bank[bank].io_2410;
+                if (!bt)
+                        continue;
+                printk(KERN_DEBUG "%s %d: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, "
+                       "Tcoh=%d.%d, Tcah=%d.%d\n", pfx, bank,
+                       print_ns(bt->tacs),
+                       print_ns(bt->tcos),
+                       print_ns(bt->tacc),
+                       print_ns(bt->tcoh),
+                       print_ns(bt->tcah));
+        }
+}
+/**
+ * bank_reg - convert bank number to pointer to the control register.
+ * @bank: The IO bank number.
+ */
+static inline void __iomem *bank_reg(unsigned int bank)
+{
+        return S3C2410_BANKCON0 + (bank << 2);
+}
+/**
+ * bank_is_io - test whether bank is used for IO
+ * @bankcon: The bank control register.
+ *
+ * This is a simplistic test to see if any BANKCON[x] is not an IO
+ * bank. It currently does not take into account whether BWSCON has
+ * an illegal width-setting in it, or if the pin connected to nCS[x]
+ * is actually being handled as a chip-select.
+ */
+static inline int bank_is_io(unsigned long bankcon)
+{
+        return !(bankcon & S3C2410_BANKCON_SDRAM);
+}
+/**
+ * to_div - convert cycle time to divisor
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ *
+ * Convert the given cycle time into the divisor to use to obtain it from
+ * HCLK.
+*/
+static inline unsigned int to_div(unsigned int cyc, unsigned int hclk_tns)
+{
+        if (cyc == 0)
+                return 0;
+        return DIV_ROUND_UP(cyc, hclk_tns);
+}
+/**
+ * calc_0124 - calculate divisor control for divisors that do /0, /1. /2 and /4
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @v: Pointer to register to alter.
+ * @shift: The shift to get to the control bits.
+ *
+ * Calculate the divisor, and turn it into the correct control bits to
+ * set in the result, @v.
+ */
+static unsigned int calc_0124(unsigned int cyc, unsigned long hclk_tns,
+                              unsigned long *v, int shift)
+{
+        unsigned int div = to_div(cyc, hclk_tns);
+        unsigned long val;
+        s3c_freq_iodbg("%s: cyc=%d, hclk=%lu, shift=%d => div %d\n",
+                       __func__, cyc, hclk_tns, shift, div);
+        switch (div) {
+        case 0:
+                val = 0;
+                break;
+        case 1:
+                val = 1;
+                break;
+        case 2:
+                val = 2;
+                break;
+        case 3:
+        case 4:
+                val = 3;
+                break;
+        default:
+                return -1;
+        }
+        *v |= val << shift;
+        return 0;
+}
+int calc_tacp(unsigned int cyc, unsigned long hclk, unsigned long *v)
+{
+        /* Currently no support for Tacp calculations. */
+        return 0;
+}
+/**
+ * calc_tacc - calculate divisor control for tacc.
+ * @cyc: The cycle time, in 10ths of nanoseconds.
+ * @nwait_en: IS nWAIT enabled for this bank.
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @v: Pointer to register to alter.
+ *
+ * Calculate the divisor control for tACC, taking into account whether
+ * the bank has nWAIT enabled. The result is used to modify the value
+ * pointed to by @v.
+*/
+static int calc_tacc(unsigned int cyc, int nwait_en,
+                     unsigned long hclk_tns, unsigned long *v)
+{
+        unsigned int div = to_div(cyc, hclk_tns);
+        unsigned long val;
+        s3c_freq_iodbg("%s: cyc=%u, nwait=%d, hclk=%lu => div=%u\n",
+                       __func__, cyc, nwait_en, hclk_tns, div);
+        /* if nWait enabled on an bank, Tacc must be at-least 4 cycles. */
+        if (nwait_en && div < 4)
+                div = 4;
+        switch (div) {
+        case 0:
+                val = 0;
+                break;
+        case 1:
+        case 2:
+        case 3:
+        case 4:
+                val = div - 1;
+                break;
+        case 5:
+        case 6:
+                val = 4;
+                break;
+        case 7:
+        case 8:
+                val = 5;
+                break;
+        case 9:
+        case 10:
+                val = 6;
+                break;
+        case 11:
+        case 12:
+        case 13:
+        case 14:
+                val = 7;
+                break;
+        default:
+                return -1;
+        }
+        *v |= val << 8;
+        return 0;
+}
+/**
+ * s3c2410_calc_bank - calculate bank timing infromation
+ * @cfg: The configuration we need to calculate for.
+ * @bt: The bank timing information.
+ *
+ * Given the cycle timine for a bank @bt, calculate the new BANKCON
+ * setting for the @cfg timing. This updates the timing information
+ * ready for the cpu frequency change.
+ */
+static int s3c2410_calc_bank(struct s3c_cpufreq_config *cfg,
+                             struct s3c2410_iobank_timing *bt)
+{
+        unsigned long hclk = cfg->freq.hclk_tns;
+        unsigned long res;
+        int ret;
+        res  = bt->bankcon;
+        res &= (S3C2410_BANKCON_SDRAM | S3C2410_BANKCON_PMC16);
+        /* tacp: 2,3,4,5 */
+        /* tcah: 0,1,2,4 */
+        /* tcoh: 0,1,2,4 */
+        /* tacc: 1,2,3,4,6,7,10,14 (>4 for nwait) */
+        /* tcos: 0,1,2,4 */
+        /* tacs: 0,1,2,4 */
+        ret  = calc_0124(bt->tacs, hclk, &res, S3C2410_BANKCON_Tacs_SHIFT);
+        ret |= calc_0124(bt->tcos, hclk, &res, S3C2410_BANKCON_Tcos_SHIFT);
+        ret |= calc_0124(bt->tcah, hclk, &res, S3C2410_BANKCON_Tcah_SHIFT);
+        ret |= calc_0124(bt->tcoh, hclk, &res, S3C2410_BANKCON_Tcoh_SHIFT);
+        if (ret)
+                return -EINVAL;
+        ret |= calc_tacp(bt->tacp, hclk, &res);
+        ret |= calc_tacc(bt->tacc, bt->nwait_en, hclk, &res);
+        if (ret)
+                return -EINVAL;
+        bt->bankcon = res;
+        return 0;
+}
+static unsigned int tacc_tab[] = {
+        [0]     = 1,
+        [1]     = 2,
+        [2]     = 3,
+        [3]     = 4,
+        [4]     = 6,
+        [5]     = 9,
+        [6]     = 10,
+        [7]     = 14,
+};
+/**
+ * get_tacc - turn tACC value into cycle time
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @val: The bank timing register value, shifed down.
+ */
+static unsigned int get_tacc(unsigned long hclk_tns,
+                             unsigned long val)
+{
+        val &= 7;
+        return hclk_tns * tacc_tab[val];
+}
+/**
+ * get_0124 - turn 0/1/2/4 divider into cycle time
+ * @hclk_tns: The cycle time for HCLK, in 10ths of nanoseconds.
+ * @val: The bank timing register value, shifed down.
+ */
+static unsigned int get_0124(unsigned long hclk_tns,
+                             unsigned long val)
+{
+        val &= 3;
+        return hclk_tns * ((val == 3) ? 4 : val);
+}
+/**
+ * s3c2410_iotiming_getbank - turn BANKCON into cycle time information
+ * @cfg: The frequency configuration
+ * @bt: The bank timing to fill in (uses cached BANKCON)
+ *
+ * Given the BANKCON setting in @bt and the current frequency settings
+ * in @cfg, update the cycle timing information.
+ */
+void s3c2410_iotiming_getbank(struct s3c_cpufreq_config *cfg,
+                              struct s3c2410_iobank_timing *bt)
+{
+        unsigned long bankcon = bt->bankcon;
+        unsigned long hclk = cfg->freq.hclk_tns;
+        bt->tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
+        bt->tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
+        bt->tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
+        bt->tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
+        bt->tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
+}
+/**
+ * s3c2410_iotiming_debugfs - debugfs show io bank timing information
+ * @seq: The seq_file to write output to using seq_printf().
+ * @cfg: The current configuration.
+ * @iob: The IO bank information to decode.
+ */
+void s3c2410_iotiming_debugfs(struct seq_file *seq,
+                              struct s3c_cpufreq_config *cfg,
+                              union s3c_iobank *iob)
+{
+        struct s3c2410_iobank_timing *bt = iob->io_2410;
+        unsigned long bankcon = bt->bankcon;
+        unsigned long hclk = cfg->freq.hclk_tns;
+        unsigned int tacs;
+        unsigned int tcos;
+        unsigned int tacc;
+        unsigned int tcoh;
+        unsigned int tcah;
+        seq_printf(seq, "BANKCON=0x%08lx\n", bankcon);
+        tcah = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcah_SHIFT);
+        tcoh = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcoh_SHIFT);
+        tcos = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tcos_SHIFT);
+        tacs = get_0124(hclk, bankcon >> S3C2410_BANKCON_Tacs_SHIFT);
+        tacc = get_tacc(hclk, bankcon >> S3C2410_BANKCON_Tacc_SHIFT);
+        seq_printf(seq,
+                   "\tRead: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
+                   print_ns(bt->tacs),
+                   print_ns(bt->tcos),
+                   print_ns(bt->tacc),
+                   print_ns(bt->tcoh),
+                   print_ns(bt->tcah));
+        seq_printf(seq,
+                   "\t Set: Tacs=%d.%d, Tcos=%d.%d, Tacc=%d.%d, Tcoh=%d.%d, Tcah=%d.%d\n",
+                   print_ns(tacs),
+                   print_ns(tcos),
+                   print_ns(tacc),
+                   print_ns(tcoh),
+                   print_ns(tcah));
+}
+/**
+ * s3c2410_iotiming_calc - Calculate bank timing for frequency change.
+ * @cfg: The frequency configuration
+ * @iot: The IO timing information to fill out.
+ *
+ * Calculate the new values for the banks in @iot based on the new
+ * frequency information in @cfg. This is then used by s3c2410_iotiming_set()
+ * to update the timing when necessary.
+ */
+int s3c2410_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2410_iobank_timing *bt;
+        unsigned long bankcon;
+        int bank;
+        int ret;
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bankcon = __raw_readl(bank_reg(bank));
+                bt = iot->bank[bank].io_2410;
+                if (!bt)
+                        continue;
+                bt->bankcon = bankcon;
+                ret = s3c2410_calc_bank(cfg, bt);
+                if (ret) {
+                        printk(KERN_ERR "%s: cannot calculate bank %d io\n",
+                               __func__, bank);
+                        goto err;
+                }
+                s3c_freq_iodbg("%s: bank %d: con=%08lx\n",
+                               __func__, bank, bt->bankcon);
+        }
+        return 0;
+ err:
+        return ret;
+}
+/**
+ * s3c2410_iotiming_set - set the IO timings from the given setup.
+ * @cfg: The frequency configuration
+ * @iot: The IO timing information to use.
+ *
+ * Set all the currently used IO bank timing information generated
+ * by s3c2410_iotiming_calc() once the core has validated that all
+ * the new values are within permitted bounds.
+ */
+void s3c2410_iotiming_set(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2410_iobank_timing *bt;
+        int bank;
+        /* set the io timings from the specifier */
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2410;
+                if (!bt)
+                        continue;
+                __raw_writel(bt->bankcon, bank_reg(bank));
+        }
+}
+/**
+ * s3c2410_iotiming_get - Get the timing information from current registers.
+ * @cfg: The frequency configuration
+ * @timings: The IO timing information to fill out.
+ *
+ * Calculate the @timings timing information from the current frequency
+ * information in @cfg, and the new frequency configur
+ * through all the IO banks, reading the state and then updating @iot
+ * as necessary.
+ *
+ * This is used at the moment on initialisation to get the current
+ * configuration so that boards do not have to carry their own setup
+ * if the timings are correct on initialisation.
+ */
+int s3c2410_iotiming_get(struct s3c_cpufreq_config *cfg,
+                         struct s3c_iotimings *timings)
+{
+        struct s3c2410_iobank_timing *bt;
+        unsigned long bankcon;
+        unsigned long bwscon;
+        int bank;
+        bwscon = __raw_readl(S3C2410_BWSCON);
+        /* look through all banks to see what is currently set. */
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bankcon = __raw_readl(bank_reg(bank));
+                if (!bank_is_io(bankcon))
+                        continue;
+                s3c_freq_iodbg("%s: bank %d: con %08lx\n",
+                               __func__, bank, bankcon);
+                bt = kzalloc(sizeof(struct s3c2410_iobank_timing), GFP_KERNEL);
+                if (!bt) {
+                        printk(KERN_ERR "%s: no memory for bank\n", __func__);
+                        return -ENOMEM;
+                }
+                /* find out in nWait is enabled for bank. */
+                if (bank != 0) {
+                        unsigned long tmp  = S3C2410_BWSCON_GET(bwscon, bank);
+                        if (tmp & S3C2410_BWSCON_WS)
+                                bt->nwait_en = 1;
+                }
+                timings->bank[bank].io_2410 = bt;
+                bt->bankcon = bankcon;
+                s3c2410_iotiming_getbank(cfg, bt);
+        }
+        s3c2410_print_timing("get", timings);
+        return 0;
+}
diff --git a/arch/arm/plat-s3c24xx/s3c2412-iotiming.c b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
new file mode 100644
index 000000000000..fd45e47facbc
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
@@ -0,0 +1,285 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2412-iotiming.c
+ *
+ * Copyright (c) 2006,2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2412/S3C2443 (PL093 based) IO timing support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/seq_file.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/amba/pl093.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/regs-s3c2412-mem.h>
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+#include <plat/clock.h>
+#define print_ns(x) ((x) / 10), ((x) % 10)
+/**
+ * s3c2412_print_timing - print timing infromation via printk.
+ * @pfx: The prefix to print each line with.
+ * @iot: The IO timing information
+ */
+static void s3c2412_print_timing(const char *pfx, struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        unsigned int bank;
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+                printk(KERN_DEBUG "%s: %d: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
+                       "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n", pfx, bank,
+                       print_ns(bt->idcy),
+                       print_ns(bt->wstrd),
+                       print_ns(bt->wstwr),
+                       print_ns(bt->wstoen),
+                       print_ns(bt->wstwen),
+                       print_ns(bt->wstbrd));
+        }
+}
+/**
+ * to_div - turn a cycle length into a divisor setting.
+ * @cyc_tns: The cycle time in 10ths of nanoseconds.
+ * @clk_tns: The clock period in 10ths of nanoseconds.
+ */
+static inline unsigned int to_div(unsigned int cyc_tns, unsigned int clk_tns)
+{
+        return cyc_tns ? DIV_ROUND_UP(cyc_tns, clk_tns) : 0;
+}
+/**
+ * calc_timing - calculate timing divisor value and check in range.
+ * @hwtm: The hardware timing in 10ths of nanoseconds.
+ * @clk_tns: The clock period in 10ths of nanoseconds.
+ * @err: Pointer to err variable to update in event of failure.
+ */
+static unsigned int calc_timing(unsigned int hwtm, unsigned int clk_tns,
+                                unsigned int *err)
+{
+        unsigned int ret = to_div(hwtm, clk_tns);
+        if (ret > 0xf)
+                *err = -EINVAL;
+        return ret;
+}
+/**
+ * s3c2412_calc_bank - calculate the bank divisor settings.
+ * @cfg: The current frequency configuration.
+ * @bt: The bank timing.
+ */
+static int s3c2412_calc_bank(struct s3c_cpufreq_config *cfg,
+                             struct s3c2412_iobank_timing *bt)
+{
+        unsigned int hclk = cfg->freq.hclk_tns;
+        int err = 0;
+        bt->smbidcyr = calc_timing(bt->idcy, hclk, &err);
+        bt->smbwstrd = calc_timing(bt->wstrd, hclk, &err);
+        bt->smbwstwr = calc_timing(bt->wstwr, hclk, &err);
+        bt->smbwstoen = calc_timing(bt->wstoen, hclk, &err);
+        bt->smbwstwen = calc_timing(bt->wstwen, hclk, &err);
+        bt->smbwstbrd = calc_timing(bt->wstbrd, hclk, &err);
+        return err;
+}
+/**
+ * s3c2412_iotiming_debugfs - debugfs show io bank timing information
+ * @seq: The seq_file to write output to using seq_printf().
+ * @cfg: The current configuration.
+ * @iob: The IO bank information to decode.
+*/
+void s3c2412_iotiming_debugfs(struct seq_file *seq,
+                              struct s3c_cpufreq_config *cfg,
+                              union s3c_iobank *iob)
+{
+        struct s3c2412_iobank_timing *bt = iob->io_2412;
+        seq_printf(seq,
+                   "\tRead: idcy=%d.%d wstrd=%d.%d wstwr=%d,%d"
+                   "wstoen=%d.%d wstwen=%d.%d wstbrd=%d.%d\n",
+                   print_ns(bt->idcy),
+                   print_ns(bt->wstrd),
+                   print_ns(bt->wstwr),
+                   print_ns(bt->wstoen),
+                   print_ns(bt->wstwen),
+                   print_ns(bt->wstbrd));
+}
+/**
+ * s3c2412_iotiming_calc - calculate all the bank divisor settings.
+ * @cfg: The current frequency configuration.
+ * @iot: The bank timing information.
+ *
+ * Calculate the timing information for all the banks that are
+ * configured as IO, using s3c2412_calc_bank().
+ */
+int s3c2412_iotiming_calc(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        int bank;
+        int ret;
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+                ret = s3c2412_calc_bank(cfg, bt);
+                if (ret) {
+                        printk(KERN_ERR "%s: cannot calculate bank %d io\n",
+                               __func__, bank);
+                        goto err;
+                }
+        }
+        return 0;
+ err:
+        return ret;
+}
+/**
+ * s3c2412_iotiming_set - set the timing information
+ * @cfg: The current frequency configuration.
+ * @iot: The bank timing information.
+ *
+ * Set the IO bank information from the details calculated earlier from
+ * calling s3c2412_iotiming_calc().
+ */
+void s3c2412_iotiming_set(struct s3c_cpufreq_config *cfg,
+                          struct s3c_iotimings *iot)
+{
+        struct s3c2412_iobank_timing *bt;
+        void __iomem *regs;
+        int bank;
+        /* set the io timings from the specifier */
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                bt = iot->bank[bank].io_2412;
+                if (!bt)
+                        continue;
+                regs = S3C2412_SSMC_BANK(bank);
+                __raw_writel(bt->smbidcyr, regs + SMBIDCYR);
+                __raw_writel(bt->smbwstrd, regs + SMBWSTRDR);
+                __raw_writel(bt->smbwstwr, regs + SMBWSTWRR);
+                __raw_writel(bt->smbwstoen, regs + SMBWSTOENR);
+                __raw_writel(bt->smbwstwen, regs + SMBWSTWENR);
+                __raw_writel(bt->smbwstbrd, regs + SMBWSTBRDR);
+        }
+}
+static inline unsigned int s3c2412_decode_timing(unsigned int clock, u32 reg)
+{
+        return (reg & 0xf) * clock;
+}
+static void s3c2412_iotiming_getbank(struct s3c_cpufreq_config *cfg,
+                                     struct s3c2412_iobank_timing *bt,
+                                     unsigned int bank)
+{
+        unsigned long clk = cfg->freq.hclk_tns;  /* ssmc clock??? */
+        void __iomem *regs = S3C2412_SSMC_BANK(bank);
+        bt->idcy = s3c2412_decode_timing(clk, __raw_readl(regs + SMBIDCYR));
+        bt->wstrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTRDR));
+        bt->wstoen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTOENR));
+        bt->wstwen = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTWENR));
+        bt->wstbrd = s3c2412_decode_timing(clk, __raw_readl(regs + SMBWSTBRDR));
+}
+/**
+ * bank_is_io - return true if bank is (possibly) IO.
+ * @bank: The bank number.
+ * @bankcfg: The value of S3C2412_EBI_BANKCFG.
+ */
+static inline bool bank_is_io(unsigned int bank, u32 bankcfg)
+{
+        if (bank < 2)
+                return true;
+        return !(bankcfg & (1 << bank));
+}
+int s3c2412_iotiming_get(struct s3c_cpufreq_config *cfg,
+                         struct s3c_iotimings *timings)
+{
+        struct s3c2412_iobank_timing *bt;
+        u32 bankcfg = __raw_readl(S3C2412_EBI_BANKCFG);
+        unsigned int bank;
+        /* look through all banks to see what is currently set. */
+        for (bank = 0; bank < MAX_BANKS; bank++) {
+                if (!bank_is_io(bank, bankcfg))
+                        continue;
+                bt = kzalloc(sizeof(struct s3c2412_iobank_timing), GFP_KERNEL);
+                if (!bt) {
+                        printk(KERN_ERR "%s: no memory for bank\n", __func__);
+                        return -ENOMEM;
+                }
+                timings->bank[bank].io_2412 = bt;
+                s3c2412_iotiming_getbank(cfg, bt, bank);
+        }
+        s3c2412_print_timing("get", timings);
+        return 0;
+}
+/* this is in here as it is so small, it doesn't currently warrant a file
+ * to itself. We expect that any s3c24xx needing this is going to also
+ * need the iotiming support.
+ */
+void s3c2412_cpufreq_setrefresh(struct s3c_cpufreq_config *cfg)
+{
+        struct s3c_cpufreq_board *board = cfg->board;
+        u32 refresh;
+        WARN_ON(board == NULL);
+        /* Reduce both the refresh time (in ns) and the frequency (in MHz)
+         * down to ensure that we do not overflow 32 bit numbers.
+         *
+         * This should work for HCLK up to 133MHz and refresh period up
+         * to 30usec.
+         */
+        refresh = (cfg->freq.hclk / 100) * (board->refresh / 10);
+        refresh = DIV_ROUND_UP(refresh, (1000 * 1000)); /* apply scale  */
+        refresh &= ((1 << 16) - 1);
+        s3c_freq_dbg("%s: refresh value %u\n", __func__, (unsigned int)refresh);
+        __raw_writel(refresh, S3C2412_REFRESH);
+}
diff --git a/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
new file mode 100644
index 000000000000..ae2e6c604f27
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
@@ -0,0 +1,311 @@
+/* linux/arch/arm/plat-s3c24xx/s3c2440-cpufreq.c
+ *
+ * Copyright (c) 2006,2008,2009 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@simtec.co.uk>
+ *
+ * S3C2440/S3C2442 CPU Frequency scaling
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/cpufreq.h>
+#include <linux/sysdev.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/regs-clock.h>
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+#include <plat/clock.h>
+static struct clk *xtal;
+static struct clk *fclk;
+static struct clk *hclk;
+static struct clk *armclk;
+/* HDIV: 1, 2, 3, 4, 6, 8 */
+static inline int within_khz(unsigned long a, unsigned long b)
+{
+        long diff = a - b;
+        return (diff >= -1000 && diff <= 1000);
+}
+/**
+ * s3c2440_cpufreq_calcdivs - calculate divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Calcualte the divider values for the given frequency settings
+ * specified in @cfg. The values are stored in @cfg for later use
+ * by the relevant set routine if the request settings can be reached.
+ */
+int s3c2440_cpufreq_calcdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned int hdiv, pdiv;
+        unsigned long hclk, fclk, armclk;
+        unsigned long hclk_max;
+        fclk = cfg->freq.fclk;
+        armclk = cfg->freq.armclk;
+        hclk_max = cfg->max.hclk;
+        s3c_freq_dbg("%s: fclk is %lu, armclk %lu, max hclk %lu\n",
+                     __func__, fclk, armclk, hclk_max);
+        if (armclk > fclk) {
+                printk(KERN_WARNING "%s: armclk > fclk\n", __func__);
+                armclk = fclk;
+        }
+        /* if we are in DVS, we need HCLK to be <= ARMCLK */
+        if (armclk < fclk && armclk < hclk_max)
+                hclk_max = armclk;
+        for (hdiv = 1; hdiv < 9; hdiv++) {
+                if (hdiv == 5 || hdiv == 7)
+                        hdiv++;
+                hclk = (fclk / hdiv);
+                if (hclk <= hclk_max || within_khz(hclk, hclk_max))
+                        break;
+        }
+        s3c_freq_dbg("%s: hclk %lu, div %d\n", __func__, hclk, hdiv);
+        if (hdiv > 8)
+                goto invalid;
+        pdiv = (hclk > cfg->max.pclk) ? 2 : 1;
+        if ((hclk / pdiv) > cfg->max.pclk)
+                pdiv++;
+        s3c_freq_dbg("%s: pdiv %d\n", __func__, pdiv);
+        if (pdiv > 2)
+                goto invalid;
+        pdiv *= hdiv;
+        /* calculate a valid armclk */
+        if (armclk < hclk)
+                armclk = hclk;
+        /* if we're running armclk lower than fclk, this really means
+         * that the system should go into dvs mode, which means that
+         * armclk is connected to hclk. */
+        if (armclk < fclk) {
+                cfg->divs.dvs = 1;
+                armclk = hclk;
+        } else
+                cfg->divs.dvs = 0;
+        cfg->freq.armclk = armclk;
+        /* store the result, and then return */
+        cfg->divs.h_divisor = hdiv;
+        cfg->divs.p_divisor = pdiv;
+        return 0;
+ invalid:
+        return -EINVAL;
+}
+#define CAMDIVN_HCLK_HALF (S3C2440_CAMDIVN_HCLK3_HALF | \
+                           S3C2440_CAMDIVN_HCLK4_HALF)
+/**
+ * s3c2440_cpufreq_setdivs - set the cpu frequency divider settings
+ * @cfg: The cpu frequency settings.
+ *
+ * Set the divisors from the settings in @cfg, which where generated
+ * during the calculation phase by s3c2440_cpufreq_calcdivs().
+ */
+static void s3c2440_cpufreq_setdivs(struct s3c_cpufreq_config *cfg)
+{
+        unsigned long clkdiv, camdiv;
+        s3c_freq_dbg("%s: divsiors: h=%d, p=%d\n", __func__,
+                     cfg->divs.h_divisor, cfg->divs.p_divisor);
+        clkdiv = __raw_readl(S3C2410_CLKDIVN);
+        camdiv = __raw_readl(S3C2440_CAMDIVN);
+        clkdiv &= ~(S3C2440_CLKDIVN_HDIVN_MASK | S3C2440_CLKDIVN_PDIVN);
+        camdiv &= ~CAMDIVN_HCLK_HALF;
+        switch (cfg->divs.h_divisor) {
+        case 1:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_1;
+                break;
+        case 2:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_2;
+                break;
+        case 6:
+                camdiv |= S3C2440_CAMDIVN_HCLK3_HALF;
+        case 3:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_3_6;
+                break;
+        case 8:
+                camdiv |= S3C2440_CAMDIVN_HCLK4_HALF;
+        case 4:
+                clkdiv |= S3C2440_CLKDIVN_HDIVN_4_8;
+                break;
+        default:
+                BUG();  /* we don't expect to get here. */
+        }
+        if (cfg->divs.p_divisor != cfg->divs.h_divisor)
+                clkdiv |= S3C2440_CLKDIVN_PDIVN;
+        /* todo - set pclk. */
+        /* Write the divisors first with hclk intentionally halved so that
+         * when we write clkdiv we will under-frequency instead of over. We
+         * then make a short delay and remove the hclk halving if necessary.
+         */
+        __raw_writel(camdiv | CAMDIVN_HCLK_HALF, S3C2440_CAMDIVN);
+        __raw_writel(clkdiv, S3C2410_CLKDIVN);
+        ndelay(20);
+        __raw_writel(camdiv, S3C2440_CAMDIVN);
+        clk_set_parent(armclk, cfg->divs.dvs ? hclk : fclk);
+}
+static int run_freq_for(unsigned long max_hclk, unsigned long fclk,
+                        int *divs,
+                        struct cpufreq_frequency_table *table,
+                        size_t table_size)
+{
+        unsigned long freq;
+        int index = 0;
+        int div;
+        for (div = *divs; div > 0; div = *divs++) {
+                freq = fclk / div;
+                if (freq > max_hclk && div != 1)
+                        continue;
+                freq /= 1000; /* table is in kHz */
+                index = s3c_cpufreq_addfreq(table, index, table_size, freq);
+                if (index < 0)
+                        break;
+        }
+        return index;
+}
+static int hclk_divs[] = { 1, 2, 3, 4, 6, 8, -1 };
+static int s3c2440_cpufreq_calctable(struct s3c_cpufreq_config *cfg,
+                                     struct cpufreq_frequency_table *table,
+                                     size_t table_size)
+{
+        int ret;
+        WARN_ON(cfg->info == NULL);
+        WARN_ON(cfg->board == NULL);
+        ret = run_freq_for(cfg->info->max.hclk,
+                           cfg->info->max.fclk,
+                           hclk_divs,
+                           table, table_size);
+        s3c_freq_dbg("%s: returning %d\n", __func__, ret);
+        return ret;
+}
+struct s3c_cpufreq_info s3c2440_cpufreq_info = {
+        .max            = {
+                .fclk   = 400000000,
+                .hclk   = 133333333,
+                .pclk   =  66666666,
+        },
+        .locktime_m     = 300,
+        .locktime_u     = 300,
+        .locktime_bits  = 16,
+        .name           = "s3c244x",
+        .calc_iotiming  = s3c2410_iotiming_calc,
+        .set_iotiming   = s3c2410_iotiming_set,
+        .get_iotiming   = s3c2410_iotiming_get,
+        .set_fvco       = s3c2410_set_fvco,
+        .set_refresh    = s3c2410_cpufreq_setrefresh,
+        .set_divs       = s3c2440_cpufreq_setdivs,
+        .calc_divs      = s3c2440_cpufreq_calcdivs,
+        .calc_freqtable = s3c2440_cpufreq_calctable,
+        .resume_clocks  = s3c244x_setup_clocks,
+        .debug_io_show  = s3c_cpufreq_debugfs_call(s3c2410_iotiming_debugfs),
+};
+static int s3c2440_cpufreq_add(struct sys_device *sysdev)
+{
+        xtal = s3c_cpufreq_clk_get(NULL, "xtal");
+        hclk = s3c_cpufreq_clk_get(NULL, "hclk");
+        fclk = s3c_cpufreq_clk_get(NULL, "fclk");
+        armclk = s3c_cpufreq_clk_get(NULL, "armclk");
+        if (IS_ERR(xtal) || IS_ERR(hclk) || IS_ERR(fclk) || IS_ERR(armclk)) {
+                printk(KERN_ERR "%s: failed to get clocks\n", __func__);
+                return -ENOENT;
+        }
+        return s3c_cpufreq_register(&s3c2440_cpufreq_info);
+}
+static struct sysdev_driver s3c2440_cpufreq_driver = {
+        .add            = s3c2440_cpufreq_add,
+};
+static int s3c2440_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2440_sysclass,
+                                      &s3c2440_cpufreq_driver);
+}
+/* arch_initcall adds the clocks we need, so use subsys_initcall. */
+subsys_initcall(s3c2440_cpufreq_init);
+static struct sysdev_driver s3c2442_cpufreq_driver = {
+        .add            = s3c2440_cpufreq_add,
+};
+static int s3c2442_cpufreq_init(void)
+{
+        return sysdev_driver_register(&s3c2442_sysclass,
+                                      &s3c2442_cpufreq_driver);
+}
+subsys_initcall(s3c2442_cpufreq_init);
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
new file mode 100644
index 000000000000..ff9443b233aa
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
@@ -0,0 +1,97 @@
+/* arch/arm/plat-s3c24xx/s3c2440-pll-12000000.c
+ *
+ * Copyright (c) 2006,2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+static struct cpufreq_frequency_table s3c2440_plls_12[] __initdata = {
+        { .frequency = 75000000,        .index = PLLVAL(0x75, 3, 3),  },        /* FVco 600.000000 */
+        { .frequency = 80000000,        .index = PLLVAL(0x98, 4, 3),  },        /* FVco 640.000000 */
+        { .frequency = 90000000,        .index = PLLVAL(0x70, 2, 3),  },        /* FVco 720.000000 */
+        { .frequency = 100000000,       .index = PLLVAL(0x5c, 1, 3),  },        /* FVco 800.000000 */
+        { .frequency = 110000000,       .index = PLLVAL(0x66, 1, 3),  },        /* FVco 880.000000 */
+        { .frequency = 120000000,       .index = PLLVAL(0x70, 1, 3),  },        /* FVco 960.000000 */
+        { .frequency = 150000000,       .index = PLLVAL(0x75, 3, 2),  },        /* FVco 600.000000 */
+        { .frequency = 160000000,       .index = PLLVAL(0x98, 4, 2),  },        /* FVco 640.000000 */
+        { .frequency = 170000000,       .index = PLLVAL(0x4d, 1, 2),  },        /* FVco 680.000000 */
+        { .frequency = 180000000,       .index = PLLVAL(0x70, 2, 2),  },        /* FVco 720.000000 */
+        { .frequency = 190000000,       .index = PLLVAL(0x57, 1, 2),  },        /* FVco 760.000000 */
+        { .frequency = 200000000,       .index = PLLVAL(0x5c, 1, 2),  },        /* FVco 800.000000 */
+        { .frequency = 210000000,       .index = PLLVAL(0x84, 2, 2),  },        /* FVco 840.000000 */
+        { .frequency = 220000000,       .index = PLLVAL(0x66, 1, 2),  },        /* FVco 880.000000 */
+        { .frequency = 230000000,       .index = PLLVAL(0x6b, 1, 2),  },        /* FVco 920.000000 */
+        { .frequency = 240000000,       .index = PLLVAL(0x70, 1, 2),  },        /* FVco 960.000000 */
+        { .frequency = 300000000,       .index = PLLVAL(0x75, 3, 1),  },        /* FVco 600.000000 */
+        { .frequency = 310000000,       .index = PLLVAL(0x93, 4, 1),  },        /* FVco 620.000000 */
+        { .frequency = 320000000,       .index = PLLVAL(0x98, 4, 1),  },        /* FVco 640.000000 */
+        { .frequency = 330000000,       .index = PLLVAL(0x66, 2, 1),  },        /* FVco 660.000000 */
+        { .frequency = 340000000,       .index = PLLVAL(0x4d, 1, 1),  },        /* FVco 680.000000 */
+        { .frequency = 350000000,       .index = PLLVAL(0xa7, 4, 1),  },        /* FVco 700.000000 */
+        { .frequency = 360000000,       .index = PLLVAL(0x70, 2, 1),  },        /* FVco 720.000000 */
+        { .frequency = 370000000,       .index = PLLVAL(0xb1, 4, 1),  },        /* FVco 740.000000 */
+        { .frequency = 380000000,       .index = PLLVAL(0x57, 1, 1),  },        /* FVco 760.000000 */
+        { .frequency = 390000000,       .index = PLLVAL(0x7a, 2, 1),  },        /* FVco 780.000000 */
+        { .frequency = 400000000,       .index = PLLVAL(0x5c, 1, 1),  },        /* FVco 800.000000 */
+};
+static int s3c2440_plls12_add(struct sys_device *dev)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+        if (xtal == 12000000) {
+                printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_12,
+                                           ARRAY_SIZE(s3c2440_plls_12));
+        }
+        return 0;
+}
+static struct sysdev_driver s3c2440_plls12_drv = {
+        .add    = s3c2440_plls12_add,
+};
+static int __init s3c2440_pll_12mhz(void)
+{
+        return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_plls12_drv);
+}
+arch_initcall(s3c2440_pll_12mhz);
+static struct sysdev_driver s3c2442_plls12_drv = {
+        .add    = s3c2440_plls12_add,
+};
+static int __init s3c2442_pll_12mhz(void)
+{
+        return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_plls12_drv);
+}
+arch_initcall(s3c2442_pll_12mhz);
diff --git a/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
new file mode 100644
index 000000000000..7679af13a94d
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
@@ -0,0 +1,127 @@
+/* arch/arm/plat-s3c24xx/s3c2440-pll-16934400.c
+ *
+ * Copyright (c) 2006-2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@arm.linux.org.uk>
+ *
+ * S3C2440/S3C2442 CPU PLL tables (16.93444MHz Crystal)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sysdev.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <plat/cpu.h>
+#include <plat/cpu-freq-core.h>
+static struct cpufreq_frequency_table s3c2440_plls_169344[] __initdata = {
+        { .frequency = 78019200,        .index = PLLVAL(121, 5, 3),     },      /* FVco 624.153600 */
+        { .frequency = 84067200,        .index = PLLVAL(131, 5, 3),     },      /* FVco 672.537600 */
+        { .frequency = 90115200,        .index = PLLVAL(141, 5, 3),     },      /* FVco 720.921600 */
+        { .frequency = 96163200,        .index = PLLVAL(151, 5, 3),     },      /* FVco 769.305600 */
+        { .frequency = 102135600,       .index = PLLVAL(185, 6, 3),     },      /* FVco 817.084800 */
+        { .frequency = 108259200,       .index = PLLVAL(171, 5, 3),     },      /* FVco 866.073600 */
+        { .frequency = 114307200,       .index = PLLVAL(127, 3, 3),     },      /* FVco 914.457600 */
+        { .frequency = 120234240,       .index = PLLVAL(134, 3, 3),     },      /* FVco 961.873920 */
+        { .frequency = 126161280,       .index = PLLVAL(141, 3, 3),     },      /* FVco 1009.290240 */
+        { .frequency = 132088320,       .index = PLLVAL(148, 3, 3),     },      /* FVco 1056.706560 */
+        { .frequency = 138015360,       .index = PLLVAL(155, 3, 3),     },      /* FVco 1104.122880 */
+        { .frequency = 144789120,       .index = PLLVAL(163, 3, 3),     },      /* FVco 1158.312960 */
+        { .frequency = 150100363,       .index = PLLVAL(187, 9, 2),     },      /* FVco 600.401454 */
+        { .frequency = 156038400,       .index = PLLVAL(121, 5, 2),     },      /* FVco 624.153600 */
+        { .frequency = 162086400,       .index = PLLVAL(126, 5, 2),     },      /* FVco 648.345600 */
+        { .frequency = 168134400,       .index = PLLVAL(131, 5, 2),     },      /* FVco 672.537600 */
+        { .frequency = 174048000,       .index = PLLVAL(177, 7, 2),     },      /* FVco 696.192000 */
+        { .frequency = 180230400,       .index = PLLVAL(141, 5, 2),     },      /* FVco 720.921600 */
+        { .frequency = 186278400,       .index = PLLVAL(124, 4, 2),     },      /* FVco 745.113600 */
+        { .frequency = 192326400,       .index = PLLVAL(151, 5, 2),     },      /* FVco 769.305600 */
+        { .frequency = 198132480,       .index = PLLVAL(109, 3, 2),     },      /* FVco 792.529920 */
+        { .frequency = 204271200,       .index = PLLVAL(185, 6, 2),     },      /* FVco 817.084800 */
+        { .frequency = 210268800,       .index = PLLVAL(141, 4, 2),     },      /* FVco 841.075200 */
+        { .frequency = 216518400,       .index = PLLVAL(171, 5, 2),     },      /* FVco 866.073600 */
+        { .frequency = 222264000,       .index = PLLVAL(97, 2, 2),      },      /* FVco 889.056000 */
+        { .frequency = 228614400,       .index = PLLVAL(127, 3, 2),     },      /* FVco 914.457600 */
+        { .frequency = 234259200,       .index = PLLVAL(158, 4, 2),     },      /* FVco 937.036800 */
+        { .frequency = 240468480,       .index = PLLVAL(134, 3, 2),     },      /* FVco 961.873920 */
+        { .frequency = 246960000,       .index = PLLVAL(167, 4, 2),     },      /* FVco 987.840000 */
+        { .frequency = 252322560,       .index = PLLVAL(141, 3, 2),     },      /* FVco 1009.290240 */
+        { .frequency = 258249600,       .index = PLLVAL(114, 2, 2),     },      /* FVco 1032.998400 */
+        { .frequency = 264176640,       .index = PLLVAL(148, 3, 2),     },      /* FVco 1056.706560 */
+        { .frequency = 270950400,       .index = PLLVAL(120, 2, 2),     },      /* FVco 1083.801600 */
+        { .frequency = 276030720,       .index = PLLVAL(155, 3, 2),     },      /* FVco 1104.122880 */
+        { .frequency = 282240000,       .index = PLLVAL(92, 1, 2),      },      /* FVco 1128.960000 */
+        { .frequency = 289578240,       .index = PLLVAL(163, 3, 2),     },      /* FVco 1158.312960 */
+        { .frequency = 294235200,       .index = PLLVAL(131, 2, 2),     },      /* FVco 1176.940800 */
+        { .frequency = 300200727,       .index = PLLVAL(187, 9, 1),     },      /* FVco 600.401454 */
+        { .frequency = 306358690,       .index = PLLVAL(191, 9, 1),     },      /* FVco 612.717380 */
+        { .frequency = 312076800,       .index = PLLVAL(121, 5, 1),     },      /* FVco 624.153600 */
+        { .frequency = 318366720,       .index = PLLVAL(86, 3, 1),      },      /* FVco 636.733440 */
+        { .frequency = 324172800,       .index = PLLVAL(126, 5, 1),     },      /* FVco 648.345600 */
+        { .frequency = 330220800,       .index = PLLVAL(109, 4, 1),     },      /* FVco 660.441600 */
+        { .frequency = 336268800,       .index = PLLVAL(131, 5, 1),     },      /* FVco 672.537600 */
+        { .frequency = 342074880,       .index = PLLVAL(93, 3, 1),      },      /* FVco 684.149760 */
+        { .frequency = 348096000,       .index = PLLVAL(177, 7, 1),     },      /* FVco 696.192000 */
+        { .frequency = 355622400,       .index = PLLVAL(118, 4, 1),     },      /* FVco 711.244800 */
+        { .frequency = 360460800,       .index = PLLVAL(141, 5, 1),     },      /* FVco 720.921600 */
+        { .frequency = 366206400,       .index = PLLVAL(165, 6, 1),     },      /* FVco 732.412800 */
+        { .frequency = 372556800,       .index = PLLVAL(124, 4, 1),     },      /* FVco 745.113600 */
+        { .frequency = 378201600,       .index = PLLVAL(126, 4, 1),     },      /* FVco 756.403200 */
+        { .frequency = 384652800,       .index = PLLVAL(151, 5, 1),     },      /* FVco 769.305600 */
+        { .frequency = 391608000,       .index = PLLVAL(177, 6, 1),     },      /* FVco 783.216000 */
+        { .frequency = 396264960,       .index = PLLVAL(109, 3, 1),     },      /* FVco 792.529920 */
+        { .frequency = 402192000,       .index = PLLVAL(87, 2, 1),      },      /* FVco 804.384000 */
+};
+static int s3c2440_plls169344_add(struct sys_device *dev)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+        xtal_clk = clk_get(NULL, "xtal");
+        if (IS_ERR(xtal_clk))
+                return PTR_ERR(xtal_clk);
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+        if (xtal == 169344000) {
+                printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
+                return s3c_plltab_register(s3c2440_plls_169344,
+                                           ARRAY_SIZE(s3c2440_plls_169344));
+        }
+        return 0;
+}
+static struct sysdev_driver s3c2440_plls169344_drv = {
+        .add    = s3c2440_plls169344_add,
+};
+static int __init s3c2440_pll_16934400(void)
+{
+        return sysdev_driver_register(&s3c2440_sysclass,
+                                      &s3c2440_plls169344_drv);
+}
+arch_initcall(s3c2440_pll_16934400);
+static struct sysdev_driver s3c2442_plls169344_drv = {
+        .add    = s3c2440_plls169344_add,
+};
+static int __init s3c2442_pll_16934400(void)
+{
+        return sysdev_driver_register(&s3c2442_sysclass,
+                                      &s3c2442_plls169344_drv);
+}
+arch_initcall(s3c2442_pll_16934400);
diff --git a/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
new file mode 100644
index 000000000000..89fcf5308cf6
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/spi-bus1-gpd8_9_10.c
@@ -0,0 +1,38 @@
+/* linux/arch/arm/plat-s3c24xx/spi-bus0-gpd8_9_10.c
+ *
+ * Copyright (c) 2008 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C24XX SPI - gpio configuration for bus 1 on gpd8,9,10
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+*/
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <mach/spi.h>
+#include <mach/regs-gpio.h>
+void s3c24xx_spi_gpiocfg_bus1_gpd8_9_10(struct s3c2410_spi_info *spi,
+                                        int enable)
+{
+        printk(KERN_INFO "%s(%d)\n", __func__, enable);
+        if (enable) {
+                s3c2410_gpio_cfgpin(S3C2410_GPD(10), S3C2440_GPD10_SPICLK1);
+                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2440_GPD9_SPIMOSI1);
+                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2440_GPD8_SPIMISO1);
+                s3c2410_gpio_pullup(S3C2410_GPD(10), 0);
+                s3c2410_gpio_pullup(S3C2410_GPD(9), 0);
+        } else {
+                s3c2410_gpio_cfgpin(S3C2410_GPD(8), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_cfgpin(S3C2410_GPD(9), S3C2410_GPIO_INPUT);
+                s3c2410_gpio_pullup(S3C2410_GPD(10), 1);
+                s3c2410_gpio_pullup(S3C2410_GPD(9), 1);
+                s3c2410_gpio_pullup(S3C2410_GPD(8), 1);
+        }
+}
diff --git a/arch/arm/plat-s3c64xx/Kconfig b/arch/arm/plat-s3c64xx/Kconfig
index 5ebd8b425a54..bcfa778614d8 100644
--- a/arch/arm/plat-s3c64xx/Kconfig
+++ b/arch/arm/plat-s3c64xx/Kconfig
@@ -19,6 +19,7 @@ config PLAT_S3C64XX
        select S3C_GPIO_PULL_UPDOWN
        select S3C_GPIO_CFG_S3C24XX
        select S3C_GPIO_CFG_S3C64XX
+        select S3C_DEV_NAND
        select USB_ARCH_HAS_OHCI
        help
          Base platform code for any Samsung S3C64XX device
diff --git a/arch/arm/plat-s3c64xx/Makefile b/arch/arm/plat-s3c64xx/Makefile
index 3c8882cd6268..b85b4359e935 100644
--- a/arch/arm/plat-s3c64xx/Makefile
+++ b/arch/arm/plat-s3c64xx/Makefile
@@ -40,4 +40,5 @@ obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
 obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
 obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
-obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
-\ No newline at end of file
+obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+obj-$(CONFIG_SND_S3C24XX_SOC) += dev-audio.o
diff --git a/arch/arm/plat-s3c/dev-audio.c b/arch/arm/plat-s3c64xx/dev-audio.c
index 1322beb40dd7..1322beb40dd7 100644
--- a/arch/arm/plat-s3c/dev-audio.c
+++ b/arch/arm/plat-s3c64xx/dev-audio.c
diff --git a/arch/arm/plat-s5pc1xx/Kconfig b/arch/arm/plat-s5pc1xx/Kconfig
new file mode 100644
index 000000000000..a8a711c3c064
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/Kconfig
@@ -0,0 +1,50 @@
+# arch/arm/plat-s5pc1xx/Kconfig
+#
+# Copyright 2009 Samsung Electronics Co.
+#       Byungho Min <bhmin@samsung.com>
+#
+# Licensed under GPLv2
+config PLAT_S5PC1XX
+        bool
+        depends on ARCH_S5PC1XX
+        default y
+        select PLAT_S3C
+        select ARM_VIC
+        select NO_IOPORT
+        select ARCH_REQUIRE_GPIOLIB
+        select S3C_GPIO_TRACK
+        select S3C_GPIO_PULL_UPDOWN
+        help
+          Base platform code for any Samsung S5PC1XX device
+if PLAT_S5PC1XX
+# Configuration options shared by all S3C64XX implementations
+config CPU_S5PC100_INIT
+        bool
+        help
+          Common initialisation code for the S5PC1XX
+config CPU_S5PC100_CLOCK
+        bool
+        help
+          Common clock support code for the S5PC1XX
+# platform specific device setup
+config S5PC100_SETUP_I2C0
+        bool
+        default y
+        help
+          Common setup code for i2c bus 0.
+          Note, currently since i2c0 is always compiled, this setup helper
+          is always compiled with it.
+config S5PC100_SETUP_I2C1
+        bool
+        help
+          Common setup code for i2c bus 1.
+endif
diff --git a/arch/arm/plat-s5pc1xx/Makefile b/arch/arm/plat-s5pc1xx/Makefile
new file mode 100644
index 000000000000..f1ecb2c37ee2
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/Makefile
@@ -0,0 +1,26 @@
+# arch/arm/plat-s5pc1xx/Makefile
+#
+# Copyright 2009 Samsung Electronics Co.
+#
+# Licensed under GPLv2
+obj-y                           :=
+obj-m                           :=
+obj-n                           := dummy.o
+obj-                            :=
+# Core files
+obj-y                           += dev-uart.o
+obj-y                           += cpu.o
+obj-y                           += irq.o
+# CPU support
+obj-$(CONFIG_CPU_S5PC100_INIT)  += s5pc100-init.o
+obj-$(CONFIG_CPU_S5PC100_CLOCK) += s5pc100-clock.o
+# Device setup
+obj-$(CONFIG_S5PC100_SETUP_I2C0) += setup-i2c0.o
+obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
diff --git a/arch/arm/plat-s5pc1xx/cpu.c b/arch/arm/plat-s5pc1xx/cpu.c
new file mode 100644
index 000000000000..715a7330794d
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/cpu.c
@@ -0,0 +1,112 @@
+/* linux/arch/arm/plat-s5pc1xx/cpu.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX CPU Support
+ *
+ * Based on plat-s3c64xx/cpu.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <asm/mach/map.h>
+#include <plat/regs-serial.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/clock.h>
+#include <plat/s5pc100.h>
+/* table of supported CPUs */
+static const char name_s5pc100[] = "S5PC100";
+static struct cpu_table cpu_ids[] __initdata = {
+        {
+                .idcode         = 0x43100000,
+                .idmask         = 0xfffff000,
+                .map_io         = s5pc100_map_io,
+                .init_clocks    = s5pc100_init_clocks,
+                .init_uarts     = s5pc100_init_uarts,
+                .init           = s5pc100_init,
+                .name           = name_s5pc100,
+        },
+};
+/* minimal IO mapping */
+/* see notes on uart map in arch/arm/mach-s5pc100/include/mach/debug-macro.S */
+#define UART_OFFS (S3C_PA_UART & 0xffff)
+static struct map_desc s5pc1xx_iodesc[] __initdata = {
+        {
+                .virtual        = (unsigned long)S5PC1XX_VA_CHIPID,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_CHIPID),
+                .length         = SZ_16,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_CLK,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_CLK),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_PWR,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_PWR),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)(S5PC1XX_VA_UART),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_UART),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_VIC(0),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(0)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_VIC(1),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(1)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_VIC(2),
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_VIC(2)),
+                .length         = SZ_4K,
+                .type           = MT_DEVICE,
+        }, {
+                .virtual        = (unsigned long)S5PC1XX_VA_TIMER,
+                .pfn            = __phys_to_pfn(S5PC1XX_PA_TIMER),
+                .length         = SZ_256,
+                .type           = MT_DEVICE,
+        },
+};
+/* read cpu identification code */
+void __init s5pc1xx_init_io(struct map_desc *mach_desc, int size)
+{
+        unsigned long idcode;
+        /* initialise the io descriptors we need for initialisation */
+        iotable_init(s5pc1xx_iodesc, ARRAY_SIZE(s5pc1xx_iodesc));
+        iotable_init(mach_desc, size);
+        idcode = __raw_readl(S5PC1XX_VA_CHIPID);
+        s3c_init_cpu(idcode, cpu_ids, ARRAY_SIZE(cpu_ids));
+}
diff --git a/arch/arm/plat-s5pc1xx/dev-uart.c b/arch/arm/plat-s5pc1xx/dev-uart.c
new file mode 100644
index 000000000000..f749bc5407b5
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/dev-uart.c
@@ -0,0 +1,174 @@
+/* linux/arch/arm/plat-s5pc1xx/dev-uart.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Based on plat-s3c64xx/dev-uart.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/list.h>
+#include <linux/platform_device.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <plat/devs.h>
+/* Serial port registrations */
+/* 64xx uarts are closer together */
+static struct resource s5pc1xx_uart0_resource[] = {
+        [0] = {
+                .start  = S3C_PA_UART0,
+                .end    = S3C_PA_UART0 + 0x100,
+                .flags  = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX0,
+                .end    = IRQ_S3CUART_RX0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX0,
+                .end    = IRQ_S3CUART_TX0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR0,
+                .end    = IRQ_S3CUART_ERR0,
+                .flags  = IORESOURCE_IRQ,
+        }
+};
+static struct resource s5pc1xx_uart1_resource[] = {
+        [0] = {
+                .start = S3C_PA_UART1,
+                .end   = S3C_PA_UART1 + 0x100,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX1,
+                .end    = IRQ_S3CUART_RX1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX1,
+                .end    = IRQ_S3CUART_TX1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR1,
+                .end    = IRQ_S3CUART_ERR1,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct resource s5pc1xx_uart2_resource[] = {
+        [0] = {
+                .start = S3C_PA_UART2,
+                .end   = S3C_PA_UART2 + 0x100,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX2,
+                .end    = IRQ_S3CUART_RX2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX2,
+                .end    = IRQ_S3CUART_TX2,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR2,
+                .end    = IRQ_S3CUART_ERR2,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+static struct resource s5pc1xx_uart3_resource[] = {
+        [0] = {
+                .start = S3C_PA_UART3,
+                .end   = S3C_PA_UART3 + 0x100,
+                .flags = IORESOURCE_MEM,
+        },
+        [1] = {
+                .start  = IRQ_S3CUART_RX3,
+                .end    = IRQ_S3CUART_RX3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [2] = {
+                .start  = IRQ_S3CUART_TX3,
+                .end    = IRQ_S3CUART_TX3,
+                .flags  = IORESOURCE_IRQ,
+        },
+        [3] = {
+                .start  = IRQ_S3CUART_ERR3,
+                .end    = IRQ_S3CUART_ERR3,
+                .flags  = IORESOURCE_IRQ,
+        },
+};
+struct s3c24xx_uart_resources s5pc1xx_uart_resources[] __initdata = {
+        [0] = {
+                .resources      = s5pc1xx_uart0_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart0_resource),
+        },
+        [1] = {
+                .resources      = s5pc1xx_uart1_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart1_resource),
+        },
+        [2] = {
+                .resources      = s5pc1xx_uart2_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart2_resource),
+        },
+        [3] = {
+                .resources      = s5pc1xx_uart3_resource,
+                .nr_resources   = ARRAY_SIZE(s5pc1xx_uart3_resource),
+        },
+};
+/* uart devices */
+static struct platform_device s3c24xx_uart_device0 = {
+        .id             = 0,
+};
+static struct platform_device s3c24xx_uart_device1 = {
+        .id             = 1,
+};
+static struct platform_device s3c24xx_uart_device2 = {
+        .id             = 2,
+};
+static struct platform_device s3c24xx_uart_device3 = {
+        .id             = 3,
+};
+struct platform_device *s3c24xx_uart_src[4] = {
+        &s3c24xx_uart_device0,
+        &s3c24xx_uart_device1,
+        &s3c24xx_uart_device2,
+        &s3c24xx_uart_device3,
+};
+struct platform_device *s3c24xx_uart_devs[4] = {
+};
diff --git a/arch/arm/plat-s5pc1xx/include/plat/irqs.h b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
new file mode 100644
index 000000000000..f07d8c3b25d6
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/irqs.h
@@ -0,0 +1,182 @@
+/* linux/arch/arm/plat-s5pc1xx/include/plat/irqs.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - Common IRQ support
+ *
+ * Based on plat-s3c64xx/include/plat/irqs.h
+ */
+#ifndef __ASM_PLAT_S5PC1XX_IRQS_H
+#define __ASM_PLAT_S5PC1XX_IRQS_H __FILE__
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ *
+ * note, since we're using the VICs, our start must be a
+ * mulitple of 32 to allow the common code to work
+ */
+#define S3C_IRQ_OFFSET          (32)
+#define S3C_IRQ(x)              ((x) + S3C_IRQ_OFFSET)
+#define S3C_VIC0_BASE           S3C_IRQ(0)
+#define S3C_VIC1_BASE           S3C_IRQ(32)
+#define S3C_VIC2_BASE           S3C_IRQ(64)
+/* UART interrupts, each UART has 4 intterupts per channel so
+ * use the space between the ISA and S3C main interrupts. Note, these
+ * are not in the same order as the S3C24XX series! */
+#define IRQ_S3CUART_BASE0       (16)
+#define IRQ_S3CUART_BASE1       (20)
+#define IRQ_S3CUART_BASE2       (24)
+#define IRQ_S3CUART_BASE3       (28)
+#define UART_IRQ_RXD            (0)
+#define UART_IRQ_ERR            (1)
+#define UART_IRQ_TXD            (2)
+#define UART_IRQ_MODEM          (3)
+#define IRQ_S3CUART_RX0         (IRQ_S3CUART_BASE0 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX0         (IRQ_S3CUART_BASE0 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR0        (IRQ_S3CUART_BASE0 + UART_IRQ_ERR)
+#define IRQ_S3CUART_RX1         (IRQ_S3CUART_BASE1 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX1         (IRQ_S3CUART_BASE1 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR1        (IRQ_S3CUART_BASE1 + UART_IRQ_ERR)
+#define IRQ_S3CUART_RX2         (IRQ_S3CUART_BASE2 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX2         (IRQ_S3CUART_BASE2 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR2        (IRQ_S3CUART_BASE2 + UART_IRQ_ERR)
+#define IRQ_S3CUART_RX3         (IRQ_S3CUART_BASE3 + UART_IRQ_RXD)
+#define IRQ_S3CUART_TX3         (IRQ_S3CUART_BASE3 + UART_IRQ_TXD)
+#define IRQ_S3CUART_ERR3        (IRQ_S3CUART_BASE3 + UART_IRQ_ERR)
+/* VIC based IRQs */
+#define S5PC1XX_IRQ_VIC0(x)     (S3C_VIC0_BASE + (x))
+#define S5PC1XX_IRQ_VIC1(x)     (S3C_VIC1_BASE + (x))
+#define S5PC1XX_IRQ_VIC2(x)     (S3C_VIC2_BASE + (x))
+/*
+ * VIC0: system, DMA, timer
+ */
+#define IRQ_EINT0               S5PC1XX_IRQ_VIC0(0)
+#define IRQ_EINT1               S5PC1XX_IRQ_VIC0(1)
+#define IRQ_EINT2               S5PC1XX_IRQ_VIC0(2)
+#define IRQ_EINT3               S5PC1XX_IRQ_VIC0(3)
+#define IRQ_EINT4               S5PC1XX_IRQ_VIC0(4)
+#define IRQ_EINT5               S5PC1XX_IRQ_VIC0(5)
+#define IRQ_EINT6               S5PC1XX_IRQ_VIC0(6)
+#define IRQ_EINT7               S5PC1XX_IRQ_VIC0(7)
+#define IRQ_EINT8               S5PC1XX_IRQ_VIC0(8)
+#define IRQ_EINT9               S5PC1XX_IRQ_VIC0(9)
+#define IRQ_EINT10              S5PC1XX_IRQ_VIC0(10)
+#define IRQ_EINT11              S5PC1XX_IRQ_VIC0(11)
+#define IRQ_EINT12              S5PC1XX_IRQ_VIC0(12)
+#define IRQ_EINT13              S5PC1XX_IRQ_VIC0(13)
+#define IRQ_EINT14              S5PC1XX_IRQ_VIC0(14)
+#define IRQ_EINT15              S5PC1XX_IRQ_VIC0(15)
+#define IRQ_EINT16_31           S5PC1XX_IRQ_VIC0(16)
+#define IRQ_BATF                S5PC1XX_IRQ_VIC0(17)
+#define IRQ_MDMA                S5PC1XX_IRQ_VIC0(18)
+#define IRQ_PDMA0               S5PC1XX_IRQ_VIC0(19)
+#define IRQ_PDMA1               S5PC1XX_IRQ_VIC0(20)
+#define IRQ_TIMER0              S5PC1XX_IRQ_VIC0(21)
+#define IRQ_TIMER1              S5PC1XX_IRQ_VIC0(22)
+#define IRQ_TIMER2              S5PC1XX_IRQ_VIC0(23)
+#define IRQ_TIMER3              S5PC1XX_IRQ_VIC0(24)
+#define IRQ_TIMER4              S5PC1XX_IRQ_VIC0(25)
+#define IRQ_SYSTIMER            S5PC1XX_IRQ_VIC0(26)
+#define IRQ_WDT                 S5PC1XX_IRQ_VIC0(27)
+#define IRQ_RTC_ALARM           S5PC1XX_IRQ_VIC0(28)
+#define IRQ_RTC_TIC             S5PC1XX_IRQ_VIC0(29)
+#define IRQ_GPIOINT             S5PC1XX_IRQ_VIC0(30)
+/*
+ * VIC1: ARM, power, memory, connectivity
+ */
+#define IRQ_CORTEX0             S5PC1XX_IRQ_VIC1(0)
+#define IRQ_CORTEX1             S5PC1XX_IRQ_VIC1(1)
+#define IRQ_CORTEX2             S5PC1XX_IRQ_VIC1(2)
+#define IRQ_CORTEX3             S5PC1XX_IRQ_VIC1(3)
+#define IRQ_CORTEX4             S5PC1XX_IRQ_VIC1(4)
+#define IRQ_IEMAPC              S5PC1XX_IRQ_VIC1(5)
+#define IRQ_IEMIEC              S5PC1XX_IRQ_VIC1(6)
+#define IRQ_ONENAND             S5PC1XX_IRQ_VIC1(7)
+#define IRQ_NFC                 S5PC1XX_IRQ_VIC1(8)
+#define IRQ_CFC                 S5PC1XX_IRQ_VIC1(9)
+#define IRQ_UART0               S5PC1XX_IRQ_VIC1(10)
+#define IRQ_UART1               S5PC1XX_IRQ_VIC1(11)
+#define IRQ_UART2               S5PC1XX_IRQ_VIC1(12)
+#define IRQ_UART3               S5PC1XX_IRQ_VIC1(13)
+#define IRQ_IIC                 S5PC1XX_IRQ_VIC1(14)
+#define IRQ_SPI0                S5PC1XX_IRQ_VIC1(15)
+#define IRQ_SPI1                S5PC1XX_IRQ_VIC1(16)
+#define IRQ_SPI2                S5PC1XX_IRQ_VIC1(17)
+#define IRQ_IRDA                S5PC1XX_IRQ_VIC1(18)
+#define IRQ_CAN0                S5PC1XX_IRQ_VIC1(19)
+#define IRQ_CAN1                S5PC1XX_IRQ_VIC1(20)
+#define IRQ_HSIRX               S5PC1XX_IRQ_VIC1(21)
+#define IRQ_HSITX               S5PC1XX_IRQ_VIC1(22)
+#define IRQ_UHOST               S5PC1XX_IRQ_VIC1(23)
+#define IRQ_OTG                 S5PC1XX_IRQ_VIC1(24)
+#define IRQ_MSM                 S5PC1XX_IRQ_VIC1(25)
+#define IRQ_HSMMC0              S5PC1XX_IRQ_VIC1(26)
+#define IRQ_HSMMC1              S5PC1XX_IRQ_VIC1(27)
+#define IRQ_HSMMC2              S5PC1XX_IRQ_VIC1(28)
+#define IRQ_MIPICSI             S5PC1XX_IRQ_VIC1(29)
+#define IRQ_MIPIDSI             S5PC1XX_IRQ_VIC1(30)
+/*
+ * VIC2: multimedia, audio, security
+ */
+#define IRQ_LCD0                S5PC1XX_IRQ_VIC2(0)
+#define IRQ_LCD1                S5PC1XX_IRQ_VIC2(1)
+#define IRQ_LCD2                S5PC1XX_IRQ_VIC2(2)
+#define IRQ_LCD3                S5PC1XX_IRQ_VIC2(3)
+#define IRQ_ROTATOR             S5PC1XX_IRQ_VIC2(4)
+#define IRQ_FIMC0               S5PC1XX_IRQ_VIC2(5)
+#define IRQ_FIMC1               S5PC1XX_IRQ_VIC2(6)
+#define IRQ_FIMC2               S5PC1XX_IRQ_VIC2(7)
+#define IRQ_JPEG                S5PC1XX_IRQ_VIC2(8)
+#define IRQ_2D                  S5PC1XX_IRQ_VIC2(9)
+#define IRQ_3D                  S5PC1XX_IRQ_VIC2(10)
+#define IRQ_MIXER               S5PC1XX_IRQ_VIC2(11)
+#define IRQ_HDMI                S5PC1XX_IRQ_VIC2(12)
+#define IRQ_IIC1                S5PC1XX_IRQ_VIC2(13)
+#define IRQ_MFC                 S5PC1XX_IRQ_VIC2(14)
+#define IRQ_TVENC               S5PC1XX_IRQ_VIC2(15)
+#define IRQ_I2S0                S5PC1XX_IRQ_VIC2(16)
+#define IRQ_I2S1                S5PC1XX_IRQ_VIC2(17)
+#define IRQ_I2S2                S5PC1XX_IRQ_VIC2(18)
+#define IRQ_AC97                S5PC1XX_IRQ_VIC2(19)
+#define IRQ_PCM0                S5PC1XX_IRQ_VIC2(20)
+#define IRQ_PCM1                S5PC1XX_IRQ_VIC2(21)
+#define IRQ_SPDIF               S5PC1XX_IRQ_VIC2(22)
+#define IRQ_ADC                 S5PC1XX_IRQ_VIC2(23)
+#define IRQ_PENDN               S5PC1XX_IRQ_VIC2(24)
+#define IRQ_TC                  IRQ_PENDN
+#define IRQ_KEYPAD              S5PC1XX_IRQ_VIC2(25)
+#define IRQ_CG                  S5PC1XX_IRQ_VIC2(26)
+#define IRQ_SEC                 S5PC1XX_IRQ_VIC2(27)
+#define IRQ_SECRX               S5PC1XX_IRQ_VIC2(28)
+#define IRQ_SECTX               S5PC1XX_IRQ_VIC2(29)
+#define IRQ_SDMIRQ              S5PC1XX_IRQ_VIC2(30)
+#define IRQ_SDMFIQ              S5PC1XX_IRQ_VIC2(31)
+#define S3C_IRQ_EINT_BASE       (IRQ_SDMFIQ + 1)
+#define S3C_EINT(x)             ((x) + S3C_IRQ_EINT_BASE)
+#define IRQ_EINT(x)             S3C_EINT(x)
+#define NR_IRQS                 (IRQ_EINT(31)+1)
+#endif /* __ASM_PLAT_S5PC1XX_IRQS_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/pll.h b/arch/arm/plat-s5pc1xx/include/plat/pll.h
new file mode 100644
index 000000000000..21afef1573e7
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/pll.h
@@ -0,0 +1,38 @@
+/* arch/arm/plat-s5pc1xx/include/plat/pll.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX PLL code
+ *
+ * Based on plat-s3c64xx/include/plat/pll.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define S5P_PLL_MDIV_MASK       ((1 << (25-16+1)) - 1)
+#define S5P_PLL_PDIV_MASK       ((1 << (13-8+1)) - 1)
+#define S5P_PLL_SDIV_MASK       ((1 << (2-0+1)) - 1)
+#define S5P_PLL_MDIV_SHIFT      (16)
+#define S5P_PLL_PDIV_SHIFT      (8)
+#define S5P_PLL_SDIV_SHIFT      (0)
+#include <asm/div64.h>
+static inline unsigned long s5pc1xx_get_pll(unsigned long baseclk,
+                                            u32 pllcon)
+{
+        u32 mdiv, pdiv, sdiv;
+        u64 fvco = baseclk;
+        mdiv = (pllcon >> S5P_PLL_MDIV_SHIFT) & S5P_PLL_MDIV_MASK;
+        pdiv = (pllcon >> S5P_PLL_PDIV_SHIFT) & S5P_PLL_PDIV_MASK;
+        sdiv = (pllcon >> S5P_PLL_SDIV_SHIFT) & S5P_PLL_SDIV_MASK;
+        fvco *= mdiv;
+        do_div(fvco, (pdiv << sdiv));
+        return (unsigned long)fvco;
+}
diff --git a/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
new file mode 100644
index 000000000000..75c8390cb827
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
@@ -0,0 +1,421 @@
+/* arch/arm/plat-s5pc1xx/include/plat/regs-clock.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __PLAT_REGS_CLOCK_H
+#define __PLAT_REGS_CLOCK_H __FILE__
+#define S5PC1XX_CLKREG(x)               (S5PC1XX_VA_CLK + (x))
+#define S5PC1XX_APLL_LOCK               S5PC1XX_CLKREG(0x00)
+#define S5PC1XX_MPLL_LOCK               S5PC1XX_CLKREG(0x04)
+#define S5PC1XX_EPLL_LOCK               S5PC1XX_CLKREG(0x08)
+#define S5PC100_HPLL_LOCK               S5PC1XX_CLKREG(0x0C)
+#define S5PC1XX_APLL_CON                S5PC1XX_CLKREG(0x100)
+#define S5PC1XX_MPLL_CON                S5PC1XX_CLKREG(0x104)
+#define S5PC1XX_EPLL_CON                S5PC1XX_CLKREG(0x108)
+#define S5PC100_HPLL_CON                S5PC1XX_CLKREG(0x10C)
+#define S5PC1XX_CLK_SRC0                S5PC1XX_CLKREG(0x200)
+#define S5PC1XX_CLK_SRC1                S5PC1XX_CLKREG(0x204)
+#define S5PC1XX_CLK_SRC2                S5PC1XX_CLKREG(0x208)
+#define S5PC1XX_CLK_SRC3                S5PC1XX_CLKREG(0x20C)
+#define S5PC1XX_CLK_DIV0                S5PC1XX_CLKREG(0x300)
+#define S5PC1XX_CLK_DIV1                S5PC1XX_CLKREG(0x304)
+#define S5PC1XX_CLK_DIV2                S5PC1XX_CLKREG(0x308)
+#define S5PC1XX_CLK_DIV3                S5PC1XX_CLKREG(0x30C)
+#define S5PC1XX_CLK_DIV4                S5PC1XX_CLKREG(0x310)
+#define S5PC100_CLK_OUT                 S5PC1XX_CLKREG(0x400)
+#define S5PC100_CLKGATE_D00             S5PC1XX_CLKREG(0x500)
+#define S5PC100_CLKGATE_D01             S5PC1XX_CLKREG(0x504)
+#define S5PC100_CLKGATE_D02             S5PC1XX_CLKREG(0x508)
+#define S5PC100_CLKGATE_D10             S5PC1XX_CLKREG(0x520)
+#define S5PC100_CLKGATE_D11             S5PC1XX_CLKREG(0x524)
+#define S5PC100_CLKGATE_D12             S5PC1XX_CLKREG(0x528)
+#define S5PC100_CLKGATE_D13             S5PC1XX_CLKREG(0x52C)
+#define S5PC100_CLKGATE_D14             S5PC1XX_CLKREG(0x530)
+#define S5PC100_CLKGATE_D15             S5PC1XX_CLKREG(0x534)
+#define S5PC100_CLKGATE_D20             S5PC1XX_CLKREG(0x540)
+#define S5PC100_SCLKGATE0               S5PC1XX_CLKREG(0x560)
+#define S5PC100_SCLKGATE1               S5PC1XX_CLKREG(0x564)
+#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+#define S5PC1XX_EPLL_EN     (1<<31)
+#define S5PC1XX_EPLL_MASK   0xffffffff
+#define S5PC1XX_EPLLVAL(_m, _p, _s)   ((_m) << 16 | ((_p) << 8) | ((_s)))
+/* CLKSRC0 */
+#define S5PC1XX_CLKSRC0_APLL_MASK               (0x1<<0)
+#define S5PC1XX_CLKSRC0_APLL_SHIFT              (0)
+#define S5PC1XX_CLKSRC0_MPLL_MASK               (0x1<<4)
+#define S5PC1XX_CLKSRC0_MPLL_SHIFT              (4)
+#define S5PC1XX_CLKSRC0_EPLL_MASK               (0x1<<8)
+#define S5PC1XX_CLKSRC0_EPLL_SHIFT              (8)
+#define S5PC100_CLKSRC0_HPLL_MASK               (0x1<<12)
+#define S5PC100_CLKSRC0_HPLL_SHIFT              (12)
+#define S5PC100_CLKSRC0_AMMUX_MASK              (0x1<<16)
+#define S5PC100_CLKSRC0_AMMUX_SHIFT             (16)
+#define S5PC100_CLKSRC0_HREF_MASK               (0x1<<20)
+#define S5PC100_CLKSRC0_HREF_SHIFT              (20)
+#define S5PC1XX_CLKSRC0_ONENAND_MASK    (0x1<<24)
+#define S5PC1XX_CLKSRC0_ONENAND_SHIFT   (24)
+/* CLKSRC1 */
+#define S5PC100_CLKSRC1_UART_MASK               (0x1<<0)
+#define S5PC100_CLKSRC1_UART_SHIFT              (0)
+#define S5PC100_CLKSRC1_SPI0_MASK               (0x3<<4)
+#define S5PC100_CLKSRC1_SPI0_SHIFT              (4)
+#define S5PC100_CLKSRC1_SPI1_MASK               (0x3<<8)
+#define S5PC100_CLKSRC1_SPI1_SHIFT              (8)
+#define S5PC100_CLKSRC1_SPI2_MASK               (0x3<<12)
+#define S5PC100_CLKSRC1_SPI2_SHIFT              (12)
+#define S5PC100_CLKSRC1_IRDA_MASK               (0x3<<16)
+#define S5PC100_CLKSRC1_IRDA_SHIFT              (16)
+#define S5PC100_CLKSRC1_UHOST_MASK              (0x3<<20)
+#define S5PC100_CLKSRC1_UHOST_SHIFT             (20)
+#define S5PC100_CLKSRC1_CLK48M_MASK             (0x1<<24)
+#define S5PC100_CLKSRC1_CLK48M_SHIFT    (24)
+/* CLKSRC2 */
+#define S5PC100_CLKSRC2_MMC0_MASK               (0x3<<0)
+#define S5PC100_CLKSRC2_MMC0_SHIFT              (0)
+#define S5PC100_CLKSRC2_MMC1_MASK               (0x3<<4)
+#define S5PC100_CLKSRC2_MMC1_SHIFT              (4)
+#define S5PC100_CLKSRC2_MMC2_MASK               (0x3<<8)
+#define S5PC100_CLKSRC2_MMC2_SHIFT              (8)
+#define S5PC100_CLKSRC2_LCD_MASK                (0x3<<12)
+#define S5PC100_CLKSRC2_LCD_SHIFT               (12)
+#define S5PC100_CLKSRC2_FIMC0_MASK              (0x3<<16)
+#define S5PC100_CLKSRC2_FIMC0_SHIFT             (16)
+#define S5PC100_CLKSRC2_FIMC1_MASK              (0x3<<20)
+#define S5PC100_CLKSRC2_FIMC1_SHIFT             (20)
+#define S5PC100_CLKSRC2_FIMC2_MASK              (0x3<<24)
+#define S5PC100_CLKSRC2_FIMC2_SHIFT             (24)
+#define S5PC100_CLKSRC2_MIXER_MASK              (0x3<<28)
+#define S5PC100_CLKSRC2_MIXER_SHIFT             (28)
+/* CLKSRC3 */
+#define S5PC100_CLKSRC3_PWI_MASK                (0x3<<0)
+#define S5PC100_CLKSRC3_PWI_SHIFT               (0)
+#define S5PC100_CLKSRC3_HCLKD2_MASK             (0x1<<4)
+#define S5PC100_CLKSRC3_HCLKD2_SHIFT    (4)
+#define S5PC100_CLKSRC3_I2SD2_MASK              (0x3<<8)
+#define S5PC100_CLKSRC3_I2SD2_SHIFT             (8)
+#define S5PC100_CLKSRC3_AUDIO0_MASK             (0x7<<12)
+#define S5PC100_CLKSRC3_AUDIO0_SHIFT    (12)
+#define S5PC100_CLKSRC3_AUDIO1_MASK             (0x7<<16)
+#define S5PC100_CLKSRC3_AUDIO1_SHIFT    (16)
+#define S5PC100_CLKSRC3_AUDIO2_MASK             (0x7<<20)
+#define S5PC100_CLKSRC3_AUDIO2_SHIFT    (20)
+#define S5PC100_CLKSRC3_SPDIF_MASK              (0x3<<24)
+#define S5PC100_CLKSRC3_SPDIF_SHIFT             (24)
+/* CLKDIV0 */
+#define S5PC1XX_CLKDIV0_APLL_MASK               (0x1<<0)
+#define S5PC1XX_CLKDIV0_APLL_SHIFT              (0)
+#define S5PC100_CLKDIV0_ARM_MASK                (0x7<<4)
+#define S5PC100_CLKDIV0_ARM_SHIFT               (4)
+#define S5PC100_CLKDIV0_D0_MASK         (0x7<<8)
+#define S5PC100_CLKDIV0_D0_SHIFT                (8)
+#define S5PC100_CLKDIV0_PCLKD0_MASK             (0x7<<12)
+#define S5PC100_CLKDIV0_PCLKD0_SHIFT    (12)
+#define S5PC100_CLKDIV0_SECSS_MASK              (0x7<<16)
+#define S5PC100_CLKDIV0_SECSS_SHIFT             (16)
+/* CLKDIV1 */
+#define S5PC100_CLKDIV1_AM_MASK         (0x7<<0)
+#define S5PC100_CLKDIV1_AM_SHIFT                (0)
+#define S5PC100_CLKDIV1_MPLL_MASK               (0x3<<4)
+#define S5PC100_CLKDIV1_MPLL_SHIFT              (4)
+#define S5PC100_CLKDIV1_MPLL2_MASK              (0x1<<8)
+#define S5PC100_CLKDIV1_MPLL2_SHIFT             (8)
+#define S5PC100_CLKDIV1_D1_MASK         (0x7<<12)
+#define S5PC100_CLKDIV1_D1_SHIFT                (12)
+#define S5PC100_CLKDIV1_PCLKD1_MASK             (0x7<<16)
+#define S5PC100_CLKDIV1_PCLKD1_SHIFT    (16)
+#define S5PC100_CLKDIV1_ONENAND_MASK    (0x3<<20)
+#define S5PC100_CLKDIV1_ONENAND_SHIFT   (20)
+#define S5PC100_CLKDIV1_CAM_MASK                (0x1F<<24)
+#define S5PC100_CLKDIV1_CAM_SHIFT               (24)
+/* CLKDIV2 */
+#define S5PC100_CLKDIV2_UART_MASK               (0x7<<0)
+#define S5PC100_CLKDIV2_UART_SHIFT              (0)
+#define S5PC100_CLKDIV2_SPI0_MASK               (0xf<<4)
+#define S5PC100_CLKDIV2_SPI0_SHIFT              (4)
+#define S5PC100_CLKDIV2_SPI1_MASK               (0xf<<8)
+#define S5PC100_CLKDIV2_SPI1_SHIFT              (8)
+#define S5PC100_CLKDIV2_SPI2_MASK               (0xf<<12)
+#define S5PC100_CLKDIV2_SPI2_SHIFT              (12)
+#define S5PC100_CLKDIV2_IRDA_MASK               (0xf<<16)
+#define S5PC100_CLKDIV2_IRDA_SHIFT              (16)
+#define S5PC100_CLKDIV2_UHOST_MASK              (0xf<<20)
+#define S5PC100_CLKDIV2_UHOST_SHIFT             (20)
+/* CLKDIV3 */
+#define S5PC100_CLKDIV3_MMC0_MASK               (0xf<<0)
+#define S5PC100_CLKDIV3_MMC0_SHIFT              (0)
+#define S5PC100_CLKDIV3_MMC1_MASK               (0xf<<4)
+#define S5PC100_CLKDIV3_MMC1_SHIFT              (4)
+#define S5PC100_CLKDIV3_MMC2_MASK               (0xf<<8)
+#define S5PC100_CLKDIV3_MMC2_SHIFT              (8)
+#define S5PC100_CLKDIV3_LCD_MASK                (0xf<<12)
+#define S5PC100_CLKDIV3_LCD_SHIFT               (12)
+#define S5PC100_CLKDIV3_FIMC0_MASK              (0xf<<16)
+#define S5PC100_CLKDIV3_FIMC0_SHIFT             (16)
+#define S5PC100_CLKDIV3_FIMC1_MASK              (0xf<<20)
+#define S5PC100_CLKDIV3_FIMC1_SHIFT             (20)
+#define S5PC100_CLKDIV3_FIMC2_MASK              (0xf<<24)
+#define S5PC100_CLKDIV3_FIMC2_SHIFT             (24)
+#define S5PC100_CLKDIV3_HDMI_MASK               (0xf<<28)
+#define S5PC100_CLKDIV3_HDMI_SHIFT              (28)
+/* CLKDIV4 */
+#define S5PC100_CLKDIV4_PWI_MASK                (0x7<<0)
+#define S5PC100_CLKDIV4_PWI_SHIFT               (0)
+#define S5PC100_CLKDIV4_HCLKD2_MASK             (0x7<<4)
+#define S5PC100_CLKDIV4_HCLKD2_SHIFT    (4)
+#define S5PC100_CLKDIV4_I2SD2_MASK              (0xf<<8)
+#define S5PC100_CLKDIV4_I2SD2_SHIFT             (8)
+#define S5PC100_CLKDIV4_AUDIO0_MASK             (0xf<<12)
+#define S5PC100_CLKDIV4_AUDIO0_SHIFT    (12)
+#define S5PC100_CLKDIV4_AUDIO1_MASK             (0xf<<16)
+#define S5PC100_CLKDIV4_AUDIO1_SHIFT    (16)
+#define S5PC100_CLKDIV4_AUDIO2_MASK             (0xf<<20)
+#define S5PC100_CLKDIV4_AUDIO2_SHIFT    (20)
+/* HCLKD0/PCLKD0 Clock Gate 0 Registers */
+#define S5PC100_CLKGATE_D00_INTC                (1<<0)
+#define S5PC100_CLKGATE_D00_TZIC                (1<<1)
+#define S5PC100_CLKGATE_D00_CFCON               (1<<2)
+#define S5PC100_CLKGATE_D00_MDMA                (1<<3)
+#define S5PC100_CLKGATE_D00_G2D         (1<<4)
+#define S5PC100_CLKGATE_D00_SECSS               (1<<5)
+#define S5PC100_CLKGATE_D00_CSSYS               (1<<6)
+/* HCLKD0/PCLKD0 Clock Gate 1 Registers */
+#define S5PC100_CLKGATE_D01_DMC         (1<<0)
+#define S5PC100_CLKGATE_D01_SROMC               (1<<1)
+#define S5PC100_CLKGATE_D01_ONENAND             (1<<2)
+#define S5PC100_CLKGATE_D01_NFCON               (1<<3)
+#define S5PC100_CLKGATE_D01_INTMEM              (1<<4)
+#define S5PC100_CLKGATE_D01_EBI         (1<<5)
+/* PCLKD0 Clock Gate 2 Registers */
+#define S5PC100_CLKGATE_D02_SECKEY              (1<<1)
+#define S5PC100_CLKGATE_D02_SDM         (1<<2)
+/* HCLKD1/PCLKD1 Clock Gate 0 Registers */
+#define S5PC100_CLKGATE_D10_PDMA0               (1<<0)
+#define S5PC100_CLKGATE_D10_PDMA1               (1<<1)
+#define S5PC100_CLKGATE_D10_USBHOST             (1<<2)
+#define S5PC100_CLKGATE_D10_USBOTG              (1<<3)
+#define S5PC100_CLKGATE_D10_MODEMIF             (1<<4)
+#define S5PC100_CLKGATE_D10_HSMMC0              (1<<5)
+#define S5PC100_CLKGATE_D10_HSMMC1              (1<<6)
+#define S5PC100_CLKGATE_D10_HSMMC2              (1<<7)
+/* HCLKD1/PCLKD1 Clock Gate 1 Registers */
+#define S5PC100_CLKGATE_D11_LCD         (1<<0)
+#define S5PC100_CLKGATE_D11_ROTATOR             (1<<1)
+#define S5PC100_CLKGATE_D11_FIMC0               (1<<2)
+#define S5PC100_CLKGATE_D11_FIMC1               (1<<3)
+#define S5PC100_CLKGATE_D11_FIMC2               (1<<4)
+#define S5PC100_CLKGATE_D11_JPEG                (1<<5)
+#define S5PC100_CLKGATE_D11_DSI         (1<<6)
+#define S5PC100_CLKGATE_D11_CSI         (1<<7)
+#define S5PC100_CLKGATE_D11_G3D         (1<<8)
+/* HCLKD1/PCLKD1 Clock Gate 2 Registers */
+#define S5PC100_CLKGATE_D12_TV          (1<<0)
+#define S5PC100_CLKGATE_D12_VP          (1<<1)
+#define S5PC100_CLKGATE_D12_MIXER               (1<<2)
+#define S5PC100_CLKGATE_D12_HDMI                (1<<3)
+#define S5PC100_CLKGATE_D12_MFC         (1<<4)
+/* HCLKD1/PCLKD1 Clock Gate 3 Registers */
+#define S5PC100_CLKGATE_D13_CHIPID              (1<<0)
+#define S5PC100_CLKGATE_D13_GPIO                (1<<1)
+#define S5PC100_CLKGATE_D13_APC         (1<<2)
+#define S5PC100_CLKGATE_D13_IEC         (1<<3)
+#define S5PC100_CLKGATE_D13_PWM         (1<<6)
+#define S5PC100_CLKGATE_D13_SYSTIMER    (1<<7)
+#define S5PC100_CLKGATE_D13_WDT         (1<<8)
+#define S5PC100_CLKGATE_D13_RTC         (1<<9)
+/* HCLKD1/PCLKD1 Clock Gate 4 Registers */
+#define S5PC100_CLKGATE_D14_UART0               (1<<0)
+#define S5PC100_CLKGATE_D14_UART1               (1<<1)
+#define S5PC100_CLKGATE_D14_UART2               (1<<2)
+#define S5PC100_CLKGATE_D14_UART3               (1<<3)
+#define S5PC100_CLKGATE_D14_IIC         (1<<4)
+#define S5PC100_CLKGATE_D14_HDMI_IIC    (1<<5)
+#define S5PC100_CLKGATE_D14_SPI0                (1<<6)
+#define S5PC100_CLKGATE_D14_SPI1                (1<<7)
+#define S5PC100_CLKGATE_D14_SPI2                (1<<8)
+#define S5PC100_CLKGATE_D14_IRDA                (1<<9)
+#define S5PC100_CLKGATE_D14_CCAN0               (1<<10)
+#define S5PC100_CLKGATE_D14_CCAN1               (1<<11)
+#define S5PC100_CLKGATE_D14_HSITX               (1<<12)
+#define S5PC100_CLKGATE_D14_HSIRX               (1<<13)
+/* HCLKD1/PCLKD1 Clock Gate 5 Registers */
+#define S5PC100_CLKGATE_D15_IIS0                (1<<0)
+#define S5PC100_CLKGATE_D15_IIS1                (1<<1)
+#define S5PC100_CLKGATE_D15_IIS2                (1<<2)
+#define S5PC100_CLKGATE_D15_AC97                (1<<3)
+#define S5PC100_CLKGATE_D15_PCM0                (1<<4)
+#define S5PC100_CLKGATE_D15_PCM1                (1<<5)
+#define S5PC100_CLKGATE_D15_SPDIF               (1<<6)
+#define S5PC100_CLKGATE_D15_TSADC               (1<<7)
+#define S5PC100_CLKGATE_D15_KEYIF               (1<<8)
+#define S5PC100_CLKGATE_D15_CG          (1<<9)
+/* HCLKD2 Clock Gate 0 Registers */
+#define S5PC100_CLKGATE_D20_HCLKD2              (1<<0)
+#define S5PC100_CLKGATE_D20_I2SD2               (1<<1)
+/* Special Clock Gate 0 Registers */
+#define S5PC1XX_CLKGATE_SCLK0_HPM               (1<<0)
+#define S5PC1XX_CLKGATE_SCLK0_PWI               (1<<1)
+#define S5PC100_CLKGATE_SCLK0_ONENAND   (1<<2)
+#define S5PC100_CLKGATE_SCLK0_UART              (1<<3)
+#define S5PC100_CLKGATE_SCLK0_SPI0              (1<<4)
+#define S5PC100_CLKGATE_SCLK0_SPI1              (1<<5)
+#define S5PC100_CLKGATE_SCLK0_SPI2              (1<<6)
+#define S5PC100_CLKGATE_SCLK0_SPI0_48   (1<<7)
+#define S5PC100_CLKGATE_SCLK0_SPI1_48   (1<<8)
+#define S5PC100_CLKGATE_SCLK0_SPI2_48   (1<<9)
+#define S5PC100_CLKGATE_SCLK0_IRDA              (1<<10)
+#define S5PC100_CLKGATE_SCLK0_USBHOST   (1<<11)
+#define S5PC100_CLKGATE_SCLK0_MMC0              (1<<12)
+#define S5PC100_CLKGATE_SCLK0_MMC1              (1<<13)
+#define S5PC100_CLKGATE_SCLK0_MMC2              (1<<14)
+#define S5PC100_CLKGATE_SCLK0_MMC0_48   (1<<15)
+#define S5PC100_CLKGATE_SCLK0_MMC1_48   (1<<16)
+#define S5PC100_CLKGATE_SCLK0_MMC2_48   (1<<17)
+/* Special Clock Gate 1 Registers */
+#define S5PC100_CLKGATE_SCLK1_LCD               (1<<0)
+#define S5PC100_CLKGATE_SCLK1_FIMC0             (1<<1)
+#define S5PC100_CLKGATE_SCLK1_FIMC1             (1<<2)
+#define S5PC100_CLKGATE_SCLK1_FIMC2             (1<<3)
+#define S5PC100_CLKGATE_SCLK1_TV54              (1<<4)
+#define S5PC100_CLKGATE_SCLK1_VDAC54    (1<<5)
+#define S5PC100_CLKGATE_SCLK1_MIXER             (1<<6)
+#define S5PC100_CLKGATE_SCLK1_HDMI              (1<<7)
+#define S5PC100_CLKGATE_SCLK1_AUDIO0    (1<<8)
+#define S5PC100_CLKGATE_SCLK1_AUDIO1    (1<<9)
+#define S5PC100_CLKGATE_SCLK1_AUDIO2    (1<<10)
+#define S5PC100_CLKGATE_SCLK1_SPDIF             (1<<11)
+#define S5PC100_CLKGATE_SCLK1_CAM               (1<<12)
+/* register for power management */
+#define S5PC100_PWR_CFG                 S5PC1XX_CLKREG(0x8000)
+#define S5PC100_EINT_WAKEUP_MASK        S5PC1XX_CLKREG(0x8004)
+#define S5PC100_NORMAL_CFG              S5PC1XX_CLKREG(0x8010)
+#define S5PC100_STOP_CFG                S5PC1XX_CLKREG(0x8014)
+#define S5PC100_SLEEP_CFG               S5PC1XX_CLKREG(0x8018)
+#define S5PC100_STOP_MEM_CFG    S5PC1XX_CLKREG(0x801C)
+#define S5PC100_OSC_FREQ                S5PC1XX_CLKREG(0x8100)
+#define S5PC100_OSC_STABLE              S5PC1XX_CLKREG(0x8104)
+#define S5PC100_PWR_STABLE              S5PC1XX_CLKREG(0x8108)
+#define S5PC100_MTC_STABLE              S5PC1XX_CLKREG(0x8110)
+#define S5PC100_CLAMP_STABLE    S5PC1XX_CLKREG(0x8114)
+#define S5PC100_OTHERS          S5PC1XX_CLKREG(0x8200)
+#define S5PC100_RST_STAT                S5PC1XX_CLKREG(0x8300)
+#define S5PC100_WAKEUP_STAT     S5PC1XX_CLKREG(0x8304)
+#define S5PC100_BLK_PWR_STAT    S5PC1XX_CLKREG(0x8308)
+#define S5PC100_INFORM0                 S5PC1XX_CLKREG(0x8400)
+#define S5PC100_INFORM1                 S5PC1XX_CLKREG(0x8404)
+#define S5PC100_INFORM2                 S5PC1XX_CLKREG(0x8408)
+#define S5PC100_INFORM3                 S5PC1XX_CLKREG(0x840C)
+#define S5PC100_INFORM4                 S5PC1XX_CLKREG(0x8410)
+#define S5PC100_INFORM5                 S5PC1XX_CLKREG(0x8414)
+#define S5PC100_INFORM6                 S5PC1XX_CLKREG(0x8418)
+#define S5PC100_INFORM7                 S5PC1XX_CLKREG(0x841C)
+#define S5PC100_DCGIDX_MAP0     S5PC1XX_CLKREG(0x8500)
+#define S5PC100_DCGIDX_MAP1     S5PC1XX_CLKREG(0x8504)
+#define S5PC100_DCGIDX_MAP2     S5PC1XX_CLKREG(0x8508)
+#define S5PC100_DCGPERF_MAP0    S5PC1XX_CLKREG(0x850C)
+#define S5PC100_DCGPERF_MAP1    S5PC1XX_CLKREG(0x8510)
+#define S5PC100_DVCIDX_MAP              S5PC1XX_CLKREG(0x8514)
+#define S5PC100_FREQ_CPU                S5PC1XX_CLKREG(0x8518)
+#define S5PC100_FREQ_DPM                S5PC1XX_CLKREG(0x851C)
+#define S5PC100_DVSEMCLK_EN     S5PC1XX_CLKREG(0x8520)
+#define S5PC100_APLL_CON_L8     S5PC1XX_CLKREG(0x8600)
+#define S5PC100_APLL_CON_L7     S5PC1XX_CLKREG(0x8604)
+#define S5PC100_APLL_CON_L6     S5PC1XX_CLKREG(0x8608)
+#define S5PC100_APLL_CON_L5     S5PC1XX_CLKREG(0x860C)
+#define S5PC100_APLL_CON_L4     S5PC1XX_CLKREG(0x8610)
+#define S5PC100_APLL_CON_L3     S5PC1XX_CLKREG(0x8614)
+#define S5PC100_APLL_CON_L2     S5PC1XX_CLKREG(0x8618)
+#define S5PC100_APLL_CON_L1     S5PC1XX_CLKREG(0x861C)
+#define S5PC100_IEM_CONTROL     S5PC1XX_CLKREG(0x8620)
+#define S5PC100_CLKDIV_IEM_L8   S5PC1XX_CLKREG(0x8700)
+#define S5PC100_CLKDIV_IEM_L7   S5PC1XX_CLKREG(0x8704)
+#define S5PC100_CLKDIV_IEM_L6   S5PC1XX_CLKREG(0x8708)
+#define S5PC100_CLKDIV_IEM_L5   S5PC1XX_CLKREG(0x870C)
+#define S5PC100_CLKDIV_IEM_L4   S5PC1XX_CLKREG(0x8710)
+#define S5PC100_CLKDIV_IEM_L3   S5PC1XX_CLKREG(0x8714)
+#define S5PC100_CLKDIV_IEM_L2   S5PC1XX_CLKREG(0x8718)
+#define S5PC100_CLKDIV_IEM_L1   S5PC1XX_CLKREG(0x871C)
+#define S5PC100_IEM_HPMCLK_DIV  S5PC1XX_CLKREG(0x8724)
+#define S5PC100_SWRESET         S5PC1XX_CLKREG(0x100000)
+#define S5PC100_OND_SWRESET             S5PC1XX_CLKREG(0x100008)
+#define S5PC100_GEN_CTRL                S5PC1XX_CLKREG(0x100100)
+#define S5PC100_GEN_STATUS              S5PC1XX_CLKREG(0x100104)
+#define S5PC100_MEM_SYS_CFG             S5PC1XX_CLKREG(0x100200)
+#define S5PC100_CAM_MUX_SEL             S5PC1XX_CLKREG(0x100300)
+#define S5PC100_MIXER_OUT_SEL   S5PC1XX_CLKREG(0x100304)
+#define S5PC100_LPMP_MODE_SEL   S5PC1XX_CLKREG(0x100308)
+#define S5PC100_MIPI_PHY_CON0   S5PC1XX_CLKREG(0x100400)
+#define S5PC100_MIPI_PHY_CON1   S5PC1XX_CLKREG(0x100414)
+#define S5PC100_HDMI_PHY_CON0   S5PC1XX_CLKREG(0x100420)
+#define S5PC100_CFG_WFI_CLEAN   (~(3<<5))
+#define S5PC100_CFG_WFI_IDLE    (1<<5)
+#define S5PC100_CFG_WFI_STOP    (2<<5)
+#define S5PC100_CFG_WFI_SLEEP   (3<<5)
+#define S5PC100_OTHER_SYS_INT   24
+#define S5PC100_OTHER_STA_TYPE  23
+#define STA_TYPE_EXPON          0
+#define STA_TYPE_SFR            1
+#define S5PC100_PWR_STA_EXP_SCALE       0
+#define S5PC100_PWR_STA_CNT             4
+#define S5PC100_PWR_STABLE_COUNT        85500
+#define S5PC100_SLEEP_CFG_OSC_EN        0
+/* OTHERS Resgister */
+#define S5PC100_OTHERS_USB_SIG_MASK     (1 << 16)
+#define S5PC100_OTHERS_MIPI_DPHY_EN             (1 << 28)
+/* MIPI D-PHY Control Register 0 */
+#define S5PC100_MIPI_PHY_CON0_M_RESETN  (1 << 1)
+#define S5PC100_MIPI_PHY_CON0_S_RESETN  (1 << 0)
+#endif /* _PLAT_REGS_CLOCK_H */
diff --git a/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
new file mode 100644
index 000000000000..45e275131665
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
@@ -0,0 +1,65 @@
+/* arch/arm/plat-s5pc1xx/include/plat/s5pc100.h
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Header file for s5pc100 cpu support
+ *
+ * Based on plat-s3c64xx/include/plat/s3c6400.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+/* Common init code for S5PC100 related SoCs */
+extern  int s5pc100_init(void);
+extern void s5pc100_map_io(void);
+extern void s5pc100_init_clocks(int xtal);
+extern  int s5pc100_register_baseclocks(unsigned long xtal);
+extern void s5pc100_init_irq(void);
+extern void s5pc100_init_io(struct map_desc *mach_desc, int size);
+extern void s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s5pc100_register_clocks(void);
+extern void s5pc100_setup_clocks(void);
+extern struct sysdev_class s5pc100_sysclass;
+#define s5pc100_init_uarts s5pc100_common_init_uarts
+/* Some day, belows will be moved to plat-s5pc/include/plat/cpu.h */
+extern void s5pc1xx_init_irq(u32 *vic_valid, int num);
+extern void s5pc1xx_init_io(struct map_desc *mach_desc, int size);
+/* Some day, belows will be moved to plat-s5pc/include/plat/clock.h */
+extern struct clk clk_hpll;
+extern struct clk clk_hd0;
+extern struct clk clk_pd0;
+extern struct clk clk_54m;
+extern struct clk clk_dout_mpll2;
+extern void s5pc1xx_register_clocks(void);
+extern int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable);
+extern int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable);
+/* Some day, belows will be moved to plat-s5pc/include/plat/devs.h */
+extern struct s3c24xx_uart_resources s5pc1xx_uart_resources[];
+extern struct platform_device s3c_device_g2d;
+extern struct platform_device s3c_device_g3d;
+extern struct platform_device s3c_device_vpp;
+extern struct platform_device s3c_device_tvenc;
+extern struct platform_device s3c_device_tvscaler;
+extern struct platform_device s3c_device_rotator;
+extern struct platform_device s3c_device_jpeg;
+extern struct platform_device s3c_device_onenand;
+extern struct platform_device s3c_device_usb_otghcd;
+extern struct platform_device s3c_device_keypad;
+extern struct platform_device s3c_device_ts;
+extern struct platform_device s3c_device_g3d;
+extern struct platform_device s3c_device_smc911x;
+extern struct platform_device s3c_device_fimc0;
+extern struct platform_device s3c_device_fimc1;
+extern struct platform_device s3c_device_mfc;
+extern struct platform_device s3c_device_ac97;
+extern struct platform_device s3c_device_fimc0;
+extern struct platform_device s3c_device_fimc1;
+extern struct platform_device s3c_device_fimc2;
diff --git a/arch/arm/plat-s5pc1xx/irq.c b/arch/arm/plat-s5pc1xx/irq.c
new file mode 100644
index 000000000000..80d6dd942cb8
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/irq.c
@@ -0,0 +1,259 @@
+/* arch/arm/plat-s5pc1xx/irq.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC1XX - Interrupt handling
+ *
+ * Based on plat-s3c64xx/irq.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <asm/hardware/vic.h>
+#include <mach/map.h>
+#include <plat/regs-timer.h>
+#include <plat/cpu.h>
+/* Timer interrupt handling */
+static void s3c_irq_demux_timer(unsigned int base_irq, unsigned int sub_irq)
+{
+        generic_handle_irq(sub_irq);
+}
+static void s3c_irq_demux_timer0(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER0);
+}
+static void s3c_irq_demux_timer1(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER1);
+}
+static void s3c_irq_demux_timer2(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER2);
+}
+static void s3c_irq_demux_timer3(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER3);
+}
+static void s3c_irq_demux_timer4(unsigned int irq, struct irq_desc *desc)
+{
+        s3c_irq_demux_timer(irq, IRQ_TIMER4);
+}
+/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
+static void s3c_irq_timer_mask(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+        reg &= 0x1f;  /* mask out pending interrupts */
+        reg &= ~(1 << (irq - IRQ_TIMER0));
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+static void s3c_irq_timer_unmask(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+        reg &= 0x1f;  /* mask out pending interrupts */
+        reg |= 1 << (irq - IRQ_TIMER0);
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+static void s3c_irq_timer_ack(unsigned int irq)
+{
+        u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
+        reg &= 0x1f;
+        reg |= (1 << 5) << (irq - IRQ_TIMER0);
+        __raw_writel(reg, S3C64XX_TINT_CSTAT);
+}
+static struct irq_chip s3c_irq_timer = {
+        .name           = "s3c-timer",
+        .mask           = s3c_irq_timer_mask,
+        .unmask         = s3c_irq_timer_unmask,
+        .ack            = s3c_irq_timer_ack,
+};
+struct uart_irq {
+        void __iomem    *regs;
+        unsigned int     base_irq;
+        unsigned int     parent_irq;
+};
+/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
+ * are consecutive when looking up the interrupt in the demux routines.
+ */
+static struct uart_irq uart_irqs[] = {
+        [0] = {
+                .regs           = (void *)S3C_VA_UART0,
+                .base_irq       = IRQ_S3CUART_BASE0,
+                .parent_irq     = IRQ_UART0,
+        },
+        [1] = {
+                .regs           = (void *)S3C_VA_UART1,
+                .base_irq       = IRQ_S3CUART_BASE1,
+                .parent_irq     = IRQ_UART1,
+        },
+        [2] = {
+                .regs           = (void *)S3C_VA_UART2,
+                .base_irq       = IRQ_S3CUART_BASE2,
+                .parent_irq     = IRQ_UART2,
+        },
+        [3] = {
+                .regs           = (void *)S3C_VA_UART3,
+                .base_irq       = IRQ_S3CUART_BASE3,
+                .parent_irq     = IRQ_UART3,
+        },
+};
+static inline void __iomem *s3c_irq_uart_base(unsigned int irq)
+{
+        struct uart_irq *uirq = get_irq_chip_data(irq);
+        return uirq->regs;
+}
+static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
+{
+        return irq & 3;
+}
+/* UART interrupt registers, not worth adding to seperate include header */
+#define S3C64XX_UINTP   0x30
+#define S3C64XX_UINTSP  0x34
+#define S3C64XX_UINTM   0x38
+static void s3c_irq_uart_mask(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg |= (1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+static void s3c_irq_uart_maskack(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg |= (1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+static void s3c_irq_uart_unmask(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        u32 reg;
+        reg = __raw_readl(regs + S3C64XX_UINTM);
+        reg &= ~(1 << bit);
+        __raw_writel(reg, regs + S3C64XX_UINTM);
+}
+static void s3c_irq_uart_ack(unsigned int irq)
+{
+        void __iomem *regs = s3c_irq_uart_base(irq);
+        unsigned int bit = s3c_irq_uart_bit(irq);
+        __raw_writel(1 << bit, regs + S3C64XX_UINTP);
+}
+static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
+{
+        struct uart_irq *uirq = &uart_irqs[irq - IRQ_UART0];
+        u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
+        int base = uirq->base_irq;
+        if (pend & (1 << 0))
+                generic_handle_irq(base);
+        if (pend & (1 << 1))
+                generic_handle_irq(base + 1);
+        if (pend & (1 << 2))
+                generic_handle_irq(base + 2);
+        if (pend & (1 << 3))
+                generic_handle_irq(base + 3);
+}
+static struct irq_chip s3c_irq_uart = {
+        .name           = "s3c-uart",
+        .mask           = s3c_irq_uart_mask,
+        .unmask         = s3c_irq_uart_unmask,
+        .mask_ack       = s3c_irq_uart_maskack,
+        .ack            = s3c_irq_uart_ack,
+};
+static void __init s5pc1xx_uart_irq(struct uart_irq *uirq)
+{
+        void __iomem *reg_base = uirq->regs;
+        unsigned int irq;
+        int offs;
+        /* mask all interrupts at the start. */
+        __raw_writel(0xf, reg_base + S3C64XX_UINTM);
+        for (offs = 0; offs < 3; offs++) {
+                irq = uirq->base_irq + offs;
+                set_irq_chip(irq, &s3c_irq_uart);
+                set_irq_chip_data(irq, uirq);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
+}
+void __init s5pc1xx_init_irq(u32 *vic_valid, int num)
+{
+        int i;
+        int uart, irq;
+        printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
+        /* initialise the pair of VICs */
+        for (i = 0; i < num; i++)
+                vic_init((void *)S5PC1XX_VA_VIC(i), S3C_IRQ(i * S3C_IRQ_OFFSET),
+                                vic_valid[i], 0);
+        /* add the timer sub-irqs */
+        set_irq_chained_handler(IRQ_TIMER0, s3c_irq_demux_timer0);
+        set_irq_chained_handler(IRQ_TIMER1, s3c_irq_demux_timer1);
+        set_irq_chained_handler(IRQ_TIMER2, s3c_irq_demux_timer2);
+        set_irq_chained_handler(IRQ_TIMER3, s3c_irq_demux_timer3);
+        set_irq_chained_handler(IRQ_TIMER4, s3c_irq_demux_timer4);
+        for (irq = IRQ_TIMER0; irq <= IRQ_TIMER4; irq++) {
+                set_irq_chip(irq, &s3c_irq_timer);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_flags(irq, IRQF_VALID);
+        }
+        for (uart = 0; uart < ARRAY_SIZE(uart_irqs); uart++)
+                s5pc1xx_uart_irq(&uart_irqs[uart]);
+}
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-clock.c b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
new file mode 100644
index 000000000000..6b24035172fa
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/s5pc100-clock.c
@@ -0,0 +1,1139 @@
+/* linux/arch/arm/plat-s5pc1xx/s5pc100-clock.c
+ *
+ * Copyright 2009 Samsung Electronics, Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 based common clock support
+ *
+ * Based on plat-s3c64xx/s3c6400-clock.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/sysdev.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/map.h>
+#include <plat/cpu-freq.h>
+#include <plat/regs-clock.h>
+#include <plat/clock.h>
+#include <plat/cpu.h>
+#include <plat/pll.h>
+#include <plat/devs.h>
+#include <plat/s5pc100.h>
+/* fin_apll, fin_mpll and fin_epll are all the same clock, which we call
+ * ext_xtal_mux for want of an actual name from the manual.
+*/
+static struct clk clk_ext_xtal_mux = {
+        .name           = "ext_xtal",
+        .id             = -1,
+};
+#define clk_fin_apll clk_ext_xtal_mux
+#define clk_fin_mpll clk_ext_xtal_mux
+#define clk_fin_epll clk_ext_xtal_mux
+#define clk_fin_hpll clk_ext_xtal_mux
+#define clk_fout_mpll   clk_mpll
+struct clk_sources {
+        unsigned int    nr_sources;
+        struct clk      **sources;
+};
+struct clksrc_clk {
+        struct clk              clk;
+        unsigned int            mask;
+        unsigned int            shift;
+        struct clk_sources      *sources;
+        unsigned int            divider_shift;
+        void __iomem            *reg_divider;
+        void __iomem            *reg_source;
+};
+static int clk_default_setrate(struct clk *clk, unsigned long rate)
+{
+        clk->rate = rate;
+        return 1;
+}
+struct clk clk_27m = {
+        .name           = "clk_27m",
+        .id             = -1,
+        .rate           = 27000000,
+};
+static int clk_48m_ctrl(struct clk *clk, int enable)
+{
+        unsigned long flags;
+        u32 val;
+        /* can't rely on clock lock, this register has other usages */
+        local_irq_save(flags);
+        val = __raw_readl(S5PC1XX_CLK_SRC1);
+        if (enable)
+                val |= S5PC100_CLKSRC1_CLK48M_MASK;
+        else
+                val &= ~S5PC100_CLKSRC1_CLK48M_MASK;
+        __raw_writel(val, S5PC1XX_CLK_SRC1);
+        local_irq_restore(flags);
+        return 0;
+}
+struct clk clk_48m = {
+        .name           = "clk_48m",
+        .id             = -1,
+        .rate           = 48000000,
+        .enable         = clk_48m_ctrl,
+};
+struct clk clk_54m = {
+        .name           = "clk_54m",
+        .id             = -1,
+        .rate           = 54000000,
+};
+struct clk clk_hpll = {
+        .name           = "hpll",
+        .id             = -1,
+};
+struct clk clk_hd0 = {
+        .name           = "hclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+};
+struct clk clk_pd0 = {
+        .name           = "pclkd0",
+        .id             = -1,
+        .rate           = 0,
+        .parent         = NULL,
+        .ctrlbit        = 0,
+        .set_rate       = clk_default_setrate,
+};
+static int s5pc1xx_clk_gate(void __iomem *reg,
+                                struct clk *clk,
+                                int enable)
+{
+        unsigned int ctrlbit = clk->ctrlbit;
+        u32 con;
+        con = __raw_readl(reg);
+        if (enable)
+                con |= ctrlbit;
+        else
+                con &= ~ctrlbit;
+        __raw_writel(con, reg);
+        return 0;
+}
+static int s5pc1xx_clk_d00_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D00, clk, enable);
+}
+static int s5pc1xx_clk_d01_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D01, clk, enable);
+}
+static int s5pc1xx_clk_d02_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D02, clk, enable);
+}
+static int s5pc1xx_clk_d10_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D10, clk, enable);
+}
+static int s5pc1xx_clk_d11_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D11, clk, enable);
+}
+static int s5pc1xx_clk_d12_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D12, clk, enable);
+}
+static int s5pc1xx_clk_d13_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D13, clk, enable);
+}
+static int s5pc1xx_clk_d14_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D14, clk, enable);
+}
+static int s5pc1xx_clk_d15_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D15, clk, enable);
+}
+static int s5pc1xx_clk_d20_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_CLKGATE_D20, clk, enable);
+}
+int s5pc1xx_sclk0_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE0, clk, enable);
+}
+int s5pc1xx_sclk1_ctrl(struct clk *clk, int enable)
+{
+        return s5pc1xx_clk_gate(S5PC100_SCLKGATE1, clk, enable);
+}
+static struct clk init_clocks_disable[] = {
+        {
+                .name           = "dsi",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_DSI,
+        }, {
+                .name           = "csi",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_CSI,
+        }, {
+                .name           = "ccan0",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN0,
+        }, {
+                .name           = "ccan1",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_CCAN1,
+        }, {
+                .name           = "keypad",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
+        }, {
+                .name           = "hclkd2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_HCLKD2,
+        }, {
+                .name           = "iis-d2",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_clk_d20_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D20_I2SD2,
+        }, {
+                .name           = "otg",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBOTG,
+        },
+};
+static struct clk init_clocks[] = {
+        /* System1 (D0_0) devices */
+        {
+                .name           = "intc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_INTC,
+        }, {
+                .name           = "tzic",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_TZIC,
+        }, {
+                .name           = "cf-ata",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CFCON,
+        }, {
+                .name           = "mdma",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_MDMA,
+        }, {
+                .name           = "g2d",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_G2D,
+        }, {
+                .name           = "secss",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_SECSS,
+        }, {
+                .name           = "cssys",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d00_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D00_CSSYS,
+        },
+        /* Memory (D0_1) devices */
+        {
+                .name           = "dmc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_DMC,
+        }, {
+                .name           = "sromc",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_SROMC,
+        }, {
+                .name           = "onenand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_ONENAND,
+        }, {
+                .name           = "nand",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_NFCON,
+        }, {
+                .name           = "intmem",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_INTMEM,
+        }, {
+                .name           = "ebi",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d01_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D01_EBI,
+        },
+        /* System2 (D0_2) devices */
+        {
+                .name           = "seckey",
+                .id             = -1,
+                .parent         = &clk_pd0,
+                .enable         = s5pc1xx_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SECKEY,
+        }, {
+                .name           = "sdm",
+                .id             = -1,
+                .parent         = &clk_hd0,
+                .enable         = s5pc1xx_clk_d02_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D02_SDM,
+        },
+        /* File (D1_0) devices */
+        {
+                .name           = "pdma0",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA0,
+        }, {
+                .name           = "pdma1",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_PDMA1,
+        }, {
+                .name           = "usb-host",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_USBHOST,
+        }, {
+                .name           = "modem",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_MODEMIF,
+        }, {
+                .name           = "hsmmc",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC0,
+        }, {
+                .name           = "hsmmc",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC1,
+        }, {
+                .name           = "hsmmc",
+                .id             = 2,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d10_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D10_HSMMC2,
+        },
+        /* Multimedia1 (D1_1) devices */
+        {
+                .name           = "lcd",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_LCD,
+        }, {
+                .name           = "rotator",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_ROTATOR,
+        }, {
+                .name           = "fimc",
+                .id             = 0,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC0,
+        }, {
+                .name           = "fimc",
+                .id             = 1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC1,
+        }, {
+                .name           = "fimc",
+                .id             = 2,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_FIMC2,
+        }, {
+                .name           = "jpeg",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_JPEG,
+        }, {
+                .name           = "g3d",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d11_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D11_G3D,
+        },
+        /* Multimedia2 (D1_2) devices */
+        {
+                .name           = "tv",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_TV,
+        }, {
+                .name           = "vp",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_VP,
+        }, {
+                .name           = "mixer",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MIXER,
+        }, {
+                .name           = "hdmi",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_HDMI,
+        }, {
+                .name           = "mfc",
+                .id             = -1,
+                .parent         = &clk_h,
+                .enable         = s5pc1xx_clk_d12_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D12_MFC,
+        },
+        /* System (D1_3) devices */
+        {
+                .name           = "chipid",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_CHIPID,
+        }, {
+                .name           = "gpio",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_GPIO,
+        }, {
+                .name           = "apc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_APC,
+        }, {
+                .name           = "iec",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_IEC,
+        }, {
+                .name           = "timers",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_PWM,
+        }, {
+                .name           = "systimer",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_SYSTIMER,
+        }, {
+                .name           = "watchdog",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_WDT,
+        }, {
+                .name           = "rtc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d13_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D13_RTC,
+        },
+        /* Connectivity (D1_4) devices */
+        {
+                .name           = "uart",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART0,
+        }, {
+                .name           = "uart",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART1,
+        }, {
+                .name           = "uart",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART2,
+        }, {
+                .name           = "uart",
+                .id             = 3,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_UART3,
+        }, {
+                .name           = "i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IIC,
+        }, {
+                .name           = "hdmi-i2c",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HDMI_IIC,
+        }, {
+                .name           = "spi",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI0,
+        }, {
+                .name           = "spi",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI1,
+        }, {
+                .name           = "spi",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_SPI2,
+        }, {
+                .name           = "irda",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_IRDA,
+        }, {
+                .name           = "hsitx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSITX,
+        }, {
+                .name           = "hsirx",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d14_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D14_HSIRX,
+        },
+        /* Audio (D1_5) devices */
+        {
+                .name           = "iis",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS0,
+        }, {
+                .name           = "iis",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS1,
+        }, {
+                .name           = "iis",
+                .id             = 2,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_IIS2,
+        }, {
+                .name           = "ac97",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_AC97,
+        }, {
+                .name           = "pcm",
+                .id             = 0,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM0,
+        }, {
+                .name           = "pcm",
+                .id             = 1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_PCM1,
+        }, {
+                .name           = "spdif",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_SPDIF,
+        }, {
+                .name           = "adc",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_TSADC,
+        }, {
+                .name           = "keyif",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_KEYIF,
+        }, {
+                .name           = "cg",
+                .id             = -1,
+                .parent         = &clk_p,
+                .enable         = s5pc1xx_clk_d15_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_D15_CG,
+        },
+        /* Audio (D2_0) devices: all disabled */
+        /* Special Clocks 1 */
+        {
+                .name           = "sclk_hpm",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC1XX_CLKGATE_SCLK0_HPM,
+        }, {
+                .name           = "sclk_onenand",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_ONENAND,
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI0_48,
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI1_48,
+        }, {
+                .name           = "sclk_spi_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_SPI2_48,
+        }, {
+                .name           = "sclk_mmc_48",
+                .id             = 0,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC0_48,
+        }, {
+                .name           = "sclk_mmc_48",
+                .id             = 1,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC1_48,
+        }, {
+                .name           = "sclk_mmc_48",
+                .id             = 2,
+                .parent         = &clk_48m,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_MMC2_48,
+        },
+        /* Special Clocks 2 */
+        {
+                .name           = "sclk_tv_54",
+                .id             = -1,
+                .parent         = &clk_54m,
+                .enable         = s5pc1xx_sclk1_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_TV54,
+        }, {
+                .name           = "sclk_vdac_54",
+                .id             = -1,
+                .parent         = &clk_54m,
+                .enable         = s5pc1xx_sclk1_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_VDAC54,
+        }, {
+                .name           = "sclk_spdif",
+                .id             = -1,
+                .parent         = NULL,
+                .enable         = s5pc1xx_sclk1_ctrl,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK1_SPDIF,
+        },
+};
+void __init s5pc1xx_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+        clkp = init_clocks;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+        clkp = init_clocks_disable;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+                (clkp->enable)(clkp, 0);
+        }
+        s3c_pwmclk_init();
+}
+static struct clk clk_fout_apll = {
+        .name           = "fout_apll",
+        .id             = -1,
+};
+static struct clk *clk_src_apll_list[] = {
+        [0] = &clk_fin_apll,
+        [1] = &clk_fout_apll,
+};
+static struct clk_sources clk_src_apll = {
+        .sources        = clk_src_apll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_apll_list),
+};
+static struct clksrc_clk clk_mout_apll = {
+        .clk    = {
+                .name           = "mout_apll",
+                .id             = -1,
+        },
+        .shift          = S5PC1XX_CLKSRC0_APLL_SHIFT,
+        .mask           = S5PC1XX_CLKSRC0_APLL_MASK,
+        .sources        = &clk_src_apll,
+        .reg_source     = S5PC1XX_CLK_SRC0,
+};
+static struct clk clk_fout_epll = {
+        .name           = "fout_epll",
+        .id             = -1,
+};
+static struct clk *clk_src_epll_list[] = {
+        [0] = &clk_fin_epll,
+        [1] = &clk_fout_epll,
+};
+static struct clk_sources clk_src_epll = {
+        .sources        = clk_src_epll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_epll_list),
+};
+static struct clksrc_clk clk_mout_epll = {
+        .clk    = {
+                .name           = "mout_epll",
+                .id             = -1,
+        },
+        .shift          = S5PC1XX_CLKSRC0_EPLL_SHIFT,
+        .mask           = S5PC1XX_CLKSRC0_EPLL_MASK,
+        .sources        = &clk_src_epll,
+        .reg_source     = S5PC1XX_CLK_SRC0,
+};
+static struct clk *clk_src_mpll_list[] = {
+        [0] = &clk_fin_mpll,
+        [1] = &clk_fout_mpll,
+};
+static struct clk_sources clk_src_mpll = {
+        .sources        = clk_src_mpll_list,
+        .nr_sources     = ARRAY_SIZE(clk_src_mpll_list),
+};
+static struct clksrc_clk clk_mout_mpll = {
+        .clk = {
+                .name           = "mout_mpll",
+                .id             = -1,
+        },
+        .shift          = S5PC1XX_CLKSRC0_MPLL_SHIFT,
+        .mask           = S5PC1XX_CLKSRC0_MPLL_MASK,
+        .sources        = &clk_src_mpll,
+        .reg_source     = S5PC1XX_CLK_SRC0,
+};
+static unsigned long s5pc1xx_clk_doutmpll_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv;
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
+        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL_MASK;
+        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL_SHIFT) + 1;
+        return rate;
+}
+static struct clk clk_dout_mpll = {
+        .name           = "dout_mpll",
+        .id             = -1,
+        .parent         = &clk_mout_mpll.clk,
+        .get_rate       = s5pc1xx_clk_doutmpll_get_rate,
+};
+static unsigned long s5pc1xx_clk_doutmpll2_get_rate(struct clk *clk)
+{
+        unsigned long rate = clk_get_rate(clk->parent);
+        unsigned long clkdiv;
+        printk(KERN_DEBUG "%s: parent is %ld\n", __func__, rate);
+        clkdiv = __raw_readl(S5PC1XX_CLK_DIV1) & S5PC100_CLKDIV1_MPLL2_MASK;
+        rate /= (clkdiv >> S5PC100_CLKDIV1_MPLL2_SHIFT) + 1;
+        return rate;
+}
+struct clk clk_dout_mpll2 = {
+        .name           = "dout_mpll2",
+        .id             = -1,
+        .parent         = &clk_mout_mpll.clk,
+        .get_rate       = s5pc1xx_clk_doutmpll2_get_rate,
+};
+static struct clk *clkset_uart_list[] = {
+        &clk_mout_epll.clk,
+        &clk_dout_mpll,
+        NULL,
+        NULL
+};
+static struct clk_sources clkset_uart = {
+        .sources        = clkset_uart_list,
+        .nr_sources     = ARRAY_SIZE(clkset_uart_list),
+};
+static inline struct clksrc_clk *to_clksrc(struct clk *clk)
+{
+        return container_of(clk, struct clksrc_clk, clk);
+}
+static unsigned long s5pc1xx_getrate_clksrc(struct clk *clk)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        unsigned long rate = clk_get_rate(clk->parent);
+        u32 clkdiv = __raw_readl(sclk->reg_divider);
+        clkdiv >>= sclk->divider_shift;
+        clkdiv &= 0xf;
+        clkdiv++;
+        rate /= clkdiv;
+        return rate;
+}
+static int s5pc1xx_setrate_clksrc(struct clk *clk, unsigned long rate)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        void __iomem *reg = sclk->reg_divider;
+        unsigned int div;
+        u32 val;
+        rate = clk_round_rate(clk, rate);
+        div = clk_get_rate(clk->parent) / rate;
+        if (div > 16)
+                return -EINVAL;
+        val = __raw_readl(reg);
+        val &= ~(0xf << sclk->shift);
+        val |= (div - 1) << sclk->shift;
+        __raw_writel(val, reg);
+        return 0;
+}
+static int s5pc1xx_setparent_clksrc(struct clk *clk, struct clk *parent)
+{
+        struct clksrc_clk *sclk = to_clksrc(clk);
+        struct clk_sources *srcs = sclk->sources;
+        u32 clksrc = __raw_readl(sclk->reg_source);
+        int src_nr = -1;
+        int ptr;
+        for (ptr = 0; ptr < srcs->nr_sources; ptr++)
+                if (srcs->sources[ptr] == parent) {
+                        src_nr = ptr;
+                        break;
+                }
+        if (src_nr >= 0) {
+                clksrc &= ~sclk->mask;
+                clksrc |= src_nr << sclk->shift;
+                __raw_writel(clksrc, sclk->reg_source);
+                return 0;
+        }
+        return -EINVAL;
+}
+static unsigned long s5pc1xx_roundrate_clksrc(struct clk *clk,
+                                              unsigned long rate)
+{
+        unsigned long parent_rate = clk_get_rate(clk->parent);
+        int div;
+        if (rate > parent_rate)
+                rate = parent_rate;
+        else {
+                div = rate / parent_rate;
+                if (div == 0)
+                        div = 1;
+                if (div > 16)
+                        div = 16;
+                rate = parent_rate / div;
+        }
+        return rate;
+}
+static struct clksrc_clk clk_uart_uclk1 = {
+        .clk    = {
+                .name           = "uclk1",
+                .id             = -1,
+                .ctrlbit        = S5PC100_CLKGATE_SCLK0_UART,
+                .enable         = s5pc1xx_sclk0_ctrl,
+                .set_parent     = s5pc1xx_setparent_clksrc,
+                .get_rate       = s5pc1xx_getrate_clksrc,
+                .set_rate       = s5pc1xx_setrate_clksrc,
+                .round_rate     = s5pc1xx_roundrate_clksrc,
+        },
+        .shift          = S5PC100_CLKSRC1_UART_SHIFT,
+        .mask           = S5PC100_CLKSRC1_UART_MASK,
+        .sources        = &clkset_uart,
+        .divider_shift  = S5PC100_CLKDIV2_UART_SHIFT,
+        .reg_divider    = S5PC1XX_CLK_DIV2,
+        .reg_source     = S5PC1XX_CLK_SRC1,
+};
+/* Clock initialisation code */
+static struct clksrc_clk *init_parents[] = {
+        &clk_mout_apll,
+        &clk_mout_epll,
+        &clk_mout_mpll,
+        &clk_uart_uclk1,
+};
+static void __init_or_cpufreq s5pc1xx_set_clksrc(struct clksrc_clk *clk)
+{
+        struct clk_sources *srcs = clk->sources;
+        u32 clksrc = __raw_readl(clk->reg_source);
+        clksrc &= clk->mask;
+        clksrc >>= clk->shift;
+        if (clksrc > srcs->nr_sources || !srcs->sources[clksrc]) {
+                printk(KERN_ERR "%s: bad source %d\n",
+                       clk->clk.name, clksrc);
+                return;
+        }
+        clk->clk.parent = srcs->sources[clksrc];
+        printk(KERN_INFO "%s: source is %s (%d), rate is %ld\n",
+               clk->clk.name, clk->clk.parent->name, clksrc,
+               clk_get_rate(&clk->clk));
+}
+#define GET_DIV(clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1)
+void __init_or_cpufreq s5pc100_setup_clocks(void)
+{
+        struct clk *xtal_clk;
+        unsigned long xtal;
+        unsigned long armclk;
+        unsigned long hclkd0;
+        unsigned long hclk;
+        unsigned long pclkd0;
+        unsigned long pclk;
+        unsigned long apll;
+        unsigned long mpll;
+        unsigned long hpll;
+        unsigned long epll;
+        unsigned int ptr;
+        u32 clkdiv0, clkdiv1;
+        printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+        clkdiv0 = __raw_readl(S5PC1XX_CLK_DIV0);
+        clkdiv1 = __raw_readl(S5PC1XX_CLK_DIV1);
+        printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n",
+                        __func__, clkdiv0, clkdiv1);
+        xtal_clk = clk_get(NULL, "xtal");
+        BUG_ON(IS_ERR(xtal_clk));
+        xtal = clk_get_rate(xtal_clk);
+        clk_put(xtal_clk);
+        printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+        apll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_APLL_CON));
+        mpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_MPLL_CON));
+        epll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC1XX_EPLL_CON));
+        hpll = s5pc1xx_get_pll(xtal, __raw_readl(S5PC100_HPLL_CON));
+        printk(KERN_INFO "S5PC100: PLL settings, A=%ld, M=%ld, E=%ld, H=%ld\n",
+               apll, mpll, epll, hpll);
+        armclk = apll / GET_DIV(clkdiv0, S5PC1XX_CLKDIV0_APLL);
+        armclk = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_ARM);
+        hclkd0 = armclk / GET_DIV(clkdiv0, S5PC100_CLKDIV0_D0);
+        pclkd0 = hclkd0 / GET_DIV(clkdiv0, S5PC100_CLKDIV0_PCLKD0);
+        hclk = mpll / GET_DIV(clkdiv1, S5PC100_CLKDIV1_D1);
+        pclk = hclk / GET_DIV(clkdiv1, S5PC100_CLKDIV1_PCLKD1);
+        printk(KERN_INFO "S5PC100: ARMCLK=%ld, HCLKD0=%ld, PCLKD0=%ld, HCLK=%ld, PCLK=%ld\n",
+               armclk, hclkd0, pclkd0, hclk, pclk);
+        clk_fout_apll.rate = apll;
+        clk_fout_mpll.rate = mpll;
+        clk_fout_epll.rate = epll;
+        clk_fout_apll.rate = apll;
+        clk_h.rate = hclk;
+        clk_p.rate = pclk;
+        for (ptr = 0; ptr < ARRAY_SIZE(init_parents); ptr++)
+                s5pc1xx_set_clksrc(init_parents[ptr]);
+}
+static struct clk *clks[] __initdata = {
+        &clk_ext_xtal_mux,
+        &clk_mout_epll.clk,
+        &clk_fout_epll,
+        &clk_mout_mpll.clk,
+        &clk_dout_mpll,
+        &clk_uart_uclk1.clk,
+        &clk_ext,
+        &clk_epll,
+        &clk_27m,
+        &clk_48m,
+        &clk_54m,
+};
+void __init s5pc100_register_clocks(void)
+{
+        struct clk *clkp;
+        int ret;
+        int ptr;
+        for (ptr = 0; ptr < ARRAY_SIZE(clks); ptr++) {
+                clkp = clks[ptr];
+                ret = s3c24xx_register_clock(clkp);
+                if (ret < 0) {
+                        printk(KERN_ERR "Failed to register clock %s (%d)\n",
+                               clkp->name, ret);
+                }
+        }
+        clk_mpll.parent = &clk_mout_mpll.clk;
+        clk_epll.parent = &clk_mout_epll.clk;
+}
diff --git a/arch/arm/plat-s5pc1xx/s5pc100-init.c b/arch/arm/plat-s5pc1xx/s5pc100-init.c
new file mode 100644
index 000000000000..c58710884ceb
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/s5pc100-init.c
@@ -0,0 +1,27 @@
+/* linux/arch/arm/plat-s5pc1xx/s5pc100-init.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * S5PC100 - CPU initialisation (common with other S5PC1XX chips)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <plat/cpu.h>
+#include <plat/devs.h>
+#include <plat/s5pc100.h>
+/* uart registration process */
+void __init s5pc100_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
+{
+        /* The driver name is s3c6400-uart to reuse s3c6400_serial_drv  */
+        s3c24xx_init_uartdevs("s3c6400-uart", s5pc1xx_uart_resources, cfg, no);
+}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c0.c b/arch/arm/plat-s5pc1xx/setup-i2c0.c
new file mode 100644
index 000000000000..3d00c025fffb
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-i2c0.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC1XX I2C bus 0 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c0.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+struct platform_device; /* don't need the contents */
+#include <plat/iic.h>
+void s3c_i2c0_cfg_gpio(struct platform_device *dev)
+{
+        /* Pin configuration would be needed */
+}
diff --git a/arch/arm/plat-s5pc1xx/setup-i2c1.c b/arch/arm/plat-s5pc1xx/setup-i2c1.c
new file mode 100644
index 000000000000..c8f3ca42f51d
--- /dev/null
+++ b/arch/arm/plat-s5pc1xx/setup-i2c1.c
@@ -0,0 +1,25 @@
+/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c
+ *
+ * Copyright 2009 Samsung Electronics Co.
+ *      Byungho Min <bhmin@samsung.com>
+ *
+ * Base S5PC1XX I2C bus 1 gpio configuration
+ *
+ * Based on plat-s3c64xx/setup-i2c1.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <linux/kernel.h>
+#include <linux/types.h>
+struct platform_device; /* don't need the contents */
+#include <plat/iic.h>
+void s3c_i2c1_cfg_gpio(struct platform_device *dev)
+{
+        /* Pin configuration would be needed */
+}
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 33026eff2aa4..c8c55b469342 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -12,7 +12,7 @@
 #
 #   http://www.arm.linux.org.uk/developer/machines/?action=new
 #
-# Last update: Sat Jun 20 22:28:39 2009
+# Last update: Sat Sep 12 12:00:16 2009
 #
 # machine_is_xxx        CONFIG_xxxx             MACH_TYPE_xxx           number
 #
@@ -1769,7 +1769,7 @@ mx31cicada		MACH_MX31CICADA		MX31CICADA		1777
 mi424wr                 MACH_MI424WR            MI424WR                 1778
 axs_ultrax              MACH_AXS_ULTRAX         AXS_ULTRAX              1779
 at572d940deb            MACH_AT572D940DEB       AT572D940DEB            1780
-davinci_da8xx_evm       MACH_DAVINCI_DA8XX_EVM  DAVINCI_DA8XX_EVM       1781
+davinci_da830_evm       MACH_DAVINCI_DA830_EVM  DAVINCI_DA830_EVM       1781
 ep9302                  MACH_EP9302             EP9302                  1782
 at572d940hfek           MACH_AT572D940HFEB      AT572D940HFEB           1783
 cybook3                 MACH_CYBOOK3            CYBOOK3                 1784
@@ -1962,7 +1962,7 @@ ethernut5		MACH_ETHERNUT5		ETHERNUT5		1971
 arm11                   MACH_ARM11              ARM11                   1972
 cpuat9260               MACH_CPUAT9260          CPUAT9260               1973
 cpupxa255               MACH_CPUPXA255          CPUPXA255               1974
-cpuimx27                MACH_CPUIMX27           CPUIMX27                1975
+eukrea_cpuimx27         MACH_CPUIMX27           CPUIMX27                1975
 cheflux                 MACH_CHEFLUX            CHEFLUX                 1976
 eb_cpux9k2              MACH_EB_CPUX9K2         EB_CPUX9K2              1977
 opcotec                 MACH_OPCOTEC            OPCOTEC                 1978
@@ -2249,14 +2249,14 @@ omap3_phrazer		MACH_OMAP3_PHRAZER	OMAP3_PHRAZER		2261
 darwin                  MACH_DARWIN             DARWIN                  2262
 oratiscomu              MACH_ORATISCOMU         ORATISCOMU              2263
 rtsbc20                 MACH_RTSBC20            RTSBC20                 2264
-i780                    MACH_I780               I780                    2265
+sgh_i780                MACH_I780               I780                    2265
 gemini324               MACH_GEMINI324          GEMINI324               2266
 oratislan               MACH_ORATISLAN          ORATISLAN               2267
 oratisalog              MACH_ORATISALOG         ORATISALOG              2268
 oratismadi              MACH_ORATISMADI         ORATISMADI              2269
 oratisot16              MACH_ORATISOT16         ORATISOT16              2270
 oratisdesk              MACH_ORATISDESK         ORATISDESK              2271
-v2p_ca9                 MACH_V2P_CA9            V2P_CA9                 2272
+v2_ca9                  MACH_V2P_CA9            V2P_CA9                 2272
 sintexo                 MACH_SINTEXO            SINTEXO                 2273
 cm3389                  MACH_CM3389             CM3389                  2274
 omap3_cio               MACH_OMAP3_CIO          OMAP3_CIO               2275
@@ -2280,3 +2280,132 @@ htcrhodium		MACH_HTCRHODIUM		HTCRHODIUM		2292
 htctopaz                MACH_HTCTOPAZ           HTCTOPAZ                2293
 matrix504               MACH_MATRIX504          MATRIX504               2294
 mrfsa                   MACH_MRFSA              MRFSA                   2295
+sc_p270                 MACH_SC_P270            SC_P270                 2296
+atlas5_evb              MACH_ATLAS5_EVB         ATLAS5_EVB              2297
+pelco_lobox             MACH_PELCO_LOBOX        PELCO_LOBOX             2298
+dilax_pcu200            MACH_DILAX_PCU200       DILAX_PCU200            2299
+leonardo                MACH_LEONARDO           LEONARDO                2300
+zoran_approach7         MACH_ZORAN_APPROACH7    ZORAN_APPROACH7         2301
+dp6xx                   MACH_DP6XX              DP6XX                   2302
+bcm2153_vesper          MACH_BCM2153_VESPER     BCM2153_VESPER          2303
+mahimahi                MACH_MAHIMAHI           MAHIMAHI                2304
+clickc                  MACH_CLICKC             CLICKC                  2305
+zb_gateway              MACH_ZB_GATEWAY         ZB_GATEWAY              2306
+tazcard                 MACH_TAZCARD            TAZCARD                 2307
+tazdev                  MACH_TAZDEV             TAZDEV                  2308
+annax_cb_arm            MACH_ANNAX_CB_ARM       ANNAX_CB_ARM            2309
+annax_dm3               MACH_ANNAX_DM3          ANNAX_DM3               2310
+cerebric                MACH_CEREBRIC           CEREBRIC                2311
+orca                    MACH_ORCA               ORCA                    2312
+pc9260                  MACH_PC9260             PC9260                  2313
+ems285a                 MACH_EMS285A            EMS285A                 2314
+gec2410                 MACH_GEC2410            GEC2410                 2315
+gec2440                 MACH_GEC2440            GEC2440                 2316
+mw903                   MACH_ARCH_MW903         ARCH_MW903              2317
+mw2440                  MACH_MW2440             MW2440                  2318
+ecac2378                MACH_ECAC2378           ECAC2378                2319
+tazkiosk                MACH_TAZKIOSK           TAZKIOSK                2320
+whiterabbit_mch         MACH_WHITERABBIT_MCH    WHITERABBIT_MCH         2321
+sbox9263                MACH_SBOX9263           SBOX9263                2322
+oreo                    MACH_OREO               OREO                    2323
+smdk6442                MACH_SMDK6442           SMDK6442                2324
+openrd_base             MACH_OPENRD_BASE        OPENRD_BASE             2325
+incredible              MACH_INCREDIBLE         INCREDIBLE              2326
+incrediblec             MACH_INCREDIBLEC        INCREDIBLEC             2327
+heroct                  MACH_HEROCT             HEROCT                  2328
+mmnet1000               MACH_MMNET1000          MMNET1000               2329
+devkit8000              MACH_DEVKIT8000         DEVKIT8000              2330
+devkit9000              MACH_DEVKIT9000         DEVKIT9000              2331
+mx31txtr                MACH_MX31TXTR           MX31TXTR                2332
+u380                    MACH_U380               U380                    2333
+oamp3_hualu             MACH_HUALU_BOARD        HUALU_BOARD             2334
+npcmx50                 MACH_NPCMX50            NPCMX50                 2335
+mx51_lange51            MACH_MX51_LANGE51       MX51_LANGE51            2336
+mx51_lange52            MACH_MX51_LANGE52       MX51_LANGE52            2337
+riom                    MACH_RIOM               RIOM                    2338
+comcas                  MACH_COMCAS             COMCAS                  2339
+wsi_mx27                MACH_WSI_MX27           WSI_MX27                2340
+cm_t35                  MACH_CM_T35             CM_T35                  2341
+net2big                 MACH_NET2BIG            NET2BIG                 2342
+motorola_a1600          MACH_MOTOROLA_A1600     MOTOROLA_A1600          2343
+igep0020                MACH_IGEP0020           IGEP0020                2344
+igep0010                MACH_IGEP0010           IGEP0010                2345
+mv6281gtwge2            MACH_MV6281GTWGE2       MV6281GTWGE2            2346
+scat100                 MACH_SCAT100            SCAT100                 2347
+sanmina                 MACH_SANMINA            SANMINA                 2348
+momento                 MACH_MOMENTO            MOMENTO                 2349
+nuc9xx                  MACH_NUC9XX             NUC9XX                  2350
+nuc910evb               MACH_NUC910EVB          NUC910EVB               2351
+nuc920evb               MACH_NUC920EVB          NUC920EVB               2352
+nuc950evb               MACH_NUC950EVB          NUC950EVB               2353
+nuc945evb               MACH_NUC945EVB          NUC945EVB               2354
+nuc960evb               MACH_NUC960EVB          NUC960EVB               2355
+nuc932evb               MACH_NUC932EVB          NUC932EVB               2356
+nuc900                  MACH_NUC900             NUC900                  2357
+sd1soc                  MACH_SD1SOC             SD1SOC                  2358
+ln2440bc                MACH_LN2440BC           LN2440BC                2359
+rsbc                    MACH_RSBC               RSBC                    2360
+openrd_client           MACH_OPENRD_CLIENT      OPENRD_CLIENT           2361
+hpipaq11x               MACH_HPIPAQ11X          HPIPAQ11X               2362
+wayland                 MACH_WAYLAND            WAYLAND                 2363
+acnbsx102               MACH_ACNBSX102          ACNBSX102               2364
+hwat91                  MACH_HWAT91             HWAT91                  2365
+at91sam9263cs           MACH_AT91SAM9263CS      AT91SAM9263CS           2366
+csb732                  MACH_CSB732             CSB732                  2367
+u8500                   MACH_U8500              U8500                   2368
+huqiu                   MACH_HUQIU              HUQIU                   2369
+mx51_kunlun             MACH_MX51_KUNLUN        MX51_KUNLUN             2370
+pmt1g                   MACH_PMT1G              PMT1G                   2371
+htcelf                  MACH_HTCELF             HTCELF                  2372
+armadillo420            MACH_ARMADILLO420       ARMADILLO420            2373
+armadillo440            MACH_ARMADILLO440       ARMADILLO440            2374
+u_chip_dual_arm         MACH_U_CHIP_DUAL_ARM    U_CHIP_DUAL_ARM         2375
+csr_bdb3                MACH_CSR_BDB3           CSR_BDB3                2376
+dolby_cat1018           MACH_DOLBY_CAT1018      DOLBY_CAT1018           2377
+hy9307                  MACH_HY9307             HY9307                  2378
+aspire_easystore        MACH_A_ES               A_ES                    2379
+davinci_irif            MACH_DAVINCI_IRIF       DAVINCI_IRIF            2380
+agama9263               MACH_AGAMA9263          AGAMA9263               2381
+marvell_jasper          MACH_MARVELL_JASPER     MARVELL_JASPER          2382
+flint                   MACH_FLINT              FLINT                   2383
+tavorevb3               MACH_TAVOREVB3          TAVOREVB3               2384
+sch_m490                MACH_SCH_M490           SCH_M490                2386
+rbl01                   MACH_RBL01              RBL01                   2387
+omnifi                  MACH_OMNIFI             OMNIFI                  2388
+otavalo                 MACH_OTAVALO            OTAVALO                 2389
+sienna                  MACH_SIENNA             SIENNA                  2390
+htc_excalibur_s620      MACH_HTC_EXCALIBUR_S620 HTC_EXCALIBUR_S620      2391
+htc_opal                MACH_HTC_OPAL           HTC_OPAL                2392
+touchbook               MACH_TOUCHBOOK          TOUCHBOOK               2393
+latte                   MACH_LATTE              LATTE                   2394
+xa200                   MACH_XA200              XA200                   2395
+nimrod                  MACH_NIMROD             NIMROD                  2396
+cc9p9215_3g             MACH_CC9P9215_3G        CC9P9215_3G             2397
+cc9p9215_3gjs           MACH_CC9P9215_3GJS      CC9P9215_3GJS           2398
+tk71                    MACH_TK71               TK71                    2399
+comham3525              MACH_COMHAM3525         COMHAM3525              2400
+mx31erebus              MACH_MX31EREBUS         MX31EREBUS              2401
+mcardmx27               MACH_MCARDMX27          MCARDMX27               2402
+paradise                MACH_PARADISE           PARADISE                2403
+tide                    MACH_TIDE               TIDE                    2404
+wzl2440                 MACH_WZL2440            WZL2440                 2405
+sdrdemo                 MACH_SDRDEMO            SDRDEMO                 2406
+ethercan2               MACH_ETHERCAN2          ETHERCAN2               2407
+ecmimg20                MACH_ECMIMG20           ECMIMG20                2408
+omap_dragon             MACH_OMAP_DRAGON        OMAP_DRAGON             2409
+halo                    MACH_HALO               HALO                    2410
+huangshan               MACH_HUANGSHAN          HUANGSHAN               2411
+vl_ma2sc                MACH_VL_MA2SC           VL_MA2SC                2412
+raumfeld_rc             MACH_RAUMFELD_RC        RAUMFELD_RC             2413
+raumfeld_connector      MACH_RAUMFELD_CONNECTOR RAUMFELD_CONNECTOR      2414
+raumfeld_speaker        MACH_RAUMFELD_SPEAKER   RAUMFELD_SPEAKER        2415
+multibus_master         MACH_MULTIBUS_MASTER    MULTIBUS_MASTER         2416
+multibus_pbk            MACH_MULTIBUS_PBK       MULTIBUS_PBK            2417
+tnetv107x               MACH_TNETV107X          TNETV107X               2418
+snake                   MACH_SNAKE              SNAKE                   2419
+cwmx27                  MACH_CWMX27             CWMX27                  2420
+sch_m480                MACH_SCH_M480           SCH_M480                2421
+platypus                MACH_PLATYPUS           PLATYPUS                2422
+pss2                    MACH_PSS2               PSS2                    2423
+davinci_apm150          MACH_DAVINCI_APM150     DAVINCI_APM150          2424
+str9100                 MACH_STR9100            STR9100                 2425
diff --git a/arch/arm/vfp/entry.S b/arch/arm/vfp/entry.S
index a2bed62aec21..4fa9903b83cf 100644
--- a/arch/arm/vfp/entry.S
+++ b/arch/arm/vfp/entry.S
@@ -42,6 +42,7 @@ ENTRY(vfp_null_entry)
        mov     pc, lr
 ENDPROC(vfp_null_entry)
+        .align  2
 .LCvfp:
        .word   vfp_vector
@@ -61,6 +62,7 @@ ENTRY(vfp_testing_entry)
        mov     pc, r9                  @ we have handled the fault
 ENDPROC(vfp_testing_entry)
+        .align  2
 VFP_arch_address:
        .word   VFP_arch
diff --git a/arch/arm/vfp/vfphw.S b/arch/arm/vfp/vfphw.S
index 1aeae38725dd..66dc2d03b7fc 100644
--- a/arch/arm/vfp/vfphw.S
+++ b/arch/arm/vfp/vfphw.S
@@ -209,40 +209,55 @@ ENDPROC(vfp_save_state)
 last_VFP_context_address:
        .word   last_VFP_context
-ENTRY(vfp_get_float)
+        .macro  tbl_branch, base, tmp, shift
-        add     pc, pc, r0, lsl #3
+#ifdef CONFIG_THUMB2_KERNEL
+        adr     \tmp, 1f
+        add     \tmp, \tmp, \base, lsl \shift
+        mov     pc, \tmp
+#else
+        add     pc, pc, \base, lsl \shift
        mov     r0, r0
+#endif
+1:
+        .endm
+ENTRY(vfp_get_float)
+        tbl_branch r0, r3, #3
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
+1:      mrc     p10, 0, r0, c\dr, c0, 0 @ fmrs  r0, s0
        mov     pc, lr
-        mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
+        .org    1b + 8
+1:      mrc     p10, 0, r0, c\dr, c0, 4 @ fmrs  r0, s1
        mov     pc, lr
+        .org    1b + 8
        .endr
 ENDPROC(vfp_get_float)
 ENTRY(vfp_put_float)
-        add     pc, pc, r1, lsl #3
+        tbl_branch r1, r3, #3
-        mov     r0, r0
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
+1:      mcr     p10, 0, r0, c\dr, c0, 0 @ fmsr  r0, s0
        mov     pc, lr
-        mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
+        .org    1b + 8
+1:      mcr     p10, 0, r0, c\dr, c0, 4 @ fmsr  r0, s1
        mov     pc, lr
+        .org    1b + 8
        .endr
 ENDPROC(vfp_put_float)
 ENTRY(vfp_get_double)
-        add     pc, pc, r0, lsl #3
+        tbl_branch r0, r3, #3
-        mov     r0, r0
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        fmrrd   r0, r1, d\dr
+1:      fmrrd   r0, r1, d\dr
        mov     pc, lr
+        .org    1b + 8
        .endr
 #ifdef CONFIG_VFPv3
        @ d16 - d31 registers
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
+1:      mrrc    p11, 3, r0, r1, c\dr    @ fmrrd r0, r1, d\dr
        mov     pc, lr
+        .org    1b + 8
        .endr
 #endif
@@ -253,17 +268,18 @@ ENTRY(vfp_get_double)
 ENDPROC(vfp_get_double)
 ENTRY(vfp_put_double)
-        add     pc, pc, r2, lsl #3
+        tbl_branch r2, r3, #3
-        mov     r0, r0
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        fmdrr   d\dr, r0, r1
+1:      fmdrr   d\dr, r0, r1
        mov     pc, lr
+        .org    1b + 8
        .endr
 #ifdef CONFIG_VFPv3
        @ d16 - d31 registers
        .irp    dr,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
-        mcrr    p11, 3, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
+1:      mcrr    p11, 3, r1, r2, c\dr    @ fmdrr r1, r2, d\dr
        mov     pc, lr
+        .org    1b + 8
        .endr
 #endif
 ENDPROC(vfp_put_double)
diff --git a/arch/avr32/include/asm/socket.h b/arch/avr32/include/asm/socket.h
index 04c860619700..fe863f9794d5 100644
--- a/arch/avr32/include/asm/socket.h
+++ b/arch/avr32/include/asm/socket.h
@@ -57,4 +57,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* __ASM_AVR32_SOCKET_H */
diff --git a/arch/avr32/include/asm/thread_info.h b/arch/avr32/include/asm/thread_info.h
index fc42de5ca209..fd0c5d7e9337 100644
--- a/arch/avr32/include/asm/thread_info.h
+++ b/arch/avr32/include/asm/thread_info.h
@@ -84,6 +84,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_MEMDIE              6
 #define TIF_RESTORE_SIGMASK     7       /* restore signal mask in do_signal */
 #define TIF_CPU_GOING_TO_SLEEP  8       /* CPU is entering sleep 0 mode */
+#define TIF_NOTIFY_RESUME       9       /* callback before returning to user */
 #define TIF_FREEZE              29
 #define TIF_DEBUG               30      /* debugging enabled */
 #define TIF_USERSPACE           31      /* true if FS sets userspace */
@@ -96,6 +97,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_MEMDIE             (1 << TIF_MEMDIE)
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
 #define _TIF_CPU_GOING_TO_SLEEP (1 << TIF_CPU_GOING_TO_SLEEP)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
 /* Note: The masks below must never span more than 16 bits! */
@@ -103,13 +105,15 @@ static inline struct thread_info *current_thread_info(void)
 /* work to do on interrupt/exception return */
 #define _TIF_WORK_MASK                          \
        ((1 << TIF_SIGPENDING)                  \
+         | _TIF_NOTIFY_RESUME                   \
         | (1 << TIF_NEED_RESCHED)              \
         | (1 << TIF_POLLING_NRFLAG)            \
         | (1 << TIF_BREAKPOINT)                \
         | (1 << TIF_RESTORE_SIGMASK))
 /* work to do on any return to userspace */
-#define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK | (1 << TIF_SYSCALL_TRACE))
+#define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK | (1 << TIF_SYSCALL_TRACE) | \
+                                 _TIF_NOTIFY_RESUME)
 /* work to do on return from debug mode */
 #define _TIF_DBGWORK_MASK       (_TIF_WORK_MASK & ~(1 << TIF_BREAKPOINT))
diff --git a/arch/avr32/kernel/entry-avr32b.S b/arch/avr32/kernel/entry-avr32b.S
index 009a80155d67..169268c40ae2 100644
--- a/arch/avr32/kernel/entry-avr32b.S
+++ b/arch/avr32/kernel/entry-avr32b.S
@@ -281,7 +281,7 @@ syscall_exit_work:
        ld.w    r1, r0[TI_flags]
        rjmp    1b
-2:      mov     r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK
+2:      mov     r2, _TIF_SIGPENDING | _TIF_RESTORE_SIGMASK | _TIF_NOTIFY_RESUME
        tst     r1, r2
        breq    3f
        unmask_interrupts
diff --git a/arch/avr32/kernel/signal.c b/arch/avr32/kernel/signal.c
index 27227561bad6..64f886fac2ef 100644
--- a/arch/avr32/kernel/signal.c
+++ b/arch/avr32/kernel/signal.c
@@ -16,6 +16,7 @@
 #include <linux/ptrace.h>
 #include <linux/unistd.h>
 #include <linux/freezer.h>
+#include <linux/tracehook.h>
 #include <asm/uaccess.h>
 #include <asm/ucontext.h>
@@ -322,4 +323,11 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, struct thread_info *ti)
        if (ti->flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
                do_signal(regs, &current->blocked, syscall);
+        if (ti->flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/blackfin/include/asm/bfin_rotary.h b/arch/blackfin/include/asm/bfin_rotary.h
new file mode 100644
index 000000000000..425ece64fd5e
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_rotary.h
@@ -0,0 +1,39 @@
+/*
+ * board initialization should put one of these structures into platform_data
+ * and place the bfin-rotary onto platform_bus named "bfin-rotary".
+ */
+#ifndef _BFIN_ROTARY_H
+#define _BFIN_ROTARY_H
+/* mode bitmasks */
+#define ROT_QUAD_ENC    CNTMODE_QUADENC /* quadrature/grey code encoder mode */
+#define ROT_BIN_ENC     CNTMODE_BINENC  /* binary encoder mode */
+#define ROT_UD_CNT      CNTMODE_UDCNT   /* rotary counter mode */
+#define ROT_DIR_CNT     CNTMODE_DIRCNT  /* direction counter mode */
+#define ROT_DEBE        DEBE            /* Debounce Enable */
+#define ROT_CDGINV      CDGINV          /* CDG Pin Polarity Invert */
+#define ROT_CUDINV      CUDINV          /* CUD Pin Polarity Invert */
+#define ROT_CZMINV      CZMINV          /* CZM Pin Polarity Invert */
+struct bfin_rotary_platform_data {
+        /* set rotary UP KEY_### or BTN_### in case you prefer
+         * bfin-rotary to send EV_KEY otherwise set 0
+         */
+        unsigned int rotary_up_key;
+        /* set rotary DOWN KEY_### or BTN_### in case you prefer
+         * bfin-rotary to send EV_KEY otherwise set 0
+         */
+        unsigned int rotary_down_key;
+        /* set rotary BUTTON KEY_### or BTN_### */
+        unsigned int rotary_button_key;
+        /* set rotary Relative Axis REL_### in case you prefer
+         * bfin-rotary to send EV_REL otherwise set 0
+         */
+        unsigned int rotary_rel_code;
+        unsigned short debounce;        /* 0..17 */
+        unsigned short mode;
+};
+#endif
diff --git a/arch/cris/include/asm/socket.h b/arch/cris/include/asm/socket.h
index d5cf74005408..45ec49bdb7b1 100644
--- a/arch/cris/include/asm/socket.h
+++ b/arch/cris/include/asm/socket.h
@@ -59,6 +59,9 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/cris/kernel/ptrace.c b/arch/cris/kernel/ptrace.c
index b326023baab2..48b0f3912632 100644
--- a/arch/cris/kernel/ptrace.c
+++ b/arch/cris/kernel/ptrace.c
@@ -16,6 +16,7 @@
 #include <linux/errno.h>
 #include <linux/ptrace.h>
 #include <linux/user.h>
+#include <linux/tracehook.h>
 #include <asm/uaccess.h>
 #include <asm/page.h>
@@ -36,4 +37,11 @@ void do_notify_resume(int canrestart, struct pt_regs *regs,
        /* deal with pending signal delivery */
        if (thread_info_flags & _TIF_SIGPENDING)
                do_signal(canrestart,regs);
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/frv/include/asm/socket.h b/arch/frv/include/asm/socket.h
index 57c3d4054e8b..2dea726095c2 100644
--- a/arch/frv/include/asm/socket.h
+++ b/arch/frv/include/asm/socket.h
@@ -57,5 +57,8 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/frv/kernel/signal.c b/arch/frv/kernel/signal.c
index 4a7a62c6e783..6b0a2b6fed6a 100644
--- a/arch/frv/kernel/signal.c
+++ b/arch/frv/kernel/signal.c
@@ -572,6 +572,8 @@ asmlinkage void do_notify_resume(__u32 thread_info_flags)
        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(__frame);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
 } /* end do_notify_resume() */
diff --git a/arch/h8300/include/asm/socket.h b/arch/h8300/include/asm/socket.h
index 602518a70a1a..1547f01c8e22 100644
--- a/arch/h8300/include/asm/socket.h
+++ b/arch/h8300/include/asm/socket.h
@@ -57,4 +57,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/h8300/include/asm/thread_info.h b/arch/h8300/include/asm/thread_info.h
index 8bbc8b0ee45d..70e67e47d020 100644
--- a/arch/h8300/include/asm/thread_info.h
+++ b/arch/h8300/include/asm/thread_info.h
@@ -89,6 +89,7 @@ static inline struct thread_info *current_thread_info(void)
                                           TIF_NEED_RESCHED */
 #define TIF_MEMDIE              4
 #define TIF_RESTORE_SIGMASK     5       /* restore signal mask in do_signal() */
+#define TIF_NOTIFY_RESUME       6       /* callback before returning to user */
 #define TIF_FREEZE              16      /* is freezing for suspend */
 /* as above, but as bit values */
@@ -97,6 +98,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_FREEZE             (1<<TIF_FREEZE)
 #define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
diff --git a/arch/h8300/kernel/signal.c b/arch/h8300/kernel/signal.c
index cf3472f7389b..af842c369d24 100644
--- a/arch/h8300/kernel/signal.c
+++ b/arch/h8300/kernel/signal.c
@@ -39,6 +39,7 @@
 #include <linux/tty.h>
 #include <linux/binfmts.h>
 #include <linux/freezer.h>
+#include <linux/tracehook.h>
 #include <asm/setup.h>
 #include <asm/uaccess.h>
@@ -552,4 +553,11 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags)
 {
        if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
                do_signal(regs, NULL);
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/ia64/hp/sim/simeth.c b/arch/ia64/hp/sim/simeth.c
index e4d8fde68103..7e81966ce481 100644
--- a/arch/ia64/hp/sim/simeth.c
+++ b/arch/ia64/hp/sim/simeth.c
@@ -412,7 +412,7 @@ simeth_tx(struct sk_buff *skb, struct net_device *dev)
         */
        dev_kfree_skb(skb);
-        return 0;
+        return NETDEV_TX_OK;
 }
 static inline struct sk_buff *
diff --git a/arch/ia64/include/asm/device.h b/arch/ia64/include/asm/device.h
index 41ab85d66f33..d66d446b127c 100644
--- a/arch/ia64/include/asm/device.h
+++ b/arch/ia64/include/asm/device.h
@@ -15,4 +15,7 @@ struct dev_archdata {
 #endif
 };
+struct pdev_archdata {
+};
 #endif /* _ASM_IA64_DEVICE_H */
diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
index 5a61b5c2e18f..8d3c79cd81e7 100644
--- a/arch/ia64/include/asm/dma-mapping.h
+++ b/arch/ia64/include/asm/dma-mapping.h
@@ -44,7 +44,6 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 #define get_dma_ops(dev) platform_dma_get_ops(dev)
-#define flush_write_buffers()
 #include <asm-generic/dma-mapping-common.h>
@@ -69,6 +68,24 @@ dma_set_mask (struct device *dev, u64 mask)
        return 0;
 }
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+        if (!dev->dma_mask)
+                return 0;
+        return addr + size <= *dev->dma_mask;
+}
+static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return paddr;
+}
+static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr;
+}
 extern int dma_get_cache_alignment(void);
 static inline void
diff --git a/arch/ia64/include/asm/kvm_host.h b/arch/ia64/include/asm/kvm_host.h
index 5f43697aed30..d9b6325a9328 100644
--- a/arch/ia64/include/asm/kvm_host.h
+++ b/arch/ia64/include/asm/kvm_host.h
@@ -235,7 +235,8 @@ struct kvm_vm_data {
 #define KVM_REQ_PTC_G           32
 #define KVM_REQ_RESUME          33
-#define KVM_PAGES_PER_HPAGE     1
+#define KVM_NR_PAGE_SIZES       1
+#define KVM_PAGES_PER_HPAGE(x)  1
 struct kvm;
 struct kvm_vcpu;
@@ -465,7 +466,6 @@ struct kvm_arch {
        unsigned long   metaphysical_rr4;
        unsigned long   vmm_init_rr;
-        int             online_vcpus;
        int             is_sn2;
        struct kvm_ioapic *vioapic;
diff --git a/arch/ia64/include/asm/kvm_para.h b/arch/ia64/include/asm/kvm_para.h
index 0d6d8ca07b8c..1588aee781a2 100644
--- a/arch/ia64/include/asm/kvm_para.h
+++ b/arch/ia64/include/asm/kvm_para.h
@@ -19,9 +19,13 @@
 *
 */
+#ifdef __KERNEL__
 static inline unsigned int kvm_arch_para_features(void)
 {
        return 0;
 }
 #endif
+#endif
diff --git a/arch/ia64/include/asm/socket.h b/arch/ia64/include/asm/socket.h
index 745421225ec6..0b0d5ff062e5 100644
--- a/arch/ia64/include/asm/socket.h
+++ b/arch/ia64/include/asm/socket.h
@@ -66,4 +66,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_IA64_SOCKET_H */
diff --git a/arch/ia64/kernel/head.S b/arch/ia64/kernel/head.S
index 23f846de62d5..e6c5c3d5e1f8 100644
--- a/arch/ia64/kernel/head.S
+++ b/arch/ia64/kernel/head.S
@@ -34,6 +34,7 @@
 #include <asm/mca_asm.h>
 #include <linux/init.h>
 #include <linux/linkage.h>
+#include "head.h"
 #ifdef CONFIG_HOTPLUG_CPU
 #define SAL_PSR_BITS_TO_SET                             \
diff --git a/arch/ia64/kernel/head.h b/arch/ia64/kernel/head.h
new file mode 100644
index 000000000000..2e2ac6824e65
--- /dev/null
+++ b/arch/ia64/kernel/head.h
@@ -0,0 +1 @@
+extern void console_print(const char *s);
diff --git a/arch/ia64/kernel/process.c b/arch/ia64/kernel/process.c
index 5d7c0e5b9e76..9bcec9945c12 100644
--- a/arch/ia64/kernel/process.c
+++ b/arch/ia64/kernel/process.c
@@ -161,6 +161,13 @@ show_regs (struct pt_regs *regs)
                show_stack(NULL, NULL);
 }
+/* local support for deprecated console_print */
+void
+console_print(const char *s)
+{
+        printk(KERN_EMERG "%s", s);
+}
 void
 do_notify_resume_user(sigset_t *unused, struct sigscratch *scr, long in_syscall)
 {
@@ -192,6 +199,8 @@ do_notify_resume_user(sigset_t *unused, struct sigscratch *scr, long in_syscall)
        if (test_thread_flag(TIF_NOTIFY_RESUME)) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(&scr->pt);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
        /* copy user rbs to kernel rbs */
diff --git a/arch/ia64/kvm/Kconfig b/arch/ia64/kvm/Kconfig
index 64d520937874..ef3e7be29caf 100644
--- a/arch/ia64/kvm/Kconfig
+++ b/arch/ia64/kvm/Kconfig
@@ -1,12 +1,8 @@
 #
 # KVM configuration
 #
-config HAVE_KVM
-        bool
-config HAVE_KVM_IRQCHIP
+source "virt/kvm/Kconfig"
-       bool
-       default y
 menuconfig VIRTUALIZATION
        bool "Virtualization"
@@ -28,6 +24,8 @@ config KVM
        depends on PCI
        select PREEMPT_NOTIFIERS
        select ANON_INODES
+        select HAVE_KVM_IRQCHIP
+        select KVM_APIC_ARCHITECTURE
        ---help---
          Support hosting fully virtualized guest machines using hardware
          virtualization extensions.  You will need a fairly recent
@@ -49,9 +47,6 @@ config KVM_INTEL
          Provides support for KVM on Itanium 2 processors equipped with the VT
          extensions.
-config KVM_TRACE
-       bool
 source drivers/virtio/Kconfig
 endif # VIRTUALIZATION
diff --git a/arch/ia64/kvm/kvm-ia64.c b/arch/ia64/kvm/kvm-ia64.c
index 80c57b0a21c4..0ad09f05efa9 100644
--- a/arch/ia64/kvm/kvm-ia64.c
+++ b/arch/ia64/kvm/kvm-ia64.c
@@ -210,16 +210,6 @@ int kvm_dev_ioctl_check_extension(long ext)
 }
-static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
-                                        gpa_t addr, int len, int is_write)
-{
-        struct kvm_io_device *dev;
-        dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len, is_write);
-        return dev;
-}
 static int handle_vm_error(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 {
        kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
@@ -231,6 +221,7 @@ static int handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 {
        struct kvm_mmio_req *p;
        struct kvm_io_device *mmio_dev;
+        int r;
        p = kvm_get_vcpu_ioreq(vcpu);
@@ -247,16 +238,13 @@ static int handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        kvm_run->exit_reason = KVM_EXIT_MMIO;
        return 0;
 mmio:
-        mmio_dev = vcpu_find_mmio_dev(vcpu, p->addr, p->size, !p->dir);
+        if (p->dir)
-        if (mmio_dev) {
+                r = kvm_io_bus_read(&vcpu->kvm->mmio_bus, p->addr,
-                if (!p->dir)
+                                    p->size, &p->data);
-                        kvm_iodevice_write(mmio_dev, p->addr, p->size,
+        else
-                                                &p->data);
+                r = kvm_io_bus_write(&vcpu->kvm->mmio_bus, p->addr,
-                else
+                                     p->size, &p->data);
-                        kvm_iodevice_read(mmio_dev, p->addr, p->size,
+        if (r)
-                                                &p->data);
-        } else
                printk(KERN_ERR"kvm: No iodevice found! addr:%lx\n", p->addr);
        p->state = STATE_IORESP_READY;
@@ -337,13 +325,12 @@ static struct kvm_vcpu *lid_to_vcpu(struct kvm *kvm, unsigned long id,
 {
        union ia64_lid lid;
        int i;
+        struct kvm_vcpu *vcpu;
-        for (i = 0; i < kvm->arch.online_vcpus; i++) {
+        kvm_for_each_vcpu(i, vcpu, kvm) {
-                if (kvm->vcpus[i]) {
+                lid.val = VCPU_LID(vcpu);
-                        lid.val = VCPU_LID(kvm->vcpus[i]);
+                if (lid.id == id && lid.eid == eid)
-                        if (lid.id == id && lid.eid == eid)
+                        return vcpu;
-                                return kvm->vcpus[i];
-                }
        }
        return NULL;
@@ -409,21 +396,21 @@ static int handle_global_purge(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        struct kvm *kvm = vcpu->kvm;
        struct call_data call_data;
        int i;
+        struct kvm_vcpu *vcpui;
        call_data.ptc_g_data = p->u.ptc_g_data;
-        for (i = 0; i < kvm->arch.online_vcpus; i++) {
+        kvm_for_each_vcpu(i, vcpui, kvm) {
-                if (!kvm->vcpus[i] || kvm->vcpus[i]->arch.mp_state ==
+                if (vcpui->arch.mp_state == KVM_MP_STATE_UNINITIALIZED ||
-                                                KVM_MP_STATE_UNINITIALIZED ||
+                                vcpu == vcpui)
-                                        vcpu == kvm->vcpus[i])
                        continue;
-                if (waitqueue_active(&kvm->vcpus[i]->wq))
+                if (waitqueue_active(&vcpui->wq))
-                        wake_up_interruptible(&kvm->vcpus[i]->wq);
+                        wake_up_interruptible(&vcpui->wq);
-                if (kvm->vcpus[i]->cpu != -1) {
+                if (vcpui->cpu != -1) {
-                        call_data.vcpu = kvm->vcpus[i];
+                        call_data.vcpu = vcpui;
-                        smp_call_function_single(kvm->vcpus[i]->cpu,
+                        smp_call_function_single(vcpui->cpu,
                                        vcpu_global_purge, &call_data, 1);
                } else
                        printk(KERN_WARNING"kvm: Uninit vcpu received ipi!\n");
@@ -852,8 +839,6 @@ struct  kvm *kvm_arch_create_vm(void)
        kvm_init_vm(kvm);
-        kvm->arch.online_vcpus = 0;
        return kvm;
 }
@@ -1000,10 +985,10 @@ long kvm_arch_vm_ioctl(struct file *filp,
                        goto out;
                if (irqchip_in_kernel(kvm)) {
                        __s32 status;
-                        mutex_lock(&kvm->lock);
+                        mutex_lock(&kvm->irq_lock);
                        status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
                                    irq_event.irq, irq_event.level);
-                        mutex_unlock(&kvm->lock);
+                        mutex_unlock(&kvm->irq_lock);
                        if (ioctl == KVM_IRQ_LINE_STATUS) {
                                irq_event.status = status;
                                if (copy_to_user(argp, &irq_event,
@@ -1216,7 +1201,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
        if (IS_ERR(vmm_vcpu))
                return PTR_ERR(vmm_vcpu);
-        if (vcpu->vcpu_id == 0) {
+        if (kvm_vcpu_is_bsp(vcpu)) {
                vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
                /*Set entry address for first run.*/
@@ -1224,7 +1209,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
                /*Initialize itc offset for vcpus*/
                itc_offset = 0UL - kvm_get_itc(vcpu);
-                for (i = 0; i < kvm->arch.online_vcpus; i++) {
+                for (i = 0; i < KVM_MAX_VCPUS; i++) {
                        v = (struct kvm_vcpu *)((char *)vcpu +
                                        sizeof(struct kvm_vcpu_data) * i);
                        v->arch.itc_offset = itc_offset;
@@ -1356,8 +1341,6 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
                goto fail;
        }
-        kvm->arch.online_vcpus++;
        return vcpu;
 fail:
        return ERR_PTR(r);
@@ -1952,19 +1935,6 @@ int kvm_highest_pending_irq(struct kvm_vcpu *vcpu)
    return find_highest_bits((int *)&vpd->irr[0]);
 }
-int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
-{
-        if (kvm_highest_pending_irq(vcpu) != -1)
-                return 1;
-        return 0;
-}
-int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
-{
-        /* do real check here */
-        return 1;
-}
 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
 {
        return vcpu->arch.timer_fired;
@@ -1977,7 +1947,8 @@ gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 {
-        return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE;
+        return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE) ||
+                (kvm_highest_pending_irq(vcpu) != -1);
 }
 int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
diff --git a/arch/ia64/kvm/vcpu.c b/arch/ia64/kvm/vcpu.c
index cc406d064a09..dce75b70cdd5 100644
--- a/arch/ia64/kvm/vcpu.c
+++ b/arch/ia64/kvm/vcpu.c
@@ -830,8 +830,8 @@ static void vcpu_set_itc(struct kvm_vcpu *vcpu, u64 val)
        kvm = (struct kvm *)KVM_VM_BASE;
-        if (vcpu->vcpu_id == 0) {
+        if (kvm_vcpu_is_bsp(vcpu)) {
-                for (i = 0; i < kvm->arch.online_vcpus; i++) {
+                for (i = 0; i < atomic_read(&kvm->online_vcpus); i++) {
                        v = (struct kvm_vcpu *)((char *)vcpu +
                                        sizeof(struct kvm_vcpu_data) * i);
                        VMX(v, itc_offset) = itc_offset;
diff --git a/arch/ia64/xen/time.c b/arch/ia64/xen/time.c
index fb8332690179..dbeadb9c8e20 100644
--- a/arch/ia64/xen/time.c
+++ b/arch/ia64/xen/time.c
@@ -133,8 +133,7 @@ consider_steal_time(unsigned long new_itm)
                account_idle_ticks(blocked);
                run_local_timers();
-                if (rcu_pending(cpu))
+                rcu_check_callbacks(cpu, user_mode(get_irq_regs()));
-                        rcu_check_callbacks(cpu, user_mode(get_irq_regs()));
                scheduler_tick();
                run_posix_cpu_timers(p);
diff --git a/arch/m32r/include/asm/socket.h b/arch/m32r/include/asm/socket.h
index be7ed589af5c..3390a864f224 100644
--- a/arch/m32r/include/asm/socket.h
+++ b/arch/m32r/include/asm/socket.h
@@ -57,4 +57,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_M32R_SOCKET_H */
diff --git a/arch/m32r/include/asm/thread_info.h b/arch/m32r/include/asm/thread_info.h
index 07bb5bd00e2a..71578151a403 100644
--- a/arch/m32r/include/asm/thread_info.h
+++ b/arch/m32r/include/asm/thread_info.h
@@ -149,6 +149,7 @@ static inline unsigned int get_thread_fault_code(void)
 #define TIF_NEED_RESCHED        2       /* rescheduling necessary */
 #define TIF_SINGLESTEP          3       /* restore singlestep on return to user mode */
 #define TIF_IRET                4       /* return with iret */
+#define TIF_NOTIFY_RESUME       5       /* callback before returning to user */
 #define TIF_RESTORE_SIGMASK     8       /* restore signal mask in do_signal() */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
 #define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
@@ -160,6 +161,7 @@ static inline unsigned int get_thread_fault_code(void)
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_SINGLESTEP         (1<<TIF_SINGLESTEP)
 #define _TIF_IRET               (1<<TIF_IRET)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_USEDFPU            (1<<TIF_USEDFPU)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
diff --git a/arch/m32r/kernel/signal.c b/arch/m32r/kernel/signal.c
index 18124542a6eb..144b0f124fc7 100644
--- a/arch/m32r/kernel/signal.c
+++ b/arch/m32r/kernel/signal.c
@@ -21,6 +21,7 @@
 #include <linux/stddef.h>
 #include <linux/personality.h>
 #include <linux/freezer.h>
+#include <linux/tracehook.h>
 #include <asm/cacheflush.h>
 #include <asm/ucontext.h>
 #include <asm/uaccess.h>
@@ -408,5 +409,12 @@ void do_notify_resume(struct pt_regs *regs, sigset_t *oldset,
        if (thread_info_flags & _TIF_SIGPENDING)
                do_signal(regs,oldset);
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
        clear_thread_flag(TIF_IRET);
 }
diff --git a/arch/m68k/include/asm/entry_mm.h b/arch/m68k/include/asm/entry_mm.h
index 5202f5a5b420..474125886218 100644
--- a/arch/m68k/include/asm/entry_mm.h
+++ b/arch/m68k/include/asm/entry_mm.h
@@ -46,7 +46,6 @@
 #define curptr a2
 LFLUSH_I_AND_D = 0x00000808
-LSIGTRAP = 5
 /* process bits for task_struct.ptrace */
 PT_TRACESYS_OFF = 3
@@ -118,9 +117,6 @@ PT_DTRACE_BIT = 2
 #define STR(X) STR1(X)
 #define STR1(X) #X
-#define PT_OFF_ORIG_D0   0x24
-#define PT_OFF_FORMATVEC 0x32
-#define PT_OFF_SR        0x2C
 #define SAVE_ALL_INT                            \
        "clrl   %%sp@-;"    /* stk_adj */       \
        "pea    -1:w;"      /* orig d0 = -1 */  \
diff --git a/arch/m68k/include/asm/entry_no.h b/arch/m68k/include/asm/entry_no.h
index c2553d26273d..907ed03d792f 100644
--- a/arch/m68k/include/asm/entry_no.h
+++ b/arch/m68k/include/asm/entry_no.h
@@ -72,8 +72,8 @@ LENOSYS = 38
        lea     %sp@(-32),%sp           /* space for 8 regs */
        moveml  %d1-%d5/%a0-%a2,%sp@
        movel   sw_usp,%a0              /* get usp */
-        movel   %a0@-,%sp@(PT_PC)       /* copy exception program counter */
+        movel   %a0@-,%sp@(PT_OFF_PC)   /* copy exception program counter */
-        movel   %a0@-,%sp@(PT_FORMATVEC)/* copy exception format/vector/sr */
+        movel   %a0@-,%sp@(PT_OFF_FORMATVEC)/*copy exception format/vector/sr */
        bra     7f
        6:
        clrl    %sp@-                   /* stkadj */
@@ -89,8 +89,8 @@ LENOSYS = 38
        bnes    8f                      /* no, skip */
        move    #0x2700,%sr             /* disable intrs */
        movel   sw_usp,%a0              /* get usp */
-        movel   %sp@(PT_PC),%a0@-       /* copy exception program counter */
+        movel   %sp@(PT_OFF_PC),%a0@-   /* copy exception program counter */
-        movel   %sp@(PT_FORMATVEC),%a0@-/* copy exception format/vector/sr */
+        movel   %sp@(PT_OFF_FORMATVEC),%a0@-/*copy exception format/vector/sr */
        moveml  %sp@,%d1-%d5/%a0-%a2
        lea     %sp@(32),%sp            /* space for 8 regs */
        movel   %sp@+,%d0
diff --git a/arch/m68k/include/asm/math-emu.h b/arch/m68k/include/asm/math-emu.h
index ddfab96403cb..5e9249b0014c 100644
--- a/arch/m68k/include/asm/math-emu.h
+++ b/arch/m68k/include/asm/math-emu.h
@@ -145,16 +145,16 @@ extern unsigned int fp_debugprint;
 * these are only used during instruction decoding
 * where we always know how deep we're on the stack.
 */
-#define FPS_DO          (PT_D0)
+#define FPS_DO          (PT_OFF_D0)
-#define FPS_D1          (PT_D1)
+#define FPS_D1          (PT_OFF_D1)
-#define FPS_D2          (PT_D2)
+#define FPS_D2          (PT_OFF_D2)
-#define FPS_A0          (PT_A0)
+#define FPS_A0          (PT_OFF_A0)
-#define FPS_A1          (PT_A1)
+#define FPS_A1          (PT_OFF_A1)
-#define FPS_A2          (PT_A2)
+#define FPS_A2          (PT_OFF_A2)
-#define FPS_SR          (PT_SR)
+#define FPS_SR          (PT_OFF_SR)
-#define FPS_PC          (PT_PC)
+#define FPS_PC          (PT_OFF_PC)
-#define FPS_EA          (PT_PC+6)
+#define FPS_EA          (PT_OFF_PC+6)
-#define FPS_PC2         (PT_PC+10)
+#define FPS_PC2         (PT_OFF_PC+10)
 .macro  fp_get_fp_reg
        lea     (FPD_FPREG,FPDATA,%d0.w*4),%a0
diff --git a/arch/m68k/include/asm/socket.h b/arch/m68k/include/asm/socket.h
index ca87f938b03f..eee01cce921b 100644
--- a/arch/m68k/include/asm/socket.h
+++ b/arch/m68k/include/asm/socket.h
@@ -57,4 +57,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/m68k/include/asm/thread_info_mm.h b/arch/m68k/include/asm/thread_info_mm.h
index 6ea5c33b3c56..b6da3882be9b 100644
--- a/arch/m68k/include/asm/thread_info_mm.h
+++ b/arch/m68k/include/asm/thread_info_mm.h
@@ -1,6 +1,10 @@
 #ifndef _ASM_M68K_THREAD_INFO_H
 #define _ASM_M68K_THREAD_INFO_H
+#ifndef ASM_OFFSETS_C
+#include <asm/asm-offsets.h>
+#endif
+#include <asm/current.h>
 #include <asm/types.h>
 #include <asm/page.h>
@@ -31,7 +35,12 @@ struct thread_info {
 #define init_thread_info        (init_task.thread.info)
 #define init_stack              (init_thread_union.stack)
-#define task_thread_info(tsk)   (&(tsk)->thread.info)
+#ifdef ASM_OFFSETS_C
+#define task_thread_info(tsk)   ((struct thread_info *) NULL)
+#else
+#define task_thread_info(tsk)   ((struct thread_info *)((char *)tsk+TASK_TINFO))
+#endif
 #define task_stack_page(tsk)    ((tsk)->stack)
 #define current_thread_info()   task_thread_info(current)
diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c
index b1f012f6c493..73e5e581245b 100644
--- a/arch/m68k/kernel/asm-offsets.c
+++ b/arch/m68k/kernel/asm-offsets.c
@@ -8,6 +8,8 @@
 * #defines from the assembly-language output.
 */
+#define ASM_OFFSETS_C
 #include <linux/stddef.h>
 #include <linux/sched.h>
 #include <linux/kernel_stat.h>
@@ -27,6 +29,9 @@ int main(void)
        DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
        DEFINE(TASK_MM, offsetof(struct task_struct, mm));
        DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
+#ifdef CONFIG_MMU
+        DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
+#endif
        /* offsets into the thread struct */
        DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
@@ -44,20 +49,20 @@ int main(void)
        DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags));
        /* offsets into the pt_regs */
-        DEFINE(PT_D0, offsetof(struct pt_regs, d0));
+        DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
-        DEFINE(PT_ORIG_D0, offsetof(struct pt_regs, orig_d0));
+        DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
-        DEFINE(PT_D1, offsetof(struct pt_regs, d1));
+        DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
-        DEFINE(PT_D2, offsetof(struct pt_regs, d2));
+        DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
-        DEFINE(PT_D3, offsetof(struct pt_regs, d3));
+        DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
-        DEFINE(PT_D4, offsetof(struct pt_regs, d4));
+        DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
-        DEFINE(PT_D5, offsetof(struct pt_regs, d5));
+        DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
-        DEFINE(PT_A0, offsetof(struct pt_regs, a0));
+        DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
-        DEFINE(PT_A1, offsetof(struct pt_regs, a1));
+        DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
-        DEFINE(PT_A2, offsetof(struct pt_regs, a2));
+        DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
-        DEFINE(PT_PC, offsetof(struct pt_regs, pc));
+        DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
-        DEFINE(PT_SR, offsetof(struct pt_regs, sr));
+        DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
        /* bitfields are a bit difficult */
-        DEFINE(PT_VECTOR, offsetof(struct pt_regs, pc) + 4);
+        DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
        /* offsets into the irq_handler struct */
        DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler));
@@ -84,10 +89,10 @@ int main(void)
        DEFINE(FONT_DESC_PREF, offsetof(struct font_desc, pref));
        /* signal defines */
-        DEFINE(SIGSEGV, SIGSEGV);
+        DEFINE(LSIGSEGV, SIGSEGV);
-        DEFINE(SEGV_MAPERR, SEGV_MAPERR);
+        DEFINE(LSEGV_MAPERR, SEGV_MAPERR);
-        DEFINE(SIGTRAP, SIGTRAP);
+        DEFINE(LSIGTRAP, SIGTRAP);
-        DEFINE(TRAP_TRACE, TRAP_TRACE);
+        DEFINE(LTRAP_TRACE, TRAP_TRACE);
        /* offsets into the custom struct */
        DEFINE(CUSTOMBASE, &amiga_custom);
diff --git a/arch/m68k/kernel/entry.S b/arch/m68k/kernel/entry.S
index c3735cd6207e..922f52e7ed1a 100644
--- a/arch/m68k/kernel/entry.S
+++ b/arch/m68k/kernel/entry.S
@@ -77,17 +77,17 @@ ENTRY(ret_from_fork)
        jra     .Lret_from_exception
 do_trace_entry:
-        movel   #-ENOSYS,%sp@(PT_D0)    | needed for strace
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)| needed for strace
        subql   #4,%sp
        SAVE_SWITCH_STACK
        jbsr    syscall_trace
        RESTORE_SWITCH_STACK
        addql   #4,%sp
-        movel   %sp@(PT_ORIG_D0),%d0
+        movel   %sp@(PT_OFF_ORIG_D0),%d0
        cmpl    #NR_syscalls,%d0
        jcs     syscall
 badsys:
-        movel   #-ENOSYS,%sp@(PT_D0)
+        movel   #-ENOSYS,%sp@(PT_OFF_D0)
        jra     ret_from_syscall
 do_trace_exit:
@@ -103,7 +103,7 @@ ENTRY(ret_from_signal)
        addql   #4,%sp
 /* on 68040 complete pending writebacks if any */
 #ifdef CONFIG_M68040
-        bfextu  %sp@(PT_VECTOR){#0,#4},%d0
+        bfextu  %sp@(PT_OFF_FORMATVEC){#0,#4},%d0
        subql   #7,%d0                          | bus error frame ?
        jbne    1f
        movel   %sp,%sp@-
@@ -127,7 +127,7 @@ ENTRY(system_call)
        jcc     badsys
 syscall:
        jbsr    @(sys_call_table,%d0:l:4)@(0)
-        movel   %d0,%sp@(PT_D0)         | save the return value
+        movel   %d0,%sp@(PT_OFF_D0)     | save the return value
 ret_from_syscall:
        |oriw   #0x0700,%sr
        movew   %curptr@(TASK_INFO+TINFO_FLAGS+2),%d0
@@ -135,7 +135,7 @@ ret_from_syscall:
 1:      RESTORE_ALL
 syscall_exit_work:
-        btst    #5,%sp@(PT_SR)          | check if returning to kernel
+        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
        bnes    1b                      | if so, skip resched, signals
        lslw    #1,%d0
        jcs     do_trace_exit
@@ -148,7 +148,7 @@ syscall_exit_work:
 ENTRY(ret_from_exception)
 .Lret_from_exception:
-        btst    #5,%sp@(PT_SR)          | check if returning to kernel
+        btst    #5,%sp@(PT_OFF_SR)      | check if returning to kernel
        bnes    1f                      | if so, skip resched, signals
        | only allow interrupts when we are really the last one on the
        | kernel stack, otherwise stack overflow can occur during
@@ -182,7 +182,7 @@ do_signal_return:
        jbra    resume_userspace
 do_delayed_trace:
-        bclr    #7,%sp@(PT_SR)          | clear trace bit in SR
+        bclr    #7,%sp@(PT_OFF_SR)      | clear trace bit in SR
        pea     1                       | send SIGTRAP
        movel   %curptr,%sp@-
        pea     LSIGTRAP
@@ -199,7 +199,7 @@ ENTRY(auto_inthandler)
        GET_CURRENT(%d0)
        addqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
                                        |  put exception # in d0
-        bfextu  %sp@(PT_VECTOR){#4,#10},%d0
+        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
        subw    #VEC_SPUR,%d0
        movel   %sp,%sp@-
@@ -216,7 +216,7 @@ ret_from_interrupt:
        ALIGN
 ret_from_last_interrupt:
        moveq   #(~ALLOWINT>>8)&0xff,%d0
-        andb    %sp@(PT_SR),%d0
+        andb    %sp@(PT_OFF_SR),%d0
        jne     2b
        /* check if we need to do software interrupts */
@@ -232,7 +232,7 @@ ENTRY(user_inthandler)
        GET_CURRENT(%d0)
        addqb   #1,%curptr@(TASK_INFO+TINFO_PREEMPT+1)
                                        |  put exception # in d0
-        bfextu  %sp@(PT_VECTOR){#4,#10},%d0
+        bfextu  %sp@(PT_OFF_FORMATVEC){#4,#10},%d0
 user_irqvec_fixup = . + 2
        subw    #VEC_USER,%d0
diff --git a/arch/m68k/math-emu/fp_entry.S b/arch/m68k/math-emu/fp_entry.S
index 954b4f304a7d..a3fe1f348dfe 100644
--- a/arch/m68k/math-emu/fp_entry.S
+++ b/arch/m68k/math-emu/fp_entry.S
@@ -85,8 +85,8 @@ fp_err_ua2:
 fp_err_ua1:
        addq.l  #4,%sp
        move.l  %a0,-(%sp)
-        pea     SEGV_MAPERR
+        pea     LSEGV_MAPERR
-        pea     SIGSEGV
+        pea     LSIGSEGV
        jsr     fpemu_signal
        add.w   #12,%sp
        jra     ret_from_exception
@@ -96,8 +96,8 @@ fp_err_ua1:
        | it does not really belong here, but...
 fp_sendtrace060:
        move.l  (FPS_PC,%sp),-(%sp)
-        pea     TRAP_TRACE
+        pea     LTRAP_TRACE
-        pea     SIGTRAP
+        pea     LSIGTRAP
        jsr     fpemu_signal
        add.w   #12,%sp
        jra     ret_from_exception
@@ -122,17 +122,17 @@ fp_get_data_reg:
        .long   fp_get_d6, fp_get_d7
 fp_get_d0:
-        move.l  (PT_D0+8,%sp),%d0
+        move.l  (PT_OFF_D0+8,%sp),%d0
        printf  PREGISTER,"{d0->%08x}",1,%d0
        rts
 fp_get_d1:
-        move.l  (PT_D1+8,%sp),%d0
+        move.l  (PT_OFF_D1+8,%sp),%d0
        printf  PREGISTER,"{d1->%08x}",1,%d0
        rts
 fp_get_d2:
-        move.l  (PT_D2+8,%sp),%d0
+        move.l  (PT_OFF_D2+8,%sp),%d0
        printf  PREGISTER,"{d2->%08x}",1,%d0
        rts
@@ -173,35 +173,35 @@ fp_put_data_reg:
 fp_put_d0:
        printf  PREGISTER,"{d0<-%08x}",1,%d0
-        move.l  %d0,(PT_D0+8,%sp)
+        move.l  %d0,(PT_OFF_D0+8,%sp)
        rts
 fp_put_d1:
        printf  PREGISTER,"{d1<-%08x}",1,%d0
-        move.l  %d0,(PT_D1+8,%sp)
+        move.l  %d0,(PT_OFF_D1+8,%sp)
        rts
 fp_put_d2:
        printf  PREGISTER,"{d2<-%08x}",1,%d0
-        move.l  %d0,(PT_D2+8,%sp)
+        move.l  %d0,(PT_OFF_D2+8,%sp)
        rts
 fp_put_d3:
        printf  PREGISTER,"{d3<-%08x}",1,%d0
 |       move.l  %d0,%d3
-        move.l  %d0,(PT_D3+8,%sp)
+        move.l  %d0,(PT_OFF_D3+8,%sp)
        rts
 fp_put_d4:
        printf  PREGISTER,"{d4<-%08x}",1,%d0
 |       move.l  %d0,%d4
-        move.l  %d0,(PT_D4+8,%sp)
+        move.l  %d0,(PT_OFF_D4+8,%sp)
        rts
 fp_put_d5:
        printf  PREGISTER,"{d5<-%08x}",1,%d0
 |       move.l  %d0,%d5
-        move.l  %d0,(PT_D5+8,%sp)
+        move.l  %d0,(PT_OFF_D5+8,%sp)
        rts
 fp_put_d6:
@@ -225,17 +225,17 @@ fp_get_addr_reg:
        .long   fp_get_a6, fp_get_a7
 fp_get_a0:
-        move.l  (PT_A0+8,%sp),%a0
+        move.l  (PT_OFF_A0+8,%sp),%a0
        printf  PREGISTER,"{a0->%08x}",1,%a0
        rts
 fp_get_a1:
-        move.l  (PT_A1+8,%sp),%a0
+        move.l  (PT_OFF_A1+8,%sp),%a0
        printf  PREGISTER,"{a1->%08x}",1,%a0
        rts
 fp_get_a2:
-        move.l  (PT_A2+8,%sp),%a0
+        move.l  (PT_OFF_A2+8,%sp),%a0
        printf  PREGISTER,"{a2->%08x}",1,%a0
        rts
@@ -276,17 +276,17 @@ fp_put_addr_reg:
 fp_put_a0:
        printf  PREGISTER,"{a0<-%08x}",1,%a0
-        move.l  %a0,(PT_A0+8,%sp)
+        move.l  %a0,(PT_OFF_A0+8,%sp)
        rts
 fp_put_a1:
        printf  PREGISTER,"{a1<-%08x}",1,%a0
-        move.l  %a0,(PT_A1+8,%sp)
+        move.l  %a0,(PT_OFF_A1+8,%sp)
        rts
 fp_put_a2:
        printf  PREGISTER,"{a2<-%08x}",1,%a0
-        move.l  %a0,(PT_A2+8,%sp)
+        move.l  %a0,(PT_OFF_A2+8,%sp)
        rts
 fp_put_a3:
diff --git a/arch/microblaze/include/asm/device.h b/arch/microblaze/include/asm/device.h
index c042830793ed..30286db27c1c 100644
--- a/arch/microblaze/include/asm/device.h
+++ b/arch/microblaze/include/asm/device.h
@@ -16,6 +16,9 @@ struct dev_archdata {
        struct device_node      *of_node;
 };
+struct pdev_archdata {
+};
 #endif /* _ASM_MICROBLAZE_DEVICE_H */
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index 2ecab6155932..cf50fa29b198 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -32,6 +32,8 @@
 #include <linux/leds.h>
 #include <linux/string.h>
 #include <linux/etherdevice.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
 #include <asm/addrspace.h>
 #include <asm/mach-ar7/ar7.h>
@@ -208,6 +210,12 @@ static struct physmap_flash_data physmap_flash_data = {
        .width = 2,
 };
+static struct fixed_phy_status fixed_phy_status __initdata = {
+        .link = 1,
+        .speed = 100,
+        .duplex = 1,
+};
 static struct plat_cpmac_data cpmac_low_data = {
        .reset_bit = 17,
        .power_bit = 20,
@@ -530,6 +538,9 @@ static int __init ar7_register_devices(void)
        }
        if (ar7_has_high_cpmac()) {
+                res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status);
+                if (res && res != -ENODEV)
+                        return res;
                cpmac_get_mac(1, cpmac_high_data.dev_addr);
                res = platform_device_register(&cpmac_high);
                if (res)
@@ -538,6 +549,10 @@ static int __init ar7_register_devices(void)
                cpmac_low_data.phy_mask = 0xffffffff;
        }
+        res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status);
+        if (res && res != -ENODEV)
+                return res;
        cpmac_get_mac(0, cpmac_low_data.dev_addr);
        res = platform_device_register(&cpmac_low);
        if (res)
diff --git a/arch/mips/include/asm/socket.h b/arch/mips/include/asm/socket.h
index 2abca1780169..ae05accd9fe4 100644
--- a/arch/mips/include/asm/socket.h
+++ b/arch/mips/include/asm/socket.h
@@ -42,6 +42,8 @@ To add: #define SO_REUSEPORT 0x0200	/* Allow local address and port reuse.  */
 #define SO_SNDTIMEO     0x1005  /* send timeout */
 #define SO_RCVTIMEO     0x1006  /* receive timeout */
 #define SO_ACCEPTCONN   0x1009
+#define SO_PROTOCOL     0x1028  /* protocol type */
+#define SO_DOMAIN       0x1029  /* domain/socket family */
 /* linux-specific, might as well be the same as on i386 */
 #define SO_NO_CHECK     11
diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h
index f9df720d2e40..01cc1630b66c 100644
--- a/arch/mips/include/asm/thread_info.h
+++ b/arch/mips/include/asm/thread_info.h
@@ -115,6 +115,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_NEED_RESCHED        2       /* rescheduling necessary */
 #define TIF_SYSCALL_AUDIT       3       /* syscall auditing active */
 #define TIF_SECCOMP             4       /* secure computing */
+#define TIF_NOTIFY_RESUME       5       /* callback before returning to user */
 #define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal() */
 #define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
 #define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
@@ -139,6 +140,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
 #define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
 #define _TIF_SECCOMP            (1<<TIF_SECCOMP)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
 #define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
 #define _TIF_USEDFPU            (1<<TIF_USEDFPU)
 #define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
diff --git a/arch/mips/kernel/scall64-n32.S b/arch/mips/kernel/scall64-n32.S
index e855b118a079..1a6ae124635b 100644
--- a/arch/mips/kernel/scall64-n32.S
+++ b/arch/mips/kernel/scall64-n32.S
@@ -164,7 +164,7 @@ EXPORT(sysn32_call_table)
        PTR     sys_connect
        PTR     sys_accept
        PTR     sys_sendto
-        PTR     sys_recvfrom
+        PTR     compat_sys_recvfrom
        PTR     compat_sys_sendmsg              /* 6045 */
        PTR     compat_sys_recvmsg
        PTR     sys_shutdown
diff --git a/arch/mips/kernel/scall64-o32.S b/arch/mips/kernel/scall64-o32.S
index 0c49f1a660be..cd31087a651f 100644
--- a/arch/mips/kernel/scall64-o32.S
+++ b/arch/mips/kernel/scall64-o32.S
@@ -378,8 +378,8 @@ sys_call_table:
        PTR     sys_getsockname
        PTR     sys_getsockopt
        PTR     sys_listen
-        PTR     sys_recv                        /* 4175 */
+        PTR     compat_sys_recv                 /* 4175 */
-        PTR     sys_recvfrom
+        PTR     compat_sys_recvfrom
        PTR     compat_sys_recvmsg
        PTR     sys_send
        PTR     compat_sys_sendmsg
diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c
index 830c5ef9932b..6254041b942f 100644
--- a/arch/mips/kernel/signal.c
+++ b/arch/mips/kernel/signal.c
@@ -21,6 +21,7 @@
 #include <linux/compiler.h>
 #include <linux/syscalls.h>
 #include <linux/uaccess.h>
+#include <linux/tracehook.h>
 #include <asm/abi.h>
 #include <asm/asm.h>
@@ -700,4 +701,11 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, void *unused,
        /* deal with pending signal delivery */
        if (thread_info_flags & (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK))
                do_signal(regs);
+        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/mn10300/include/asm/socket.h b/arch/mn10300/include/asm/socket.h
index fb5daf438ec9..4df75af29d76 100644
--- a/arch/mn10300/include/asm/socket.h
+++ b/arch/mn10300/include/asm/socket.h
@@ -57,4 +57,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/mn10300/kernel/signal.c b/arch/mn10300/kernel/signal.c
index feb2f2e810db..a21f43bc68e2 100644
--- a/arch/mn10300/kernel/signal.c
+++ b/arch/mn10300/kernel/signal.c
@@ -568,5 +568,7 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, u32 thread_info_flags)
        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(__frame);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
 }
diff --git a/arch/parisc/include/asm/socket.h b/arch/parisc/include/asm/socket.h
index 885472bf7b78..960b1e5d8e16 100644
--- a/arch/parisc/include/asm/socket.h
+++ b/arch/parisc/include/asm/socket.h
@@ -24,6 +24,8 @@
 #define SO_RCVTIMEO     0x1006
 #define SO_ERROR        0x1007
 #define SO_TYPE         0x1008
+#define SO_PROTOCOL     0x1028
+#define SO_DOMAIN       0x1029
 #define SO_PEERNAME     0x2000
 #define SO_NO_CHECK     0x400b
diff --git a/arch/parisc/include/asm/thread_info.h b/arch/parisc/include/asm/thread_info.h
index 4ce0edfbe969..ac775a76bff7 100644
--- a/arch/parisc/include/asm/thread_info.h
+++ b/arch/parisc/include/asm/thread_info.h
@@ -59,6 +59,7 @@ struct thread_info {
 #define TIF_MEMDIE              5
 #define TIF_RESTORE_SIGMASK     6       /* restore saved signal mask */
 #define TIF_FREEZE              7       /* is freezing for suspend */
+#define TIF_NOTIFY_RESUME       8       /* callback before returning to user */
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
@@ -67,8 +68,9 @@ struct thread_info {
 #define _TIF_32BIT              (1 << TIF_32BIT)
 #define _TIF_RESTORE_SIGMASK    (1 << TIF_RESTORE_SIGMASK)
 #define _TIF_FREEZE             (1 << TIF_FREEZE)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
-#define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | \
+#define _TIF_USER_WORK_MASK     (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | \
                                 _TIF_NEED_RESCHED | _TIF_RESTORE_SIGMASK)
 #endif /* __KERNEL__ */
diff --git a/arch/parisc/kernel/entry.S b/arch/parisc/kernel/entry.S
index e552e547cb93..8c4712b74dc1 100644
--- a/arch/parisc/kernel/entry.S
+++ b/arch/parisc/kernel/entry.S
@@ -948,7 +948,7 @@ intr_check_sig:
        /* As above */
        mfctl   %cr30,%r1
        LDREG   TI_FLAGS(%r1),%r19
-        ldi     (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK), %r20
+        ldi     (_TIF_SIGPENDING|_TIF_RESTORE_SIGMASK|_TIF_NOTIFY_RESUME), %r20
        and,COND(<>)    %r19, %r20, %r0
        b,n     intr_restore    /* skip past if we've nothing to do */
diff --git a/arch/parisc/kernel/signal.c b/arch/parisc/kernel/signal.c
index f82544225e8e..8eb3c63c407a 100644
--- a/arch/parisc/kernel/signal.c
+++ b/arch/parisc/kernel/signal.c
@@ -25,6 +25,7 @@
 #include <linux/stddef.h>
 #include <linux/compat.h>
 #include <linux/elf.h>
+#include <linux/tracehook.h>
 #include <asm/ucontext.h>
 #include <asm/rt_sigframe.h>
 #include <asm/uaccess.h>
@@ -645,4 +646,11 @@ void do_notify_resume(struct pt_regs *regs, long in_syscall)
        if (test_thread_flag(TIF_SIGPENDING) ||
            test_thread_flag(TIF_RESTORE_SIGMASK))
                do_signal(regs, in_syscall);
+        if (test_thread_flag(TIF_NOTIFY_RESUME)) {
+                clear_thread_flag(TIF_NOTIFY_RESUME);
+                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
+        }
 }
diff --git a/arch/powerpc/include/asm/device.h b/arch/powerpc/include/asm/device.h
index 7d2277cef09a..e3e06e0f7fc0 100644
--- a/arch/powerpc/include/asm/device.h
+++ b/arch/powerpc/include/asm/device.h
@@ -30,4 +30,7 @@ dev_archdata_get_node(const struct dev_archdata *ad)
        return ad->of_node;
 }
+struct pdev_archdata {
+};
 #endif /* _ASM_POWERPC_DEVICE_H */
diff --git a/arch/powerpc/include/asm/dma-mapping.h b/arch/powerpc/include/asm/dma-mapping.h
index b44aaabdd1a6..0c34371ec49c 100644
--- a/arch/powerpc/include/asm/dma-mapping.h
+++ b/arch/powerpc/include/asm/dma-mapping.h
@@ -424,6 +424,29 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 #endif
 }
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+        struct dma_mapping_ops *ops = get_dma_ops(dev);
+        if (ops->addr_needs_map && ops->addr_needs_map(dev, addr, size))
+                return 0;
+        if (!dev->dma_mask)
+                return 0;
+        return addr + size <= *dev->dma_mask;
+}
+static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return paddr + get_dma_direct_offset(dev);
+}
+static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr - get_dma_direct_offset(dev);
+}
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 #ifdef CONFIG_NOT_COHERENT_CACHE
diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h
index fddc3ed715fa..c9c930ed11d7 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -34,7 +34,8 @@
 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
 /* We don't currently support large pages. */
-#define KVM_PAGES_PER_HPAGE (1UL << 31)
+#define KVM_NR_PAGE_SIZES       1
+#define KVM_PAGES_PER_HPAGE(x)  (1UL<<31)
 struct kvm;
 struct kvm_run;
@@ -153,7 +154,6 @@ struct kvm_vcpu_arch {
        u32 pid;
        u32 swap_pid;
-        u32 pvr;
        u32 ccr0;
        u32 ccr1;
        u32 dbcr0;
diff --git a/arch/powerpc/include/asm/pgtable.h b/arch/powerpc/include/asm/pgtable.h
index eb17da781128..2a5da069714e 100644
--- a/arch/powerpc/include/asm/pgtable.h
+++ b/arch/powerpc/include/asm/pgtable.h
@@ -104,8 +104,8 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
        else
                pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte));
-#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT) && defined(CONFIG_SMP)
+#elif defined(CONFIG_PPC32) && defined(CONFIG_PTE_64BIT)
-        /* Second case is 32-bit with 64-bit PTE in SMP mode. In this case, we
+        /* Second case is 32-bit with 64-bit PTE.  In this case, we
         * can just store as long as we do the two halves in the right order
         * with a barrier in between. This is possible because we take care,
         * in the hash code, to pre-invalidate if the PTE was already hashed,
@@ -140,7 +140,7 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
 #else
        /* Anything else just stores the PTE normally. That covers all 64-bit
-         * cases, and 32-bit non-hash with 64-bit PTEs in UP mode
+         * cases, and 32-bit non-hash with 32-bit PTEs.
         */
        *ptep = pte;
 #endif
diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index 157c5ca581c8..f388f0ab193f 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -154,6 +154,7 @@ int qe_get_snum(void);
 void qe_put_snum(u8 snum);
 unsigned int qe_get_num_of_risc(void);
 unsigned int qe_get_num_of_snums(void);
+int qe_alive_during_sleep(void);
 /* we actually use cpm_muram implementation, define this for convenience */
 #define qe_muram_init cpm_muram_init
diff --git a/arch/powerpc/include/asm/socket.h b/arch/powerpc/include/asm/socket.h
index 1e5cfad0e3f7..3ab8b3e6feb0 100644
--- a/arch/powerpc/include/asm/socket.h
+++ b/arch/powerpc/include/asm/socket.h
@@ -64,4 +64,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif  /* _ASM_POWERPC_SOCKET_H */
diff --git a/arch/powerpc/include/asm/spinlock.h b/arch/powerpc/include/asm/spinlock.h
index c3b193121f81..198266cf9e2d 100644
--- a/arch/powerpc/include/asm/spinlock.h
+++ b/arch/powerpc/include/asm/spinlock.h
@@ -54,7 +54,7 @@
 * This returns the old value in the lock, so we succeeded
 * in getting the lock if the return value is 0.
 */
-static inline unsigned long __spin_trylock(raw_spinlock_t *lock)
+static inline unsigned long arch_spin_trylock(raw_spinlock_t *lock)
 {
        unsigned long tmp, token;
@@ -76,7 +76,7 @@ static inline unsigned long __spin_trylock(raw_spinlock_t *lock)
 static inline int __raw_spin_trylock(raw_spinlock_t *lock)
 {
        CLEAR_IO_SYNC;
-        return __spin_trylock(lock) == 0;
+        return arch_spin_trylock(lock) == 0;
 }
 /*
@@ -108,7 +108,7 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
 {
        CLEAR_IO_SYNC;
        while (1) {
-                if (likely(__spin_trylock(lock) == 0))
+                if (likely(arch_spin_trylock(lock) == 0))
                        break;
                do {
                        HMT_low();
@@ -126,7 +126,7 @@ void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long flags)
        CLEAR_IO_SYNC;
        while (1) {
-                if (likely(__spin_trylock(lock) == 0))
+                if (likely(arch_spin_trylock(lock) == 0))
                        break;
                local_save_flags(flags_dis);
                local_irq_restore(flags);
@@ -181,7 +181,7 @@ extern void __raw_spin_unlock_wait(raw_spinlock_t *lock);
 * This returns the old value in the lock + 1,
 * so we got a read lock if the return value is > 0.
 */
-static inline long __read_trylock(raw_rwlock_t *rw)
+static inline long arch_read_trylock(raw_rwlock_t *rw)
 {
        long tmp;
@@ -205,7 +205,7 @@ static inline long __read_trylock(raw_rwlock_t *rw)
 * This returns the old value in the lock,
 * so we got the write lock if the return value is 0.
 */
-static inline long __write_trylock(raw_rwlock_t *rw)
+static inline long arch_write_trylock(raw_rwlock_t *rw)
 {
        long tmp, token;
@@ -228,7 +228,7 @@ static inline long __write_trylock(raw_rwlock_t *rw)
 static inline void __raw_read_lock(raw_rwlock_t *rw)
 {
        while (1) {
-                if (likely(__read_trylock(rw) > 0))
+                if (likely(arch_read_trylock(rw) > 0))
                        break;
                do {
                        HMT_low();
@@ -242,7 +242,7 @@ static inline void __raw_read_lock(raw_rwlock_t *rw)
 static inline void __raw_write_lock(raw_rwlock_t *rw)
 {
        while (1) {
-                if (likely(__write_trylock(rw) == 0))
+                if (likely(arch_write_trylock(rw) == 0))
                        break;
                do {
                        HMT_low();
@@ -255,12 +255,12 @@ static inline void __raw_write_lock(raw_rwlock_t *rw)
 static inline int __raw_read_trylock(raw_rwlock_t *rw)
 {
-        return __read_trylock(rw) > 0;
+        return arch_read_trylock(rw) > 0;
 }
 static inline int __raw_write_trylock(raw_rwlock_t *rw)
 {
-        return __write_trylock(rw) == 0;
+        return arch_write_trylock(rw) == 0;
 }
 static inline void __raw_read_unlock(raw_rwlock_t *rw)
diff --git a/arch/powerpc/kernel/Makefile b/arch/powerpc/kernel/Makefile
index b73396b93905..9619285f64e8 100644
--- a/arch/powerpc/kernel/Makefile
+++ b/arch/powerpc/kernel/Makefile
@@ -97,7 +97,7 @@ obj64-$(CONFIG_AUDIT)		+= compat_audit.o
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER)     += ftrace.o
-obj-$(CONFIG_PPC_PERF_CTRS)     += perf_counter.o
+obj-$(CONFIG_PPC_PERF_CTRS)     += perf_counter.o perf_callchain.o
 obj64-$(CONFIG_PPC_PERF_CTRS)   += power4-pmu.o ppc970-pmu.o power5-pmu.o \
                                   power5+-pmu.o power6-pmu.o power7-pmu.o
 obj32-$(CONFIG_PPC_PERF_CTRS)   += mpc7450-pmu.o
diff --git a/arch/powerpc/kernel/asm-offsets.c b/arch/powerpc/kernel/asm-offsets.c
index 561b64652311..197b15646eeb 100644
--- a/arch/powerpc/kernel/asm-offsets.c
+++ b/arch/powerpc/kernel/asm-offsets.c
@@ -67,6 +67,8 @@ int main(void)
        DEFINE(MMCONTEXTID, offsetof(struct mm_struct, context.id));
 #ifdef CONFIG_PPC64
        DEFINE(AUDITCONTEXT, offsetof(struct task_struct, audit_context));
+        DEFINE(SIGSEGV, SIGSEGV);
+        DEFINE(NMI_MASK, NMI_MASK);
 #else
        DEFINE(THREAD_INFO, offsetof(struct task_struct, stack));
 #endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/kernel/dma-swiotlb.c b/arch/powerpc/kernel/dma-swiotlb.c
index 68ccf11e4f19..e8a57de85bcf 100644
--- a/arch/powerpc/kernel/dma-swiotlb.c
+++ b/arch/powerpc/kernel/dma-swiotlb.c
@@ -24,50 +24,12 @@
 int swiotlb __read_mostly;
 unsigned int ppc_swiotlb_enable;
-void *swiotlb_bus_to_virt(struct device *hwdev, dma_addr_t addr)
-{
-        unsigned long pfn = PFN_DOWN(swiotlb_bus_to_phys(hwdev, addr));
-        void *pageaddr = page_address(pfn_to_page(pfn));
-        if (pageaddr != NULL)
-                return pageaddr + (addr % PAGE_SIZE);
-        return NULL;
-}
-dma_addr_t swiotlb_phys_to_bus(struct device *hwdev, phys_addr_t paddr)
-{
-        return paddr + get_dma_direct_offset(hwdev);
-}
-phys_addr_t swiotlb_bus_to_phys(struct device *hwdev, dma_addr_t baddr)
-{
-        return baddr - get_dma_direct_offset(hwdev);
-}
-/*
- * Determine if an address needs bounce buffering via swiotlb.
- * Going forward I expect the swiotlb code to generalize on using
- * a dma_ops->addr_needs_map, and this function will move from here to the
- * generic swiotlb code.
- */
-int
-swiotlb_arch_address_needs_mapping(struct device *hwdev, dma_addr_t addr,
-                                   size_t size)
-{
-        struct dma_mapping_ops *dma_ops = get_dma_ops(hwdev);
-        BUG_ON(!dma_ops);
-        return dma_ops->addr_needs_map(hwdev, addr, size);
-}
 /*
 * Determine if an address is reachable by a pci device, or if we must bounce.
 */
 static int
 swiotlb_pci_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size)
 {
-        u64 mask = dma_get_mask(hwdev);
        dma_addr_t max;
        struct pci_controller *hose;
        struct pci_dev *pdev = to_pci_dev(hwdev);
@@ -79,16 +41,9 @@ swiotlb_pci_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size)
        if ((addr + size > max) | (addr < hose->dma_window_base_cur))
                return 1;
-        return !is_buffer_dma_capable(mask, addr, size);
+        return 0;
-}
-static int
-swiotlb_addr_needs_map(struct device *hwdev, dma_addr_t addr, size_t size)
-{
-        return !is_buffer_dma_capable(dma_get_mask(hwdev), addr, size);
 }
 /*
 * At the moment, all platforms that use this code only require
 * swiotlb to be used if we're operating on HIGHMEM.  Since
@@ -104,7 +59,6 @@ struct dma_mapping_ops swiotlb_dma_ops = {
        .dma_supported = swiotlb_dma_supported,
        .map_page = swiotlb_map_page,
        .unmap_page = swiotlb_unmap_page,
-        .addr_needs_map = swiotlb_addr_needs_map,
        .sync_single_range_for_cpu = swiotlb_sync_single_range_for_cpu,
        .sync_single_range_for_device = swiotlb_sync_single_range_for_device,
        .sync_sg_for_cpu = swiotlb_sync_sg_for_cpu,
diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index eb898112e577..8ac85e08ffae 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -729,6 +729,11 @@ BEGIN_FTR_SECTION
        bne-    do_ste_alloc            /* If so handle it */
 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
+        clrrdi  r11,r1,THREAD_SHIFT
+        lwz     r0,TI_PREEMPT(r11)      /* If we're in an "NMI" */
+        andis.  r0,r0,NMI_MASK@h        /* (i.e. an irq when soft-disabled) */
+        bne     77f                     /* then don't call hash_page now */
        /*
         * On iSeries, we soft-disable interrupts here, then
         * hard-enable interrupts so that the hash_page code can spin on
@@ -833,6 +838,20 @@ handle_page_fault:
        bl      .low_hash_fault
        b       .ret_from_except
+/*
+ * We come here as a result of a DSI at a point where we don't want
+ * to call hash_page, such as when we are accessing memory (possibly
+ * user memory) inside a PMU interrupt that occurred while interrupts
+ * were soft-disabled.  We want to invoke the exception handler for
+ * the access, or panic if there isn't a handler.
+ */
+77:     bl      .save_nvgprs
+        mr      r4,r3
+        addi    r3,r1,STACK_FRAME_OVERHEAD
+        li      r5,SIGSEGV
+        bl      .bad_page_fault
+        b       .ret_from_except
        /* here we have a segment miss */
 do_ste_alloc:
        bl      .ste_allocate           /* try to insert stab entry */
diff --git a/arch/powerpc/kernel/perf_callchain.c b/arch/powerpc/kernel/perf_callchain.c
new file mode 100644
index 000000000000..f74b62c67511
--- /dev/null
+++ b/arch/powerpc/kernel/perf_callchain.c
@@ -0,0 +1,527 @@
+/*
+ * Performance counter callchain support - powerpc architecture code
+ *
+ * Copyright © 2009 Paul Mackerras, IBM Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/perf_counter.h>
+#include <linux/percpu.h>
+#include <linux/uaccess.h>
+#include <linux/mm.h>
+#include <asm/ptrace.h>
+#include <asm/pgtable.h>
+#include <asm/sigcontext.h>
+#include <asm/ucontext.h>
+#include <asm/vdso.h>
+#ifdef CONFIG_PPC64
+#include "ppc32.h"
+#endif
+/*
+ * Store another value in a callchain_entry.
+ */
+static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip)
+{
+        unsigned int nr = entry->nr;
+        if (nr < PERF_MAX_STACK_DEPTH) {
+                entry->ip[nr] = ip;
+                entry->nr = nr + 1;
+        }
+}
+/*
+ * Is sp valid as the address of the next kernel stack frame after prev_sp?
+ * The next frame may be in a different stack area but should not go
+ * back down in the same stack area.
+ */
+static int valid_next_sp(unsigned long sp, unsigned long prev_sp)
+{
+        if (sp & 0xf)
+                return 0;               /* must be 16-byte aligned */
+        if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD))
+                return 0;
+        if (sp >= prev_sp + STACK_FRAME_OVERHEAD)
+                return 1;
+        /*
+         * sp could decrease when we jump off an interrupt stack
+         * back to the regular process stack.
+         */
+        if ((sp & ~(THREAD_SIZE - 1)) != (prev_sp & ~(THREAD_SIZE - 1)))
+                return 1;
+        return 0;
+}
+static void perf_callchain_kernel(struct pt_regs *regs,
+                                  struct perf_callchain_entry *entry)
+{
+        unsigned long sp, next_sp;
+        unsigned long next_ip;
+        unsigned long lr;
+        long level = 0;
+        unsigned long *fp;
+        lr = regs->link;
+        sp = regs->gpr[1];
+        callchain_store(entry, PERF_CONTEXT_KERNEL);
+        callchain_store(entry, regs->nip);
+        if (!validate_sp(sp, current, STACK_FRAME_OVERHEAD))
+                return;
+        for (;;) {
+                fp = (unsigned long *) sp;
+                next_sp = fp[0];
+                if (next_sp == sp + STACK_INT_FRAME_SIZE &&
+                    fp[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
+                        /*
+                         * This looks like an interrupt frame for an
+                         * interrupt that occurred in the kernel
+                         */
+                        regs = (struct pt_regs *)(sp + STACK_FRAME_OVERHEAD);
+                        next_ip = regs->nip;
+                        lr = regs->link;
+                        level = 0;
+                        callchain_store(entry, PERF_CONTEXT_KERNEL);
+                } else {
+                        if (level == 0)
+                                next_ip = lr;
+                        else
+                                next_ip = fp[STACK_FRAME_LR_SAVE];
+                        /*
+                         * We can't tell which of the first two addresses
+                         * we get are valid, but we can filter out the
+                         * obviously bogus ones here.  We replace them
+                         * with 0 rather than removing them entirely so
+                         * that userspace can tell which is which.
+                         */
+                        if ((level == 1 && next_ip == lr) ||
+                            (level <= 1 && !kernel_text_address(next_ip)))
+                                next_ip = 0;
+                        ++level;
+                }
+                callchain_store(entry, next_ip);
+                if (!valid_next_sp(next_sp, sp))
+                        return;
+                sp = next_sp;
+        }
+}
+#ifdef CONFIG_PPC64
+#ifdef CONFIG_HUGETLB_PAGE
+#define is_huge_psize(pagesize) (HPAGE_SHIFT && mmu_huge_psizes[pagesize])
+#else
+#define is_huge_psize(pagesize) 0
+#endif
+/*
+ * On 64-bit we don't want to invoke hash_page on user addresses from
+ * interrupt context, so if the access faults, we read the page tables
+ * to find which page (if any) is mapped and access it directly.
+ */
+static int read_user_stack_slow(void __user *ptr, void *ret, int nb)
+{
+        pgd_t *pgdir;
+        pte_t *ptep, pte;
+        int pagesize;
+        unsigned long addr = (unsigned long) ptr;
+        unsigned long offset;
+        unsigned long pfn;
+        void *kaddr;
+        pgdir = current->mm->pgd;
+        if (!pgdir)
+                return -EFAULT;
+        pagesize = get_slice_psize(current->mm, addr);
+        /* align address to page boundary */
+        offset = addr & ((1ul << mmu_psize_defs[pagesize].shift) - 1);
+        addr -= offset;
+        if (is_huge_psize(pagesize))
+                ptep = huge_pte_offset(current->mm, addr);
+        else
+                ptep = find_linux_pte(pgdir, addr);
+        if (ptep == NULL)
+                return -EFAULT;
+        pte = *ptep;
+        if (!pte_present(pte) || !(pte_val(pte) & _PAGE_USER))
+                return -EFAULT;
+        pfn = pte_pfn(pte);
+        if (!page_is_ram(pfn))
+                return -EFAULT;
+        /* no highmem to worry about here */
+        kaddr = pfn_to_kaddr(pfn);
+        memcpy(ret, kaddr + offset, nb);
+        return 0;
+}
+static int read_user_stack_64(unsigned long __user *ptr, unsigned long *ret)
+{
+        if ((unsigned long)ptr > TASK_SIZE - sizeof(unsigned long) ||
+            ((unsigned long)ptr & 7))
+                return -EFAULT;
+        if (!__get_user_inatomic(*ret, ptr))
+                return 0;
+        return read_user_stack_slow(ptr, ret, 8);
+}
+static int read_user_stack_32(unsigned int __user *ptr, unsigned int *ret)
+{
+        if ((unsigned long)ptr > TASK_SIZE - sizeof(unsigned int) ||
+            ((unsigned long)ptr & 3))
+                return -EFAULT;
+        if (!__get_user_inatomic(*ret, ptr))
+                return 0;
+        return read_user_stack_slow(ptr, ret, 4);
+}
+static inline int valid_user_sp(unsigned long sp, int is_64)
+{
+        if (!sp || (sp & 7) || sp > (is_64 ? TASK_SIZE : 0x100000000UL) - 32)
+                return 0;
+        return 1;
+}
+/*
+ * 64-bit user processes use the same stack frame for RT and non-RT signals.
+ */
+struct signal_frame_64 {
+        char            dummy[__SIGNAL_FRAMESIZE];
+        struct ucontext uc;
+        unsigned long   unused[2];
+        unsigned int    tramp[6];
+        struct siginfo  *pinfo;
+        void            *puc;
+        struct siginfo  info;
+        char            abigap[288];
+};
+static int is_sigreturn_64_address(unsigned long nip, unsigned long fp)
+{
+        if (nip == fp + offsetof(struct signal_frame_64, tramp))
+                return 1;
+        if (vdso64_rt_sigtramp && current->mm->context.vdso_base &&
+            nip == current->mm->context.vdso_base + vdso64_rt_sigtramp)
+                return 1;
+        return 0;
+}
+/*
+ * Do some sanity checking on the signal frame pointed to by sp.
+ * We check the pinfo and puc pointers in the frame.
+ */
+static int sane_signal_64_frame(unsigned long sp)
+{
+        struct signal_frame_64 __user *sf;
+        unsigned long pinfo, puc;
+        sf = (struct signal_frame_64 __user *) sp;
+        if (read_user_stack_64((unsigned long __user *) &sf->pinfo, &pinfo) ||
+            read_user_stack_64((unsigned long __user *) &sf->puc, &puc))
+                return 0;
+        return pinfo == (unsigned long) &sf->info &&
+                puc == (unsigned long) &sf->uc;
+}
+static void perf_callchain_user_64(struct pt_regs *regs,
+                                   struct perf_callchain_entry *entry)
+{
+        unsigned long sp, next_sp;
+        unsigned long next_ip;
+        unsigned long lr;
+        long level = 0;
+        struct signal_frame_64 __user *sigframe;
+        unsigned long __user *fp, *uregs;
+        next_ip = regs->nip;
+        lr = regs->link;
+        sp = regs->gpr[1];
+        callchain_store(entry, PERF_CONTEXT_USER);
+        callchain_store(entry, next_ip);
+        for (;;) {
+                fp = (unsigned long __user *) sp;
+                if (!valid_user_sp(sp, 1) || read_user_stack_64(fp, &next_sp))
+                        return;
+                if (level > 0 && read_user_stack_64(&fp[2], &next_ip))
+                        return;
+                /*
+                 * Note: the next_sp - sp >= signal frame size check
+                 * is true when next_sp < sp, which can happen when
+                 * transitioning from an alternate signal stack to the
+                 * normal stack.
+                 */
+                if (next_sp - sp >= sizeof(struct signal_frame_64) &&
+                    (is_sigreturn_64_address(next_ip, sp) ||
+                     (level <= 1 && is_sigreturn_64_address(lr, sp))) &&
+                    sane_signal_64_frame(sp)) {
+                        /*
+                         * This looks like an signal frame
+                         */
+                        sigframe = (struct signal_frame_64 __user *) sp;
+                        uregs = sigframe->uc.uc_mcontext.gp_regs;
+                        if (read_user_stack_64(&uregs[PT_NIP], &next_ip) ||
+                            read_user_stack_64(&uregs[PT_LNK], &lr) ||
+                            read_user_stack_64(&uregs[PT_R1], &sp))
+                                return;
+                        level = 0;
+                        callchain_store(entry, PERF_CONTEXT_USER);
+                        callchain_store(entry, next_ip);
+                        continue;
+                }
+                if (level == 0)
+                        next_ip = lr;
+                callchain_store(entry, next_ip);
+                ++level;
+                sp = next_sp;
+        }
+}
+static inline int current_is_64bit(void)
+{
+        /*
+         * We can't use test_thread_flag() here because we may be on an
+         * interrupt stack, and the thread flags don't get copied over
+         * from the thread_info on the main stack to the interrupt stack.
+         */
+        return !test_ti_thread_flag(task_thread_info(current), TIF_32BIT);
+}
+#else  /* CONFIG_PPC64 */
+/*
+ * On 32-bit we just access the address and let hash_page create a
+ * HPTE if necessary, so there is no need to fall back to reading
+ * the page tables.  Since this is called at interrupt level,
+ * do_page_fault() won't treat a DSI as a page fault.
+ */
+static int read_user_stack_32(unsigned int __user *ptr, unsigned int *ret)
+{
+        if ((unsigned long)ptr > TASK_SIZE - sizeof(unsigned int) ||
+            ((unsigned long)ptr & 3))
+                return -EFAULT;
+        return __get_user_inatomic(*ret, ptr);
+}
+static inline void perf_callchain_user_64(struct pt_regs *regs,
+                                          struct perf_callchain_entry *entry)
+{
+}
+static inline int current_is_64bit(void)
+{
+        return 0;
+}
+static inline int valid_user_sp(unsigned long sp, int is_64)
+{
+        if (!sp || (sp & 7) || sp > TASK_SIZE - 32)
+                return 0;
+        return 1;
+}
+#define __SIGNAL_FRAMESIZE32    __SIGNAL_FRAMESIZE
+#define sigcontext32            sigcontext
+#define mcontext32              mcontext
+#define ucontext32              ucontext
+#define compat_siginfo_t        struct siginfo
+#endif /* CONFIG_PPC64 */
+/*
+ * Layout for non-RT signal frames
+ */
+struct signal_frame_32 {
+        char                    dummy[__SIGNAL_FRAMESIZE32];
+        struct sigcontext32     sctx;
+        struct mcontext32       mctx;
+        int                     abigap[56];
+};
+/*
+ * Layout for RT signal frames
+ */
+struct rt_signal_frame_32 {
+        char                    dummy[__SIGNAL_FRAMESIZE32 + 16];
+        compat_siginfo_t        info;
+        struct ucontext32       uc;
+        int                     abigap[56];
+};
+static int is_sigreturn_32_address(unsigned int nip, unsigned int fp)
+{
+        if (nip == fp + offsetof(struct signal_frame_32, mctx.mc_pad))
+                return 1;
+        if (vdso32_sigtramp && current->mm->context.vdso_base &&
+            nip == current->mm->context.vdso_base + vdso32_sigtramp)
+                return 1;
+        return 0;
+}
+static int is_rt_sigreturn_32_address(unsigned int nip, unsigned int fp)
+{
+        if (nip == fp + offsetof(struct rt_signal_frame_32,
+                                 uc.uc_mcontext.mc_pad))
+                return 1;
+        if (vdso32_rt_sigtramp && current->mm->context.vdso_base &&
+            nip == current->mm->context.vdso_base + vdso32_rt_sigtramp)
+                return 1;
+        return 0;
+}
+static int sane_signal_32_frame(unsigned int sp)
+{
+        struct signal_frame_32 __user *sf;
+        unsigned int regs;
+        sf = (struct signal_frame_32 __user *) (unsigned long) sp;
+        if (read_user_stack_32((unsigned int __user *) &sf->sctx.regs, &regs))
+                return 0;
+        return regs == (unsigned long) &sf->mctx;
+}
+static int sane_rt_signal_32_frame(unsigned int sp)
+{
+        struct rt_signal_frame_32 __user *sf;
+        unsigned int regs;
+        sf = (struct rt_signal_frame_32 __user *) (unsigned long) sp;
+        if (read_user_stack_32((unsigned int __user *) &sf->uc.uc_regs, &regs))
+                return 0;
+        return regs == (unsigned long) &sf->uc.uc_mcontext;
+}
+static unsigned int __user *signal_frame_32_regs(unsigned int sp,
+                                unsigned int next_sp, unsigned int next_ip)
+{
+        struct mcontext32 __user *mctx = NULL;
+        struct signal_frame_32 __user *sf;
+        struct rt_signal_frame_32 __user *rt_sf;
+        /*
+         * Note: the next_sp - sp >= signal frame size check
+         * is true when next_sp < sp, for example, when
+         * transitioning from an alternate signal stack to the
+         * normal stack.
+         */
+        if (next_sp - sp >= sizeof(struct signal_frame_32) &&
+            is_sigreturn_32_address(next_ip, sp) &&
+            sane_signal_32_frame(sp)) {
+                sf = (struct signal_frame_32 __user *) (unsigned long) sp;
+                mctx = &sf->mctx;
+        }
+        if (!mctx && next_sp - sp >= sizeof(struct rt_signal_frame_32) &&
+            is_rt_sigreturn_32_address(next_ip, sp) &&
+            sane_rt_signal_32_frame(sp)) {
+                rt_sf = (struct rt_signal_frame_32 __user *) (unsigned long) sp;
+                mctx = &rt_sf->uc.uc_mcontext;
+        }
+        if (!mctx)
+                return NULL;
+        return mctx->mc_gregs;
+}
+static void perf_callchain_user_32(struct pt_regs *regs,
+                                   struct perf_callchain_entry *entry)
+{
+        unsigned int sp, next_sp;
+        unsigned int next_ip;
+        unsigned int lr;
+        long level = 0;
+        unsigned int __user *fp, *uregs;
+        next_ip = regs->nip;
+        lr = regs->link;
+        sp = regs->gpr[1];
+        callchain_store(entry, PERF_CONTEXT_USER);
+        callchain_store(entry, next_ip);
+        while (entry->nr < PERF_MAX_STACK_DEPTH) {
+                fp = (unsigned int __user *) (unsigned long) sp;
+                if (!valid_user_sp(sp, 0) || read_user_stack_32(fp, &next_sp))
+                        return;
+                if (level > 0 && read_user_stack_32(&fp[1], &next_ip))
+                        return;
+                uregs = signal_frame_32_regs(sp, next_sp, next_ip);
+                if (!uregs && level <= 1)
+                        uregs = signal_frame_32_regs(sp, next_sp, lr);
+                if (uregs) {
+                        /*
+                         * This looks like an signal frame, so restart
+                         * the stack trace with the values in it.
+                         */
+                        if (read_user_stack_32(&uregs[PT_NIP], &next_ip) ||
+                            read_user_stack_32(&uregs[PT_LNK], &lr) ||
+                            read_user_stack_32(&uregs[PT_R1], &sp))
+                                return;
+                        level = 0;
+                        callchain_store(entry, PERF_CONTEXT_USER);
+                        callchain_store(entry, next_ip);
+                        continue;
+                }
+                if (level == 0)
+                        next_ip = lr;
+                callchain_store(entry, next_ip);
+                ++level;
+                sp = next_sp;
+        }
+}
+/*
+ * Since we can't get PMU interrupts inside a PMU interrupt handler,
+ * we don't need separate irq and nmi entries here.
+ */
+static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
+struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
+{
+        struct perf_callchain_entry *entry = &__get_cpu_var(callchain);
+        entry->nr = 0;
+        if (current->pid == 0)          /* idle task? */
+                return entry;
+        if (!user_mode(regs)) {
+                perf_callchain_kernel(regs, entry);
+                if (current->mm)
+                        regs = task_pt_regs(current);
+                else
+                        regs = NULL;
+        }
+        if (regs) {
+                if (current_is_64bit())
+                        perf_callchain_user_64(regs, entry);
+                else
+                        perf_callchain_user_32(regs, entry);
+        }
+        return entry;
+}
diff --git a/arch/powerpc/kvm/44x.c b/arch/powerpc/kvm/44x.c
index 0cef809cec21..f4d1b55aa70b 100644
--- a/arch/powerpc/kvm/44x.c
+++ b/arch/powerpc/kvm/44x.c
@@ -138,7 +138,7 @@ void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
        kmem_cache_free(kvm_vcpu_cache, vcpu_44x);
 }
-static int kvmppc_44x_init(void)
+static int __init kvmppc_44x_init(void)
 {
        int r;
@@ -149,7 +149,7 @@ static int kvmppc_44x_init(void)
        return kvm_init(NULL, sizeof(struct kvmppc_vcpu_44x), THIS_MODULE);
 }
-static void kvmppc_44x_exit(void)
+static void __exit kvmppc_44x_exit(void)
 {
        kvmppc_booke_exit();
 }
diff --git a/arch/powerpc/kvm/44x_tlb.c b/arch/powerpc/kvm/44x_tlb.c
index 4a16f472cc18..ff3cb63b8117 100644
--- a/arch/powerpc/kvm/44x_tlb.c
+++ b/arch/powerpc/kvm/44x_tlb.c
@@ -30,6 +30,7 @@
 #include "timing.h"
 #include "44x_tlb.h"
+#include "trace.h"
 #ifndef PPC44x_TLBE_SIZE
 #define PPC44x_TLBE_SIZE        PPC44x_TLB_4K
@@ -263,7 +264,7 @@ static void kvmppc_44x_shadow_release(struct kvmppc_vcpu_44x *vcpu_44x,
        /* XXX set tlb_44x_index to stlb_index? */
-        KVMTRACE_1D(STLB_INVAL, &vcpu_44x->vcpu, stlb_index, handler);
+        trace_kvm_stlb_inval(stlb_index);
 }
 void kvmppc_mmu_destroy(struct kvm_vcpu *vcpu)
@@ -365,8 +366,8 @@ void kvmppc_mmu_map(struct kvm_vcpu *vcpu, u64 gvaddr, gpa_t gpaddr,
        /* Insert shadow mapping into hardware TLB. */
        kvmppc_44x_tlbe_set_modified(vcpu_44x, victim);
        kvmppc_44x_tlbwe(victim, &stlbe);
-        KVMTRACE_5D(STLB_WRITE, vcpu, victim, stlbe.tid, stlbe.word0, stlbe.word1,
+        trace_kvm_stlb_write(victim, stlbe.tid, stlbe.word0, stlbe.word1,
-                    stlbe.word2, handler);
+                             stlbe.word2);
 }
 /* For a particular guest TLB entry, invalidate the corresponding host TLB
@@ -485,8 +486,8 @@ int kvmppc_44x_emul_tlbwe(struct kvm_vcpu *vcpu, u8 ra, u8 rs, u8 ws)
                kvmppc_mmu_map(vcpu, eaddr, gpaddr, gtlb_index);
        }
-        KVMTRACE_5D(GTLB_WRITE, vcpu, gtlb_index, tlbe->tid, tlbe->word0,
+        trace_kvm_gtlb_write(gtlb_index, tlbe->tid, tlbe->word0, tlbe->word1,
-                    tlbe->word1, tlbe->word2, handler);
+                             tlbe->word2);
        kvmppc_set_exit_type(vcpu, EMULATED_TLBWE_EXITS);
        return EMULATE_DONE;
diff --git a/arch/powerpc/kvm/Kconfig b/arch/powerpc/kvm/Kconfig
index 5a152a52796f..c29926846613 100644
--- a/arch/powerpc/kvm/Kconfig
+++ b/arch/powerpc/kvm/Kconfig
@@ -2,8 +2,7 @@
 # KVM configuration
 #
-config HAVE_KVM_IRQCHIP
+source "virt/kvm/Kconfig"
-       bool
 menuconfig VIRTUALIZATION
        bool "Virtualization"
@@ -59,17 +58,6 @@ config KVM_E500
          If unsure, say N.
-config KVM_TRACE
-        bool "KVM trace support"
-        depends on KVM && MARKERS && SYSFS
-        select RELAY
-        select DEBUG_FS
-        default n
-        ---help---
-          This option allows reading a trace of kvm-related events through
-          relayfs.  Note the ABI is not considered stable and will be
-          modified in future updates.
 source drivers/virtio/Kconfig
 endif # VIRTUALIZATION
diff --git a/arch/powerpc/kvm/Makefile b/arch/powerpc/kvm/Makefile
index 459c7ee580f7..37655fe19f2f 100644
--- a/arch/powerpc/kvm/Makefile
+++ b/arch/powerpc/kvm/Makefile
@@ -8,7 +8,9 @@ EXTRA_CFLAGS += -Ivirt/kvm -Iarch/powerpc/kvm
 common-objs-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
-common-objs-$(CONFIG_KVM_TRACE)  += $(addprefix ../../../virt/kvm/, kvm_trace.o)
+CFLAGS_44x_tlb.o  := -I.
+CFLAGS_e500_tlb.o := -I.
+CFLAGS_emulate.o  := -I.
 kvm-objs := $(common-objs-y) powerpc.o emulate.o
 obj-$(CONFIG_KVM_EXIT_TIMING) += timing.o
diff --git a/arch/powerpc/kvm/booke.c b/arch/powerpc/kvm/booke.c
index 642e4204cf25..e7bf4d029484 100644
--- a/arch/powerpc/kvm/booke.c
+++ b/arch/powerpc/kvm/booke.c
@@ -520,7 +520,7 @@ int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
        return kvmppc_core_vcpu_translate(vcpu, tr);
 }
-int kvmppc_booke_init(void)
+int __init kvmppc_booke_init(void)
 {
        unsigned long ivor[16];
        unsigned long max_ivor = 0;
diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index d8067fd81cdd..64949eef43f1 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -60,9 +60,6 @@ int kvmppc_core_vcpu_setup(struct kvm_vcpu *vcpu)
        kvmppc_e500_tlb_setup(vcpu_e500);
-        /* Use the same core vertion as host's */
-        vcpu->arch.pvr = mfspr(SPRN_PVR);
        return 0;
 }
@@ -132,7 +129,7 @@ void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
        kmem_cache_free(kvm_vcpu_cache, vcpu_e500);
 }
-static int kvmppc_e500_init(void)
+static int __init kvmppc_e500_init(void)
 {
        int r, i;
        unsigned long ivor[3];
@@ -160,7 +157,7 @@ static int kvmppc_e500_init(void)
        return kvm_init(NULL, sizeof(struct kvmppc_vcpu_e500), THIS_MODULE);
 }
-static void kvmppc_e500_exit(void)
+static void __init kvmppc_e500_exit(void)
 {
        kvmppc_booke_exit();
 }
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index 3f760414b9f8..be95b8d8e3b7 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -180,6 +180,9 @@ int kvmppc_core_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, int rt)
        case SPRN_MMUCSR0:
                vcpu->arch.gpr[rt] = 0; break;
+        case SPRN_MMUCFG:
+                vcpu->arch.gpr[rt] = mfspr(SPRN_MMUCFG); break;
        /* extra exceptions */
        case SPRN_IVOR32:
                vcpu->arch.gpr[rt] = vcpu->arch.ivor[BOOKE_IRQPRIO_SPE_UNAVAIL];
diff --git a/arch/powerpc/kvm/e500_tlb.c b/arch/powerpc/kvm/e500_tlb.c
index 0e773fc2d5e4..fb1e1dc11ba5 100644
--- a/arch/powerpc/kvm/e500_tlb.c
+++ b/arch/powerpc/kvm/e500_tlb.c
@@ -22,6 +22,7 @@
 #include "../mm/mmu_decl.h"
 #include "e500_tlb.h"
+#include "trace.h"
 #define to_htlb1_esel(esel) (tlb1_entry_num - (esel) - 1)
@@ -224,9 +225,8 @@ static void kvmppc_e500_stlbe_invalidate(struct kvmppc_vcpu_e500 *vcpu_e500,
        kvmppc_e500_shadow_release(vcpu_e500, tlbsel, esel);
        stlbe->mas1 = 0;
-        KVMTRACE_5D(STLB_INVAL, &vcpu_e500->vcpu, index_of(tlbsel, esel),
+        trace_kvm_stlb_inval(index_of(tlbsel, esel), stlbe->mas1, stlbe->mas2,
-                        stlbe->mas1, stlbe->mas2, stlbe->mas3, stlbe->mas7,
+                             stlbe->mas3, stlbe->mas7);
-                        handler);
 }
 static void kvmppc_e500_tlb1_invalidate(struct kvmppc_vcpu_e500 *vcpu_e500,
@@ -269,7 +269,7 @@ static inline void kvmppc_e500_deliver_tlb_miss(struct kvm_vcpu *vcpu,
        tlbsel = (vcpu_e500->mas4 >> 28) & 0x1;
        victim = (tlbsel == 0) ? tlb0_get_next_victim(vcpu_e500) : 0;
        pidsel = (vcpu_e500->mas4 >> 16) & 0xf;
-        tsized = (vcpu_e500->mas4 >> 8) & 0xf;
+        tsized = (vcpu_e500->mas4 >> 7) & 0x1f;
        vcpu_e500->mas0 = MAS0_TLBSEL(tlbsel) | MAS0_ESEL(victim)
                | MAS0_NV(vcpu_e500->guest_tlb_nv[tlbsel]);
@@ -309,7 +309,7 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
        vcpu_e500->shadow_pages[tlbsel][esel] = new_page;
        /* Force TS=1 IPROT=0 TSIZE=4KB for all guest mappings. */
-        stlbe->mas1 = MAS1_TSIZE(BOOKE_PAGESZ_4K)
+        stlbe->mas1 = MAS1_TSIZE(BOOK3E_PAGESZ_4K)
                | MAS1_TID(get_tlb_tid(gtlbe)) | MAS1_TS | MAS1_VALID;
        stlbe->mas2 = (gvaddr & MAS2_EPN)
                | e500_shadow_mas2_attrib(gtlbe->mas2,
@@ -319,9 +319,8 @@ static inline void kvmppc_e500_shadow_map(struct kvmppc_vcpu_e500 *vcpu_e500,
                                vcpu_e500->vcpu.arch.msr & MSR_PR);
        stlbe->mas7 = (hpaddr >> 32) & MAS7_RPN;
-        KVMTRACE_5D(STLB_WRITE, &vcpu_e500->vcpu, index_of(tlbsel, esel),
+        trace_kvm_stlb_write(index_of(tlbsel, esel), stlbe->mas1, stlbe->mas2,
-                        stlbe->mas1, stlbe->mas2, stlbe->mas3, stlbe->mas7,
+                             stlbe->mas3, stlbe->mas7);
-                        handler);
 }
 /* XXX only map the one-one case, for now use TLB0 */
@@ -535,9 +534,8 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
        gtlbe->mas3 = vcpu_e500->mas3;
        gtlbe->mas7 = vcpu_e500->mas7;
-        KVMTRACE_5D(GTLB_WRITE, vcpu, vcpu_e500->mas0,
+        trace_kvm_gtlb_write(vcpu_e500->mas0, gtlbe->mas1, gtlbe->mas2,
-                        gtlbe->mas1, gtlbe->mas2, gtlbe->mas3, gtlbe->mas7,
+                             gtlbe->mas3, gtlbe->mas7);
-                        handler);
        /* Invalidate shadow mappings for the about-to-be-clobbered TLBE. */
        if (tlbe_is_host_safe(vcpu, gtlbe)) {
@@ -545,7 +543,7 @@ int kvmppc_e500_emul_tlbwe(struct kvm_vcpu *vcpu)
                case 0:
                        /* TLB0 */
                        gtlbe->mas1 &= ~MAS1_TSIZE(~0);
-                        gtlbe->mas1 |= MAS1_TSIZE(BOOKE_PAGESZ_4K);
+                        gtlbe->mas1 |= MAS1_TSIZE(BOOK3E_PAGESZ_4K);
                        stlbsel = 0;
                        sesel = kvmppc_e500_stlbe_map(vcpu_e500, 0, esel);
@@ -679,14 +677,14 @@ void kvmppc_e500_tlb_setup(struct kvmppc_vcpu_e500 *vcpu_e500)
        /* Insert large initial mapping for guest. */
        tlbe = &vcpu_e500->guest_tlb[1][0];
-        tlbe->mas1 = MAS1_VALID | MAS1_TSIZE(BOOKE_PAGESZ_256M);
+        tlbe->mas1 = MAS1_VALID | MAS1_TSIZE(BOOK3E_PAGESZ_256M);
        tlbe->mas2 = 0;
        tlbe->mas3 = E500_TLB_SUPER_PERM_MASK;
        tlbe->mas7 = 0;
        /* 4K map for serial output. Used by kernel wrapper. */
        tlbe = &vcpu_e500->guest_tlb[1][1];
-        tlbe->mas1 = MAS1_VALID | MAS1_TSIZE(BOOKE_PAGESZ_4K);
+        tlbe->mas1 = MAS1_VALID | MAS1_TSIZE(BOOK3E_PAGESZ_4K);
        tlbe->mas2 = (0xe0004500 & 0xFFFFF000) | MAS2_I | MAS2_G;
        tlbe->mas3 = (0xe0004500 & 0xFFFFF000) | E500_TLB_SUPER_PERM_MASK;
        tlbe->mas7 = 0;
diff --git a/arch/powerpc/kvm/e500_tlb.h b/arch/powerpc/kvm/e500_tlb.h
index 45b064b76906..d28e3010a5e2 100644
--- a/arch/powerpc/kvm/e500_tlb.h
+++ b/arch/powerpc/kvm/e500_tlb.h
@@ -16,7 +16,7 @@
 #define __KVM_E500_TLB_H__
 #include <linux/kvm_host.h>
-#include <asm/mmu-fsl-booke.h>
+#include <asm/mmu-book3e.h>
 #include <asm/tlb.h>
 #include <asm/kvm_e500.h>
@@ -59,7 +59,7 @@ extern void kvmppc_e500_tlb_setup(struct kvmppc_vcpu_e500 *);
 /* TLB helper functions */
 static inline unsigned int get_tlb_size(const struct tlbe *tlbe)
 {
-        return (tlbe->mas1 >> 8) & 0xf;
+        return (tlbe->mas1 >> 7) & 0x1f;
 }
 static inline gva_t get_tlb_eaddr(const struct tlbe *tlbe)
@@ -70,7 +70,7 @@ static inline gva_t get_tlb_eaddr(const struct tlbe *tlbe)
 static inline u64 get_tlb_bytes(const struct tlbe *tlbe)
 {
        unsigned int pgsize = get_tlb_size(tlbe);
-        return 1ULL << 10 << (pgsize << 1);
+        return 1ULL << 10 << pgsize;
 }
 static inline gva_t get_tlb_end(const struct tlbe *tlbe)
diff --git a/arch/powerpc/kvm/emulate.c b/arch/powerpc/kvm/emulate.c
index a561d6e8da1c..7737146af3fb 100644
--- a/arch/powerpc/kvm/emulate.c
+++ b/arch/powerpc/kvm/emulate.c
@@ -29,6 +29,7 @@
 #include <asm/kvm_ppc.h>
 #include <asm/disassemble.h>
 #include "timing.h"
+#include "trace.h"
 #define OP_TRAP 3
@@ -187,7 +188,9 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                        case SPRN_SRR1:
                                vcpu->arch.gpr[rt] = vcpu->arch.srr1; break;
                        case SPRN_PVR:
-                                vcpu->arch.gpr[rt] = vcpu->arch.pvr; break;
+                                vcpu->arch.gpr[rt] = mfspr(SPRN_PVR); break;
+                        case SPRN_PIR:
+                                vcpu->arch.gpr[rt] = mfspr(SPRN_PIR); break;
                        /* Note: mftb and TBRL/TBWL are user-accessible, so
                         * the guest can always access the real TB anyways.
@@ -417,7 +420,7 @@ int kvmppc_emulate_instruction(struct kvm_run *run, struct kvm_vcpu *vcpu)
                }
        }
-        KVMTRACE_3D(PPC_INSTR, vcpu, inst, (int)vcpu->arch.pc, emulated, entryexit);
+        trace_kvm_ppc_instr(inst, vcpu->arch.pc, emulated);
        if (advance)
                vcpu->arch.pc += 4; /* Advance past emulated instruction. */
diff --git a/arch/powerpc/kvm/powerpc.c b/arch/powerpc/kvm/powerpc.c
index 2cf915e51e7e..2a4551f78f60 100644
--- a/arch/powerpc/kvm/powerpc.c
+++ b/arch/powerpc/kvm/powerpc.c
@@ -31,25 +31,17 @@
 #include "timing.h"
 #include "../mm/mmu_decl.h"
+#define CREATE_TRACE_POINTS
+#include "trace.h"
 gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
 {
        return gfn;
 }
-int kvm_cpu_has_interrupt(struct kvm_vcpu *v)
-{
-        return !!(v->arch.pending_exceptions);
-}
-int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
-{
-        /* do real check here */
-        return 1;
-}
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
 {
-        return !(v->arch.msr & MSR_WE);
+        return !(v->arch.msr & MSR_WE) || !!(v->arch.pending_exceptions);
 }
@@ -122,13 +114,17 @@ struct kvm *kvm_arch_create_vm(void)
 static void kvmppc_free_vcpus(struct kvm *kvm)
 {
        unsigned int i;
+        struct kvm_vcpu *vcpu;
-        for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+        kvm_for_each_vcpu(i, vcpu, kvm)
-                if (kvm->vcpus[i]) {
+                kvm_arch_vcpu_free(vcpu);
-                        kvm_arch_vcpu_free(kvm->vcpus[i]);
-                        kvm->vcpus[i] = NULL;
+        mutex_lock(&kvm->lock);
-                }
+        for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
-        }
+                kvm->vcpus[i] = NULL;
+        atomic_set(&kvm->online_vcpus, 0);
+        mutex_unlock(&kvm->lock);
 }
 void kvm_arch_sync_events(struct kvm *kvm)
diff --git a/arch/powerpc/kvm/trace.h b/arch/powerpc/kvm/trace.h
new file mode 100644
index 000000000000..67f219de0455
--- /dev/null
+++ b/arch/powerpc/kvm/trace.h
@@ -0,0 +1,104 @@
+#if !defined(_TRACE_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_KVM_H
+#include <linux/tracepoint.h>
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM kvm
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE trace
+/*
+ * Tracepoint for guest mode entry.
+ */
+TRACE_EVENT(kvm_ppc_instr,
+        TP_PROTO(unsigned int inst, unsigned long pc, unsigned int emulate),
+        TP_ARGS(inst, pc, emulate),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   inst            )
+                __field(        unsigned long,  pc              )
+                __field(        unsigned int,   emulate         )
+        ),
+        TP_fast_assign(
+                __entry->inst           = inst;
+                __entry->pc             = pc;
+                __entry->emulate        = emulate;
+        ),
+        TP_printk("inst %u pc 0x%lx emulate %u\n",
+                  __entry->inst, __entry->pc, __entry->emulate)
+);
+TRACE_EVENT(kvm_stlb_inval,
+        TP_PROTO(unsigned int stlb_index),
+        TP_ARGS(stlb_index),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   stlb_index      )
+        ),
+        TP_fast_assign(
+                __entry->stlb_index     = stlb_index;
+        ),
+        TP_printk("stlb_index %u", __entry->stlb_index)
+);
+TRACE_EVENT(kvm_stlb_write,
+        TP_PROTO(unsigned int victim, unsigned int tid, unsigned int word0,
+                 unsigned int word1, unsigned int word2),
+        TP_ARGS(victim, tid, word0, word1, word2),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   victim          )
+                __field(        unsigned int,   tid             )
+                __field(        unsigned int,   word0           )
+                __field(        unsigned int,   word1           )
+                __field(        unsigned int,   word2           )
+        ),
+        TP_fast_assign(
+                __entry->victim         = victim;
+                __entry->tid            = tid;
+                __entry->word0          = word0;
+                __entry->word1          = word1;
+                __entry->word2          = word2;
+        ),
+        TP_printk("victim %u tid %u w0 %u w1 %u w2 %u",
+                __entry->victim, __entry->tid, __entry->word0,
+                __entry->word1, __entry->word2)
+);
+TRACE_EVENT(kvm_gtlb_write,
+        TP_PROTO(unsigned int gtlb_index, unsigned int tid, unsigned int word0,
+                 unsigned int word1, unsigned int word2),
+        TP_ARGS(gtlb_index, tid, word0, word1, word2),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   gtlb_index      )
+                __field(        unsigned int,   tid             )
+                __field(        unsigned int,   word0           )
+                __field(        unsigned int,   word1           )
+                __field(        unsigned int,   word2           )
+        ),
+        TP_fast_assign(
+                __entry->gtlb_index     = gtlb_index;
+                __entry->tid            = tid;
+                __entry->word0          = word0;
+                __entry->word1          = word1;
+                __entry->word2          = word2;
+        ),
+        TP_printk("gtlb_index %u tid %u w0 %u w1 %u w2 %u",
+                __entry->gtlb_index, __entry->tid, __entry->word0,
+                __entry->word1, __entry->word2)
+);
+#endif /* _TRACE_KVM_H */
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 5b7038f248b6..a685652effeb 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -92,15 +92,13 @@ static inline void create_shadowed_slbe(unsigned long ea, int ssize,
                     : "memory" );
 }
-void slb_flush_and_rebolt(void)
+static void __slb_flush_and_rebolt(void)
 {
        /* If you change this make sure you change SLB_NUM_BOLTED
         * appropriately too. */
        unsigned long linear_llp, vmalloc_llp, lflags, vflags;
        unsigned long ksp_esid_data, ksp_vsid_data;
-        WARN_ON(!irqs_disabled());
        linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
        vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
        lflags = SLB_VSID_KERNEL | linear_llp;
@@ -117,12 +115,6 @@ void slb_flush_and_rebolt(void)
                ksp_vsid_data = get_slb_shadow()->save_area[2].vsid;
        }
-        /*
-         * We can't take a PMU exception in the following code, so hard
-         * disable interrupts.
-         */
-        hard_irq_disable();
        /* We need to do this all in asm, so we're sure we don't touch
         * the stack between the slbia and rebolting it. */
        asm volatile("isync\n"
@@ -139,6 +131,21 @@ void slb_flush_and_rebolt(void)
                     : "memory");
 }
+void slb_flush_and_rebolt(void)
+{
+        WARN_ON(!irqs_disabled());
+        /*
+         * We can't take a PMU exception in the following code, so hard
+         * disable interrupts.
+         */
+        hard_irq_disable();
+        __slb_flush_and_rebolt();
+        get_paca()->slb_cache_ptr = 0;
+}
 void slb_vmalloc_update(void)
 {
        unsigned long vflags;
@@ -180,12 +187,20 @@ static inline int esids_match(unsigned long addr1, unsigned long addr2)
 /* Flush all user entries from the segment table of the current processor. */
 void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
 {
-        unsigned long offset = get_paca()->slb_cache_ptr;
+        unsigned long offset;
        unsigned long slbie_data = 0;
        unsigned long pc = KSTK_EIP(tsk);
        unsigned long stack = KSTK_ESP(tsk);
        unsigned long unmapped_base;
+        /*
+         * We need interrupts hard-disabled here, not just soft-disabled,
+         * so that a PMU interrupt can't occur, which might try to access
+         * user memory (to get a stack trace) and possible cause an SLB miss
+         * which would update the slb_cache/slb_cache_ptr fields in the PACA.
+         */
+        hard_irq_disable();
+        offset = get_paca()->slb_cache_ptr;
        if (!cpu_has_feature(CPU_FTR_NO_SLBIE_B) &&
            offset <= SLB_CACHE_ENTRIES) {
                int i;
@@ -200,7 +215,7 @@ void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
                }
                asm volatile("isync" : : : "memory");
        } else {
-                slb_flush_and_rebolt();
+                __slb_flush_and_rebolt();
        }
        /* Workaround POWER5 < DD2.1 issue */
diff --git a/arch/powerpc/mm/stab.c b/arch/powerpc/mm/stab.c
index 98cd1dc2ae75..ab5fb48b3e90 100644
--- a/arch/powerpc/mm/stab.c
+++ b/arch/powerpc/mm/stab.c
@@ -164,7 +164,7 @@ void switch_stab(struct task_struct *tsk, struct mm_struct *mm)
 {
        struct stab_entry *stab = (struct stab_entry *) get_paca()->stab_addr;
        struct stab_entry *ste;
-        unsigned long offset = __get_cpu_var(stab_cache_ptr);
+        unsigned long offset;
        unsigned long pc = KSTK_EIP(tsk);
        unsigned long stack = KSTK_ESP(tsk);
        unsigned long unmapped_base;
@@ -172,6 +172,15 @@ void switch_stab(struct task_struct *tsk, struct mm_struct *mm)
        /* Force previous translations to complete. DRENG */
        asm volatile("isync" : : : "memory");
+        /*
+         * We need interrupts hard-disabled here, not just soft-disabled,
+         * so that a PMU interrupt can't occur, which might try to access
+         * user memory (to get a stack trace) and possible cause an STAB miss
+         * which would update the stab_cache/stab_cache_ptr per-cpu variables.
+         */
+        hard_irq_disable();
+        offset = __get_cpu_var(stab_cache_ptr);
        if (offset <= NR_STAB_CACHE_ENTRIES) {
                int i;
diff --git a/arch/powerpc/sysdev/qe_lib/qe.c b/arch/powerpc/sysdev/qe_lib/qe.c
index 237e3654f48c..464271bea6c9 100644
--- a/arch/powerpc/sysdev/qe_lib/qe.c
+++ b/arch/powerpc/sysdev/qe_lib/qe.c
@@ -65,6 +65,19 @@ static unsigned int qe_num_of_snum;
 static phys_addr_t qebase = -1;
+int qe_alive_during_sleep(void)
+{
+        static int ret = -1;
+        if (ret != -1)
+                return ret;
+        ret = !of_find_compatible_node(NULL, NULL, "fsl,mpc8569-pmc");
+        return ret;
+}
+EXPORT_SYMBOL(qe_alive_during_sleep);
 phys_addr_t get_qe_base(void)
 {
        struct device_node *qe;
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 7238ef4c7a6b..1c866efd217d 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -95,7 +95,6 @@ config S390
        select HAVE_ARCH_TRACEHOOK
        select INIT_ALL_POSSIBLE
        select HAVE_PERF_COUNTERS
-        select GENERIC_ATOMIC64 if !64BIT
 config SCHED_OMIT_FRAME_POINTER
        bool
@@ -481,13 +480,6 @@ config CMM_IUCV
          Select this option to enable the special message interface to
          the cooperative memory management.
-config PAGE_STATES
-        bool "Unused page notification"
-        help
-          This enables the notification of unused pages to the
-          hypervisor. The ESSA instruction is used to do the states
-          changes between a page that has content and the unused state.
 config APPLDATA_BASE
        bool "Linux - VM Monitor Stream, base infrastructure"
        depends on PROC_FS
diff --git a/arch/s390/Makefile b/arch/s390/Makefile
index 0ff387cebf88..fc8fb20e7fc0 100644
--- a/arch/s390/Makefile
+++ b/arch/s390/Makefile
@@ -88,8 +88,7 @@ LDFLAGS_vmlinux := -e start
 head-y          := arch/s390/kernel/head.o arch/s390/kernel/init_task.o
 core-y          += arch/s390/mm/ arch/s390/kernel/ arch/s390/crypto/ \
-                   arch/s390/appldata/ arch/s390/hypfs/ arch/s390/kvm/ \
+                   arch/s390/appldata/ arch/s390/hypfs/ arch/s390/kvm/
-                   arch/s390/power/
 libs-y          += arch/s390/lib/
 drivers-y       += drivers/s390/
diff --git a/arch/s390/crypto/des_s390.c b/arch/s390/crypto/des_s390.c
index 4aba83b31596..2bc479ab3a66 100644
--- a/arch/s390/crypto/des_s390.c
+++ b/arch/s390/crypto/des_s390.c
@@ -250,8 +250,9 @@ static int des3_128_setkey(struct crypto_tfm *tfm, const u8 *key,
        const u8 *temp_key = key;
        u32 *flags = &tfm->crt_flags;
-        if (!(memcmp(key, &key[DES_KEY_SIZE], DES_KEY_SIZE))) {
+        if (!(memcmp(key, &key[DES_KEY_SIZE], DES_KEY_SIZE)) &&
-                *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
+            (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
+                *flags |= CRYPTO_TFM_RES_WEAK_KEY;
                return -EINVAL;
        }
        for (i = 0; i < 2; i++, temp_key += DES_KEY_SIZE) {
@@ -411,9 +412,9 @@ static int des3_192_setkey(struct crypto_tfm *tfm, const u8 *key,
        if (!(memcmp(key, &key[DES_KEY_SIZE], DES_KEY_SIZE) &&
            memcmp(&key[DES_KEY_SIZE], &key[DES_KEY_SIZE * 2],
-                   DES_KEY_SIZE))) {
+                   DES_KEY_SIZE)) &&
+            (*flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
-                *flags |= CRYPTO_TFM_RES_BAD_KEY_SCHED;
+                *flags |= CRYPTO_TFM_RES_WEAK_KEY;
                return -EINVAL;
        }
        for (i = 0; i < 3; i++, temp_key += DES_KEY_SIZE) {
diff --git a/arch/s390/crypto/sha1_s390.c b/arch/s390/crypto/sha1_s390.c
index e85ba348722a..f6de7826c979 100644
--- a/arch/s390/crypto/sha1_s390.c
+++ b/arch/s390/crypto/sha1_s390.c
@@ -46,12 +46,38 @@ static int sha1_init(struct shash_desc *desc)
        return 0;
 }
+static int sha1_export(struct shash_desc *desc, void *out)
+{
+        struct s390_sha_ctx *sctx = shash_desc_ctx(desc);
+        struct sha1_state *octx = out;
+        octx->count = sctx->count;
+        memcpy(octx->state, sctx->state, sizeof(octx->state));
+        memcpy(octx->buffer, sctx->buf, sizeof(octx->buffer));
+        return 0;
+}
+static int sha1_import(struct shash_desc *desc, const void *in)
+{
+        struct s390_sha_ctx *sctx = shash_desc_ctx(desc);
+        const struct sha1_state *ictx = in;
+        sctx->count = ictx->count;
+        memcpy(sctx->state, ictx->state, sizeof(ictx->state));
+        memcpy(sctx->buf, ictx->buffer, sizeof(ictx->buffer));
+        sctx->func = KIMD_SHA_1;
+        return 0;
+}
 static struct shash_alg alg = {
        .digestsize     =       SHA1_DIGEST_SIZE,
        .init           =       sha1_init,
        .update         =       s390_sha_update,
        .final          =       s390_sha_final,
+        .export         =       sha1_export,
+        .import         =       sha1_import,
        .descsize       =       sizeof(struct s390_sha_ctx),
+        .statesize      =       sizeof(struct sha1_state),
        .base           =       {
                .cra_name       =       "sha1",
                .cra_driver_name=       "sha1-s390",
diff --git a/arch/s390/crypto/sha256_s390.c b/arch/s390/crypto/sha256_s390.c
index f9fefc569632..61a7db372121 100644
--- a/arch/s390/crypto/sha256_s390.c
+++ b/arch/s390/crypto/sha256_s390.c
@@ -42,12 +42,38 @@ static int sha256_init(struct shash_desc *desc)
        return 0;
 }
+static int sha256_export(struct shash_desc *desc, void *out)
+{
+        struct s390_sha_ctx *sctx = shash_desc_ctx(desc);
+        struct sha256_state *octx = out;
+        octx->count = sctx->count;
+        memcpy(octx->state, sctx->state, sizeof(octx->state));
+        memcpy(octx->buf, sctx->buf, sizeof(octx->buf));
+        return 0;
+}
+static int sha256_import(struct shash_desc *desc, const void *in)
+{
+        struct s390_sha_ctx *sctx = shash_desc_ctx(desc);
+        const struct sha256_state *ictx = in;
+        sctx->count = ictx->count;
+        memcpy(sctx->state, ictx->state, sizeof(ictx->state));
+        memcpy(sctx->buf, ictx->buf, sizeof(ictx->buf));
+        sctx->func = KIMD_SHA_256;
+        return 0;
+}
 static struct shash_alg alg = {
        .digestsize     =       SHA256_DIGEST_SIZE,
        .init           =       sha256_init,
        .update         =       s390_sha_update,
        .final          =       s390_sha_final,
+        .export         =       sha256_export,
+        .import         =       sha256_import,
        .descsize       =       sizeof(struct s390_sha_ctx),
+        .statesize      =       sizeof(struct sha256_state),
        .base           =       {
                .cra_name       =       "sha256",
                .cra_driver_name=       "sha256-s390",
diff --git a/arch/s390/crypto/sha512_s390.c b/arch/s390/crypto/sha512_s390.c
index 83192bfc8048..4bf73d0dc525 100644
--- a/arch/s390/crypto/sha512_s390.c
+++ b/arch/s390/crypto/sha512_s390.c
@@ -13,7 +13,10 @@
 *
 */
 #include <crypto/internal/hash.h>
+#include <crypto/sha.h>
+#include <linux/errno.h>
 #include <linux/init.h>
+#include <linux/kernel.h>
 #include <linux/module.h>
 #include "sha.h"
@@ -37,12 +40,42 @@ static int sha512_init(struct shash_desc *desc)
        return 0;
 }
+static int sha512_export(struct shash_desc *desc, void *out)
+{
+        struct s390_sha_ctx *sctx = shash_desc_ctx(desc);
+        struct sha512_state *octx = out;
+        octx->count[0] = sctx->count;
+        octx->count[1] = 0;
+        memcpy(octx->state, sctx->state, sizeof(octx->state));
+        memcpy(octx->buf, sctx->buf, sizeof(octx->buf));
+        return 0;
+}
+static int sha512_import(struct shash_desc *desc, const void *in)
+{
+        struct s390_sha_ctx *sctx = shash_desc_ctx(desc);
+        const struct sha512_state *ictx = in;
+        if (unlikely(ictx->count[1]))
+                return -ERANGE;
+        sctx->count = ictx->count[0];
+        memcpy(sctx->state, ictx->state, sizeof(ictx->state));
+        memcpy(sctx->buf, ictx->buf, sizeof(ictx->buf));
+        sctx->func = KIMD_SHA_512;
+        return 0;
+}
 static struct shash_alg sha512_alg = {
        .digestsize     =       SHA512_DIGEST_SIZE,
        .init           =       sha512_init,
        .update         =       s390_sha_update,
        .final          =       s390_sha_final,
+        .export         =       sha512_export,
+        .import         =       sha512_import,
        .descsize       =       sizeof(struct s390_sha_ctx),
+        .statesize      =       sizeof(struct sha512_state),
        .base           =       {
                .cra_name       =       "sha512",
                .cra_driver_name=       "sha512-s390",
@@ -78,7 +111,10 @@ static struct shash_alg sha384_alg = {
        .init           =       sha384_init,
        .update         =       s390_sha_update,
        .final          =       s390_sha_final,
+        .export         =       sha512_export,
+        .import         =       sha512_import,
        .descsize       =       sizeof(struct s390_sha_ctx),
+        .statesize      =       sizeof(struct sha512_state),
        .base           =       {
                .cra_name       =       "sha384",
                .cra_driver_name=       "sha384-s390",
diff --git a/arch/s390/hypfs/inode.c b/arch/s390/hypfs/inode.c
index 5a805df216bb..bd9914b89488 100644
--- a/arch/s390/hypfs/inode.c
+++ b/arch/s390/hypfs/inode.c
@@ -355,11 +355,7 @@ static struct dentry *hypfs_create_file(struct super_block *sb,
 {
        struct dentry *dentry;
        struct inode *inode;
-        struct qstr qname;
-        qname.name = name;
-        qname.len = strlen(name);
-        qname.hash = full_name_hash(name, qname.len);
        mutex_lock(&parent->d_inode->i_mutex);
        dentry = lookup_one_len(name, parent, strlen(name));
        if (IS_ERR(dentry)) {
@@ -426,7 +422,7 @@ struct dentry *hypfs_create_u64(struct super_block *sb, struct dentry *dir,
        char tmp[TMP_SIZE];
        struct dentry *dentry;
-        snprintf(tmp, TMP_SIZE, "%lld\n", (unsigned long long int)value);
+        snprintf(tmp, TMP_SIZE, "%llu\n", (unsigned long long int)value);
        buffer = kstrdup(tmp, GFP_KERNEL);
        if (!buffer)
                return ERR_PTR(-ENOMEM);
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h
index c7d0abfb0f00..ae7c8f9f94a5 100644
--- a/arch/s390/include/asm/atomic.h
+++ b/arch/s390/include/asm/atomic.h
@@ -1,33 +1,23 @@
 #ifndef __ARCH_S390_ATOMIC__
 #define __ARCH_S390_ATOMIC__
-#include <linux/compiler.h>
-#include <linux/types.h>
 /*
- *  include/asm-s390/atomic.h
+ * Copyright 1999,2009 IBM Corp.
+ * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *            Denis Joseph Barrow,
+ *            Arnd Bergmann <arndb@de.ibm.com>,
 *
- *  S390 version
+ * Atomic operations that C can't guarantee us.
- *    Copyright (C) 1999-2005 IBM Deutschland Entwicklung GmbH, IBM Corporation
+ * Useful for resource counting etc.
- *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
+ * s390 uses 'Compare And Swap' for atomicity in SMP enviroment.
- *               Denis Joseph Barrow,
- *               Arnd Bergmann (arndb@de.ibm.com)
- *
- *  Derived from "include/asm-i386/bitops.h"
- *    Copyright (C) 1992, Linus Torvalds
 *
 */
-/*
+#include <linux/compiler.h>
- * Atomic operations that C can't guarantee us.  Useful for
+#include <linux/types.h>
- * resource counting etc..
- * S390 uses 'Compare And Swap' for atomicity in SMP enviroment
- */
 #define ATOMIC_INIT(i)  { (i) }
-#ifdef __KERNEL__
 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
 #define __CS_LOOP(ptr, op_val, op_string) ({                            \
@@ -77,7 +67,7 @@ static inline void atomic_set(atomic_t *v, int i)
        barrier();
 }
-static __inline__ int atomic_add_return(int i, atomic_t * v)
+static inline int atomic_add_return(int i, atomic_t *v)
 {
        return __CS_LOOP(v, i, "ar");
 }
@@ -87,7 +77,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v)
 #define atomic_inc_return(_v)           atomic_add_return(1, _v)
 #define atomic_inc_and_test(_v)         (atomic_add_return(1, _v) == 0)
-static __inline__ int atomic_sub_return(int i, atomic_t * v)
+static inline int atomic_sub_return(int i, atomic_t *v)
 {
        return __CS_LOOP(v, i, "sr");
 }
@@ -97,19 +87,19 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v)
 #define atomic_dec_return(_v)           atomic_sub_return(1, _v)
 #define atomic_dec_and_test(_v)         (atomic_sub_return(1, _v) == 0)
-static __inline__ void atomic_clear_mask(unsigned long mask, atomic_t * v)
+static inline void atomic_clear_mask(unsigned long mask, atomic_t *v)
 {
-               __CS_LOOP(v, ~mask, "nr");
+        __CS_LOOP(v, ~mask, "nr");
 }
-static __inline__ void atomic_set_mask(unsigned long mask, atomic_t * v)
+static inline void atomic_set_mask(unsigned long mask, atomic_t *v)
 {
-               __CS_LOOP(v, mask, "or");
+        __CS_LOOP(v, mask, "or");
 }
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-static __inline__ int atomic_cmpxchg(atomic_t *v, int old, int new)
+static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
 {
 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
        asm volatile(
@@ -127,7 +117,7 @@ static __inline__ int atomic_cmpxchg(atomic_t *v, int old, int new)
        return old;
 }
-static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
 {
        int c, old;
        c = atomic_read(v);
@@ -146,9 +136,10 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
 #undef __CS_LOOP
-#ifdef __s390x__
 #define ATOMIC64_INIT(i)  { (i) }
+#ifdef CONFIG_64BIT
 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
 #define __CSG_LOOP(ptr, op_val, op_string) ({                           \
@@ -162,7 +153,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
                : "=&d" (old_val), "=&d" (new_val),                     \
                  "=Q" (((atomic_t *)(ptr))->counter)                   \
                : "d" (op_val), "Q" (((atomic_t *)(ptr))->counter)      \
-                : "cc", "memory" );                                     \
+                : "cc", "memory");                                      \
        new_val;                                                        \
 })
@@ -180,7 +171,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
                  "=m" (((atomic_t *)(ptr))->counter)                   \
                : "a" (ptr), "d" (op_val),                              \
                  "m" (((atomic_t *)(ptr))->counter)                    \
-                : "cc", "memory" );                                     \
+                : "cc", "memory");                                      \
        new_val;                                                        \
 })
@@ -198,39 +189,29 @@ static inline void atomic64_set(atomic64_t *v, long long i)
        barrier();
 }
-static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
+static inline long long atomic64_add_return(long long i, atomic64_t *v)
 {
        return __CSG_LOOP(v, i, "agr");
 }
-#define atomic64_add(_i, _v)            atomic64_add_return(_i, _v)
-#define atomic64_add_negative(_i, _v)   (atomic64_add_return(_i, _v) < 0)
-#define atomic64_inc(_v)                atomic64_add_return(1, _v)
-#define atomic64_inc_return(_v)         atomic64_add_return(1, _v)
-#define atomic64_inc_and_test(_v)       (atomic64_add_return(1, _v) == 0)
-static __inline__ long long atomic64_sub_return(long long i, atomic64_t * v)
+static inline long long atomic64_sub_return(long long i, atomic64_t *v)
 {
        return __CSG_LOOP(v, i, "sgr");
 }
-#define atomic64_sub(_i, _v)            atomic64_sub_return(_i, _v)
-#define atomic64_sub_and_test(_i, _v)   (atomic64_sub_return(_i, _v) == 0)
-#define atomic64_dec(_v)                atomic64_sub_return(1, _v)
-#define atomic64_dec_return(_v)         atomic64_sub_return(1, _v)
-#define atomic64_dec_and_test(_v)       (atomic64_sub_return(1, _v) == 0)
-static __inline__ void atomic64_clear_mask(unsigned long mask, atomic64_t * v)
+static inline void atomic64_clear_mask(unsigned long mask, atomic64_t *v)
 {
-               __CSG_LOOP(v, ~mask, "ngr");
+        __CSG_LOOP(v, ~mask, "ngr");
 }
-static __inline__ void atomic64_set_mask(unsigned long mask, atomic64_t * v)
+static inline void atomic64_set_mask(unsigned long mask, atomic64_t *v)
 {
-               __CSG_LOOP(v, mask, "ogr");
+        __CSG_LOOP(v, mask, "ogr");
 }
 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
-static __inline__ long long atomic64_cmpxchg(atomic64_t *v,
+static inline long long atomic64_cmpxchg(atomic64_t *v,
                                             long long old, long long new)
 {
 #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ > 2)
@@ -249,8 +230,112 @@ static __inline__ long long atomic64_cmpxchg(atomic64_t *v,
        return old;
 }
-static __inline__ int atomic64_add_unless(atomic64_t *v,
+#undef __CSG_LOOP
-                                          long long a, long long u)
+#else /* CONFIG_64BIT */
+typedef struct {
+        long long counter;
+} atomic64_t;
+static inline long long atomic64_read(const atomic64_t *v)
+{
+        register_pair rp;
+        asm volatile(
+                "       lm      %0,%N0,0(%1)"
+                : "=&d" (rp)
+                : "a" (&v->counter), "m" (v->counter)
+                );
+        return rp.pair;
+}
+static inline void atomic64_set(atomic64_t *v, long long i)
+{
+        register_pair rp = {.pair = i};
+        asm volatile(
+                "       stm     %1,%N1,0(%2)"
+                : "=m" (v->counter)
+                : "d" (rp), "a" (&v->counter)
+                );
+}
+static inline long long atomic64_xchg(atomic64_t *v, long long new)
+{
+        register_pair rp_new = {.pair = new};
+        register_pair rp_old;
+        asm volatile(
+                "       lm      %0,%N0,0(%2)\n"
+                "0:     cds     %0,%3,0(%2)\n"
+                "       jl      0b\n"
+                : "=&d" (rp_old), "+m" (v->counter)
+                : "a" (&v->counter), "d" (rp_new)
+                : "cc");
+        return rp_old.pair;
+}
+static inline long long atomic64_cmpxchg(atomic64_t *v,
+                                         long long old, long long new)
+{
+        register_pair rp_old = {.pair = old};
+        register_pair rp_new = {.pair = new};
+        asm volatile(
+                "       cds     %0,%3,0(%2)"
+                : "+&d" (rp_old), "+m" (v->counter)
+                : "a" (&v->counter), "d" (rp_new)
+                : "cc");
+        return rp_old.pair;
+}
+static inline long long atomic64_add_return(long long i, atomic64_t *v)
+{
+        long long old, new;
+        do {
+                old = atomic64_read(v);
+                new = old + i;
+        } while (atomic64_cmpxchg(v, old, new) != old);
+        return new;
+}
+static inline long long atomic64_sub_return(long long i, atomic64_t *v)
+{
+        long long old, new;
+        do {
+                old = atomic64_read(v);
+                new = old - i;
+        } while (atomic64_cmpxchg(v, old, new) != old);
+        return new;
+}
+static inline void atomic64_set_mask(unsigned long long mask, atomic64_t *v)
+{
+        long long old, new;
+        do {
+                old = atomic64_read(v);
+                new = old | mask;
+        } while (atomic64_cmpxchg(v, old, new) != old);
+}
+static inline void atomic64_clear_mask(unsigned long long mask, atomic64_t *v)
+{
+        long long old, new;
+        do {
+                old = atomic64_read(v);
+                new = old & mask;
+        } while (atomic64_cmpxchg(v, old, new) != old);
+}
+#endif /* CONFIG_64BIT */
+static inline int atomic64_add_unless(atomic64_t *v, long long a, long long u)
 {
        long long c, old;
        c = atomic64_read(v);
@@ -265,15 +350,17 @@ static __inline__ int atomic64_add_unless(atomic64_t *v,
        return c != u;
 }
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+#define atomic64_add(_i, _v)            atomic64_add_return(_i, _v)
+#define atomic64_add_negative(_i, _v)   (atomic64_add_return(_i, _v) < 0)
-#undef __CSG_LOOP
+#define atomic64_inc(_v)                atomic64_add_return(1, _v)
+#define atomic64_inc_return(_v)         atomic64_add_return(1, _v)
-#else /* __s390x__ */
+#define atomic64_inc_and_test(_v)       (atomic64_add_return(1, _v) == 0)
+#define atomic64_sub(_i, _v)            atomic64_sub_return(_i, _v)
-#include <asm-generic/atomic64.h>
+#define atomic64_sub_and_test(_i, _v)   (atomic64_sub_return(_i, _v) == 0)
+#define atomic64_dec(_v)                atomic64_sub_return(1, _v)
-#endif /* __s390x__ */
+#define atomic64_dec_return(_v)         atomic64_sub_return(1, _v)
+#define atomic64_dec_and_test(_v)       (atomic64_sub_return(1, _v) == 0)
+#define atomic64_inc_not_zero(v)        atomic64_add_unless((v), 1, 0)
 #define smp_mb__before_atomic_dec()     smp_mb()
 #define smp_mb__after_atomic_dec()      smp_mb()
@@ -281,5 +368,5 @@ static __inline__ int atomic64_add_unless(atomic64_t *v,
 #define smp_mb__after_atomic_inc()      smp_mb()
 #include <asm-generic/atomic-long.h>
-#endif /* __KERNEL__ */
 #endif /* __ARCH_S390_ATOMIC__  */
diff --git a/arch/s390/include/asm/checksum.h b/arch/s390/include/asm/checksum.h
index d5a8e7c1477c..6c00f6800a34 100644
--- a/arch/s390/include/asm/checksum.h
+++ b/arch/s390/include/asm/checksum.h
@@ -78,28 +78,11 @@ csum_partial_copy_nocheck (const void *src, void *dst, int len, __wsum sum)
 */
 static inline __sum16 csum_fold(__wsum sum)
 {
-#ifndef __s390x__
+        u32 csum = (__force u32) sum;
-        register_pair rp;
-        asm volatile(
+        csum += (csum >> 16) + (csum << 16);
-                "       slr     %N1,%N1\n"      /* %0 = H L */
+        csum >>= 16;
-                "       lr      %1,%0\n"        /* %0 = H L, %1 = H L 0 0 */
+        return (__force __sum16) ~csum;
-                "       srdl    %1,16\n"        /* %0 = H L, %1 = 0 H L 0 */
-                "       alr     %1,%N1\n"       /* %0 = H L, %1 = L H L 0 */
-                "       alr     %0,%1\n"        /* %0 = H+L+C L+H */
-                "       srl     %0,16\n"        /* %0 = H+L+C */
-                : "+&d" (sum), "=d" (rp) : : "cc");
-#else /* __s390x__ */
-        asm volatile(
-                "       sr      3,3\n"          /* %0 = H*65536 + L */
-                "       lr      2,%0\n"         /* %0 = H L, 2/3 = H L / 0 0 */
-                "       srdl    2,16\n"         /* %0 = H L, 2/3 = 0 H / L 0 */
-                "       alr     2,3\n"          /* %0 = H L, 2/3 = L H / L 0 */
-                "       alr     %0,2\n"         /* %0 = H+L+C L+H */
-                "       srl     %0,16\n"        /* %0 = H+L+C */
-                : "+&d" (sum) : : "cc", "2", "3");
-#endif /* __s390x__ */
-        return (__force __sum16) ~sum;
 }
 /*
diff --git a/arch/s390/include/asm/chsc.h b/arch/s390/include/asm/chsc.h
index 807997f7414b..4943654ed7fd 100644
--- a/arch/s390/include/asm/chsc.h
+++ b/arch/s390/include/asm/chsc.h
@@ -125,4 +125,32 @@ struct chsc_cpd_info {
 #define CHSC_INFO_CPD _IOWR(CHSC_IOCTL_MAGIC, 0x87, struct chsc_cpd_info)
 #define CHSC_INFO_DCAL _IOWR(CHSC_IOCTL_MAGIC, 0x88, struct chsc_dcal)
+#ifdef __KERNEL__
+struct css_general_char {
+        u64 : 12;
+        u32 dynio : 1;   /* bit 12 */
+        u32 : 28;
+        u32 aif : 1;     /* bit 41 */
+        u32 : 3;
+        u32 mcss : 1;    /* bit 45 */
+        u32 fcs : 1;     /* bit 46 */
+        u32 : 1;
+        u32 ext_mb : 1;  /* bit 48 */
+        u32 : 7;
+        u32 aif_tdd : 1; /* bit 56 */
+        u32 : 1;
+        u32 qebsm : 1;   /* bit 58 */
+        u32 : 8;
+        u32 aif_osa : 1; /* bit 67 */
+        u32 : 14;
+        u32 cib : 1;     /* bit 82 */
+        u32 : 5;
+        u32 fcx : 1;     /* bit 88 */
+        u32 : 7;
+}__attribute__((packed));
+extern struct css_general_char css_general_characteristics;
+#endif /* __KERNEL__ */
 #endif
diff --git a/arch/s390/include/asm/cio.h b/arch/s390/include/asm/cio.h
index 619bf94b11f1..e85679af54dd 100644
--- a/arch/s390/include/asm/cio.h
+++ b/arch/s390/include/asm/cio.h
@@ -15,228 +15,7 @@
 #define LPM_ANYPATH 0xff
 #define __MAX_CSSID 0
-/**
+#include <asm/scsw.h>
- * struct cmd_scsw - command-mode subchannel status word
- * @key: subchannel key
- * @sctl: suspend control
- * @eswf: esw format
- * @cc: deferred condition code
- * @fmt: format
- * @pfch: prefetch
- * @isic: initial-status interruption control
- * @alcc: address-limit checking control
- * @ssi: suppress-suspended interruption
- * @zcc: zero condition code
- * @ectl: extended control
- * @pno: path not operational
- * @res: reserved
- * @fctl: function control
- * @actl: activity control
- * @stctl: status control
- * @cpa: channel program address
- * @dstat: device status
- * @cstat: subchannel status
- * @count: residual count
- */
-struct cmd_scsw {
-        __u32 key  : 4;
-        __u32 sctl : 1;
-        __u32 eswf : 1;
-        __u32 cc   : 2;
-        __u32 fmt  : 1;
-        __u32 pfch : 1;
-        __u32 isic : 1;
-        __u32 alcc : 1;
-        __u32 ssi  : 1;
-        __u32 zcc  : 1;
-        __u32 ectl : 1;
-        __u32 pno  : 1;
-        __u32 res  : 1;
-        __u32 fctl : 3;
-        __u32 actl : 7;
-        __u32 stctl : 5;
-        __u32 cpa;
-        __u32 dstat : 8;
-        __u32 cstat : 8;
-        __u32 count : 16;
-} __attribute__ ((packed));
-/**
- * struct tm_scsw - transport-mode subchannel status word
- * @key: subchannel key
- * @eswf: esw format
- * @cc: deferred condition code
- * @fmt: format
- * @x: IRB-format control
- * @q: interrogate-complete
- * @ectl: extended control
- * @pno: path not operational
- * @fctl: function control
- * @actl: activity control
- * @stctl: status control
- * @tcw: TCW address
- * @dstat: device status
- * @cstat: subchannel status
- * @fcxs: FCX status
- * @schxs: subchannel-extended status
- */
-struct tm_scsw {
-        u32 key:4;
-        u32 :1;
-        u32 eswf:1;
-        u32 cc:2;
-        u32 fmt:3;
-        u32 x:1;
-        u32 q:1;
-        u32 :1;
-        u32 ectl:1;
-        u32 pno:1;
-        u32 :1;
-        u32 fctl:3;
-        u32 actl:7;
-        u32 stctl:5;
-        u32 tcw;
-        u32 dstat:8;
-        u32 cstat:8;
-        u32 fcxs:8;
-        u32 schxs:8;
-} __attribute__ ((packed));
-/**
- * union scsw - subchannel status word
- * @cmd: command-mode SCSW
- * @tm: transport-mode SCSW
- */
-union scsw {
-        struct cmd_scsw cmd;
-        struct tm_scsw tm;
-} __attribute__ ((packed));
-int scsw_is_tm(union scsw *scsw);
-u32 scsw_key(union scsw *scsw);
-u32 scsw_eswf(union scsw *scsw);
-u32 scsw_cc(union scsw *scsw);
-u32 scsw_ectl(union scsw *scsw);
-u32 scsw_pno(union scsw *scsw);
-u32 scsw_fctl(union scsw *scsw);
-u32 scsw_actl(union scsw *scsw);
-u32 scsw_stctl(union scsw *scsw);
-u32 scsw_dstat(union scsw *scsw);
-u32 scsw_cstat(union scsw *scsw);
-int scsw_is_solicited(union scsw *scsw);
-int scsw_is_valid_key(union scsw *scsw);
-int scsw_is_valid_eswf(union scsw *scsw);
-int scsw_is_valid_cc(union scsw *scsw);
-int scsw_is_valid_ectl(union scsw *scsw);
-int scsw_is_valid_pno(union scsw *scsw);
-int scsw_is_valid_fctl(union scsw *scsw);
-int scsw_is_valid_actl(union scsw *scsw);
-int scsw_is_valid_stctl(union scsw *scsw);
-int scsw_is_valid_dstat(union scsw *scsw);
-int scsw_is_valid_cstat(union scsw *scsw);
-int scsw_cmd_is_valid_key(union scsw *scsw);
-int scsw_cmd_is_valid_sctl(union scsw *scsw);
-int scsw_cmd_is_valid_eswf(union scsw *scsw);
-int scsw_cmd_is_valid_cc(union scsw *scsw);
-int scsw_cmd_is_valid_fmt(union scsw *scsw);
-int scsw_cmd_is_valid_pfch(union scsw *scsw);
-int scsw_cmd_is_valid_isic(union scsw *scsw);
-int scsw_cmd_is_valid_alcc(union scsw *scsw);
-int scsw_cmd_is_valid_ssi(union scsw *scsw);
-int scsw_cmd_is_valid_zcc(union scsw *scsw);
-int scsw_cmd_is_valid_ectl(union scsw *scsw);
-int scsw_cmd_is_valid_pno(union scsw *scsw);
-int scsw_cmd_is_valid_fctl(union scsw *scsw);
-int scsw_cmd_is_valid_actl(union scsw *scsw);
-int scsw_cmd_is_valid_stctl(union scsw *scsw);
-int scsw_cmd_is_valid_dstat(union scsw *scsw);
-int scsw_cmd_is_valid_cstat(union scsw *scsw);
-int scsw_cmd_is_solicited(union scsw *scsw);
-int scsw_tm_is_valid_key(union scsw *scsw);
-int scsw_tm_is_valid_eswf(union scsw *scsw);
-int scsw_tm_is_valid_cc(union scsw *scsw);
-int scsw_tm_is_valid_fmt(union scsw *scsw);
-int scsw_tm_is_valid_x(union scsw *scsw);
-int scsw_tm_is_valid_q(union scsw *scsw);
-int scsw_tm_is_valid_ectl(union scsw *scsw);
-int scsw_tm_is_valid_pno(union scsw *scsw);
-int scsw_tm_is_valid_fctl(union scsw *scsw);
-int scsw_tm_is_valid_actl(union scsw *scsw);
-int scsw_tm_is_valid_stctl(union scsw *scsw);
-int scsw_tm_is_valid_dstat(union scsw *scsw);
-int scsw_tm_is_valid_cstat(union scsw *scsw);
-int scsw_tm_is_valid_fcxs(union scsw *scsw);
-int scsw_tm_is_valid_schxs(union scsw *scsw);
-int scsw_tm_is_solicited(union scsw *scsw);
-#define SCSW_FCTL_CLEAR_FUNC     0x1
-#define SCSW_FCTL_HALT_FUNC      0x2
-#define SCSW_FCTL_START_FUNC     0x4
-#define SCSW_ACTL_SUSPENDED      0x1
-#define SCSW_ACTL_DEVACT         0x2
-#define SCSW_ACTL_SCHACT         0x4
-#define SCSW_ACTL_CLEAR_PEND     0x8
-#define SCSW_ACTL_HALT_PEND      0x10
-#define SCSW_ACTL_START_PEND     0x20
-#define SCSW_ACTL_RESUME_PEND    0x40
-#define SCSW_STCTL_STATUS_PEND   0x1
-#define SCSW_STCTL_SEC_STATUS    0x2
-#define SCSW_STCTL_PRIM_STATUS   0x4
-#define SCSW_STCTL_INTER_STATUS  0x8
-#define SCSW_STCTL_ALERT_STATUS  0x10
-#define DEV_STAT_ATTENTION       0x80
-#define DEV_STAT_STAT_MOD        0x40
-#define DEV_STAT_CU_END          0x20
-#define DEV_STAT_BUSY            0x10
-#define DEV_STAT_CHN_END         0x08
-#define DEV_STAT_DEV_END         0x04
-#define DEV_STAT_UNIT_CHECK      0x02
-#define DEV_STAT_UNIT_EXCEP      0x01
-#define SCHN_STAT_PCI            0x80
-#define SCHN_STAT_INCORR_LEN     0x40
-#define SCHN_STAT_PROG_CHECK     0x20
-#define SCHN_STAT_PROT_CHECK     0x10
-#define SCHN_STAT_CHN_DATA_CHK   0x08
-#define SCHN_STAT_CHN_CTRL_CHK   0x04
-#define SCHN_STAT_INTF_CTRL_CHK  0x02
-#define SCHN_STAT_CHAIN_CHECK    0x01
-/*
- * architectured values for first sense byte
- */
-#define SNS0_CMD_REJECT         0x80
-#define SNS_CMD_REJECT          SNS0_CMD_REJEC
-#define SNS0_INTERVENTION_REQ   0x40
-#define SNS0_BUS_OUT_CHECK      0x20
-#define SNS0_EQUIPMENT_CHECK    0x10
-#define SNS0_DATA_CHECK         0x08
-#define SNS0_OVERRUN            0x04
-#define SNS0_INCOMPL_DOMAIN     0x01
-/*
- * architectured values for second sense byte
- */
-#define SNS1_PERM_ERR           0x80
-#define SNS1_INV_TRACK_FORMAT   0x40
-#define SNS1_EOC                0x20
-#define SNS1_MESSAGE_TO_OPER    0x10
-#define SNS1_NO_REC_FOUND       0x08
-#define SNS1_FILE_PROTECTED     0x04
-#define SNS1_WRITE_INHIBITED    0x02
-#define SNS1_INPRECISE_END      0x01
-/*
- * architectured values for third sense byte
- */
-#define SNS2_REQ_INH_WRITE      0x80
-#define SNS2_CORRECTABLE        0x40
-#define SNS2_FIRST_LOG_ERR      0x20
-#define SNS2_ENV_DATA_PRESENT   0x10
-#define SNS2_INPRECISE_END      0x04
 /**
 * struct ccw1 - channel command word
diff --git a/arch/s390/include/asm/cpu.h b/arch/s390/include/asm/cpu.h
new file mode 100644
index 000000000000..471234b90574
--- /dev/null
+++ b/arch/s390/include/asm/cpu.h
@@ -0,0 +1,26 @@
+/*
+ *    Copyright IBM Corp. 2000,2009
+ *    Author(s): Hartmut Penner <hp@de.ibm.com>,
+ *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
+ *               Christian Ehrhardt <ehrhardt@de.ibm.com>,
+ */
+#ifndef _ASM_S390_CPU_H
+#define _ASM_S390_CPU_H
+#define MAX_CPU_ADDRESS 255
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+struct cpuid
+{
+        unsigned int version :  8;
+        unsigned int ident   : 24;
+        unsigned int machine : 16;
+        unsigned int unused  : 16;
+} __packed;
+#endif /* __ASSEMBLY__ */
+#endif /* _ASM_S390_CPU_H */
diff --git a/arch/s390/include/asm/cpuid.h b/arch/s390/include/asm/cpuid.h
deleted file mode 100644
index 07836a2e5222..000000000000
--- a/arch/s390/include/asm/cpuid.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- *    Copyright IBM Corp. 2000,2009
- *    Author(s): Hartmut Penner <hp@de.ibm.com>,
- *               Martin Schwidefsky <schwidefsky@de.ibm.com>
- *               Christian Ehrhardt <ehrhardt@de.ibm.com>
- */
-#ifndef _ASM_S390_CPUID_H_
-#define _ASM_S390_CPUID_H_
-/*
- *  CPU type and hardware bug flags. Kept separately for each CPU.
- *  Members of this structure are referenced in head.S, so think twice
- *  before touching them. [mj]
- */
-typedef struct
-{
-        unsigned int version :  8;
-        unsigned int ident   : 24;
-        unsigned int machine : 16;
-        unsigned int unused  : 16;
-} __attribute__ ((packed)) cpuid_t;
-#endif /* _ASM_S390_CPUID_H_ */
diff --git a/arch/s390/include/asm/debug.h b/arch/s390/include/asm/debug.h
index 31ed5686a968..18124b75a7ab 100644
--- a/arch/s390/include/asm/debug.h
+++ b/arch/s390/include/asm/debug.h
@@ -167,6 +167,10 @@ debug_text_event(debug_info_t* id, int level, const char* txt)
        return debug_event_common(id,level,txt,strlen(txt));
 }
+/*
+ * IMPORTANT: Use "%s" in sprintf format strings with care! Only pointers are
+ * stored in the s390dbf. See Documentation/s390/s390dbf.txt for more details!
+ */
 extern debug_entry_t *
 debug_sprintf_event(debug_info_t* id,int level,char *string,...)
        __attribute__ ((format(printf, 3, 4)));
@@ -206,7 +210,10 @@ debug_text_exception(debug_info_t* id, int level, const char* txt)
        return debug_exception_common(id,level,txt,strlen(txt));
 }
+/*
+ * IMPORTANT: Use "%s" in sprintf format strings with care! Only pointers are
+ * stored in the s390dbf. See Documentation/s390/s390dbf.txt for more details!
+ */
 extern debug_entry_t *
 debug_sprintf_exception(debug_info_t* id,int level,char *string,...)
        __attribute__ ((format(printf, 3, 4)));
diff --git a/arch/s390/include/asm/hardirq.h b/arch/s390/include/asm/hardirq.h
index 89ec7056da28..498bc3892385 100644
--- a/arch/s390/include/asm/hardirq.h
+++ b/arch/s390/include/asm/hardirq.h
@@ -18,13 +18,6 @@
 #include <linux/interrupt.h>
 #include <asm/lowcore.h>
-/* irq_cpustat_t is unused currently, but could be converted
- * into a percpu variable instead of storing softirq_pending
- * on the lowcore */
-typedef struct {
-        unsigned int __softirq_pending;
-} irq_cpustat_t;
 #define local_softirq_pending() (S390_lowcore.softirq_pending)
 #define __ARCH_IRQ_STAT
diff --git a/arch/s390/include/asm/ipl.h b/arch/s390/include/asm/ipl.h
index 1171e6d144a3..5e95d95450b3 100644
--- a/arch/s390/include/asm/ipl.h
+++ b/arch/s390/include/asm/ipl.h
@@ -57,6 +57,8 @@ struct ipl_block_fcp {
 } __attribute__((packed));
 #define DIAG308_VMPARM_SIZE     64
+#define DIAG308_SCPDATA_SIZE    (PAGE_SIZE - (sizeof(struct ipl_list_hdr) + \
+                                 offsetof(struct ipl_block_fcp, scp_data)))
 struct ipl_block_ccw {
        u8  load_parm[8];
@@ -91,7 +93,8 @@ extern void do_halt(void);
 extern void do_poff(void);
 extern void ipl_save_parameters(void);
 extern void ipl_update_parameters(void);
-extern void get_ipl_vmparm(char *);
+extern size_t append_ipl_vmparm(char *, size_t);
+extern size_t append_ipl_scpdata(char *, size_t);
 enum {
        IPL_DEVNO_VALID         = 1,
diff --git a/arch/s390/include/asm/kvm.h b/arch/s390/include/asm/kvm.h
index 0b2f829f6d50..3dfcaeb5d7f4 100644
--- a/arch/s390/include/asm/kvm.h
+++ b/arch/s390/include/asm/kvm.h
@@ -15,15 +15,6 @@
 */
 #include <linux/types.h>
-/* for KVM_GET_IRQCHIP and KVM_SET_IRQCHIP */
-struct kvm_pic_state {
-        /* no PIC for s390 */
-};
-struct kvm_ioapic_state {
-        /* no IOAPIC for s390 */
-};
 /* for KVM_GET_REGS and KVM_SET_REGS */
 struct kvm_regs {
        /* general purpose regs for s390 */
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h
index 1cd02f6073a0..27605b62b980 100644
--- a/arch/s390/include/asm/kvm_host.h
+++ b/arch/s390/include/asm/kvm_host.h
@@ -1,7 +1,7 @@
 /*
 * asm-s390/kvm_host.h - definition for kernel virtual machines on s390
 *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008,2009
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
@@ -17,7 +17,7 @@
 #include <linux/interrupt.h>
 #include <linux/kvm_host.h>
 #include <asm/debug.h>
-#include <asm/cpuid.h>
+#include <asm/cpu.h>
 #define KVM_MAX_VCPUS 64
 #define KVM_MEMORY_SLOTS 32
@@ -40,7 +40,11 @@ struct sca_block {
        struct sca_entry cpu[64];
 } __attribute__((packed));
-#define KVM_PAGES_PER_HPAGE 256
+#define KVM_NR_PAGE_SIZES 2
+#define KVM_HPAGE_SHIFT(x) (PAGE_SHIFT + ((x) - 1) * 8)
+#define KVM_HPAGE_SIZE(x) (1UL << KVM_HPAGE_SHIFT(x))
+#define KVM_HPAGE_MASK(x)       (~(KVM_HPAGE_SIZE(x) - 1))
+#define KVM_PAGES_PER_HPAGE(x)  (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
 #define CPUSTAT_HOST       0x80000000
 #define CPUSTAT_WAIT       0x10000000
@@ -182,8 +186,9 @@ struct kvm_s390_interrupt_info {
 };
 /* for local_interrupt.action_flags */
-#define ACTION_STORE_ON_STOP 1
+#define ACTION_STORE_ON_STOP            (1<<0)
-#define ACTION_STOP_ON_STOP  2
+#define ACTION_STOP_ON_STOP             (1<<1)
+#define ACTION_RELOADVCPU_ON_STOP       (1<<2)
 struct kvm_s390_local_interrupt {
        spinlock_t lock;
@@ -217,8 +222,8 @@ struct kvm_vcpu_arch {
        struct hrtimer    ckc_timer;
        struct tasklet_struct tasklet;
        union  {
-                cpuid_t   cpu_id;
+                struct cpuid    cpu_id;
-                u64       stidp_data;
+                u64             stidp_data;
        };
 };
@@ -227,8 +232,6 @@ struct kvm_vm_stat {
 };
 struct kvm_arch{
-        unsigned long guest_origin;
-        unsigned long guest_memsize;
        struct sca_block *sca;
        debug_info_t *dbf;
        struct kvm_s390_float_interrupt float_int;
diff --git a/arch/s390/include/asm/kvm_para.h b/arch/s390/include/asm/kvm_para.h
index 2c503796b619..6964db226f83 100644
--- a/arch/s390/include/asm/kvm_para.h
+++ b/arch/s390/include/asm/kvm_para.h
@@ -13,6 +13,8 @@
 #ifndef __S390_KVM_PARA_H
 #define __S390_KVM_PARA_H
+#ifdef __KERNEL__
 /*
 * Hypercalls for KVM on s390. The calling convention is similar to the
 * s390 ABI, so we use R2-R6 for parameters 1-5. In addition we use R1
@@ -147,4 +149,6 @@ static inline unsigned int kvm_arch_para_features(void)
        return 0;
 }
+#endif
 #endif /* __S390_KVM_PARA_H */
diff --git a/arch/s390/include/asm/kvm_virtio.h b/arch/s390/include/asm/kvm_virtio.h
index 0503936f101f..acdfdff26611 100644
--- a/arch/s390/include/asm/kvm_virtio.h
+++ b/arch/s390/include/asm/kvm_virtio.h
@@ -54,14 +54,4 @@ struct kvm_vqconfig {
 * This is pagesize for historical reasons. */
 #define KVM_S390_VIRTIO_RING_ALIGN      4096
-#ifdef __KERNEL__
-/* early virtio console setup */
-#ifdef CONFIG_S390_GUEST
-extern void s390_virtio_console_init(void);
-#else
-static inline void s390_virtio_console_init(void)
-{
-}
-#endif /* CONFIG_VIRTIO_CONSOLE */
-#endif /* __KERNEL__ */
 #endif
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index 5046ad6b7a63..6bc9426a6fbf 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -132,7 +132,7 @@
 #ifndef __ASSEMBLY__
-#include <asm/cpuid.h>
+#include <asm/cpu.h>
 #include <asm/ptrace.h>
 #include <linux/types.h>
@@ -275,7 +275,7 @@ struct _lowcore
        __u32   user_exec_asce;                 /* 0x02ac */
        /* SMP info area */
-        cpuid_t cpu_id;                         /* 0x02b0 */
+        struct cpuid cpu_id;                    /* 0x02b0 */
        __u32   cpu_nr;                         /* 0x02b8 */
        __u32   softirq_pending;                /* 0x02bc */
        __u32   percpu_offset;                  /* 0x02c0 */
@@ -380,7 +380,7 @@ struct _lowcore
        __u64   user_exec_asce;                 /* 0x0318 */
        /* SMP info area */
-        cpuid_t cpu_id;                         /* 0x0320 */
+        struct cpuid cpu_id;                    /* 0x0320 */
        __u32   cpu_nr;                         /* 0x0328 */
        __u32   softirq_pending;                /* 0x032c */
        __u64   percpu_offset;                  /* 0x0330 */
diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h
index 3b59216e6284..03be99919d62 100644
--- a/arch/s390/include/asm/mmu.h
+++ b/arch/s390/include/asm/mmu.h
@@ -2,6 +2,7 @@
 #define __MMU_H
 typedef struct {
+        spinlock_t list_lock;
        struct list_head crst_list;
        struct list_head pgtable_list;
        unsigned long asce_bits;
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
index 3e3594d01f83..5e9daf5d7f22 100644
--- a/arch/s390/include/asm/page.h
+++ b/arch/s390/include/asm/page.h
@@ -125,8 +125,6 @@ page_get_storage_key(unsigned long addr)
        return skey;
 }
-#ifdef CONFIG_PAGE_STATES
 struct page;
 void arch_free_page(struct page *page, int order);
 void arch_alloc_page(struct page *page, int order);
@@ -134,8 +132,6 @@ void arch_alloc_page(struct page *page, int order);
 #define HAVE_ARCH_FREE_PAGE
 #define HAVE_ARCH_ALLOC_PAGE
-#endif
 #endif /* !__ASSEMBLY__ */
 #define __PAGE_OFFSET           0x0UL
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
index b2658b9220fe..ddad5903341c 100644
--- a/arch/s390/include/asm/pgalloc.h
+++ b/arch/s390/include/asm/pgalloc.h
@@ -140,6 +140,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
+        spin_lock_init(&mm->context.list_lock);
        INIT_LIST_HEAD(&mm->context.crst_list);
        INIT_LIST_HEAD(&mm->context.pgtable_list);
        return (pgd_t *) crst_table_alloc(mm, s390_noexec);
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index c139fa7b8e89..cf8eed3fa779 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -14,7 +14,7 @@
 #define __ASM_S390_PROCESSOR_H
 #include <linux/linkage.h>
-#include <asm/cpuid.h>
+#include <asm/cpu.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include <asm/setup.h>
@@ -26,7 +26,7 @@
 */
 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
-static inline void get_cpu_id(cpuid_t *ptr)
+static inline void get_cpu_id(struct cpuid *ptr)
 {
        asm volatile("stidp 0(%1)" : "=m" (*ptr) : "a" (ptr));
 }
diff --git a/arch/s390/include/asm/scatterlist.h b/arch/s390/include/asm/scatterlist.h
index 29ec8e28c8df..35d786fe93ae 100644
--- a/arch/s390/include/asm/scatterlist.h
+++ b/arch/s390/include/asm/scatterlist.h
@@ -1,19 +1 @@
-#ifndef _ASMS390_SCATTERLIST_H
+#include <asm-generic/scatterlist.h>
-#define _ASMS390_SCATTERLIST_H
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-    unsigned long sg_magic;
-#endif
-    unsigned long page_link;
-    unsigned int offset;
-    unsigned int length;
-};
-#ifdef __s390x__
-#define ISA_DMA_THRESHOLD (0xffffffffffffffffUL)
-#else
-#define ISA_DMA_THRESHOLD (0xffffffffUL)
-#endif
-#endif /* _ASMS390X_SCATTERLIST_H */
diff --git a/arch/s390/include/asm/scsw.h b/arch/s390/include/asm/scsw.h
new file mode 100644
index 000000000000..de389cb54d28
--- /dev/null
+++ b/arch/s390/include/asm/scsw.h
@@ -0,0 +1,956 @@
+/*
+ *  Helper functions for scsw access.
+ *
+ *    Copyright IBM Corp. 2008,2009
+ *    Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
+ */
+#ifndef _ASM_S390_SCSW_H_
+#define _ASM_S390_SCSW_H_
+#include <linux/types.h>
+#include <asm/chsc.h>
+#include <asm/cio.h>
+/**
+ * struct cmd_scsw - command-mode subchannel status word
+ * @key: subchannel key
+ * @sctl: suspend control
+ * @eswf: esw format
+ * @cc: deferred condition code
+ * @fmt: format
+ * @pfch: prefetch
+ * @isic: initial-status interruption control
+ * @alcc: address-limit checking control
+ * @ssi: suppress-suspended interruption
+ * @zcc: zero condition code
+ * @ectl: extended control
+ * @pno: path not operational
+ * @res: reserved
+ * @fctl: function control
+ * @actl: activity control
+ * @stctl: status control
+ * @cpa: channel program address
+ * @dstat: device status
+ * @cstat: subchannel status
+ * @count: residual count
+ */
+struct cmd_scsw {
+        __u32 key  : 4;
+        __u32 sctl : 1;
+        __u32 eswf : 1;
+        __u32 cc   : 2;
+        __u32 fmt  : 1;
+        __u32 pfch : 1;
+        __u32 isic : 1;
+        __u32 alcc : 1;
+        __u32 ssi  : 1;
+        __u32 zcc  : 1;
+        __u32 ectl : 1;
+        __u32 pno  : 1;
+        __u32 res  : 1;
+        __u32 fctl : 3;
+        __u32 actl : 7;
+        __u32 stctl : 5;
+        __u32 cpa;
+        __u32 dstat : 8;
+        __u32 cstat : 8;
+        __u32 count : 16;
+} __attribute__ ((packed));
+/**
+ * struct tm_scsw - transport-mode subchannel status word
+ * @key: subchannel key
+ * @eswf: esw format
+ * @cc: deferred condition code
+ * @fmt: format
+ * @x: IRB-format control
+ * @q: interrogate-complete
+ * @ectl: extended control
+ * @pno: path not operational
+ * @fctl: function control
+ * @actl: activity control
+ * @stctl: status control
+ * @tcw: TCW address
+ * @dstat: device status
+ * @cstat: subchannel status
+ * @fcxs: FCX status
+ * @schxs: subchannel-extended status
+ */
+struct tm_scsw {
+        u32 key:4;
+        u32 :1;
+        u32 eswf:1;
+        u32 cc:2;
+        u32 fmt:3;
+        u32 x:1;
+        u32 q:1;
+        u32 :1;
+        u32 ectl:1;
+        u32 pno:1;
+        u32 :1;
+        u32 fctl:3;
+        u32 actl:7;
+        u32 stctl:5;
+        u32 tcw;
+        u32 dstat:8;
+        u32 cstat:8;
+        u32 fcxs:8;
+        u32 schxs:8;
+} __attribute__ ((packed));
+/**
+ * union scsw - subchannel status word
+ * @cmd: command-mode SCSW
+ * @tm: transport-mode SCSW
+ */
+union scsw {
+        struct cmd_scsw cmd;
+        struct tm_scsw tm;
+} __attribute__ ((packed));
+#define SCSW_FCTL_CLEAR_FUNC     0x1
+#define SCSW_FCTL_HALT_FUNC      0x2
+#define SCSW_FCTL_START_FUNC     0x4
+#define SCSW_ACTL_SUSPENDED      0x1
+#define SCSW_ACTL_DEVACT         0x2
+#define SCSW_ACTL_SCHACT         0x4
+#define SCSW_ACTL_CLEAR_PEND     0x8
+#define SCSW_ACTL_HALT_PEND      0x10
+#define SCSW_ACTL_START_PEND     0x20
+#define SCSW_ACTL_RESUME_PEND    0x40
+#define SCSW_STCTL_STATUS_PEND   0x1
+#define SCSW_STCTL_SEC_STATUS    0x2
+#define SCSW_STCTL_PRIM_STATUS   0x4
+#define SCSW_STCTL_INTER_STATUS  0x8
+#define SCSW_STCTL_ALERT_STATUS  0x10
+#define DEV_STAT_ATTENTION       0x80
+#define DEV_STAT_STAT_MOD        0x40
+#define DEV_STAT_CU_END          0x20
+#define DEV_STAT_BUSY            0x10
+#define DEV_STAT_CHN_END         0x08
+#define DEV_STAT_DEV_END         0x04
+#define DEV_STAT_UNIT_CHECK      0x02
+#define DEV_STAT_UNIT_EXCEP      0x01
+#define SCHN_STAT_PCI            0x80
+#define SCHN_STAT_INCORR_LEN     0x40
+#define SCHN_STAT_PROG_CHECK     0x20
+#define SCHN_STAT_PROT_CHECK     0x10
+#define SCHN_STAT_CHN_DATA_CHK   0x08
+#define SCHN_STAT_CHN_CTRL_CHK   0x04
+#define SCHN_STAT_INTF_CTRL_CHK  0x02
+#define SCHN_STAT_CHAIN_CHECK    0x01
+/*
+ * architectured values for first sense byte
+ */
+#define SNS0_CMD_REJECT         0x80
+#define SNS_CMD_REJECT          SNS0_CMD_REJEC
+#define SNS0_INTERVENTION_REQ   0x40
+#define SNS0_BUS_OUT_CHECK      0x20
+#define SNS0_EQUIPMENT_CHECK    0x10
+#define SNS0_DATA_CHECK         0x08
+#define SNS0_OVERRUN            0x04
+#define SNS0_INCOMPL_DOMAIN     0x01
+/*
+ * architectured values for second sense byte
+ */
+#define SNS1_PERM_ERR           0x80
+#define SNS1_INV_TRACK_FORMAT   0x40
+#define SNS1_EOC                0x20
+#define SNS1_MESSAGE_TO_OPER    0x10
+#define SNS1_NO_REC_FOUND       0x08
+#define SNS1_FILE_PROTECTED     0x04
+#define SNS1_WRITE_INHIBITED    0x02
+#define SNS1_INPRECISE_END      0x01
+/*
+ * architectured values for third sense byte
+ */
+#define SNS2_REQ_INH_WRITE      0x80
+#define SNS2_CORRECTABLE        0x40
+#define SNS2_FIRST_LOG_ERR      0x20
+#define SNS2_ENV_DATA_PRESENT   0x10
+#define SNS2_INPRECISE_END      0x04
+/**
+ * scsw_is_tm - check for transport mode scsw
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the specified scsw is a transport mode scsw, zero
+ * otherwise.
+ */
+static inline int scsw_is_tm(union scsw *scsw)
+{
+        return css_general_characteristics.fcx && (scsw->tm.x == 1);
+}
+/**
+ * scsw_key - return scsw key field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the key field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_key(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.key;
+        else
+                return scsw->cmd.key;
+}
+/**
+ * scsw_eswf - return scsw eswf field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the eswf field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_eswf(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.eswf;
+        else
+                return scsw->cmd.eswf;
+}
+/**
+ * scsw_cc - return scsw cc field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the cc field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_cc(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.cc;
+        else
+                return scsw->cmd.cc;
+}
+/**
+ * scsw_ectl - return scsw ectl field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the ectl field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_ectl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.ectl;
+        else
+                return scsw->cmd.ectl;
+}
+/**
+ * scsw_pno - return scsw pno field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the pno field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_pno(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.pno;
+        else
+                return scsw->cmd.pno;
+}
+/**
+ * scsw_fctl - return scsw fctl field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the fctl field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_fctl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.fctl;
+        else
+                return scsw->cmd.fctl;
+}
+/**
+ * scsw_actl - return scsw actl field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the actl field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_actl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.actl;
+        else
+                return scsw->cmd.actl;
+}
+/**
+ * scsw_stctl - return scsw stctl field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the stctl field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_stctl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.stctl;
+        else
+                return scsw->cmd.stctl;
+}
+/**
+ * scsw_dstat - return scsw dstat field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the dstat field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_dstat(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.dstat;
+        else
+                return scsw->cmd.dstat;
+}
+/**
+ * scsw_cstat - return scsw cstat field
+ * @scsw: pointer to scsw
+ *
+ * Return the value of the cstat field of the specified scsw, regardless of
+ * whether it is a transport mode or command mode scsw.
+ */
+static inline u32 scsw_cstat(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw->tm.cstat;
+        else
+                return scsw->cmd.cstat;
+}
+/**
+ * scsw_cmd_is_valid_key - check key field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the key field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_key(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_cmd_is_valid_sctl - check fctl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the fctl field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_sctl(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_cmd_is_valid_eswf - check eswf field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the eswf field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_eswf(union scsw *scsw)
+{
+        return (scsw->cmd.stctl & SCSW_STCTL_STATUS_PEND);
+}
+/**
+ * scsw_cmd_is_valid_cc - check cc field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the cc field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_cc(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC) &&
+               (scsw->cmd.stctl & SCSW_STCTL_STATUS_PEND);
+}
+/**
+ * scsw_cmd_is_valid_fmt - check fmt field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the fmt field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_fmt(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_cmd_is_valid_pfch - check pfch field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the pfch field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_pfch(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_cmd_is_valid_isic - check isic field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the isic field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_isic(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_cmd_is_valid_alcc - check alcc field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the alcc field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_alcc(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_cmd_is_valid_ssi - check ssi field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the ssi field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_ssi(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_cmd_is_valid_zcc - check zcc field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the zcc field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_zcc(union scsw *scsw)
+{
+        return (scsw->cmd.fctl & SCSW_FCTL_START_FUNC) &&
+               (scsw->cmd.stctl & SCSW_STCTL_INTER_STATUS);
+}
+/**
+ * scsw_cmd_is_valid_ectl - check ectl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the ectl field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_ectl(union scsw *scsw)
+{
+        return (scsw->cmd.stctl & SCSW_STCTL_STATUS_PEND) &&
+               !(scsw->cmd.stctl & SCSW_STCTL_INTER_STATUS) &&
+               (scsw->cmd.stctl & SCSW_STCTL_ALERT_STATUS);
+}
+/**
+ * scsw_cmd_is_valid_pno - check pno field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the pno field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_pno(union scsw *scsw)
+{
+        return (scsw->cmd.fctl != 0) &&
+               (scsw->cmd.stctl & SCSW_STCTL_STATUS_PEND) &&
+               (!(scsw->cmd.stctl & SCSW_STCTL_INTER_STATUS) ||
+                 ((scsw->cmd.stctl & SCSW_STCTL_INTER_STATUS) &&
+                  (scsw->cmd.actl & SCSW_ACTL_SUSPENDED)));
+}
+/**
+ * scsw_cmd_is_valid_fctl - check fctl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the fctl field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_fctl(union scsw *scsw)
+{
+        /* Only valid if pmcw.dnv == 1*/
+        return 1;
+}
+/**
+ * scsw_cmd_is_valid_actl - check actl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the actl field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_actl(union scsw *scsw)
+{
+        /* Only valid if pmcw.dnv == 1*/
+        return 1;
+}
+/**
+ * scsw_cmd_is_valid_stctl - check stctl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the stctl field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_stctl(union scsw *scsw)
+{
+        /* Only valid if pmcw.dnv == 1*/
+        return 1;
+}
+/**
+ * scsw_cmd_is_valid_dstat - check dstat field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the dstat field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_dstat(union scsw *scsw)
+{
+        return (scsw->cmd.stctl & SCSW_STCTL_STATUS_PEND) &&
+               (scsw->cmd.cc != 3);
+}
+/**
+ * scsw_cmd_is_valid_cstat - check cstat field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the cstat field of the specified command mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_cmd_is_valid_cstat(union scsw *scsw)
+{
+        return (scsw->cmd.stctl & SCSW_STCTL_STATUS_PEND) &&
+               (scsw->cmd.cc != 3);
+}
+/**
+ * scsw_tm_is_valid_key - check key field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the key field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_key(union scsw *scsw)
+{
+        return (scsw->tm.fctl & SCSW_FCTL_START_FUNC);
+}
+/**
+ * scsw_tm_is_valid_eswf - check eswf field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the eswf field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_eswf(union scsw *scsw)
+{
+        return (scsw->tm.stctl & SCSW_STCTL_STATUS_PEND);
+}
+/**
+ * scsw_tm_is_valid_cc - check cc field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the cc field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_cc(union scsw *scsw)
+{
+        return (scsw->tm.fctl & SCSW_FCTL_START_FUNC) &&
+               (scsw->tm.stctl & SCSW_STCTL_STATUS_PEND);
+}
+/**
+ * scsw_tm_is_valid_fmt - check fmt field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the fmt field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_fmt(union scsw *scsw)
+{
+        return 1;
+}
+/**
+ * scsw_tm_is_valid_x - check x field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the x field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_x(union scsw *scsw)
+{
+        return 1;
+}
+/**
+ * scsw_tm_is_valid_q - check q field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the q field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_q(union scsw *scsw)
+{
+        return 1;
+}
+/**
+ * scsw_tm_is_valid_ectl - check ectl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the ectl field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_ectl(union scsw *scsw)
+{
+        return (scsw->tm.stctl & SCSW_STCTL_STATUS_PEND) &&
+               !(scsw->tm.stctl & SCSW_STCTL_INTER_STATUS) &&
+               (scsw->tm.stctl & SCSW_STCTL_ALERT_STATUS);
+}
+/**
+ * scsw_tm_is_valid_pno - check pno field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the pno field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_pno(union scsw *scsw)
+{
+        return (scsw->tm.fctl != 0) &&
+               (scsw->tm.stctl & SCSW_STCTL_STATUS_PEND) &&
+               (!(scsw->tm.stctl & SCSW_STCTL_INTER_STATUS) ||
+                 ((scsw->tm.stctl & SCSW_STCTL_INTER_STATUS) &&
+                  (scsw->tm.actl & SCSW_ACTL_SUSPENDED)));
+}
+/**
+ * scsw_tm_is_valid_fctl - check fctl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the fctl field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_fctl(union scsw *scsw)
+{
+        /* Only valid if pmcw.dnv == 1*/
+        return 1;
+}
+/**
+ * scsw_tm_is_valid_actl - check actl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the actl field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_actl(union scsw *scsw)
+{
+        /* Only valid if pmcw.dnv == 1*/
+        return 1;
+}
+/**
+ * scsw_tm_is_valid_stctl - check stctl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the stctl field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_stctl(union scsw *scsw)
+{
+        /* Only valid if pmcw.dnv == 1*/
+        return 1;
+}
+/**
+ * scsw_tm_is_valid_dstat - check dstat field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the dstat field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_dstat(union scsw *scsw)
+{
+        return (scsw->tm.stctl & SCSW_STCTL_STATUS_PEND) &&
+               (scsw->tm.cc != 3);
+}
+/**
+ * scsw_tm_is_valid_cstat - check cstat field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the cstat field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_cstat(union scsw *scsw)
+{
+        return (scsw->tm.stctl & SCSW_STCTL_STATUS_PEND) &&
+               (scsw->tm.cc != 3);
+}
+/**
+ * scsw_tm_is_valid_fcxs - check fcxs field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the fcxs field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_fcxs(union scsw *scsw)
+{
+        return 1;
+}
+/**
+ * scsw_tm_is_valid_schxs - check schxs field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the schxs field of the specified transport mode scsw is
+ * valid, zero otherwise.
+ */
+static inline int scsw_tm_is_valid_schxs(union scsw *scsw)
+{
+        return (scsw->tm.cstat & (SCHN_STAT_PROG_CHECK |
+                                  SCHN_STAT_INTF_CTRL_CHK |
+                                  SCHN_STAT_PROT_CHECK |
+                                  SCHN_STAT_CHN_DATA_CHK));
+}
+/**
+ * scsw_is_valid_actl - check actl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the actl field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_actl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_actl(scsw);
+        else
+                return scsw_cmd_is_valid_actl(scsw);
+}
+/**
+ * scsw_is_valid_cc - check cc field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the cc field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_cc(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_cc(scsw);
+        else
+                return scsw_cmd_is_valid_cc(scsw);
+}
+/**
+ * scsw_is_valid_cstat - check cstat field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the cstat field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_cstat(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_cstat(scsw);
+        else
+                return scsw_cmd_is_valid_cstat(scsw);
+}
+/**
+ * scsw_is_valid_dstat - check dstat field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the dstat field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_dstat(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_dstat(scsw);
+        else
+                return scsw_cmd_is_valid_dstat(scsw);
+}
+/**
+ * scsw_is_valid_ectl - check ectl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the ectl field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_ectl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_ectl(scsw);
+        else
+                return scsw_cmd_is_valid_ectl(scsw);
+}
+/**
+ * scsw_is_valid_eswf - check eswf field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the eswf field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_eswf(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_eswf(scsw);
+        else
+                return scsw_cmd_is_valid_eswf(scsw);
+}
+/**
+ * scsw_is_valid_fctl - check fctl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the fctl field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_fctl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_fctl(scsw);
+        else
+                return scsw_cmd_is_valid_fctl(scsw);
+}
+/**
+ * scsw_is_valid_key - check key field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the key field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_key(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_key(scsw);
+        else
+                return scsw_cmd_is_valid_key(scsw);
+}
+/**
+ * scsw_is_valid_pno - check pno field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the pno field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_pno(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_pno(scsw);
+        else
+                return scsw_cmd_is_valid_pno(scsw);
+}
+/**
+ * scsw_is_valid_stctl - check stctl field validity
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the stctl field of the specified scsw is valid,
+ * regardless of whether it is a transport mode or command mode scsw.
+ * Return zero if the field does not contain a valid value.
+ */
+static inline int scsw_is_valid_stctl(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_valid_stctl(scsw);
+        else
+                return scsw_cmd_is_valid_stctl(scsw);
+}
+/**
+ * scsw_cmd_is_solicited - check for solicited scsw
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the command mode scsw indicates that the associated
+ * status condition is solicited, zero if it is unsolicited.
+ */
+static inline int scsw_cmd_is_solicited(union scsw *scsw)
+{
+        return (scsw->cmd.cc != 0) || (scsw->cmd.stctl !=
+                (SCSW_STCTL_STATUS_PEND | SCSW_STCTL_ALERT_STATUS));
+}
+/**
+ * scsw_tm_is_solicited - check for solicited scsw
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the transport mode scsw indicates that the associated
+ * status condition is solicited, zero if it is unsolicited.
+ */
+static inline int scsw_tm_is_solicited(union scsw *scsw)
+{
+        return (scsw->tm.cc != 0) || (scsw->tm.stctl !=
+                (SCSW_STCTL_STATUS_PEND | SCSW_STCTL_ALERT_STATUS));
+}
+/**
+ * scsw_is_solicited - check for solicited scsw
+ * @scsw: pointer to scsw
+ *
+ * Return non-zero if the transport or command mode scsw indicates that the
+ * associated status condition is solicited, zero if it is unsolicited.
+ */
+static inline int scsw_is_solicited(union scsw *scsw)
+{
+        if (scsw_is_tm(scsw))
+                return scsw_tm_is_solicited(scsw);
+        else
+                return scsw_cmd_is_solicited(scsw);
+}
+#endif /* _ASM_S390_SCSW_H_ */
diff --git a/arch/s390/include/asm/setup.h b/arch/s390/include/asm/setup.h
index 38b0fc221ed7..e37478e87286 100644
--- a/arch/s390/include/asm/setup.h
+++ b/arch/s390/include/asm/setup.h
@@ -8,7 +8,7 @@
 #ifndef _ASM_S390_SETUP_H
 #define _ASM_S390_SETUP_H
-#define COMMAND_LINE_SIZE       1024
+#define COMMAND_LINE_SIZE       4096
 #define ARCH_COMMAND_LINE_SIZE  896
diff --git a/arch/s390/include/asm/smp.h b/arch/s390/include/asm/smp.h
index 72137bc907ac..c991fe6473c9 100644
--- a/arch/s390/include/asm/smp.h
+++ b/arch/s390/include/asm/smp.h
@@ -51,32 +51,7 @@ extern void machine_power_off_smp(void);
 #define PROC_CHANGE_PENALTY     20              /* Schedule penalty */
 #define raw_smp_processor_id()  (S390_lowcore.cpu_nr)
+#define cpu_logical_map(cpu)    (cpu)
-/*
- * returns 1 if cpu is in stopped/check stopped state or not operational
- * returns 0 otherwise
- */
-static inline int
-smp_cpu_not_running(int cpu)
-{
-        __u32 status;
-        switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
-        case sigp_order_code_accepted:
-        case sigp_status_stored:
-                /* Check for stopped and check stop state */
-                if (status & 0x50)
-                        return 1;
-                break;
-        case sigp_not_operational:
-                return 1;
-        default:
-                break;
-        }
-        return 0;
-}
-#define cpu_logical_map(cpu) (cpu)
 extern int __cpu_disable (void);
 extern void __cpu_die (unsigned int cpu);
@@ -91,11 +66,6 @@ extern void arch_send_call_function_ipi(cpumask_t mask);
 #endif
-#ifndef CONFIG_SMP
-#define hard_smp_processor_id()         0
-#define smp_cpu_not_running(cpu)        1
-#endif
 #ifdef CONFIG_HOTPLUG_CPU
 extern int smp_rescan_cpus(void);
 #else
diff --git a/arch/s390/include/asm/socket.h b/arch/s390/include/asm/socket.h
index 02330c50241b..e42df89a0b85 100644
--- a/arch/s390/include/asm/socket.h
+++ b/arch/s390/include/asm/socket.h
@@ -65,4 +65,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif /* _ASM_SOCKET_H */
diff --git a/arch/s390/include/asm/spinlock.h b/arch/s390/include/asm/spinlock.h
index c9af0d19c7ab..41ce6861174e 100644
--- a/arch/s390/include/asm/spinlock.h
+++ b/arch/s390/include/asm/spinlock.h
@@ -191,4 +191,33 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
 #define _raw_read_relax(lock)   cpu_relax()
 #define _raw_write_relax(lock)  cpu_relax()
+#define __always_inline__spin_lock
+#define __always_inline__read_lock
+#define __always_inline__write_lock
+#define __always_inline__spin_lock_bh
+#define __always_inline__read_lock_bh
+#define __always_inline__write_lock_bh
+#define __always_inline__spin_lock_irq
+#define __always_inline__read_lock_irq
+#define __always_inline__write_lock_irq
+#define __always_inline__spin_lock_irqsave
+#define __always_inline__read_lock_irqsave
+#define __always_inline__write_lock_irqsave
+#define __always_inline__spin_trylock
+#define __always_inline__read_trylock
+#define __always_inline__write_trylock
+#define __always_inline__spin_trylock_bh
+#define __always_inline__spin_unlock
+#define __always_inline__read_unlock
+#define __always_inline__write_unlock
+#define __always_inline__spin_unlock_bh
+#define __always_inline__read_unlock_bh
+#define __always_inline__write_unlock_bh
+#define __always_inline__spin_unlock_irq
+#define __always_inline__read_unlock_irq
+#define __always_inline__write_unlock_irq
+#define __always_inline__spin_unlock_irqrestore
+#define __always_inline__read_unlock_irqrestore
+#define __always_inline__write_unlock_irqrestore
 #endif /* __ASM_SPINLOCK_H */
diff --git a/arch/s390/include/asm/system.h b/arch/s390/include/asm/system.h
index 4fb83c1cdb77..379661d2f81a 100644
--- a/arch/s390/include/asm/system.h
+++ b/arch/s390/include/asm/system.h
@@ -109,11 +109,7 @@ extern void pfault_fini(void);
 #define pfault_fini()           do { } while (0)
 #endif /* CONFIG_PFAULT */
-#ifdef CONFIG_PAGE_STATES
 extern void cmma_init(void);
-#else
-static inline void cmma_init(void) { }
-#endif
 #define finish_arch_switch(prev) do {                                        \
        set_fs(current->thread.mm_segment);                                  \
diff --git a/arch/s390/include/asm/timex.h b/arch/s390/include/asm/timex.h
index cc21e3e20fd7..68d9fea34b4b 100644
--- a/arch/s390/include/asm/timex.h
+++ b/arch/s390/include/asm/timex.h
@@ -88,6 +88,28 @@ int get_sync_clock(unsigned long long *clock);
 void init_cpu_timer(void);
 unsigned long long monotonic_clock(void);
+void tod_to_timeval(__u64, struct timespec *);
+static inline
+void stck_to_timespec(unsigned long long stck, struct timespec *ts)
+{
+        tod_to_timeval(stck - TOD_UNIX_EPOCH, ts);
+}
 extern u64 sched_clock_base_cc;
+/**
+ * get_clock_monotonic - returns current time in clock rate units
+ *
+ * The caller must ensure that preemption is disabled.
+ * The clock and sched_clock_base get changed via stop_machine.
+ * Therefore preemption must be disabled when calling this
+ * function, otherwise the returned value is not guaranteed to
+ * be monotonic.
+ */
+static inline unsigned long long get_clock_monotonic(void)
+{
+        return get_clock_xt() - sched_clock_base_cc;
+}
 #endif
diff --git a/arch/s390/kernel/Makefile b/arch/s390/kernel/Makefile
index c75ed43b1a18..c7be8e10b87e 100644
--- a/arch/s390/kernel/Makefile
+++ b/arch/s390/kernel/Makefile
@@ -32,7 +32,7 @@ extra-y				+= head.o init_task.o vmlinux.lds
 obj-$(CONFIG_MODULES)           += s390_ksyms.o module.o
 obj-$(CONFIG_SMP)               += smp.o topology.o
+obj-$(CONFIG_HIBERNATION)       += suspend.o swsusp_asm64.o
 obj-$(CONFIG_AUDIT)             += audit.o
 compat-obj-$(CONFIG_AUDIT)      += compat_audit.o
 obj-$(CONFIG_COMPAT)            += compat_linux.o compat_signal.o \
@@ -41,7 +41,7 @@ obj-$(CONFIG_COMPAT)		+= compat_linux.o compat_signal.o \
 obj-$(CONFIG_STACKTRACE)        += stacktrace.o
 obj-$(CONFIG_KPROBES)           += kprobes.o
-obj-$(CONFIG_FUNCTION_TRACER)   += mcount.o
+obj-$(CONFIG_FUNCTION_TRACER)   += $(if $(CONFIG_64BIT),mcount64.o,mcount.o)
 obj-$(CONFIG_DYNAMIC_FTRACE)    += ftrace.o
 obj-$(CONFIG_FUNCTION_GRAPH_TRACER) += ftrace.o
diff --git a/arch/s390/kernel/debug.c b/arch/s390/kernel/debug.c
index be8bceaf37d9..4c512561687d 100644
--- a/arch/s390/kernel/debug.c
+++ b/arch/s390/kernel/debug.c
@@ -63,8 +63,6 @@ typedef struct
 } debug_sprintf_entry_t;
-extern void tod_to_timeval(uint64_t todval, struct timespec *xtime);
 /* internal function prototyes */
 static int debug_init(void);
@@ -1450,17 +1448,13 @@ debug_dflt_header_fn(debug_info_t * id, struct debug_view *view,
                         int area, debug_entry_t * entry, char *out_buf)
 {
        struct timespec time_spec;
-        unsigned long long time;
        char *except_str;
        unsigned long caller;
        int rc = 0;
        unsigned int level;
        level = entry->id.fields.level;
-        time = entry->id.stck;
+        stck_to_timespec(entry->id.stck, &time_spec);
-        /* adjust todclock to 1970 */
-        time -= 0x8126d60e46000000LL - (0x3c26700LL * 1000000 * 4096);
-        tod_to_timeval(time, &time_spec);
        if (entry->id.fields.exception)
                except_str = "*";
diff --git a/arch/s390/kernel/early.c b/arch/s390/kernel/early.c
index cae14c499511..bf8b4ae7ff2d 100644
--- a/arch/s390/kernel/early.c
+++ b/arch/s390/kernel/early.c
@@ -6,6 +6,9 @@
 *               Heiko Carstens <heiko.carstens@de.ibm.com>
 */
+#define KMSG_COMPONENT "setup"
+#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
 #include <linux/compiler.h>
 #include <linux/init.h>
 #include <linux/errno.h>
@@ -16,6 +19,7 @@
 #include <linux/module.h>
 #include <linux/pfn.h>
 #include <linux/uaccess.h>
+#include <linux/kernel.h>
 #include <asm/ebcdic.h>
 #include <asm/ipl.h>
 #include <asm/lowcore.h>
@@ -35,8 +39,6 @@
 char kernel_nss_name[NSS_NAME_SIZE + 1];
-static unsigned long machine_flags;
 static void __init setup_boot_command_line(void);
 /*
@@ -81,6 +83,8 @@ asm(
        "       br      14\n"
        "       .size   savesys_ipl_nss, .-savesys_ipl_nss\n");
+static __initdata char upper_command_line[COMMAND_LINE_SIZE];
 static noinline __init void create_kernel_nss(void)
 {
        unsigned int i, stext_pfn, eshared_pfn, end_pfn, min_size;
@@ -90,7 +94,6 @@ static noinline __init void create_kernel_nss(void)
        int response;
        size_t len;
        char *savesys_ptr;
-        char upper_command_line[COMMAND_LINE_SIZE];
        char defsys_cmd[DEFSYS_CMD_SIZE];
        char savesys_cmd[SAVESYS_CMD_SIZE];
@@ -141,6 +144,8 @@ static noinline __init void create_kernel_nss(void)
        __cpcmd(defsys_cmd, NULL, 0, &response);
        if (response != 0) {
+                pr_err("Defining the Linux kernel NSS failed with rc=%d\n",
+                        response);
                kernel_nss_name[0] = '\0';
                return;
        }
@@ -153,8 +158,11 @@ static noinline __init void create_kernel_nss(void)
         *             max SAVESYS_CMD_SIZE
         * On error: response contains the numeric portion of cp error message.
         *           for SAVESYS it will be >= 263
+         *           for missing privilege class, it will be 1
         */
-        if (response > SAVESYS_CMD_SIZE) {
+        if (response > SAVESYS_CMD_SIZE || response == 1) {
+                pr_err("Saving the Linux kernel NSS failed with rc=%d\n",
+                        response);
                kernel_nss_name[0] = '\0';
                return;
        }
@@ -205,12 +213,9 @@ static noinline __init void detect_machine_type(void)
        /* Running under KVM? If not we assume z/VM */
        if (!memcmp(vmms.vm[0].cpi, "\xd2\xe5\xd4", 3))
-                machine_flags |= MACHINE_FLAG_KVM;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_KVM;
        else
-                machine_flags |= MACHINE_FLAG_VM;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_VM;
-        /* Store machine flags for setting up lowcore early */
-        S390_lowcore.machine_flags = machine_flags;
 }
 static __init void early_pgm_check_handler(void)
@@ -245,7 +250,7 @@ static noinline __init void setup_hpage(void)
        facilities = stfl();
        if (!(facilities & (1UL << 23)) || !(facilities & (1UL << 29)))
                return;
-        machine_flags |= MACHINE_FLAG_HPAGE;
+        S390_lowcore.machine_flags |= MACHINE_FLAG_HPAGE;
        __ctl_set_bit(0, 23);
 #endif
 }
@@ -263,7 +268,7 @@ static __init void detect_mvpg(void)
                EX_TABLE(0b,1b)
                : "=d" (rc) : "0" (-EOPNOTSUPP), "a" (0) : "memory", "cc", "0");
        if (!rc)
-                machine_flags |= MACHINE_FLAG_MVPG;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_MVPG;
 #endif
 }
@@ -279,7 +284,7 @@ static __init void detect_ieee(void)
                EX_TABLE(0b,1b)
                : "=d" (rc), "=d" (tmp): "0" (-EOPNOTSUPP) : "cc");
        if (!rc)
-                machine_flags |= MACHINE_FLAG_IEEE;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_IEEE;
 #endif
 }
@@ -298,7 +303,7 @@ static __init void detect_csp(void)
                EX_TABLE(0b,1b)
                : "=d" (rc) : "0" (-EOPNOTSUPP) : "cc", "0", "1", "2");
        if (!rc)
-                machine_flags |= MACHINE_FLAG_CSP;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_CSP;
 #endif
 }
@@ -315,7 +320,7 @@ static __init void detect_diag9c(void)
                EX_TABLE(0b,1b)
                : "=d" (rc) : "0" (-EOPNOTSUPP), "d" (cpu_address) : "cc");
        if (!rc)
-                machine_flags |= MACHINE_FLAG_DIAG9C;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_DIAG9C;
 }
 static __init void detect_diag44(void)
@@ -330,7 +335,7 @@ static __init void detect_diag44(void)
                EX_TABLE(0b,1b)
                : "=d" (rc) : "0" (-EOPNOTSUPP) : "cc");
        if (!rc)
-                machine_flags |= MACHINE_FLAG_DIAG44;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_DIAG44;
 #endif
 }
@@ -341,11 +346,11 @@ static __init void detect_machine_facilities(void)
        facilities = stfl();
        if (facilities & (1 << 28))
-                machine_flags |= MACHINE_FLAG_IDTE;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_IDTE;
        if (facilities & (1 << 23))
-                machine_flags |= MACHINE_FLAG_PFMF;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_PFMF;
        if (facilities & (1 << 4))
-                machine_flags |= MACHINE_FLAG_MVCOS;
+                S390_lowcore.machine_flags |= MACHINE_FLAG_MVCOS;
 #endif
 }
@@ -367,21 +372,35 @@ static __init void rescue_initrd(void)
 }
 /* Set up boot command line */
-static void __init setup_boot_command_line(void)
+static void __init append_to_cmdline(size_t (*ipl_data)(char *, size_t))
 {
-        char *parm = NULL;
+        char *parm, *delim;
+        size_t rc, len;
+        len = strlen(boot_command_line);
+        delim = boot_command_line + len;        /* '\0' character position */
+        parm  = boot_command_line + len + 1;    /* append right after '\0' */
+        rc = ipl_data(parm, COMMAND_LINE_SIZE - len - 1);
+        if (rc) {
+                if (*parm == '=')
+                        memmove(boot_command_line, parm + 1, rc);
+                else
+                        *delim = ' ';           /* replace '\0' with space */
+        }
+}
+static void __init setup_boot_command_line(void)
+{
        /* copy arch command line */
        strlcpy(boot_command_line, COMMAND_LINE, ARCH_COMMAND_LINE_SIZE);
        /* append IPL PARM data to the boot command line */
-        if (MACHINE_IS_VM) {
+        if (MACHINE_IS_VM)
-                parm = boot_command_line + strlen(boot_command_line);
+                append_to_cmdline(append_ipl_vmparm);
-                *parm++ = ' ';
-                get_ipl_vmparm(parm);
+        append_to_cmdline(append_ipl_scpdata);
-                if (parm[0] == '=')
-                        memmove(boot_command_line, parm + 1, strlen(parm));
-        }
 }
@@ -413,7 +432,6 @@ void __init startup_init(void)
        setup_hpage();
        sclp_facilities_detect();
        detect_memory_layout(memory_chunk);
-        S390_lowcore.machine_flags = machine_flags;
 #ifdef CONFIG_DYNAMIC_FTRACE
        S390_lowcore.ftrace_func = (unsigned long)ftrace_caller;
 #endif
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 5d40fce878a5..f43d2ee54464 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -278,7 +278,8 @@ sysc_return:
        bnz     BASED(sysc_work)  # there is work to do (signals etc.)
 sysc_restore:
 #ifdef CONFIG_TRACE_IRQFLAGS
-        la      %r1,BASED(sysc_restore_trace_psw)
+        la      %r1,BASED(sysc_restore_trace_psw_addr)
+        l       %r1,0(%r1)
        lpsw    0(%r1)
 sysc_restore_trace:
        TRACE_IRQS_CHECK
@@ -289,10 +290,15 @@ sysc_leave:
 sysc_done:
 #ifdef CONFIG_TRACE_IRQFLAGS
+sysc_restore_trace_psw_addr:
+        .long sysc_restore_trace_psw
+        .section .data,"aw",@progbits
        .align  8
        .globl  sysc_restore_trace_psw
 sysc_restore_trace_psw:
        .long   0, sysc_restore_trace + 0x80000000
+        .previous
 #endif
 #
@@ -606,7 +612,8 @@ io_return:
        bnz     BASED(io_work)          # there is work to do (signals etc.)
 io_restore:
 #ifdef CONFIG_TRACE_IRQFLAGS
-        la      %r1,BASED(io_restore_trace_psw)
+        la      %r1,BASED(io_restore_trace_psw_addr)
+        l       %r1,0(%r1)
        lpsw    0(%r1)
 io_restore_trace:
        TRACE_IRQS_CHECK
@@ -617,10 +624,15 @@ io_leave:
 io_done:
 #ifdef CONFIG_TRACE_IRQFLAGS
+io_restore_trace_psw_addr:
+        .long io_restore_trace_psw
+        .section .data,"aw",@progbits
        .align  8
        .globl  io_restore_trace_psw
 io_restore_trace_psw:
        .long   0, io_restore_trace + 0x80000000
+        .previous
 #endif
 #
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 3ceb53c9c493..a6f7b20df616 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -284,10 +284,12 @@ sysc_leave:
 sysc_done:
 #ifdef CONFIG_TRACE_IRQFLAGS
+        .section .data,"aw",@progbits
        .align  8
        .globl sysc_restore_trace_psw
 sysc_restore_trace_psw:
        .quad   0, sysc_restore_trace
+        .previous
 #endif
 #
@@ -595,10 +597,12 @@ io_leave:
 io_done:
 #ifdef CONFIG_TRACE_IRQFLAGS
+        .section .data,"aw",@progbits
        .align  8
        .globl io_restore_trace_psw
 io_restore_trace_psw:
        .quad   0, io_restore_trace
+        .previous
 #endif
 #
diff --git a/arch/s390/kernel/head.S b/arch/s390/kernel/head.S
index ec6882348520..c52b4f7742fa 100644
--- a/arch/s390/kernel/head.S
+++ b/arch/s390/kernel/head.S
@@ -27,6 +27,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/thread_info.h>
 #include <asm/page.h>
+#include <asm/cpu.h>
 #ifdef CONFIG_64BIT
 #define ARCH_OFFSET     4
diff --git a/arch/s390/kernel/head31.S b/arch/s390/kernel/head31.S
index 2ced846065b7..602b508cd4c4 100644
--- a/arch/s390/kernel/head31.S
+++ b/arch/s390/kernel/head31.S
@@ -24,6 +24,7 @@ startup_continue:
 # Setup stack
 #
        l       %r15,.Linittu-.LPG1(%r13)
+        st      %r15,__LC_THREAD_INFO   # cache thread info in lowcore
        mvc     __LC_CURRENT(4),__TI_task(%r15)
        ahi     %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union+THREAD_SIZE
        st      %r15,__LC_KERNEL_STACK  # set end of kernel stack
diff --git a/arch/s390/kernel/head64.S b/arch/s390/kernel/head64.S
index 65667b2e65ce..6a250808092b 100644
--- a/arch/s390/kernel/head64.S
+++ b/arch/s390/kernel/head64.S
@@ -62,9 +62,9 @@ startup_continue:
        clr     %r11,%r12
        je      5f                      # no more space in prefix array
 4:
-        ahi     %r8,1                           # next cpu (r8 += 1)
+        ahi     %r8,1                   # next cpu (r8 += 1)
-        cl      %r8,.Llast_cpu-.LPG1(%r13)      # is last possible cpu ?
+        chi     %r8,MAX_CPU_ADDRESS     # is last possible cpu ?
-        jl      1b                              # jump if not last cpu
+        jle     1b                      # jump if not last cpu
 5:
        lhi     %r1,2                   # mode 2 = esame (dump)
        j       6f
@@ -92,6 +92,7 @@ startup_continue:
 # Setup stack
 #
        larl    %r15,init_thread_union
+        stg     %r15,__LC_THREAD_INFO   # cache thread info in lowcore
        lg      %r14,__TI_task(%r15)    # cache current in lowcore
        stg     %r14,__LC_CURRENT
        aghi    %r15,1<<(PAGE_SHIFT+THREAD_ORDER) # init_task_union + THREAD_SIZE
@@ -129,8 +130,6 @@ startup_continue:
 #ifdef CONFIG_ZFCPDUMP
 .Lcurrent_cpu:
        .long 0x0
-.Llast_cpu:
-        .long 0x0000ffff
 .Lpref_arr_ptr:
        .long zfcpdump_prefix_array
 #endif /* CONFIG_ZFCPDUMP */
diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c
index 371a2d88f4ac..ee57a42e6e93 100644
--- a/arch/s390/kernel/ipl.c
+++ b/arch/s390/kernel/ipl.c
@@ -272,17 +272,18 @@ static ssize_t ipl_type_show(struct kobject *kobj, struct kobj_attribute *attr,
 static struct kobj_attribute sys_ipl_type_attr = __ATTR_RO(ipl_type);
 /* VM IPL PARM routines */
-static void reipl_get_ascii_vmparm(char *dest,
+size_t reipl_get_ascii_vmparm(char *dest, size_t size,
                                   const struct ipl_parameter_block *ipb)
 {
        int i;
-        int len = 0;
+        size_t len;
        char has_lowercase = 0;
+        len = 0;
        if ((ipb->ipl_info.ccw.vm_flags & DIAG308_VM_FLAGS_VP_VALID) &&
            (ipb->ipl_info.ccw.vm_parm_len > 0)) {
-                len = ipb->ipl_info.ccw.vm_parm_len;
+                len = min_t(size_t, size - 1, ipb->ipl_info.ccw.vm_parm_len);
                memcpy(dest, ipb->ipl_info.ccw.vm_parm, len);
                /* If at least one character is lowercase, we assume mixed
                 * case; otherwise we convert everything to lowercase.
@@ -299,14 +300,20 @@ static void reipl_get_ascii_vmparm(char *dest,
                EBCASC(dest, len);
        }
        dest[len] = 0;
+        return len;
 }
-void get_ipl_vmparm(char *dest)
+size_t append_ipl_vmparm(char *dest, size_t size)
 {
+        size_t rc;
+        rc = 0;
        if (diag308_set_works && (ipl_block.hdr.pbt == DIAG308_IPL_TYPE_CCW))
-                reipl_get_ascii_vmparm(dest, &ipl_block);
+                rc = reipl_get_ascii_vmparm(dest, size, &ipl_block);
        else
                dest[0] = 0;
+        return rc;
 }
 static ssize_t ipl_vm_parm_show(struct kobject *kobj,
@@ -314,10 +321,65 @@ static ssize_t ipl_vm_parm_show(struct kobject *kobj,
 {
        char parm[DIAG308_VMPARM_SIZE + 1] = {};
-        get_ipl_vmparm(parm);
+        append_ipl_vmparm(parm, sizeof(parm));
        return sprintf(page, "%s\n", parm);
 }
+static size_t scpdata_length(const char* buf, size_t count)
+{
+        while (count) {
+                if (buf[count - 1] != '\0' && buf[count - 1] != ' ')
+                        break;
+                count--;
+        }
+        return count;
+}
+size_t reipl_append_ascii_scpdata(char *dest, size_t size,
+                                  const struct ipl_parameter_block *ipb)
+{
+        size_t count;
+        size_t i;
+        int has_lowercase;
+        count = min(size - 1, scpdata_length(ipb->ipl_info.fcp.scp_data,
+                                             ipb->ipl_info.fcp.scp_data_len));
+        if (!count)
+                goto out;
+        has_lowercase = 0;
+        for (i = 0; i < count; i++) {
+                if (!isascii(ipb->ipl_info.fcp.scp_data[i])) {
+                        count = 0;
+                        goto out;
+                }
+                if (!has_lowercase && islower(ipb->ipl_info.fcp.scp_data[i]))
+                        has_lowercase = 1;
+        }
+        if (has_lowercase)
+                memcpy(dest, ipb->ipl_info.fcp.scp_data, count);
+        else
+                for (i = 0; i < count; i++)
+                        dest[i] = tolower(ipb->ipl_info.fcp.scp_data[i]);
+out:
+        dest[count] = '\0';
+        return count;
+}
+size_t append_ipl_scpdata(char *dest, size_t len)
+{
+        size_t rc;
+        rc = 0;
+        if (ipl_block.hdr.pbt == DIAG308_IPL_TYPE_FCP)
+                rc = reipl_append_ascii_scpdata(dest, len, &ipl_block);
+        else
+                dest[0] = 0;
+        return rc;
+}
 static struct kobj_attribute sys_ipl_vm_parm_attr =
        __ATTR(parm, S_IRUGO, ipl_vm_parm_show, NULL);
@@ -553,7 +615,7 @@ static ssize_t reipl_generic_vmparm_show(struct ipl_parameter_block *ipb,
 {
        char vmparm[DIAG308_VMPARM_SIZE + 1] = {};
-        reipl_get_ascii_vmparm(vmparm, ipb);
+        reipl_get_ascii_vmparm(vmparm, sizeof(vmparm), ipb);
        return sprintf(page, "%s\n", vmparm);
 }
@@ -626,6 +688,59 @@ static struct kobj_attribute sys_reipl_ccw_vmparm_attr =
 /* FCP reipl device attributes */
+static ssize_t reipl_fcp_scpdata_read(struct kobject *kobj,
+                                      struct bin_attribute *attr,
+                                      char *buf, loff_t off, size_t count)
+{
+        size_t size = reipl_block_fcp->ipl_info.fcp.scp_data_len;
+        void *scp_data = reipl_block_fcp->ipl_info.fcp.scp_data;
+        return memory_read_from_buffer(buf, count, &off, scp_data, size);
+}
+static ssize_t reipl_fcp_scpdata_write(struct kobject *kobj,
+                                       struct bin_attribute *attr,
+                                       char *buf, loff_t off, size_t count)
+{
+        size_t padding;
+        size_t scpdata_len;
+        if (off < 0)
+                return -EINVAL;
+        if (off >= DIAG308_SCPDATA_SIZE)
+                return -ENOSPC;
+        if (count > DIAG308_SCPDATA_SIZE - off)
+                count = DIAG308_SCPDATA_SIZE - off;
+        memcpy(reipl_block_fcp->ipl_info.fcp.scp_data, buf + off, count);
+        scpdata_len = off + count;
+        if (scpdata_len % 8) {
+                padding = 8 - (scpdata_len % 8);
+                memset(reipl_block_fcp->ipl_info.fcp.scp_data + scpdata_len,
+                       0, padding);
+                scpdata_len += padding;
+        }
+        reipl_block_fcp->ipl_info.fcp.scp_data_len = scpdata_len;
+        reipl_block_fcp->hdr.len = IPL_PARM_BLK_FCP_LEN + scpdata_len;
+        reipl_block_fcp->hdr.blk0_len = IPL_PARM_BLK0_FCP_LEN + scpdata_len;
+        return count;
+}
+static struct bin_attribute sys_reipl_fcp_scp_data_attr = {
+        .attr = {
+                .name = "scp_data",
+                .mode = S_IRUGO | S_IWUSR,
+        },
+        .size = PAGE_SIZE,
+        .read = reipl_fcp_scpdata_read,
+        .write = reipl_fcp_scpdata_write,
+};
 DEFINE_IPL_ATTR_RW(reipl_fcp, wwpn, "0x%016llx\n", "%016llx\n",
                   reipl_block_fcp->ipl_info.fcp.wwpn);
 DEFINE_IPL_ATTR_RW(reipl_fcp, lun, "0x%016llx\n", "%016llx\n",
@@ -647,7 +762,6 @@ static struct attribute *reipl_fcp_attrs[] = {
 };
 static struct attribute_group reipl_fcp_attr_group = {
-        .name  = IPL_FCP_STR,
        .attrs = reipl_fcp_attrs,
 };
@@ -895,6 +1009,7 @@ static struct kobj_attribute reipl_type_attr =
        __ATTR(reipl_type, 0644, reipl_type_show, reipl_type_store);
 static struct kset *reipl_kset;
+static struct kset *reipl_fcp_kset;
 static void get_ipl_string(char *dst, struct ipl_parameter_block *ipb,
                           const enum ipl_method m)
@@ -906,7 +1021,7 @@ static void get_ipl_string(char *dst, struct ipl_parameter_block *ipb,
        reipl_get_ascii_loadparm(loadparm, ipb);
        reipl_get_ascii_nss_name(nss_name, ipb);
-        reipl_get_ascii_vmparm(vmparm, ipb);
+        reipl_get_ascii_vmparm(vmparm, sizeof(vmparm), ipb);
        switch (m) {
        case REIPL_METHOD_CCW_VM:
@@ -1076,23 +1191,44 @@ static int __init reipl_fcp_init(void)
        int rc;
        if (!diag308_set_works) {
-                if (ipl_info.type == IPL_TYPE_FCP)
+                if (ipl_info.type == IPL_TYPE_FCP) {
                        make_attrs_ro(reipl_fcp_attrs);
-                else
+                        sys_reipl_fcp_scp_data_attr.attr.mode = S_IRUGO;
+                } else
                        return 0;
        }
        reipl_block_fcp = (void *) get_zeroed_page(GFP_KERNEL);
        if (!reipl_block_fcp)
                return -ENOMEM;
-        rc = sysfs_create_group(&reipl_kset->kobj, &reipl_fcp_attr_group);
+        /* sysfs: create fcp kset for mixing attr group and bin attrs */
+        reipl_fcp_kset = kset_create_and_add(IPL_FCP_STR, NULL,
+                                             &reipl_kset->kobj);
+        if (!reipl_kset) {
+                free_page((unsigned long) reipl_block_fcp);
+                return -ENOMEM;
+        }
+        rc = sysfs_create_group(&reipl_fcp_kset->kobj, &reipl_fcp_attr_group);
+        if (rc) {
+                kset_unregister(reipl_fcp_kset);
+                free_page((unsigned long) reipl_block_fcp);
+                return rc;
+        }
+        rc = sysfs_create_bin_file(&reipl_fcp_kset->kobj,
+                                   &sys_reipl_fcp_scp_data_attr);
        if (rc) {
-                free_page((unsigned long)reipl_block_fcp);
+                sysfs_remove_group(&reipl_fcp_kset->kobj, &reipl_fcp_attr_group);
+                kset_unregister(reipl_fcp_kset);
+                free_page((unsigned long) reipl_block_fcp);
                return rc;
        }
-        if (ipl_info.type == IPL_TYPE_FCP) {
+        if (ipl_info.type == IPL_TYPE_FCP)
                memcpy(reipl_block_fcp, IPL_PARMBLOCK_START, PAGE_SIZE);
-        } else {
+        else {
                reipl_block_fcp->hdr.len = IPL_PARM_BLK_FCP_LEN;
                reipl_block_fcp->hdr.version = IPL_PARM_BLOCK_VERSION;
                reipl_block_fcp->hdr.blk0_len = IPL_PARM_BLK0_FCP_LEN;
diff --git a/arch/s390/kernel/mcount.S b/arch/s390/kernel/mcount.S
index 2a0a5e97ba8c..dfe015d7398c 100644
--- a/arch/s390/kernel/mcount.S
+++ b/arch/s390/kernel/mcount.S
@@ -11,111 +11,27 @@
 ftrace_stub:
        br      %r14
-#ifdef CONFIG_64BIT
-#ifdef CONFIG_DYNAMIC_FTRACE
        .globl _mcount
 _mcount:
-        br      %r14
+#ifdef CONFIG_DYNAMIC_FTRACE
-        .globl ftrace_caller
-ftrace_caller:
-        larl    %r1,function_trace_stop
-        icm     %r1,0xf,0(%r1)
-        bnzr    %r14
-        stmg    %r2,%r5,32(%r15)
-        stg     %r14,112(%r15)
-        lgr     %r1,%r15
-        aghi    %r15,-160
-        stg     %r1,__SF_BACKCHAIN(%r15)
-        lgr     %r2,%r14
-        lg      %r3,168(%r15)
-        larl    %r14,ftrace_dyn_func
-        lg      %r14,0(%r14)
-        basr    %r14,%r14
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-        .globl  ftrace_graph_caller
-ftrace_graph_caller:
-        # This unconditional branch gets runtime patched. Change only if
-        # you know what you are doing. See ftrace_enable_graph_caller().
-        j       0f
-        lg      %r2,272(%r15)
-        lg      %r3,168(%r15)
-        brasl   %r14,prepare_ftrace_return
-        stg     %r2,168(%r15)
-0:
-#endif
-        aghi    %r15,160
-        lmg     %r2,%r5,32(%r15)
-        lg      %r14,112(%r15)
        br      %r14
        .data
        .globl  ftrace_dyn_func
 ftrace_dyn_func:
-        .quad   ftrace_stub
+        .long   ftrace_stub
        .previous
-#else /* CONFIG_DYNAMIC_FTRACE */
-        .globl _mcount
-_mcount:
-        larl    %r1,function_trace_stop
-        icm     %r1,0xf,0(%r1)
-        bnzr    %r14
-        stmg    %r2,%r5,32(%r15)
-        stg     %r14,112(%r15)
-        lgr     %r1,%r15
-        aghi    %r15,-160
-        stg     %r1,__SF_BACKCHAIN(%r15)
-        lgr     %r2,%r14
-        lg      %r3,168(%r15)
-        larl    %r14,ftrace_trace_function
-        lg      %r14,0(%r14)
-        basr    %r14,%r14
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-        lg      %r2,272(%r15)
-        lg      %r3,168(%r15)
-        brasl   %r14,prepare_ftrace_return
-        stg     %r2,168(%r15)
-#endif
-        aghi    %r15,160
-        lmg     %r2,%r5,32(%r15)
-        lg      %r14,112(%r15)
-        br      %r14
-#endif /* CONFIG_DYNAMIC_FTRACE */
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
-        .globl  return_to_handler
-return_to_handler:
-        stmg    %r2,%r5,32(%r15)
-        lgr     %r1,%r15
-        aghi    %r15,-160
-        stg     %r1,__SF_BACKCHAIN(%r15)
-        brasl   %r14,ftrace_return_to_handler
-        aghi    %r15,160
-        lgr     %r14,%r2
-        lmg     %r2,%r5,32(%r15)
-        br      %r14
-#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
-#else /* CONFIG_64BIT */
-#ifdef CONFIG_DYNAMIC_FTRACE
-        .globl _mcount
-_mcount:
-        br      %r14
        .globl ftrace_caller
 ftrace_caller:
+#endif
        stm     %r2,%r5,16(%r15)
        bras    %r1,2f
+#ifdef CONFIG_DYNAMIC_FTRACE
+0:      .long   ftrace_dyn_func
+#else
 0:      .long   ftrace_trace_function
+#endif
 1:      .long   function_trace_stop
 2:      l       %r2,1b-0b(%r1)
        icm     %r2,0xf,0(%r2)
@@ -131,53 +47,13 @@ ftrace_caller:
        l       %r14,0(%r14)
        basr    %r14,%r14
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#ifdef CONFIG_DYNAMIC_FTRACE
        .globl  ftrace_graph_caller
 ftrace_graph_caller:
        # This unconditional branch gets runtime patched. Change only if
        # you know what you are doing. See ftrace_enable_graph_caller().
        j       1f
-        bras    %r1,0f
-        .long   prepare_ftrace_return
-0:      l       %r2,152(%r15)
-        l       %r4,0(%r1)
-        l       %r3,100(%r15)
-        basr    %r14,%r4
-        st      %r2,100(%r15)
-1:
 #endif
-        ahi     %r15,96
-        l       %r14,56(%r15)
-3:      lm      %r2,%r5,16(%r15)
-        br      %r14
-        .data
-        .globl  ftrace_dyn_func
-ftrace_dyn_func:
-        .long   ftrace_stub
-        .previous
-#else /* CONFIG_DYNAMIC_FTRACE */
-        .globl _mcount
-_mcount:
-        stm     %r2,%r5,16(%r15)
-        bras    %r1,2f
-0:      .long   ftrace_trace_function
-1:      .long   function_trace_stop
-2:      l       %r2,1b-0b(%r1)
-        icm     %r2,0xf,0(%r2)
-        jnz     3f
-        st      %r14,56(%r15)
-        lr      %r0,%r15
-        ahi     %r15,-96
-        l       %r3,100(%r15)
-        la      %r2,0(%r14)
-        st      %r0,__SF_BACKCHAIN(%r15)
-        la      %r3,0(%r3)
-        l       %r14,0b-0b(%r1)
-        l       %r14,0(%r14)
-        basr    %r14,%r14
-#ifdef CONFIG_FUNCTION_GRAPH_TRACER
        bras    %r1,0f
        .long   prepare_ftrace_return
 0:      l       %r2,152(%r15)
@@ -185,14 +61,13 @@ _mcount:
        l       %r3,100(%r15)
        basr    %r14,%r4
        st      %r2,100(%r15)
+1:
 #endif
        ahi     %r15,96
        l       %r14,56(%r15)
 3:      lm      %r2,%r5,16(%r15)
        br      %r14
-#endif /* CONFIG_DYNAMIC_FTRACE */
 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
        .globl  return_to_handler
@@ -211,6 +86,4 @@ return_to_handler:
        lm      %r2,%r5,16(%r15)
        br      %r14
-#endif /* CONFIG_FUNCTION_GRAPH_TRACER */
+#endif
-#endif /* CONFIG_64BIT */
diff --git a/arch/s390/kernel/mcount64.S b/arch/s390/kernel/mcount64.S
new file mode 100644
index 000000000000..c37211c6092b
--- /dev/null
+++ b/arch/s390/kernel/mcount64.S
@@ -0,0 +1,78 @@
+/*
+ * Copyright IBM Corp. 2008,2009
+ *
+ *   Author(s): Heiko Carstens <heiko.carstens@de.ibm.com>,
+ *
+ */
+#include <asm/asm-offsets.h>
+        .globl ftrace_stub
+ftrace_stub:
+        br      %r14
+        .globl _mcount
+_mcount:
+#ifdef CONFIG_DYNAMIC_FTRACE
+        br      %r14
+        .data
+        .globl  ftrace_dyn_func
+ftrace_dyn_func:
+        .quad   ftrace_stub
+        .previous
+        .globl ftrace_caller
+ftrace_caller:
+#endif
+        larl    %r1,function_trace_stop
+        icm     %r1,0xf,0(%r1)
+        bnzr    %r14
+        stmg    %r2,%r5,32(%r15)
+        stg     %r14,112(%r15)
+        lgr     %r1,%r15
+        aghi    %r15,-160
+        stg     %r1,__SF_BACKCHAIN(%r15)
+        lgr     %r2,%r14
+        lg      %r3,168(%r15)
+#ifdef CONFIG_DYNAMIC_FTRACE
+        larl    %r14,ftrace_dyn_func
+#else
+        larl    %r14,ftrace_trace_function
+#endif
+        lg      %r14,0(%r14)
+        basr    %r14,%r14
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+#ifdef CONFIG_DYNAMIC_FTRACE
+        .globl  ftrace_graph_caller
+ftrace_graph_caller:
+        # This unconditional branch gets runtime patched. Change only if
+        # you know what you are doing. See ftrace_enable_graph_caller().
+        j       0f
+#endif
+        lg      %r2,272(%r15)
+        lg      %r3,168(%r15)
+        brasl   %r14,prepare_ftrace_return
+        stg     %r2,168(%r15)
+0:
+#endif
+        aghi    %r15,160
+        lmg     %r2,%r5,32(%r15)
+        lg      %r14,112(%r15)
+        br      %r14
+#ifdef CONFIG_FUNCTION_GRAPH_TRACER
+        .globl  return_to_handler
+return_to_handler:
+        stmg    %r2,%r5,32(%r15)
+        lgr     %r1,%r15
+        aghi    %r15,-160
+        stg     %r1,__SF_BACKCHAIN(%r15)
+        brasl   %r14,ftrace_return_to_handler
+        aghi    %r15,160
+        lgr     %r14,%r2
+        lmg     %r2,%r5,32(%r15)
+        br      %r14
+#endif
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index cbb897bc50bd..9ed13a1ed376 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -156,15 +156,11 @@ __setup("condev=", condev_setup);
 static void __init set_preferred_console(void)
 {
-        if (MACHINE_IS_KVM) {
+        if (MACHINE_IS_KVM)
                add_preferred_console("hvc", 0, NULL);
-                s390_virtio_console_init();
+        else if (CONSOLE_IS_3215 || CONSOLE_IS_SCLP)
-                return;
-        }
-        if (CONSOLE_IS_3215 || CONSOLE_IS_SCLP)
                add_preferred_console("ttyS", 0, NULL);
-        if (CONSOLE_IS_3270)
+        else if (CONSOLE_IS_3270)
                add_preferred_console("tty3270", 0, NULL);
 }
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index 062bd64e65fa..6b4fef877f9d 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -536,4 +536,6 @@ void do_notify_resume(struct pt_regs *regs)
 {
        clear_thread_flag(TIF_NOTIFY_RESUME);
        tracehook_notify_resume(regs);
+        if (current->replacement_session_keyring)
+                key_replace_session_keyring();
 }
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index be2cae083406..56c16876b919 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -49,6 +49,7 @@
 #include <asm/sclp.h>
 #include <asm/cputime.h>
 #include <asm/vdso.h>
+#include <asm/cpu.h>
 #include "entry.h"
 static struct task_struct *current_set[NR_CPUS];
@@ -70,6 +71,23 @@ static DEFINE_PER_CPU(struct cpu, cpu_devices);
 static void smp_ext_bitcall(int, ec_bit_sig);
+static int cpu_stopped(int cpu)
+{
+        __u32 status;
+        switch (signal_processor_ps(&status, 0, cpu, sigp_sense)) {
+        case sigp_order_code_accepted:
+        case sigp_status_stored:
+                /* Check for stopped and check stop state */
+                if (status & 0x50)
+                        return 1;
+                break;
+        default:
+                break;
+        }
+        return 0;
+}
 void smp_send_stop(void)
 {
        int cpu, rc;
@@ -86,7 +104,7 @@ void smp_send_stop(void)
                        rc = signal_processor(cpu, sigp_stop);
                } while (rc == sigp_busy);
-                while (!smp_cpu_not_running(cpu))
+                while (!cpu_stopped(cpu))
                        cpu_relax();
        }
 }
@@ -269,19 +287,6 @@ static inline void smp_get_save_area(unsigned int cpu, unsigned int phy_cpu) { }
 #endif /* CONFIG_ZFCPDUMP */
-static int cpu_stopped(int cpu)
-{
-        __u32 status;
-        /* Check for stopped state */
-        if (signal_processor_ps(&status, 0, cpu, sigp_sense) ==
-            sigp_status_stored) {
-                if (status & 0x40)
-                        return 1;
-        }
-        return 0;
-}
 static int cpu_known(int cpu_id)
 {
        int cpu;
@@ -300,7 +305,7 @@ static int smp_rescan_cpus_sigp(cpumask_t avail)
        logical_cpu = cpumask_first(&avail);
        if (logical_cpu >= nr_cpu_ids)
                return 0;
-        for (cpu_id = 0; cpu_id <= 65535; cpu_id++) {
+        for (cpu_id = 0; cpu_id <= MAX_CPU_ADDRESS; cpu_id++) {
                if (cpu_known(cpu_id))
                        continue;
                __cpu_logical_map[logical_cpu] = cpu_id;
@@ -379,7 +384,7 @@ static void __init smp_detect_cpus(void)
        /* Use sigp detection algorithm if sclp doesn't work. */
        if (sclp_get_cpu_info(info)) {
                smp_use_sigp_detection = 1;
-                for (cpu = 0; cpu <= 65535; cpu++) {
+                for (cpu = 0; cpu <= MAX_CPU_ADDRESS; cpu++) {
                        if (cpu == boot_cpu_addr)
                                continue;
                        __cpu_logical_map[CPU_INIT_NO] = cpu;
@@ -635,7 +640,7 @@ int __cpu_disable(void)
 void __cpu_die(unsigned int cpu)
 {
        /* Wait until target cpu is down */
-        while (!smp_cpu_not_running(cpu))
+        while (!cpu_stopped(cpu))
                cpu_relax();
        smp_free_lowcore(cpu);
        pr_info("Processor %d stopped\n", cpu);
diff --git a/arch/s390/power/swsusp.c b/arch/s390/kernel/suspend.c
index bd1f5c6b0b8c..086bee970cae 100644
--- a/arch/s390/power/swsusp.c
+++ b/arch/s390/kernel/suspend.c
@@ -1,13 +1,44 @@
 /*
- * Support for suspend and resume on s390
+ * Suspend support specific for s390.
 *
 * Copyright IBM Corp. 2009
 *
 * Author(s): Hans-Joachim Picht <hans@linux.vnet.ibm.com>
- *
 */
+#include <linux/suspend.h>
+#include <linux/reboot.h>
+#include <linux/pfn.h>
+#include <linux/mm.h>
+#include <asm/sections.h>
 #include <asm/system.h>
+#include <asm/ipl.h>
+/*
+ * References to section boundaries
+ */
+extern const void __nosave_begin, __nosave_end;
+/*
+ *  check if given pfn is in the 'nosave' or in the read only NSS section
+ */
+int pfn_is_nosave(unsigned long pfn)
+{
+        unsigned long nosave_begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT;
+        unsigned long nosave_end_pfn = PAGE_ALIGN(__pa(&__nosave_end))
+                                        >> PAGE_SHIFT;
+        unsigned long eshared_pfn = PFN_DOWN(__pa(&_eshared)) - 1;
+        unsigned long stext_pfn = PFN_DOWN(__pa(&_stext));
+        if (pfn >= nosave_begin_pfn && pfn < nosave_end_pfn)
+                return 1;
+        if (pfn >= stext_pfn && pfn <= eshared_pfn) {
+                if (ipl_info.type == IPL_TYPE_NSS)
+                        return 1;
+        } else if ((tprot(pfn * PAGE_SIZE) && pfn > 0))
+                return 1;
+        return 0;
+}
 void save_processor_state(void)
 {
diff --git a/arch/s390/power/swsusp_asm64.S b/arch/s390/kernel/swsusp_asm64.S
index b26df5c5933e..7cd6b096f0d1 100644
--- a/arch/s390/power/swsusp_asm64.S
+++ b/arch/s390/kernel/swsusp_asm64.S
@@ -21,7 +21,7 @@
 * This function runs with disabled interrupts.
 */
        .section .text
-        .align  2
+        .align  4
        .globl swsusp_arch_suspend
 swsusp_arch_suspend:
        stmg    %r6,%r15,__SF_GPRS(%r15)
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index d4c8e9c47c81..e3dc28b8075d 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -60,6 +60,7 @@
 #define TICK_SIZE tick
 u64 sched_clock_base_cc = -1;   /* Force to data section. */
+EXPORT_SYMBOL_GPL(sched_clock_base_cc);
 static DEFINE_PER_CPU(struct clock_event_device, comparators);
@@ -68,7 +69,7 @@ static DEFINE_PER_CPU(struct clock_event_device, comparators);
 */
 unsigned long long notrace sched_clock(void)
 {
-        return ((get_clock_xt() - sched_clock_base_cc) * 125) >> 9;
+        return (get_clock_monotonic() * 125) >> 9;
 }
 /*
@@ -90,6 +91,7 @@ void tod_to_timeval(__u64 todval, struct timespec *xtime)
        todval -= (sec * 1000000) << 12;
        xtime->tv_nsec = ((todval * 1000) >> 12);
 }
+EXPORT_SYMBOL(tod_to_timeval);
 void clock_comparator_work(void)
 {
diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S
index a53db23ee092..7315f9e67e1d 100644
--- a/arch/s390/kernel/vmlinux.lds.S
+++ b/arch/s390/kernel/vmlinux.lds.S
@@ -52,55 +52,18 @@ SECTIONS
        . = ALIGN(PAGE_SIZE);
        _eshared = .;           /* End of shareable data */
-        . = ALIGN(16);          /* Exception table */
+        EXCEPTION_TABLE(16) :data
-        __ex_table : {
-                __start___ex_table = .;
-                *(__ex_table)
-                __stop___ex_table = .;
-        } :data
-        .data : {               /* Data */
-                DATA_DATA
-                CONSTRUCTORS
-        }
-        . = ALIGN(PAGE_SIZE);
-        .data_nosave : {
-        __nosave_begin = .;
-                *(.data.nosave)
-        }
-        . = ALIGN(PAGE_SIZE);
-        __nosave_end = .;
-        . = ALIGN(PAGE_SIZE);
-        .data.page_aligned : {
-                *(.data.idt)
-        }
-        . = ALIGN(0x100);
+        RW_DATA_SECTION(0x100, PAGE_SIZE, THREAD_SIZE)
-        .data.cacheline_aligned : {
-                *(.data.cacheline_aligned)
-        }
-        . = ALIGN(0x100);
-        .data.read_mostly : {
-                *(.data.read_mostly)
-        }
        _edata = .;             /* End of data section */
-        . = ALIGN(THREAD_SIZE); /* init_task */
-        .data.init_task : {
-                *(.data.init_task)
-        }
        /* will be freed after init */
        . = ALIGN(PAGE_SIZE);   /* Init code and data */
        __init_begin = .;
-        .init.text : {
-                _sinittext = .;
+        INIT_TEXT_SECTION(PAGE_SIZE)
-                INIT_TEXT
-                _einittext = .;
-        }
        /*
         * .exit.text is discarded at runtime, not link time,
         * to deal with references from __bug_table
@@ -111,49 +74,13 @@ SECTIONS
        /* early.c uses stsi, which requires page aligned data. */
        . = ALIGN(PAGE_SIZE);
-        .init.data : {
+        INIT_DATA_SECTION(0x100)
-                INIT_DATA
-        }
-        . = ALIGN(0x100);
-        .init.setup : {
-                __setup_start = .;
-                *(.init.setup)
-                __setup_end = .;
-        }
-        .initcall.init : {
-                __initcall_start = .;
-                INITCALLS
-                __initcall_end = .;
-        }
-        .con_initcall.init : {
-                __con_initcall_start = .;
-                *(.con_initcall.init)
-                __con_initcall_end = .;
-        }
-        SECURITY_INIT
-#ifdef CONFIG_BLK_DEV_INITRD
-        . = ALIGN(0x100);
-        .init.ramfs : {
-                __initramfs_start = .;
-                *(.init.ramfs)
-                . = ALIGN(2);
-                __initramfs_end = .;
-        }
-#endif
        PERCPU(PAGE_SIZE)
        . = ALIGN(PAGE_SIZE);
        __init_end = .;         /* freed after init ends here */
-        /* BSS */
+        BSS_SECTION(0, 2, 0)
-        .bss : {
-                __bss_start = .;
-                *(.bss)
-                . = ALIGN(2);
-                __bss_stop = .;
-        }
        _end = . ;
diff --git a/arch/s390/kvm/Kconfig b/arch/s390/kvm/Kconfig
index 3e260b7e37b2..bf164fc21864 100644
--- a/arch/s390/kvm/Kconfig
+++ b/arch/s390/kvm/Kconfig
@@ -1,11 +1,7 @@
 #
 # KVM configuration
 #
-config HAVE_KVM
+source "virt/kvm/Kconfig"
-       bool
-config HAVE_KVM_IRQCHIP
-       bool
 menuconfig VIRTUALIZATION
        bool "Virtualization"
@@ -38,9 +34,6 @@ config KVM
          If unsure, say N.
-config KVM_TRACE
-       bool
 # OK, it's a little counter-intuitive to do this, but it puts it neatly under
 # the virtualization menu.
 source drivers/virtio/Kconfig
diff --git a/arch/s390/kvm/gaccess.h b/arch/s390/kvm/gaccess.h
index ed60f3a74a85..03c716a0f01f 100644
--- a/arch/s390/kvm/gaccess.h
+++ b/arch/s390/kvm/gaccess.h
@@ -1,7 +1,7 @@
 /*
 * gaccess.h -  access guest memory
 *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008,2009
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
@@ -16,13 +16,14 @@
 #include <linux/compiler.h>
 #include <linux/kvm_host.h>
 #include <asm/uaccess.h>
+#include "kvm-s390.h"
 static inline void __user *__guestaddr_to_user(struct kvm_vcpu *vcpu,
                                               unsigned long guestaddr)
 {
        unsigned long prefix  = vcpu->arch.sie_block->prefix;
-        unsigned long origin  = vcpu->kvm->arch.guest_origin;
+        unsigned long origin  = vcpu->arch.sie_block->gmsor;
-        unsigned long memsize = vcpu->kvm->arch.guest_memsize;
+        unsigned long memsize = kvm_s390_vcpu_get_memsize(vcpu);
        if (guestaddr < 2 * PAGE_SIZE)
                guestaddr += prefix;
@@ -158,8 +159,8 @@ static inline int copy_to_guest(struct kvm_vcpu *vcpu, unsigned long guestdest,
                                const void *from, unsigned long n)
 {
        unsigned long prefix  = vcpu->arch.sie_block->prefix;
-        unsigned long origin  = vcpu->kvm->arch.guest_origin;
+        unsigned long origin  = vcpu->arch.sie_block->gmsor;
-        unsigned long memsize = vcpu->kvm->arch.guest_memsize;
+        unsigned long memsize = kvm_s390_vcpu_get_memsize(vcpu);
        if ((guestdest < 2 * PAGE_SIZE) && (guestdest + n > 2 * PAGE_SIZE))
                goto slowpath;
@@ -209,8 +210,8 @@ static inline int copy_from_guest(struct kvm_vcpu *vcpu, void *to,
                                  unsigned long guestsrc, unsigned long n)
 {
        unsigned long prefix  = vcpu->arch.sie_block->prefix;
-        unsigned long origin  = vcpu->kvm->arch.guest_origin;
+        unsigned long origin  = vcpu->arch.sie_block->gmsor;
-        unsigned long memsize = vcpu->kvm->arch.guest_memsize;
+        unsigned long memsize = kvm_s390_vcpu_get_memsize(vcpu);
        if ((guestsrc < 2 * PAGE_SIZE) && (guestsrc + n > 2 * PAGE_SIZE))
                goto slowpath;
@@ -244,8 +245,8 @@ static inline int copy_to_guest_absolute(struct kvm_vcpu *vcpu,
                                         unsigned long guestdest,
                                         const void *from, unsigned long n)
 {
-        unsigned long origin  = vcpu->kvm->arch.guest_origin;
+        unsigned long origin  = vcpu->arch.sie_block->gmsor;
-        unsigned long memsize = vcpu->kvm->arch.guest_memsize;
+        unsigned long memsize = kvm_s390_vcpu_get_memsize(vcpu);
        if (guestdest + n > memsize)
                return -EFAULT;
@@ -262,8 +263,8 @@ static inline int copy_from_guest_absolute(struct kvm_vcpu *vcpu, void *to,
                                           unsigned long guestsrc,
                                           unsigned long n)
 {
-        unsigned long origin  = vcpu->kvm->arch.guest_origin;
+        unsigned long origin  = vcpu->arch.sie_block->gmsor;
-        unsigned long memsize = vcpu->kvm->arch.guest_memsize;
+        unsigned long memsize = kvm_s390_vcpu_get_memsize(vcpu);
        if (guestsrc + n > memsize)
                return -EFAULT;
diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c
index 98997ccba501..ba9d8a7bc1ac 100644
--- a/arch/s390/kvm/intercept.c
+++ b/arch/s390/kvm/intercept.c
@@ -1,7 +1,7 @@
 /*
 * intercept.c - in-kernel handling for sie intercepts
 *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008,2009
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
@@ -128,7 +128,7 @@ static int handle_noop(struct kvm_vcpu *vcpu)
 static int handle_stop(struct kvm_vcpu *vcpu)
 {
-        int rc;
+        int rc = 0;
        vcpu->stat.exit_stop_request++;
        atomic_clear_mask(CPUSTAT_RUNNING, &vcpu->arch.sie_block->cpuflags);
@@ -141,12 +141,18 @@ static int handle_stop(struct kvm_vcpu *vcpu)
                        rc = -ENOTSUPP;
        }
+        if (vcpu->arch.local_int.action_bits & ACTION_RELOADVCPU_ON_STOP) {
+                vcpu->arch.local_int.action_bits &= ~ACTION_RELOADVCPU_ON_STOP;
+                rc = SIE_INTERCEPT_RERUNVCPU;
+                vcpu->run->exit_reason = KVM_EXIT_INTR;
+        }
        if (vcpu->arch.local_int.action_bits & ACTION_STOP_ON_STOP) {
                vcpu->arch.local_int.action_bits &= ~ACTION_STOP_ON_STOP;
                VCPU_EVENT(vcpu, 3, "%s", "cpu stopped");
                rc = -ENOTSUPP;
-        } else
+        }
-                rc = 0;
        spin_unlock_bh(&vcpu->arch.local_int.lock);
        return rc;
 }
@@ -158,9 +164,9 @@ static int handle_validity(struct kvm_vcpu *vcpu)
        vcpu->stat.exit_validity++;
        if ((viwhy == 0x37) && (vcpu->arch.sie_block->prefix
-                <= vcpu->kvm->arch.guest_memsize - 2*PAGE_SIZE)){
+                <= kvm_s390_vcpu_get_memsize(vcpu) - 2*PAGE_SIZE)) {
                rc = fault_in_pages_writeable((char __user *)
-                         vcpu->kvm->arch.guest_origin +
+                         vcpu->arch.sie_block->gmsor +
                         vcpu->arch.sie_block->prefix,
                         2*PAGE_SIZE);
                if (rc)
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 4d613415c435..2c2f98353415 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -283,7 +283,7 @@ static int __try_deliver_ckc_interrupt(struct kvm_vcpu *vcpu)
        return 1;
 }
-int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
+static int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
 {
        struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
        struct kvm_s390_float_interrupt *fi = vcpu->arch.local_int.float_int;
@@ -320,12 +320,6 @@ int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
        return rc;
 }
-int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
-{
-        /* do real check here */
-        return 1;
-}
 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
 {
        return 0;
diff --git a/arch/s390/kvm/kvm-s390.c b/arch/s390/kvm/kvm-s390.c
index 90d9d1ba258b..07ced89740d7 100644
--- a/arch/s390/kvm/kvm-s390.c
+++ b/arch/s390/kvm/kvm-s390.c
@@ -1,7 +1,7 @@
 /*
 * s390host.c --  hosting zSeries kernel virtual machines
 *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008,2009
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
@@ -10,6 +10,7 @@
 *    Author(s): Carsten Otte <cotte@de.ibm.com>
 *               Christian Borntraeger <borntraeger@de.ibm.com>
 *               Heiko Carstens <heiko.carstens@de.ibm.com>
+ *               Christian Ehrhardt <ehrhardt@de.ibm.com>
 */
 #include <linux/compiler.h>
@@ -210,13 +211,17 @@ void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
 static void kvm_free_vcpus(struct kvm *kvm)
 {
        unsigned int i;
+        struct kvm_vcpu *vcpu;
-        for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+        kvm_for_each_vcpu(i, vcpu, kvm)
-                if (kvm->vcpus[i]) {
+                kvm_arch_vcpu_destroy(vcpu);
-                        kvm_arch_vcpu_destroy(kvm->vcpus[i]);
-                        kvm->vcpus[i] = NULL;
+        mutex_lock(&kvm->lock);
-                }
+        for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
-        }
+                kvm->vcpus[i] = NULL;
+        atomic_set(&kvm->online_vcpus, 0);
+        mutex_unlock(&kvm->lock);
 }
 void kvm_arch_sync_events(struct kvm *kvm)
@@ -278,16 +283,10 @@ static void kvm_s390_vcpu_initial_reset(struct kvm_vcpu *vcpu)
        vcpu->arch.sie_block->gbea = 1;
 }
-/* The current code can have up to 256 pages for virtio */
-#define VIRTIODESCSPACE (256ul * 4096ul)
 int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
 {
        atomic_set(&vcpu->arch.sie_block->cpuflags, CPUSTAT_ZARCH);
-        vcpu->arch.sie_block->gmslm = vcpu->kvm->arch.guest_memsize +
+        set_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests);
-                                      vcpu->kvm->arch.guest_origin +
-                                      VIRTIODESCSPACE - 1ul;
-        vcpu->arch.sie_block->gmsor = vcpu->kvm->arch.guest_origin;
        vcpu->arch.sie_block->ecb   = 2;
        vcpu->arch.sie_block->eca   = 0xC1002001U;
        vcpu->arch.sie_block->fac   = (int) (long) facilities;
@@ -319,8 +318,6 @@ struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
        BUG_ON(!kvm->arch.sca);
        if (!kvm->arch.sca->cpu[id].sda)
                kvm->arch.sca->cpu[id].sda = (__u64) vcpu->arch.sie_block;
-        else
-                BUG_ON(!kvm->vcpus[id]); /* vcpu does already exist */
        vcpu->arch.sie_block->scaoh = (__u32)(((__u64)kvm->arch.sca) >> 32);
        vcpu->arch.sie_block->scaol = (__u32)(__u64)kvm->arch.sca;
@@ -490,9 +487,15 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        vcpu_load(vcpu);
+rerun_vcpu:
+        if (vcpu->requests)
+                if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
+                        kvm_s390_vcpu_set_mem(vcpu);
        /* verify, that memory has been registered */
-        if (!vcpu->kvm->arch.guest_memsize) {
+        if (!vcpu->arch.sie_block->gmslm) {
                vcpu_put(vcpu);
+                VCPU_EVENT(vcpu, 3, "%s", "no memory registered to run vcpu");
                return -EINVAL;
        }
@@ -509,6 +512,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                vcpu->arch.sie_block->gpsw.addr = kvm_run->s390_sieic.addr;
                break;
        case KVM_EXIT_UNKNOWN:
+        case KVM_EXIT_INTR:
        case KVM_EXIT_S390_RESET:
                break;
        default:
@@ -522,8 +526,13 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                rc = kvm_handle_sie_intercept(vcpu);
        } while (!signal_pending(current) && !rc);
-        if (signal_pending(current) && !rc)
+        if (rc == SIE_INTERCEPT_RERUNVCPU)
+                goto rerun_vcpu;
+        if (signal_pending(current) && !rc) {
+                kvm_run->exit_reason = KVM_EXIT_INTR;
                rc = -EINTR;
+        }
        if (rc == -ENOTSUPP) {
                /* intercept cannot be handled in-kernel, prepare kvm-run */
@@ -676,6 +685,7 @@ int kvm_arch_set_memory_region(struct kvm *kvm,
                                int user_alloc)
 {
        int i;
+        struct kvm_vcpu *vcpu;
        /* A few sanity checks. We can have exactly one memory slot which has
           to start at guest virtual zero and which has to be located at a
@@ -684,7 +694,7 @@ int kvm_arch_set_memory_region(struct kvm *kvm,
           vmas. It is okay to mmap() and munmap() stuff in this slot after
           doing this call at any time */
-        if (mem->slot || kvm->arch.guest_memsize)
+        if (mem->slot)
                return -EINVAL;
        if (mem->guest_phys_addr)
@@ -699,36 +709,14 @@ int kvm_arch_set_memory_region(struct kvm *kvm,
        if (!user_alloc)
                return -EINVAL;
-        /* lock all vcpus */
+        /* request update of sie control block for all available vcpus */
-        for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+        kvm_for_each_vcpu(i, vcpu, kvm) {
-                if (!kvm->vcpus[i])
+                if (test_and_set_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
                        continue;
-                if (!mutex_trylock(&kvm->vcpus[i]->mutex))
+                kvm_s390_inject_sigp_stop(vcpu, ACTION_RELOADVCPU_ON_STOP);
-                        goto fail_out;
-        }
-        kvm->arch.guest_origin = mem->userspace_addr;
-        kvm->arch.guest_memsize = mem->memory_size;
-        /* update sie control blocks, and unlock all vcpus */
-        for (i = 0; i < KVM_MAX_VCPUS; ++i) {
-                if (kvm->vcpus[i]) {
-                        kvm->vcpus[i]->arch.sie_block->gmsor =
-                                kvm->arch.guest_origin;
-                        kvm->vcpus[i]->arch.sie_block->gmslm =
-                                kvm->arch.guest_memsize +
-                                kvm->arch.guest_origin +
-                                VIRTIODESCSPACE - 1ul;
-                        mutex_unlock(&kvm->vcpus[i]->mutex);
-                }
        }
        return 0;
-fail_out:
-        for (; i >= 0; i--)
-                mutex_unlock(&kvm->vcpus[i]->mutex);
-        return -EINVAL;
 }
 void kvm_arch_flush_shadow(struct kvm *kvm)
diff --git a/arch/s390/kvm/kvm-s390.h b/arch/s390/kvm/kvm-s390.h
index 748fee872323..ec5eee7c25d8 100644
--- a/arch/s390/kvm/kvm-s390.h
+++ b/arch/s390/kvm/kvm-s390.h
@@ -1,7 +1,7 @@
 /*
 * kvm_s390.h -  definition for kvm on s390
 *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008,2009
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
@@ -9,6 +9,7 @@
 *
 *    Author(s): Carsten Otte <cotte@de.ibm.com>
 *               Christian Borntraeger <borntraeger@de.ibm.com>
+ *               Christian Ehrhardt <ehrhardt@de.ibm.com>
 */
 #ifndef ARCH_S390_KVM_S390_H
@@ -18,8 +19,13 @@
 #include <linux/kvm.h>
 #include <linux/kvm_host.h>
+/* The current code can have up to 256 pages for virtio */
+#define VIRTIODESCSPACE (256ul * 4096ul)
 typedef int (*intercept_handler_t)(struct kvm_vcpu *vcpu);
+/* negativ values are error codes, positive values for internal conditions */
+#define SIE_INTERCEPT_RERUNVCPU         (1<<0)
 int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu);
 #define VM_EVENT(d_kvm, d_loglevel, d_string, d_args...)\
@@ -50,6 +56,30 @@ int kvm_s390_inject_vm(struct kvm *kvm,
 int kvm_s390_inject_vcpu(struct kvm_vcpu *vcpu,
                struct kvm_s390_interrupt *s390int);
 int kvm_s390_inject_program_int(struct kvm_vcpu *vcpu, u16 code);
+int kvm_s390_inject_sigp_stop(struct kvm_vcpu *vcpu, int action);
+static inline int kvm_s390_vcpu_get_memsize(struct kvm_vcpu *vcpu)
+{
+        return vcpu->arch.sie_block->gmslm
+                - vcpu->arch.sie_block->gmsor
+                - VIRTIODESCSPACE + 1ul;
+}
+static inline void kvm_s390_vcpu_set_mem(struct kvm_vcpu *vcpu)
+{
+        struct kvm_memory_slot *mem;
+        down_read(&vcpu->kvm->slots_lock);
+        mem = &vcpu->kvm->memslots[0];
+        vcpu->arch.sie_block->gmsor = mem->userspace_addr;
+        vcpu->arch.sie_block->gmslm =
+                mem->userspace_addr +
+                (mem->npages << PAGE_SHIFT) +
+                VIRTIODESCSPACE - 1ul;
+        up_read(&vcpu->kvm->slots_lock);
+}
 /* implemented in priv.c */
 int kvm_s390_handle_b2(struct kvm_vcpu *vcpu);
diff --git a/arch/s390/kvm/sigp.c b/arch/s390/kvm/sigp.c
index 0ef81d6776e9..40c8c6748cfe 100644
--- a/arch/s390/kvm/sigp.c
+++ b/arch/s390/kvm/sigp.c
@@ -1,7 +1,7 @@
 /*
 * sigp.c - handlinge interprocessor communication
 *
- * Copyright IBM Corp. 2008
+ * Copyright IBM Corp. 2008,2009
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License (version 2 only)
@@ -9,6 +9,7 @@
 *
 *    Author(s): Carsten Otte <cotte@de.ibm.com>
 *               Christian Borntraeger <borntraeger@de.ibm.com>
+ *               Christian Ehrhardt <ehrhardt@de.ibm.com>
 */
 #include <linux/kvm.h>
@@ -107,46 +108,57 @@ unlock:
        return rc;
 }
-static int __sigp_stop(struct kvm_vcpu *vcpu, u16 cpu_addr, int store)
+static int __inject_sigp_stop(struct kvm_s390_local_interrupt *li, int action)
 {
-        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
-        struct kvm_s390_local_interrupt *li;
        struct kvm_s390_interrupt_info *inti;
-        int rc;
-        if (cpu_addr >= KVM_MAX_VCPUS)
-                return 3; /* not operational */
        inti = kzalloc(sizeof(*inti), GFP_KERNEL);
        if (!inti)
                return -ENOMEM;
        inti->type = KVM_S390_SIGP_STOP;
-        spin_lock(&fi->lock);
-        li = fi->local_int[cpu_addr];
-        if (li == NULL) {
-                rc = 3; /* not operational */
-                kfree(inti);
-                goto unlock;
-        }
        spin_lock_bh(&li->lock);
        list_add_tail(&inti->list, &li->list);
        atomic_set(&li->active, 1);
        atomic_set_mask(CPUSTAT_STOP_INT, li->cpuflags);
-        if (store)
+        li->action_bits |= action;
-                li->action_bits |= ACTION_STORE_ON_STOP;
-        li->action_bits |= ACTION_STOP_ON_STOP;
        if (waitqueue_active(&li->wq))
                wake_up_interruptible(&li->wq);
        spin_unlock_bh(&li->lock);
-        rc = 0; /* order accepted */
+        return 0; /* order accepted */
+}
+static int __sigp_stop(struct kvm_vcpu *vcpu, u16 cpu_addr, int action)
+{
+        struct kvm_s390_float_interrupt *fi = &vcpu->kvm->arch.float_int;
+        struct kvm_s390_local_interrupt *li;
+        int rc;
+        if (cpu_addr >= KVM_MAX_VCPUS)
+                return 3; /* not operational */
+        spin_lock(&fi->lock);
+        li = fi->local_int[cpu_addr];
+        if (li == NULL) {
+                rc = 3; /* not operational */
+                goto unlock;
+        }
+        rc = __inject_sigp_stop(li, action);
 unlock:
        spin_unlock(&fi->lock);
        VCPU_EVENT(vcpu, 4, "sent sigp stop to cpu %x", cpu_addr);
        return rc;
 }
+int kvm_s390_inject_sigp_stop(struct kvm_vcpu *vcpu, int action)
+{
+        struct kvm_s390_local_interrupt *li = &vcpu->arch.local_int;
+        return __inject_sigp_stop(li, action);
+}
 static int __sigp_set_arch(struct kvm_vcpu *vcpu, u32 parameter)
 {
        int rc;
@@ -177,9 +189,9 @@ static int __sigp_set_prefix(struct kvm_vcpu *vcpu, u16 cpu_addr, u32 address,
        /* make sure that the new value is valid memory */
        address = address & 0x7fffe000u;
        if ((copy_from_guest(vcpu, &tmp,
-                (u64) (address + vcpu->kvm->arch.guest_origin) , 1)) ||
+                (u64) (address + vcpu->arch.sie_block->gmsor) , 1)) ||
           (copy_from_guest(vcpu, &tmp, (u64) (address +
-                        vcpu->kvm->arch.guest_origin + PAGE_SIZE), 1))) {
+                        vcpu->arch.sie_block->gmsor + PAGE_SIZE), 1))) {
                *reg |= SIGP_STAT_INVALID_PARAMETER;
                return 1; /* invalid parameter */
        }
@@ -262,11 +274,11 @@ int kvm_s390_handle_sigp(struct kvm_vcpu *vcpu)
                break;
        case SIGP_STOP:
                vcpu->stat.instruction_sigp_stop++;
-                rc = __sigp_stop(vcpu, cpu_addr, 0);
+                rc = __sigp_stop(vcpu, cpu_addr, ACTION_STOP_ON_STOP);
                break;
        case SIGP_STOP_STORE_STATUS:
                vcpu->stat.instruction_sigp_stop++;
-                rc = __sigp_stop(vcpu, cpu_addr, 1);
+                rc = __sigp_stop(vcpu, cpu_addr, ACTION_STORE_ON_STOP);
                break;
        case SIGP_SET_ARCH:
                vcpu->stat.instruction_sigp_arch++;
diff --git a/arch/s390/mm/Makefile b/arch/s390/mm/Makefile
index db05661ac895..eec054484419 100644
--- a/arch/s390/mm/Makefile
+++ b/arch/s390/mm/Makefile
@@ -2,7 +2,7 @@
 # Makefile for the linux s390-specific parts of the memory manager.
 #
-obj-y    := init.o fault.o extmem.o mmap.o vmem.o pgtable.o maccess.o
+obj-y    := init.o fault.o extmem.o mmap.o vmem.o pgtable.o maccess.o \
+            page-states.o
 obj-$(CONFIG_CMM) += cmm.o
 obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
-obj-$(CONFIG_PAGE_STATES) += page-states.o
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index e5e119fe03b2..1abbadd497e1 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -10,6 +10,7 @@
 *    Copyright (C) 1995  Linus Torvalds
 */
+#include <linux/perf_counter.h>
 #include <linux/signal.h>
 #include <linux/sched.h>
 #include <linux/kernel.h>
@@ -305,7 +306,7 @@ do_exception(struct pt_regs *regs, unsigned long error_code, int write)
         * interrupts again and then search the VMAs
         */
        local_irq_enable();
+        perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS, 1, 0, regs, address);
        down_read(&mm->mmap_sem);
        si_code = SEGV_MAPERR;
@@ -363,11 +364,15 @@ good_area:
                }
                BUG();
        }
-        if (fault & VM_FAULT_MAJOR)
+        if (fault & VM_FAULT_MAJOR) {
                tsk->maj_flt++;
-        else
+                perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MAJ, 1, 0,
+                                     regs, address);
+        } else {
                tsk->min_flt++;
+                perf_swcounter_event(PERF_COUNT_SW_PAGE_FAULTS_MIN, 1, 0,
+                                     regs, address);
+        }
        up_read(&mm->mmap_sem);
        /*
         * The instruction that caused the program check will
diff --git a/arch/s390/mm/page-states.c b/arch/s390/mm/page-states.c
index fc0ad73ffd90..f92ec203ad92 100644
--- a/arch/s390/mm/page-states.c
+++ b/arch/s390/mm/page-states.c
@@ -1,6 +1,4 @@
 /*
- * arch/s390/mm/page-states.c
- *
 * Copyright IBM Corp. 2008
 *
 * Guest page hinting for unused pages.
@@ -17,11 +15,12 @@
 #define ESSA_SET_STABLE         1
 #define ESSA_SET_UNUSED         2
-static int cmma_flag;
+static int cmma_flag = 1;
 static int __init cmma(char *str)
 {
        char *parm;
        parm = strstrip(str);
        if (strcmp(parm, "yes") == 0 || strcmp(parm, "on") == 0) {
                cmma_flag = 1;
@@ -32,7 +31,6 @@ static int __init cmma(char *str)
                return 1;
        return 0;
 }
 __setup("cmma=", cmma);
 void __init cmma_init(void)
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index 565667207985..c70215247071 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -78,9 +78,9 @@ unsigned long *crst_table_alloc(struct mm_struct *mm, int noexec)
                }
                page->index = page_to_phys(shadow);
        }
-        spin_lock(&mm->page_table_lock);
+        spin_lock(&mm->context.list_lock);
        list_add(&page->lru, &mm->context.crst_list);
-        spin_unlock(&mm->page_table_lock);
+        spin_unlock(&mm->context.list_lock);
        return (unsigned long *) page_to_phys(page);
 }
@@ -89,9 +89,9 @@ void crst_table_free(struct mm_struct *mm, unsigned long *table)
        unsigned long *shadow = get_shadow_table(table);
        struct page *page = virt_to_page(table);
-        spin_lock(&mm->page_table_lock);
+        spin_lock(&mm->context.list_lock);
        list_del(&page->lru);
-        spin_unlock(&mm->page_table_lock);
+        spin_unlock(&mm->context.list_lock);
        if (shadow)
                free_pages((unsigned long) shadow, ALLOC_ORDER);
        free_pages((unsigned long) table, ALLOC_ORDER);
@@ -182,7 +182,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm)
        unsigned long bits;
        bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
-        spin_lock(&mm->page_table_lock);
+        spin_lock(&mm->context.list_lock);
        page = NULL;
        if (!list_empty(&mm->context.pgtable_list)) {
                page = list_first_entry(&mm->context.pgtable_list,
@@ -191,7 +191,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm)
                        page = NULL;
        }
        if (!page) {
-                spin_unlock(&mm->page_table_lock);
+                spin_unlock(&mm->context.list_lock);
                page = alloc_page(GFP_KERNEL|__GFP_REPEAT);
                if (!page)
                        return NULL;
@@ -202,7 +202,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm)
                        clear_table_pgstes(table);
                else
                        clear_table(table, _PAGE_TYPE_EMPTY, PAGE_SIZE);
-                spin_lock(&mm->page_table_lock);
+                spin_lock(&mm->context.list_lock);
                list_add(&page->lru, &mm->context.pgtable_list);
        }
        table = (unsigned long *) page_to_phys(page);
@@ -213,7 +213,7 @@ unsigned long *page_table_alloc(struct mm_struct *mm)
        page->flags |= bits;
        if ((page->flags & FRAG_MASK) == ((1UL << TABLES_PER_PAGE) - 1))
                list_move_tail(&page->lru, &mm->context.pgtable_list);
-        spin_unlock(&mm->page_table_lock);
+        spin_unlock(&mm->context.list_lock);
        return table;
 }
@@ -225,7 +225,7 @@ void page_table_free(struct mm_struct *mm, unsigned long *table)
        bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
        bits <<= (__pa(table) & (PAGE_SIZE - 1)) / 256 / sizeof(unsigned long);
        page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
-        spin_lock(&mm->page_table_lock);
+        spin_lock(&mm->context.list_lock);
        page->flags ^= bits;
        if (page->flags & FRAG_MASK) {
                /* Page now has some free pgtable fragments. */
@@ -234,7 +234,7 @@ void page_table_free(struct mm_struct *mm, unsigned long *table)
        } else
                /* All fragments of the 4K page have been freed. */
                list_del(&page->lru);
-        spin_unlock(&mm->page_table_lock);
+        spin_unlock(&mm->context.list_lock);
        if (page) {
                pgtable_page_dtor(page);
                __free_page(page);
@@ -245,7 +245,7 @@ void disable_noexec(struct mm_struct *mm, struct task_struct *tsk)
 {
        struct page *page;
-        spin_lock(&mm->page_table_lock);
+        spin_lock(&mm->context.list_lock);
        /* Free shadow region and segment tables. */
        list_for_each_entry(page, &mm->context.crst_list, lru)
                if (page->index) {
@@ -255,7 +255,7 @@ void disable_noexec(struct mm_struct *mm, struct task_struct *tsk)
        /* "Free" second halves of page tables. */
        list_for_each_entry(page, &mm->context.pgtable_list, lru)
                page->flags &= ~SECOND_HALVES;
-        spin_unlock(&mm->page_table_lock);
+        spin_unlock(&mm->context.list_lock);
        mm->context.noexec = 0;
        update_mm(mm, tsk);
 }
diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
index e4868bfc672f..5f91a38d7592 100644
--- a/arch/s390/mm/vmem.c
+++ b/arch/s390/mm/vmem.c
@@ -331,6 +331,7 @@ void __init vmem_map_init(void)
        unsigned long start, end;
        int i;
+        spin_lock_init(&init_mm.context.list_lock);
        INIT_LIST_HEAD(&init_mm.context.crst_list);
        INIT_LIST_HEAD(&init_mm.context.pgtable_list);
        init_mm.context.noexec = 0;
diff --git a/arch/s390/power/Makefile b/arch/s390/power/Makefile
deleted file mode 100644
index 973bb45a8fec..000000000000
--- a/arch/s390/power/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for s390 PM support
-#
-obj-$(CONFIG_HIBERNATION) += suspend.o
-obj-$(CONFIG_HIBERNATION) += swsusp.o
-obj-$(CONFIG_HIBERNATION) += swsusp_64.o
-obj-$(CONFIG_HIBERNATION) += swsusp_asm64.o
diff --git a/arch/s390/power/suspend.c b/arch/s390/power/suspend.c
deleted file mode 100644
index b3351eceebbe..000000000000
--- a/arch/s390/power/suspend.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Suspend support specific for s390.
- *
- * Copyright IBM Corp. 2009
- *
- * Author(s): Hans-Joachim Picht <hans@linux.vnet.ibm.com>
- */
-#include <linux/mm.h>
-#include <linux/suspend.h>
-#include <linux/reboot.h>
-#include <linux/pfn.h>
-#include <asm/sections.h>
-#include <asm/ipl.h>
-/*
- * References to section boundaries
- */
-extern const void __nosave_begin, __nosave_end;
-/*
- *  check if given pfn is in the 'nosave' or in the read only NSS section
- */
-int pfn_is_nosave(unsigned long pfn)
-{
-        unsigned long nosave_begin_pfn = __pa(&__nosave_begin) >> PAGE_SHIFT;
-        unsigned long nosave_end_pfn = PAGE_ALIGN(__pa(&__nosave_end))
-                                        >> PAGE_SHIFT;
-        unsigned long eshared_pfn = PFN_DOWN(__pa(&_eshared)) - 1;
-        unsigned long stext_pfn = PFN_DOWN(__pa(&_stext));
-        if (pfn >= nosave_begin_pfn && pfn < nosave_end_pfn)
-                return 1;
-        if (pfn >= stext_pfn && pfn <= eshared_pfn) {
-                if (ipl_info.type == IPL_TYPE_NSS)
-                        return 1;
-        } else if ((tprot(pfn * PAGE_SIZE) && pfn > 0))
-                return 1;
-        return 0;
-}
diff --git a/arch/s390/power/swsusp_64.c b/arch/s390/power/swsusp_64.c
deleted file mode 100644
index 9516a517d72f..000000000000
--- a/arch/s390/power/swsusp_64.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Support for suspend and resume on s390
- *
- * Copyright IBM Corp. 2009
- *
- * Author(s): Hans-Joachim Picht <hans@linux.vnet.ibm.com>
- *
- */
-#include <asm/system.h>
-#include <linux/interrupt.h>
-void do_after_copyback(void)
-{
-        mb();
-}
diff --git a/arch/sh/include/asm/sh_eth.h b/arch/sh/include/asm/sh_eth.h
index bb832584f3c1..acf99700deed 100644
--- a/arch/sh/include/asm/sh_eth.h
+++ b/arch/sh/include/asm/sh_eth.h
@@ -6,6 +6,9 @@ enum {EDMAC_LITTLE_ENDIAN, EDMAC_BIG_ENDIAN};
 struct sh_eth_plat_data {
        int phy;
        int edmac_endian;
+        unsigned no_ether_link:1;
+        unsigned ether_link_active_low:1;
 };
 #endif
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index b5afbec1db59..04a21883f327 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -640,5 +640,7 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned int save_r0,
        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
 }
diff --git a/arch/sh/kernel/signal_64.c b/arch/sh/kernel/signal_64.c
index 0663a0ee6021..9e5c9b1d7e98 100644
--- a/arch/sh/kernel/signal_64.c
+++ b/arch/sh/kernel/signal_64.c
@@ -772,5 +772,7 @@ asmlinkage void do_notify_resume(struct pt_regs *regs, unsigned long thread_info
        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
 }
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 3f8b6a92eabd..2bd5c287538a 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -25,6 +25,9 @@ config SPARC
        select ARCH_WANT_OPTIONAL_GPIOLIB
        select RTC_CLASS
        select RTC_DRV_M48T59
+        select HAVE_PERF_COUNTERS
+        select HAVE_DMA_ATTRS
+        select HAVE_DMA_API_DEBUG
 config SPARC32
        def_bool !64BIT
@@ -44,6 +47,7 @@ config SPARC64
        select RTC_DRV_BQ4802
        select RTC_DRV_SUN4V
        select RTC_DRV_STARFIRE
+        select HAVE_PERF_COUNTERS
 config ARCH_DEFCONFIG
        string
@@ -437,6 +441,17 @@ config SERIAL_CONSOLE
          If unsure, say N.
+config SPARC_LEON
+        bool "Sparc Leon processor family"
+        depends on SPARC32
+        ---help---
+          If you say Y here if you are running on a SPARC-LEON processor.
+          The LEON processor is a synthesizable VHDL model of the
+          SPARC-v8 standard. LEON is  part of the GRLIB collection of
+          IP cores that are distributed under GPL. GRLIB can be downloaded
+          from www.gaisler.com. You can download a sparc-linux cross-compilation
+          toolchain at www.gaisler.com.
 endmenu
 menu "Bus options (PCI etc.)"
diff --git a/arch/sparc/Makefile b/arch/sparc/Makefile
index 2003ded054c2..467221dd5702 100644
--- a/arch/sparc/Makefile
+++ b/arch/sparc/Makefile
@@ -38,10 +38,6 @@ CPPFLAGS_vmlinux.lds += -m32
 #  Actual linking is done with "make image".
 LDFLAGS_vmlinux = -r
-# Default target
-all: zImage
 else
 #####
 # sparc64
@@ -91,6 +87,9 @@ endif
 boot := arch/sparc/boot
+# Default target
+all: zImage
 image zImage tftpboot.img vmlinux.aout: vmlinux
        $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
@@ -109,8 +108,9 @@ define archhelp
 endef
 else
 define archhelp
-  echo  '* vmlinux       - Standard sparc64 kernel'
+  echo  '* vmlinux      - standard sparc64 kernel'
-  echo  '  vmlinux.aout  - a.out kernel for sparc64'
+  echo  '* zImage       - stripped and compressed sparc64 kernel ($(boot)/zImage)'
+  echo  '  vmlinux.aout - a.out kernel for sparc64'
  echo  '  tftpboot.img - image prepared for tftp'
 endef
 endif
diff --git a/arch/sparc/boot/Makefile b/arch/sparc/boot/Makefile
index 1ff0fd924756..97e3feb9ff1b 100644
--- a/arch/sparc/boot/Makefile
+++ b/arch/sparc/boot/Makefile
@@ -79,6 +79,9 @@ $(obj)/image: vmlinux FORCE
        $(call if_changed,strip)
        @echo '  kernel: $@ is ready'
+$(obj)/zImage: $(obj)/image
+        $(call if_changed,gzip)
 $(obj)/tftpboot.img: $(obj)/image $(obj)/piggyback_64 System.map $(ROOT_IMG) FORCE
        $(call if_changed,elftoaout)
        $(call if_changed,piggy)
diff --git a/arch/sparc/include/asm/asi.h b/arch/sparc/include/asm/asi.h
index 74703c5ef985..b2e3db63a64b 100644
--- a/arch/sparc/include/asm/asi.h
+++ b/arch/sparc/include/asm/asi.h
@@ -40,7 +40,11 @@
 #define ASI_M_UNA01         0x01   /* Same here... */
 #define ASI_M_MXCC          0x02   /* Access to TI VIKING MXCC registers */
 #define ASI_M_FLUSH_PROBE   0x03   /* Reference MMU Flush/Probe; rw, ss */
+#ifndef CONFIG_SPARC_LEON
 #define ASI_M_MMUREGS       0x04   /* MMU Registers; rw, ss */
+#else
+#define ASI_M_MMUREGS       0x19
+#endif /* CONFIG_SPARC_LEON */
 #define ASI_M_TLBDIAG       0x05   /* MMU TLB only Diagnostics */
 #define ASI_M_DIAGS         0x06   /* Reference MMU Diagnostics */
 #define ASI_M_IODIAG        0x07   /* MMU I/O TLB only Diagnostics */
diff --git a/arch/sparc/include/asm/device.h b/arch/sparc/include/asm/device.h
index 3702e087df2c..f3b85b6b0b76 100644
--- a/arch/sparc/include/asm/device.h
+++ b/arch/sparc/include/asm/device.h
@@ -32,4 +32,7 @@ dev_archdata_get_node(const struct dev_archdata *ad)
        return ad->prom_node;
 }
+struct pdev_archdata {
+};
 #endif /* _ASM_SPARC_DEVICE_H */
diff --git a/arch/sparc/include/asm/dma-mapping.h b/arch/sparc/include/asm/dma-mapping.h
index 204e4bf64438..5a8c308e2b5c 100644
--- a/arch/sparc/include/asm/dma-mapping.h
+++ b/arch/sparc/include/asm/dma-mapping.h
@@ -3,6 +3,7 @@
 #include <linux/scatterlist.h>
 #include <linux/mm.h>
+#include <linux/dma-debug.h>
 #define DMA_ERROR_CODE  (~(dma_addr_t)0x0)
@@ -13,142 +14,40 @@ extern int dma_set_mask(struct device *dev, u64 dma_mask);
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
 #define dma_is_consistent(d, h) (1)
-struct dma_ops {
+extern struct dma_map_ops *dma_ops, pci32_dma_ops;
-        void *(*alloc_coherent)(struct device *dev, size_t size,
+extern struct bus_type pci_bus_type;
-                                dma_addr_t *dma_handle, gfp_t flag);
-        void (*free_coherent)(struct device *dev, size_t size,
-                              void *cpu_addr, dma_addr_t dma_handle);
-        dma_addr_t (*map_page)(struct device *dev, struct page *page,
-                               unsigned long offset, size_t size,
-                               enum dma_data_direction direction);
-        void (*unmap_page)(struct device *dev, dma_addr_t dma_addr,
-                           size_t size,
-                           enum dma_data_direction direction);
-        int (*map_sg)(struct device *dev, struct scatterlist *sg, int nents,
-                      enum dma_data_direction direction);
-        void (*unmap_sg)(struct device *dev, struct scatterlist *sg,
-                         int nhwentries,
-                         enum dma_data_direction direction);
-        void (*sync_single_for_cpu)(struct device *dev,
-                                    dma_addr_t dma_handle, size_t size,
-                                    enum dma_data_direction direction);
-        void (*sync_single_for_device)(struct device *dev,
-                                       dma_addr_t dma_handle, size_t size,
-                                       enum dma_data_direction direction);
-        void (*sync_sg_for_cpu)(struct device *dev, struct scatterlist *sg,
-                                int nelems,
-                                enum dma_data_direction direction);
-        void (*sync_sg_for_device)(struct device *dev,
-                                   struct scatterlist *sg, int nents,
-                                   enum dma_data_direction dir);
-};
-extern const struct dma_ops *dma_ops;
-static inline void *dma_alloc_coherent(struct device *dev, size_t size,
+static inline struct dma_map_ops *get_dma_ops(struct device *dev)
-                                       dma_addr_t *dma_handle, gfp_t flag)
-{
-        return dma_ops->alloc_coherent(dev, size, dma_handle, flag);
-}
-static inline void dma_free_coherent(struct device *dev, size_t size,
-                                     void *cpu_addr, dma_addr_t dma_handle)
-{
-        dma_ops->free_coherent(dev, size, cpu_addr, dma_handle);
-}
-static inline dma_addr_t dma_map_single(struct device *dev, void *cpu_addr,
-                                        size_t size,
-                                        enum dma_data_direction direction)
-{
-        return dma_ops->map_page(dev, virt_to_page(cpu_addr),
-                                 (unsigned long)cpu_addr & ~PAGE_MASK, size,
-                                 direction);
-}
-static inline void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-                                    size_t size,
-                                    enum dma_data_direction direction)
-{
-        dma_ops->unmap_page(dev, dma_addr, size, direction);
-}
-static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
-                                      unsigned long offset, size_t size,
-                                      enum dma_data_direction direction)
-{
-        return dma_ops->map_page(dev, page, offset, size, direction);
-}
-static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-                                  size_t size,
-                                  enum dma_data_direction direction)
-{
-        dma_ops->unmap_page(dev, dma_address, size, direction);
-}
-static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
-                             int nents, enum dma_data_direction direction)
-{
-        return dma_ops->map_sg(dev, sg, nents, direction);
-}
-static inline void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                                int nents, enum dma_data_direction direction)
 {
-        dma_ops->unmap_sg(dev, sg, nents, direction);
+#if defined(CONFIG_SPARC32) && defined(CONFIG_PCI)
-}
+        if (dev->bus == &pci_bus_type)
+                return &pci32_dma_ops;
-static inline void dma_sync_single_for_cpu(struct device *dev,
+#endif
-                                           dma_addr_t dma_handle, size_t size,
+        return dma_ops;
-                                           enum dma_data_direction direction)
-{
-        dma_ops->sync_single_for_cpu(dev, dma_handle, size, direction);
 }
-static inline void dma_sync_single_for_device(struct device *dev,
+#include <asm-generic/dma-mapping-common.h>
-                                              dma_addr_t dma_handle,
-                                              size_t size,
-                                              enum dma_data_direction direction)
-{
-        if (dma_ops->sync_single_for_device)
-                dma_ops->sync_single_for_device(dev, dma_handle, size,
-                                                direction);
-}
-static inline void dma_sync_sg_for_cpu(struct device *dev,
+static inline void *dma_alloc_coherent(struct device *dev, size_t size,
-                                       struct scatterlist *sg, int nelems,
+                                       dma_addr_t *dma_handle, gfp_t flag)
-                                       enum dma_data_direction direction)
 {
-        dma_ops->sync_sg_for_cpu(dev, sg, nelems, direction);
+        struct dma_map_ops *ops = get_dma_ops(dev);
-}
+        void *cpu_addr;
-static inline void dma_sync_sg_for_device(struct device *dev,
+        cpu_addr = ops->alloc_coherent(dev, size, dma_handle, flag);
-                                          struct scatterlist *sg, int nelems,
+        debug_dma_alloc_coherent(dev, size, *dma_handle, cpu_addr);
-                                          enum dma_data_direction direction)
+        return cpu_addr;
-{
-        if (dma_ops->sync_sg_for_device)
-                dma_ops->sync_sg_for_device(dev, sg, nelems, direction);
 }
-static inline void dma_sync_single_range_for_cpu(struct device *dev,
+static inline void dma_free_coherent(struct device *dev, size_t size,
-                                                 dma_addr_t dma_handle,
+                                     void *cpu_addr, dma_addr_t dma_handle)
-                                                 unsigned long offset,
-                                                 size_t size,
-                                                 enum dma_data_direction dir)
 {
-        dma_sync_single_for_cpu(dev, dma_handle+offset, size, dir);
+        struct dma_map_ops *ops = get_dma_ops(dev);
-}
-static inline void dma_sync_single_range_for_device(struct device *dev,
+        debug_dma_free_coherent(dev, size, cpu_addr, dma_handle);
-                                                    dma_addr_t dma_handle,
+        ops->free_coherent(dev, size, cpu_addr, dma_handle);
-                                                    unsigned long offset,
-                                                    size_t size,
-                                                    enum dma_data_direction dir)
-{
-        dma_sync_single_for_device(dev, dma_handle+offset, size, dir);
 }
 static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 {
        return (dma_addr == DMA_ERROR_CODE);
diff --git a/arch/sparc/include/asm/irq_64.h b/arch/sparc/include/asm/irq_64.h
index 1934f2cbf513..a0b443cb3c1f 100644
--- a/arch/sparc/include/asm/irq_64.h
+++ b/arch/sparc/include/asm/irq_64.h
@@ -89,8 +89,8 @@ static inline unsigned long get_softint(void)
        return retval;
 }
-void __trigger_all_cpu_backtrace(void);
+void arch_trigger_all_cpu_backtrace(void);
-#define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
+#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
 extern void *hardirq_stack[NR_CPUS];
 extern void *softirq_stack[NR_CPUS];
diff --git a/arch/sparc/include/asm/leon.h b/arch/sparc/include/asm/leon.h
new file mode 100644
index 000000000000..28a42b73f64f
--- /dev/null
+++ b/arch/sparc/include/asm/leon.h
@@ -0,0 +1,362 @@
+/*
+ * Copyright (C) 2004 Konrad Eisele (eiselekd@web.de,konrad@gaisler.com) Gaisler Research
+ * Copyright (C) 2004 Stefan Holst (mail@s-holst.de) Uni-Stuttgart
+ * Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB
+ * Copyright (C) 2009 Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB
+ */
+#ifndef LEON_H_INCLUDE
+#define LEON_H_INCLUDE
+#ifdef CONFIG_SPARC_LEON
+#define ASI_LEON_NOCACHE        0x01
+#define ASI_LEON_DCACHE_MISS    0x1
+#define ASI_LEON_CACHEREGS      0x02
+#define ASI_LEON_IFLUSH         0x10
+#define ASI_LEON_DFLUSH         0x11
+#define ASI_LEON_MMUFLUSH       0x18
+#define ASI_LEON_MMUREGS        0x19
+#define ASI_LEON_BYPASS         0x1c
+#define ASI_LEON_FLUSH_PAGE     0x10
+/* mmu register access, ASI_LEON_MMUREGS */
+#define LEON_CNR_CTRL           0x000
+#define LEON_CNR_CTXP           0x100
+#define LEON_CNR_CTX            0x200
+#define LEON_CNR_F              0x300
+#define LEON_CNR_FADDR          0x400
+#define LEON_CNR_CTX_NCTX       256     /*number of MMU ctx */
+#define LEON_CNR_CTRL_TLBDIS    0x80000000
+#define LEON_MMUTLB_ENT_MAX     64
+/*
+ * diagnostic access from mmutlb.vhd:
+ * 0: pte address
+ * 4: pte
+ * 8: additional flags
+ */
+#define LEON_DIAGF_LVL          0x3
+#define LEON_DIAGF_WR           0x8
+#define LEON_DIAGF_WR_SHIFT     3
+#define LEON_DIAGF_HIT          0x10
+#define LEON_DIAGF_HIT_SHIFT    4
+#define LEON_DIAGF_CTX          0x1fe0
+#define LEON_DIAGF_CTX_SHIFT    5
+#define LEON_DIAGF_VALID        0x2000
+#define LEON_DIAGF_VALID_SHIFT  13
+/*
+ *  Interrupt Sources
+ *
+ *  The interrupt source numbers directly map to the trap type and to
+ *  the bits used in the Interrupt Clear, Interrupt Force, Interrupt Mask,
+ *  and the Interrupt Pending Registers.
+ */
+#define LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1
+#define LEON_INTERRUPT_UART_1_RX_TX             2
+#define LEON_INTERRUPT_UART_0_RX_TX             3
+#define LEON_INTERRUPT_EXTERNAL_0               4
+#define LEON_INTERRUPT_EXTERNAL_1               5
+#define LEON_INTERRUPT_EXTERNAL_2               6
+#define LEON_INTERRUPT_EXTERNAL_3               7
+#define LEON_INTERRUPT_TIMER1                   8
+#define LEON_INTERRUPT_TIMER2                   9
+#define LEON_INTERRUPT_EMPTY1                   10
+#define LEON_INTERRUPT_EMPTY2                   11
+#define LEON_INTERRUPT_OPEN_ETH                 12
+#define LEON_INTERRUPT_EMPTY4                   13
+#define LEON_INTERRUPT_EMPTY5                   14
+#define LEON_INTERRUPT_EMPTY6                   15
+/* irq masks */
+#define LEON_HARD_INT(x)        (1 << (x))      /* irq 0-15 */
+#define LEON_IRQMASK_R          0x0000fffe      /* bit 15- 1 of lregs.irqmask */
+#define LEON_IRQPRIO_R          0xfffe0000      /* bit 31-17 of lregs.irqmask */
+/* leon uart register definitions */
+#define LEON_OFF_UDATA  0x0
+#define LEON_OFF_USTAT  0x4
+#define LEON_OFF_UCTRL  0x8
+#define LEON_OFF_USCAL  0xc
+#define LEON_UCTRL_RE   0x01
+#define LEON_UCTRL_TE   0x02
+#define LEON_UCTRL_RI   0x04
+#define LEON_UCTRL_TI   0x08
+#define LEON_UCTRL_PS   0x10
+#define LEON_UCTRL_PE   0x20
+#define LEON_UCTRL_FL   0x40
+#define LEON_UCTRL_LB   0x80
+#define LEON_USTAT_DR   0x01
+#define LEON_USTAT_TS   0x02
+#define LEON_USTAT_TH   0x04
+#define LEON_USTAT_BR   0x08
+#define LEON_USTAT_OV   0x10
+#define LEON_USTAT_PE   0x20
+#define LEON_USTAT_FE   0x40
+#define LEON_MCFG2_SRAMDIS              0x00002000
+#define LEON_MCFG2_SDRAMEN              0x00004000
+#define LEON_MCFG2_SRAMBANKSZ           0x00001e00      /* [12-9] */
+#define LEON_MCFG2_SRAMBANKSZ_SHIFT     9
+#define LEON_MCFG2_SDRAMBANKSZ          0x03800000      /* [25-23] */
+#define LEON_MCFG2_SDRAMBANKSZ_SHIFT    23
+#define LEON_TCNT0_MASK 0x7fffff
+#define LEON_USTAT_ERROR (LEON_USTAT_OV | LEON_USTAT_PE | LEON_USTAT_FE)
+/* no break yet */
+#define ASI_LEON3_SYSCTRL               0x02
+#define ASI_LEON3_SYSCTRL_ICFG          0x08
+#define ASI_LEON3_SYSCTRL_DCFG          0x0c
+#define ASI_LEON3_SYSCTRL_CFG_SNOOPING (1 << 27)
+#define ASI_LEON3_SYSCTRL_CFG_SSIZE(c) (1 << ((c >> 20) & 0xf))
+#ifndef __ASSEMBLY__
+/* do a virtual address read without cache */
+static inline unsigned long leon_readnobuffer_reg(unsigned long paddr)
+{
+        unsigned long retval;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r"(retval) : "r"(paddr), "i"(ASI_LEON_NOCACHE));
+        return retval;
+}
+/* do a physical address bypass write, i.e. for 0x80000000 */
+static inline void leon_store_reg(unsigned long paddr, unsigned long value)
+{
+        __asm__ __volatile__("sta %0, [%1] %2\n\t" : : "r"(value), "r"(paddr),
+                             "i"(ASI_LEON_BYPASS) : "memory");
+}
+/* do a physical address bypass load, i.e. for 0x80000000 */
+static inline unsigned long leon_load_reg(unsigned long paddr)
+{
+        unsigned long retval;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r"(retval) : "r"(paddr), "i"(ASI_LEON_BYPASS));
+        return retval;
+}
+extern inline void leon_srmmu_disabletlb(void)
+{
+        unsigned int retval;
+        __asm__ __volatile__("lda [%%g0] %2, %0\n\t" : "=r"(retval) : "r"(0),
+                             "i"(ASI_LEON_MMUREGS));
+        retval |= LEON_CNR_CTRL_TLBDIS;
+        __asm__ __volatile__("sta %0, [%%g0] %2\n\t" : : "r"(retval), "r"(0),
+                             "i"(ASI_LEON_MMUREGS) : "memory");
+}
+extern inline void leon_srmmu_enabletlb(void)
+{
+        unsigned int retval;
+        __asm__ __volatile__("lda [%%g0] %2, %0\n\t" : "=r"(retval) : "r"(0),
+                             "i"(ASI_LEON_MMUREGS));
+        retval = retval & ~LEON_CNR_CTRL_TLBDIS;
+        __asm__ __volatile__("sta %0, [%%g0] %2\n\t" : : "r"(retval), "r"(0),
+                             "i"(ASI_LEON_MMUREGS) : "memory");
+}
+/* macro access for leon_load_reg() and leon_store_reg() */
+#define LEON3_BYPASS_LOAD_PA(x)     (leon_load_reg((unsigned long)(x)))
+#define LEON3_BYPASS_STORE_PA(x, v) (leon_store_reg((unsigned long)(x), (unsigned long)(v)))
+#define LEON3_BYPASS_ANDIN_PA(x, v) LEON3_BYPASS_STORE_PA(x, LEON3_BYPASS_LOAD_PA(x) & v)
+#define LEON3_BYPASS_ORIN_PA(x, v)  LEON3_BYPASS_STORE_PA(x, LEON3_BYPASS_LOAD_PA(x) | v)
+#define LEON_BYPASS_LOAD_PA(x)      leon_load_reg((unsigned long)(x))
+#define LEON_BYPASS_STORE_PA(x, v)  leon_store_reg((unsigned long)(x), (unsigned long)(v))
+#define LEON_REGLOAD_PA(x)          leon_load_reg((unsigned long)(x)+LEON_PREGS)
+#define LEON_REGSTORE_PA(x, v)      leon_store_reg((unsigned long)(x)+LEON_PREGS, (unsigned long)(v))
+#define LEON_REGSTORE_OR_PA(x, v)   LEON_REGSTORE_PA(x, LEON_REGLOAD_PA(x) | (unsigned long)(v))
+#define LEON_REGSTORE_AND_PA(x, v)  LEON_REGSTORE_PA(x, LEON_REGLOAD_PA(x) & (unsigned long)(v))
+/* macro access for leon_readnobuffer_reg() */
+#define LEON_BYPASSCACHE_LOAD_VA(x) leon_readnobuffer_reg((unsigned long)(x))
+extern void sparc_leon_eirq_register(int eirq);
+extern void leon_init(void);
+extern void leon_switch_mm(void);
+extern void leon_init_IRQ(void);
+extern unsigned long last_valid_pfn;
+extern inline unsigned long sparc_leon3_get_dcachecfg(void)
+{
+        unsigned int retval;
+        __asm__ __volatile__("lda [%1] %2, %0\n\t" :
+                             "=r"(retval) :
+                             "r"(ASI_LEON3_SYSCTRL_DCFG),
+                             "i"(ASI_LEON3_SYSCTRL));
+        return retval;
+}
+/* enable snooping */
+extern inline void sparc_leon3_enable_snooping(void)
+{
+        __asm__ __volatile__ ("lda [%%g0] 2, %%l1\n\t"
+                          "set 0x800000, %%l2\n\t"
+                          "or  %%l2, %%l1, %%l2\n\t"
+                          "sta %%l2, [%%g0] 2\n\t" : : : "l1", "l2");
+};
+extern inline void sparc_leon3_disable_cache(void)
+{
+        __asm__ __volatile__ ("lda [%%g0] 2, %%l1\n\t"
+                          "set 0x00000f, %%l2\n\t"
+                          "andn  %%l2, %%l1, %%l2\n\t"
+                          "sta %%l2, [%%g0] 2\n\t" : : : "l1", "l2");
+};
+#endif /*!__ASSEMBLY__*/
+#ifdef CONFIG_SMP
+# define LEON3_IRQ_RESCHEDULE           13
+# define LEON3_IRQ_TICKER               (leon_percpu_timer_dev[0].irq)
+# define LEON3_IRQ_CROSS_CALL           15
+#endif
+#if defined(PAGE_SIZE_LEON_8K)
+#define LEON_PAGE_SIZE_LEON 1
+#elif defined(PAGE_SIZE_LEON_16K)
+#define LEON_PAGE_SIZE_LEON 2)
+#else
+#define LEON_PAGE_SIZE_LEON 0
+#endif
+#if LEON_PAGE_SIZE_LEON == 0
+/* [ 8, 6, 6 ] + 12 */
+#define LEON_PGD_SH    24
+#define LEON_PGD_M     0xff
+#define LEON_PMD_SH    18
+#define LEON_PMD_SH_V  (LEON_PGD_SH-2)
+#define LEON_PMD_M     0x3f
+#define LEON_PTE_SH    12
+#define LEON_PTE_M     0x3f
+#elif LEON_PAGE_SIZE_LEON == 1
+/* [ 7, 6, 6 ] + 13 */
+#define LEON_PGD_SH    25
+#define LEON_PGD_M     0x7f
+#define LEON_PMD_SH    19
+#define LEON_PMD_SH_V  (LEON_PGD_SH-1)
+#define LEON_PMD_M     0x3f
+#define LEON_PTE_SH    13
+#define LEON_PTE_M     0x3f
+#elif LEON_PAGE_SIZE_LEON == 2
+/* [ 6, 6, 6 ] + 14 */
+#define LEON_PGD_SH    26
+#define LEON_PGD_M     0x3f
+#define LEON_PMD_SH    20
+#define LEON_PMD_SH_V  (LEON_PGD_SH-0)
+#define LEON_PMD_M     0x3f
+#define LEON_PTE_SH    14
+#define LEON_PTE_M     0x3f
+#elif LEON_PAGE_SIZE_LEON == 3
+/* [ 4, 7, 6 ] + 15 */
+#define LEON_PGD_SH    28
+#define LEON_PGD_M     0x0f
+#define LEON_PMD_SH    21
+#define LEON_PMD_SH_V  (LEON_PGD_SH-0)
+#define LEON_PMD_M     0x7f
+#define LEON_PTE_SH    15
+#define LEON_PTE_M     0x3f
+#else
+#error cannot determine LEON_PAGE_SIZE_LEON
+#endif
+#define PAGE_MIN_SHIFT   (12)
+#define PAGE_MIN_SIZE    (1UL << PAGE_MIN_SHIFT)
+#define LEON3_XCCR_SETS_MASK  0x07000000UL
+#define LEON3_XCCR_SSIZE_MASK 0x00f00000UL
+#define LEON2_CCR_DSETS_MASK 0x03000000UL
+#define LEON2_CFG_SSIZE_MASK 0x00007000UL
+#ifndef __ASSEMBLY__
+extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr);
+extern void leon_flush_icache_all(void);
+extern void leon_flush_dcache_all(void);
+extern void leon_flush_cache_all(void);
+extern void leon_flush_tlb_all(void);
+extern int leon_flush_during_switch;
+extern int leon_flush_needed(void);
+struct vm_area_struct;
+extern void leon_flush_icache_all(void);
+extern void leon_flush_dcache_all(void);
+extern void leon_flush_pcache_all(struct vm_area_struct *vma, unsigned long page);
+extern void leon_flush_cache_all(void);
+extern void leon_flush_tlb_all(void);
+extern int leon_flush_during_switch;
+extern int leon_flush_needed(void);
+extern void leon_flush_pcache_all(struct vm_area_struct *vma, unsigned long page);
+/* struct that hold LEON3 cache configuration registers */
+struct leon3_cacheregs {
+        unsigned long ccr;      /* 0x00 - Cache Control Register  */
+        unsigned long iccr;     /* 0x08 - Instruction Cache Configuration Register */
+        unsigned long dccr;     /* 0x0c - Data Cache Configuration Register */
+};
+/* struct that hold LEON2 cache configuration register
+ * & configuration register
+ */
+struct leon2_cacheregs {
+        unsigned long ccr, cfg;
+};
+#ifdef __KERNEL__
+#include <linux/interrupt.h>
+struct device_node;
+extern int sparc_leon_eirq_get(int eirq, int cpu);
+extern irqreturn_t sparc_leon_eirq_isr(int dummy, void *dev_id);
+extern void sparc_leon_eirq_register(int eirq);
+extern void leon_clear_clock_irq(void);
+extern void leon_load_profile_irq(int cpu, unsigned int limit);
+extern void leon_init_timers(irq_handler_t counter_fn);
+extern void leon_clear_clock_irq(void);
+extern void leon_load_profile_irq(int cpu, unsigned int limit);
+extern void leon_trans_init(struct device_node *dp);
+extern void leon_node_init(struct device_node *dp, struct device_node ***nextp);
+extern void leon_init_IRQ(void);
+extern void leon_init(void);
+extern unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr);
+extern void init_leon(void);
+extern void poke_leonsparc(void);
+extern void leon3_getCacheRegs(struct leon3_cacheregs *regs);
+extern int leon_flush_needed(void);
+extern void leon_switch_mm(void);
+extern int srmmu_swprobe_trace;
+#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+/* macros used in leon_mm.c */
+#define PFN(x)           ((x) >> PAGE_SHIFT)
+#define _pfn_valid(pfn)  ((pfn < last_valid_pfn) && (pfn >= PFN(phys_base)))
+#define _SRMMU_PTE_PMASK_LEON 0xffffffff
+#else /* defined(CONFIG_SPARC_LEON) */
+/* nop definitions for !LEON case */
+#define leon_init() do {} while (0)
+#define leon_switch_mm() do {} while (0)
+#define leon_init_IRQ() do {} while (0)
+#define init_leon() do {} while (0)
+#endif /* !defined(CONFIG_SPARC_LEON) */
+#endif
diff --git a/arch/sparc/include/asm/leon_amba.h b/arch/sparc/include/asm/leon_amba.h
new file mode 100644
index 000000000000..618e88821795
--- /dev/null
+++ b/arch/sparc/include/asm/leon_amba.h
@@ -0,0 +1,263 @@
+/*
+*Copyright (C) 2004 Konrad Eisele (eiselekd@web.de,konrad@gaisler.com), Gaisler Research
+*Copyright (C) 2004 Stefan Holst (mail@s-holst.de), Uni-Stuttgart
+*Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com),Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB
+*/
+#ifndef LEON_AMBA_H_INCLUDE
+#define LEON_AMBA_H_INCLUDE
+#ifndef __ASSEMBLY__
+struct amba_prom_registers {
+        unsigned int phys_addr; /* The physical address of this register */
+        unsigned int reg_size;  /* How many bytes does this register take up? */
+};
+#endif
+/*
+ *  The following defines the bits in the LEON UART Status Registers.
+ */
+#define LEON_REG_UART_STATUS_DR   0x00000001    /* Data Ready */
+#define LEON_REG_UART_STATUS_TSE  0x00000002    /* TX Send Register Empty */
+#define LEON_REG_UART_STATUS_THE  0x00000004    /* TX Hold Register Empty */
+#define LEON_REG_UART_STATUS_BR   0x00000008    /* Break Error */
+#define LEON_REG_UART_STATUS_OE   0x00000010    /* RX Overrun Error */
+#define LEON_REG_UART_STATUS_PE   0x00000020    /* RX Parity Error */
+#define LEON_REG_UART_STATUS_FE   0x00000040    /* RX Framing Error */
+#define LEON_REG_UART_STATUS_ERR  0x00000078    /* Error Mask */
+/*
+ *  The following defines the bits in the LEON UART Ctrl Registers.
+ */
+#define LEON_REG_UART_CTRL_RE     0x00000001    /* Receiver enable */
+#define LEON_REG_UART_CTRL_TE     0x00000002    /* Transmitter enable */
+#define LEON_REG_UART_CTRL_RI     0x00000004    /* Receiver interrupt enable */
+#define LEON_REG_UART_CTRL_TI     0x00000008    /* Transmitter irq */
+#define LEON_REG_UART_CTRL_PS     0x00000010    /* Parity select */
+#define LEON_REG_UART_CTRL_PE     0x00000020    /* Parity enable */
+#define LEON_REG_UART_CTRL_FL     0x00000040    /* Flow control enable */
+#define LEON_REG_UART_CTRL_LB     0x00000080    /* Loop Back enable */
+#define LEON3_GPTIMER_EN 1
+#define LEON3_GPTIMER_RL 2
+#define LEON3_GPTIMER_LD 4
+#define LEON3_GPTIMER_IRQEN 8
+#define LEON3_GPTIMER_SEPIRQ 8
+#define LEON23_REG_TIMER_CONTROL_EN    0x00000001 /* 1 = enable counting */
+/* 0 = hold scalar and counter */
+#define LEON23_REG_TIMER_CONTROL_RL    0x00000002 /* 1 = reload at 0 */
+                                                  /* 0 = stop at 0 */
+#define LEON23_REG_TIMER_CONTROL_LD    0x00000004 /* 1 = load counter */
+                                                  /* 0 = no function */
+#define LEON23_REG_TIMER_CONTROL_IQ    0x00000008 /* 1 = irq enable */
+                                                  /* 0 = no function */
+/*
+ *  The following defines the bits in the LEON PS/2 Status Registers.
+ */
+#define LEON_REG_PS2_STATUS_DR   0x00000001     /* Data Ready */
+#define LEON_REG_PS2_STATUS_PE   0x00000002     /* Parity error */
+#define LEON_REG_PS2_STATUS_FE   0x00000004     /* Framing error */
+#define LEON_REG_PS2_STATUS_KI   0x00000008     /* Keyboard inhibit */
+#define LEON_REG_PS2_STATUS_RF   0x00000010     /* RX buffer full */
+#define LEON_REG_PS2_STATUS_TF   0x00000020     /* TX buffer full */
+/*
+ *  The following defines the bits in the LEON PS/2 Ctrl Registers.
+ */
+#define LEON_REG_PS2_CTRL_RE 0x00000001 /* Receiver enable */
+#define LEON_REG_PS2_CTRL_TE 0x00000002 /* Transmitter enable */
+#define LEON_REG_PS2_CTRL_RI 0x00000004 /* Keyboard receive irq  */
+#define LEON_REG_PS2_CTRL_TI 0x00000008 /* Keyboard transmit irq */
+#define LEON3_IRQMPSTATUS_CPUNR     28
+#define LEON3_IRQMPSTATUS_BROADCAST 27
+#define GPTIMER_CONFIG_IRQNT(a)          (((a) >> 3) & 0x1f)
+#define GPTIMER_CONFIG_ISSEP(a)          ((a) & (1 << 8))
+#define GPTIMER_CONFIG_NTIMERS(a)        ((a) & (0x7))
+#define LEON3_GPTIMER_CTRL_PENDING       0x10
+#define LEON3_GPTIMER_CONFIG_NRTIMERS(c) ((c)->config & 0x7)
+#define LEON3_GPTIMER_CTRL_ISPENDING(r)  (((r)&LEON3_GPTIMER_CTRL_PENDING) ? 1 : 0)
+#ifdef CONFIG_SPARC_LEON
+#ifndef __ASSEMBLY__
+struct leon3_irqctrl_regs_map {
+        u32 ilevel;
+        u32 ipend;
+        u32 iforce;
+        u32 iclear;
+        u32 mpstatus;
+        u32 mpbroadcast;
+        u32 notused02;
+        u32 notused03;
+        u32 notused10;
+        u32 notused11;
+        u32 notused12;
+        u32 notused13;
+        u32 notused20;
+        u32 notused21;
+        u32 notused22;
+        u32 notused23;
+        u32 mask[16];
+        u32 force[16];
+        /* Extended IRQ registers */
+        u32 intid[16];  /* 0xc0 */
+};
+struct leon3_apbuart_regs_map {
+        u32 data;
+        u32 status;
+        u32 ctrl;
+        u32 scaler;
+};
+struct leon3_gptimerelem_regs_map {
+        u32 val;
+        u32 rld;
+        u32 ctrl;
+        u32 unused;
+};
+struct leon3_gptimer_regs_map {
+        u32 scalar;
+        u32 scalar_reload;
+        u32 config;
+        u32 unused;
+        struct leon3_gptimerelem_regs_map e[8];
+};
+/*
+ *  Types and structure used for AMBA Plug & Play bus scanning
+ */
+#define AMBA_MAXAPB_DEVS 64
+#define AMBA_MAXAPB_DEVS_PERBUS 16
+struct amba_device_table {
+        int devnr;                 /* number of devices on AHB or APB bus */
+        unsigned int *addr[16];    /* addresses to the devices configuration tables */
+        unsigned int allocbits[1]; /* 0=unallocated, 1=allocated driver */
+};
+struct amba_apbslv_device_table {
+        int devnr;                                /* number of devices on AHB or APB bus */
+        unsigned int *addr[AMBA_MAXAPB_DEVS];     /* addresses to the devices configuration tables */
+        unsigned int apbmst[AMBA_MAXAPB_DEVS];    /* apb master if a entry is a apb slave */
+        unsigned int apbmstidx[AMBA_MAXAPB_DEVS]; /* apb master idx if a entry is a apb slave */
+        unsigned int allocbits[4];                /* 0=unallocated, 1=allocated driver */
+};
+struct amba_confarea_type {
+        struct amba_confarea_type *next;/* next bus in chain */
+        struct amba_device_table ahbmst;
+        struct amba_device_table ahbslv;
+        struct amba_apbslv_device_table apbslv;
+        unsigned int apbmst;
+};
+/* collect apb slaves */
+struct amba_apb_device {
+        unsigned int start, irq, bus_id;
+        struct amba_confarea_type *bus;
+};
+/* collect ahb slaves */
+struct amba_ahb_device {
+        unsigned int start[4], irq, bus_id;
+        struct amba_confarea_type *bus;
+};
+struct device_node;
+void _amba_init(struct device_node *dp, struct device_node ***nextp);
+extern struct leon3_irqctrl_regs_map *leon3_irqctrl_regs;
+extern struct leon3_gptimer_regs_map *leon3_gptimer_regs;
+extern struct amba_apb_device leon_percpu_timer_dev[16];
+extern int leondebug_irq_disable;
+extern int leon_debug_irqout;
+extern unsigned long leon3_gptimer_irq;
+extern unsigned int sparc_leon_eirq;
+#endif /* __ASSEMBLY__ */
+#define LEON3_IO_AREA 0xfff00000
+#define LEON3_CONF_AREA 0xff000
+#define LEON3_AHB_SLAVE_CONF_AREA (1 << 11)
+#define LEON3_AHB_CONF_WORDS 8
+#define LEON3_APB_CONF_WORDS 2
+#define LEON3_AHB_MASTERS 16
+#define LEON3_AHB_SLAVES 16
+#define LEON3_APB_SLAVES 16
+#define LEON3_APBUARTS 8
+/* Vendor codes */
+#define VENDOR_GAISLER   1
+#define VENDOR_PENDER    2
+#define VENDOR_ESA       4
+#define VENDOR_OPENCORES 8
+/* Gaisler Research device id's */
+#define GAISLER_LEON3    0x003
+#define GAISLER_LEON3DSU 0x004
+#define GAISLER_ETHAHB   0x005
+#define GAISLER_APBMST   0x006
+#define GAISLER_AHBUART  0x007
+#define GAISLER_SRCTRL   0x008
+#define GAISLER_SDCTRL   0x009
+#define GAISLER_APBUART  0x00C
+#define GAISLER_IRQMP    0x00D
+#define GAISLER_AHBRAM   0x00E
+#define GAISLER_GPTIMER  0x011
+#define GAISLER_PCITRG   0x012
+#define GAISLER_PCISBRG  0x013
+#define GAISLER_PCIFBRG  0x014
+#define GAISLER_PCITRACE 0x015
+#define GAISLER_PCIDMA   0x016
+#define GAISLER_AHBTRACE 0x017
+#define GAISLER_ETHDSU   0x018
+#define GAISLER_PIOPORT  0x01A
+#define GAISLER_GRGPIO   0x01A
+#define GAISLER_AHBJTAG  0x01c
+#define GAISLER_ETHMAC   0x01D
+#define GAISLER_AHB2AHB  0x020
+#define GAISLER_USBDC    0x021
+#define GAISLER_ATACTRL  0x024
+#define GAISLER_DDRSPA   0x025
+#define GAISLER_USBEHC   0x026
+#define GAISLER_USBUHC   0x027
+#define GAISLER_I2CMST   0x028
+#define GAISLER_SPICTRL  0x02D
+#define GAISLER_DDR2SPA  0x02E
+#define GAISLER_SPIMCTRL 0x045
+#define GAISLER_LEON4    0x048
+#define GAISLER_LEON4DSU 0x049
+#define GAISLER_AHBSTAT  0x052
+#define GAISLER_FTMCTRL  0x054
+#define GAISLER_KBD      0x060
+#define GAISLER_VGA      0x061
+#define GAISLER_SVGA     0x063
+#define GAISLER_GRSYSMON 0x066
+#define GAISLER_GRACECTRL 0x067
+#define GAISLER_L2TIME   0xffd  /* internal device: leon2 timer */
+#define GAISLER_L2C      0xffe  /* internal device: leon2compat */
+#define GAISLER_PLUGPLAY 0xfff  /* internal device: plug & play configarea */
+#define amba_vendor(x) (((x) >> 24) & 0xff)
+#define amba_device(x) (((x) >> 12) & 0xfff)
+#endif /* !defined(CONFIG_SPARC_LEON) */
+#endif
diff --git a/arch/sparc/include/asm/machines.h b/arch/sparc/include/asm/machines.h
index c28c2f248794..cd9c099567e4 100644
--- a/arch/sparc/include/asm/machines.h
+++ b/arch/sparc/include/asm/machines.h
@@ -15,7 +15,7 @@ struct Sun_Machine_Models {
 /* Current number of machines we know about that has an IDPROM
 * machtype entry including one entry for the 0x80 OBP machines.
 */
-#define NUM_SUN_MACHINES   15
+#define NUM_SUN_MACHINES   16
 /* The machine type in the idprom area looks like this:
 *
@@ -30,6 +30,7 @@ struct Sun_Machine_Models {
 #define SM_ARCH_MASK  0xf0
 #define SM_SUN4       0x20
+#define  M_LEON       0x30
 #define SM_SUN4C      0x50
 #define SM_SUN4M      0x70
 #define SM_SUN4M_OBP  0x80
@@ -41,6 +42,9 @@ struct Sun_Machine_Models {
 #define SM_4_330      0x03    /* Sun 4/300 series */
 #define SM_4_470      0x04    /* Sun 4/400 series */
+/* Leon machines */
+#define M_LEON3_SOC   0x02    /* Leon3 SoC */
 /* Sun4c machines                Full Name              - PROM NAME */
 #define SM_4C_SS1     0x01    /* Sun4c SparcStation 1   - Sun 4/60  */
 #define SM_4C_IPC     0x02    /* Sun4c SparcStation IPC - Sun 4/40  */
diff --git a/arch/sparc/include/asm/nmi.h b/arch/sparc/include/asm/nmi.h
index fbd546dd4feb..72e6500e7ab0 100644
--- a/arch/sparc/include/asm/nmi.h
+++ b/arch/sparc/include/asm/nmi.h
@@ -5,6 +5,9 @@ extern int __init nmi_init(void);
 extern void perfctr_irq(int irq, struct pt_regs *regs);
 extern void nmi_adjust_hz(unsigned int new_hz);
-extern int nmi_usable;
+extern atomic_t nmi_active;
+extern void start_nmi_watchdog(void *unused);
+extern void stop_nmi_watchdog(void *unused);
 #endif /* __NMI_H */
diff --git a/arch/sparc/include/asm/pci.h b/arch/sparc/include/asm/pci.h
index 6e14fd179335..d9c031f9910f 100644
--- a/arch/sparc/include/asm/pci.h
+++ b/arch/sparc/include/asm/pci.h
@@ -5,4 +5,7 @@
 #else
 #include <asm/pci_32.h>
 #endif
+#include <asm-generic/pci-dma-compat.h>
 #endif
diff --git a/arch/sparc/include/asm/pci_32.h b/arch/sparc/include/asm/pci_32.h
index b41c4c198159..ac0e8369fd97 100644
--- a/arch/sparc/include/asm/pci_32.h
+++ b/arch/sparc/include/asm/pci_32.h
@@ -31,42 +31,8 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
 */
 #define PCI_DMA_BUS_IS_PHYS     (0)
-#include <asm/scatterlist.h>
 struct pci_dev;
-/* Allocate and map kernel buffer using consistent mode DMA for a device.
- * hwdev should be valid struct pci_dev pointer for PCI devices.
- */
-extern void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, dma_addr_t *dma_handle);
-/* Free and unmap a consistent DMA buffer.
- * cpu_addr is what was returned from pci_alloc_consistent,
- * size must be the same as what as passed into pci_alloc_consistent,
- * and likewise dma_addr must be the same as what *dma_addrp was set to.
- *
- * References to the memory and mappings assosciated with cpu_addr/dma_addr
- * past this call are illegal.
- */
-extern void pci_free_consistent(struct pci_dev *hwdev, size_t size, void *vaddr, dma_addr_t dma_handle);
-/* Map a single buffer of the indicated size for DMA in streaming mode.
- * The 32-bit bus address to use is returned.
- *
- * Once the device is given the dma address, the device owns this memory
- * until either pci_unmap_single or pci_dma_sync_single_for_cpu is performed.
- */
-extern dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size, int direction);
-/* Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guaranteed to see
- * whatever the device wrote there.
- */
-extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t size, int direction);
 /* pci_unmap_{single,page} is not a nop, thus... */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
        dma_addr_t ADDR_NAME;
@@ -81,69 +47,6 @@ extern void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr, size_t
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
        (((PTR)->LEN_NAME) = (VAL))
-/*
- * Same as above, only with pages instead of mapped addresses.
- */
-extern dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
-                        unsigned long offset, size_t size, int direction);
-extern void pci_unmap_page(struct pci_dev *hwdev,
-                        dma_addr_t dma_address, size_t size, int direction);
-/* Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-extern int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nents, int direction);
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-extern void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg, int nhwents, int direction);
-/* Make physical memory consistent for a single
- * streaming mode DMA translation after a transfer.
- *
- * If you perform a pci_map_single() but wish to interrogate the
- * buffer using the cpu, yet do not wish to teardown the PCI dma
- * mapping, you must call this function before doing so.  At the
- * next point you give the PCI dma address back to the card, you
- * must first perform a pci_dma_sync_for_device, and then the device
- * again owns the buffer.
- */
-extern void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
-extern void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t dma_handle, size_t size, int direction);
-/* Make physical memory consistent for a set of streaming
- * mode DMA translations after a transfer.
- *
- * The same as pci_dma_sync_single_* but for a scatter-gather list,
- * same rules and usage.
- */
-extern void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
-extern void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sg, int nelems, int direction);
-/* Return whether the given PCI device DMA address mask can
- * be supported properly.  For example, if your device can
- * only drive the low 24-bits during PCI bus mastering, then
- * you would pass 0x00ffffff as the mask to this function.
- */
-static inline int pci_dma_supported(struct pci_dev *hwdev, u64 mask)
-{
-        return 1;
-}
 #ifdef CONFIG_PCI
 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
                                        enum pci_dma_burst_strategy *strat,
@@ -154,14 +57,6 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev,
 }
 #endif
-#define PCI_DMA_ERROR_CODE      (~(dma_addr_t)0x0)
-static inline int pci_dma_mapping_error(struct pci_dev *pdev,
-                                        dma_addr_t dma_addr)
-{
-        return (dma_addr == PCI_DMA_ERROR_CODE);
-}
 struct device_node;
 extern struct device_node *pci_device_to_OF_node(struct pci_dev *pdev);
diff --git a/arch/sparc/include/asm/pci_64.h b/arch/sparc/include/asm/pci_64.h
index 7a1e3566e59c..5cc9f6aa5494 100644
--- a/arch/sparc/include/asm/pci_64.h
+++ b/arch/sparc/include/asm/pci_64.h
@@ -35,37 +35,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
 */
 #define PCI_DMA_BUS_IS_PHYS     (0)
-static inline void *pci_alloc_consistent(struct pci_dev *pdev, size_t size,
-                                         dma_addr_t *dma_handle)
-{
-        return dma_alloc_coherent(&pdev->dev, size, dma_handle, GFP_ATOMIC);
-}
-static inline void pci_free_consistent(struct pci_dev *pdev, size_t size,
-                                       void *vaddr, dma_addr_t dma_handle)
-{
-        return dma_free_coherent(&pdev->dev, size, vaddr, dma_handle);
-}
-static inline dma_addr_t pci_map_single(struct pci_dev *pdev, void *ptr,
-                                        size_t size, int direction)
-{
-        return dma_map_single(&pdev->dev, ptr, size,
-                              (enum dma_data_direction) direction);
-}
-static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
-                                    size_t size, int direction)
-{
-        dma_unmap_single(&pdev->dev, dma_addr, size,
-                         (enum dma_data_direction) direction);
-}
-#define pci_map_page(dev, page, off, size, dir) \
-        pci_map_single(dev, (page_address(page) + (off)), size, dir)
-#define pci_unmap_page(dev,addr,sz,dir) \
-        pci_unmap_single(dev,addr,sz,dir)
 /* pci_unmap_{single,page} is not a nop, thus... */
 #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
        dma_addr_t ADDR_NAME;
@@ -80,57 +49,6 @@ static inline void pci_unmap_single(struct pci_dev *pdev, dma_addr_t dma_addr,
 #define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
        (((PTR)->LEN_NAME) = (VAL))
-static inline int pci_map_sg(struct pci_dev *pdev, struct scatterlist *sg,
-                             int nents, int direction)
-{
-        return dma_map_sg(&pdev->dev, sg, nents,
-                          (enum dma_data_direction) direction);
-}
-static inline void pci_unmap_sg(struct pci_dev *pdev, struct scatterlist *sg,
-                                int nents, int direction)
-{
-        dma_unmap_sg(&pdev->dev, sg, nents,
-                     (enum dma_data_direction) direction);
-}
-static inline void pci_dma_sync_single_for_cpu(struct pci_dev *pdev,
-                                               dma_addr_t dma_handle,
-                                               size_t size, int direction)
-{
-        dma_sync_single_for_cpu(&pdev->dev, dma_handle, size,
-                                (enum dma_data_direction) direction);
-}
-static inline void pci_dma_sync_single_for_device(struct pci_dev *pdev,
-                                                  dma_addr_t dma_handle,
-                                                  size_t size, int direction)
-{
-        /* No flushing needed to sync cpu writes to the device.  */
-}
-static inline void pci_dma_sync_sg_for_cpu(struct pci_dev *pdev,
-                                           struct scatterlist *sg,
-                                           int nents, int direction)
-{
-        dma_sync_sg_for_cpu(&pdev->dev, sg, nents,
-                            (enum dma_data_direction) direction);
-}
-static inline void pci_dma_sync_sg_for_device(struct pci_dev *pdev,
-                                              struct scatterlist *sg,
-                                              int nelems, int direction)
-{
-        /* No flushing needed to sync cpu writes to the device.  */
-}
-/* Return whether the given PCI device DMA address mask can
- * be supported properly.  For example, if your device can
- * only drive the low 24-bits during PCI bus mastering, then
- * you would pass 0x00ffffff as the mask to this function.
- */
-extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
 /* PCI IOMMU mapping bypass support. */
 /* PCI 64-bit addressing works for all slots on all controller
@@ -140,12 +58,6 @@ extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
 #define PCI64_REQUIRED_MASK     (~(dma64_addr_t)0)
 #define PCI64_ADDR_BASE         0xfffc000000000000UL
-static inline int pci_dma_mapping_error(struct pci_dev *pdev,
-                                        dma_addr_t dma_addr)
-{
-        return dma_mapping_error(&pdev->dev, dma_addr);
-}
 #ifdef CONFIG_PCI
 static inline void pci_dma_burst_advice(struct pci_dev *pdev,
                                        enum pci_dma_burst_strategy *strat,
diff --git a/arch/sparc/include/asm/perf_counter.h b/arch/sparc/include/asm/perf_counter.h
new file mode 100644
index 000000000000..5d7a8ca0e491
--- /dev/null
+++ b/arch/sparc/include/asm/perf_counter.h
@@ -0,0 +1,14 @@
+#ifndef __ASM_SPARC_PERF_COUNTER_H
+#define __ASM_SPARC_PERF_COUNTER_H
+extern void set_perf_counter_pending(void);
+#define PERF_COUNTER_INDEX_OFFSET       0
+#ifdef CONFIG_PERF_COUNTERS
+extern void init_hw_perf_counters(void);
+#else
+static inline void init_hw_perf_counters(void)  { }
+#endif
+#endif
diff --git a/arch/sparc/include/asm/pgtsrmmu.h b/arch/sparc/include/asm/pgtsrmmu.h
index 808555fc1d58..1407c07bdade 100644
--- a/arch/sparc/include/asm/pgtsrmmu.h
+++ b/arch/sparc/include/asm/pgtsrmmu.h
@@ -267,6 +267,7 @@ static inline void srmmu_flush_tlb_page(unsigned long page)
 }
+#ifndef CONFIG_SPARC_LEON
 static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
 {
        unsigned long retval;
@@ -278,6 +279,9 @@ static inline unsigned long srmmu_hwprobe(unsigned long vaddr)
        return retval;
 }
+#else
+#define srmmu_hwprobe(addr) (srmmu_swprobe(addr, 0) & SRMMU_PTE_PMASK)
+#endif
 static inline int
 srmmu_get_pte (unsigned long addr)
diff --git a/arch/sparc/include/asm/prom.h b/arch/sparc/include/asm/prom.h
index be8d7aaeb60d..82a190d7efc1 100644
--- a/arch/sparc/include/asm/prom.h
+++ b/arch/sparc/include/asm/prom.h
@@ -118,5 +118,8 @@ extern struct device_node *of_console_device;
 extern char *of_console_path;
 extern char *of_console_options;
+extern void (*prom_build_more)(struct device_node *dp, struct device_node ***nextp);
+extern char *build_full_name(struct device_node *dp);
 #endif /* __KERNEL__ */
 #endif /* _SPARC_PROM_H */
diff --git a/arch/sparc/include/asm/socket.h b/arch/sparc/include/asm/socket.h
index 982a12f959f4..3a5ae3d12088 100644
--- a/arch/sparc/include/asm/socket.h
+++ b/arch/sparc/include/asm/socket.h
@@ -29,6 +29,9 @@
 #define SO_RCVBUFFORCE  0x100b
 #define SO_ERROR        0x1007
 #define SO_TYPE         0x1008
+#define SO_PROTOCOL     0x1028
+#define SO_DOMAIN       0x1029
 /* Linux specific, keep the same. */
 #define SO_NO_CHECK     0x000b
diff --git a/arch/sparc/include/asm/spinlock_32.h b/arch/sparc/include/asm/spinlock_32.h
index 46f91ab66a50..857630cff636 100644
--- a/arch/sparc/include/asm/spinlock_32.h
+++ b/arch/sparc/include/asm/spinlock_32.h
@@ -76,7 +76,7 @@ static inline void __raw_spin_unlock(raw_spinlock_t *lock)
 *
 * Unfortunately this scheme limits us to ~16,000,000 cpus.
 */
-static inline void __read_lock(raw_rwlock_t *rw)
+static inline void arch_read_lock(raw_rwlock_t *rw)
 {
        register raw_rwlock_t *lp asm("g1");
        lp = rw;
@@ -92,11 +92,11 @@ static inline void __read_lock(raw_rwlock_t *rw)
 #define __raw_read_lock(lock) \
 do {    unsigned long flags; \
        local_irq_save(flags); \
-        __read_lock(lock); \
+        arch_read_lock(lock); \
        local_irq_restore(flags); \
 } while(0)
-static inline void __read_unlock(raw_rwlock_t *rw)
+static inline void arch_read_unlock(raw_rwlock_t *rw)
 {
        register raw_rwlock_t *lp asm("g1");
        lp = rw;
@@ -112,7 +112,7 @@ static inline void __read_unlock(raw_rwlock_t *rw)
 #define __raw_read_unlock(lock) \
 do {    unsigned long flags; \
        local_irq_save(flags); \
-        __read_unlock(lock); \
+        arch_read_unlock(lock); \
        local_irq_restore(flags); \
 } while(0)
@@ -150,7 +150,7 @@ static inline int __raw_write_trylock(raw_rwlock_t *rw)
        return (val == 0);
 }
-static inline int __read_trylock(raw_rwlock_t *rw)
+static inline int arch_read_trylock(raw_rwlock_t *rw)
 {
        register raw_rwlock_t *lp asm("g1");
        register int res asm("o0");
@@ -169,7 +169,7 @@ static inline int __read_trylock(raw_rwlock_t *rw)
 ({      unsigned long flags; \
        int res; \
        local_irq_save(flags); \
-        res = __read_trylock(lock); \
+        res = arch_read_trylock(lock); \
        local_irq_restore(flags); \
        res; \
 })
diff --git a/arch/sparc/include/asm/spinlock_64.h b/arch/sparc/include/asm/spinlock_64.h
index f6b2b92ad8d2..43e514783582 100644
--- a/arch/sparc/include/asm/spinlock_64.h
+++ b/arch/sparc/include/asm/spinlock_64.h
@@ -92,7 +92,7 @@ static inline void __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long fla
 /* Multi-reader locks, these are much saner than the 32-bit Sparc ones... */
-static void inline __read_lock(raw_rwlock_t *lock)
+static void inline arch_read_lock(raw_rwlock_t *lock)
 {
        unsigned long tmp1, tmp2;
@@ -115,7 +115,7 @@ static void inline __read_lock(raw_rwlock_t *lock)
        : "memory");
 }
-static int inline __read_trylock(raw_rwlock_t *lock)
+static int inline arch_read_trylock(raw_rwlock_t *lock)
 {
        int tmp1, tmp2;
@@ -136,7 +136,7 @@ static int inline __read_trylock(raw_rwlock_t *lock)
        return tmp1;
 }
-static void inline __read_unlock(raw_rwlock_t *lock)
+static void inline arch_read_unlock(raw_rwlock_t *lock)
 {
        unsigned long tmp1, tmp2;
@@ -152,7 +152,7 @@ static void inline __read_unlock(raw_rwlock_t *lock)
        : "memory");
 }
-static void inline __write_lock(raw_rwlock_t *lock)
+static void inline arch_write_lock(raw_rwlock_t *lock)
 {
        unsigned long mask, tmp1, tmp2;
@@ -177,7 +177,7 @@ static void inline __write_lock(raw_rwlock_t *lock)
        : "memory");
 }
-static void inline __write_unlock(raw_rwlock_t *lock)
+static void inline arch_write_unlock(raw_rwlock_t *lock)
 {
        __asm__ __volatile__(
 "       stw             %%g0, [%0]"
@@ -186,7 +186,7 @@ static void inline __write_unlock(raw_rwlock_t *lock)
        : "memory");
 }
-static int inline __write_trylock(raw_rwlock_t *lock)
+static int inline arch_write_trylock(raw_rwlock_t *lock)
 {
        unsigned long mask, tmp1, tmp2, result;
@@ -210,14 +210,14 @@ static int inline __write_trylock(raw_rwlock_t *lock)
        return result;
 }
-#define __raw_read_lock(p)      __read_lock(p)
+#define __raw_read_lock(p)      arch_read_lock(p)
-#define __raw_read_lock_flags(p, f) __read_lock(p)
+#define __raw_read_lock_flags(p, f) arch_read_lock(p)
-#define __raw_read_trylock(p)   __read_trylock(p)
+#define __raw_read_trylock(p)   arch_read_trylock(p)
-#define __raw_read_unlock(p)    __read_unlock(p)
+#define __raw_read_unlock(p)    arch_read_unlock(p)
-#define __raw_write_lock(p)     __write_lock(p)
+#define __raw_write_lock(p)     arch_write_lock(p)
-#define __raw_write_lock_flags(p, f) __write_lock(p)
+#define __raw_write_lock_flags(p, f) arch_write_lock(p)
-#define __raw_write_unlock(p)   __write_unlock(p)
+#define __raw_write_unlock(p)   arch_write_unlock(p)
-#define __raw_write_trylock(p)  __write_trylock(p)
+#define __raw_write_trylock(p)  arch_write_trylock(p)
 #define __raw_read_can_lock(rw)         (!((rw)->lock & 0x80000000UL))
 #define __raw_write_can_lock(rw)        (!(rw)->lock)
diff --git a/arch/sparc/include/asm/system_32.h b/arch/sparc/include/asm/system_32.h
index 751c8c17f5a0..890036b3689a 100644
--- a/arch/sparc/include/asm/system_32.h
+++ b/arch/sparc/include/asm/system_32.h
@@ -32,6 +32,7 @@ enum sparc_cpu {
  sun4u       = 0x05, /* V8 ploos ploos */
  sun_unknown = 0x06,
  ap1000      = 0x07, /* almost a sun4m */
+  sparc_leon  = 0x08, /* Leon SoC */
 };
 /* Really, userland should not be looking at any of this... */
diff --git a/arch/sparc/include/asm/system_64.h b/arch/sparc/include/asm/system_64.h
index 6c077816ab28..25e848f0cad7 100644
--- a/arch/sparc/include/asm/system_64.h
+++ b/arch/sparc/include/asm/system_64.h
@@ -29,6 +29,10 @@ enum sparc_cpu {
 /* This cannot ever be a sun4c :) That's just history. */
 #define ARCH_SUN4C 0
+extern const char *sparc_cpu_type;
+extern const char *sparc_fpu_type;
+extern const char *sparc_pmu_type;
 extern char reboot_command[];
 /* These are here in an effort to more fully work around Spitfire Errata
diff --git a/arch/sparc/include/asm/types.h b/arch/sparc/include/asm/types.h
index de671d73baed..09c79a9c8516 100644
--- a/arch/sparc/include/asm/types.h
+++ b/arch/sparc/include/asm/types.h
@@ -8,9 +8,8 @@
 * need to be careful to avoid a name clashes.
 */
-#if defined(__sparc__) && defined(__arch64__)
+#if defined(__sparc__)
-/*** SPARC 64 bit ***/
 #include <asm-generic/int-ll64.h>
 #ifndef __ASSEMBLY__
@@ -26,33 +25,21 @@ typedef unsigned short umode_t;
 /* Dma addresses come in generic and 64-bit flavours.  */
 typedef u32 dma_addr_t;
-typedef u64 dma64_addr_t;
-#endif /* __ASSEMBLY__ */
+#if defined(__arch64__)
-#endif /* __KERNEL__ */
+/*** SPARC 64 bit ***/
+typedef u64 dma64_addr_t;
 #else
 /*** SPARC 32 bit ***/
-#include <asm-generic/int-ll64.h>
-#ifndef __ASSEMBLY__
-typedef unsigned short umode_t;
-#endif /* __ASSEMBLY__ */
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-typedef u32 dma_addr_t;
 typedef u32 dma64_addr_t;
+#endif /* defined(__arch64__) */
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
-#endif /* defined(__sparc__) && defined(__arch64__) */
+#endif /* defined(__sparc__) */
 #endif /* defined(_SPARC_TYPES_H) */
diff --git a/arch/sparc/include/asm/uaccess_64.h b/arch/sparc/include/asm/uaccess_64.h
index a38c03238918..9ea271e19c70 100644
--- a/arch/sparc/include/asm/uaccess_64.h
+++ b/arch/sparc/include/asm/uaccess_64.h
@@ -7,8 +7,8 @@
 #ifdef __KERNEL__
 #include <linux/compiler.h>
-#include <linux/sched.h>
 #include <linux/string.h>
+#include <linux/thread_info.h>
 #include <asm/asi.h>
 #include <asm/system.h>
 #include <asm/spitfire.h>
diff --git a/arch/sparc/include/asm/unistd.h b/arch/sparc/include/asm/unistd.h
index b2c406de7d4f..706df669f3b8 100644
--- a/arch/sparc/include/asm/unistd.h
+++ b/arch/sparc/include/asm/unistd.h
@@ -395,8 +395,9 @@
 #define __NR_preadv             324
 #define __NR_pwritev            325
 #define __NR_rt_tgsigqueueinfo  326
+#define __NR_perf_counter_open  327
-#define NR_SYSCALLS             327
+#define NR_SYSCALLS             328
 #ifdef __32bit_syscall_numbers__
 /* Sparc 32-bit only has the "setresuid32", "getresuid32" variants,
diff --git a/arch/sparc/kernel/Makefile b/arch/sparc/kernel/Makefile
index 475ce4696acd..247cc620cee5 100644
--- a/arch/sparc/kernel/Makefile
+++ b/arch/sparc/kernel/Makefile
@@ -41,6 +41,8 @@ obj-y                   += of_device_common.o
 obj-y                   += of_device_$(BITS).o
 obj-$(CONFIG_SPARC64)   += prom_irqtrans.o
+obj-$(CONFIG_SPARC_LEON)+= leon_kernel.o
 obj-$(CONFIG_SPARC64)   += reboot.o
 obj-$(CONFIG_SPARC64)   += sysfs.o
 obj-$(CONFIG_SPARC64)   += iommu.o
@@ -61,7 +63,7 @@ obj-$(CONFIG_SPARC64_SMP) += cpumap.o
 obj-$(CONFIG_SPARC32)     += devres.o
 devres-y                  := ../../../kernel/irq/devres.o
-obj-$(CONFIG_SPARC32)     += dma.o
+obj-y                     += dma.o
 obj-$(CONFIG_SPARC32_PCI) += pcic.o
@@ -101,3 +103,6 @@ obj-$(CONFIG_SUN_LDOMS) += ldc.o vio.o viohs.o ds.o
 obj-$(CONFIG_AUDIT)     += audit.o
 audit--$(CONFIG_AUDIT)  := compat_audit.o
 obj-$(CONFIG_COMPAT)    += $(audit--y)
+pc--$(CONFIG_PERF_COUNTERS) := perf_counter.o
+obj-$(CONFIG_SPARC64)   += $(pc--y)
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index d85c3dc4953a..1446df90ef85 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -312,7 +312,12 @@ void __cpuinit cpu_probe(void)
        psr = get_psr();
        put_psr(psr | PSR_EF);
+#ifdef CONFIG_SPARC_LEON
+        fpu_vers = 7;
+#else
        fpu_vers = ((get_fsr() >> 17) & 0x7);
+#endif
        put_psr(psr);
        set_cpu_and_fpu(psr_impl, psr_vers, fpu_vers);
diff --git a/arch/sparc/kernel/dma.c b/arch/sparc/kernel/dma.c
index 524c32f97c55..e1ba8ee21b9a 100644
--- a/arch/sparc/kernel/dma.c
+++ b/arch/sparc/kernel/dma.c
@@ -1,178 +1,13 @@
-/* dma.c: PCI and SBUS DMA accessors for 32-bit sparc.
- *
- * Copyright (C) 2008 David S. Miller <davem@davemloft.net>
- */
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/dma-mapping.h>
-#include <linux/scatterlist.h>
+#include <linux/dma-debug.h>
-#include <linux/mm.h>
-#ifdef CONFIG_PCI
-#include <linux/pci.h>
-#endif
-#include "dma.h"
+#define PREALLOC_DMA_DEBUG_ENTRIES       (1 << 15)
-int dma_supported(struct device *dev, u64 mask)
+static int __init dma_init(void)
 {
-#ifdef CONFIG_PCI
+        dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
-        if (dev->bus == &pci_bus_type)
-                return pci_dma_supported(to_pci_dev(dev), mask);
-#endif
        return 0;
 }
-EXPORT_SYMBOL(dma_supported);
+fs_initcall(dma_init);
-int dma_set_mask(struct device *dev, u64 dma_mask)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type)
-                return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
-#endif
-        return -EOPNOTSUPP;
-}
-EXPORT_SYMBOL(dma_set_mask);
-static void *dma32_alloc_coherent(struct device *dev, size_t size,
-                                  dma_addr_t *dma_handle, gfp_t flag)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type)
-                return pci_alloc_consistent(to_pci_dev(dev), size, dma_handle);
-#endif
-        return sbus_alloc_consistent(dev, size, dma_handle);
-}
-static void dma32_free_coherent(struct device *dev, size_t size,
-                                void *cpu_addr, dma_addr_t dma_handle)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_free_consistent(to_pci_dev(dev), size,
-                                    cpu_addr, dma_handle);
-                return;
-        }
-#endif
-        sbus_free_consistent(dev, size, cpu_addr, dma_handle);
-}
-static dma_addr_t dma32_map_page(struct device *dev, struct page *page,
-                                 unsigned long offset, size_t size,
-                                 enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type)
-                return pci_map_page(to_pci_dev(dev), page, offset,
-                                    size, (int)direction);
-#endif
-        return sbus_map_single(dev, page_address(page) + offset,
-                               size, (int)direction);
-}
-static void dma32_unmap_page(struct device *dev, dma_addr_t dma_address,
-                             size_t size, enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_unmap_page(to_pci_dev(dev), dma_address,
-                               size, (int)direction);
-                return;
-        }
-#endif
-        sbus_unmap_single(dev, dma_address, size, (int)direction);
-}
-static int dma32_map_sg(struct device *dev, struct scatterlist *sg,
-                        int nents, enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type)
-                return pci_map_sg(to_pci_dev(dev), sg, nents, (int)direction);
-#endif
-        return sbus_map_sg(dev, sg, nents, direction);
-}
-void dma32_unmap_sg(struct device *dev, struct scatterlist *sg,
-                    int nents, enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_unmap_sg(to_pci_dev(dev), sg, nents, (int)direction);
-                return;
-        }
-#endif
-        sbus_unmap_sg(dev, sg, nents, (int)direction);
-}
-static void dma32_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-                                      size_t size,
-                                      enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_dma_sync_single_for_cpu(to_pci_dev(dev), dma_handle,
-                                            size, (int)direction);
-                return;
-        }
-#endif
-        sbus_dma_sync_single_for_cpu(dev, dma_handle, size, (int) direction);
-}
-static void dma32_sync_single_for_device(struct device *dev,
-                                         dma_addr_t dma_handle, size_t size,
-                                         enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_dma_sync_single_for_device(to_pci_dev(dev), dma_handle,
-                                               size, (int)direction);
-                return;
-        }
-#endif
-        sbus_dma_sync_single_for_device(dev, dma_handle, size, (int) direction);
-}
-static void dma32_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
-                                  int nelems, enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_dma_sync_sg_for_cpu(to_pci_dev(dev), sg,
-                                        nelems, (int)direction);
-                return;
-        }
-#endif
-        BUG();
-}
-static void dma32_sync_sg_for_device(struct device *dev,
-                                     struct scatterlist *sg, int nelems,
-                                     enum dma_data_direction direction)
-{
-#ifdef CONFIG_PCI
-        if (dev->bus == &pci_bus_type) {
-                pci_dma_sync_sg_for_device(to_pci_dev(dev), sg,
-                                           nelems, (int)direction);
-                return;
-        }
-#endif
-        BUG();
-}
-static const struct dma_ops dma32_dma_ops = {
-        .alloc_coherent         = dma32_alloc_coherent,
-        .free_coherent          = dma32_free_coherent,
-        .map_page               = dma32_map_page,
-        .unmap_page             = dma32_unmap_page,
-        .map_sg                 = dma32_map_sg,
-        .unmap_sg               = dma32_unmap_sg,
-        .sync_single_for_cpu    = dma32_sync_single_for_cpu,
-        .sync_single_for_device = dma32_sync_single_for_device,
-        .sync_sg_for_cpu        = dma32_sync_sg_for_cpu,
-        .sync_sg_for_device     = dma32_sync_sg_for_device,
-};
-const struct dma_ops *dma_ops = &dma32_dma_ops;
-EXPORT_SYMBOL(dma_ops);
diff --git a/arch/sparc/kernel/dma.h b/arch/sparc/kernel/dma.h
deleted file mode 100644
index f8d8951adb53..000000000000
--- a/arch/sparc/kernel/dma.h
+++ /dev/null
@@ -1,14 +0,0 @@
-void *sbus_alloc_consistent(struct device *dev, long len, u32 *dma_addrp);
-void sbus_free_consistent(struct device *dev, long n, void *p, u32 ba);
-dma_addr_t sbus_map_single(struct device *dev, void *va,
-                           size_t len, int direction);
-void sbus_unmap_single(struct device *dev, dma_addr_t ba,
-                       size_t n, int direction);
-int sbus_map_sg(struct device *dev, struct scatterlist *sg,
-                int n, int direction);
-void sbus_unmap_sg(struct device *dev, struct scatterlist *sg,
-                   int n, int direction);
-void sbus_dma_sync_single_for_cpu(struct device *dev, dma_addr_t ba,
-                                  size_t size, int direction);
-void sbus_dma_sync_single_for_device(struct device *dev, dma_addr_t ba,
-                                     size_t size, int direction);
diff --git a/arch/sparc/kernel/head_32.S b/arch/sparc/kernel/head_32.S
index 6b4d8acc4c83..439d82a95ac9 100644
--- a/arch/sparc/kernel/head_32.S
+++ b/arch/sparc/kernel/head_32.S
@@ -809,6 +809,11 @@ found_version:
                 nop
 got_prop:
+#ifdef CONFIG_SPARC_LEON
+                /* no cpu-type check is needed, it is a SPARC-LEON */
+                ba sun4c_continue_boot
+                 nop
+#endif
                set     cputypval, %o2
                ldub    [%o2 + 0x4], %l1
diff --git a/arch/sparc/kernel/idprom.c b/arch/sparc/kernel/idprom.c
index 57922f69c3f7..52a15fe2db19 100644
--- a/arch/sparc/kernel/idprom.c
+++ b/arch/sparc/kernel/idprom.c
@@ -31,6 +31,8 @@ static struct Sun_Machine_Models Sun_Machines[NUM_SUN_MACHINES] = {
 { .name = "Sun 4/200 Series",        .id_machtype = (SM_SUN4 | SM_4_260) },
 { .name = "Sun 4/300 Series",        .id_machtype = (SM_SUN4 | SM_4_330) },
 { .name = "Sun 4/400 Series",        .id_machtype = (SM_SUN4 | SM_4_470) },
+/* Now Leon */
+{ .name = "Leon3 System-on-a-Chip",  .id_machtype = (M_LEON | M_LEON3_SOC) },
 /* Now, Sun4c's */
 { .name = "Sun4c SparcStation 1",    .id_machtype = (SM_SUN4C | SM_4C_SS1) },
 { .name = "Sun4c SparcStation IPC",  .id_machtype = (SM_SUN4C | SM_4C_IPC) },
diff --git a/arch/sparc/kernel/iommu.c b/arch/sparc/kernel/iommu.c
index 0aeaefe696b9..7690cc219ecc 100644
--- a/arch/sparc/kernel/iommu.c
+++ b/arch/sparc/kernel/iommu.c
@@ -353,7 +353,8 @@ static void dma_4u_free_coherent(struct device *dev, size_t size,
 static dma_addr_t dma_4u_map_page(struct device *dev, struct page *page,
                                  unsigned long offset, size_t sz,
-                                  enum dma_data_direction direction)
+                                  enum dma_data_direction direction,
+                                  struct dma_attrs *attrs)
 {
        struct iommu *iommu;
        struct strbuf *strbuf;
@@ -474,7 +475,8 @@ do_flush_sync:
 }
 static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
-                              size_t sz, enum dma_data_direction direction)
+                              size_t sz, enum dma_data_direction direction,
+                              struct dma_attrs *attrs)
 {
        struct iommu *iommu;
        struct strbuf *strbuf;
@@ -520,7 +522,8 @@ static void dma_4u_unmap_page(struct device *dev, dma_addr_t bus_addr,
 }
 static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist,
-                         int nelems, enum dma_data_direction direction)
+                         int nelems, enum dma_data_direction direction,
+                         struct dma_attrs *attrs)
 {
        struct scatterlist *s, *outs, *segstart;
        unsigned long flags, handle, prot, ctx;
@@ -691,7 +694,8 @@ static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg)
 }
 static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist,
-                            int nelems, enum dma_data_direction direction)
+                            int nelems, enum dma_data_direction direction,
+                            struct dma_attrs *attrs)
 {
        unsigned long flags, ctx;
        struct scatterlist *sg;
@@ -822,7 +826,7 @@ static void dma_4u_sync_sg_for_cpu(struct device *dev,
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
-static const struct dma_ops sun4u_dma_ops = {
+static struct dma_map_ops sun4u_dma_ops = {
        .alloc_coherent         = dma_4u_alloc_coherent,
        .free_coherent          = dma_4u_free_coherent,
        .map_page               = dma_4u_map_page,
@@ -833,9 +837,11 @@ static const struct dma_ops sun4u_dma_ops = {
        .sync_sg_for_cpu        = dma_4u_sync_sg_for_cpu,
 };
-const struct dma_ops *dma_ops = &sun4u_dma_ops;
+struct dma_map_ops *dma_ops = &sun4u_dma_ops;
 EXPORT_SYMBOL(dma_ops);
+extern int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask);
 int dma_supported(struct device *dev, u64 device_mask)
 {
        struct iommu *iommu = dev->archdata.iommu;
@@ -849,7 +855,7 @@ int dma_supported(struct device *dev, u64 device_mask)
 #ifdef CONFIG_PCI
        if (dev->bus == &pci_bus_type)
-                return pci_dma_supported(to_pci_dev(dev), device_mask);
+                return pci64_dma_supported(to_pci_dev(dev), device_mask);
 #endif
        return 0;
diff --git a/arch/sparc/kernel/ioport.c b/arch/sparc/kernel/ioport.c
index 87ea0d03d975..9f61fd8cbb7b 100644
--- a/arch/sparc/kernel/ioport.c
+++ b/arch/sparc/kernel/ioport.c
@@ -35,6 +35,7 @@
 #include <linux/slab.h>
 #include <linux/pci.h>          /* struct pci_dev */
 #include <linux/proc_fs.h>
+#include <linux/seq_file.h>
 #include <linux/scatterlist.h>
 #include <linux/of_device.h>
@@ -48,8 +49,6 @@
 #include <asm/iommu.h>
 #include <asm/io-unit.h>
-#include "dma.h"
 #define mmu_inval_dma_area(p, l)        /* Anton pulled it out for 2.4.0-xx */
 static struct resource *_sparc_find_resource(struct resource *r,
@@ -246,7 +245,8 @@ EXPORT_SYMBOL(sbus_set_sbus64);
 * Typically devices use them for control blocks.
 * CPU may access them without any explicit flushing.
 */
-void *sbus_alloc_consistent(struct device *dev, long len, u32 *dma_addrp)
+static void *sbus_alloc_coherent(struct device *dev, size_t len,
+                                 dma_addr_t *dma_addrp, gfp_t gfp)
 {
        struct of_device *op = to_of_device(dev);
        unsigned long len_total = (len + PAGE_SIZE-1) & PAGE_MASK;
@@ -299,7 +299,8 @@ err_nopages:
        return NULL;
 }
-void sbus_free_consistent(struct device *dev, long n, void *p, u32 ba)
+static void sbus_free_coherent(struct device *dev, size_t n, void *p,
+                               dma_addr_t ba)
 {
        struct resource *res;
        struct page *pgv;
@@ -317,7 +318,7 @@ void sbus_free_consistent(struct device *dev, long n, void *p, u32 ba)
        n = (n + PAGE_SIZE-1) & PAGE_MASK;
        if ((res->end-res->start)+1 != n) {
-                printk("sbus_free_consistent: region 0x%lx asked 0x%lx\n",
+                printk("sbus_free_consistent: region 0x%lx asked 0x%zx\n",
                    (long)((res->end-res->start)+1), n);
                return;
        }
@@ -337,8 +338,13 @@ void sbus_free_consistent(struct device *dev, long n, void *p, u32 ba)
 * CPU view of this memory may be inconsistent with
 * a device view and explicit flushing is necessary.
 */
-dma_addr_t sbus_map_single(struct device *dev, void *va, size_t len, int direction)
+static dma_addr_t sbus_map_page(struct device *dev, struct page *page,
+                                unsigned long offset, size_t len,
+                                enum dma_data_direction dir,
+                                struct dma_attrs *attrs)
 {
+        void *va = page_address(page) + offset;
        /* XXX why are some lengths signed, others unsigned? */
        if (len <= 0) {
                return 0;
@@ -350,12 +356,14 @@ dma_addr_t sbus_map_single(struct device *dev, void *va, size_t len, int directi
        return mmu_get_scsi_one(dev, va, len);
 }
-void sbus_unmap_single(struct device *dev, dma_addr_t ba, size_t n, int direction)
+static void sbus_unmap_page(struct device *dev, dma_addr_t ba, size_t n,
+                            enum dma_data_direction dir, struct dma_attrs *attrs)
 {
        mmu_release_scsi_one(dev, ba, n);
 }
-int sbus_map_sg(struct device *dev, struct scatterlist *sg, int n, int direction)
+static int sbus_map_sg(struct device *dev, struct scatterlist *sg, int n,
+                       enum dma_data_direction dir, struct dma_attrs *attrs)
 {
        mmu_get_scsi_sgl(dev, sg, n);
@@ -366,19 +374,38 @@ int sbus_map_sg(struct device *dev, struct scatterlist *sg, int n, int direction
        return n;
 }
-void sbus_unmap_sg(struct device *dev, struct scatterlist *sg, int n, int direction)
+static void sbus_unmap_sg(struct device *dev, struct scatterlist *sg, int n,
+                          enum dma_data_direction dir, struct dma_attrs *attrs)
 {
        mmu_release_scsi_sgl(dev, sg, n);
 }
-void sbus_dma_sync_single_for_cpu(struct device *dev, dma_addr_t ba, size_t size, int direction)
+static void sbus_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
+                                 int n, enum dma_data_direction dir)
 {
+        BUG();
 }
-void sbus_dma_sync_single_for_device(struct device *dev, dma_addr_t ba, size_t size, int direction)
+static void sbus_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+                                    int n, enum dma_data_direction dir)
 {
+        BUG();
 }
+struct dma_map_ops sbus_dma_ops = {
+        .alloc_coherent         = sbus_alloc_coherent,
+        .free_coherent          = sbus_free_coherent,
+        .map_page               = sbus_map_page,
+        .unmap_page             = sbus_unmap_page,
+        .map_sg                 = sbus_map_sg,
+        .unmap_sg               = sbus_unmap_sg,
+        .sync_sg_for_cpu        = sbus_sync_sg_for_cpu,
+        .sync_sg_for_device     = sbus_sync_sg_for_device,
+};
+struct dma_map_ops *dma_ops = &sbus_dma_ops;
+EXPORT_SYMBOL(dma_ops);
 static int __init sparc_register_ioport(void)
 {
        register_proc_sparc_ioport();
@@ -395,7 +422,8 @@ arch_initcall(sparc_register_ioport);
 /* Allocate and map kernel buffer using consistent mode DMA for a device.
 * hwdev should be valid struct pci_dev pointer for PCI devices.
 */
-void *pci_alloc_consistent(struct pci_dev *pdev, size_t len, dma_addr_t *pba)
+static void *pci32_alloc_coherent(struct device *dev, size_t len,
+                                  dma_addr_t *pba, gfp_t gfp)
 {
        unsigned long len_total = (len + PAGE_SIZE-1) & PAGE_MASK;
        unsigned long va;
@@ -439,7 +467,6 @@ void *pci_alloc_consistent(struct pci_dev *pdev, size_t len, dma_addr_t *pba)
        *pba = virt_to_phys(va); /* equals virt_to_bus (R.I.P.) for us. */
        return (void *) res->start;
 }
-EXPORT_SYMBOL(pci_alloc_consistent);
 /* Free and unmap a consistent DMA buffer.
 * cpu_addr is what was returned from pci_alloc_consistent,
@@ -449,7 +476,8 @@ EXPORT_SYMBOL(pci_alloc_consistent);
 * References to the memory and mappings associated with cpu_addr/dma_addr
 * past this call are illegal.
 */
-void pci_free_consistent(struct pci_dev *pdev, size_t n, void *p, dma_addr_t ba)
+static void pci32_free_coherent(struct device *dev, size_t n, void *p,
+                                dma_addr_t ba)
 {
        struct resource *res;
        unsigned long pgp;
@@ -481,60 +509,18 @@ void pci_free_consistent(struct pci_dev *pdev, size_t n, void *p, dma_addr_t ba)
        free_pages(pgp, get_order(n));
 }
-EXPORT_SYMBOL(pci_free_consistent);
-/* Map a single buffer of the indicated size for DMA in streaming mode.
- * The 32-bit bus address to use is returned.
- *
- * Once the device is given the dma address, the device owns this memory
- * until either pci_unmap_single or pci_dma_sync_single_* is performed.
- */
-dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr, size_t size,
-    int direction)
-{
-        BUG_ON(direction == PCI_DMA_NONE);
-        /* IIep is write-through, not flushing. */
-        return virt_to_phys(ptr);
-}
-EXPORT_SYMBOL(pci_map_single);
-/* Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guaranteed to see
- * whatever the device wrote there.
- */
-void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t ba, size_t size,
-    int direction)
-{
-        BUG_ON(direction == PCI_DMA_NONE);
-        if (direction != PCI_DMA_TODEVICE) {
-                mmu_inval_dma_area((unsigned long)phys_to_virt(ba),
-                    (size + PAGE_SIZE-1) & PAGE_MASK);
-        }
-}
-EXPORT_SYMBOL(pci_unmap_single);
 /*
 * Same as pci_map_single, but with pages.
 */
-dma_addr_t pci_map_page(struct pci_dev *hwdev, struct page *page,
+static dma_addr_t pci32_map_page(struct device *dev, struct page *page,
-                        unsigned long offset, size_t size, int direction)
+                                 unsigned long offset, size_t size,
+                                 enum dma_data_direction dir,
+                                 struct dma_attrs *attrs)
 {
-        BUG_ON(direction == PCI_DMA_NONE);
        /* IIep is write-through, not flushing. */
        return page_to_phys(page) + offset;
 }
-EXPORT_SYMBOL(pci_map_page);
-void pci_unmap_page(struct pci_dev *hwdev,
-                        dma_addr_t dma_address, size_t size, int direction)
-{
-        BUG_ON(direction == PCI_DMA_NONE);
-        /* mmu_inval_dma_area XXX */
-}
-EXPORT_SYMBOL(pci_unmap_page);
 /* Map a set of buffers described by scatterlist in streaming
 * mode for DMA.  This is the scather-gather version of the
@@ -551,13 +537,13 @@ EXPORT_SYMBOL(pci_unmap_page);
 * Device ownership issues as mentioned above for pci_map_single are
 * the same here.
 */
-int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents,
+static int pci32_map_sg(struct device *device, struct scatterlist *sgl,
-    int direction)
+                        int nents, enum dma_data_direction dir,
+                        struct dma_attrs *attrs)
 {
        struct scatterlist *sg;
        int n;
-        BUG_ON(direction == PCI_DMA_NONE);
        /* IIep is write-through, not flushing. */
        for_each_sg(sgl, sg, nents, n) {
                BUG_ON(page_address(sg_page(sg)) == NULL);
@@ -566,20 +552,19 @@ int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents,
        }
        return nents;
 }
-EXPORT_SYMBOL(pci_map_sg);
 /* Unmap a set of streaming mode DMA translations.
 * Again, cpu read rules concerning calls here are the same as for
 * pci_unmap_single() above.
 */
-void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents,
+static void pci32_unmap_sg(struct device *dev, struct scatterlist *sgl,
-    int direction)
+                           int nents, enum dma_data_direction dir,
+                           struct dma_attrs *attrs)
 {
        struct scatterlist *sg;
        int n;
-        BUG_ON(direction == PCI_DMA_NONE);
+        if (dir != PCI_DMA_TODEVICE) {
-        if (direction != PCI_DMA_TODEVICE) {
                for_each_sg(sgl, sg, nents, n) {
                        BUG_ON(page_address(sg_page(sg)) == NULL);
                        mmu_inval_dma_area(
@@ -588,7 +573,6 @@ void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sgl, int nents,
                }
        }
 }
-EXPORT_SYMBOL(pci_unmap_sg);
 /* Make physical memory consistent for a single
 * streaming mode DMA translation before or after a transfer.
@@ -600,25 +584,23 @@ EXPORT_SYMBOL(pci_unmap_sg);
 * must first perform a pci_dma_sync_for_device, and then the
 * device again owns the buffer.
 */
-void pci_dma_sync_single_for_cpu(struct pci_dev *hwdev, dma_addr_t ba, size_t size, int direction)
+static void pci32_sync_single_for_cpu(struct device *dev, dma_addr_t ba,
+                                      size_t size, enum dma_data_direction dir)
 {
-        BUG_ON(direction == PCI_DMA_NONE);
+        if (dir != PCI_DMA_TODEVICE) {
-        if (direction != PCI_DMA_TODEVICE) {
                mmu_inval_dma_area((unsigned long)phys_to_virt(ba),
                    (size + PAGE_SIZE-1) & PAGE_MASK);
        }
 }
-EXPORT_SYMBOL(pci_dma_sync_single_for_cpu);
-void pci_dma_sync_single_for_device(struct pci_dev *hwdev, dma_addr_t ba, size_t size, int direction)
+static void pci32_sync_single_for_device(struct device *dev, dma_addr_t ba,
+                                         size_t size, enum dma_data_direction dir)
 {
-        BUG_ON(direction == PCI_DMA_NONE);
+        if (dir != PCI_DMA_TODEVICE) {
-        if (direction != PCI_DMA_TODEVICE) {
                mmu_inval_dma_area((unsigned long)phys_to_virt(ba),
                    (size + PAGE_SIZE-1) & PAGE_MASK);
        }
 }
-EXPORT_SYMBOL(pci_dma_sync_single_for_device);
 /* Make physical memory consistent for a set of streaming
 * mode DMA translations after a transfer.
@@ -626,13 +608,13 @@ EXPORT_SYMBOL(pci_dma_sync_single_for_device);
 * The same as pci_dma_sync_single_* but for a scatter-gather list,
 * same rules and usage.
 */
-void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, int direction)
+static void pci32_sync_sg_for_cpu(struct device *dev, struct scatterlist *sgl,
+                                  int nents, enum dma_data_direction dir)
 {
        struct scatterlist *sg;
        int n;
-        BUG_ON(direction == PCI_DMA_NONE);
+        if (dir != PCI_DMA_TODEVICE) {
-        if (direction != PCI_DMA_TODEVICE) {
                for_each_sg(sgl, sg, nents, n) {
                        BUG_ON(page_address(sg_page(sg)) == NULL);
                        mmu_inval_dma_area(
@@ -641,15 +623,14 @@ void pci_dma_sync_sg_for_cpu(struct pci_dev *hwdev, struct scatterlist *sgl, int
                }
        }
 }
-EXPORT_SYMBOL(pci_dma_sync_sg_for_cpu);
-void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl, int nents, int direction)
+static void pci32_sync_sg_for_device(struct device *device, struct scatterlist *sgl,
+                                     int nents, enum dma_data_direction dir)
 {
        struct scatterlist *sg;
        int n;
-        BUG_ON(direction == PCI_DMA_NONE);
+        if (dir != PCI_DMA_TODEVICE) {
-        if (direction != PCI_DMA_TODEVICE) {
                for_each_sg(sgl, sg, nents, n) {
                        BUG_ON(page_address(sg_page(sg)) == NULL);
                        mmu_inval_dma_area(
@@ -658,31 +639,78 @@ void pci_dma_sync_sg_for_device(struct pci_dev *hwdev, struct scatterlist *sgl,
                }
        }
 }
-EXPORT_SYMBOL(pci_dma_sync_sg_for_device);
+struct dma_map_ops pci32_dma_ops = {
+        .alloc_coherent         = pci32_alloc_coherent,
+        .free_coherent          = pci32_free_coherent,
+        .map_page               = pci32_map_page,
+        .map_sg                 = pci32_map_sg,
+        .unmap_sg               = pci32_unmap_sg,
+        .sync_single_for_cpu    = pci32_sync_single_for_cpu,
+        .sync_single_for_device = pci32_sync_single_for_device,
+        .sync_sg_for_cpu        = pci32_sync_sg_for_cpu,
+        .sync_sg_for_device     = pci32_sync_sg_for_device,
+};
+EXPORT_SYMBOL(pci32_dma_ops);
 #endif /* CONFIG_PCI */
+/*
+ * Return whether the given PCI device DMA address mask can be
+ * supported properly.  For example, if your device can only drive the
+ * low 24-bits during PCI bus mastering, then you would pass
+ * 0x00ffffff as the mask to this function.
+ */
+int dma_supported(struct device *dev, u64 mask)
+{
+#ifdef CONFIG_PCI
+        if (dev->bus == &pci_bus_type)
+                return 1;
+#endif
+        return 0;
+}
+EXPORT_SYMBOL(dma_supported);
+int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+#ifdef CONFIG_PCI
+        if (dev->bus == &pci_bus_type)
+                return pci_set_dma_mask(to_pci_dev(dev), dma_mask);
+#endif
+        return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(dma_set_mask);
 #ifdef CONFIG_PROC_FS
-static int
+static int sparc_io_proc_show(struct seq_file *m, void *v)
-_sparc_io_get_info(char *buf, char **start, off_t fpos, int length, int *eof,
-    void *data)
 {
-        char *p = buf, *e = buf + length;
+        struct resource *root = m->private, *r;
-        struct resource *r;
        const char *nm;
-        for (r = ((struct resource *)data)->child; r != NULL; r = r->sibling) {
+        for (r = root->child; r != NULL; r = r->sibling) {
-                if (p + 32 >= e)        /* Better than nothing */
-                        break;
                if ((nm = r->name) == 0) nm = "???";
-                p += sprintf(p, "%016llx-%016llx: %s\n",
+                seq_printf(m, "%016llx-%016llx: %s\n",
                                (unsigned long long)r->start,
                                (unsigned long long)r->end, nm);
        }
-        return p-buf;
+        return 0;
 }
+static int sparc_io_proc_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, sparc_io_proc_show, PDE(inode)->data);
+}
+static const struct file_operations sparc_io_proc_fops = {
+        .owner          = THIS_MODULE,
+        .open           = sparc_io_proc_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
 #endif /* CONFIG_PROC_FS */
 /*
@@ -707,7 +735,7 @@ static struct resource *_sparc_find_resource(struct resource *root,
 static void register_proc_sparc_ioport(void)
 {
 #ifdef CONFIG_PROC_FS
-        create_proc_read_entry("io_map",0,NULL,_sparc_io_get_info,&sparc_iomap);
+        proc_create_data("io_map", 0, NULL, &sparc_io_proc_fops, &sparc_iomap);
-        create_proc_read_entry("dvma_map",0,NULL,_sparc_io_get_info,&_sparc_dvma);
+        proc_create_data("dvma_map", 0, NULL, &sparc_io_proc_fops, &_sparc_dvma);
 #endif
 }
diff --git a/arch/sparc/kernel/irq_32.c b/arch/sparc/kernel/irq_32.c
index ad800b80c718..e1af43728329 100644
--- a/arch/sparc/kernel/irq_32.c
+++ b/arch/sparc/kernel/irq_32.c
@@ -45,6 +45,7 @@
 #include <asm/pcic.h>
 #include <asm/cacheflush.h>
 #include <asm/irq_regs.h>
+#include <asm/leon.h>
 #include "kernel.h"
 #include "irq.h"
@@ -661,6 +662,10 @@ void __init init_IRQ(void)
                sun4d_init_IRQ();
                break;
+        case sparc_leon:
+                leon_init_IRQ();
+                break;
        default:
                prom_printf("Cannot initialize IRQs on this Sun machine...");
                break;
diff --git a/arch/sparc/kernel/leon_kernel.c b/arch/sparc/kernel/leon_kernel.c
new file mode 100644
index 000000000000..54d8a5bd4824
--- /dev/null
+++ b/arch/sparc/kernel/leon_kernel.c
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB
+ * Copyright (C) 2009 Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/errno.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/interrupt.h>
+#include <linux/of_device.h>
+#include <asm/oplib.h>
+#include <asm/timer.h>
+#include <asm/prom.h>
+#include <asm/leon.h>
+#include <asm/leon_amba.h>
+#include "prom.h"
+#include "irq.h"
+struct leon3_irqctrl_regs_map *leon3_irqctrl_regs; /* interrupt controller base address, initialized by amba_init() */
+struct leon3_gptimer_regs_map *leon3_gptimer_regs; /* timer controller base address, initialized by amba_init() */
+struct amba_apb_device leon_percpu_timer_dev[16];
+int leondebug_irq_disable;
+int leon_debug_irqout;
+static int dummy_master_l10_counter;
+unsigned long leon3_gptimer_irq; /* interrupt controller irq number, initialized by amba_init() */
+unsigned int sparc_leon_eirq;
+#define LEON_IMASK ((&leon3_irqctrl_regs->mask[0]))
+/* Return the IRQ of the pending IRQ on the extended IRQ controller */
+int sparc_leon_eirq_get(int eirq, int cpu)
+{
+        return LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->intid[cpu]) & 0x1f;
+}
+irqreturn_t sparc_leon_eirq_isr(int dummy, void *dev_id)
+{
+        printk(KERN_ERR "sparc_leon_eirq_isr: ERROR EXTENDED IRQ\n");
+        return IRQ_HANDLED;
+}
+/* The extended IRQ controller has been found, this function registers it */
+void sparc_leon_eirq_register(int eirq)
+{
+        int irq;
+        /* Register a "BAD" handler for this interrupt, it should never happen */
+        irq = request_irq(eirq, sparc_leon_eirq_isr,
+                          (IRQF_DISABLED | SA_STATIC_ALLOC), "extirq", NULL);
+        if (irq) {
+                printk(KERN_ERR
+                       "sparc_leon_eirq_register: unable to attach IRQ%d\n",
+                       eirq);
+        } else {
+                sparc_leon_eirq = eirq;
+        }
+}
+static inline unsigned long get_irqmask(unsigned int irq)
+{
+        unsigned long mask;
+        if (!irq || ((irq > 0xf) && !sparc_leon_eirq)
+            || ((irq > 0x1f) && sparc_leon_eirq)) {
+                printk(KERN_ERR
+                       "leon_get_irqmask: false irq number: %d\n", irq);
+                mask = 0;
+        } else {
+                mask = LEON_HARD_INT(irq);
+        }
+        return mask;
+}
+static void leon_enable_irq(unsigned int irq_nr)
+{
+        unsigned long mask, flags;
+        mask = get_irqmask(irq_nr);
+        local_irq_save(flags);
+        LEON3_BYPASS_STORE_PA(LEON_IMASK,
+                              (LEON3_BYPASS_LOAD_PA(LEON_IMASK) | (mask)));
+        local_irq_restore(flags);
+}
+static void leon_disable_irq(unsigned int irq_nr)
+{
+        unsigned long mask, flags;
+        mask = get_irqmask(irq_nr);
+        local_irq_save(flags);
+        LEON3_BYPASS_STORE_PA(LEON_IMASK,
+                              (LEON3_BYPASS_LOAD_PA(LEON_IMASK) & ~(mask)));
+        local_irq_restore(flags);
+}
+void __init leon_init_timers(irq_handler_t counter_fn)
+{
+        int irq;
+        leondebug_irq_disable = 0;
+        leon_debug_irqout = 0;
+        master_l10_counter = (unsigned int *)&dummy_master_l10_counter;
+        dummy_master_l10_counter = 0;
+        if (leon3_gptimer_regs && leon3_irqctrl_regs) {
+                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].val, 0);
+                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].rld,
+                                      (((1000000 / 100) - 1)));
+                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].ctrl, 0);
+        } else {
+                printk(KERN_ERR "No Timer/irqctrl found\n");
+                BUG();
+        }
+        irq = request_irq(leon3_gptimer_irq,
+                          counter_fn,
+                          (IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
+        if (irq) {
+                printk(KERN_ERR "leon_time_init: unable to attach IRQ%d\n",
+                       LEON_INTERRUPT_TIMER1);
+                prom_halt();
+        }
+        if (leon3_gptimer_regs) {
+                LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[0].ctrl,
+                                      LEON3_GPTIMER_EN |
+                                      LEON3_GPTIMER_RL |
+                                      LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
+        }
+}
+void leon_clear_clock_irq(void)
+{
+}
+void leon_load_profile_irq(int cpu, unsigned int limit)
+{
+        BUG();
+}
+void __init leon_trans_init(struct device_node *dp)
+{
+        if (strcmp(dp->type, "cpu") == 0 && strcmp(dp->name, "<NULL>") == 0) {
+                struct property *p;
+                p = of_find_property(dp, "mid", (void *)0);
+                if (p) {
+                        int mid;
+                        dp->name = prom_early_alloc(5 + 1);
+                        memcpy(&mid, p->value, p->length);
+                        sprintf((char *)dp->name, "cpu%.2d", mid);
+                }
+        }
+}
+void __initdata (*prom_amba_init)(struct device_node *dp, struct device_node ***nextp) = 0;
+void __init leon_node_init(struct device_node *dp, struct device_node ***nextp)
+{
+        if (prom_amba_init &&
+            strcmp(dp->type, "ambapp") == 0 &&
+            strcmp(dp->name, "ambapp0") == 0) {
+                prom_amba_init(dp, nextp);
+        }
+}
+void __init leon_init_IRQ(void)
+{
+        sparc_init_timers = leon_init_timers;
+        BTFIXUPSET_CALL(enable_irq, leon_enable_irq, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(disable_irq, leon_disable_irq, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(enable_pil_irq, leon_enable_irq, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(disable_pil_irq, leon_disable_irq, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(clear_clock_irq, leon_clear_clock_irq,
+                        BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(load_profile_irq, leon_load_profile_irq,
+                        BTFIXUPCALL_NOP);
+#ifdef CONFIG_SMP
+        BTFIXUPSET_CALL(set_cpu_int, leon_set_cpu_int, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(clear_cpu_int, leon_clear_ipi, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(set_irq_udt, leon_set_udt, BTFIXUPCALL_NORM);
+#endif
+}
+void __init leon_init(void)
+{
+        prom_build_more = &leon_node_init;
+}
diff --git a/arch/sparc/kernel/nmi.c b/arch/sparc/kernel/nmi.c
index b75bf502cd42..378eb53e0776 100644
--- a/arch/sparc/kernel/nmi.c
+++ b/arch/sparc/kernel/nmi.c
@@ -19,6 +19,7 @@
 #include <linux/delay.h>
 #include <linux/smp.h>
+#include <asm/perf_counter.h>
 #include <asm/ptrace.h>
 #include <asm/local.h>
 #include <asm/pcr.h>
@@ -31,13 +32,19 @@
 * level 14 as our IRQ off level.
 */
-static int nmi_watchdog_active;
 static int panic_on_timeout;
-int nmi_usable;
+/* nmi_active:
-EXPORT_SYMBOL_GPL(nmi_usable);
+ * >0: the NMI watchdog is active, but can be disabled
+ * <0: the NMI watchdog has not been set up, and cannot be enabled
+ *  0: the NMI watchdog is disabled, but can be enabled
+ */
+atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
+EXPORT_SYMBOL(nmi_active);
 static unsigned int nmi_hz = HZ;
+static DEFINE_PER_CPU(short, wd_enabled);
+static int endflag __initdata;
 static DEFINE_PER_CPU(unsigned int, last_irq_sum);
 static DEFINE_PER_CPU(local_t, alert_counter);
@@ -45,7 +52,7 @@ static DEFINE_PER_CPU(int, nmi_touch);
 void touch_nmi_watchdog(void)
 {
-        if (nmi_watchdog_active) {
+        if (atomic_read(&nmi_active)) {
                int cpu;
                for_each_present_cpu(cpu) {
@@ -78,6 +85,7 @@ static void die_nmi(const char *str, struct pt_regs *regs, int do_panic)
        if (do_panic || panic_on_oops)
                panic("Non maskable interrupt");
+        nmi_exit();
        local_irq_enable();
        do_exit(SIGBUS);
 }
@@ -92,6 +100,8 @@ notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs)
        local_cpu_data().__nmi_count++;
+        nmi_enter();
        if (notify_die(DIE_NMI, "nmi", regs, 0,
                       pt_regs_trap_type(regs), SIGINT) == NOTIFY_STOP)
                touched = 1;
@@ -110,10 +120,12 @@ notrace __kprobes void perfctr_irq(int irq, struct pt_regs *regs)
                __get_cpu_var(last_irq_sum) = sum;
                local_set(&__get_cpu_var(alert_counter), 0);
        }
-        if (nmi_usable) {
+        if (__get_cpu_var(wd_enabled)) {
                write_pic(picl_value(nmi_hz));
                pcr_ops->write(pcr_enable);
        }
+        nmi_exit();
 }
 static inline unsigned int get_nmi_count(int cpu)
@@ -121,8 +133,6 @@ static inline unsigned int get_nmi_count(int cpu)
        return cpu_data(cpu).__nmi_count;
 }
-static int endflag __initdata;
 static __init void nmi_cpu_busy(void *data)
 {
        local_irq_enable_in_hardirq();
@@ -143,12 +153,15 @@ static void report_broken_nmi(int cpu, int *prev_nmi_count)
        printk(KERN_WARNING
                "and attach the output of the 'dmesg' command.\n");
-        nmi_usable = 0;
+        per_cpu(wd_enabled, cpu) = 0;
+        atomic_dec(&nmi_active);
 }
-static void stop_watchdog(void *unused)
+void stop_nmi_watchdog(void *unused)
 {
        pcr_ops->write(PCR_PIC_PRIV);
+        __get_cpu_var(wd_enabled) = 0;
+        atomic_dec(&nmi_active);
 }
 static int __init check_nmi_watchdog(void)
@@ -156,6 +169,9 @@ static int __init check_nmi_watchdog(void)
        unsigned int *prev_nmi_count;
        int cpu, err;
+        if (!atomic_read(&nmi_active))
+                return 0;
        prev_nmi_count = kmalloc(nr_cpu_ids * sizeof(unsigned int), GFP_KERNEL);
        if (!prev_nmi_count) {
                err = -ENOMEM;
@@ -172,12 +188,15 @@ static int __init check_nmi_watchdog(void)
        mdelay((20 * 1000) / nmi_hz); /* wait 20 ticks */
        for_each_online_cpu(cpu) {
+                if (!per_cpu(wd_enabled, cpu))
+                        continue;
                if (get_nmi_count(cpu) - prev_nmi_count[cpu] <= 5)
                        report_broken_nmi(cpu, prev_nmi_count);
        }
        endflag = 1;
-        if (!nmi_usable) {
+        if (!atomic_read(&nmi_active)) {
                kfree(prev_nmi_count);
+                atomic_set(&nmi_active, -1);
                err = -ENODEV;
                goto error;
        }
@@ -188,12 +207,26 @@ static int __init check_nmi_watchdog(void)
        kfree(prev_nmi_count);
        return 0;
 error:
-        on_each_cpu(stop_watchdog, NULL, 1);
+        on_each_cpu(stop_nmi_watchdog, NULL, 1);
        return err;
 }
-static void start_watchdog(void *unused)
+void start_nmi_watchdog(void *unused)
 {
+        __get_cpu_var(wd_enabled) = 1;
+        atomic_inc(&nmi_active);
+        pcr_ops->write(PCR_PIC_PRIV);
+        write_pic(picl_value(nmi_hz));
+        pcr_ops->write(pcr_enable);
+}
+static void nmi_adjust_hz_one(void *unused)
+{
+        if (!__get_cpu_var(wd_enabled))
+                return;
        pcr_ops->write(PCR_PIC_PRIV);
        write_pic(picl_value(nmi_hz));
@@ -203,13 +236,13 @@ static void start_watchdog(void *unused)
 void nmi_adjust_hz(unsigned int new_hz)
 {
        nmi_hz = new_hz;
-        on_each_cpu(start_watchdog, NULL, 1);
+        on_each_cpu(nmi_adjust_hz_one, NULL, 1);
 }
 EXPORT_SYMBOL_GPL(nmi_adjust_hz);
 static int nmi_shutdown(struct notifier_block *nb, unsigned long cmd, void *p)
 {
-        on_each_cpu(stop_watchdog, NULL, 1);
+        on_each_cpu(stop_nmi_watchdog, NULL, 1);
        return 0;
 }
@@ -221,18 +254,19 @@ int __init nmi_init(void)
 {
        int err;
-        nmi_usable = 1;
+        on_each_cpu(start_nmi_watchdog, NULL, 1);
-        on_each_cpu(start_watchdog, NULL, 1);
        err = check_nmi_watchdog();
        if (!err) {
                err = register_reboot_notifier(&nmi_reboot_notifier);
                if (err) {
-                        nmi_usable = 0;
+                        on_each_cpu(stop_nmi_watchdog, NULL, 1);
-                        on_each_cpu(stop_watchdog, NULL, 1);
+                        atomic_set(&nmi_active, -1);
                }
        }
+        if (!err)
+                init_hw_perf_counters();
        return err;
 }
diff --git a/arch/sparc/kernel/of_device_32.c b/arch/sparc/kernel/of_device_32.c
index 90396702ea2c..4c26eb59e742 100644
--- a/arch/sparc/kernel/of_device_32.c
+++ b/arch/sparc/kernel/of_device_32.c
@@ -9,6 +9,8 @@
 #include <linux/irq.h>
 #include <linux/of_device.h>
 #include <linux/of_platform.h>
+#include <asm/leon.h>
+#include <asm/leon_amba.h>
 #include "of_device_common.h"
@@ -97,6 +99,35 @@ static unsigned long of_bus_sbus_get_flags(const u32 *addr, unsigned long flags)
        return IORESOURCE_MEM;
 }
+ /*
+ * AMBAPP bus specific translator
+ */
+static int of_bus_ambapp_match(struct device_node *np)
+{
+        return !strcmp(np->name, "ambapp");
+}
+static void of_bus_ambapp_count_cells(struct device_node *child,
+                                      int *addrc, int *sizec)
+{
+        if (addrc)
+                *addrc = 1;
+        if (sizec)
+                *sizec = 1;
+}
+static int of_bus_ambapp_map(u32 *addr, const u32 *range,
+                             int na, int ns, int pna)
+{
+        return of_bus_default_map(addr, range, na, ns, pna);
+}
+static unsigned long of_bus_ambapp_get_flags(const u32 *addr,
+                                             unsigned long flags)
+{
+        return IORESOURCE_MEM;
+}
 /*
 * Array of bus specific translators
@@ -121,6 +152,15 @@ static struct of_bus of_busses[] = {
                .map = of_bus_default_map,
                .get_flags = of_bus_sbus_get_flags,
        },
+        /* AMBA */
+        {
+                .name = "ambapp",
+                .addr_prop_name = "reg",
+                .match = of_bus_ambapp_match,
+                .count_cells = of_bus_ambapp_count_cells,
+                .map = of_bus_ambapp_map,
+                .get_flags = of_bus_ambapp_get_flags,
+        },
        /* Default */
        {
                .name = "default",
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 57859ad23547..c68648662802 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -1039,7 +1039,7 @@ static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
        pci_dev_put(ali_isa_bridge);
 }
-int pci_dma_supported(struct pci_dev *pdev, u64 device_mask)
+int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
 {
        u64 dma_addr_mask;
diff --git a/arch/sparc/kernel/pci_sun4v.c b/arch/sparc/kernel/pci_sun4v.c
index 2485eaa23101..23c33ff9c31e 100644
--- a/arch/sparc/kernel/pci_sun4v.c
+++ b/arch/sparc/kernel/pci_sun4v.c
@@ -232,7 +232,8 @@ static void dma_4v_free_coherent(struct device *dev, size_t size, void *cpu,
 static dma_addr_t dma_4v_map_page(struct device *dev, struct page *page,
                                  unsigned long offset, size_t sz,
-                                  enum dma_data_direction direction)
+                                  enum dma_data_direction direction,
+                                  struct dma_attrs *attrs)
 {
        struct iommu *iommu;
        unsigned long flags, npages, oaddr;
@@ -296,7 +297,8 @@ iommu_map_fail:
 }
 static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
-                              size_t sz, enum dma_data_direction direction)
+                              size_t sz, enum dma_data_direction direction,
+                              struct dma_attrs *attrs)
 {
        struct pci_pbm_info *pbm;
        struct iommu *iommu;
@@ -336,7 +338,8 @@ static void dma_4v_unmap_page(struct device *dev, dma_addr_t bus_addr,
 }
 static int dma_4v_map_sg(struct device *dev, struct scatterlist *sglist,
-                         int nelems, enum dma_data_direction direction)
+                         int nelems, enum dma_data_direction direction,
+                         struct dma_attrs *attrs)
 {
        struct scatterlist *s, *outs, *segstart;
        unsigned long flags, handle, prot;
@@ -478,7 +481,8 @@ iommu_map_failed:
 }
 static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
-                            int nelems, enum dma_data_direction direction)
+                            int nelems, enum dma_data_direction direction,
+                            struct dma_attrs *attrs)
 {
        struct pci_pbm_info *pbm;
        struct scatterlist *sg;
@@ -521,29 +525,13 @@ static void dma_4v_unmap_sg(struct device *dev, struct scatterlist *sglist,
        spin_unlock_irqrestore(&iommu->lock, flags);
 }
-static void dma_4v_sync_single_for_cpu(struct device *dev,
+static struct dma_map_ops sun4v_dma_ops = {
-                                       dma_addr_t bus_addr, size_t sz,
-                                       enum dma_data_direction direction)
-{
-        /* Nothing to do... */
-}
-static void dma_4v_sync_sg_for_cpu(struct device *dev,
-                                   struct scatterlist *sglist, int nelems,
-                                   enum dma_data_direction direction)
-{
-        /* Nothing to do... */
-}
-static const struct dma_ops sun4v_dma_ops = {
        .alloc_coherent                 = dma_4v_alloc_coherent,
        .free_coherent                  = dma_4v_free_coherent,
        .map_page                       = dma_4v_map_page,
        .unmap_page                     = dma_4v_unmap_page,
        .map_sg                         = dma_4v_map_sg,
        .unmap_sg                       = dma_4v_unmap_sg,
-        .sync_single_for_cpu            = dma_4v_sync_single_for_cpu,
-        .sync_sg_for_cpu                = dma_4v_sync_sg_for_cpu,
 };
 static void __devinit pci_sun4v_scan_bus(struct pci_pbm_info *pbm,
diff --git a/arch/sparc/kernel/pcr.c b/arch/sparc/kernel/pcr.c
index 1ae8cdd7e703..68ff00107073 100644
--- a/arch/sparc/kernel/pcr.c
+++ b/arch/sparc/kernel/pcr.c
@@ -7,6 +7,8 @@
 #include <linux/init.h>
 #include <linux/irq.h>
+#include <linux/perf_counter.h>
 #include <asm/pil.h>
 #include <asm/pcr.h>
 #include <asm/nmi.h>
@@ -34,10 +36,20 @@ unsigned int picl_shift;
 */
 void deferred_pcr_work_irq(int irq, struct pt_regs *regs)
 {
+        struct pt_regs *old_regs;
        clear_softint(1 << PIL_DEFERRED_PCR_WORK);
+        old_regs = set_irq_regs(regs);
+        irq_enter();
+#ifdef CONFIG_PERF_COUNTERS
+        perf_counter_do_pending();
+#endif
+        irq_exit();
+        set_irq_regs(old_regs);
 }
-void schedule_deferred_pcr_work(void)
+void set_perf_counter_pending(void)
 {
        set_softint(1 << PIL_DEFERRED_PCR_WORK);
 }
diff --git a/arch/sparc/kernel/perf_counter.c b/arch/sparc/kernel/perf_counter.c
new file mode 100644
index 000000000000..09de4035eaa9
--- /dev/null
+++ b/arch/sparc/kernel/perf_counter.c
@@ -0,0 +1,557 @@
+/* Performance counter support for sparc64.
+ *
+ * Copyright (C) 2009 David S. Miller <davem@davemloft.net>
+ *
+ * This code is based almost entirely upon the x86 perf counter
+ * code, which is:
+ *
+ *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
+ *  Copyright (C) 2009 Jaswinder Singh Rajput
+ *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
+ *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ */
+#include <linux/perf_counter.h>
+#include <linux/kprobes.h>
+#include <linux/kernel.h>
+#include <linux/kdebug.h>
+#include <linux/mutex.h>
+#include <asm/cpudata.h>
+#include <asm/atomic.h>
+#include <asm/nmi.h>
+#include <asm/pcr.h>
+/* Sparc64 chips have two performance counters, 32-bits each, with
+ * overflow interrupts generated on transition from 0xffffffff to 0.
+ * The counters are accessed in one go using a 64-bit register.
+ *
+ * Both counters are controlled using a single control register.  The
+ * only way to stop all sampling is to clear all of the context (user,
+ * supervisor, hypervisor) sampling enable bits.  But these bits apply
+ * to both counters, thus the two counters can't be enabled/disabled
+ * individually.
+ *
+ * The control register has two event fields, one for each of the two
+ * counters.  It's thus nearly impossible to have one counter going
+ * while keeping the other one stopped.  Therefore it is possible to
+ * get overflow interrupts for counters not currently "in use" and
+ * that condition must be checked in the overflow interrupt handler.
+ *
+ * So we use a hack, in that we program inactive counters with the
+ * "sw_count0" and "sw_count1" events.  These count how many times
+ * the instruction "sethi %hi(0xfc000), %g0" is executed.  It's an
+ * unusual way to encode a NOP and therefore will not trigger in
+ * normal code.
+ */
+#define MAX_HWCOUNTERS                  2
+#define MAX_PERIOD                      ((1UL << 32) - 1)
+#define PIC_UPPER_INDEX                 0
+#define PIC_LOWER_INDEX                 1
+struct cpu_hw_counters {
+        struct perf_counter     *counters[MAX_HWCOUNTERS];
+        unsigned long           used_mask[BITS_TO_LONGS(MAX_HWCOUNTERS)];
+        unsigned long           active_mask[BITS_TO_LONGS(MAX_HWCOUNTERS)];
+        int enabled;
+};
+DEFINE_PER_CPU(struct cpu_hw_counters, cpu_hw_counters) = { .enabled = 1, };
+struct perf_event_map {
+        u16     encoding;
+        u8      pic_mask;
+#define PIC_NONE        0x00
+#define PIC_UPPER       0x01
+#define PIC_LOWER       0x02
+};
+struct sparc_pmu {
+        const struct perf_event_map     *(*event_map)(int);
+        int                             max_events;
+        int                             upper_shift;
+        int                             lower_shift;
+        int                             event_mask;
+        int                             hv_bit;
+        int                             irq_bit;
+        int                             upper_nop;
+        int                             lower_nop;
+};
+static const struct perf_event_map ultra3i_perfmon_event_map[] = {
+        [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
+        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
+        [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
+        [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
+};
+static const struct perf_event_map *ultra3i_event_map(int event)
+{
+        return &ultra3i_perfmon_event_map[event];
+}
+static const struct sparc_pmu ultra3i_pmu = {
+        .event_map      = ultra3i_event_map,
+        .max_events     = ARRAY_SIZE(ultra3i_perfmon_event_map),
+        .upper_shift    = 11,
+        .lower_shift    = 4,
+        .event_mask     = 0x3f,
+        .upper_nop      = 0x1c,
+        .lower_nop      = 0x14,
+};
+static const struct perf_event_map niagara2_perfmon_event_map[] = {
+        [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
+        [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
+        [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
+        [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
+        [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
+        [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
+};
+static const struct perf_event_map *niagara2_event_map(int event)
+{
+        return &niagara2_perfmon_event_map[event];
+}
+static const struct sparc_pmu niagara2_pmu = {
+        .event_map      = niagara2_event_map,
+        .max_events     = ARRAY_SIZE(niagara2_perfmon_event_map),
+        .upper_shift    = 19,
+        .lower_shift    = 6,
+        .event_mask     = 0xfff,
+        .hv_bit         = 0x8,
+        .irq_bit        = 0x03,
+        .upper_nop      = 0x220,
+        .lower_nop      = 0x220,
+};
+static const struct sparc_pmu *sparc_pmu __read_mostly;
+static u64 event_encoding(u64 event, int idx)
+{
+        if (idx == PIC_UPPER_INDEX)
+                event <<= sparc_pmu->upper_shift;
+        else
+                event <<= sparc_pmu->lower_shift;
+        return event;
+}
+static u64 mask_for_index(int idx)
+{
+        return event_encoding(sparc_pmu->event_mask, idx);
+}
+static u64 nop_for_index(int idx)
+{
+        return event_encoding(idx == PIC_UPPER_INDEX ?
+                              sparc_pmu->upper_nop :
+                              sparc_pmu->lower_nop, idx);
+}
+static inline void sparc_pmu_enable_counter(struct hw_perf_counter *hwc,
+                                            int idx)
+{
+        u64 val, mask = mask_for_index(idx);
+        val = pcr_ops->read();
+        pcr_ops->write((val & ~mask) | hwc->config);
+}
+static inline void sparc_pmu_disable_counter(struct hw_perf_counter *hwc,
+                                             int idx)
+{
+        u64 mask = mask_for_index(idx);
+        u64 nop = nop_for_index(idx);
+        u64 val = pcr_ops->read();
+        pcr_ops->write((val & ~mask) | nop);
+}
+void hw_perf_enable(void)
+{
+        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+        u64 val;
+        int i;
+        if (cpuc->enabled)
+                return;
+        cpuc->enabled = 1;
+        barrier();
+        val = pcr_ops->read();
+        for (i = 0; i < MAX_HWCOUNTERS; i++) {
+                struct perf_counter *cp = cpuc->counters[i];
+                struct hw_perf_counter *hwc;
+                if (!cp)
+                        continue;
+                hwc = &cp->hw;
+                val |= hwc->config_base;
+        }
+        pcr_ops->write(val);
+}
+void hw_perf_disable(void)
+{
+        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+        u64 val;
+        if (!cpuc->enabled)
+                return;
+        cpuc->enabled = 0;
+        val = pcr_ops->read();
+        val &= ~(PCR_UTRACE | PCR_STRACE |
+                 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
+        pcr_ops->write(val);
+}
+static u32 read_pmc(int idx)
+{
+        u64 val;
+        read_pic(val);
+        if (idx == PIC_UPPER_INDEX)
+                val >>= 32;
+        return val & 0xffffffff;
+}
+static void write_pmc(int idx, u64 val)
+{
+        u64 shift, mask, pic;
+        shift = 0;
+        if (idx == PIC_UPPER_INDEX)
+                shift = 32;
+        mask = ((u64) 0xffffffff) << shift;
+        val <<= shift;
+        read_pic(pic);
+        pic &= ~mask;
+        pic |= val;
+        write_pic(pic);
+}
+static int sparc_perf_counter_set_period(struct perf_counter *counter,
+                                         struct hw_perf_counter *hwc, int idx)
+{
+        s64 left = atomic64_read(&hwc->period_left);
+        s64 period = hwc->sample_period;
+        int ret = 0;
+        if (unlikely(left <= -period)) {
+                left = period;
+                atomic64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+        if (unlikely(left <= 0)) {
+                left += period;
+                atomic64_set(&hwc->period_left, left);
+                hwc->last_period = period;
+                ret = 1;
+        }
+        if (left > MAX_PERIOD)
+                left = MAX_PERIOD;
+        atomic64_set(&hwc->prev_count, (u64)-left);
+        write_pmc(idx, (u64)(-left) & 0xffffffff);
+        perf_counter_update_userpage(counter);
+        return ret;
+}
+static int sparc_pmu_enable(struct perf_counter *counter)
+{
+        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+        struct hw_perf_counter *hwc = &counter->hw;
+        int idx = hwc->idx;
+        if (test_and_set_bit(idx, cpuc->used_mask))
+                return -EAGAIN;
+        sparc_pmu_disable_counter(hwc, idx);
+        cpuc->counters[idx] = counter;
+        set_bit(idx, cpuc->active_mask);
+        sparc_perf_counter_set_period(counter, hwc, idx);
+        sparc_pmu_enable_counter(hwc, idx);
+        perf_counter_update_userpage(counter);
+        return 0;
+}
+static u64 sparc_perf_counter_update(struct perf_counter *counter,
+                                     struct hw_perf_counter *hwc, int idx)
+{
+        int shift = 64 - 32;
+        u64 prev_raw_count, new_raw_count;
+        s64 delta;
+again:
+        prev_raw_count = atomic64_read(&hwc->prev_count);
+        new_raw_count = read_pmc(idx);
+        if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
+                             new_raw_count) != prev_raw_count)
+                goto again;
+        delta = (new_raw_count << shift) - (prev_raw_count << shift);
+        delta >>= shift;
+        atomic64_add(delta, &counter->count);
+        atomic64_sub(delta, &hwc->period_left);
+        return new_raw_count;
+}
+static void sparc_pmu_disable(struct perf_counter *counter)
+{
+        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+        struct hw_perf_counter *hwc = &counter->hw;
+        int idx = hwc->idx;
+        clear_bit(idx, cpuc->active_mask);
+        sparc_pmu_disable_counter(hwc, idx);
+        barrier();
+        sparc_perf_counter_update(counter, hwc, idx);
+        cpuc->counters[idx] = NULL;
+        clear_bit(idx, cpuc->used_mask);
+        perf_counter_update_userpage(counter);
+}
+static void sparc_pmu_read(struct perf_counter *counter)
+{
+        struct hw_perf_counter *hwc = &counter->hw;
+        sparc_perf_counter_update(counter, hwc, hwc->idx);
+}
+static void sparc_pmu_unthrottle(struct perf_counter *counter)
+{
+        struct hw_perf_counter *hwc = &counter->hw;
+        sparc_pmu_enable_counter(hwc, hwc->idx);
+}
+static atomic_t active_counters = ATOMIC_INIT(0);
+static DEFINE_MUTEX(pmc_grab_mutex);
+void perf_counter_grab_pmc(void)
+{
+        if (atomic_inc_not_zero(&active_counters))
+                return;
+        mutex_lock(&pmc_grab_mutex);
+        if (atomic_read(&active_counters) == 0) {
+                if (atomic_read(&nmi_active) > 0) {
+                        on_each_cpu(stop_nmi_watchdog, NULL, 1);
+                        BUG_ON(atomic_read(&nmi_active) != 0);
+                }
+                atomic_inc(&active_counters);
+        }
+        mutex_unlock(&pmc_grab_mutex);
+}
+void perf_counter_release_pmc(void)
+{
+        if (atomic_dec_and_mutex_lock(&active_counters, &pmc_grab_mutex)) {
+                if (atomic_read(&nmi_active) == 0)
+                        on_each_cpu(start_nmi_watchdog, NULL, 1);
+                mutex_unlock(&pmc_grab_mutex);
+        }
+}
+static void hw_perf_counter_destroy(struct perf_counter *counter)
+{
+        perf_counter_release_pmc();
+}
+static int __hw_perf_counter_init(struct perf_counter *counter)
+{
+        struct perf_counter_attr *attr = &counter->attr;
+        struct hw_perf_counter *hwc = &counter->hw;
+        const struct perf_event_map *pmap;
+        u64 enc;
+        if (atomic_read(&nmi_active) < 0)
+                return -ENODEV;
+        if (attr->type != PERF_TYPE_HARDWARE)
+                return -EOPNOTSUPP;
+        if (attr->config >= sparc_pmu->max_events)
+                return -EINVAL;
+        perf_counter_grab_pmc();
+        counter->destroy = hw_perf_counter_destroy;
+        /* We save the enable bits in the config_base.  So to
+         * turn off sampling just write 'config', and to enable
+         * things write 'config | config_base'.
+         */
+        hwc->config_base = sparc_pmu->irq_bit;
+        if (!attr->exclude_user)
+                hwc->config_base |= PCR_UTRACE;
+        if (!attr->exclude_kernel)
+                hwc->config_base |= PCR_STRACE;
+        if (!attr->exclude_hv)
+                hwc->config_base |= sparc_pmu->hv_bit;
+        if (!hwc->sample_period) {
+                hwc->sample_period = MAX_PERIOD;
+                hwc->last_period = hwc->sample_period;
+                atomic64_set(&hwc->period_left, hwc->sample_period);
+        }
+        pmap = sparc_pmu->event_map(attr->config);
+        enc = pmap->encoding;
+        if (pmap->pic_mask & PIC_UPPER) {
+                hwc->idx = PIC_UPPER_INDEX;
+                enc <<= sparc_pmu->upper_shift;
+        } else {
+                hwc->idx = PIC_LOWER_INDEX;
+                enc <<= sparc_pmu->lower_shift;
+        }
+        hwc->config |= enc;
+        return 0;
+}
+static const struct pmu pmu = {
+        .enable         = sparc_pmu_enable,
+        .disable        = sparc_pmu_disable,
+        .read           = sparc_pmu_read,
+        .unthrottle     = sparc_pmu_unthrottle,
+};
+const struct pmu *hw_perf_counter_init(struct perf_counter *counter)
+{
+        int err = __hw_perf_counter_init(counter);
+        if (err)
+                return ERR_PTR(err);
+        return &pmu;
+}
+void perf_counter_print_debug(void)
+{
+        unsigned long flags;
+        u64 pcr, pic;
+        int cpu;
+        if (!sparc_pmu)
+                return;
+        local_irq_save(flags);
+        cpu = smp_processor_id();
+        pcr = pcr_ops->read();
+        read_pic(pic);
+        pr_info("\n");
+        pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
+                cpu, pcr, pic);
+        local_irq_restore(flags);
+}
+static int __kprobes perf_counter_nmi_handler(struct notifier_block *self,
+                                              unsigned long cmd, void *__args)
+{
+        struct die_args *args = __args;
+        struct perf_sample_data data;
+        struct cpu_hw_counters *cpuc;
+        struct pt_regs *regs;
+        int idx;
+        if (!atomic_read(&active_counters))
+                return NOTIFY_DONE;
+        switch (cmd) {
+        case DIE_NMI:
+                break;
+        default:
+                return NOTIFY_DONE;
+        }
+        regs = args->regs;
+        data.regs = regs;
+        data.addr = 0;
+        cpuc = &__get_cpu_var(cpu_hw_counters);
+        for (idx = 0; idx < MAX_HWCOUNTERS; idx++) {
+                struct perf_counter *counter = cpuc->counters[idx];
+                struct hw_perf_counter *hwc;
+                u64 val;
+                if (!test_bit(idx, cpuc->active_mask))
+                        continue;
+                hwc = &counter->hw;
+                val = sparc_perf_counter_update(counter, hwc, idx);
+                if (val & (1ULL << 31))
+                        continue;
+                data.period = counter->hw.last_period;
+                if (!sparc_perf_counter_set_period(counter, hwc, idx))
+                        continue;
+                if (perf_counter_overflow(counter, 1, &data))
+                        sparc_pmu_disable_counter(hwc, idx);
+        }
+        return NOTIFY_STOP;
+}
+static __read_mostly struct notifier_block perf_counter_nmi_notifier = {
+        .notifier_call          = perf_counter_nmi_handler,
+};
+static bool __init supported_pmu(void)
+{
+        if (!strcmp(sparc_pmu_type, "ultra3i")) {
+                sparc_pmu = &ultra3i_pmu;
+                return true;
+        }
+        if (!strcmp(sparc_pmu_type, "niagara2")) {
+                sparc_pmu = &niagara2_pmu;
+                return true;
+        }
+        return false;
+}
+void __init init_hw_perf_counters(void)
+{
+        pr_info("Performance counters: ");
+        if (!supported_pmu()) {
+                pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
+                return;
+        }
+        pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
+        /* All sparc64 PMUs currently have 2 counters.  But this simple
+         * driver only supports one active counter at a time.
+         */
+        perf_max_counters = 1;
+        register_die_notifier(&perf_counter_nmi_notifier);
+}
diff --git a/arch/sparc/kernel/process_64.c b/arch/sparc/kernel/process_64.c
index 4041f94e7724..18d67854a1b8 100644
--- a/arch/sparc/kernel/process_64.c
+++ b/arch/sparc/kernel/process_64.c
@@ -251,7 +251,7 @@ static void __global_reg_poll(struct global_reg_snapshot *gp)
        }
 }
-void __trigger_all_cpu_backtrace(void)
+void arch_trigger_all_cpu_backtrace(void)
 {
        struct thread_info *tp = current_thread_info();
        struct pt_regs *regs = get_irq_regs();
@@ -304,7 +304,7 @@ void __trigger_all_cpu_backtrace(void)
 static void sysrq_handle_globreg(int key, struct tty_struct *tty)
 {
-        __trigger_all_cpu_backtrace();
+        arch_trigger_all_cpu_backtrace();
 }
 static struct sysrq_key_op sparc_globalreg_op = {
diff --git a/arch/sparc/kernel/prom_32.c b/arch/sparc/kernel/prom_32.c
index fe43e80772db..0a37e8cfd160 100644
--- a/arch/sparc/kernel/prom_32.c
+++ b/arch/sparc/kernel/prom_32.c
@@ -24,6 +24,8 @@
 #include <asm/prom.h>
 #include <asm/oplib.h>
+#include <asm/leon.h>
+#include <asm/leon_amba.h>
 #include "prom.h"
@@ -131,6 +133,35 @@ static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
                regs->which_io, regs->phys_addr);
 }
+/* "name:vendor:device@irq,addrlo" */
+static void __init ambapp_path_component(struct device_node *dp, char *tmp_buf)
+{
+        struct amba_prom_registers *regs; unsigned int *intr;
+        unsigned int *device, *vendor;
+        struct property *prop;
+        prop = of_find_property(dp, "reg", NULL);
+        if (!prop)
+                return;
+        regs = prop->value;
+        prop = of_find_property(dp, "interrupts", NULL);
+        if (!prop)
+                return;
+        intr = prop->value;
+        prop = of_find_property(dp, "vendor", NULL);
+        if (!prop)
+                return;
+        vendor = prop->value;
+        prop = of_find_property(dp, "device", NULL);
+        if (!prop)
+                return;
+        device = prop->value;
+        sprintf(tmp_buf, "%s:%d:%d@%x,%x",
+                dp->name, *vendor, *device,
+                *intr, regs->phys_addr);
+}
 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
 {
        struct device_node *parent = dp->parent;
@@ -143,6 +174,8 @@ static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
                        return sbus_path_component(dp, tmp_buf);
                if (!strcmp(parent->type, "ebus"))
                        return ebus_path_component(dp, tmp_buf);
+                if (!strcmp(parent->type, "ambapp"))
+                        return ambapp_path_component(dp, tmp_buf);
                /* "isa" is handled with platform naming */
        }
diff --git a/arch/sparc/kernel/prom_common.c b/arch/sparc/kernel/prom_common.c
index 0fb5789d43c8..138910c67206 100644
--- a/arch/sparc/kernel/prom_common.c
+++ b/arch/sparc/kernel/prom_common.c
@@ -22,9 +22,12 @@
 #include <linux/of.h>
 #include <asm/prom.h>
 #include <asm/oplib.h>
+#include <asm/leon.h>
 #include "prom.h"
+void (*prom_build_more)(struct device_node *dp, struct device_node ***nextp);
 struct device_node *of_console_device;
 EXPORT_SYMBOL(of_console_device);
@@ -161,7 +164,7 @@ static struct property * __init build_one_prop(phandle node, char *prev,
                        name = prom_nextprop(node, prev, p->name);
                }
-                if (strlen(name) == 0) {
+                if (!name || strlen(name) == 0) {
                        tmp = p;
                        return NULL;
                }
@@ -242,7 +245,7 @@ static struct device_node * __init prom_create_node(phandle node,
        return dp;
 }
-static char * __init build_full_name(struct device_node *dp)
+char * __init build_full_name(struct device_node *dp)
 {
        int len, ourlen, plen;
        char *n;
@@ -289,6 +292,9 @@ static struct device_node * __init prom_build_tree(struct device_node *parent,
                dp->child = prom_build_tree(dp, prom_getchild(node), nextp);
+                if (prom_build_more)
+                        prom_build_more(dp, nextp);
                node = prom_getsibling(node);
        }
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 998cadb4e7f2..16a47ffe03c1 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -235,6 +235,8 @@ void __init setup_arch(char **cmdline_p)
                sparc_cpu_model = sun4e;
        if (!strcmp(&cputypval,"sun4u"))
                sparc_cpu_model = sun4u;
+        if (!strncmp(&cputypval, "leon" , 4))
+                sparc_cpu_model = sparc_leon;
        printk("ARCH: ");
        switch(sparc_cpu_model) {
@@ -256,6 +258,9 @@ void __init setup_arch(char **cmdline_p)
        case sun4u:
                printk("SUN4U\n");
                break;
+        case sparc_leon:
+                printk("LEON\n");
+                break;
        default:
                printk("UNKNOWN!\n");
                break;
diff --git a/arch/sparc/kernel/signal_32.c b/arch/sparc/kernel/signal_32.c
index 181d069a2d44..7ce1a1005b1d 100644
--- a/arch/sparc/kernel/signal_32.c
+++ b/arch/sparc/kernel/signal_32.c
@@ -590,6 +590,8 @@ void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0,
        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
 }
diff --git a/arch/sparc/kernel/signal_64.c b/arch/sparc/kernel/signal_64.c
index ec82d76dc6f2..647afbda7ae1 100644
--- a/arch/sparc/kernel/signal_64.c
+++ b/arch/sparc/kernel/signal_64.c
@@ -613,5 +613,8 @@ void do_notify_resume(struct pt_regs *regs, unsigned long orig_i0, unsigned long
        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
 }
diff --git a/arch/sparc/kernel/sys32.S b/arch/sparc/kernel/sys32.S
index aed94869ad6a..e7061138c98a 100644
--- a/arch/sparc/kernel/sys32.S
+++ b/arch/sparc/kernel/sys32.S
@@ -121,7 +121,7 @@ SIGN2(sys32_syslog, sys_syslog, %o0, %o2)
 SIGN1(sys32_umask, sys_umask, %o0)
 SIGN3(sys32_tgkill, sys_tgkill, %o0, %o1, %o2)
 SIGN1(sys32_sendto, sys_sendto, %o0)
-SIGN1(sys32_recvfrom, sys_recvfrom, %o0)
+SIGN1(sys32_recvfrom, compat_sys_recvfrom, %o0)
 SIGN3(sys32_socket, sys_socket, %o0, %o1, %o2)
 SIGN2(sys32_connect, sys_connect, %o0, %o2)
 SIGN2(sys32_bind, sys_bind, %o0, %o2)
diff --git a/arch/sparc/kernel/sysfs.c b/arch/sparc/kernel/sysfs.c
index d28f496f4669..ca39c606fe8e 100644
--- a/arch/sparc/kernel/sysfs.c
+++ b/arch/sparc/kernel/sysfs.c
@@ -2,6 +2,7 @@
 *
 * Copyright (C) 2007 David S. Miller <davem@davemloft.net>
 */
+#include <linux/sched.h>
 #include <linux/sysdev.h>
 #include <linux/cpu.h>
 #include <linux/smp.h>
diff --git a/arch/sparc/kernel/systbls_32.S b/arch/sparc/kernel/systbls_32.S
index 690901657291..04181577cb65 100644
--- a/arch/sparc/kernel/systbls_32.S
+++ b/arch/sparc/kernel/systbls_32.S
@@ -82,5 +82,5 @@ sys_call_table:
 /*310*/ .long sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
 /*315*/ .long sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1
 /*320*/ .long sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
-/*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo
+/*325*/ .long sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_counter_open
diff --git a/arch/sparc/kernel/systbls_64.S b/arch/sparc/kernel/systbls_64.S
index 2ee7250ba7ae..91b06b7f7acf 100644
--- a/arch/sparc/kernel/systbls_64.S
+++ b/arch/sparc/kernel/systbls_64.S
@@ -83,7 +83,7 @@ sys_call_table32:
 /*310*/ .word compat_sys_utimensat, compat_sys_signalfd, sys_timerfd_create, sys_eventfd, compat_sys_fallocate
        .word compat_sys_timerfd_settime, compat_sys_timerfd_gettime, compat_sys_signalfd4, sys_eventfd2, sys_epoll_create1
 /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, compat_sys_preadv
-        .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo
+        .word compat_sys_pwritev, compat_sys_rt_tgsigqueueinfo, sys_perf_counter_open
 #endif /* CONFIG_COMPAT */
@@ -158,4 +158,4 @@ sys_call_table:
 /*310*/ .word sys_utimensat, sys_signalfd, sys_timerfd_create, sys_eventfd, sys_fallocate
        .word sys_timerfd_settime, sys_timerfd_gettime, sys_signalfd4, sys_eventfd2, sys_epoll_create1
 /*320*/ .word sys_dup3, sys_pipe2, sys_inotify_init1, sys_accept4, sys_preadv
-        .word sys_pwritev, sys_rt_tgsigqueueinfo
+        .word sys_pwritev, sys_rt_tgsigqueueinfo, sys_perf_counter_open
diff --git a/arch/sparc/mm/Makefile b/arch/sparc/mm/Makefile
index 681abe0a4594..79836a7dd00c 100644
--- a/arch/sparc/mm/Makefile
+++ b/arch/sparc/mm/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_SPARC32)   += loadmmu.o
 obj-y                   += generic_$(BITS).o
 obj-$(CONFIG_SPARC32)   += extable.o btfixup.o srmmu.o iommu.o io-unit.o
 obj-$(CONFIG_SPARC32)   += hypersparc.o viking.o tsunami.o swift.o
+obj-$(CONFIG_SPARC_LEON)+= leon_mm.o
 # Only used by sparc64
 obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index 26bb3919ff1f..54114ad0bdee 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -34,6 +34,7 @@
 #include <asm/pgalloc.h>        /* bug in asm-generic/tlb.h: check_pgt_cache */
 #include <asm/tlb.h>
 #include <asm/prom.h>
+#include <asm/leon.h>
 DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -326,6 +327,9 @@ void __init paging_init(void)
                sparc_unmapped_base = 0xe0000000;
                BTFIXUPSET_SETHI(sparc_unmapped_base, 0xe0000000);
                break;
+        case sparc_leon:
+                leon_init();
+                /* fall through */
        case sun4m:
        case sun4d:
                srmmu_paging_init();
diff --git a/arch/sparc/mm/leon_mm.c b/arch/sparc/mm/leon_mm.c
new file mode 100644
index 000000000000..c0e01297e64e
--- /dev/null
+++ b/arch/sparc/mm/leon_mm.c
@@ -0,0 +1,260 @@
+/*
+ *  linux/arch/sparc/mm/leon_m.c
+ *
+ * Copyright (C) 2004 Konrad Eisele (eiselekd@web.de, konrad@gaisler.com) Gaisler Research
+ * Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB
+ * Copyright (C) 2009 Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB
+ *
+ * do srmmu probe in software
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/mm.h>
+#include <asm/asi.h>
+#include <asm/leon.h>
+#include <asm/tlbflush.h>
+int leon_flush_during_switch = 1;
+int srmmu_swprobe_trace;
+unsigned long srmmu_swprobe(unsigned long vaddr, unsigned long *paddr)
+{
+        unsigned int ctxtbl;
+        unsigned int pgd, pmd, ped;
+        unsigned int ptr;
+        unsigned int lvl, pte, paddrbase;
+        unsigned int ctx;
+        unsigned int paddr_calc;
+        paddrbase = 0;
+        if (srmmu_swprobe_trace)
+                printk(KERN_INFO "swprobe: trace on\n");
+        ctxtbl = srmmu_get_ctable_ptr();
+        if (!(ctxtbl)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: srmmu_get_ctable_ptr returned 0=>0\n");
+                return 0;
+        }
+        if (!_pfn_valid(PFN(ctxtbl))) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO
+                               "swprobe: !_pfn_valid(%x)=>0\n",
+                               PFN(ctxtbl));
+                return 0;
+        }
+        ctx = srmmu_get_context();
+        if (srmmu_swprobe_trace)
+                printk(KERN_INFO "swprobe:  --- ctx (%x) ---\n", ctx);
+        pgd = LEON_BYPASS_LOAD_PA(ctxtbl + (ctx * 4));
+        if (((pgd & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: pgd is entry level 3\n");
+                lvl = 3;
+                pte = pgd;
+                paddrbase = pgd & _SRMMU_PTE_PMASK_LEON;
+                goto ready;
+        }
+        if (((pgd & SRMMU_ET_MASK) != SRMMU_ET_PTD)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: pgd is invalid => 0\n");
+                return 0;
+        }
+        if (srmmu_swprobe_trace)
+                printk(KERN_INFO "swprobe:  --- pgd (%x) ---\n", pgd);
+        ptr = (pgd & SRMMU_PTD_PMASK) << 4;
+        ptr += ((((vaddr) >> LEON_PGD_SH) & LEON_PGD_M) * 4);
+        if (!_pfn_valid(PFN(ptr)))
+                return 0;
+        pmd = LEON_BYPASS_LOAD_PA(ptr);
+        if (((pmd & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: pmd is entry level 2\n");
+                lvl = 2;
+                pte = pmd;
+                paddrbase = pmd & _SRMMU_PTE_PMASK_LEON;
+                goto ready;
+        }
+        if (((pmd & SRMMU_ET_MASK) != SRMMU_ET_PTD)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: pmd is invalid => 0\n");
+                return 0;
+        }
+        if (srmmu_swprobe_trace)
+                printk(KERN_INFO "swprobe:  --- pmd (%x) ---\n", pmd);
+        ptr = (pmd & SRMMU_PTD_PMASK) << 4;
+        ptr += (((vaddr >> LEON_PMD_SH) & LEON_PMD_M) * 4);
+        if (!_pfn_valid(PFN(ptr))) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: !_pfn_valid(%x)=>0\n",
+                               PFN(ptr));
+                return 0;
+        }
+        ped = LEON_BYPASS_LOAD_PA(ptr);
+        if (((ped & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: ped is entry level 1\n");
+                lvl = 1;
+                pte = ped;
+                paddrbase = ped & _SRMMU_PTE_PMASK_LEON;
+                goto ready;
+        }
+        if (((ped & SRMMU_ET_MASK) != SRMMU_ET_PTD)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: ped is invalid => 0\n");
+                return 0;
+        }
+        if (srmmu_swprobe_trace)
+                printk(KERN_INFO "swprobe:  --- ped (%x) ---\n", ped);
+        ptr = (ped & SRMMU_PTD_PMASK) << 4;
+        ptr += (((vaddr >> LEON_PTE_SH) & LEON_PTE_M) * 4);
+        if (!_pfn_valid(PFN(ptr)))
+                return 0;
+        ptr = LEON_BYPASS_LOAD_PA(ptr);
+        if (((ptr & SRMMU_ET_MASK) == SRMMU_ET_PTE)) {
+                if (srmmu_swprobe_trace)
+                        printk(KERN_INFO "swprobe: ptr is entry level 0\n");
+                lvl = 0;
+                pte = ptr;
+                paddrbase = ptr & _SRMMU_PTE_PMASK_LEON;
+                goto ready;
+        }
+        if (srmmu_swprobe_trace)
+                printk(KERN_INFO "swprobe: ptr is invalid => 0\n");
+        return 0;
+ready:
+        switch (lvl) {
+        case 0:
+                paddr_calc =
+                    (vaddr & ~(-1 << LEON_PTE_SH)) | ((pte & ~0xff) << 4);
+                break;
+        case 1:
+                paddr_calc =
+                    (vaddr & ~(-1 << LEON_PMD_SH)) | ((pte & ~0xff) << 4);
+                break;
+        case 2:
+                paddr_calc =
+                    (vaddr & ~(-1 << LEON_PGD_SH)) | ((pte & ~0xff) << 4);
+                break;
+        default:
+        case 3:
+                paddr_calc = vaddr;
+                break;
+        }
+        if (srmmu_swprobe_trace)
+                printk(KERN_INFO "swprobe: padde %x\n", paddr_calc);
+        if (paddr)
+                *paddr = paddr_calc;
+        return paddrbase;
+}
+void leon_flush_icache_all(void)
+{
+        __asm__ __volatile__(" flush ");        /*iflush*/
+}
+void leon_flush_dcache_all(void)
+{
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
+                             "i"(ASI_LEON_DFLUSH) : "memory");
+}
+void leon_flush_pcache_all(struct vm_area_struct *vma, unsigned long page)
+{
+        if (vma->vm_flags & VM_EXEC)
+                leon_flush_icache_all();
+        leon_flush_dcache_all();
+}
+void leon_flush_cache_all(void)
+{
+        __asm__ __volatile__(" flush ");        /*iflush*/
+        __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t" : :
+                             "i"(ASI_LEON_DFLUSH) : "memory");
+}
+void leon_flush_tlb_all(void)
+{
+        leon_flush_cache_all();
+        __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : : "r"(0x400),
+                             "i"(ASI_LEON_MMUFLUSH) : "memory");
+}
+/* get all cache regs */
+void leon3_getCacheRegs(struct leon3_cacheregs *regs)
+{
+        unsigned long ccr, iccr, dccr;
+        if (!regs)
+                return;
+        /* Get Cache regs from "Cache ASI" address 0x0, 0x8 and 0xC */
+        __asm__ __volatile__("lda [%%g0] %3, %0\n\t"
+                             "mov 0x08, %%g1\n\t"
+                             "lda [%%g1] %3, %1\n\t"
+                             "mov 0x0c, %%g1\n\t"
+                             "lda [%%g1] %3, %2\n\t"
+                             : "=r"(ccr), "=r"(iccr), "=r"(dccr)
+                               /* output */
+                             : "i"(ASI_LEON_CACHEREGS)  /* input */
+                             : "g1"     /* clobber list */
+            );
+        regs->ccr = ccr;
+        regs->iccr = iccr;
+        regs->dccr = dccr;
+}
+/* Due to virtual cache we need to check cache configuration if
+ * it is possible to skip flushing in some cases.
+ *
+ * Leon2 and Leon3 differ in their way of telling cache information
+ *
+ */
+int leon_flush_needed(void)
+{
+        int flush_needed = -1;
+        unsigned int ssize, sets;
+        char *setStr[4] =
+            { "direct mapped", "2-way associative", "3-way associative",
+                "4-way associative"
+        };
+        /* leon 3 */
+        struct leon3_cacheregs cregs;
+        leon3_getCacheRegs(&cregs);
+        sets = (cregs.dccr & LEON3_XCCR_SETS_MASK) >> 24;
+        /* (ssize=>realsize) 0=>1k, 1=>2k, 2=>4k, 3=>8k ... */
+        ssize = 1 << ((cregs.dccr & LEON3_XCCR_SSIZE_MASK) >> 20);
+        printk(KERN_INFO "CACHE: %s cache, set size %dk\n",
+               sets > 3 ? "unknown" : setStr[sets], ssize);
+        if ((ssize <= (PAGE_SIZE / 1024)) && (sets == 0)) {
+                /* Set Size <= Page size  ==>
+                   flush on every context switch not needed. */
+                flush_needed = 0;
+                printk(KERN_INFO "CACHE: not flushing on every context switch\n");
+        }
+        return flush_needed;
+}
+void leon_switch_mm(void)
+{
+        flush_tlb_mm((void *)0);
+        if (leon_flush_during_switch)
+                leon_flush_cache_all();
+}
diff --git a/arch/sparc/mm/loadmmu.c b/arch/sparc/mm/loadmmu.c
index 652be05acbea..82ec8f666036 100644
--- a/arch/sparc/mm/loadmmu.c
+++ b/arch/sparc/mm/loadmmu.c
@@ -33,6 +33,7 @@ void __init load_mmu(void)
                break;
        case sun4m:
        case sun4d:
+        case sparc_leon:
                ld_mmu_srmmu();
                break;
        default:
diff --git a/arch/sparc/mm/srmmu.c b/arch/sparc/mm/srmmu.c
index ade4eb373bdd..509b1ffeba66 100644
--- a/arch/sparc/mm/srmmu.c
+++ b/arch/sparc/mm/srmmu.c
@@ -46,6 +46,7 @@
 #include <asm/tsunami.h>
 #include <asm/swift.h>
 #include <asm/turbosparc.h>
+#include <asm/leon.h>
 #include <asm/btfixup.h>
@@ -569,6 +570,9 @@ static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
                srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
        }
+        if (sparc_cpu_model == sparc_leon)
+                leon_switch_mm();
        if (is_hypersparc)
                hyper_flush_whole_icache();
@@ -1977,6 +1981,45 @@ static void __init init_viking(void)
        poke_srmmu = poke_viking;
 }
+#ifdef CONFIG_SPARC_LEON
+void __init poke_leonsparc(void)
+{
+}
+void __init init_leon(void)
+{
+        srmmu_name = "Leon";
+        BTFIXUPSET_CALL(flush_cache_all, leon_flush_cache_all,
+                        BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_cache_mm, leon_flush_cache_all,
+                        BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_cache_page, leon_flush_pcache_all,
+                        BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_cache_range, leon_flush_cache_all,
+                        BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_page_for_dma, leon_flush_dcache_all,
+                        BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_tlb_all, leon_flush_tlb_all, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_tlb_mm, leon_flush_tlb_all, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_tlb_page, leon_flush_tlb_all, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(flush_tlb_range, leon_flush_tlb_all, BTFIXUPCALL_NORM);
+        BTFIXUPSET_CALL(__flush_page_to_ram, leon_flush_cache_all,
+                        BTFIXUPCALL_NOP);
+        BTFIXUPSET_CALL(flush_sig_insns, leon_flush_cache_all, BTFIXUPCALL_NOP);
+        poke_srmmu = poke_leonsparc;
+        srmmu_cache_pagetables = 0;
+        leon_flush_during_switch = leon_flush_needed();
+}
+#endif
 /* Probe for the srmmu chip version. */
 static void __init get_srmmu_type(void)
 {
@@ -1992,7 +2035,15 @@ static void __init get_srmmu_type(void)
        psr_typ = (psr >> 28) & 0xf;
        psr_vers = (psr >> 24) & 0xf;
-        /* First, check for HyperSparc or Cypress. */
+        /* First, check for sparc-leon. */
+        if (sparc_cpu_model == sparc_leon) {
+                psr_typ = 0xf;  /* hardcoded ids for older models/simulators */
+                psr_vers = 2;
+                init_leon();
+                return;
+        }
+        /* Second, check for HyperSparc or Cypress. */
        if(mod_typ == 1) {
                switch(mod_rev) {
                case 7:
diff --git a/arch/sparc/oprofile/init.c b/arch/sparc/oprofile/init.c
index d172f86439b1..f97cb8b6ee5f 100644
--- a/arch/sparc/oprofile/init.c
+++ b/arch/sparc/oprofile/init.c
@@ -21,7 +21,7 @@
 static int profile_timer_exceptions_notify(struct notifier_block *self,
                                           unsigned long val, void *data)
 {
-        struct die_args *args = (struct die_args *)data;
+        struct die_args *args = data;
        int ret = NOTIFY_DONE;
        switch (val) {
@@ -57,7 +57,7 @@ static void timer_stop(void)
 static int op_nmi_timer_init(struct oprofile_operations *ops)
 {
-        if (!nmi_usable)
+        if (atomic_read(&nmi_active) <= 0)
                return -ENODEV;
        ops->start = timer_start;
diff --git a/arch/um/drivers/net_kern.c b/arch/um/drivers/net_kern.c
index 3b44b47c7e1d..f114813ae258 100644
--- a/arch/um/drivers/net_kern.c
+++ b/arch/um/drivers/net_kern.c
@@ -245,7 +245,7 @@ static int uml_net_start_xmit(struct sk_buff *skb, struct net_device *dev)
        dev_kfree_skb(skb);
-        return 0;
+        return NETDEV_TX_OK;
 }
 static void uml_net_set_multicast_list(struct net_device *dev)
@@ -285,7 +285,7 @@ static void uml_net_get_drvinfo(struct net_device *dev,
        strcpy(info->version, "42");
 }
-static struct ethtool_ops uml_net_ethtool_ops = {
+static const struct ethtool_ops uml_net_ethtool_ops = {
        .get_drvinfo    = uml_net_get_drvinfo,
        .get_link       = ethtool_op_get_link,
 };
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index f46f30d23eb0..c71a8f8bdba8 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -587,7 +587,6 @@ config GART_IOMMU
        bool "GART IOMMU support" if EMBEDDED
        default y
        select SWIOTLB
-        select AGP
        depends on X86_64 && PCI
        ---help---
          Support for full DMA access of devices with 32bit memory access only
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 8130334329c0..527519b8a9f9 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -262,6 +262,15 @@ config MCORE2
          family in /proc/cpuinfo. Newer ones have 6 and older ones 15
          (not a typo)
+config MATOM
+        bool "Intel Atom"
+        ---help---
+          Select this for the Intel Atom platform. Intel Atom CPUs have an
+          in-order pipelining architecture and thus can benefit from
+          accordingly optimized code. Use a recent GCC with specific Atom
+          support in order to fully benefit from selecting this option.
 config GENERIC_CPU
        bool "Generic-x86-64"
        depends on X86_64
@@ -295,7 +304,7 @@ config X86_CPU
 config X86_L1_CACHE_BYTES
        int
        default "128" if MPSC
-        default "64" if GENERIC_CPU || MK8 || MCORE2 || X86_32
+        default "64" if GENERIC_CPU || MK8 || MCORE2 || MATOM || X86_32
 config X86_INTERNODE_CACHE_BYTES
        int
@@ -310,7 +319,7 @@ config X86_L1_CACHE_SHIFT
        default "7" if MPENTIUM4 || MPSC
        default "4" if X86_ELAN || M486 || M386 || MGEODEGX1
        default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
-        default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MVIAC7 || X86_GENERIC || GENERIC_CPU
+        default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
 config X86_XADD
        def_bool y
@@ -359,7 +368,7 @@ config X86_INTEL_USERCOPY
 config X86_USE_PPRO_CHECKSUM
        def_bool y
-        depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2
+        depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
 config X86_USE_3DNOW
        def_bool y
@@ -387,7 +396,7 @@ config X86_P6_NOP
 config X86_TSC
        def_bool y
-        depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2) && !X86_NUMAQ) || X86_64
+        depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64
 config X86_CMPXCHG64
        def_bool y
@@ -397,7 +406,7 @@ config X86_CMPXCHG64
 # generates cmov.
 config X86_CMOV
        def_bool y
-        depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64)
+        depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM)
 config X86_MINIMUM_CPU_FAMILY
        int
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 1b68659c41b4..7983c420eaf2 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -32,8 +32,8 @@ ifeq ($(CONFIG_X86_32),y)
        # Disable unit-at-a-time mode on pre-gcc-4.0 compilers, it makes gcc use
        # a lot more stack due to the lack of sharing of stacklots:
-        KBUILD_CFLAGS += $(shell if [ $(call cc-version) -lt 0400 ] ; then \
+        KBUILD_CFLAGS += $(call cc-ifversion, -lt, 0400, \
-                echo $(call cc-option,-fno-unit-at-a-time); fi ;)
+                                $(call cc-option,-fno-unit-at-a-time))
        # CPU-specific tuning. Anything which can be shared with UML should go here.
        include $(srctree)/arch/x86/Makefile_32.cpu
@@ -55,6 +55,8 @@ else
        cflags-$(CONFIG_MCORE2) += \
                $(call cc-option,-march=core2,$(call cc-option,-mtune=generic))
+        cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom) \
+                $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
        cflags-$(CONFIG_GENERIC_CPU) += $(call cc-option,-mtune=generic)
        KBUILD_CFLAGS += $(cflags-y)
@@ -72,7 +74,7 @@ endif
 ifdef CONFIG_CC_STACKPROTECTOR
        cc_has_sp := $(srctree)/scripts/gcc-x86_$(BITS)-has-stack-protector.sh
-        ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC)),y)
+        ifeq ($(shell $(CONFIG_SHELL) $(cc_has_sp) $(CC) $(biarch)),y)
                stackp-y := -fstack-protector
                stackp-$(CONFIG_CC_STACKPROTECTOR_ALL) += -fstack-protector-all
                KBUILD_CFLAGS += $(stackp-y)
diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu
index 80177ec052f0..30e9a264f69d 100644
--- a/arch/x86/Makefile_32.cpu
+++ b/arch/x86/Makefile_32.cpu
@@ -33,6 +33,8 @@ cflags-$(CONFIG_MCYRIXIII)	+= $(call cc-option,-march=c3,-march=i486) $(align)-f
 cflags-$(CONFIG_MVIAC3_2)       += $(call cc-option,-march=c3-2,-march=i686)
 cflags-$(CONFIG_MVIAC7)         += -march=i686
 cflags-$(CONFIG_MCORE2)         += -march=i686 $(call tune,core2)
+cflags-$(CONFIG_MATOM)          += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \
+        $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
 # AMD Elan support
 cflags-$(CONFIG_X86_ELAN)       += -march=i486
diff --git a/arch/x86/boot/video-vesa.c b/arch/x86/boot/video-vesa.c
index 275dd177f198..11e8c6eb80a1 100644
--- a/arch/x86/boot/video-vesa.c
+++ b/arch/x86/boot/video-vesa.c
@@ -31,7 +31,6 @@ static inline void vesa_store_mode_params_graphics(void) {}
 static int vesa_probe(void)
 {
-#if defined(CONFIG_VIDEO_VESA) || defined(CONFIG_FIRMWARE_EDID)
        struct biosregs ireg, oreg;
        u16 mode;
        addr_t mode_ptr;
@@ -49,8 +48,7 @@ static int vesa_probe(void)
            vginfo.signature != VESA_MAGIC ||
            vginfo.version < 0x0102)
                return 0;       /* Not present */
-#endif /* CONFIG_VIDEO_VESA || CONFIG_FIRMWARE_EDID */
-#ifdef CONFIG_VIDEO_VESA
        set_fs(vginfo.video_mode_ptr.seg);
        mode_ptr = vginfo.video_mode_ptr.off;
@@ -102,9 +100,6 @@ static int vesa_probe(void)
        }
        return nmodes;
-#else
-        return 0;
-#endif /* CONFIG_VIDEO_VESA */
 }
 static int vesa_set_mode(struct mode_info *mode)
diff --git a/arch/x86/boot/video-vga.c b/arch/x86/boot/video-vga.c
index 8f8d827e254d..819caa1f2008 100644
--- a/arch/x86/boot/video-vga.c
+++ b/arch/x86/boot/video-vga.c
@@ -47,14 +47,6 @@ static u8 vga_set_basic_mode(void)
        initregs(&ireg);
-#ifdef CONFIG_VIDEO_400_HACK
-        if (adapter >= ADAPTER_VGA) {
-                ireg.ax = 0x1202;
-                ireg.bx = 0x0030;
-                intcall(0x10, &ireg, NULL);
-        }
-#endif
        ax = 0x0f00;
        intcall(0x10, &ireg, &oreg);
        mode = oreg.al;
@@ -62,11 +54,9 @@ static u8 vga_set_basic_mode(void)
        set_fs(0);
        rows = rdfs8(0x484);    /* rows minus one */
-#ifndef CONFIG_VIDEO_400_HACK
        if ((oreg.ax == 0x5003 || oreg.ax == 0x5007) &&
            (rows == 0 || rows == 24))
                return mode;
-#endif
        if (mode != 3 && mode != 7)
                mode = 3;
diff --git a/arch/x86/boot/video.c b/arch/x86/boot/video.c
index bad728b76fc2..d42da3802499 100644
--- a/arch/x86/boot/video.c
+++ b/arch/x86/boot/video.c
@@ -221,7 +221,6 @@ static unsigned int mode_menu(void)
        }
 }
-#ifdef CONFIG_VIDEO_RETAIN
 /* Save screen content to the heap */
 static struct saved_screen {
        int x, y;
@@ -299,10 +298,6 @@ static void restore_screen(void)
        ireg.dl = saved.curx;
        intcall(0x10, &ireg, NULL);
 }
-#else
-#define save_screen()           ((void)0)
-#define restore_screen()        ((void)0)
-#endif
 void set_video(void)
 {
diff --git a/arch/x86/boot/video.h b/arch/x86/boot/video.h
index 5bb174a997fc..ff339c5db311 100644
--- a/arch/x86/boot/video.h
+++ b/arch/x86/boot/video.h
@@ -17,19 +17,8 @@
 #include <linux/types.h>
-/* Enable autodetection of SVGA adapters and modes. */
+/*
-#undef CONFIG_VIDEO_SVGA
+ * This code uses an extended set of video mode numbers. These include:
-/* Enable autodetection of VESA modes */
-#define CONFIG_VIDEO_VESA
-/* Retain screen contents when switching modes */
-#define CONFIG_VIDEO_RETAIN
-/* Force 400 scan lines for standard modes (hack to fix bad BIOS behaviour */
-#undef CONFIG_VIDEO_400_HACK
-/* This code uses an extended set of video mode numbers. These include:
 * Aliases for standard modes
 *      NORMAL_VGA (-1)
 *      EXTENDED_VGA (-2)
@@ -67,13 +56,8 @@
 /* The "recalculate timings" flag */
 #define VIDEO_RECALC 0x8000
-/* Define DO_STORE according to CONFIG_VIDEO_RETAIN */
-#ifdef CONFIG_VIDEO_RETAIN
 void store_screen(void);
 #define DO_STORE() store_screen()
-#else
-#define DO_STORE() ((void)0)
-#endif /* CONFIG_VIDEO_RETAIN */
 /*
 * Mode table structures
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index c580c5ec1cad..585edebe12cf 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -59,13 +59,6 @@ asmlinkage void aesni_cbc_enc(struct crypto_aes_ctx *ctx, u8 *out,
 asmlinkage void aesni_cbc_dec(struct crypto_aes_ctx *ctx, u8 *out,
                              const u8 *in, unsigned int len, u8 *iv);
-static inline int kernel_fpu_using(void)
-{
-        if (in_interrupt() && !(read_cr0() & X86_CR0_TS))
-                return 1;
-        return 0;
-}
 static inline struct crypto_aes_ctx *aes_ctx(void *raw_ctx)
 {
        unsigned long addr = (unsigned long)raw_ctx;
@@ -89,7 +82,7 @@ static int aes_set_key_common(struct crypto_tfm *tfm, void *raw_ctx,
                return -EINVAL;
        }
-        if (kernel_fpu_using())
+        if (irq_fpu_usable())
                err = crypto_aes_expand_key(ctx, in_key, key_len);
        else {
                kernel_fpu_begin();
@@ -110,7 +103,7 @@ static void aes_encrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
 {
        struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
-        if (kernel_fpu_using())
+        if (irq_fpu_usable())
                crypto_aes_encrypt_x86(ctx, dst, src);
        else {
                kernel_fpu_begin();
@@ -123,7 +116,7 @@ static void aes_decrypt(struct crypto_tfm *tfm, u8 *dst, const u8 *src)
 {
        struct crypto_aes_ctx *ctx = aes_ctx(crypto_tfm_ctx(tfm));
-        if (kernel_fpu_using())
+        if (irq_fpu_usable())
                crypto_aes_decrypt_x86(ctx, dst, src);
        else {
                kernel_fpu_begin();
@@ -349,7 +342,7 @@ static int ablk_encrypt(struct ablkcipher_request *req)
        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
        struct async_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-        if (kernel_fpu_using()) {
+        if (irq_fpu_usable()) {
                struct ablkcipher_request *cryptd_req =
                        ablkcipher_request_ctx(req);
                memcpy(cryptd_req, req, sizeof(*req));
@@ -370,7 +363,7 @@ static int ablk_decrypt(struct ablkcipher_request *req)
        struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
        struct async_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
-        if (kernel_fpu_using()) {
+        if (irq_fpu_usable()) {
                struct ablkcipher_request *cryptd_req =
                        ablkcipher_request_ctx(req);
                memcpy(cryptd_req, req, sizeof(*req));
@@ -636,7 +629,7 @@ static int __init aesni_init(void)
        int err;
        if (!cpu_has_aes) {
-                printk(KERN_ERR "Intel AES-NI instructions are not detected.\n");
+                printk(KERN_INFO "Intel AES-NI instructions are not detected.\n");
                return -ENODEV;
        }
        if ((err = crypto_register_alg(&aesni_alg)))
diff --git a/arch/x86/ia32/ia32entry.S b/arch/x86/ia32/ia32entry.S
index e590261ba059..ba331bfd1112 100644
--- a/arch/x86/ia32/ia32entry.S
+++ b/arch/x86/ia32/ia32entry.S
@@ -537,7 +537,7 @@ ia32_sys_call_table:
        .quad sys_mkdir
        .quad sys_rmdir         /* 40 */
        .quad sys_dup
-        .quad sys32_pipe
+        .quad sys_pipe
        .quad compat_sys_times
        .quad quiet_ni_syscall                  /* old prof syscall holder */
        .quad sys_brk           /* 45 */
diff --git a/arch/x86/ia32/sys_ia32.c b/arch/x86/ia32/sys_ia32.c
index 085a8c35f149..9f5527198825 100644
--- a/arch/x86/ia32/sys_ia32.c
+++ b/arch/x86/ia32/sys_ia32.c
@@ -189,20 +189,6 @@ asmlinkage long sys32_mprotect(unsigned long start, size_t len,
        return sys_mprotect(start, len, prot);
 }
-asmlinkage long sys32_pipe(int __user *fd)
-{
-        int retval;
-        int fds[2];
-        retval = do_pipe_flags(fds, 0);
-        if (retval)
-                goto out;
-        if (copy_to_user(fd, fds, sizeof(fds)))
-                retval = -EFAULT;
-out:
-        return retval;
-}
 asmlinkage long sys32_rt_sigaction(int sig, struct sigaction32 __user *act,
                                   struct sigaction32 __user *oact,
                                   unsigned int sigsetsize)
diff --git a/arch/x86/include/asm/alternative.h b/arch/x86/include/asm/alternative.h
index 1a37bcdc8606..c240efc74e00 100644
--- a/arch/x86/include/asm/alternative.h
+++ b/arch/x86/include/asm/alternative.h
@@ -73,8 +73,6 @@ static inline void alternatives_smp_module_del(struct module *mod) {}
 static inline void alternatives_smp_switch(int smp) {}
 #endif  /* CONFIG_SMP */
-const unsigned char *const *find_nop_table(void);
 /* alternative assembly primitive: */
 #define ALTERNATIVE(oldinstr, newinstr, feature)                        \
                                                                        \
@@ -144,8 +142,6 @@ static inline void apply_paravirt(struct paravirt_patch_site *start,
 #define __parainstructions_end  NULL
 #endif
-extern void add_nops(void *insns, unsigned int len);
 /*
 * Clear and restore the kernel write-protection flag on the local CPU.
 * Allows the kernel to edit read-only pages.
@@ -161,10 +157,7 @@ extern void add_nops(void *insns, unsigned int len);
 * Intel's errata.
 * On the local CPU you need to be protected again NMI or MCE handlers seeing an
 * inconsistent instruction while you patch.
- * The _early version expects the memory to already be RW.
 */
 extern void *text_poke(void *addr, const void *opcode, size_t len);
-extern void *text_poke_early(void *addr, const void *opcode, size_t len);
 #endif /* _ASM_X86_ALTERNATIVE_H */
diff --git a/arch/x86/include/asm/amd_iommu.h b/arch/x86/include/asm/amd_iommu.h
index bdf96f119f06..ac95995b7bad 100644
--- a/arch/x86/include/asm/amd_iommu.h
+++ b/arch/x86/include/asm/amd_iommu.h
@@ -25,6 +25,7 @@
 #ifdef CONFIG_AMD_IOMMU
 extern int amd_iommu_init(void);
 extern int amd_iommu_init_dma_ops(void);
+extern int amd_iommu_init_passthrough(void);
 extern void amd_iommu_detect(void);
 extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
 extern void amd_iommu_flush_all_domains(void);
diff --git a/arch/x86/include/asm/amd_iommu_types.h b/arch/x86/include/asm/amd_iommu_types.h
index 0c878caaa0a2..2a2cc7a78a81 100644
--- a/arch/x86/include/asm/amd_iommu_types.h
+++ b/arch/x86/include/asm/amd_iommu_types.h
@@ -143,22 +143,29 @@
 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 #define EVT_LEN_MASK            (0x9ULL << 56)
+#define PAGE_MODE_NONE    0x00
 #define PAGE_MODE_1_LEVEL 0x01
 #define PAGE_MODE_2_LEVEL 0x02
 #define PAGE_MODE_3_LEVEL 0x03
+#define PAGE_MODE_4_LEVEL 0x04
-#define IOMMU_PDE_NL_0   0x000ULL
+#define PAGE_MODE_5_LEVEL 0x05
-#define IOMMU_PDE_NL_1   0x200ULL
+#define PAGE_MODE_6_LEVEL 0x06
-#define IOMMU_PDE_NL_2   0x400ULL
-#define IOMMU_PDE_NL_3   0x600ULL
+#define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
+#define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
-#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
+                                  ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
-#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
+                                   (0xffffffffffffffffULL))
-#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
+#define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
+#define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
-#define IOMMU_MAP_SIZE_L1 (1ULL << 21)
+#define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
-#define IOMMU_MAP_SIZE_L2 (1ULL << 30)
+                                 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
-#define IOMMU_MAP_SIZE_L3 (1ULL << 39)
+#define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
+#define PM_MAP_4k               0
+#define PM_ADDR_MASK            0x000ffffffffff000ULL
+#define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
+                                (~((1ULL << (12 + ((lvl) * 9))) - 1)))
+#define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 #define IOMMU_PTE_P  (1ULL << 0)
 #define IOMMU_PTE_TV (1ULL << 1)
@@ -167,11 +174,6 @@
 #define IOMMU_PTE_IR (1ULL << 61)
 #define IOMMU_PTE_IW (1ULL << 62)
-#define IOMMU_L1_PDE(address) \
-        ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
-#define IOMMU_L2_PDE(address) \
-        ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
@@ -194,11 +196,14 @@
 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
                                              domain for an IOMMU */
+#define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
+                                              translation */
 extern bool amd_iommu_dump;
 #define DUMP_printk(format, arg...)                                     \
        do {                                                            \
                if (amd_iommu_dump)                                             \
-                        printk(KERN_INFO "AMD IOMMU: " format, ## arg); \
+                        printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
        } while(0);
 /*
@@ -226,6 +231,7 @@ struct protection_domain {
        int mode;               /* paging mode (0-6 levels) */
        u64 *pt_root;           /* page table root pointer */
        unsigned long flags;    /* flags to find out type of domain */
+        bool updated;           /* complete domain flush required */
        unsigned dev_cnt;       /* devices assigned to this domain */
        void *priv;             /* private data */
 };
@@ -337,6 +343,9 @@ struct amd_iommu {
        /* if one, we need to send a completion wait command */
        bool need_sync;
+        /* becomes true if a command buffer reset is running */
+        bool reset_in_progress;
        /* default dma_ops domain for that IOMMU */
        struct dma_ops_domain *default_dom;
 };
@@ -457,4 +466,7 @@ static inline void amd_iommu_stats_init(void) { }
 #endif /* CONFIG_AMD_IOMMU_STATS */
+/* some function prototypes */
+extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index bb7d47925847..586b7adb8e53 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -183,6 +183,10 @@ static inline int x2apic_enabled(void)
 }
 #define x2apic_supported()      (cpu_has_x2apic)
+static inline void x2apic_force_phys(void)
+{
+        x2apic_phys = 1;
+}
 #else
 static inline void check_x2apic(void)
 {
@@ -194,6 +198,9 @@ static inline int x2apic_enabled(void)
 {
        return 0;
 }
+static inline void x2apic_force_phys(void)
+{
+}
 #define x2apic_preenabled 0
 #define x2apic_supported()      0
diff --git a/arch/x86/include/asm/apicdef.h b/arch/x86/include/asm/apicdef.h
index 7ddb36ab933b..3b62da926de9 100644
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -8,12 +8,14 @@
 * Ingo Molnar <mingo@redhat.com>, 1999, 2000
 */
-#define APIC_DEFAULT_PHYS_BASE  0xfee00000
+#define IO_APIC_DEFAULT_PHYS_BASE       0xfec00000
+#define APIC_DEFAULT_PHYS_BASE          0xfee00000
 #define APIC_ID         0x20
 #define APIC_LVR        0x30
 #define         APIC_LVR_MASK           0xFF00FF
+#define         APIC_LVR_DIRECTED_EOI   (1 << 24)
 #define         GET_APIC_VERSION(x)     ((x) & 0xFFu)
 #define         GET_APIC_MAXLVT(x)      (((x) >> 16) & 0xFFu)
 #ifdef CONFIG_X86_32
@@ -40,6 +42,7 @@
 #define         APIC_DFR_CLUSTER                0x0FFFFFFFul
 #define         APIC_DFR_FLAT                   0xFFFFFFFFul
 #define APIC_SPIV       0xF0
+#define         APIC_SPIV_DIRECTED_EOI          (1 << 12)
 #define         APIC_SPIV_FOCUS_DISABLED        (1 << 9)
 #define         APIC_SPIV_APIC_ENABLED          (1 << 8)
 #define APIC_ISR        0x100
diff --git a/arch/x86/include/asm/asm.h b/arch/x86/include/asm/asm.h
index 56be78f582f0..b3ed1e1460ff 100644
--- a/arch/x86/include/asm/asm.h
+++ b/arch/x86/include/asm/asm.h
@@ -3,7 +3,7 @@
 #ifdef __ASSEMBLY__
 # define __ASM_FORM(x)  x
-# define __ASM_EX_SEC   .section __ex_table
+# define __ASM_EX_SEC   .section __ex_table, "a"
 #else
 # define __ASM_FORM(x)  " " #x " "
 # define __ASM_EX_SEC   " .section __ex_table,\"a\"\n"
@@ -38,10 +38,18 @@
 #define _ASM_DI         __ASM_REG(di)
 /* Exception table entry */
+#ifdef __ASSEMBLY__
+# define _ASM_EXTABLE(from,to)      \
+        __ASM_EX_SEC ;              \
+        _ASM_ALIGN ;                \
+        _ASM_PTR from , to ;        \
+        .previous
+#else
 # define _ASM_EXTABLE(from,to) \
        __ASM_EX_SEC    \
        _ASM_ALIGN "\n" \
        _ASM_PTR #from "," #to "\n" \
        " .previous\n"
+#endif
 #endif /* _ASM_X86_ASM_H */
diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
index 4a28d22d4793..847fee6493a2 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -95,6 +95,7 @@
 #define X86_FEATURE_NONSTOP_TSC (3*32+24) /* TSC does not stop in C states */
 #define X86_FEATURE_CLFLUSH_MONITOR (3*32+25) /* "" clflush reqd with monitor */
 #define X86_FEATURE_EXTD_APICID (3*32+26) /* has extended APICID (8 bits) */
+#define X86_FEATURE_AMD_DCM     (3*32+27) /* multi-node processor */
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
diff --git a/arch/x86/include/asm/current.h b/arch/x86/include/asm/current.h
index c68c361697e1..4d447b732d82 100644
--- a/arch/x86/include/asm/current.h
+++ b/arch/x86/include/asm/current.h
@@ -11,7 +11,7 @@ DECLARE_PER_CPU(struct task_struct *, current_task);
 static __always_inline struct task_struct *get_current(void)
 {
-        return percpu_read(current_task);
+        return percpu_read_stable(current_task);
 }
 #define current get_current()
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index c993e9e0fed4..e8de2f6f5ca5 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -291,11 +291,24 @@ static inline unsigned long get_desc_base(const struct desc_struct *desc)
        return desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24);
 }
+static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
+{
+        desc->base0 = base & 0xffff;
+        desc->base1 = (base >> 16) & 0xff;
+        desc->base2 = (base >> 24) & 0xff;
+}
 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
 {
        return desc->limit0 | (desc->limit << 16);
 }
+static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
+{
+        desc->limit0 = limit & 0xffff;
+        desc->limit = (limit >> 16) & 0xf;
+}
 static inline void _set_gate(int gate, unsigned type, void *addr,
                             unsigned dpl, unsigned ist, unsigned seg)
 {
diff --git a/arch/x86/include/asm/desc_defs.h b/arch/x86/include/asm/desc_defs.h
index a6adefa28b94..9d6684849fd9 100644
--- a/arch/x86/include/asm/desc_defs.h
+++ b/arch/x86/include/asm/desc_defs.h
@@ -34,6 +34,12 @@ struct desc_struct {
        };
 } __attribute__((packed));
+#define GDT_ENTRY_INIT(flags, base, limit) { { { \
+                .a = ((limit) & 0xffff) | (((base) & 0xffff) << 16), \
+                .b = (((base) & 0xff0000) >> 16) | (((flags) & 0xf0ff) << 8) | \
+                        ((limit) & 0xf0000) | ((base) & 0xff000000), \
+        } } }
 enum {
        GATE_INTERRUPT = 0xE,
        GATE_TRAP = 0xF,
diff --git a/arch/x86/include/asm/device.h b/arch/x86/include/asm/device.h
index 4994a20acbcb..cee34e9ca45b 100644
--- a/arch/x86/include/asm/device.h
+++ b/arch/x86/include/asm/device.h
@@ -13,4 +13,7 @@ struct dma_map_ops *dma_ops;
 #endif
 };
+struct pdev_archdata {
+};
 #endif /* _ASM_X86_DEVICE_H */
diff --git a/arch/x86/include/asm/dma-mapping.h b/arch/x86/include/asm/dma-mapping.h
index 1c3f9435f1c9..0ee770d23d0e 100644
--- a/arch/x86/include/asm/dma-mapping.h
+++ b/arch/x86/include/asm/dma-mapping.h
@@ -55,6 +55,24 @@ extern int dma_set_mask(struct device *dev, u64 mask);
 extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
                                        dma_addr_t *dma_addr, gfp_t flag);
+static inline bool dma_capable(struct device *dev, dma_addr_t addr, size_t size)
+{
+        if (!dev->dma_mask)
+                return 0;
+        return addr + size <= *dev->dma_mask;
+}
+static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr)
+{
+        return paddr;
+}
+static inline phys_addr_t dma_to_phys(struct device *dev, dma_addr_t daddr)
+{
+        return daddr;
+}
 static inline void
 dma_cache_sync(struct device *dev, void *vaddr, size_t size,
        enum dma_data_direction dir)
diff --git a/arch/x86/include/asm/dwarf2.h b/arch/x86/include/asm/dwarf2.h
index 3afc5e87cfdd..ae6253ab9029 100644
--- a/arch/x86/include/asm/dwarf2.h
+++ b/arch/x86/include/asm/dwarf2.h
@@ -87,9 +87,25 @@
        CFI_RESTORE \reg
        .endm
 #else /*!CONFIG_X86_64*/
+        .macro pushl_cfi reg
+        pushl \reg
+        CFI_ADJUST_CFA_OFFSET 4
+        .endm
-        /* 32bit defenitions are missed yet */
+        .macro popl_cfi reg
+        popl \reg
+        CFI_ADJUST_CFA_OFFSET -4
+        .endm
+        .macro movl_cfi reg offset=0
+        movl %\reg, \offset(%esp)
+        CFI_REL_OFFSET \reg, \offset
+        .endm
+        .macro movl_cfi_restore offset reg
+        movl \offset(%esp), %\reg
+        CFI_RESTORE \reg
+        .endm
 #endif /*!CONFIG_X86_64*/
 #endif /*__ASSEMBLY__*/
diff --git a/arch/x86/include/asm/i387.h b/arch/x86/include/asm/i387.h
index 175adf58dd4f..0b20bbb758f2 100644
--- a/arch/x86/include/asm/i387.h
+++ b/arch/x86/include/asm/i387.h
@@ -26,6 +26,7 @@ extern void fpu_init(void);
 extern void mxcsr_feature_mask_init(void);
 extern int init_fpu(struct task_struct *child);
 extern asmlinkage void math_state_restore(void);
+extern void __math_state_restore(void);
 extern void init_thread_xstate(void);
 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
@@ -301,6 +302,14 @@ static inline void kernel_fpu_end(void)
        preempt_enable();
 }
+static inline bool irq_fpu_usable(void)
+{
+        struct pt_regs *regs;
+        return !in_interrupt() || !(regs = get_irq_regs()) || \
+                user_mode(regs) || (read_cr0() & X86_CR0_TS);
+}
 /*
 * Some instructions like VIA's padlock instructions generate a spurious
 * DNA fault but don't modify SSE registers. And these instructions
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index 330ee807f89e..85232d32fcb8 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -150,11 +150,10 @@ extern int timer_through_8259;
 #define io_apic_assign_pci_irqs \
        (mp_irq_entries && !skip_ioapic_setup && io_apic_irqs)
-#ifdef CONFIG_ACPI
+extern u8 io_apic_unique_id(u8 id);
 extern int io_apic_get_unique_id(int ioapic, int apic_id);
 extern int io_apic_get_version(int ioapic);
 extern int io_apic_get_redir_entries(int ioapic);
-#endif /* CONFIG_ACPI */
 struct io_apic_irq_attr;
 extern int io_apic_set_pci_routing(struct device *dev, int irq,
@@ -177,6 +176,16 @@ extern int setup_ioapic_entry(int apic, int irq,
                              int polarity, int vector, int pin);
 extern void ioapic_write_entry(int apic, int pin,
                               struct IO_APIC_route_entry e);
+struct mp_ioapic_gsi{
+        int gsi_base;
+        int gsi_end;
+};
+extern struct mp_ioapic_gsi  mp_gsi_routing[];
+int mp_find_ioapic(int gsi);
+int mp_find_ioapic_pin(int ioapic, int gsi);
+void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
 #else  /* !CONFIG_X86_IO_APIC */
 #define io_apic_assign_pci_irqs 0
 static const int timer_through_8259 = 0;
diff --git a/arch/x86/include/asm/ioctls.h b/arch/x86/include/asm/ioctls.h
index 0d5b23b7b06e..ec34c760665e 100644
--- a/arch/x86/include/asm/ioctls.h
+++ b/arch/x86/include/asm/ioctls.h
@@ -1,94 +1 @@
-#ifndef _ASM_X86_IOCTLS_H
+#include <asm-generic/ioctls.h>
-#define _ASM_X86_IOCTLS_H
-#include <asm/ioctl.h>
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-#define TCGETS          0x5401
-#define TCSETS          0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
-#define TCSETSW         0x5403
-#define TCSETSF         0x5404
-#define TCGETA          0x5405
-#define TCSETA          0x5406
-#define TCSETAW         0x5407
-#define TCSETAF         0x5408
-#define TCSBRK          0x5409
-#define TCXONC          0x540A
-#define TCFLSH          0x540B
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-#define TIOCGPGRP       0x540F
-#define TIOCSPGRP       0x5410
-#define TIOCOUTQ        0x5411
-#define TIOCSTI         0x5412
-#define TIOCGWINSZ      0x5413
-#define TIOCSWINSZ      0x5414
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define FIONREAD        0x541B
-#define TIOCINQ         FIONREAD
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-#define FIONBIO         0x5421
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-/* #define TIOCTTYGSTRUCT 0x5426 - Former debugging-only ioctl */
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TCGETS2         _IOR('T', 0x2A, struct termios2)
-#define TCSETS2         _IOW('T', 0x2B, struct termios2)
-#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
-#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
-#define TIOCGRS485      0x542E
-#define TIOCSRS485      0x542F
-#define TIOCGPTN        _IOR('T', 0x30, unsigned int)
-                                /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
-#define TCGETX          0x5432 /* SYS5 TCGETX compatibility */
-#define TCSETX          0x5433
-#define TCSETXF         0x5434
-#define TCSETXW         0x5435
-#define FIONCLEX        0x5450
-#define FIOCLEX         0x5451
-#define FIOASYNC        0x5452
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-#define TIOCGHAYESESP   0x545E  /* Get Hayes ESP configuration */
-#define TIOCSHAYESESP   0x545F  /* Set Hayes ESP configuration */
-#define FIOQSIZE        0x5460
-/* Used for packet mode */
-#define TIOCPKT_DATA             0
-#define TIOCPKT_FLUSHREAD        1
-#define TIOCPKT_FLUSHWRITE       2
-#define TIOCPKT_STOP             4
-#define TIOCPKT_START            8
-#define TIOCPKT_NOSTOP          16
-#define TIOCPKT_DOSTOP          32
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
-#endif /* _ASM_X86_IOCTLS_H */
diff --git a/arch/x86/include/asm/ipcbuf.h b/arch/x86/include/asm/ipcbuf.h
index ee678fd51594..84c7e51cb6d0 100644
--- a/arch/x86/include/asm/ipcbuf.h
+++ b/arch/x86/include/asm/ipcbuf.h
@@ -1,28 +1 @@
-#ifndef _ASM_X86_IPCBUF_H
+#include <asm-generic/ipcbuf.h>
-#define _ASM_X86_IPCBUF_H
-/*
- * The ipc64_perm structure for x86 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode_t and seq
- * - 2 miscellaneous 32-bit values
- */
-struct ipc64_perm {
-        __kernel_key_t          key;
-        __kernel_uid32_t        uid;
-        __kernel_gid32_t        gid;
-        __kernel_uid32_t        cuid;
-        __kernel_gid32_t        cgid;
-        __kernel_mode_t         mode;
-        unsigned short          __pad1;
-        unsigned short          seq;
-        unsigned short          __pad2;
-        unsigned long           __unused1;
-        unsigned long           __unused2;
-};
-#endif /* _ASM_X86_IPCBUF_H */
diff --git a/arch/x86/include/asm/irqflags.h b/arch/x86/include/asm/irqflags.h
index c6ccbe7e81ad..9e2b952f810a 100644
--- a/arch/x86/include/asm/irqflags.h
+++ b/arch/x86/include/asm/irqflags.h
@@ -13,14 +13,13 @@ static inline unsigned long native_save_fl(void)
        unsigned long flags;
        /*
-         * Note: this needs to be "=r" not "=rm", because we have the
+         * "=rm" is safe here, because "pop" adjusts the stack before
-         * stack offset from what gcc expects at the time the "pop" is
+         * it evaluates its effective address -- this is part of the
-         * executed, and so a memory reference with respect to the stack
+         * documented behavior of the "pop" instruction.
-         * would end up using the wrong address.
         */
        asm volatile("# __raw_save_flags\n\t"
                     "pushf ; pop %0"
-                     : "=r" (flags)
+                     : "=rm" (flags)
                     : /* no input */
                     : "memory");
diff --git a/arch/x86/include/asm/kvm.h b/arch/x86/include/asm/kvm.h
index 125be8b19568..4a5fe914dc59 100644
--- a/arch/x86/include/asm/kvm.h
+++ b/arch/x86/include/asm/kvm.h
@@ -17,6 +17,8 @@
 #define __KVM_HAVE_USER_NMI
 #define __KVM_HAVE_GUEST_DEBUG
 #define __KVM_HAVE_MSIX
+#define __KVM_HAVE_MCE
+#define __KVM_HAVE_PIT_STATE2
 /* Architectural interrupt line count. */
 #define KVM_NR_INTERRUPTS 256
@@ -236,6 +238,14 @@ struct kvm_pit_state {
        struct kvm_pit_channel_state channels[3];
 };
+#define KVM_PIT_FLAGS_HPET_LEGACY  0x00000001
+struct kvm_pit_state2 {
+        struct kvm_pit_channel_state channels[3];
+        __u32 flags;
+        __u32 reserved[9];
+};
 struct kvm_reinject_control {
        __u8 pit_reinject;
        __u8 reserved[31];
diff --git a/arch/x86/include/asm/kvm_x86_emulate.h b/arch/x86/include/asm/kvm_emulate.h
index b7ed2c423116..b7ed2c423116 100644
--- a/arch/x86/include/asm/kvm_x86_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index eabdc1cfab5c..3be000435fad 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -14,6 +14,7 @@
 #include <linux/types.h>
 #include <linux/mm.h>
 #include <linux/mmu_notifier.h>
+#include <linux/tracepoint.h>
 #include <linux/kvm.h>
 #include <linux/kvm_para.h>
@@ -37,12 +38,14 @@
 #define CR3_L_MODE_RESERVED_BITS (CR3_NONPAE_RESERVED_BITS |    \
                                  0xFFFFFF0000000000ULL)
-#define KVM_GUEST_CR0_MASK                                 \
+#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
-        (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE \
+        (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
-         | X86_CR0_NW | X86_CR0_CD)
+#define KVM_GUEST_CR0_MASK                                              \
+        (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
+#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
+        (X86_CR0_WP | X86_CR0_NE | X86_CR0_TS | X86_CR0_MP)
 #define KVM_VM_CR0_ALWAYS_ON                                            \
-        (X86_CR0_PG | X86_CR0_PE | X86_CR0_WP | X86_CR0_NE | X86_CR0_TS \
+        (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
-         | X86_CR0_MP)
 #define KVM_GUEST_CR4_MASK                                              \
        (X86_CR4_VME | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_PGE | X86_CR4_VMXE)
 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
@@ -51,12 +54,12 @@
 #define INVALID_PAGE (~(hpa_t)0)
 #define UNMAPPED_GVA (~(gpa_t)0)
-/* shadow tables are PAE even on non-PAE hosts */
+/* KVM Hugepage definitions for x86 */
-#define KVM_HPAGE_SHIFT 21
+#define KVM_NR_PAGE_SIZES       3
-#define KVM_HPAGE_SIZE (1UL << KVM_HPAGE_SHIFT)
+#define KVM_HPAGE_SHIFT(x)      (PAGE_SHIFT + (((x) - 1) * 9))
-#define KVM_HPAGE_MASK (~(KVM_HPAGE_SIZE - 1))
+#define KVM_HPAGE_SIZE(x)       (1UL << KVM_HPAGE_SHIFT(x))
+#define KVM_HPAGE_MASK(x)       (~(KVM_HPAGE_SIZE(x) - 1))
-#define KVM_PAGES_PER_HPAGE (KVM_HPAGE_SIZE / PAGE_SIZE)
+#define KVM_PAGES_PER_HPAGE(x)  (KVM_HPAGE_SIZE(x) / PAGE_SIZE)
 #define DE_VECTOR 0
 #define DB_VECTOR 1
@@ -120,6 +123,10 @@ enum kvm_reg {
        NR_VCPU_REGS
 };
+enum kvm_reg_ex {
+        VCPU_EXREG_PDPTR = NR_VCPU_REGS,
+};
 enum {
        VCPU_SREG_ES,
        VCPU_SREG_CS,
@@ -131,7 +138,7 @@ enum {
        VCPU_SREG_LDTR,
 };
-#include <asm/kvm_x86_emulate.h>
+#include <asm/kvm_emulate.h>
 #define KVM_NR_MEM_OBJS 40
@@ -308,7 +315,6 @@ struct kvm_vcpu_arch {
        struct {
                gfn_t gfn;      /* presumed gfn during guest pte update */
                pfn_t pfn;      /* pfn corresponding to that gfn */
-                int largepage;
                unsigned long mmu_seq;
        } update_pte;
@@ -334,16 +340,6 @@ struct kvm_vcpu_arch {
                u8 nr;
        } interrupt;
-        struct {
-                int vm86_active;
-                u8 save_iopl;
-                struct kvm_save_segment {
-                        u16 selector;
-                        unsigned long base;
-                        u32 limit;
-                        u32 ar;
-                } tr, es, ds, fs, gs;
-        } rmode;
        int halt_request; /* real mode on Intel only */
        int cpuid_nent;
@@ -366,13 +362,15 @@ struct kvm_vcpu_arch {
        u32 pat;
        int switch_db_regs;
-        unsigned long host_db[KVM_NR_DB_REGS];
-        unsigned long host_dr6;
-        unsigned long host_dr7;
        unsigned long db[KVM_NR_DB_REGS];
        unsigned long dr6;
        unsigned long dr7;
        unsigned long eff_db[KVM_NR_DB_REGS];
+        u64 mcg_cap;
+        u64 mcg_status;
+        u64 mcg_ctl;
+        u64 *mce_banks;
 };
 struct kvm_mem_alias {
@@ -409,6 +407,7 @@ struct kvm_arch{
        struct page *ept_identity_pagetable;
        bool ept_identity_pagetable_done;
+        gpa_t ept_identity_map_addr;
        unsigned long irq_sources_bitmap;
        unsigned long irq_states[KVM_IOAPIC_NUM_PINS];
@@ -526,6 +525,9 @@ struct kvm_x86_ops {
        int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
        int (*get_tdp_level)(void);
        u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
+        bool (*gb_page_enable)(void);
+        const struct trace_print_flags *exit_reasons_str;
 };
 extern struct kvm_x86_ops *kvm_x86_ops;
@@ -618,6 +620,7 @@ void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr);
 void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2,
                           u32 error_code);
+bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl);
 int kvm_pic_set_irq(void *opaque, int irq, int level);
@@ -752,8 +755,6 @@ static inline void kvm_inject_gp(struct kvm_vcpu *vcpu, u32 error_code)
        kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
 }
-#define MSR_IA32_TIME_STAMP_COUNTER             0x010
 #define TSS_IOPB_BASE_OFFSET 0x66
 #define TSS_BASE_SIZE 0x68
 #define TSS_IOPB_SIZE (65536 / 8)
@@ -796,5 +797,8 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 int kvm_age_hva(struct kvm *kvm, unsigned long hva);
 int cpuid_maxphyaddr(struct kvm_vcpu *vcpu);
+int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu);
+int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu);
+int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
 #endif /* _ASM_X86_KVM_HOST_H */
diff --git a/arch/x86/include/asm/kvm_para.h b/arch/x86/include/asm/kvm_para.h
index b8a3305ae093..c584076a47f4 100644
--- a/arch/x86/include/asm/kvm_para.h
+++ b/arch/x86/include/asm/kvm_para.h
@@ -1,6 +1,8 @@
 #ifndef _ASM_X86_KVM_PARA_H
 #define _ASM_X86_KVM_PARA_H
+#include <linux/types.h>
 /* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx.  It
 * should be used to determine that a VM is running under KVM.
 */
diff --git a/arch/x86/include/asm/lguest.h b/arch/x86/include/asm/lguest.h
index 5136dad57cbb..0d97deba1e35 100644
--- a/arch/x86/include/asm/lguest.h
+++ b/arch/x86/include/asm/lguest.h
@@ -90,8 +90,9 @@ static inline void lguest_set_ts(void)
 }
 /* Full 4G segment descriptors, suitable for CS and DS. */
-#define FULL_EXEC_SEGMENT ((struct desc_struct){ { {0x0000ffff, 0x00cf9b00} } })
+#define FULL_EXEC_SEGMENT \
-#define FULL_SEGMENT ((struct desc_struct){ { {0x0000ffff, 0x00cf9300} } })
+        ((struct desc_struct)GDT_ENTRY_INIT(0xc09b, 0, 0xfffff))
+#define FULL_SEGMENT ((struct desc_struct)GDT_ENTRY_INIT(0xc093, 0, 0xfffff))
 #endif /* __ASSEMBLY__ */
diff --git a/arch/x86/include/asm/mman.h b/arch/x86/include/asm/mman.h
index 751af2550ed9..593e51d4643f 100644
--- a/arch/x86/include/asm/mman.h
+++ b/arch/x86/include/asm/mman.h
@@ -1,20 +1,8 @@
 #ifndef _ASM_X86_MMAN_H
 #define _ASM_X86_MMAN_H
-#include <asm-generic/mman-common.h>
 #define MAP_32BIT       0x40            /* only give out 32bit addresses */
-#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
+#include <asm-generic/mman.h>
-#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
-#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
-#define MAP_LOCKED      0x2000          /* pages are locked */
-#define MAP_NORESERVE   0x4000          /* don't check for reservations */
-#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
-#define MAP_NONBLOCK    0x10000         /* do not block on IO */
-#define MAP_STACK       0x20000         /* give out an address that is best suited for process/thread stacks */
-#define MCL_CURRENT     1               /* lock all current mappings */
-#define MCL_FUTURE      2               /* lock all future mappings */
 #endif /* _ASM_X86_MMAN_H */
diff --git a/arch/x86/include/asm/module.h b/arch/x86/include/asm/module.h
index 47d62743c4d5..3e2ce58a31a3 100644
--- a/arch/x86/include/asm/module.h
+++ b/arch/x86/include/asm/module.h
@@ -1,18 +1,7 @@
 #ifndef _ASM_X86_MODULE_H
 #define _ASM_X86_MODULE_H
-/* x86_32/64 are simple */
+#include <asm-generic/module.h>
-struct mod_arch_specific {};
-#ifdef CONFIG_X86_32
-# define Elf_Shdr Elf32_Shdr
-# define Elf_Sym Elf32_Sym
-# define Elf_Ehdr Elf32_Ehdr
-#else
-# define Elf_Shdr Elf64_Shdr
-# define Elf_Sym Elf64_Sym
-# define Elf_Ehdr Elf64_Ehdr
-#endif
 #ifdef CONFIG_X86_64
 /* X86_64 does not define MODULE_PROC_FAMILY */
@@ -28,6 +17,8 @@ struct mod_arch_specific {};
 #define MODULE_PROC_FAMILY "586MMX "
 #elif defined CONFIG_MCORE2
 #define MODULE_PROC_FAMILY "CORE2 "
+#elif defined CONFIG_MATOM
+#define MODULE_PROC_FAMILY "ATOM "
 #elif defined CONFIG_M686
 #define MODULE_PROC_FAMILY "686 "
 #elif defined CONFIG_MPENTIUMII
diff --git a/arch/x86/include/asm/msgbuf.h b/arch/x86/include/asm/msgbuf.h
index 7e4e9481f51c..809134c644a6 100644
--- a/arch/x86/include/asm/msgbuf.h
+++ b/arch/x86/include/asm/msgbuf.h
@@ -1,39 +1 @@
-#ifndef _ASM_X86_MSGBUF_H
+#include <asm-generic/msgbuf.h>
-#define _ASM_X86_MSGBUF_H
-/*
- * The msqid64_ds structure for i386 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space on i386 is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- *
- * Pad space on x8664 is left for:
- * - 2 miscellaneous 64-bit values
- */
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-#ifdef __i386__
-        unsigned long   __unused1;
-#endif
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-#ifdef __i386__
-        unsigned long   __unused2;
-#endif
-        __kernel_time_t msg_ctime;      /* last change time */
-#ifdef __i386__
-        unsigned long   __unused3;
-#endif
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-#endif /* _ASM_X86_MSGBUF_H */
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6be7fc254b59..bd5549034a95 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -374,6 +374,7 @@
 /* AMD-V MSRs */
 #define MSR_VM_CR                       0xc0010114
+#define MSR_VM_IGNNE                    0xc0010115
 #define MSR_VM_HSAVE_PA                 0xc0010117
 #endif /* _ASM_X86_MSR_INDEX_H */
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 48ad9d29484a..7e2b6ba962ff 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -3,10 +3,16 @@
 #include <asm/msr-index.h>
-#ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
+#include <linux/ioctl.h>
+#define X86_IOC_RDMSR_REGS      _IOWR('c', 0xA0, __u32[8])
+#define X86_IOC_WRMSR_REGS      _IOWR('c', 0xA1, __u32[8])
+#ifdef __KERNEL__
 #include <asm/asm.h>
 #include <asm/errno.h>
 #include <asm/cpumask.h>
@@ -67,23 +73,7 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
                     ".previous\n\t"
                     _ASM_EXTABLE(2b, 3b)
                     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
-                     : "c" (msr), [fault] "i" (-EFAULT));
+                     : "c" (msr), [fault] "i" (-EIO));
-        return EAX_EDX_VAL(val, low, high);
-}
-static inline unsigned long long native_read_msr_amd_safe(unsigned int msr,
-                                                      int *err)
-{
-        DECLARE_ARGS(val, low, high);
-        asm volatile("2: rdmsr ; xor %0,%0\n"
-                     "1:\n\t"
-                     ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %3,%0 ; jmp 1b\n\t"
-                     ".previous\n\t"
-                     _ASM_EXTABLE(2b, 3b)
-                     : "=r" (*err), EAX_EDX_RET(val, low, high)
-                     : "c" (msr), "D" (0x9c5a203a), "i" (-EFAULT));
        return EAX_EDX_VAL(val, low, high);
 }
@@ -106,13 +96,16 @@ notrace static inline int native_write_msr_safe(unsigned int msr,
                     _ASM_EXTABLE(2b, 3b)
                     : [err] "=a" (err)
                     : "c" (msr), "0" (low), "d" (high),
-                       [fault] "i" (-EFAULT)
+                       [fault] "i" (-EIO)
                     : "memory");
        return err;
 }
 extern unsigned long long native_read_tsc(void);
+extern int native_rdmsr_safe_regs(u32 regs[8]);
+extern int native_wrmsr_safe_regs(u32 regs[8]);
 static __always_inline unsigned long long __native_read_tsc(void)
 {
        DECLARE_ARGS(val, low, high);
@@ -181,14 +174,44 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
        *p = native_read_msr_safe(msr, &err);
        return err;
 }
 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
 {
+        u32 gprs[8] = { 0 };
        int err;
-        *p = native_read_msr_amd_safe(msr, &err);
+        gprs[1] = msr;
+        gprs[7] = 0x9c5a203a;
+        err = native_rdmsr_safe_regs(gprs);
+        *p = gprs[0] | ((u64)gprs[2] << 32);
        return err;
 }
+static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
+{
+        u32 gprs[8] = { 0 };
+        gprs[0] = (u32)val;
+        gprs[1] = msr;
+        gprs[2] = val >> 32;
+        gprs[7] = 0x9c5a203a;
+        return native_wrmsr_safe_regs(gprs);
+}
+static inline int rdmsr_safe_regs(u32 regs[8])
+{
+        return native_rdmsr_safe_regs(regs);
+}
+static inline int wrmsr_safe_regs(u32 regs[8])
+{
+        return native_wrmsr_safe_regs(regs);
+}
 #define rdtscl(low)                                             \
        ((low) = (u32)__native_read_tsc())
@@ -228,6 +251,8 @@ void rdmsr_on_cpus(const cpumask_t *mask, u32 msr_no, struct msr *msrs);
 void wrmsr_on_cpus(const cpumask_t *mask, u32 msr_no, struct msr *msrs);
 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
+int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]);
 #else  /*  CONFIG_SMP  */
 static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
@@ -258,7 +283,15 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
        return wrmsr_safe(msr_no, l, h);
 }
+static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
+{
+        return rdmsr_safe_regs(regs);
+}
+static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8])
+{
+        return wrmsr_safe_regs(regs);
+}
 #endif  /* CONFIG_SMP */
-#endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
 #endif /* _ASM_X86_MSR_H */
diff --git a/arch/x86/include/asm/nmi.h b/arch/x86/include/asm/nmi.h
index c86e5ed4af51..e63cf7d441e1 100644
--- a/arch/x86/include/asm/nmi.h
+++ b/arch/x86/include/asm/nmi.h
@@ -45,8 +45,8 @@ extern int proc_nmi_enabled(struct ctl_table *, int , struct file *,
                        void __user *, size_t *, loff_t *);
 extern int unknown_nmi_panic;
-void __trigger_all_cpu_backtrace(void);
+void arch_trigger_all_cpu_backtrace(void);
-#define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
+#define arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
 static inline void localise_nmi_watchdog(void)
 {
diff --git a/arch/x86/include/asm/param.h b/arch/x86/include/asm/param.h
index 6f0d0422f4ca..965d45427975 100644
--- a/arch/x86/include/asm/param.h
+++ b/arch/x86/include/asm/param.h
@@ -1,22 +1 @@
-#ifndef _ASM_X86_PARAM_H
+#include <asm-generic/param.h>
-#define _ASM_X86_PARAM_H
-#ifdef __KERNEL__
-# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ        100             /* some user interfaces are */
-# define CLOCKS_PER_SEC (USER_HZ)       /* in "ticks" like times() */
-#endif
-#ifndef HZ
-#define HZ 100
-#endif
-#define EXEC_PAGESIZE   4096
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-#endif /* _ASM_X86_PARAM_H */
diff --git a/arch/x86/include/asm/paravirt.h b/arch/x86/include/asm/paravirt.h
index 4fb37c8a0832..40d6586af25b 100644
--- a/arch/x86/include/asm/paravirt.h
+++ b/arch/x86/include/asm/paravirt.h
@@ -7,689 +7,11 @@
 #include <asm/pgtable_types.h>
 #include <asm/asm.h>
-/* Bitmask of what can be clobbered: usually at least eax. */
+#include <asm/paravirt_types.h>
-#define CLBR_NONE 0
-#define CLBR_EAX  (1 << 0)
-#define CLBR_ECX  (1 << 1)
-#define CLBR_EDX  (1 << 2)
-#define CLBR_EDI  (1 << 3)
-#ifdef CONFIG_X86_32
-/* CLBR_ANY should match all regs platform has. For i386, that's just it */
-#define CLBR_ANY  ((1 << 4) - 1)
-#define CLBR_ARG_REGS   (CLBR_EAX | CLBR_EDX | CLBR_ECX)
-#define CLBR_RET_REG    (CLBR_EAX | CLBR_EDX)
-#define CLBR_SCRATCH    (0)
-#else
-#define CLBR_RAX  CLBR_EAX
-#define CLBR_RCX  CLBR_ECX
-#define CLBR_RDX  CLBR_EDX
-#define CLBR_RDI  CLBR_EDI
-#define CLBR_RSI  (1 << 4)
-#define CLBR_R8   (1 << 5)
-#define CLBR_R9   (1 << 6)
-#define CLBR_R10  (1 << 7)
-#define CLBR_R11  (1 << 8)
-#define CLBR_ANY  ((1 << 9) - 1)
-#define CLBR_ARG_REGS   (CLBR_RDI | CLBR_RSI | CLBR_RDX | \
-                         CLBR_RCX | CLBR_R8 | CLBR_R9)
-#define CLBR_RET_REG    (CLBR_RAX)
-#define CLBR_SCRATCH    (CLBR_R10 | CLBR_R11)
-#include <asm/desc_defs.h>
-#endif /* X86_64 */
-#define CLBR_CALLEE_SAVE ((CLBR_ARG_REGS | CLBR_SCRATCH) & ~CLBR_RET_REG)
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
 #include <linux/cpumask.h>
-#include <asm/kmap_types.h>
-#include <asm/desc_defs.h>
-struct page;
-struct thread_struct;
-struct desc_ptr;
-struct tss_struct;
-struct mm_struct;
-struct desc_struct;
-struct task_struct;
-/*
- * Wrapper type for pointers to code which uses the non-standard
- * calling convention.  See PV_CALL_SAVE_REGS_THUNK below.
- */
-struct paravirt_callee_save {
-        void *func;
-};
-/* general info */
-struct pv_info {
-        unsigned int kernel_rpl;
-        int shared_kernel_pmd;
-        int paravirt_enabled;
-        const char *name;
-};
-struct pv_init_ops {
-        /*
-         * Patch may replace one of the defined code sequences with
-         * arbitrary code, subject to the same register constraints.
-         * This generally means the code is not free to clobber any
-         * registers other than EAX.  The patch function should return
-         * the number of bytes of code generated, as we nop pad the
-         * rest in generic code.
-         */
-        unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
-                          unsigned long addr, unsigned len);
-        /* Basic arch-specific setup */
-        void (*arch_setup)(void);
-        char *(*memory_setup)(void);
-        void (*post_allocator_init)(void);
-        /* Print a banner to identify the environment */
-        void (*banner)(void);
-};
-struct pv_lazy_ops {
-        /* Set deferred update mode, used for batching operations. */
-        void (*enter)(void);
-        void (*leave)(void);
-};
-struct pv_time_ops {
-        void (*time_init)(void);
-        /* Set and set time of day */
-        unsigned long (*get_wallclock)(void);
-        int (*set_wallclock)(unsigned long);
-        unsigned long long (*sched_clock)(void);
-        unsigned long (*get_tsc_khz)(void);
-};
-struct pv_cpu_ops {
-        /* hooks for various privileged instructions */
-        unsigned long (*get_debugreg)(int regno);
-        void (*set_debugreg)(int regno, unsigned long value);
-        void (*clts)(void);
-        unsigned long (*read_cr0)(void);
-        void (*write_cr0)(unsigned long);
-        unsigned long (*read_cr4_safe)(void);
-        unsigned long (*read_cr4)(void);
-        void (*write_cr4)(unsigned long);
-#ifdef CONFIG_X86_64
-        unsigned long (*read_cr8)(void);
-        void (*write_cr8)(unsigned long);
-#endif
-        /* Segment descriptor handling */
-        void (*load_tr_desc)(void);
-        void (*load_gdt)(const struct desc_ptr *);
-        void (*load_idt)(const struct desc_ptr *);
-        void (*store_gdt)(struct desc_ptr *);
-        void (*store_idt)(struct desc_ptr *);
-        void (*set_ldt)(const void *desc, unsigned entries);
-        unsigned long (*store_tr)(void);
-        void (*load_tls)(struct thread_struct *t, unsigned int cpu);
-#ifdef CONFIG_X86_64
-        void (*load_gs_index)(unsigned int idx);
-#endif
-        void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
-                                const void *desc);
-        void (*write_gdt_entry)(struct desc_struct *,
-                                int entrynum, const void *desc, int size);
-        void (*write_idt_entry)(gate_desc *,
-                                int entrynum, const gate_desc *gate);
-        void (*alloc_ldt)(struct desc_struct *ldt, unsigned entries);
-        void (*free_ldt)(struct desc_struct *ldt, unsigned entries);
-        void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
-        void (*set_iopl_mask)(unsigned mask);
-        void (*wbinvd)(void);
-        void (*io_delay)(void);
-        /* cpuid emulation, mostly so that caps bits can be disabled */
-        void (*cpuid)(unsigned int *eax, unsigned int *ebx,
-                      unsigned int *ecx, unsigned int *edx);
-        /* MSR, PMC and TSR operations.
-           err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
-        u64 (*read_msr_amd)(unsigned int msr, int *err);
-        u64 (*read_msr)(unsigned int msr, int *err);
-        int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
-        u64 (*read_tsc)(void);
-        u64 (*read_pmc)(int counter);
-        unsigned long long (*read_tscp)(unsigned int *aux);
-        /*
-         * Atomically enable interrupts and return to userspace.  This
-         * is only ever used to return to 32-bit processes; in a
-         * 64-bit kernel, it's used for 32-on-64 compat processes, but
-         * never native 64-bit processes.  (Jump, not call.)
-         */
-        void (*irq_enable_sysexit)(void);
-        /*
-         * Switch to usermode gs and return to 64-bit usermode using
-         * sysret.  Only used in 64-bit kernels to return to 64-bit
-         * processes.  Usermode register state, including %rsp, must
-         * already be restored.
-         */
-        void (*usergs_sysret64)(void);
-        /*
-         * Switch to usermode gs and return to 32-bit usermode using
-         * sysret.  Used to return to 32-on-64 compat processes.
-         * Other usermode register state, including %esp, must already
-         * be restored.
-         */
-        void (*usergs_sysret32)(void);
-        /* Normal iret.  Jump to this with the standard iret stack
-           frame set up. */
-        void (*iret)(void);
-        void (*swapgs)(void);
-        void (*start_context_switch)(struct task_struct *prev);
-        void (*end_context_switch)(struct task_struct *next);
-};
-struct pv_irq_ops {
-        void (*init_IRQ)(void);
-        /*
-         * Get/set interrupt state.  save_fl and restore_fl are only
-         * expected to use X86_EFLAGS_IF; all other bits
-         * returned from save_fl are undefined, and may be ignored by
-         * restore_fl.
-         *
-         * NOTE: These functions callers expect the callee to preserve
-         * more registers than the standard C calling convention.
-         */
-        struct paravirt_callee_save save_fl;
-        struct paravirt_callee_save restore_fl;
-        struct paravirt_callee_save irq_disable;
-        struct paravirt_callee_save irq_enable;
-        void (*safe_halt)(void);
-        void (*halt)(void);
-#ifdef CONFIG_X86_64
-        void (*adjust_exception_frame)(void);
-#endif
-};
-struct pv_apic_ops {
-#ifdef CONFIG_X86_LOCAL_APIC
-        void (*setup_boot_clock)(void);
-        void (*setup_secondary_clock)(void);
-        void (*startup_ipi_hook)(int phys_apicid,
-                                 unsigned long start_eip,
-                                 unsigned long start_esp);
-#endif
-};
-struct pv_mmu_ops {
-        /*
-         * Called before/after init_mm pagetable setup. setup_start
-         * may reset %cr3, and may pre-install parts of the pagetable;
-         * pagetable setup is expected to preserve any existing
-         * mapping.
-         */
-        void (*pagetable_setup_start)(pgd_t *pgd_base);
-        void (*pagetable_setup_done)(pgd_t *pgd_base);
-        unsigned long (*read_cr2)(void);
-        void (*write_cr2)(unsigned long);
-        unsigned long (*read_cr3)(void);
-        void (*write_cr3)(unsigned long);
-        /*
-         * Hooks for intercepting the creation/use/destruction of an
-         * mm_struct.
-         */
-        void (*activate_mm)(struct mm_struct *prev,
-                            struct mm_struct *next);
-        void (*dup_mmap)(struct mm_struct *oldmm,
-                         struct mm_struct *mm);
-        void (*exit_mmap)(struct mm_struct *mm);
-        /* TLB operations */
-        void (*flush_tlb_user)(void);
-        void (*flush_tlb_kernel)(void);
-        void (*flush_tlb_single)(unsigned long addr);
-        void (*flush_tlb_others)(const struct cpumask *cpus,
-                                 struct mm_struct *mm,
-                                 unsigned long va);
-        /* Hooks for allocating and freeing a pagetable top-level */
-        int  (*pgd_alloc)(struct mm_struct *mm);
-        void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd);
-        /*
-         * Hooks for allocating/releasing pagetable pages when they're
-         * attached to a pagetable
-         */
-        void (*alloc_pte)(struct mm_struct *mm, unsigned long pfn);
-        void (*alloc_pmd)(struct mm_struct *mm, unsigned long pfn);
-        void (*alloc_pmd_clone)(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count);
-        void (*alloc_pud)(struct mm_struct *mm, unsigned long pfn);
-        void (*release_pte)(unsigned long pfn);
-        void (*release_pmd)(unsigned long pfn);
-        void (*release_pud)(unsigned long pfn);
-        /* Pagetable manipulation functions */
-        void (*set_pte)(pte_t *ptep, pte_t pteval);
-        void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
-                           pte_t *ptep, pte_t pteval);
-        void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
-        void (*pte_update)(struct mm_struct *mm, unsigned long addr,
-                           pte_t *ptep);
-        void (*pte_update_defer)(struct mm_struct *mm,
-                                 unsigned long addr, pte_t *ptep);
-        pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr,
-                                        pte_t *ptep);
-        void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr,
-                                        pte_t *ptep, pte_t pte);
-        struct paravirt_callee_save pte_val;
-        struct paravirt_callee_save make_pte;
-        struct paravirt_callee_save pgd_val;
-        struct paravirt_callee_save make_pgd;
-#if PAGETABLE_LEVELS >= 3
-#ifdef CONFIG_X86_PAE
-        void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
-        void (*pte_clear)(struct mm_struct *mm, unsigned long addr,
-                          pte_t *ptep);
-        void (*pmd_clear)(pmd_t *pmdp);
-#endif  /* CONFIG_X86_PAE */
-        void (*set_pud)(pud_t *pudp, pud_t pudval);
-        struct paravirt_callee_save pmd_val;
-        struct paravirt_callee_save make_pmd;
-#if PAGETABLE_LEVELS == 4
-        struct paravirt_callee_save pud_val;
-        struct paravirt_callee_save make_pud;
-        void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
-#endif  /* PAGETABLE_LEVELS == 4 */
-#endif  /* PAGETABLE_LEVELS >= 3 */
-#ifdef CONFIG_HIGHPTE
-        void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
-#endif
-        struct pv_lazy_ops lazy_mode;
-        /* dom0 ops */
-        /* Sometimes the physical address is a pfn, and sometimes its
-           an mfn.  We can tell which is which from the index. */
-        void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx,
-                           phys_addr_t phys, pgprot_t flags);
-};
-struct raw_spinlock;
-struct pv_lock_ops {
-        int (*spin_is_locked)(struct raw_spinlock *lock);
-        int (*spin_is_contended)(struct raw_spinlock *lock);
-        void (*spin_lock)(struct raw_spinlock *lock);
-        void (*spin_lock_flags)(struct raw_spinlock *lock, unsigned long flags);
-        int (*spin_trylock)(struct raw_spinlock *lock);
-        void (*spin_unlock)(struct raw_spinlock *lock);
-};
-/* This contains all the paravirt structures: we get a convenient
- * number for each function using the offset which we use to indicate
- * what to patch. */
-struct paravirt_patch_template {
-        struct pv_init_ops pv_init_ops;
-        struct pv_time_ops pv_time_ops;
-        struct pv_cpu_ops pv_cpu_ops;
-        struct pv_irq_ops pv_irq_ops;
-        struct pv_apic_ops pv_apic_ops;
-        struct pv_mmu_ops pv_mmu_ops;
-        struct pv_lock_ops pv_lock_ops;
-};
-extern struct pv_info pv_info;
-extern struct pv_init_ops pv_init_ops;
-extern struct pv_time_ops pv_time_ops;
-extern struct pv_cpu_ops pv_cpu_ops;
-extern struct pv_irq_ops pv_irq_ops;
-extern struct pv_apic_ops pv_apic_ops;
-extern struct pv_mmu_ops pv_mmu_ops;
-extern struct pv_lock_ops pv_lock_ops;
-#define PARAVIRT_PATCH(x)                                       \
-        (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
-#define paravirt_type(op)                               \
-        [paravirt_typenum] "i" (PARAVIRT_PATCH(op)),    \
-        [paravirt_opptr] "i" (&(op))
-#define paravirt_clobber(clobber)               \
-        [paravirt_clobber] "i" (clobber)
-/*
- * Generate some code, and mark it as patchable by the
- * apply_paravirt() alternate instruction patcher.
- */
-#define _paravirt_alt(insn_string, type, clobber)       \
-        "771:\n\t" insn_string "\n" "772:\n"            \
-        ".pushsection .parainstructions,\"a\"\n"        \
-        _ASM_ALIGN "\n"                                 \
-        _ASM_PTR " 771b\n"                              \
-        "  .byte " type "\n"                            \
-        "  .byte 772b-771b\n"                           \
-        "  .short " clobber "\n"                        \
-        ".popsection\n"
-/* Generate patchable code, with the default asm parameters. */
-#define paravirt_alt(insn_string)                                       \
-        _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
-/* Simple instruction patching code. */
-#define DEF_NATIVE(ops, name, code)                                     \
-        extern const char start_##ops##_##name[], end_##ops##_##name[]; \
-        asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
-unsigned paravirt_patch_nop(void);
-unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len);
-unsigned paravirt_patch_ident_64(void *insnbuf, unsigned len);
-unsigned paravirt_patch_ignore(unsigned len);
-unsigned paravirt_patch_call(void *insnbuf,
-                             const void *target, u16 tgt_clobbers,
-                             unsigned long addr, u16 site_clobbers,
-                             unsigned len);
-unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
-                            unsigned long addr, unsigned len);
-unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
-                                unsigned long addr, unsigned len);
-unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
-                              const char *start, const char *end);
-unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
-                      unsigned long addr, unsigned len);
-int paravirt_disable_iospace(void);
-/*
- * This generates an indirect call based on the operation type number.
- * The type number, computed in PARAVIRT_PATCH, is derived from the
- * offset into the paravirt_patch_template structure, and can therefore be
- * freely converted back into a structure offset.
- */
-#define PARAVIRT_CALL   "call *%c[paravirt_opptr];"
-/*
- * These macros are intended to wrap calls through one of the paravirt
- * ops structs, so that they can be later identified and patched at
- * runtime.
- *
- * Normally, a call to a pv_op function is a simple indirect call:
- * (pv_op_struct.operations)(args...).
- *
- * Unfortunately, this is a relatively slow operation for modern CPUs,
- * because it cannot necessarily determine what the destination
- * address is.  In this case, the address is a runtime constant, so at
- * the very least we can patch the call to e a simple direct call, or
- * ideally, patch an inline implementation into the callsite.  (Direct
- * calls are essentially free, because the call and return addresses
- * are completely predictable.)
- *
- * For i386, these macros rely on the standard gcc "regparm(3)" calling
- * convention, in which the first three arguments are placed in %eax,
- * %edx, %ecx (in that order), and the remaining arguments are placed
- * on the stack.  All caller-save registers (eax,edx,ecx) are expected
- * to be modified (either clobbered or used for return values).
- * X86_64, on the other hand, already specifies a register-based calling
- * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
- * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
- * special handling for dealing with 4 arguments, unlike i386.
- * However, x86_64 also have to clobber all caller saved registers, which
- * unfortunately, are quite a bit (r8 - r11)
- *
- * The call instruction itself is marked by placing its start address
- * and size into the .parainstructions section, so that
- * apply_paravirt() in arch/i386/kernel/alternative.c can do the
- * appropriate patching under the control of the backend pv_init_ops
- * implementation.
- *
- * Unfortunately there's no way to get gcc to generate the args setup
- * for the call, and then allow the call itself to be generated by an
- * inline asm.  Because of this, we must do the complete arg setup and
- * return value handling from within these macros.  This is fairly
- * cumbersome.
- *
- * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
- * It could be extended to more arguments, but there would be little
- * to be gained from that.  For each number of arguments, there are
- * the two VCALL and CALL variants for void and non-void functions.
- *
- * When there is a return value, the invoker of the macro must specify
- * the return type.  The macro then uses sizeof() on that type to
- * determine whether its a 32 or 64 bit value, and places the return
- * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
- * 64-bit). For x86_64 machines, it just returns at %rax regardless of
- * the return value size.
- *
- * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
- * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
- * in low,high order
- *
- * Small structures are passed and returned in registers.  The macro
- * calling convention can't directly deal with this, so the wrapper
- * functions must do this.
- *
- * These PVOP_* macros are only defined within this header.  This
- * means that all uses must be wrapped in inline functions.  This also
- * makes sure the incoming and outgoing types are always correct.
- */
-#ifdef CONFIG_X86_32
-#define PVOP_VCALL_ARGS                         \
-        unsigned long __eax = __eax, __edx = __edx, __ecx = __ecx
-#define PVOP_CALL_ARGS                  PVOP_VCALL_ARGS
-#define PVOP_CALL_ARG1(x)               "a" ((unsigned long)(x))
-#define PVOP_CALL_ARG2(x)               "d" ((unsigned long)(x))
-#define PVOP_CALL_ARG3(x)               "c" ((unsigned long)(x))
-#define PVOP_VCALL_CLOBBERS             "=a" (__eax), "=d" (__edx),     \
-                                        "=c" (__ecx)
-#define PVOP_CALL_CLOBBERS              PVOP_VCALL_CLOBBERS
-#define PVOP_VCALLEE_CLOBBERS           "=a" (__eax), "=d" (__edx)
-#define PVOP_CALLEE_CLOBBERS            PVOP_VCALLEE_CLOBBERS
-#define EXTRA_CLOBBERS
-#define VEXTRA_CLOBBERS
-#else  /* CONFIG_X86_64 */
-#define PVOP_VCALL_ARGS                                 \
-        unsigned long __edi = __edi, __esi = __esi,     \
-                __edx = __edx, __ecx = __ecx
-#define PVOP_CALL_ARGS          PVOP_VCALL_ARGS, __eax
-#define PVOP_CALL_ARG1(x)               "D" ((unsigned long)(x))
-#define PVOP_CALL_ARG2(x)               "S" ((unsigned long)(x))
-#define PVOP_CALL_ARG3(x)               "d" ((unsigned long)(x))
-#define PVOP_CALL_ARG4(x)               "c" ((unsigned long)(x))
-#define PVOP_VCALL_CLOBBERS     "=D" (__edi),                           \
-                                "=S" (__esi), "=d" (__edx),             \
-                                "=c" (__ecx)
-#define PVOP_CALL_CLOBBERS      PVOP_VCALL_CLOBBERS, "=a" (__eax)
-#define PVOP_VCALLEE_CLOBBERS   "=a" (__eax)
-#define PVOP_CALLEE_CLOBBERS    PVOP_VCALLEE_CLOBBERS
-#define EXTRA_CLOBBERS   , "r8", "r9", "r10", "r11"
-#define VEXTRA_CLOBBERS  , "rax", "r8", "r9", "r10", "r11"
-#endif  /* CONFIG_X86_32 */
-#ifdef CONFIG_PARAVIRT_DEBUG
-#define PVOP_TEST_NULL(op)      BUG_ON(op == NULL)
-#else
-#define PVOP_TEST_NULL(op)      ((void)op)
-#endif
-#define ____PVOP_CALL(rettype, op, clbr, call_clbr, extra_clbr,         \
-                      pre, post, ...)                                   \
-        ({                                                              \
-                rettype __ret;                                          \
-                PVOP_CALL_ARGS;                                         \
-                PVOP_TEST_NULL(op);                                     \
-                /* This is 32-bit specific, but is okay in 64-bit */    \
-                /* since this condition will never hold */              \
-                if (sizeof(rettype) > sizeof(unsigned long)) {          \
-                        asm volatile(pre                                \
-                                     paravirt_alt(PARAVIRT_CALL)        \
-                                     post                               \
-                                     : call_clbr                        \
-                                     : paravirt_type(op),               \
-                                       paravirt_clobber(clbr),          \
-                                       ##__VA_ARGS__                    \
-                                     : "memory", "cc" extra_clbr);      \
-                        __ret = (rettype)((((u64)__edx) << 32) | __eax); \
-                } else {                                                \
-                        asm volatile(pre                                \
-                                     paravirt_alt(PARAVIRT_CALL)        \
-                                     post                               \
-                                     : call_clbr                        \
-                                     : paravirt_type(op),               \
-                                       paravirt_clobber(clbr),          \
-                                       ##__VA_ARGS__                    \
-                                     : "memory", "cc" extra_clbr);      \
-                        __ret = (rettype)__eax;                         \
-                }                                                       \
-                __ret;                                                  \
-        })
-#define __PVOP_CALL(rettype, op, pre, post, ...)                        \
-        ____PVOP_CALL(rettype, op, CLBR_ANY, PVOP_CALL_CLOBBERS,        \
-                      EXTRA_CLOBBERS, pre, post, ##__VA_ARGS__)
-#define __PVOP_CALLEESAVE(rettype, op, pre, post, ...)                  \
-        ____PVOP_CALL(rettype, op.func, CLBR_RET_REG,                   \
-                      PVOP_CALLEE_CLOBBERS, ,                           \
-                      pre, post, ##__VA_ARGS__)
-#define ____PVOP_VCALL(op, clbr, call_clbr, extra_clbr, pre, post, ...) \
-        ({                                                              \
-                PVOP_VCALL_ARGS;                                        \
-                PVOP_TEST_NULL(op);                                     \
-                asm volatile(pre                                        \
-                             paravirt_alt(PARAVIRT_CALL)                \
-                             post                                       \
-                             : call_clbr                                \
-                             : paravirt_type(op),                       \
-                               paravirt_clobber(clbr),                  \
-                               ##__VA_ARGS__                            \
-                             : "memory", "cc" extra_clbr);              \
-        })
-#define __PVOP_VCALL(op, pre, post, ...)                                \
-        ____PVOP_VCALL(op, CLBR_ANY, PVOP_VCALL_CLOBBERS,               \
-                       VEXTRA_CLOBBERS,                                 \
-                       pre, post, ##__VA_ARGS__)
-#define __PVOP_VCALLEESAVE(rettype, op, pre, post, ...)                 \
-        ____PVOP_CALL(rettype, op.func, CLBR_RET_REG,                   \
-                      PVOP_VCALLEE_CLOBBERS, ,                          \
-                      pre, post, ##__VA_ARGS__)
-#define PVOP_CALL0(rettype, op)                                         \
-        __PVOP_CALL(rettype, op, "", "")
-#define PVOP_VCALL0(op)                                                 \
-        __PVOP_VCALL(op, "", "")
-#define PVOP_CALLEE0(rettype, op)                                       \
-        __PVOP_CALLEESAVE(rettype, op, "", "")
-#define PVOP_VCALLEE0(op)                                               \
-        __PVOP_VCALLEESAVE(op, "", "")
-#define PVOP_CALL1(rettype, op, arg1)                                   \
-        __PVOP_CALL(rettype, op, "", "", PVOP_CALL_ARG1(arg1))
-#define PVOP_VCALL1(op, arg1)                                           \
-        __PVOP_VCALL(op, "", "", PVOP_CALL_ARG1(arg1))
-#define PVOP_CALLEE1(rettype, op, arg1)                                 \
-        __PVOP_CALLEESAVE(rettype, op, "", "", PVOP_CALL_ARG1(arg1))
-#define PVOP_VCALLEE1(op, arg1)                                         \
-        __PVOP_VCALLEESAVE(op, "", "", PVOP_CALL_ARG1(arg1))
-#define PVOP_CALL2(rettype, op, arg1, arg2)                             \
-        __PVOP_CALL(rettype, op, "", "", PVOP_CALL_ARG1(arg1),          \
-                    PVOP_CALL_ARG2(arg2))
-#define PVOP_VCALL2(op, arg1, arg2)                                     \
-        __PVOP_VCALL(op, "", "", PVOP_CALL_ARG1(arg1),                  \
-                     PVOP_CALL_ARG2(arg2))
-#define PVOP_CALLEE2(rettype, op, arg1, arg2)                           \
-        __PVOP_CALLEESAVE(rettype, op, "", "", PVOP_CALL_ARG1(arg1),    \
-                          PVOP_CALL_ARG2(arg2))
-#define PVOP_VCALLEE2(op, arg1, arg2)                                   \
-        __PVOP_VCALLEESAVE(op, "", "", PVOP_CALL_ARG1(arg1),            \
-                           PVOP_CALL_ARG2(arg2))
-#define PVOP_CALL3(rettype, op, arg1, arg2, arg3)                       \
-        __PVOP_CALL(rettype, op, "", "", PVOP_CALL_ARG1(arg1),          \
-                    PVOP_CALL_ARG2(arg2), PVOP_CALL_ARG3(arg3))
-#define PVOP_VCALL3(op, arg1, arg2, arg3)                               \
-        __PVOP_VCALL(op, "", "", PVOP_CALL_ARG1(arg1),                  \
-                     PVOP_CALL_ARG2(arg2), PVOP_CALL_ARG3(arg3))
-/* This is the only difference in x86_64. We can make it much simpler */
-#ifdef CONFIG_X86_32
-#define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4)                 \
-        __PVOP_CALL(rettype, op,                                        \
-                    "push %[_arg4];", "lea 4(%%esp),%%esp;",            \
-                    PVOP_CALL_ARG1(arg1), PVOP_CALL_ARG2(arg2),         \
-                    PVOP_CALL_ARG3(arg3), [_arg4] "mr" ((u32)(arg4)))
-#define PVOP_VCALL4(op, arg1, arg2, arg3, arg4)                         \
-        __PVOP_VCALL(op,                                                \
-                    "push %[_arg4];", "lea 4(%%esp),%%esp;",            \
-                    "0" ((u32)(arg1)), "1" ((u32)(arg2)),               \
-                    "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
-#else
-#define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4)                 \
-        __PVOP_CALL(rettype, op, "", "",                                \
-                    PVOP_CALL_ARG1(arg1), PVOP_CALL_ARG2(arg2),         \
-                    PVOP_CALL_ARG3(arg3), PVOP_CALL_ARG4(arg4))
-#define PVOP_VCALL4(op, arg1, arg2, arg3, arg4)                         \
-        __PVOP_VCALL(op, "", "",                                        \
-                     PVOP_CALL_ARG1(arg1), PVOP_CALL_ARG2(arg2),        \
-                     PVOP_CALL_ARG3(arg3), PVOP_CALL_ARG4(arg4))
-#endif
 static inline int paravirt_enabled(void)
 {
@@ -820,15 +142,22 @@ static inline u64 paravirt_read_msr(unsigned msr, int *err)
 {
        return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
 }
-static inline u64 paravirt_read_msr_amd(unsigned msr, int *err)
+static inline int paravirt_rdmsr_regs(u32 *regs)
 {
-        return PVOP_CALL2(u64, pv_cpu_ops.read_msr_amd, msr, err);
+        return PVOP_CALL1(int, pv_cpu_ops.rdmsr_regs, regs);
 }
 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
 {
        return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
 }
+static inline int paravirt_wrmsr_regs(u32 *regs)
+{
+        return PVOP_CALL1(int, pv_cpu_ops.wrmsr_regs, regs);
+}
 /* These should all do BUG_ON(_err), but our headers are too tangled. */
 #define rdmsr(msr, val1, val2)                  \
 do {                                            \
@@ -862,6 +191,9 @@ do {						\
        _err;                                   \
 })
+#define rdmsr_safe_regs(regs)   paravirt_rdmsr_regs(regs)
+#define wrmsr_safe_regs(regs)   paravirt_wrmsr_regs(regs)
 static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
 {
        int err;
@@ -871,12 +203,31 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
 }
 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
 {
+        u32 gprs[8] = { 0 };
        int err;
-        *p = paravirt_read_msr_amd(msr, &err);
+        gprs[1] = msr;
+        gprs[7] = 0x9c5a203a;
+        err = paravirt_rdmsr_regs(gprs);
+        *p = gprs[0] | ((u64)gprs[2] << 32);
        return err;
 }
+static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
+{
+        u32 gprs[8] = { 0 };
+        gprs[0] = (u32)val;
+        gprs[1] = msr;
+        gprs[2] = val >> 32;
+        gprs[7] = 0x9c5a203a;
+        return paravirt_wrmsr_regs(gprs);
+}
 static inline u64 paravirt_read_tsc(void)
 {
        return PVOP_CALL0(u64, pv_cpu_ops.read_tsc);
@@ -1393,20 +744,6 @@ static inline void pmd_clear(pmd_t *pmdp)
 }
 #endif  /* CONFIG_X86_PAE */
-/* Lazy mode for batching updates / context switch */
-enum paravirt_lazy_mode {
-        PARAVIRT_LAZY_NONE,
-        PARAVIRT_LAZY_MMU,
-        PARAVIRT_LAZY_CPU,
-};
-enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
-void paravirt_start_context_switch(struct task_struct *prev);
-void paravirt_end_context_switch(struct task_struct *next);
-void paravirt_enter_lazy_mmu(void);
-void paravirt_leave_lazy_mmu(void);
 #define  __HAVE_ARCH_START_CONTEXT_SWITCH
 static inline void arch_start_context_switch(struct task_struct *prev)
 {
@@ -1437,12 +774,6 @@ static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
        pv_mmu_ops.set_fixmap(idx, phys, flags);
 }
-void _paravirt_nop(void);
-u32 _paravirt_ident_32(u32);
-u64 _paravirt_ident_64(u64);
-#define paravirt_nop    ((void *)_paravirt_nop)
 #if defined(CONFIG_SMP) && defined(CONFIG_PARAVIRT_SPINLOCKS)
 static inline int __raw_spin_is_locked(struct raw_spinlock *lock)
@@ -1479,17 +810,6 @@ static __always_inline void __raw_spin_unlock(struct raw_spinlock *lock)
 #endif
-/* These all sit in the .parainstructions section to tell us what to patch. */
-struct paravirt_patch_site {
-        u8 *instr;              /* original instructions */
-        u8 instrtype;           /* type of this instruction */
-        u8 len;                 /* length of original instruction */
-        u16 clobbers;           /* what registers you may clobber */
-};
-extern struct paravirt_patch_site __parainstructions[],
-        __parainstructions_end[];
 #ifdef CONFIG_X86_32
 #define PV_SAVE_REGS "pushl %ecx; pushl %edx;"
 #define PV_RESTORE_REGS "popl %edx; popl %ecx;"
diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h
new file mode 100644
index 000000000000..25402d0006e7
--- /dev/null
+++ b/arch/x86/include/asm/paravirt_types.h
@@ -0,0 +1,721 @@
+#ifndef _ASM_X86_PARAVIRT_TYPES_H
+#define _ASM_X86_PARAVIRT_TYPES_H
+/* Bitmask of what can be clobbered: usually at least eax. */
+#define CLBR_NONE 0
+#define CLBR_EAX  (1 << 0)
+#define CLBR_ECX  (1 << 1)
+#define CLBR_EDX  (1 << 2)
+#define CLBR_EDI  (1 << 3)
+#ifdef CONFIG_X86_32
+/* CLBR_ANY should match all regs platform has. For i386, that's just it */
+#define CLBR_ANY  ((1 << 4) - 1)
+#define CLBR_ARG_REGS   (CLBR_EAX | CLBR_EDX | CLBR_ECX)
+#define CLBR_RET_REG    (CLBR_EAX | CLBR_EDX)
+#define CLBR_SCRATCH    (0)
+#else
+#define CLBR_RAX  CLBR_EAX
+#define CLBR_RCX  CLBR_ECX
+#define CLBR_RDX  CLBR_EDX
+#define CLBR_RDI  CLBR_EDI
+#define CLBR_RSI  (1 << 4)
+#define CLBR_R8   (1 << 5)
+#define CLBR_R9   (1 << 6)
+#define CLBR_R10  (1 << 7)
+#define CLBR_R11  (1 << 8)
+#define CLBR_ANY  ((1 << 9) - 1)
+#define CLBR_ARG_REGS   (CLBR_RDI | CLBR_RSI | CLBR_RDX | \
+                         CLBR_RCX | CLBR_R8 | CLBR_R9)
+#define CLBR_RET_REG    (CLBR_RAX)
+#define CLBR_SCRATCH    (CLBR_R10 | CLBR_R11)
+#endif /* X86_64 */
+#define CLBR_CALLEE_SAVE ((CLBR_ARG_REGS | CLBR_SCRATCH) & ~CLBR_RET_REG)
+#ifndef __ASSEMBLY__
+#include <asm/desc_defs.h>
+#include <asm/kmap_types.h>
+struct page;
+struct thread_struct;
+struct desc_ptr;
+struct tss_struct;
+struct mm_struct;
+struct desc_struct;
+struct task_struct;
+struct cpumask;
+/*
+ * Wrapper type for pointers to code which uses the non-standard
+ * calling convention.  See PV_CALL_SAVE_REGS_THUNK below.
+ */
+struct paravirt_callee_save {
+        void *func;
+};
+/* general info */
+struct pv_info {
+        unsigned int kernel_rpl;
+        int shared_kernel_pmd;
+        int paravirt_enabled;
+        const char *name;
+};
+struct pv_init_ops {
+        /*
+         * Patch may replace one of the defined code sequences with
+         * arbitrary code, subject to the same register constraints.
+         * This generally means the code is not free to clobber any
+         * registers other than EAX.  The patch function should return
+         * the number of bytes of code generated, as we nop pad the
+         * rest in generic code.
+         */
+        unsigned (*patch)(u8 type, u16 clobber, void *insnbuf,
+                          unsigned long addr, unsigned len);
+        /* Basic arch-specific setup */
+        void (*arch_setup)(void);
+        char *(*memory_setup)(void);
+        void (*post_allocator_init)(void);
+        /* Print a banner to identify the environment */
+        void (*banner)(void);
+};
+struct pv_lazy_ops {
+        /* Set deferred update mode, used for batching operations. */
+        void (*enter)(void);
+        void (*leave)(void);
+};
+struct pv_time_ops {
+        void (*time_init)(void);
+        /* Set and set time of day */
+        unsigned long (*get_wallclock)(void);
+        int (*set_wallclock)(unsigned long);
+        unsigned long long (*sched_clock)(void);
+        unsigned long (*get_tsc_khz)(void);
+};
+struct pv_cpu_ops {
+        /* hooks for various privileged instructions */
+        unsigned long (*get_debugreg)(int regno);
+        void (*set_debugreg)(int regno, unsigned long value);
+        void (*clts)(void);
+        unsigned long (*read_cr0)(void);
+        void (*write_cr0)(unsigned long);
+        unsigned long (*read_cr4_safe)(void);
+        unsigned long (*read_cr4)(void);
+        void (*write_cr4)(unsigned long);
+#ifdef CONFIG_X86_64
+        unsigned long (*read_cr8)(void);
+        void (*write_cr8)(unsigned long);
+#endif
+        /* Segment descriptor handling */
+        void (*load_tr_desc)(void);
+        void (*load_gdt)(const struct desc_ptr *);
+        void (*load_idt)(const struct desc_ptr *);
+        void (*store_gdt)(struct desc_ptr *);
+        void (*store_idt)(struct desc_ptr *);
+        void (*set_ldt)(const void *desc, unsigned entries);
+        unsigned long (*store_tr)(void);
+        void (*load_tls)(struct thread_struct *t, unsigned int cpu);
+#ifdef CONFIG_X86_64
+        void (*load_gs_index)(unsigned int idx);
+#endif
+        void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
+                                const void *desc);
+        void (*write_gdt_entry)(struct desc_struct *,
+                                int entrynum, const void *desc, int size);
+        void (*write_idt_entry)(gate_desc *,
+                                int entrynum, const gate_desc *gate);
+        void (*alloc_ldt)(struct desc_struct *ldt, unsigned entries);
+        void (*free_ldt)(struct desc_struct *ldt, unsigned entries);
+        void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
+        void (*set_iopl_mask)(unsigned mask);
+        void (*wbinvd)(void);
+        void (*io_delay)(void);
+        /* cpuid emulation, mostly so that caps bits can be disabled */
+        void (*cpuid)(unsigned int *eax, unsigned int *ebx,
+                      unsigned int *ecx, unsigned int *edx);
+        /* MSR, PMC and TSR operations.
+           err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
+        u64 (*read_msr)(unsigned int msr, int *err);
+        int (*rdmsr_regs)(u32 *regs);
+        int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
+        int (*wrmsr_regs)(u32 *regs);
+        u64 (*read_tsc)(void);
+        u64 (*read_pmc)(int counter);
+        unsigned long long (*read_tscp)(unsigned int *aux);
+        /*
+         * Atomically enable interrupts and return to userspace.  This
+         * is only ever used to return to 32-bit processes; in a
+         * 64-bit kernel, it's used for 32-on-64 compat processes, but
+         * never native 64-bit processes.  (Jump, not call.)
+         */
+        void (*irq_enable_sysexit)(void);
+        /*
+         * Switch to usermode gs and return to 64-bit usermode using
+         * sysret.  Only used in 64-bit kernels to return to 64-bit
+         * processes.  Usermode register state, including %rsp, must
+         * already be restored.
+         */
+        void (*usergs_sysret64)(void);
+        /*
+         * Switch to usermode gs and return to 32-bit usermode using
+         * sysret.  Used to return to 32-on-64 compat processes.
+         * Other usermode register state, including %esp, must already
+         * be restored.
+         */
+        void (*usergs_sysret32)(void);
+        /* Normal iret.  Jump to this with the standard iret stack
+           frame set up. */
+        void (*iret)(void);
+        void (*swapgs)(void);
+        void (*start_context_switch)(struct task_struct *prev);
+        void (*end_context_switch)(struct task_struct *next);
+};
+struct pv_irq_ops {
+        void (*init_IRQ)(void);
+        /*
+         * Get/set interrupt state.  save_fl and restore_fl are only
+         * expected to use X86_EFLAGS_IF; all other bits
+         * returned from save_fl are undefined, and may be ignored by
+         * restore_fl.
+         *
+         * NOTE: These functions callers expect the callee to preserve
+         * more registers than the standard C calling convention.
+         */
+        struct paravirt_callee_save save_fl;
+        struct paravirt_callee_save restore_fl;
+        struct paravirt_callee_save irq_disable;
+        struct paravirt_callee_save irq_enable;
+        void (*safe_halt)(void);
+        void (*halt)(void);
+#ifdef CONFIG_X86_64
+        void (*adjust_exception_frame)(void);
+#endif
+};
+struct pv_apic_ops {
+#ifdef CONFIG_X86_LOCAL_APIC
+        void (*setup_boot_clock)(void);
+        void (*setup_secondary_clock)(void);
+        void (*startup_ipi_hook)(int phys_apicid,
+                                 unsigned long start_eip,
+                                 unsigned long start_esp);
+#endif
+};
+struct pv_mmu_ops {
+        /*
+         * Called before/after init_mm pagetable setup. setup_start
+         * may reset %cr3, and may pre-install parts of the pagetable;
+         * pagetable setup is expected to preserve any existing
+         * mapping.
+         */
+        void (*pagetable_setup_start)(pgd_t *pgd_base);
+        void (*pagetable_setup_done)(pgd_t *pgd_base);
+        unsigned long (*read_cr2)(void);
+        void (*write_cr2)(unsigned long);
+        unsigned long (*read_cr3)(void);
+        void (*write_cr3)(unsigned long);
+        /*
+         * Hooks for intercepting the creation/use/destruction of an
+         * mm_struct.
+         */
+        void (*activate_mm)(struct mm_struct *prev,
+                            struct mm_struct *next);
+        void (*dup_mmap)(struct mm_struct *oldmm,
+                         struct mm_struct *mm);
+        void (*exit_mmap)(struct mm_struct *mm);
+        /* TLB operations */
+        void (*flush_tlb_user)(void);
+        void (*flush_tlb_kernel)(void);
+        void (*flush_tlb_single)(unsigned long addr);
+        void (*flush_tlb_others)(const struct cpumask *cpus,
+                                 struct mm_struct *mm,
+                                 unsigned long va);
+        /* Hooks for allocating and freeing a pagetable top-level */
+        int  (*pgd_alloc)(struct mm_struct *mm);
+        void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd);
+        /*
+         * Hooks for allocating/releasing pagetable pages when they're
+         * attached to a pagetable
+         */
+        void (*alloc_pte)(struct mm_struct *mm, unsigned long pfn);
+        void (*alloc_pmd)(struct mm_struct *mm, unsigned long pfn);
+        void (*alloc_pmd_clone)(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count);
+        void (*alloc_pud)(struct mm_struct *mm, unsigned long pfn);
+        void (*release_pte)(unsigned long pfn);
+        void (*release_pmd)(unsigned long pfn);
+        void (*release_pud)(unsigned long pfn);
+        /* Pagetable manipulation functions */
+        void (*set_pte)(pte_t *ptep, pte_t pteval);
+        void (*set_pte_at)(struct mm_struct *mm, unsigned long addr,
+                           pte_t *ptep, pte_t pteval);
+        void (*set_pmd)(pmd_t *pmdp, pmd_t pmdval);
+        void (*pte_update)(struct mm_struct *mm, unsigned long addr,
+                           pte_t *ptep);
+        void (*pte_update_defer)(struct mm_struct *mm,
+                                 unsigned long addr, pte_t *ptep);
+        pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr,
+                                        pte_t *ptep);
+        void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr,
+                                        pte_t *ptep, pte_t pte);
+        struct paravirt_callee_save pte_val;
+        struct paravirt_callee_save make_pte;
+        struct paravirt_callee_save pgd_val;
+        struct paravirt_callee_save make_pgd;
+#if PAGETABLE_LEVELS >= 3
+#ifdef CONFIG_X86_PAE
+        void (*set_pte_atomic)(pte_t *ptep, pte_t pteval);
+        void (*pte_clear)(struct mm_struct *mm, unsigned long addr,
+                          pte_t *ptep);
+        void (*pmd_clear)(pmd_t *pmdp);
+#endif  /* CONFIG_X86_PAE */
+        void (*set_pud)(pud_t *pudp, pud_t pudval);
+        struct paravirt_callee_save pmd_val;
+        struct paravirt_callee_save make_pmd;
+#if PAGETABLE_LEVELS == 4
+        struct paravirt_callee_save pud_val;
+        struct paravirt_callee_save make_pud;
+        void (*set_pgd)(pgd_t *pudp, pgd_t pgdval);
+#endif  /* PAGETABLE_LEVELS == 4 */
+#endif  /* PAGETABLE_LEVELS >= 3 */
+#ifdef CONFIG_HIGHPTE
+        void *(*kmap_atomic_pte)(struct page *page, enum km_type type);
+#endif
+        struct pv_lazy_ops lazy_mode;
+        /* dom0 ops */
+        /* Sometimes the physical address is a pfn, and sometimes its
+           an mfn.  We can tell which is which from the index. */
+        void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx,
+                           phys_addr_t phys, pgprot_t flags);
+};
+struct raw_spinlock;
+struct pv_lock_ops {
+        int (*spin_is_locked)(struct raw_spinlock *lock);
+        int (*spin_is_contended)(struct raw_spinlock *lock);
+        void (*spin_lock)(struct raw_spinlock *lock);
+        void (*spin_lock_flags)(struct raw_spinlock *lock, unsigned long flags);
+        int (*spin_trylock)(struct raw_spinlock *lock);
+        void (*spin_unlock)(struct raw_spinlock *lock);
+};
+/* This contains all the paravirt structures: we get a convenient
+ * number for each function using the offset which we use to indicate
+ * what to patch. */
+struct paravirt_patch_template {
+        struct pv_init_ops pv_init_ops;
+        struct pv_time_ops pv_time_ops;
+        struct pv_cpu_ops pv_cpu_ops;
+        struct pv_irq_ops pv_irq_ops;
+        struct pv_apic_ops pv_apic_ops;
+        struct pv_mmu_ops pv_mmu_ops;
+        struct pv_lock_ops pv_lock_ops;
+};
+extern struct pv_info pv_info;
+extern struct pv_init_ops pv_init_ops;
+extern struct pv_time_ops pv_time_ops;
+extern struct pv_cpu_ops pv_cpu_ops;
+extern struct pv_irq_ops pv_irq_ops;
+extern struct pv_apic_ops pv_apic_ops;
+extern struct pv_mmu_ops pv_mmu_ops;
+extern struct pv_lock_ops pv_lock_ops;
+#define PARAVIRT_PATCH(x)                                       \
+        (offsetof(struct paravirt_patch_template, x) / sizeof(void *))
+#define paravirt_type(op)                               \
+        [paravirt_typenum] "i" (PARAVIRT_PATCH(op)),    \
+        [paravirt_opptr] "i" (&(op))
+#define paravirt_clobber(clobber)               \
+        [paravirt_clobber] "i" (clobber)
+/*
+ * Generate some code, and mark it as patchable by the
+ * apply_paravirt() alternate instruction patcher.
+ */
+#define _paravirt_alt(insn_string, type, clobber)       \
+        "771:\n\t" insn_string "\n" "772:\n"            \
+        ".pushsection .parainstructions,\"a\"\n"        \
+        _ASM_ALIGN "\n"                                 \
+        _ASM_PTR " 771b\n"                              \
+        "  .byte " type "\n"                            \
+        "  .byte 772b-771b\n"                           \
+        "  .short " clobber "\n"                        \
+        ".popsection\n"
+/* Generate patchable code, with the default asm parameters. */
+#define paravirt_alt(insn_string)                                       \
+        _paravirt_alt(insn_string, "%c[paravirt_typenum]", "%c[paravirt_clobber]")
+/* Simple instruction patching code. */
+#define DEF_NATIVE(ops, name, code)                                     \
+        extern const char start_##ops##_##name[], end_##ops##_##name[]; \
+        asm("start_" #ops "_" #name ": " code "; end_" #ops "_" #name ":")
+unsigned paravirt_patch_nop(void);
+unsigned paravirt_patch_ident_32(void *insnbuf, unsigned len);
+unsigned paravirt_patch_ident_64(void *insnbuf, unsigned len);
+unsigned paravirt_patch_ignore(unsigned len);
+unsigned paravirt_patch_call(void *insnbuf,
+                             const void *target, u16 tgt_clobbers,
+                             unsigned long addr, u16 site_clobbers,
+                             unsigned len);
+unsigned paravirt_patch_jmp(void *insnbuf, const void *target,
+                            unsigned long addr, unsigned len);
+unsigned paravirt_patch_default(u8 type, u16 clobbers, void *insnbuf,
+                                unsigned long addr, unsigned len);
+unsigned paravirt_patch_insns(void *insnbuf, unsigned len,
+                              const char *start, const char *end);
+unsigned native_patch(u8 type, u16 clobbers, void *ibuf,
+                      unsigned long addr, unsigned len);
+int paravirt_disable_iospace(void);
+/*
+ * This generates an indirect call based on the operation type number.
+ * The type number, computed in PARAVIRT_PATCH, is derived from the
+ * offset into the paravirt_patch_template structure, and can therefore be
+ * freely converted back into a structure offset.
+ */
+#define PARAVIRT_CALL   "call *%c[paravirt_opptr];"
+/*
+ * These macros are intended to wrap calls through one of the paravirt
+ * ops structs, so that they can be later identified and patched at
+ * runtime.
+ *
+ * Normally, a call to a pv_op function is a simple indirect call:
+ * (pv_op_struct.operations)(args...).
+ *
+ * Unfortunately, this is a relatively slow operation for modern CPUs,
+ * because it cannot necessarily determine what the destination
+ * address is.  In this case, the address is a runtime constant, so at
+ * the very least we can patch the call to e a simple direct call, or
+ * ideally, patch an inline implementation into the callsite.  (Direct
+ * calls are essentially free, because the call and return addresses
+ * are completely predictable.)
+ *
+ * For i386, these macros rely on the standard gcc "regparm(3)" calling
+ * convention, in which the first three arguments are placed in %eax,
+ * %edx, %ecx (in that order), and the remaining arguments are placed
+ * on the stack.  All caller-save registers (eax,edx,ecx) are expected
+ * to be modified (either clobbered or used for return values).
+ * X86_64, on the other hand, already specifies a register-based calling
+ * conventions, returning at %rax, with parameteres going on %rdi, %rsi,
+ * %rdx, and %rcx. Note that for this reason, x86_64 does not need any
+ * special handling for dealing with 4 arguments, unlike i386.
+ * However, x86_64 also have to clobber all caller saved registers, which
+ * unfortunately, are quite a bit (r8 - r11)
+ *
+ * The call instruction itself is marked by placing its start address
+ * and size into the .parainstructions section, so that
+ * apply_paravirt() in arch/i386/kernel/alternative.c can do the
+ * appropriate patching under the control of the backend pv_init_ops
+ * implementation.
+ *
+ * Unfortunately there's no way to get gcc to generate the args setup
+ * for the call, and then allow the call itself to be generated by an
+ * inline asm.  Because of this, we must do the complete arg setup and
+ * return value handling from within these macros.  This is fairly
+ * cumbersome.
+ *
+ * There are 5 sets of PVOP_* macros for dealing with 0-4 arguments.
+ * It could be extended to more arguments, but there would be little
+ * to be gained from that.  For each number of arguments, there are
+ * the two VCALL and CALL variants for void and non-void functions.
+ *
+ * When there is a return value, the invoker of the macro must specify
+ * the return type.  The macro then uses sizeof() on that type to
+ * determine whether its a 32 or 64 bit value, and places the return
+ * in the right register(s) (just %eax for 32-bit, and %edx:%eax for
+ * 64-bit). For x86_64 machines, it just returns at %rax regardless of
+ * the return value size.
+ *
+ * 64-bit arguments are passed as a pair of adjacent 32-bit arguments
+ * i386 also passes 64-bit arguments as a pair of adjacent 32-bit arguments
+ * in low,high order
+ *
+ * Small structures are passed and returned in registers.  The macro
+ * calling convention can't directly deal with this, so the wrapper
+ * functions must do this.
+ *
+ * These PVOP_* macros are only defined within this header.  This
+ * means that all uses must be wrapped in inline functions.  This also
+ * makes sure the incoming and outgoing types are always correct.
+ */
+#ifdef CONFIG_X86_32
+#define PVOP_VCALL_ARGS                         \
+        unsigned long __eax = __eax, __edx = __edx, __ecx = __ecx
+#define PVOP_CALL_ARGS                  PVOP_VCALL_ARGS
+#define PVOP_CALL_ARG1(x)               "a" ((unsigned long)(x))
+#define PVOP_CALL_ARG2(x)               "d" ((unsigned long)(x))
+#define PVOP_CALL_ARG3(x)               "c" ((unsigned long)(x))
+#define PVOP_VCALL_CLOBBERS             "=a" (__eax), "=d" (__edx),     \
+                                        "=c" (__ecx)
+#define PVOP_CALL_CLOBBERS              PVOP_VCALL_CLOBBERS
+#define PVOP_VCALLEE_CLOBBERS           "=a" (__eax), "=d" (__edx)
+#define PVOP_CALLEE_CLOBBERS            PVOP_VCALLEE_CLOBBERS
+#define EXTRA_CLOBBERS
+#define VEXTRA_CLOBBERS
+#else  /* CONFIG_X86_64 */
+#define PVOP_VCALL_ARGS                                 \
+        unsigned long __edi = __edi, __esi = __esi,     \
+                __edx = __edx, __ecx = __ecx
+#define PVOP_CALL_ARGS          PVOP_VCALL_ARGS, __eax
+#define PVOP_CALL_ARG1(x)               "D" ((unsigned long)(x))
+#define PVOP_CALL_ARG2(x)               "S" ((unsigned long)(x))
+#define PVOP_CALL_ARG3(x)               "d" ((unsigned long)(x))
+#define PVOP_CALL_ARG4(x)               "c" ((unsigned long)(x))
+#define PVOP_VCALL_CLOBBERS     "=D" (__edi),                           \
+                                "=S" (__esi), "=d" (__edx),             \
+                                "=c" (__ecx)
+#define PVOP_CALL_CLOBBERS      PVOP_VCALL_CLOBBERS, "=a" (__eax)
+#define PVOP_VCALLEE_CLOBBERS   "=a" (__eax)
+#define PVOP_CALLEE_CLOBBERS    PVOP_VCALLEE_CLOBBERS
+#define EXTRA_CLOBBERS   , "r8", "r9", "r10", "r11"
+#define VEXTRA_CLOBBERS  , "rax", "r8", "r9", "r10", "r11"
+#endif  /* CONFIG_X86_32 */
+#ifdef CONFIG_PARAVIRT_DEBUG
+#define PVOP_TEST_NULL(op)      BUG_ON(op == NULL)
+#else
+#define PVOP_TEST_NULL(op)      ((void)op)
+#endif
+#define ____PVOP_CALL(rettype, op, clbr, call_clbr, extra_clbr,         \
+                      pre, post, ...)                                   \
+        ({                                                              \
+                rettype __ret;                                          \
+                PVOP_CALL_ARGS;                                         \
+                PVOP_TEST_NULL(op);                                     \
+                /* This is 32-bit specific, but is okay in 64-bit */    \
+                /* since this condition will never hold */              \
+                if (sizeof(rettype) > sizeof(unsigned long)) {          \
+                        asm volatile(pre                                \
+                                     paravirt_alt(PARAVIRT_CALL)        \
+                                     post                               \
+                                     : call_clbr                        \
+                                     : paravirt_type(op),               \
+                                       paravirt_clobber(clbr),          \
+                                       ##__VA_ARGS__                    \
+                                     : "memory", "cc" extra_clbr);      \
+                        __ret = (rettype)((((u64)__edx) << 32) | __eax); \
+                } else {                                                \
+                        asm volatile(pre                                \
+                                     paravirt_alt(PARAVIRT_CALL)        \
+                                     post                               \
+                                     : call_clbr                        \
+                                     : paravirt_type(op),               \
+                                       paravirt_clobber(clbr),          \
+                                       ##__VA_ARGS__                    \
+                                     : "memory", "cc" extra_clbr);      \
+                        __ret = (rettype)__eax;                         \
+                }                                                       \
+                __ret;                                                  \
+        })
+#define __PVOP_CALL(rettype, op, pre, post, ...)                        \
+        ____PVOP_CALL(rettype, op, CLBR_ANY, PVOP_CALL_CLOBBERS,        \
+                      EXTRA_CLOBBERS, pre, post, ##__VA_ARGS__)
+#define __PVOP_CALLEESAVE(rettype, op, pre, post, ...)                  \
+        ____PVOP_CALL(rettype, op.func, CLBR_RET_REG,                   \
+                      PVOP_CALLEE_CLOBBERS, ,                           \
+                      pre, post, ##__VA_ARGS__)
+#define ____PVOP_VCALL(op, clbr, call_clbr, extra_clbr, pre, post, ...) \
+        ({                                                              \
+                PVOP_VCALL_ARGS;                                        \
+                PVOP_TEST_NULL(op);                                     \
+                asm volatile(pre                                        \
+                             paravirt_alt(PARAVIRT_CALL)                \
+                             post                                       \
+                             : call_clbr                                \
+                             : paravirt_type(op),                       \
+                               paravirt_clobber(clbr),                  \
+                               ##__VA_ARGS__                            \
+                             : "memory", "cc" extra_clbr);              \
+        })
+#define __PVOP_VCALL(op, pre, post, ...)                                \
+        ____PVOP_VCALL(op, CLBR_ANY, PVOP_VCALL_CLOBBERS,               \
+                       VEXTRA_CLOBBERS,                                 \
+                       pre, post, ##__VA_ARGS__)
+#define __PVOP_VCALLEESAVE(rettype, op, pre, post, ...)                 \
+        ____PVOP_CALL(rettype, op.func, CLBR_RET_REG,                   \
+                      PVOP_VCALLEE_CLOBBERS, ,                          \
+                      pre, post, ##__VA_ARGS__)
+#define PVOP_CALL0(rettype, op)                                         \
+        __PVOP_CALL(rettype, op, "", "")
+#define PVOP_VCALL0(op)                                                 \
+        __PVOP_VCALL(op, "", "")
+#define PVOP_CALLEE0(rettype, op)                                       \
+        __PVOP_CALLEESAVE(rettype, op, "", "")
+#define PVOP_VCALLEE0(op)                                               \
+        __PVOP_VCALLEESAVE(op, "", "")
+#define PVOP_CALL1(rettype, op, arg1)                                   \
+        __PVOP_CALL(rettype, op, "", "", PVOP_CALL_ARG1(arg1))
+#define PVOP_VCALL1(op, arg1)                                           \
+        __PVOP_VCALL(op, "", "", PVOP_CALL_ARG1(arg1))
+#define PVOP_CALLEE1(rettype, op, arg1)                                 \
+        __PVOP_CALLEESAVE(rettype, op, "", "", PVOP_CALL_ARG1(arg1))
+#define PVOP_VCALLEE1(op, arg1)                                         \
+        __PVOP_VCALLEESAVE(op, "", "", PVOP_CALL_ARG1(arg1))
+#define PVOP_CALL2(rettype, op, arg1, arg2)                             \
+        __PVOP_CALL(rettype, op, "", "", PVOP_CALL_ARG1(arg1),          \
+                    PVOP_CALL_ARG2(arg2))
+#define PVOP_VCALL2(op, arg1, arg2)                                     \
+        __PVOP_VCALL(op, "", "", PVOP_CALL_ARG1(arg1),                  \
+                     PVOP_CALL_ARG2(arg2))
+#define PVOP_CALLEE2(rettype, op, arg1, arg2)                           \
+        __PVOP_CALLEESAVE(rettype, op, "", "", PVOP_CALL_ARG1(arg1),    \
+                          PVOP_CALL_ARG2(arg2))
+#define PVOP_VCALLEE2(op, arg1, arg2)                                   \
+        __PVOP_VCALLEESAVE(op, "", "", PVOP_CALL_ARG1(arg1),            \
+                           PVOP_CALL_ARG2(arg2))
+#define PVOP_CALL3(rettype, op, arg1, arg2, arg3)                       \
+        __PVOP_CALL(rettype, op, "", "", PVOP_CALL_ARG1(arg1),          \
+                    PVOP_CALL_ARG2(arg2), PVOP_CALL_ARG3(arg3))
+#define PVOP_VCALL3(op, arg1, arg2, arg3)                               \
+        __PVOP_VCALL(op, "", "", PVOP_CALL_ARG1(arg1),                  \
+                     PVOP_CALL_ARG2(arg2), PVOP_CALL_ARG3(arg3))
+/* This is the only difference in x86_64. We can make it much simpler */
+#ifdef CONFIG_X86_32
+#define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4)                 \
+        __PVOP_CALL(rettype, op,                                        \
+                    "push %[_arg4];", "lea 4(%%esp),%%esp;",            \
+                    PVOP_CALL_ARG1(arg1), PVOP_CALL_ARG2(arg2),         \
+                    PVOP_CALL_ARG3(arg3), [_arg4] "mr" ((u32)(arg4)))
+#define PVOP_VCALL4(op, arg1, arg2, arg3, arg4)                         \
+        __PVOP_VCALL(op,                                                \
+                    "push %[_arg4];", "lea 4(%%esp),%%esp;",            \
+                    "0" ((u32)(arg1)), "1" ((u32)(arg2)),               \
+                    "2" ((u32)(arg3)), [_arg4] "mr" ((u32)(arg4)))
+#else
+#define PVOP_CALL4(rettype, op, arg1, arg2, arg3, arg4)                 \
+        __PVOP_CALL(rettype, op, "", "",                                \
+                    PVOP_CALL_ARG1(arg1), PVOP_CALL_ARG2(arg2),         \
+                    PVOP_CALL_ARG3(arg3), PVOP_CALL_ARG4(arg4))
+#define PVOP_VCALL4(op, arg1, arg2, arg3, arg4)                         \
+        __PVOP_VCALL(op, "", "",                                        \
+                     PVOP_CALL_ARG1(arg1), PVOP_CALL_ARG2(arg2),        \
+                     PVOP_CALL_ARG3(arg3), PVOP_CALL_ARG4(arg4))
+#endif
+/* Lazy mode for batching updates / context switch */
+enum paravirt_lazy_mode {
+        PARAVIRT_LAZY_NONE,
+        PARAVIRT_LAZY_MMU,
+        PARAVIRT_LAZY_CPU,
+};
+enum paravirt_lazy_mode paravirt_get_lazy_mode(void);
+void paravirt_start_context_switch(struct task_struct *prev);
+void paravirt_end_context_switch(struct task_struct *next);
+void paravirt_enter_lazy_mmu(void);
+void paravirt_leave_lazy_mmu(void);
+void _paravirt_nop(void);
+u32 _paravirt_ident_32(u32);
+u64 _paravirt_ident_64(u64);
+#define paravirt_nop    ((void *)_paravirt_nop)
+/* These all sit in the .parainstructions section to tell us what to patch. */
+struct paravirt_patch_site {
+        u8 *instr;              /* original instructions */
+        u8 instrtype;           /* type of this instruction */
+        u8 len;                 /* length of original instruction */
+        u16 clobbers;           /* what registers you may clobber */
+};
+extern struct paravirt_patch_site __parainstructions[],
+        __parainstructions_end[];
+#endif  /* __ASSEMBLY__ */
+#endif  /* _ASM_X86_PARAVIRT_TYPES_H */
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 103f1ddb0d85..04eacefcfd26 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -49,7 +49,7 @@
 #define __percpu_arg(x)         "%%"__stringify(__percpu_seg)":%P" #x
 #define __my_cpu_offset         percpu_read(this_cpu_off)
 #else
-#define __percpu_arg(x)         "%" #x
+#define __percpu_arg(x)         "%P" #x
 #endif
 /*
@@ -104,36 +104,48 @@ do {							\
        }                                               \
 } while (0)
-#define percpu_from_op(op, var)                         \
+#define percpu_from_op(op, var, constraint)             \
 ({                                                      \
        typeof(var) ret__;                              \
        switch (sizeof(var)) {                          \
        case 1:                                         \
                asm(op "b "__percpu_arg(1)",%0"         \
                    : "=q" (ret__)                      \
-                    : "m" (var));                       \
+                    : constraint);                      \
                break;                                  \
        case 2:                                         \
                asm(op "w "__percpu_arg(1)",%0"         \
                    : "=r" (ret__)                      \
-                    : "m" (var));                       \
+                    : constraint);                      \
                break;                                  \
        case 4:                                         \
                asm(op "l "__percpu_arg(1)",%0"         \
                    : "=r" (ret__)                      \
-                    : "m" (var));                       \
+                    : constraint);                      \
                break;                                  \
        case 8:                                         \
                asm(op "q "__percpu_arg(1)",%0"         \
                    : "=r" (ret__)                      \
-                    : "m" (var));                       \
+                    : constraint);                      \
                break;                                  \
        default: __bad_percpu_size();                   \
        }                                               \
        ret__;                                          \
 })
-#define percpu_read(var)        percpu_from_op("mov", per_cpu__##var)
+/*
+ * percpu_read() makes gcc load the percpu variable every time it is
+ * accessed while percpu_read_stable() allows the value to be cached.
+ * percpu_read_stable() is more efficient and can be used if its value
+ * is guaranteed to be valid across cpus.  The current users include
+ * get_current() and get_thread_info() both of which are actually
+ * per-thread variables implemented as per-cpu variables and thus
+ * stable for the duration of the respective task.
+ */
+#define percpu_read(var)        percpu_from_op("mov", per_cpu__##var,   \
+                                               "m" (per_cpu__##var))
+#define percpu_read_stable(var) percpu_from_op("mov", per_cpu__##var,   \
+                                               "p" (&per_cpu__##var))
 #define percpu_write(var, val)  percpu_to_op("mov", per_cpu__##var, val)
 #define percpu_add(var, val)    percpu_to_op("add", per_cpu__##var, val)
 #define percpu_sub(var, val)    percpu_to_op("sub", per_cpu__##var, val)
diff --git a/arch/x86/include/asm/perf_counter.h b/arch/x86/include/asm/perf_counter.h
index fa64e401589d..e7b7c938ae27 100644
--- a/arch/x86/include/asm/perf_counter.h
+++ b/arch/x86/include/asm/perf_counter.h
@@ -84,6 +84,16 @@ union cpuid10_edx {
 #define MSR_ARCH_PERFMON_FIXED_CTR2                     0x30b
 #define X86_PMC_IDX_FIXED_BUS_CYCLES                    (X86_PMC_IDX_FIXED + 2)
+/*
+ * We model BTS tracing as another fixed-mode PMC.
+ *
+ * We choose a value in the middle of the fixed counter range, since lower
+ * values are used by actual fixed counters and higher values are used
+ * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
+ */
+#define X86_PMC_IDX_FIXED_BTS                           (X86_PMC_IDX_FIXED + 16)
 #ifdef CONFIG_PERF_COUNTERS
 extern void init_hw_perf_counters(void);
 extern void perf_counters_lapic_init(void);
diff --git a/arch/x86/include/asm/pgtable.h b/arch/x86/include/asm/pgtable.h
index 16748077559a..4c5b51fdc788 100644
--- a/arch/x86/include/asm/pgtable.h
+++ b/arch/x86/include/asm/pgtable.h
@@ -135,6 +135,11 @@ static inline unsigned long pte_pfn(pte_t pte)
        return (pte_val(pte) & PTE_PFN_MASK) >> PAGE_SHIFT;
 }
+static inline unsigned long pmd_pfn(pmd_t pmd)
+{
+        return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT;
+}
 #define pte_page(pte)   pfn_to_page(pte_pfn(pte))
 static inline int pmd_large(pmd_t pte)
@@ -359,7 +364,7 @@ static inline unsigned long pmd_page_vaddr(pmd_t pmd)
 * this macro returns the index of the entry in the pmd page which would
 * control the given virtual address
 */
-static inline unsigned pmd_index(unsigned long address)
+static inline unsigned long pmd_index(unsigned long address)
 {
        return (address >> PMD_SHIFT) & (PTRS_PER_PMD - 1);
 }
@@ -379,7 +384,7 @@ static inline unsigned pmd_index(unsigned long address)
 * this function returns the index of the entry in the pte page which would
 * control the given virtual address
 */
-static inline unsigned pte_index(unsigned long address)
+static inline unsigned long pte_index(unsigned long address)
 {
        return (address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1);
 }
@@ -430,11 +435,6 @@ static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
        return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(address);
 }
-static inline unsigned long pmd_pfn(pmd_t pmd)
-{
-        return (pmd_val(pmd) & PTE_PFN_MASK) >> PAGE_SHIFT;
-}
 static inline int pud_large(pud_t pud)
 {
        return (pud_val(pud) & (_PAGE_PSE | _PAGE_PRESENT)) ==
@@ -470,7 +470,7 @@ static inline unsigned long pgd_page_vaddr(pgd_t pgd)
 #define pgd_page(pgd)           pfn_to_page(pgd_val(pgd) >> PAGE_SHIFT)
 /* to find an entry in a page-table-directory. */
-static inline unsigned pud_index(unsigned long address)
+static inline unsigned long pud_index(unsigned long address)
 {
        return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
 }
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 2b03f700d3f2..1153037ae9ff 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -404,7 +404,17 @@ extern unsigned long kernel_eflags;
 extern asmlinkage void ignore_sysret(void);
 #else   /* X86_64 */
 #ifdef CONFIG_CC_STACKPROTECTOR
-DECLARE_PER_CPU(unsigned long, stack_canary);
+/*
+ * Make sure stack canary segment base is cached-aligned:
+ *   "For Intel Atom processors, avoid non zero segment base address
+ *    that is not aligned to cache line boundary at all cost."
+ * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
+ */
+struct stack_canary {
+        char __pad[20];         /* canary at %gs:20 */
+        unsigned long canary;
+};
+DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 #endif
 #endif  /* X86_64 */
@@ -703,13 +713,23 @@ static inline void cpu_relax(void)
        rep_nop();
 }
-/* Stop speculative execution: */
+/* Stop speculative execution and prefetching of modified code. */
 static inline void sync_core(void)
 {
        int tmp;
-        asm volatile("cpuid" : "=a" (tmp) : "0" (1)
+#if defined(CONFIG_M386) || defined(CONFIG_M486)
-                     : "ebx", "ecx", "edx", "memory");
+        if (boot_cpu_data.x86 < 5)
+                /* There is no speculative execution.
+                 * jmp is a barrier to prefetching. */
+                asm volatile("jmp 1f\n1:\n" ::: "memory");
+        else
+#endif
+                /* cpuid is a barrier to speculative execution.
+                 * Prefetched instructions are automatically
+                 * invalidated when modified. */
+                asm volatile("cpuid" : "=a" (tmp) : "0" (1)
+                             : "ebx", "ecx", "edx", "memory");
 }
 static inline void __monitor(const void *eax, unsigned long ecx,
diff --git a/arch/x86/include/asm/scatterlist.h b/arch/x86/include/asm/scatterlist.h
index 263d397d2eef..75af592677ec 100644
--- a/arch/x86/include/asm/scatterlist.h
+++ b/arch/x86/include/asm/scatterlist.h
@@ -1,33 +1,8 @@
 #ifndef _ASM_X86_SCATTERLIST_H
 #define _ASM_X86_SCATTERLIST_H
-#include <asm/types.h>
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long   sg_magic;
-#endif
-        unsigned long   page_link;
-        unsigned int    offset;
-        unsigned int    length;
-        dma_addr_t      dma_address;
-        unsigned int    dma_length;
-};
-#define ARCH_HAS_SG_CHAIN
 #define ISA_DMA_THRESHOLD (0x00ffffff)
-/*
+#include <asm-generic/scatterlist.h>
- * These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns.
- */
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#ifdef CONFIG_X86_32
-# define sg_dma_len(sg)         ((sg)->length)
-#else
-# define sg_dma_len(sg)         ((sg)->dma_length)
-#endif
 #endif /* _ASM_X86_SCATTERLIST_H */
diff --git a/arch/x86/include/asm/shmbuf.h b/arch/x86/include/asm/shmbuf.h
index b51413b74971..83c05fc2de38 100644
--- a/arch/x86/include/asm/shmbuf.h
+++ b/arch/x86/include/asm/shmbuf.h
@@ -1,51 +1 @@
-#ifndef _ASM_X86_SHMBUF_H
+#include <asm-generic/shmbuf.h>
-#define _ASM_X86_SHMBUF_H
-/*
- * The shmid64_ds structure for x86 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space on 32 bit is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- *
- * Pad space on 64 bit is left for:
- * - 2 miscellaneous 64-bit values
- */
-struct shmid64_ds {
-        struct ipc64_perm       shm_perm;       /* operation perms */
-        size_t                  shm_segsz;      /* size of segment (bytes) */
-        __kernel_time_t         shm_atime;      /* last attach time */
-#ifdef __i386__
-        unsigned long           __unused1;
-#endif
-        __kernel_time_t         shm_dtime;      /* last detach time */
-#ifdef __i386__
-        unsigned long           __unused2;
-#endif
-        __kernel_time_t         shm_ctime;      /* last change time */
-#ifdef __i386__
-        unsigned long           __unused3;
-#endif
-        __kernel_pid_t          shm_cpid;       /* pid of creator */
-        __kernel_pid_t          shm_lpid;       /* pid of last operator */
-        unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused4;
-        unsigned long           __unused5;
-};
-struct shminfo64 {
-        unsigned long   shmmax;
-        unsigned long   shmmin;
-        unsigned long   shmmni;
-        unsigned long   shmseg;
-        unsigned long   shmall;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-#endif /* _ASM_X86_SHMBUF_H */
diff --git a/arch/x86/include/asm/socket.h b/arch/x86/include/asm/socket.h
index ca8bf2cd0ba9..6b71384b9d8b 100644
--- a/arch/x86/include/asm/socket.h
+++ b/arch/x86/include/asm/socket.h
@@ -1,60 +1 @@
-#ifndef _ASM_X86_SOCKET_H
+#include <asm-generic/socket.h>
-#define _ASM_X86_SOCKET_H
-#include <asm/sockios.h>
-/* For setsockopt(2) */
-#define SOL_SOCKET      1
-#define SO_DEBUG        1
-#define SO_REUSEADDR    2
-#define SO_TYPE         3
-#define SO_ERROR        4
-#define SO_DONTROUTE    5
-#define SO_BROADCAST    6
-#define SO_SNDBUF       7
-#define SO_RCVBUF       8
-#define SO_SNDBUFFORCE  32
-#define SO_RCVBUFFORCE  33
-#define SO_KEEPALIVE    9
-#define SO_OOBINLINE    10
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_LINGER       13
-#define SO_BSDCOMPAT    14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED     16
-#define SO_PEERCRED     17
-#define SO_RCVLOWAT     18
-#define SO_SNDLOWAT     19
-#define SO_RCVTIMEO     20
-#define SO_SNDTIMEO     21
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-#define SO_BINDTODEVICE 25
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-#define SO_ACCEPTCONN           30
-#define SO_PEERSEC              31
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-#define SO_MARK                 36
-#define SO_TIMESTAMPING         37
-#define SCM_TIMESTAMPING        SO_TIMESTAMPING
-#endif /* _ASM_X86_SOCKET_H */
diff --git a/arch/x86/include/asm/sockios.h b/arch/x86/include/asm/sockios.h
index 49cc72b5d3c9..def6d4746ee7 100644
--- a/arch/x86/include/asm/sockios.h
+++ b/arch/x86/include/asm/sockios.h
@@ -1,13 +1 @@
-#ifndef _ASM_X86_SOCKIOS_H
+#include <asm-generic/sockios.h>
-#define _ASM_X86_SOCKIOS_H
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
-#endif /* _ASM_X86_SOCKIOS_H */
diff --git a/arch/x86/include/asm/stackprotector.h b/arch/x86/include/asm/stackprotector.h
index c2d742c6e15f..157517763565 100644
--- a/arch/x86/include/asm/stackprotector.h
+++ b/arch/x86/include/asm/stackprotector.h
@@ -48,7 +48,7 @@
 * head_32 for boot CPU and setup_per_cpu_areas() for others.
 */
 #define GDT_STACK_CANARY_INIT                                           \
-        [GDT_ENTRY_STACK_CANARY] = { { { 0x00000018, 0x00409000 } } },
+        [GDT_ENTRY_STACK_CANARY] = GDT_ENTRY_INIT(0x4090, 0, 0x18),
 /*
 * Initialize the stackprotector canary value.
@@ -78,21 +78,19 @@ static __always_inline void boot_init_stack_canary(void)
 #ifdef CONFIG_X86_64
        percpu_write(irq_stack_union.stack_canary, canary);
 #else
-        percpu_write(stack_canary, canary);
+        percpu_write(stack_canary.canary, canary);
 #endif
 }
 static inline void setup_stack_canary_segment(int cpu)
 {
 #ifdef CONFIG_X86_32
-        unsigned long canary = (unsigned long)&per_cpu(stack_canary, cpu) - 20;
+        unsigned long canary = (unsigned long)&per_cpu(stack_canary, cpu);
        struct desc_struct *gdt_table = get_cpu_gdt_table(cpu);
        struct desc_struct desc;
        desc = gdt_table[GDT_ENTRY_STACK_CANARY];
-        desc.base0 = canary & 0xffff;
+        set_desc_base(&desc, canary);
-        desc.base1 = (canary >> 16) & 0xff;
-        desc.base2 = (canary >> 24) & 0xff;
        write_gdt_entry(gdt_table, GDT_ENTRY_STACK_CANARY, &desc, DESCTYPE_S);
 #endif
 }
diff --git a/arch/x86/include/asm/system.h b/arch/x86/include/asm/system.h
index 643c59b4bc6e..f08f97374892 100644
--- a/arch/x86/include/asm/system.h
+++ b/arch/x86/include/asm/system.h
@@ -31,7 +31,7 @@ void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
        "movl %P[task_canary](%[next]), %%ebx\n\t"                      \
        "movl %%ebx, "__percpu_arg([stack_canary])"\n\t"
 #define __switch_canary_oparam                                          \
-        , [stack_canary] "=m" (per_cpu_var(stack_canary))
+        , [stack_canary] "=m" (per_cpu_var(stack_canary.canary))
 #define __switch_canary_iparam                                          \
        , [task_canary] "i" (offsetof(struct task_struct, stack_canary))
 #else   /* CC_STACKPROTECTOR */
@@ -150,33 +150,6 @@ do {									\
 #endif
 #ifdef __KERNEL__
-#define _set_base(addr, base) do { unsigned long __pr; \
-__asm__ __volatile__ ("movw %%dx,%1\n\t" \
-        "rorl $16,%%edx\n\t" \
-        "movb %%dl,%2\n\t" \
-        "movb %%dh,%3" \
-        :"=&d" (__pr) \
-        :"m" (*((addr)+2)), \
-         "m" (*((addr)+4)), \
-         "m" (*((addr)+7)), \
-         "0" (base) \
-        ); } while (0)
-#define _set_limit(addr, limit) do { unsigned long __lr; \
-__asm__ __volatile__ ("movw %%dx,%1\n\t" \
-        "rorl $16,%%edx\n\t" \
-        "movb %2,%%dh\n\t" \
-        "andb $0xf0,%%dh\n\t" \
-        "orb %%dh,%%dl\n\t" \
-        "movb %%dl,%2" \
-        :"=&d" (__lr) \
-        :"m" (*(addr)), \
-         "m" (*((addr)+6)), \
-         "0" (limit) \
-        ); } while (0)
-#define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
-#define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
 extern void native_load_gs_index(unsigned);
diff --git a/arch/x86/include/asm/termbits.h b/arch/x86/include/asm/termbits.h
index af1b70ea440f..3935b106de79 100644
--- a/arch/x86/include/asm/termbits.h
+++ b/arch/x86/include/asm/termbits.h
@@ -1,198 +1 @@
-#ifndef _ASM_X86_TERMBITS_H
+#include <asm-generic/termbits.h>
-#define _ASM_X86_TERMBITS_H
-#include <linux/posix_types.h>
-typedef unsigned char   cc_t;
-typedef unsigned int    speed_t;
-typedef unsigned int    tcflag_t;
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-};
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IUCLC   0001000
-#define IXON    0002000
-#define IXANY   0004000
-#define IXOFF   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-/* c_oflag bits */
-#define OPOST   0000001
-#define OLCUC   0000002
-#define ONLCR   0000004
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define    BOTHER 0010000               /* non standard rate */
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000  /* input baud rate */
-#define CMSPAR    010000000000  /* mark or space (stick) parity */
-#define CRTSCTS   020000000000  /* flow control */
-#define IBSHIFT   16            /* Shift from CBAUD to CIBAUD */
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-/* tcsetattr uses these */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-#endif /* _ASM_X86_TERMBITS_H */
diff --git a/arch/x86/include/asm/termios.h b/arch/x86/include/asm/termios.h
index c4ee8056baca..280d78a9d966 100644
--- a/arch/x86/include/asm/termios.h
+++ b/arch/x86/include/asm/termios.h
@@ -1,114 +1 @@
-#ifndef _ASM_X86_TERMIOS_H
+#include <asm-generic/termios.h>
-#define _ASM_X86_TERMIOS_H
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-#define NCC 8
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        unsigned char c_line;           /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-#ifdef __KERNEL__
-#include <asm/uaccess.h>
-/*      intr=^C         quit=^\         erase=del       kill=^U
-        eof=^D          vtime=\0        vmin=\1         sxtc=\0
-        start=^Q        stop=^S         susp=^Z         eol=\0
-        reprint=^R      discard=^U      werase=^W       lnext=^V
-        eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-        unsigned short __tmp; \
-        get_user(__tmp,&(termio)->x); \
-        *(unsigned short *) &(termios)->x = __tmp; \
-}
-static inline int user_termio_to_kernel_termios(struct ktermios *termios,
-                                                struct termio __user *termio)
-{
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag);
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag);
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag);
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag);
-        get_user(termios->c_line, &termio->c_line);
-        return copy_from_user(termios->c_cc, termio->c_cc, NCC);
-}
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-static inline int kernel_termios_to_user_termio(struct termio __user *termio,
-                                            struct ktermios *termios)
-{
-        put_user((termios)->c_iflag, &(termio)->c_iflag);
-        put_user((termios)->c_oflag, &(termio)->c_oflag);
-        put_user((termios)->c_cflag, &(termio)->c_cflag);
-        put_user((termios)->c_lflag, &(termio)->c_lflag);
-        put_user((termios)->c_line,  &(termio)->c_line);
-        return copy_to_user((termio)->c_cc, (termios)->c_cc, NCC);
-}
-static inline int user_termios_to_kernel_termios(struct ktermios *k,
-                                                 struct termios2 __user *u)
-{
-        return copy_from_user(k, u, sizeof(struct termios2));
-}
-static inline int kernel_termios_to_user_termios(struct termios2 __user *u,
-                                                 struct ktermios *k)
-{
-        return copy_to_user(u, k, sizeof(struct termios2));
-}
-static inline int user_termios_to_kernel_termios_1(struct ktermios *k,
-                                                   struct termios __user *u)
-{
-        return copy_from_user(k, u, sizeof(struct termios));
-}
-static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
-                                                   struct ktermios *k)
-{
-        return copy_to_user(u, k, sizeof(struct termios));
-}
-#endif  /* __KERNEL__ */
-#endif /* _ASM_X86_TERMIOS_H */
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 6f7786aea4fc..d27d0a2fec4c 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -214,7 +214,7 @@ DECLARE_PER_CPU(unsigned long, kernel_stack);
 static inline struct thread_info *current_thread_info(void)
 {
        struct thread_info *ti;
-        ti = (void *)(percpu_read(kernel_stack) +
+        ti = (void *)(percpu_read_stable(kernel_stack) +
                      KERNEL_STACK_OFFSET - THREAD_SIZE);
        return ti;
 }
diff --git a/arch/x86/include/asm/topology.h b/arch/x86/include/asm/topology.h
index 066ef590d7e0..26d06e052a18 100644
--- a/arch/x86/include/asm/topology.h
+++ b/arch/x86/include/asm/topology.h
@@ -129,25 +129,34 @@ extern unsigned long node_remap_size[];
 #endif
 /* sched_domains SD_NODE_INIT for NUMA machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
+#define SD_NODE_INIT (struct sched_domain) {                            \
-        .min_interval           = 8,                    \
+        .min_interval           = 8,                                    \
-        .max_interval           = 32,                   \
+        .max_interval           = 32,                                   \
-        .busy_factor            = 32,                   \
+        .busy_factor            = 32,                                   \
-        .imbalance_pct          = 125,                  \
+        .imbalance_pct          = 125,                                  \
-        .cache_nice_tries       = SD_CACHE_NICE_TRIES,  \
+        .cache_nice_tries       = SD_CACHE_NICE_TRIES,                  \
-        .busy_idx               = 3,                    \
+        .busy_idx               = 3,                                    \
-        .idle_idx               = SD_IDLE_IDX,          \
+        .idle_idx               = SD_IDLE_IDX,                          \
-        .newidle_idx            = SD_NEWIDLE_IDX,       \
+        .newidle_idx            = SD_NEWIDLE_IDX,                       \
-        .wake_idx               = 1,                    \
+        .wake_idx               = 1,                                    \
-        .forkexec_idx           = SD_FORKEXEC_IDX,      \
+        .forkexec_idx           = SD_FORKEXEC_IDX,                      \
-        .flags                  = SD_LOAD_BALANCE       \
+                                                                        \
-                                | SD_BALANCE_EXEC       \
+        .flags                  = 1*SD_LOAD_BALANCE                     \
-                                | SD_BALANCE_FORK       \
+                                | 1*SD_BALANCE_NEWIDLE                  \
-                                | SD_WAKE_AFFINE        \
+                                | 1*SD_BALANCE_EXEC                     \
-                                | SD_WAKE_BALANCE       \
+                                | 1*SD_BALANCE_FORK                     \
-                                | SD_SERIALIZE,         \
+                                | 0*SD_WAKE_IDLE                        \
-        .last_balance           = jiffies,              \
+                                | 1*SD_WAKE_AFFINE                      \
-        .balance_interval       = 1,                    \
+                                | 1*SD_WAKE_BALANCE                     \
+                                | 0*SD_SHARE_CPUPOWER                   \
+                                | 0*SD_POWERSAVINGS_BALANCE             \
+                                | 0*SD_SHARE_PKG_RESOURCES              \
+                                | 1*SD_SERIALIZE                        \
+                                | 1*SD_WAKE_IDLE_FAR                    \
+                                | 0*SD_PREFER_SIBLING                   \
+                                ,                                       \
+        .last_balance           = jiffies,                              \
+        .balance_interval       = 1,                                    \
 }
 #ifdef CONFIG_X86_64_ACPI_NUMA
diff --git a/arch/x86/include/asm/traps.h b/arch/x86/include/asm/traps.h
index bfd74c032fca..4da91ad69e0d 100644
--- a/arch/x86/include/asm/traps.h
+++ b/arch/x86/include/asm/traps.h
@@ -81,9 +81,7 @@ extern int panic_on_unrecovered_nmi;
 void math_error(void __user *);
 void math_emulate(struct math_emu_info *);
-#ifdef CONFIG_X86_32
+#ifndef CONFIG_X86_32
-unsigned long patch_espfix_desc(unsigned long, unsigned long);
-#else
 asmlinkage void smp_thermal_interrupt(void);
 asmlinkage void mce_threshold_interrupt(void);
 #endif
diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h
index 09b97745772f..df1da20f4534 100644
--- a/arch/x86/include/asm/types.h
+++ b/arch/x86/include/asm/types.h
@@ -1,19 +1,11 @@
 #ifndef _ASM_X86_TYPES_H
 #define _ASM_X86_TYPES_H
-#include <asm-generic/int-ll64.h>
+#define dma_addr_t      dma_addr_t
-#ifndef __ASSEMBLY__
+#include <asm-generic/types.h>
-typedef unsigned short umode_t;
-#endif /* __ASSEMBLY__ */
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 typedef u64 dma64_addr_t;
diff --git a/arch/x86/include/asm/ucontext.h b/arch/x86/include/asm/ucontext.h
index 87324cf439d9..b7c29c8017f2 100644
--- a/arch/x86/include/asm/ucontext.h
+++ b/arch/x86/include/asm/ucontext.h
@@ -7,12 +7,6 @@
                                 * sigcontext struct (uc_mcontext).
                                 */
-struct ucontext {
+#include <asm-generic/ucontext.h>
-        unsigned long     uc_flags;
-        struct ucontext  *uc_link;
-        stack_t           uc_stack;
-        struct sigcontext uc_mcontext;
-        sigset_t          uc_sigmask;   /* mask last for extensibility */
-};
 #endif /* _ASM_X86_UCONTEXT_H */
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 11be5ad2e0e9..272514c2d456 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -55,6 +55,7 @@
 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
+#define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
@@ -351,9 +352,16 @@ enum vmcs_field {
 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
 #define VMX_EPT_EXTENT_CONTEXT                  1
 #define VMX_EPT_EXTENT_GLOBAL                   2
+#define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
+#define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
+#define VMX_EPTP_UC_BIT                         (1ull << 8)
+#define VMX_EPTP_WB_BIT                         (1ull << 14)
+#define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 #define VMX_EPT_DEFAULT_GAW                     3
 #define VMX_EPT_MAX_GAW                         0x4
 #define VMX_EPT_MT_EPTE_SHIFT                   3
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 6b8ca3a0285d..67e929b89875 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -833,106 +833,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
 extern int es7000_plat;
 #endif
-static struct {
-        int gsi_base;
-        int gsi_end;
-} mp_ioapic_routing[MAX_IO_APICS];
-int mp_find_ioapic(int gsi)
-{
-        int i = 0;
-        /* Find the IOAPIC that manages this GSI. */
-        for (i = 0; i < nr_ioapics; i++) {
-                if ((gsi >= mp_ioapic_routing[i].gsi_base)
-                    && (gsi <= mp_ioapic_routing[i].gsi_end))
-                        return i;
-        }
-        printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
-        return -1;
-}
-int mp_find_ioapic_pin(int ioapic, int gsi)
-{
-        if (WARN_ON(ioapic == -1))
-                return -1;
-        if (WARN_ON(gsi > mp_ioapic_routing[ioapic].gsi_end))
-                return -1;
-        return gsi - mp_ioapic_routing[ioapic].gsi_base;
-}
-static u8 __init uniq_ioapic_id(u8 id)
-{
-#ifdef CONFIG_X86_32
-        if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
-            !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
-                return io_apic_get_unique_id(nr_ioapics, id);
-        else
-                return id;
-#else
-        int i;
-        DECLARE_BITMAP(used, 256);
-        bitmap_zero(used, 256);
-        for (i = 0; i < nr_ioapics; i++) {
-                struct mpc_ioapic *ia = &mp_ioapics[i];
-                __set_bit(ia->apicid, used);
-        }
-        if (!test_bit(id, used))
-                return id;
-        return find_first_zero_bit(used, 256);
-#endif
-}
-static int bad_ioapic(unsigned long address)
-{
-        if (nr_ioapics >= MAX_IO_APICS) {
-                printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
-                       "(found %d)\n", MAX_IO_APICS, nr_ioapics);
-                panic("Recompile kernel with bigger MAX_IO_APICS!\n");
-        }
-        if (!address) {
-                printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
-                       " found in table, skipping!\n");
-                return 1;
-        }
-        return 0;
-}
-void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
-{
-        int idx = 0;
-        if (bad_ioapic(address))
-                return;
-        idx = nr_ioapics;
-        mp_ioapics[idx].type = MP_IOAPIC;
-        mp_ioapics[idx].flags = MPC_APIC_USABLE;
-        mp_ioapics[idx].apicaddr = address;
-        set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
-        mp_ioapics[idx].apicid = uniq_ioapic_id(id);
-        mp_ioapics[idx].apicver = io_apic_get_version(idx);
-        /*
-         * Build basic GSI lookup table to facilitate gsi->io_apic lookups
-         * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
-         */
-        mp_ioapic_routing[idx].gsi_base = gsi_base;
-        mp_ioapic_routing[idx].gsi_end = gsi_base +
-            io_apic_get_redir_entries(idx);
-        printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
-               "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
-               mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
-               mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
-        nr_ioapics++;
-}
 int __init acpi_probe_gsi(void)
 {
        int idx;
@@ -947,7 +847,7 @@ int __init acpi_probe_gsi(void)
        max_gsi = 0;
        for (idx = 0; idx < nr_ioapics; idx++) {
-                gsi = mp_ioapic_routing[idx].gsi_end;
+                gsi = mp_gsi_routing[idx].gsi_end;
                if (gsi > max_gsi)
                        max_gsi = gsi;
@@ -1179,9 +1079,8 @@ static int __init acpi_parse_madt_ioapic_entries(void)
         * If MPS is present, it will handle them,
         * otherwise the system will stay in PIC mode
         */
-        if (acpi_disabled || acpi_noirq) {
+        if (acpi_disabled || acpi_noirq)
                return -ENODEV;
-        }
        if (!cpu_has_apic)
                return -ENODEV;
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index f57658702571..de7353c0ce9c 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -2,6 +2,7 @@
 #include <linux/sched.h>
 #include <linux/mutex.h>
 #include <linux/list.h>
+#include <linux/stringify.h>
 #include <linux/kprobes.h>
 #include <linux/mm.h>
 #include <linux/vmalloc.h>
@@ -32,7 +33,7 @@ __setup("smp-alt-boot", bootonly);
 #define smp_alt_once 1
 #endif
-static int debug_alternative;
+static int __initdata_or_module debug_alternative;
 static int __init debug_alt(char *str)
 {
@@ -51,7 +52,7 @@ static int __init setup_noreplace_smp(char *str)
 __setup("noreplace-smp", setup_noreplace_smp);
 #ifdef CONFIG_PARAVIRT
-static int noreplace_paravirt = 0;
+static int __initdata_or_module noreplace_paravirt = 0;
 static int __init setup_noreplace_paravirt(char *str)
 {
@@ -64,16 +65,17 @@ __setup("noreplace-paravirt", setup_noreplace_paravirt);
 #define DPRINTK(fmt, args...) if (debug_alternative) \
        printk(KERN_DEBUG fmt, args)
-#ifdef GENERIC_NOP1
+#if defined(GENERIC_NOP1) && !defined(CONFIG_X86_64)
 /* Use inline assembly to define this because the nops are defined
   as inline assembly strings in the include files and we cannot
   get them easily into strings. */
-asm("\t.section .rodata, \"a\"\nintelnops: "
+asm("\t" __stringify(__INITRODATA_OR_MODULE) "\nintelnops: "
        GENERIC_NOP1 GENERIC_NOP2 GENERIC_NOP3 GENERIC_NOP4 GENERIC_NOP5 GENERIC_NOP6
        GENERIC_NOP7 GENERIC_NOP8
    "\t.previous");
 extern const unsigned char intelnops[];
-static const unsigned char *const intel_nops[ASM_NOP_MAX+1] = {
+static const unsigned char *const __initconst_or_module
+intel_nops[ASM_NOP_MAX+1] = {
        NULL,
        intelnops,
        intelnops + 1,
@@ -87,12 +89,13 @@ static const unsigned char *const intel_nops[ASM_NOP_MAX+1] = {
 #endif
 #ifdef K8_NOP1
-asm("\t.section .rodata, \"a\"\nk8nops: "
+asm("\t" __stringify(__INITRODATA_OR_MODULE) "\nk8nops: "
        K8_NOP1 K8_NOP2 K8_NOP3 K8_NOP4 K8_NOP5 K8_NOP6
        K8_NOP7 K8_NOP8
    "\t.previous");
 extern const unsigned char k8nops[];
-static const unsigned char *const k8_nops[ASM_NOP_MAX+1] = {
+static const unsigned char *const __initconst_or_module
+k8_nops[ASM_NOP_MAX+1] = {
        NULL,
        k8nops,
        k8nops + 1,
@@ -105,13 +108,14 @@ static const unsigned char *const k8_nops[ASM_NOP_MAX+1] = {
 };
 #endif
-#ifdef K7_NOP1
+#if defined(K7_NOP1) && !defined(CONFIG_X86_64)
-asm("\t.section .rodata, \"a\"\nk7nops: "
+asm("\t" __stringify(__INITRODATA_OR_MODULE) "\nk7nops: "
        K7_NOP1 K7_NOP2 K7_NOP3 K7_NOP4 K7_NOP5 K7_NOP6
        K7_NOP7 K7_NOP8
    "\t.previous");
 extern const unsigned char k7nops[];
-static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = {
+static const unsigned char *const __initconst_or_module
+k7_nops[ASM_NOP_MAX+1] = {
        NULL,
        k7nops,
        k7nops + 1,
@@ -125,12 +129,13 @@ static const unsigned char *const k7_nops[ASM_NOP_MAX+1] = {
 #endif
 #ifdef P6_NOP1
-asm("\t.section .rodata, \"a\"\np6nops: "
+asm("\t" __stringify(__INITRODATA_OR_MODULE) "\np6nops: "
        P6_NOP1 P6_NOP2 P6_NOP3 P6_NOP4 P6_NOP5 P6_NOP6
        P6_NOP7 P6_NOP8
    "\t.previous");
 extern const unsigned char p6nops[];
-static const unsigned char *const p6_nops[ASM_NOP_MAX+1] = {
+static const unsigned char *const __initconst_or_module
+p6_nops[ASM_NOP_MAX+1] = {
        NULL,
        p6nops,
        p6nops + 1,
@@ -146,7 +151,7 @@ static const unsigned char *const p6_nops[ASM_NOP_MAX+1] = {
 #ifdef CONFIG_X86_64
 extern char __vsyscall_0;
-const unsigned char *const *find_nop_table(void)
+static const unsigned char *const *__init_or_module find_nop_table(void)
 {
        if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
            boot_cpu_has(X86_FEATURE_NOPL))
@@ -157,7 +162,7 @@ const unsigned char *const *find_nop_table(void)
 #else /* CONFIG_X86_64 */
-const unsigned char *const *find_nop_table(void)
+static const unsigned char *const *__init_or_module find_nop_table(void)
 {
        if (boot_cpu_has(X86_FEATURE_K8))
                return k8_nops;
@@ -172,7 +177,7 @@ const unsigned char *const *find_nop_table(void)
 #endif /* CONFIG_X86_64 */
 /* Use this to add nops to a buffer, then text_poke the whole buffer. */
-void add_nops(void *insns, unsigned int len)
+static void __init_or_module add_nops(void *insns, unsigned int len)
 {
        const unsigned char *const *noptable = find_nop_table();
@@ -185,10 +190,10 @@ void add_nops(void *insns, unsigned int len)
                len -= noplen;
        }
 }
-EXPORT_SYMBOL_GPL(add_nops);
 extern struct alt_instr __alt_instructions[], __alt_instructions_end[];
 extern u8 *__smp_locks[], *__smp_locks_end[];
+static void *text_poke_early(void *addr, const void *opcode, size_t len);
 /* Replace instructions with better alternatives for this CPU type.
   This runs before SMP is initialized to avoid SMP problems with
@@ -196,7 +201,8 @@ extern u8 *__smp_locks[], *__smp_locks_end[];
   APs have less capabilities than the boot processor are not handled.
   Tough. Make sure you disable such features by hand. */
-void apply_alternatives(struct alt_instr *start, struct alt_instr *end)
+void __init_or_module apply_alternatives(struct alt_instr *start,
+                                         struct alt_instr *end)
 {
        struct alt_instr *a;
        char insnbuf[MAX_PATCH_LEN];
@@ -279,9 +285,10 @@ static LIST_HEAD(smp_alt_modules);
 static DEFINE_MUTEX(smp_alt);
 static int smp_mode = 1;        /* protected by smp_alt */
-void alternatives_smp_module_add(struct module *mod, char *name,
+void __init_or_module alternatives_smp_module_add(struct module *mod,
-                                 void *locks, void *locks_end,
+                                                  char *name,
-                                 void *text,  void *text_end)
+                                                  void *locks, void *locks_end,
+                                                  void *text,  void *text_end)
 {
        struct smp_alt_module *smp;
@@ -317,7 +324,7 @@ void alternatives_smp_module_add(struct module *mod, char *name,
        mutex_unlock(&smp_alt);
 }
-void alternatives_smp_module_del(struct module *mod)
+void __init_or_module alternatives_smp_module_del(struct module *mod)
 {
        struct smp_alt_module *item;
@@ -386,8 +393,8 @@ void alternatives_smp_switch(int smp)
 #endif
 #ifdef CONFIG_PARAVIRT
-void apply_paravirt(struct paravirt_patch_site *start,
+void __init_or_module apply_paravirt(struct paravirt_patch_site *start,
-                    struct paravirt_patch_site *end)
+                                     struct paravirt_patch_site *end)
 {
        struct paravirt_patch_site *p;
        char insnbuf[MAX_PATCH_LEN];
@@ -485,13 +492,14 @@ void __init alternative_instructions(void)
 * instructions. And on the local CPU you need to be protected again NMI or MCE
 * handlers seeing an inconsistent instruction while you patch.
 */
-void *text_poke_early(void *addr, const void *opcode, size_t len)
+static void *__init_or_module text_poke_early(void *addr, const void *opcode,
+                                              size_t len)
 {
        unsigned long flags;
        local_irq_save(flags);
        memcpy(addr, opcode, len);
-        local_irq_restore(flags);
        sync_core();
+        local_irq_restore(flags);
        /* Could also do a CLFLUSH here to speed up CPU recovery; but
           that causes hangs on some VIA CPUs. */
        return addr;
diff --git a/arch/x86/kernel/amd_iommu.c b/arch/x86/kernel/amd_iommu.c
index 6c99f5037801..98f230f6a28d 100644
--- a/arch/x86/kernel/amd_iommu.c
+++ b/arch/x86/kernel/amd_iommu.c
@@ -41,9 +41,13 @@ static DEFINE_RWLOCK(amd_iommu_devtable_lock);
 static LIST_HEAD(iommu_pd_list);
 static DEFINE_SPINLOCK(iommu_pd_list_lock);
-#ifdef CONFIG_IOMMU_API
+/*
+ * Domain for untranslated devices - only allocated
+ * if iommu=pt passed on kernel cmd line.
+ */
+static struct protection_domain *pt_domain;
 static struct iommu_ops amd_iommu_ops;
-#endif
 /*
 * general struct to manage commands send to an IOMMU
@@ -55,16 +59,16 @@ struct iommu_cmd {
 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
                             struct unity_map_entry *e);
 static struct dma_ops_domain *find_protection_domain(u16 devid);
-static u64* alloc_pte(struct protection_domain *dom,
+static u64 *alloc_pte(struct protection_domain *domain,
-                      unsigned long address, u64
+                      unsigned long address, int end_lvl,
-                      **pte_page, gfp_t gfp);
+                      u64 **pte_page, gfp_t gfp);
 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
                                      unsigned long start_page,
                                      unsigned int pages);
+static void reset_iommu_command_buffer(struct amd_iommu *iommu);
-#ifndef BUS_NOTIFY_UNBOUND_DRIVER
+static u64 *fetch_pte(struct protection_domain *domain,
-#define BUS_NOTIFY_UNBOUND_DRIVER 0x0005
+                      unsigned long address, int map_size);
-#endif
+static void update_domain(struct protection_domain *domain);
 #ifdef CONFIG_AMD_IOMMU_STATS
@@ -138,7 +142,25 @@ static int iommu_has_npcache(struct amd_iommu *iommu)
 *
 ****************************************************************************/
-static void iommu_print_event(void *__evt)
+static void dump_dte_entry(u16 devid)
+{
+        int i;
+        for (i = 0; i < 8; ++i)
+                pr_err("AMD-Vi: DTE[%d]: %08x\n", i,
+                        amd_iommu_dev_table[devid].data[i]);
+}
+static void dump_command(unsigned long phys_addr)
+{
+        struct iommu_cmd *cmd = phys_to_virt(phys_addr);
+        int i;
+        for (i = 0; i < 4; ++i)
+                pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
+}
+static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
 {
        u32 *event = __evt;
        int type  = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;
@@ -147,7 +169,7 @@ static void iommu_print_event(void *__evt)
        int flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
        u64 address = (u64)(((u64)event[3]) << 32) | event[2];
-        printk(KERN_ERR "AMD IOMMU: Event logged [");
+        printk(KERN_ERR "AMD-Vi: Event logged [");
        switch (type) {
        case EVENT_TYPE_ILL_DEV:
@@ -155,6 +177,7 @@ static void iommu_print_event(void *__evt)
                       "address=0x%016llx flags=0x%04x]\n",
                       PCI_BUS(devid), PCI_SLOT(devid), PCI_FUNC(devid),
                       address, flags);
+                dump_dte_entry(devid);
                break;
        case EVENT_TYPE_IO_FAULT:
                printk("IO_PAGE_FAULT device=%02x:%02x.%x "
@@ -176,6 +199,8 @@ static void iommu_print_event(void *__evt)
                break;
        case EVENT_TYPE_ILL_CMD:
                printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
+                reset_iommu_command_buffer(iommu);
+                dump_command(address);
                break;
        case EVENT_TYPE_CMD_HARD_ERR:
                printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
@@ -209,7 +234,7 @@ static void iommu_poll_events(struct amd_iommu *iommu)
        tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
        while (head != tail) {
-                iommu_print_event(iommu->evt_buf + head);
+                iommu_print_event(iommu, iommu->evt_buf + head);
                head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
        }
@@ -296,8 +321,11 @@ static void __iommu_wait_for_completion(struct amd_iommu *iommu)
        status &= ~MMIO_STATUS_COM_WAIT_INT_MASK;
        writel(status, iommu->mmio_base + MMIO_STATUS_OFFSET);
-        if (unlikely(i == EXIT_LOOP_COUNT))
+        if (unlikely(i == EXIT_LOOP_COUNT)) {
-                panic("AMD IOMMU: Completion wait loop failed\n");
+                spin_unlock(&iommu->lock);
+                reset_iommu_command_buffer(iommu);
+                spin_lock(&iommu->lock);
+        }
 }
 /*
@@ -445,47 +473,78 @@ static void iommu_flush_tlb_pde(struct amd_iommu *iommu, u16 domid)
 }
 /*
+ * This function flushes one domain on one IOMMU
+ */
+static void flush_domain_on_iommu(struct amd_iommu *iommu, u16 domid)
+{
+        struct iommu_cmd cmd;
+        unsigned long flags;
+        __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
+                                      domid, 1, 1);
+        spin_lock_irqsave(&iommu->lock, flags);
+        __iommu_queue_command(iommu, &cmd);
+        __iommu_completion_wait(iommu);
+        __iommu_wait_for_completion(iommu);
+        spin_unlock_irqrestore(&iommu->lock, flags);
+}
+static void flush_all_domains_on_iommu(struct amd_iommu *iommu)
+{
+        int i;
+        for (i = 1; i < MAX_DOMAIN_ID; ++i) {
+                if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
+                        continue;
+                flush_domain_on_iommu(iommu, i);
+        }
+}
+/*
 * This function is used to flush the IO/TLB for a given protection domain
 * on every IOMMU in the system
 */
 static void iommu_flush_domain(u16 domid)
 {
-        unsigned long flags;
        struct amd_iommu *iommu;
-        struct iommu_cmd cmd;
        INC_STATS_COUNTER(domain_flush_all);
-        __iommu_build_inv_iommu_pages(&cmd, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
+        for_each_iommu(iommu)
-                                      domid, 1, 1);
+                flush_domain_on_iommu(iommu, domid);
-        for_each_iommu(iommu) {
-                spin_lock_irqsave(&iommu->lock, flags);
-                __iommu_queue_command(iommu, &cmd);
-                __iommu_completion_wait(iommu);
-                __iommu_wait_for_completion(iommu);
-                spin_unlock_irqrestore(&iommu->lock, flags);
-        }
 }
 void amd_iommu_flush_all_domains(void)
 {
+        struct amd_iommu *iommu;
+        for_each_iommu(iommu)
+                flush_all_domains_on_iommu(iommu);
+}
+static void flush_all_devices_for_iommu(struct amd_iommu *iommu)
+{
        int i;
-        for (i = 1; i < MAX_DOMAIN_ID; ++i) {
+        for (i = 0; i <= amd_iommu_last_bdf; ++i) {
-                if (!test_bit(i, amd_iommu_pd_alloc_bitmap))
+                if (iommu != amd_iommu_rlookup_table[i])
                        continue;
-                iommu_flush_domain(i);
+                iommu_queue_inv_dev_entry(iommu, i);
+                iommu_completion_wait(iommu);
        }
 }
-void amd_iommu_flush_all_devices(void)
+static void flush_devices_by_domain(struct protection_domain *domain)
 {
        struct amd_iommu *iommu;
        int i;
        for (i = 0; i <= amd_iommu_last_bdf; ++i) {
-                if (amd_iommu_pd_table[i] == NULL)
+                if ((domain == NULL && amd_iommu_pd_table[i] == NULL) ||
+                    (amd_iommu_pd_table[i] != domain))
                        continue;
                iommu = amd_iommu_rlookup_table[i];
@@ -497,6 +556,27 @@ void amd_iommu_flush_all_devices(void)
        }
 }
+static void reset_iommu_command_buffer(struct amd_iommu *iommu)
+{
+        pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
+        if (iommu->reset_in_progress)
+                panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
+        iommu->reset_in_progress = true;
+        amd_iommu_reset_cmd_buffer(iommu);
+        flush_all_devices_for_iommu(iommu);
+        flush_all_domains_on_iommu(iommu);
+        iommu->reset_in_progress = false;
+}
+void amd_iommu_flush_all_devices(void)
+{
+        flush_devices_by_domain(NULL);
+}
 /****************************************************************************
 *
 * The functions below are used the create the page table mappings for
@@ -514,18 +594,21 @@ void amd_iommu_flush_all_devices(void)
 static int iommu_map_page(struct protection_domain *dom,
                          unsigned long bus_addr,
                          unsigned long phys_addr,
-                          int prot)
+                          int prot,
+                          int map_size)
 {
        u64 __pte, *pte;
        bus_addr  = PAGE_ALIGN(bus_addr);
        phys_addr = PAGE_ALIGN(phys_addr);
-        /* only support 512GB address spaces for now */
+        BUG_ON(!PM_ALIGNED(map_size, bus_addr));
-        if (bus_addr > IOMMU_MAP_SIZE_L3 || !(prot & IOMMU_PROT_MASK))
+        BUG_ON(!PM_ALIGNED(map_size, phys_addr));
+        if (!(prot & IOMMU_PROT_MASK))
                return -EINVAL;
-        pte = alloc_pte(dom, bus_addr, NULL, GFP_KERNEL);
+        pte = alloc_pte(dom, bus_addr, map_size, NULL, GFP_KERNEL);
        if (IOMMU_PTE_PRESENT(*pte))
                return -EBUSY;
@@ -538,29 +621,18 @@ static int iommu_map_page(struct protection_domain *dom,
        *pte = __pte;
+        update_domain(dom);
        return 0;
 }
 static void iommu_unmap_page(struct protection_domain *dom,
-                             unsigned long bus_addr)
+                             unsigned long bus_addr, int map_size)
 {
-        u64 *pte;
+        u64 *pte = fetch_pte(dom, bus_addr, map_size);
-        pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(bus_addr)];
-        if (!IOMMU_PTE_PRESENT(*pte))
-                return;
-        pte = IOMMU_PTE_PAGE(*pte);
-        pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
-        if (!IOMMU_PTE_PRESENT(*pte))
+        if (pte)
-                return;
+                *pte = 0;
-        pte = IOMMU_PTE_PAGE(*pte);
-        pte = &pte[IOMMU_PTE_L1_INDEX(bus_addr)];
-        *pte = 0;
 }
 /*
@@ -615,7 +687,8 @@ static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
        for (addr = e->address_start; addr < e->address_end;
             addr += PAGE_SIZE) {
-                ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot);
+                ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
+                                     PM_MAP_4k);
                if (ret)
                        return ret;
                /*
@@ -670,24 +743,29 @@ static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
 * This function checks if there is a PTE for a given dma address. If
 * there is one, it returns the pointer to it.
 */
-static u64* fetch_pte(struct protection_domain *domain,
+static u64 *fetch_pte(struct protection_domain *domain,
-                      unsigned long address)
+                      unsigned long address, int map_size)
 {
+        int level;
        u64 *pte;
-        pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(address)];
+        level =  domain->mode - 1;
+        pte   = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
-        if (!IOMMU_PTE_PRESENT(*pte))
+        while (level > map_size) {
-                return NULL;
+                if (!IOMMU_PTE_PRESENT(*pte))
+                        return NULL;
-        pte = IOMMU_PTE_PAGE(*pte);
+                level -= 1;
-        pte = &pte[IOMMU_PTE_L1_INDEX(address)];
-        if (!IOMMU_PTE_PRESENT(*pte))
+                pte = IOMMU_PTE_PAGE(*pte);
-                return NULL;
+                pte = &pte[PM_LEVEL_INDEX(level, address)];
-        pte = IOMMU_PTE_PAGE(*pte);
+                if ((PM_PTE_LEVEL(*pte) == 0) && level != map_size) {
-        pte = &pte[IOMMU_PTE_L0_INDEX(address)];
+                        pte = NULL;
+                        break;
+                }
+        }
        return pte;
 }
@@ -727,7 +805,7 @@ static int alloc_new_range(struct amd_iommu *iommu,
                u64 *pte, *pte_page;
                for (i = 0; i < num_ptes; ++i) {
-                        pte = alloc_pte(&dma_dom->domain, address,
+                        pte = alloc_pte(&dma_dom->domain, address, PM_MAP_4k,
                                        &pte_page, gfp);
                        if (!pte)
                                goto out_free;
@@ -760,16 +838,20 @@ static int alloc_new_range(struct amd_iommu *iommu,
        for (i = dma_dom->aperture[index]->offset;
             i < dma_dom->aperture_size;
             i += PAGE_SIZE) {
-                u64 *pte = fetch_pte(&dma_dom->domain, i);
+                u64 *pte = fetch_pte(&dma_dom->domain, i, PM_MAP_4k);
                if (!pte || !IOMMU_PTE_PRESENT(*pte))
                        continue;
                dma_ops_reserve_addresses(dma_dom, i << PAGE_SHIFT, 1);
        }
+        update_domain(&dma_dom->domain);
        return 0;
 out_free:
+        update_domain(&dma_dom->domain);
        free_page((unsigned long)dma_dom->aperture[index]->bitmap);
        kfree(dma_dom->aperture[index]);
@@ -1009,7 +1091,7 @@ static struct dma_ops_domain *dma_ops_domain_alloc(struct amd_iommu *iommu)
        dma_dom->domain.id = domain_id_alloc();
        if (dma_dom->domain.id == 0)
                goto free_dma_dom;
-        dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
+        dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
        dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
        dma_dom->domain.flags = PD_DMA_OPS_MASK;
        dma_dom->domain.priv = dma_dom;
@@ -1063,6 +1145,41 @@ static struct protection_domain *domain_for_device(u16 devid)
        return dom;
 }
+static void set_dte_entry(u16 devid, struct protection_domain *domain)
+{
+        u64 pte_root = virt_to_phys(domain->pt_root);
+        pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
+                    << DEV_ENTRY_MODE_SHIFT;
+        pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
+        amd_iommu_dev_table[devid].data[2] = domain->id;
+        amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
+        amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
+        amd_iommu_pd_table[devid] = domain;
+}
+/*
+ * If a device is not yet associated with a domain, this function does
+ * assigns it visible for the hardware
+ */
+static void __attach_device(struct amd_iommu *iommu,
+                            struct protection_domain *domain,
+                            u16 devid)
+{
+        /* lock domain */
+        spin_lock(&domain->lock);
+        /* update DTE entry */
+        set_dte_entry(devid, domain);
+        domain->dev_cnt += 1;
+        /* ready */
+        spin_unlock(&domain->lock);
+}
 /*
 * If a device is not yet associated with a domain, this function does
 * assigns it visible for the hardware
@@ -1072,27 +1189,16 @@ static void attach_device(struct amd_iommu *iommu,
                          u16 devid)
 {
        unsigned long flags;
-        u64 pte_root = virt_to_phys(domain->pt_root);
-        domain->dev_cnt += 1;
-        pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
-                    << DEV_ENTRY_MODE_SHIFT;
-        pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
        write_lock_irqsave(&amd_iommu_devtable_lock, flags);
-        amd_iommu_dev_table[devid].data[0] = lower_32_bits(pte_root);
+        __attach_device(iommu, domain, devid);
-        amd_iommu_dev_table[devid].data[1] = upper_32_bits(pte_root);
-        amd_iommu_dev_table[devid].data[2] = domain->id;
-        amd_iommu_pd_table[devid] = domain;
        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
-       /*
+        /*
-        * We might boot into a crash-kernel here. The crashed kernel
+         * We might boot into a crash-kernel here. The crashed kernel
-        * left the caches in the IOMMU dirty. So we have to flush
+         * left the caches in the IOMMU dirty. So we have to flush
-        * here to evict all dirty stuff.
+         * here to evict all dirty stuff.
-        */
+         */
        iommu_queue_inv_dev_entry(iommu, devid);
        iommu_flush_tlb_pde(iommu, domain->id);
 }
@@ -1119,6 +1225,15 @@ static void __detach_device(struct protection_domain *domain, u16 devid)
        /* ready */
        spin_unlock(&domain->lock);
+        /*
+         * If we run in passthrough mode the device must be assigned to the
+         * passthrough domain if it is detached from any other domain
+         */
+        if (iommu_pass_through) {
+                struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
+                __attach_device(iommu, pt_domain, devid);
+        }
 }
 /*
@@ -1164,6 +1279,8 @@ static int device_change_notifier(struct notifier_block *nb,
        case BUS_NOTIFY_UNBOUND_DRIVER:
                if (!domain)
                        goto out;
+                if (iommu_pass_through)
+                        break;
                detach_device(domain, devid);
                break;
        case BUS_NOTIFY_ADD_DEVICE:
@@ -1292,39 +1409,91 @@ static int get_device_resources(struct device *dev,
        return 1;
 }
+static void update_device_table(struct protection_domain *domain)
+{
+        unsigned long flags;
+        int i;
+        for (i = 0; i <= amd_iommu_last_bdf; ++i) {
+                if (amd_iommu_pd_table[i] != domain)
+                        continue;
+                write_lock_irqsave(&amd_iommu_devtable_lock, flags);
+                set_dte_entry(i, domain);
+                write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
+        }
+}
+static void update_domain(struct protection_domain *domain)
+{
+        if (!domain->updated)
+                return;
+        update_device_table(domain);
+        flush_devices_by_domain(domain);
+        iommu_flush_domain(domain->id);
+        domain->updated = false;
+}
 /*
- * If the pte_page is not yet allocated this function is called
+ * This function is used to add another level to an IO page table. Adding
+ * another level increases the size of the address space by 9 bits to a size up
+ * to 64 bits.
 */
-static u64* alloc_pte(struct protection_domain *dom,
+static bool increase_address_space(struct protection_domain *domain,
-                      unsigned long address, u64 **pte_page, gfp_t gfp)
+                                   gfp_t gfp)
+{
+        u64 *pte;
+        if (domain->mode == PAGE_MODE_6_LEVEL)
+                /* address space already 64 bit large */
+                return false;
+        pte = (void *)get_zeroed_page(gfp);
+        if (!pte)
+                return false;
+        *pte             = PM_LEVEL_PDE(domain->mode,
+                                        virt_to_phys(domain->pt_root));
+        domain->pt_root  = pte;
+        domain->mode    += 1;
+        domain->updated  = true;
+        return true;
+}
+static u64 *alloc_pte(struct protection_domain *domain,
+                      unsigned long address,
+                      int end_lvl,
+                      u64 **pte_page,
+                      gfp_t gfp)
 {
        u64 *pte, *page;
+        int level;
-        pte = &dom->pt_root[IOMMU_PTE_L2_INDEX(address)];
+        while (address > PM_LEVEL_SIZE(domain->mode))
+                increase_address_space(domain, gfp);
-        if (!IOMMU_PTE_PRESENT(*pte)) {
+        level =  domain->mode - 1;
-                page = (u64 *)get_zeroed_page(gfp);
+        pte   = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
-                if (!page)
-                        return NULL;
-                *pte = IOMMU_L2_PDE(virt_to_phys(page));
-        }
-        pte = IOMMU_PTE_PAGE(*pte);
+        while (level > end_lvl) {
-        pte = &pte[IOMMU_PTE_L1_INDEX(address)];
+                if (!IOMMU_PTE_PRESENT(*pte)) {
+                        page = (u64 *)get_zeroed_page(gfp);
+                        if (!page)
+                                return NULL;
+                        *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
+                }
-        if (!IOMMU_PTE_PRESENT(*pte)) {
+                level -= 1;
-                page = (u64 *)get_zeroed_page(gfp);
-                if (!page)
-                        return NULL;
-                *pte = IOMMU_L1_PDE(virt_to_phys(page));
-        }
-        pte = IOMMU_PTE_PAGE(*pte);
+                pte = IOMMU_PTE_PAGE(*pte);
-        if (pte_page)
+                if (pte_page && level == end_lvl)
-                *pte_page = pte;
+                        *pte_page = pte;
-        pte = &pte[IOMMU_PTE_L0_INDEX(address)];
+                pte = &pte[PM_LEVEL_INDEX(level, address)];
+        }
        return pte;
 }
@@ -1344,10 +1513,13 @@ static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
        pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
        if (!pte) {
-                pte = alloc_pte(&dom->domain, address, &pte_page, GFP_ATOMIC);
+                pte = alloc_pte(&dom->domain, address, PM_MAP_4k, &pte_page,
+                                GFP_ATOMIC);
                aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
        } else
-                pte += IOMMU_PTE_L0_INDEX(address);
+                pte += PM_LEVEL_INDEX(0, address);
+        update_domain(&dom->domain);
        return pte;
 }
@@ -1409,7 +1581,7 @@ static void dma_ops_domain_unmap(struct amd_iommu *iommu,
        if (!pte)
                return;
-        pte += IOMMU_PTE_L0_INDEX(address);
+        pte += PM_LEVEL_INDEX(0, address);
        WARN_ON(!*pte);
@@ -1988,19 +2160,47 @@ static void cleanup_domain(struct protection_domain *domain)
        write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
 }
-static int amd_iommu_domain_init(struct iommu_domain *dom)
+static void protection_domain_free(struct protection_domain *domain)
+{
+        if (!domain)
+                return;
+        if (domain->id)
+                domain_id_free(domain->id);
+        kfree(domain);
+}
+static struct protection_domain *protection_domain_alloc(void)
 {
        struct protection_domain *domain;
        domain = kzalloc(sizeof(*domain), GFP_KERNEL);
        if (!domain)
-                return -ENOMEM;
+                return NULL;
        spin_lock_init(&domain->lock);
-        domain->mode = PAGE_MODE_3_LEVEL;
        domain->id = domain_id_alloc();
        if (!domain->id)
+                goto out_err;
+        return domain;
+out_err:
+        kfree(domain);
+        return NULL;
+}
+static int amd_iommu_domain_init(struct iommu_domain *dom)
+{
+        struct protection_domain *domain;
+        domain = protection_domain_alloc();
+        if (!domain)
                goto out_free;
+        domain->mode    = PAGE_MODE_3_LEVEL;
        domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
        if (!domain->pt_root)
                goto out_free;
@@ -2010,7 +2210,7 @@ static int amd_iommu_domain_init(struct iommu_domain *dom)
        return 0;
 out_free:
-        kfree(domain);
+        protection_domain_free(domain);
        return -ENOMEM;
 }
@@ -2115,7 +2315,7 @@ static int amd_iommu_map_range(struct iommu_domain *dom,
        paddr &= PAGE_MASK;
        for (i = 0; i < npages; ++i) {
-                ret = iommu_map_page(domain, iova, paddr, prot);
+                ret = iommu_map_page(domain, iova, paddr, prot, PM_MAP_4k);
                if (ret)
                        return ret;
@@ -2136,7 +2336,7 @@ static void amd_iommu_unmap_range(struct iommu_domain *dom,
        iova  &= PAGE_MASK;
        for (i = 0; i < npages; ++i) {
-                iommu_unmap_page(domain, iova);
+                iommu_unmap_page(domain, iova, PM_MAP_4k);
                iova  += PAGE_SIZE;
        }
@@ -2151,21 +2351,9 @@ static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
        phys_addr_t paddr;
        u64 *pte;
-        pte = &domain->pt_root[IOMMU_PTE_L2_INDEX(iova)];
+        pte = fetch_pte(domain, iova, PM_MAP_4k);
-        if (!IOMMU_PTE_PRESENT(*pte))
-                return 0;
-        pte = IOMMU_PTE_PAGE(*pte);
-        pte = &pte[IOMMU_PTE_L1_INDEX(iova)];
-        if (!IOMMU_PTE_PRESENT(*pte))
-                return 0;
-        pte = IOMMU_PTE_PAGE(*pte);
-        pte = &pte[IOMMU_PTE_L0_INDEX(iova)];
-        if (!IOMMU_PTE_PRESENT(*pte))
+        if (!pte || !IOMMU_PTE_PRESENT(*pte))
                return 0;
        paddr  = *pte & IOMMU_PAGE_MASK;
@@ -2191,3 +2379,46 @@ static struct iommu_ops amd_iommu_ops = {
        .domain_has_cap = amd_iommu_domain_has_cap,
 };
+/*****************************************************************************
+ *
+ * The next functions do a basic initialization of IOMMU for pass through
+ * mode
+ *
+ * In passthrough mode the IOMMU is initialized and enabled but not used for
+ * DMA-API translation.
+ *
+ *****************************************************************************/
+int __init amd_iommu_init_passthrough(void)
+{
+        struct pci_dev *dev = NULL;
+        u16 devid, devid2;
+        /* allocate passthroug domain */
+        pt_domain = protection_domain_alloc();
+        if (!pt_domain)
+                return -ENOMEM;
+        pt_domain->mode |= PAGE_MODE_NONE;
+        while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
+                struct amd_iommu *iommu;
+                devid = calc_devid(dev->bus->number, dev->devfn);
+                if (devid > amd_iommu_last_bdf)
+                        continue;
+                devid2 = amd_iommu_alias_table[devid];
+                iommu = amd_iommu_rlookup_table[devid2];
+                if (!iommu)
+                        continue;
+                __attach_device(iommu, pt_domain, devid);
+                __attach_device(iommu, pt_domain, devid2);
+        }
+        pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
+        return 0;
+}
diff --git a/arch/x86/kernel/amd_iommu_init.c b/arch/x86/kernel/amd_iommu_init.c
index c1b17e97252e..b4b61d462dcc 100644
--- a/arch/x86/kernel/amd_iommu_init.c
+++ b/arch/x86/kernel/amd_iommu_init.c
@@ -252,7 +252,7 @@ static void __init iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
 /* Function to enable the hardware */
 static void iommu_enable(struct amd_iommu *iommu)
 {
-        printk(KERN_INFO "AMD IOMMU: Enabling IOMMU at %s cap 0x%hx\n",
+        printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
               dev_name(&iommu->dev->dev), iommu->cap_ptr);
        iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
@@ -435,6 +435,20 @@ static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
 }
 /*
+ * This function resets the command buffer if the IOMMU stopped fetching
+ * commands from it.
+ */
+void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
+{
+        iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
+        writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
+        writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
+        iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
+}
+/*
 * This function writes the command buffer address to the hardware and
 * enables it.
 */
@@ -450,11 +464,7 @@ static void iommu_enable_command_buffer(struct amd_iommu *iommu)
        memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
                    &entry, sizeof(entry));
-        /* set head and tail to zero manually */
+        amd_iommu_reset_cmd_buffer(iommu);
-        writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
-        writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
-        iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
 }
 static void __init free_command_buffer(struct amd_iommu *iommu)
@@ -858,7 +868,7 @@ static int __init init_iommu_all(struct acpi_table_header *table)
                switch (*p) {
                case ACPI_IVHD_TYPE:
-                        DUMP_printk("IOMMU: device: %02x:%02x.%01x cap: %04x "
+                        DUMP_printk("device: %02x:%02x.%01x cap: %04x "
                                    "seg: %d flags: %01x info %04x\n",
                                    PCI_BUS(h->devid), PCI_SLOT(h->devid),
                                    PCI_FUNC(h->devid), h->cap_ptr,
@@ -902,7 +912,7 @@ static int __init iommu_setup_msi(struct amd_iommu *iommu)
        r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
                        IRQF_SAMPLE_RANDOM,
-                        "AMD IOMMU",
+                        "AMD-Vi",
                        NULL);
        if (r) {
@@ -1150,7 +1160,7 @@ int __init amd_iommu_init(void)
        if (no_iommu) {
-                printk(KERN_INFO "AMD IOMMU disabled by kernel command line\n");
+                printk(KERN_INFO "AMD-Vi disabled by kernel command line\n");
                return 0;
        }
@@ -1242,22 +1252,28 @@ int __init amd_iommu_init(void)
        if (ret)
                goto free;
-        ret = amd_iommu_init_dma_ops();
+        if (iommu_pass_through)
+                ret = amd_iommu_init_passthrough();
+        else
+                ret = amd_iommu_init_dma_ops();
        if (ret)
                goto free;
        enable_iommus();
-        printk(KERN_INFO "AMD IOMMU: device isolation ");
+        if (iommu_pass_through)
+                goto out;
+        printk(KERN_INFO "AMD-Vi: device isolation ");
        if (amd_iommu_isolate)
                printk("enabled\n");
        else
                printk("disabled\n");
        if (amd_iommu_unmap_flush)
-                printk(KERN_INFO "AMD IOMMU: IO/TLB flush on unmap enabled\n");
+                printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
        else
-                printk(KERN_INFO "AMD IOMMU: Lazy IO/TLB flushing enabled\n");
+                printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
 out:
        return ret;
diff --git a/arch/x86/kernel/aperture_64.c b/arch/x86/kernel/aperture_64.c
index 676debfc1702..128111d8ffe0 100644
--- a/arch/x86/kernel/aperture_64.c
+++ b/arch/x86/kernel/aperture_64.c
@@ -20,6 +20,7 @@
 #include <linux/bitops.h>
 #include <linux/ioport.h>
 #include <linux/suspend.h>
+#include <linux/kmemleak.h>
 #include <asm/e820.h>
 #include <asm/io.h>
 #include <asm/iommu.h>
@@ -94,6 +95,11 @@ static u32 __init allocate_aperture(void)
         * code for safe
         */
        p = __alloc_bootmem_nopanic(aper_size, aper_size, 512ULL<<20);
+        /*
+         * Kmemleak should not scan this block as it may not be mapped via the
+         * kernel direct mapping.
+         */
+        kmemleak_ignore(p);
        if (!p || __pa(p)+aper_size > 0xffffffff) {
                printk(KERN_ERR
                        "Cannot allocate aperture memory hole (%p,%uK)\n",
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 0a1c2830ec66..159740decc41 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -49,6 +49,7 @@
 #include <asm/mtrr.h>
 #include <asm/smp.h>
 #include <asm/mce.h>
+#include <asm/kvm_para.h>
 unsigned int num_processors;
@@ -1361,52 +1362,80 @@ void enable_x2apic(void)
 }
 #endif /* CONFIG_X86_X2APIC */
-void __init enable_IR_x2apic(void)
+int __init enable_IR(void)
 {
 #ifdef CONFIG_INTR_REMAP
-        int ret;
-        unsigned long flags;
-        struct IO_APIC_route_entry **ioapic_entries = NULL;
-        ret = dmar_table_init();
-        if (ret) {
-                pr_debug("dmar_table_init() failed with %d:\n", ret);
-                goto ir_failed;
-        }
        if (!intr_remapping_supported()) {
                pr_debug("intr-remapping not supported\n");
-                goto ir_failed;
+                return 0;
        }
        if (!x2apic_preenabled && skip_ioapic_setup) {
                pr_info("Skipped enabling intr-remap because of skipping "
                        "io-apic setup\n");
-                return;
+                return 0;
        }
+        if (enable_intr_remapping(x2apic_supported()))
+                return 0;
+        pr_info("Enabled Interrupt-remapping\n");
+        return 1;
+#endif
+        return 0;
+}
+void __init enable_IR_x2apic(void)
+{
+        unsigned long flags;
+        struct IO_APIC_route_entry **ioapic_entries = NULL;
+        int ret, x2apic_enabled = 0;
+        int dmar_table_init_ret = 0;
+#ifdef CONFIG_INTR_REMAP
+        dmar_table_init_ret = dmar_table_init();
+        if (dmar_table_init_ret)
+                pr_debug("dmar_table_init() failed with %d:\n",
+                                dmar_table_init_ret);
+#endif
        ioapic_entries = alloc_ioapic_entries();
        if (!ioapic_entries) {
-                pr_info("Allocate ioapic_entries failed: %d\n", ret);
+                pr_err("Allocate ioapic_entries failed\n");
-                goto end;
+                goto out;
        }
        ret = save_IO_APIC_setup(ioapic_entries);
        if (ret) {
                pr_info("Saving IO-APIC state failed: %d\n", ret);
-                goto end;
+                goto out;
        }
        local_irq_save(flags);
-        mask_IO_APIC_setup(ioapic_entries);
        mask_8259A();
+        mask_IO_APIC_setup(ioapic_entries);
-        ret = enable_intr_remapping(x2apic_supported());
+        if (dmar_table_init_ret)
-        if (ret)
+                ret = 0;
-                goto end_restore;
+        else
+                ret = enable_IR();
-        pr_info("Enabled Interrupt-remapping\n");
+        if (!ret) {
+                /* IR is required if there is APIC ID > 255 even when running
+                 * under KVM
+                 */
+                if (max_physical_apicid > 255 || !kvm_para_available())
+                        goto nox2apic;
+                /*
+                 * without IR all CPUs can be addressed by IOAPIC/MSI
+                 * only in physical mode
+                 */
+                x2apic_force_phys();
+        }
+        x2apic_enabled = 1;
        if (x2apic_supported() && !x2apic_mode) {
                x2apic_mode = 1;
@@ -1414,41 +1443,25 @@ void __init enable_IR_x2apic(void)
                pr_info("Enabled x2apic\n");
        }
-end_restore:
+nox2apic:
-        if (ret)
+        if (!ret) /* IR enabling failed */
-                /*
-                 * IR enabling failed
-                 */
                restore_IO_APIC_setup(ioapic_entries);
        unmask_8259A();
        local_irq_restore(flags);
-end:
+out:
        if (ioapic_entries)
                free_ioapic_entries(ioapic_entries);
-        if (!ret)
+        if (x2apic_enabled)
                return;
-ir_failed:
        if (x2apic_preenabled)
-                panic("x2apic enabled by bios. But IR enabling failed");
+                panic("x2apic: enabled by BIOS but kernel init failed.");
        else if (cpu_has_x2apic)
-                pr_info("Not enabling x2apic,Intr-remapping\n");
+                pr_info("Not enabling x2apic, Intr-remapping init failed.\n");
-#else
-        if (!cpu_has_x2apic)
-                return;
-        if (x2apic_preenabled)
-                panic("x2apic enabled prior OS handover,"
-                      " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP");
-#endif
-        return;
 }
 #ifdef CONFIG_X86_64
 /*
 * Detect and enable local APICs on non-SMP boards.
@@ -1549,8 +1562,6 @@ no_apic:
 #ifdef CONFIG_X86_64
 void __init early_init_lapic_mapping(void)
 {
-        unsigned long phys_addr;
        /*
         * If no local APIC can be found then go out
         * : it means there is no mpatable and MADT
@@ -1558,11 +1569,9 @@ void __init early_init_lapic_mapping(void)
        if (!smp_found_config)
                return;
-        phys_addr = mp_lapic_addr;
+        set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
-        set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
        apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
-                    APIC_BASE, phys_addr);
+                    APIC_BASE, mp_lapic_addr);
        /*
         * Fetch the APIC ID of the BSP in case we have a
@@ -1651,7 +1660,6 @@ int __init APIC_init_uniprocessor(void)
            APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
                pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
                        boot_cpu_physical_apicid);
-                clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
                return -1;
        }
 #endif
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index 8952a5890281..89174f847b49 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -167,7 +167,7 @@ static int es7000_apic_is_cluster(void)
 {
        /* MPENTIUMIII */
        if (boot_cpu_data.x86 == 6 &&
-            (boot_cpu_data.x86_model >= 7 || boot_cpu_data.x86_model <= 11))
+            (boot_cpu_data.x86_model >= 7 && boot_cpu_data.x86_model <= 11))
                return 1;
        return 0;
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index d2ed6c5ddc80..3c8f9e75d038 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -66,6 +66,8 @@
 #include <asm/apic.h>
 #define __apicdebuginit(type) static type __init
+#define for_each_irq_pin(entry, head) \
+        for (entry = head; entry; entry = entry->next)
 /*
 *      Is the SiS APIC rmw bug present ?
@@ -85,6 +87,9 @@ int nr_ioapic_registers[MAX_IO_APICS];
 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
 int nr_ioapics;
+/* IO APIC gsi routing info */
+struct mp_ioapic_gsi  mp_gsi_routing[MAX_IO_APICS];
 /* MP IRQ source entries */
 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
@@ -116,15 +121,6 @@ static int __init parse_noapic(char *str)
 }
 early_param("noapic", parse_noapic);
-struct irq_pin_list;
-/*
- * This is performance-critical, we want to do it O(1)
- *
- * the indexing order of this array favors 1:1 mappings
- * between pins and IRQs.
- */
 struct irq_pin_list {
        int apic, pin;
        struct irq_pin_list *next;
@@ -139,6 +135,11 @@ static struct irq_pin_list *get_one_free_irq_2_pin(int node)
        return pin;
 }
+/*
+ * This is performance-critical, we want to do it O(1)
+ *
+ * Most irqs are mapped 1:1 with pins.
+ */
 struct irq_cfg {
        struct irq_pin_list *irq_2_pin;
        cpumask_var_t domain;
@@ -414,13 +415,10 @@ static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
        unsigned long flags;
        spin_lock_irqsave(&ioapic_lock, flags);
-        entry = cfg->irq_2_pin;
+        for_each_irq_pin(entry, cfg->irq_2_pin) {
-        for (;;) {
                unsigned int reg;
                int pin;
-                if (!entry)
-                        break;
                pin = entry->pin;
                reg = io_apic_read(entry->apic, 0x10 + pin*2);
                /* Is the remote IRR bit set? */
@@ -428,9 +426,6 @@ static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
                        spin_unlock_irqrestore(&ioapic_lock, flags);
                        return true;
                }
-                if (!entry->next)
-                        break;
-                entry = entry->next;
        }
        spin_unlock_irqrestore(&ioapic_lock, flags);
@@ -498,72 +493,68 @@ static void ioapic_mask_entry(int apic, int pin)
 * shared ISA-space IRQs, so we have to support them. We are super
 * fast in the common case, and fast for shared ISA-space IRQs.
 */
-static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
+static int
+add_pin_to_irq_node_nopanic(struct irq_cfg *cfg, int node, int apic, int pin)
 {
-        struct irq_pin_list *entry;
+        struct irq_pin_list **last, *entry;
-        entry = cfg->irq_2_pin;
+        /* don't allow duplicates */
-        if (!entry) {
+        last = &cfg->irq_2_pin;
-                entry = get_one_free_irq_2_pin(node);
+        for_each_irq_pin(entry, cfg->irq_2_pin) {
-                if (!entry) {
-                        printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
-                                        apic, pin);
-                        return;
-                }
-                cfg->irq_2_pin = entry;
-                entry->apic = apic;
-                entry->pin = pin;
-                return;
-        }
-        while (entry->next) {
-                /* not again, please */
                if (entry->apic == apic && entry->pin == pin)
-                        return;
+                        return 0;
+                last = &entry->next;
-                entry = entry->next;
        }
-        entry->next = get_one_free_irq_2_pin(node);
+        entry = get_one_free_irq_2_pin(node);
-        entry = entry->next;
+        if (!entry) {
+                printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
+                                node, apic, pin);
+                return -ENOMEM;
+        }
        entry->apic = apic;
        entry->pin = pin;
+        *last = entry;
+        return 0;
+}
+static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
+{
+        if (add_pin_to_irq_node_nopanic(cfg, node, apic, pin))
+                panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
 }
 /*
 * Reroute an IRQ to a different pin.
 */
 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
-                                      int oldapic, int oldpin,
+                                           int oldapic, int oldpin,
-                                      int newapic, int newpin)
+                                           int newapic, int newpin)
 {
-        struct irq_pin_list *entry = cfg->irq_2_pin;
+        struct irq_pin_list *entry;
-        int replaced = 0;
-        while (entry) {
+        for_each_irq_pin(entry, cfg->irq_2_pin) {
                if (entry->apic == oldapic && entry->pin == oldpin) {
                        entry->apic = newapic;
                        entry->pin = newpin;
-                        replaced = 1;
                        /* every one is different, right? */
-                        break;
+                        return;
                }
-                entry = entry->next;
        }
-        /* why? call replace before add? */
+        /* old apic/pin didn't exist, so just add new ones */
-        if (!replaced)
+        add_pin_to_irq_node(cfg, node, newapic, newpin);
-                add_pin_to_irq_node(cfg, node, newapic, newpin);
 }
-static inline void io_apic_modify_irq(struct irq_cfg *cfg,
+static void io_apic_modify_irq(struct irq_cfg *cfg,
-                                int mask_and, int mask_or,
+                               int mask_and, int mask_or,
-                                void (*final)(struct irq_pin_list *entry))
+                               void (*final)(struct irq_pin_list *entry))
 {
        int pin;
        struct irq_pin_list *entry;
-        for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
+        for_each_irq_pin(entry, cfg->irq_2_pin) {
                unsigned int reg;
                pin = entry->pin;
                reg = io_apic_read(entry->apic, 0x10 + pin * 2);
@@ -580,7 +571,6 @@ static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
        io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 }
-#ifdef CONFIG_X86_64
 static void io_apic_sync(struct irq_pin_list *entry)
 {
        /*
@@ -596,11 +586,6 @@ static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 {
        io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 }
-#else /* CONFIG_X86_32 */
-static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
-{
-        io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
-}
 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 {
@@ -613,7 +598,6 @@ static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
        io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
                        IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 }
-#endif /* CONFIG_X86_32 */
 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 {
@@ -1702,12 +1686,8 @@ __apicdebuginit(void) print_IO_APIC(void)
                if (!entry)
                        continue;
                printk(KERN_DEBUG "IRQ%d ", irq);
-                for (;;) {
+                for_each_irq_pin(entry, cfg->irq_2_pin)
                        printk("-> %d:%d", entry->apic, entry->pin);
-                        if (!entry->next)
-                                break;
-                        entry = entry->next;
-                }
                printk("\n");
        }
@@ -2211,7 +2191,6 @@ static unsigned int startup_ioapic_irq(unsigned int irq)
        return was_pending;
 }
-#ifdef CONFIG_X86_64
 static int ioapic_retrigger_irq(unsigned int irq)
 {
@@ -2224,14 +2203,6 @@ static int ioapic_retrigger_irq(unsigned int irq)
        return 1;
 }
-#else
-static int ioapic_retrigger_irq(unsigned int irq)
-{
-        apic->send_IPI_self(irq_cfg(irq)->vector);
-        return 1;
-}
-#endif
 /*
 * Level and edge triggered IO-APIC interrupts need different handling,
@@ -2269,13 +2240,9 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
        struct irq_pin_list *entry;
        u8 vector = cfg->vector;
-        entry = cfg->irq_2_pin;
+        for_each_irq_pin(entry, cfg->irq_2_pin) {
-        for (;;) {
                unsigned int reg;
-                if (!entry)
-                        break;
                apic = entry->apic;
                pin = entry->pin;
                /*
@@ -2288,9 +2255,6 @@ static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq
                reg &= ~IO_APIC_REDIR_VECTOR_MASK;
                reg |= vector;
                io_apic_modify(apic, 0x10 + pin*2, reg);
-                if (!entry->next)
-                        break;
-                entry = entry->next;
        }
 }
@@ -2515,11 +2479,8 @@ atomic_t irq_mis_count;
 static void ack_apic_level(unsigned int irq)
 {
        struct irq_desc *desc = irq_to_desc(irq);
-#ifdef CONFIG_X86_32
        unsigned long v;
        int i;
-#endif
        struct irq_cfg *cfg;
        int do_unmask_irq = 0;
@@ -2532,31 +2493,28 @@ static void ack_apic_level(unsigned int irq)
        }
 #endif
-#ifdef CONFIG_X86_32
        /*
-        * It appears there is an erratum which affects at least version 0x11
+         * It appears there is an erratum which affects at least version 0x11
-        * of I/O APIC (that's the 82093AA and cores integrated into various
+         * of I/O APIC (that's the 82093AA and cores integrated into various
-        * chipsets).  Under certain conditions a level-triggered interrupt is
+         * chipsets).  Under certain conditions a level-triggered interrupt is
-        * erroneously delivered as edge-triggered one but the respective IRR
+         * erroneously delivered as edge-triggered one but the respective IRR
-        * bit gets set nevertheless.  As a result the I/O unit expects an EOI
+         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
-        * message but it will never arrive and further interrupts are blocked
+         * message but it will never arrive and further interrupts are blocked
-        * from the source.  The exact reason is so far unknown, but the
+         * from the source.  The exact reason is so far unknown, but the
-        * phenomenon was observed when two consecutive interrupt requests
+         * phenomenon was observed when two consecutive interrupt requests
-        * from a given source get delivered to the same CPU and the source is
+         * from a given source get delivered to the same CPU and the source is
-        * temporarily disabled in between.
+         * temporarily disabled in between.
-        *
+         *
-        * A workaround is to simulate an EOI message manually.  We achieve it
+         * A workaround is to simulate an EOI message manually.  We achieve it
-        * by setting the trigger mode to edge and then to level when the edge
+         * by setting the trigger mode to edge and then to level when the edge
-        * trigger mode gets detected in the TMR of a local APIC for a
+         * trigger mode gets detected in the TMR of a local APIC for a
-        * level-triggered interrupt.  We mask the source for the time of the
+         * level-triggered interrupt.  We mask the source for the time of the
-        * operation to prevent an edge-triggered interrupt escaping meanwhile.
+         * operation to prevent an edge-triggered interrupt escaping meanwhile.
-        * The idea is from Manfred Spraul.  --macro
+         * The idea is from Manfred Spraul.  --macro
-        */
+         */
        cfg = desc->chip_data;
        i = cfg->vector;
        v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
-#endif
        /*
         * We must acknowledge the irq before we move it or the acknowledge will
@@ -2598,7 +2556,7 @@ static void ack_apic_level(unsigned int irq)
                unmask_IO_APIC_irq_desc(desc);
        }
-#ifdef CONFIG_X86_32
+        /* Tail end of version 0x11 I/O APIC bug workaround */
        if (!(v & (1 << (i & 0x1f)))) {
                atomic_inc(&irq_mis_count);
                spin_lock(&ioapic_lock);
@@ -2606,26 +2564,15 @@ static void ack_apic_level(unsigned int irq)
                __unmask_and_level_IO_APIC_irq(cfg);
                spin_unlock(&ioapic_lock);
        }
-#endif
 }
 #ifdef CONFIG_INTR_REMAP
 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
 {
-        int apic, pin;
        struct irq_pin_list *entry;
-        entry = cfg->irq_2_pin;
+        for_each_irq_pin(entry, cfg->irq_2_pin)
-        for (;;) {
+                io_apic_eoi(entry->apic, entry->pin);
-                if (!entry)
-                        break;
-                apic = entry->apic;
-                pin = entry->pin;
-                io_apic_eoi(apic, pin);
-                entry = entry->next;
-        }
 }
 static void
@@ -3241,8 +3188,7 @@ void destroy_irq(unsigned int irq)
        cfg = desc->chip_data;
        dynamic_irq_cleanup(irq);
        /* connect back irq_cfg */
-        if (desc)
+        desc->chip_data = cfg;
-                desc->chip_data = cfg;
        free_irte(irq);
        spin_lock_irqsave(&vector_lock, flags);
@@ -3912,7 +3858,11 @@ static int __io_apic_set_pci_routing(struct device *dev, int irq,
         */
        if (irq >= NR_IRQS_LEGACY) {
                cfg = desc->chip_data;
-                add_pin_to_irq_node(cfg, node, ioapic, pin);
+                if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
+                        printk(KERN_INFO "can not add pin %d for irq %d\n",
+                                pin, irq);
+                        return 0;
+                }
        }
        setup_IO_APIC_irq(ioapic, pin, irq, desc, trigger, polarity);
@@ -3941,11 +3891,28 @@ int io_apic_set_pci_routing(struct device *dev, int irq,
        return __io_apic_set_pci_routing(dev, irq, irq_attr);
 }
-/* --------------------------------------------------------------------------
+u8 __init io_apic_unique_id(u8 id)
-                          ACPI-based IOAPIC Configuration
+{
-   -------------------------------------------------------------------------- */
+#ifdef CONFIG_X86_32
+        if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
+            !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
+                return io_apic_get_unique_id(nr_ioapics, id);
+        else
+                return id;
+#else
+        int i;
+        DECLARE_BITMAP(used, 256);
-#ifdef CONFIG_ACPI
+        bitmap_zero(used, 256);
+        for (i = 0; i < nr_ioapics; i++) {
+                struct mpc_ioapic *ia = &mp_ioapics[i];
+                __set_bit(ia->apicid, used);
+        }
+        if (!test_bit(id, used))
+                return id;
+        return find_first_zero_bit(used, 256);
+#endif
+}
 #ifdef CONFIG_X86_32
 int __init io_apic_get_unique_id(int ioapic, int apic_id)
@@ -4054,8 +4021,6 @@ int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
        return 0;
 }
-#endif /* CONFIG_ACPI */
 /*
 * This function currently is only a helper for the i386 smp boot process where
 * we need to reprogram the ioredtbls to cater for the cpus which have come online
@@ -4109,7 +4074,7 @@ void __init setup_ioapic_dest(void)
 static struct resource *ioapic_resources;
-static struct resource * __init ioapic_setup_resources(void)
+static struct resource * __init ioapic_setup_resources(int nr_ioapics)
 {
        unsigned long n;
        struct resource *res;
@@ -4125,15 +4090,13 @@ static struct resource * __init ioapic_setup_resources(void)
        mem = alloc_bootmem(n);
        res = (void *)mem;
-        if (mem != NULL) {
+        mem += sizeof(struct resource) * nr_ioapics;
-                mem += sizeof(struct resource) * nr_ioapics;
-                for (i = 0; i < nr_ioapics; i++) {
+        for (i = 0; i < nr_ioapics; i++) {
-                        res[i].name = mem;
+                res[i].name = mem;
-                        res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
+                res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
-                        sprintf(mem,  "IOAPIC %u", i);
+                sprintf(mem,  "IOAPIC %u", i);
-                        mem += IOAPIC_RESOURCE_NAME_SIZE;
+                mem += IOAPIC_RESOURCE_NAME_SIZE;
-                }
        }
        ioapic_resources = res;
@@ -4147,7 +4110,7 @@ void __init ioapic_init_mappings(void)
        struct resource *ioapic_res;
        int i;
-        ioapic_res = ioapic_setup_resources();
+        ioapic_res = ioapic_setup_resources(nr_ioapics);
        for (i = 0; i < nr_ioapics; i++) {
                if (smp_found_config) {
                        ioapic_phys = mp_ioapics[i].apicaddr;
@@ -4176,11 +4139,9 @@ fake_ioapic_page:
                            __fix_to_virt(idx), ioapic_phys);
                idx++;
-                if (ioapic_res != NULL) {
+                ioapic_res->start = ioapic_phys;
-                        ioapic_res->start = ioapic_phys;
+                ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
-                        ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
+                ioapic_res++;
-                        ioapic_res++;
-                }
        }
 }
@@ -4201,3 +4162,76 @@ void __init ioapic_insert_resources(void)
                r++;
        }
 }
+int mp_find_ioapic(int gsi)
+{
+        int i = 0;
+        /* Find the IOAPIC that manages this GSI. */
+        for (i = 0; i < nr_ioapics; i++) {
+                if ((gsi >= mp_gsi_routing[i].gsi_base)
+                    && (gsi <= mp_gsi_routing[i].gsi_end))
+                        return i;
+        }
+        printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
+        return -1;
+}
+int mp_find_ioapic_pin(int ioapic, int gsi)
+{
+        if (WARN_ON(ioapic == -1))
+                return -1;
+        if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
+                return -1;
+        return gsi - mp_gsi_routing[ioapic].gsi_base;
+}
+static int bad_ioapic(unsigned long address)
+{
+        if (nr_ioapics >= MAX_IO_APICS) {
+                printk(KERN_WARNING "WARING: Max # of I/O APICs (%d) exceeded "
+                       "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
+                return 1;
+        }
+        if (!address) {
+                printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
+                       " found in table, skipping!\n");
+                return 1;
+        }
+        return 0;
+}
+void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
+{
+        int idx = 0;
+        if (bad_ioapic(address))
+                return;
+        idx = nr_ioapics;
+        mp_ioapics[idx].type = MP_IOAPIC;
+        mp_ioapics[idx].flags = MPC_APIC_USABLE;
+        mp_ioapics[idx].apicaddr = address;
+        set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
+        mp_ioapics[idx].apicid = io_apic_unique_id(id);
+        mp_ioapics[idx].apicver = io_apic_get_version(idx);
+        /*
+         * Build basic GSI lookup table to facilitate gsi->io_apic lookups
+         * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
+         */
+        mp_gsi_routing[idx].gsi_base = gsi_base;
+        mp_gsi_routing[idx].gsi_end = gsi_base +
+            io_apic_get_redir_entries(idx);
+        printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
+               "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
+               mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
+               mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
+        nr_ioapics++;
+}
diff --git a/arch/x86/kernel/apic/ipi.c b/arch/x86/kernel/apic/ipi.c
index 6ef00ba4c886..08385e090a6f 100644
--- a/arch/x86/kernel/apic/ipi.c
+++ b/arch/x86/kernel/apic/ipi.c
@@ -153,7 +153,7 @@ int safe_smp_processor_id(void)
 {
        int apicid, cpuid;
-        if (!boot_cpu_has(X86_FEATURE_APIC))
+        if (!cpu_has_apic)
                return 0;
        apicid = hard_smp_processor_id();
diff --git a/arch/x86/kernel/apic/nmi.c b/arch/x86/kernel/apic/nmi.c
index b3025b43b63a..db7220220d09 100644
--- a/arch/x86/kernel/apic/nmi.c
+++ b/arch/x86/kernel/apic/nmi.c
@@ -39,7 +39,7 @@
 int unknown_nmi_panic;
 int nmi_watchdog_enabled;
-static cpumask_var_t backtrace_mask;
+static cpumask_t backtrace_mask __read_mostly;
 /* nmi_active:
 * >0: the lapic NMI watchdog is active, but can be disabled
@@ -138,7 +138,6 @@ int __init check_nmi_watchdog(void)
        if (!prev_nmi_count)
                goto error;
-        alloc_cpumask_var(&backtrace_mask, GFP_KERNEL|__GFP_ZERO);
        printk(KERN_INFO "Testing NMI watchdog ... ");
 #ifdef CONFIG_SMP
@@ -415,14 +414,17 @@ nmi_watchdog_tick(struct pt_regs *regs, unsigned reason)
        }
        /* We can be called before check_nmi_watchdog, hence NULL check. */
-        if (backtrace_mask != NULL && cpumask_test_cpu(cpu, backtrace_mask)) {
+        if (cpumask_test_cpu(cpu, &backtrace_mask)) {
                static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
                spin_lock(&lock);
                printk(KERN_WARNING "NMI backtrace for cpu %d\n", cpu);
+                show_regs(regs);
                dump_stack();
                spin_unlock(&lock);
-                cpumask_clear_cpu(cpu, backtrace_mask);
+                cpumask_clear_cpu(cpu, &backtrace_mask);
+                rc = 1;
        }
        /* Could check oops_in_progress here too, but it's safer not to */
@@ -552,14 +554,18 @@ int do_nmi_callback(struct pt_regs *regs, int cpu)
        return 0;
 }
-void __trigger_all_cpu_backtrace(void)
+void arch_trigger_all_cpu_backtrace(void)
 {
        int i;
-        cpumask_copy(backtrace_mask, cpu_online_mask);
+        cpumask_copy(&backtrace_mask, cpu_online_mask);
+        printk(KERN_INFO "sending NMI to all CPUs:\n");
+        apic->send_IPI_all(NMI_VECTOR);
        /* Wait for up to 10 seconds for all CPUs to do the backtrace */
        for (i = 0; i < 10 * 1000; i++) {
-                if (cpumask_empty(backtrace_mask))
+                if (cpumask_empty(&backtrace_mask))
                        break;
                mdelay(1);
        }
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index fcec2f1d34a1..65edc180fc82 100644
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -55,11 +55,11 @@ static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
 void __init default_setup_apic_routing(void)
 {
 #ifdef CONFIG_X86_X2APIC
-        if (x2apic_mode && (apic != &apic_x2apic_phys &&
+        if (x2apic_mode
 #ifdef CONFIG_X86_UV
-                       apic != &apic_x2apic_uv_x &&
+                       && apic != &apic_x2apic_uv_x
 #endif
-                       apic != &apic_x2apic_cluster)) {
+                       ) {
                if (x2apic_phys)
                        apic = &apic_x2apic_phys;
                else
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 442b5508893f..151ace69a5aa 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -403,7 +403,15 @@ static DECLARE_WAIT_QUEUE_HEAD(apm_waitqueue);
 static DECLARE_WAIT_QUEUE_HEAD(apm_suspend_waitqueue);
 static struct apm_user *user_list;
 static DEFINE_SPINLOCK(user_list_lock);
-static const struct desc_struct bad_bios_desc = { { { 0, 0x00409200 } } };
+/*
+ * Set up a segment that references the real mode segment 0x40
+ * that extends up to the end of page zero (that we have reserved).
+ * This is for buggy BIOS's that refer to (real mode) segment 0x40
+ * even though they are called in protected mode.
+ */
+static struct desc_struct bad_bios_desc = GDT_ENTRY_INIT(0x4092,
+                        (unsigned long)__va(0x400UL), PAGE_SIZE - 0x400 - 1);
 static const char driver_version[] = "1.16ac";  /* no spaces */
@@ -2332,15 +2340,6 @@ static int __init apm_init(void)
        pm_flags |= PM_APM;
        /*
-         * Set up a segment that references the real mode segment 0x40
-         * that extends up to the end of page zero (that we have reserved).
-         * This is for buggy BIOS's that refer to (real mode) segment 0x40
-         * even though they are called in protected mode.
-         */
-        set_base(bad_bios_desc, __va((unsigned long)0x40 << 4));
-        _set_limit((char *)&bad_bios_desc, 4095 - (0x40 << 4));
-        /*
         * Set up the long jump entry point to the APM BIOS, which is called
         * from inline assembly.
         */
@@ -2358,12 +2357,12 @@ static int __init apm_init(void)
         * code to that CPU.
         */
        gdt = get_cpu_gdt_table(0);
-        set_base(gdt[APM_CS >> 3],
+        set_desc_base(&gdt[APM_CS >> 3],
-                 __va((unsigned long)apm_info.bios.cseg << 4));
+                 (unsigned long)__va((unsigned long)apm_info.bios.cseg << 4));
-        set_base(gdt[APM_CS_16 >> 3],
+        set_desc_base(&gdt[APM_CS_16 >> 3],
-                 __va((unsigned long)apm_info.bios.cseg_16 << 4));
+                 (unsigned long)__va((unsigned long)apm_info.bios.cseg_16 << 4));
-        set_base(gdt[APM_DS >> 3],
+        set_desc_base(&gdt[APM_DS >> 3],
-                 __va((unsigned long)apm_info.bios.dseg << 4));
+                 (unsigned long)__va((unsigned long)apm_info.bios.dseg << 4));
        proc_create("apm", 0, NULL, &apm_file_ops);
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 63fddcd082cd..22a47c82f3c0 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -2,7 +2,7 @@
 #include <linux/bitops.h>
 #include <linux/mm.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/processor.h>
 #include <asm/apic.h>
 #include <asm/cpu.h>
@@ -45,8 +45,8 @@ static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
 #define CBAR_ENB        (0x80000000)
 #define CBAR_KEY        (0X000000CB)
        if (c->x86_model == 9 || c->x86_model == 10) {
-                if (inl (CBAR) & CBAR_ENB)
+                if (inl(CBAR) & CBAR_ENB)
-                        outl (0 | CBAR_KEY, CBAR);
+                        outl(0 | CBAR_KEY, CBAR);
        }
 }
@@ -87,9 +87,10 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
                d = d2-d;
                if (d > 20*K6_BUG_LOOP)
-                        printk("system stability may be impaired when more than 32 MB are used.\n");
+                        printk(KERN_CONT
+                                "system stability may be impaired when more than 32 MB are used.\n");
                else
-                        printk("probably OK (after B9730xxxx).\n");
+                        printk(KERN_CONT "probably OK (after B9730xxxx).\n");
                printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
        }
@@ -219,8 +220,9 @@ static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
        if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
                rdmsr(MSR_K7_CLK_CTL, l, h);
                if ((l & 0xfff00000) != 0x20000000) {
-                        printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l,
+                        printk(KERN_INFO
-                                ((l & 0x000fffff)|0x20000000));
+                            "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
+                                        l, ((l & 0x000fffff)|0x20000000));
                        wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
                }
        }
@@ -251,6 +253,64 @@ static int __cpuinit nearby_node(int apicid)
 #endif
 /*
+ * Fixup core topology information for AMD multi-node processors.
+ * Assumption 1: Number of cores in each internal node is the same.
+ * Assumption 2: Mixed systems with both single-node and dual-node
+ *               processors are not supported.
+ */
+#ifdef CONFIG_X86_HT
+static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
+{
+#ifdef CONFIG_PCI
+        u32 t, cpn;
+        u8 n, n_id;
+        int cpu = smp_processor_id();
+        /* fixup topology information only once for a core */
+        if (cpu_has(c, X86_FEATURE_AMD_DCM))
+                return;
+        /* check for multi-node processor on boot cpu */
+        t = read_pci_config(0, 24, 3, 0xe8);
+        if (!(t & (1 << 29)))
+                return;
+        set_cpu_cap(c, X86_FEATURE_AMD_DCM);
+        /* cores per node: each internal node has half the number of cores */
+        cpn = c->x86_max_cores >> 1;
+        /* even-numbered NB_id of this dual-node processor */
+        n = c->phys_proc_id << 1;
+        /*
+         * determine internal node id and assign cores fifty-fifty to
+         * each node of the dual-node processor
+         */
+        t = read_pci_config(0, 24 + n, 3, 0xe8);
+        n = (t>>30) & 0x3;
+        if (n == 0) {
+                if (c->cpu_core_id < cpn)
+                        n_id = 0;
+                else
+                        n_id = 1;
+        } else {
+                if (c->cpu_core_id < cpn)
+                        n_id = 1;
+                else
+                        n_id = 0;
+        }
+        /* compute entire NodeID, use llc_shared_map to store sibling info */
+        per_cpu(cpu_llc_id, cpu) = (c->phys_proc_id << 1) + n_id;
+        /* fixup core id to be in range from 0 to cpn */
+        c->cpu_core_id = c->cpu_core_id % cpn;
+#endif
+}
+#endif
+/*
 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 * Assumes number of cores is a power of two.
 */
@@ -267,6 +327,9 @@ static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
        c->phys_proc_id = c->initial_apicid >> bits;
        /* use socket ID also for last level cache */
        per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
+        /* fixup topology information on multi-node processors */
+        if ((c->x86 == 0x10) && (c->x86_model == 9))
+                amd_fixup_dcm(c);
 #endif
 }
@@ -275,9 +338,10 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
        int cpu = smp_processor_id();
        int node;
-        unsigned apicid = cpu_has_apic ? hard_smp_processor_id() : c->apicid;
+        unsigned apicid = c->apicid;
+        node = per_cpu(cpu_llc_id, cpu);
-        node = c->phys_proc_id;
        if (apicid_to_node[apicid] != NUMA_NO_NODE)
                node = apicid_to_node[apicid];
        if (!node_online(node)) {
@@ -398,18 +462,30 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                u32 level;
                level = cpuid_eax(1);
-                if((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
+                if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
                        set_cpu_cap(c, X86_FEATURE_REP_GOOD);
                /*
                 * Some BIOSes incorrectly force this feature, but only K8
                 * revision D (model = 0x14) and later actually support it.
+                 * (AMD Erratum #110, docId: 25759).
                 */
-                if (c->x86_model < 0x14)
+                if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
+                        u64 val;
                        clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
+                        if (!rdmsrl_amd_safe(0xc001100d, &val)) {
+                                val &= ~(1ULL << 32);
+                                wrmsrl_amd_safe(0xc001100d, val);
+                        }
+                }
        }
        if (c->x86 == 0x10 || c->x86 == 0x11)
                set_cpu_cap(c, X86_FEATURE_REP_GOOD);
+        /* get apicid instead of initial apic id from cpuid */
+        c->apicid = hard_smp_processor_id();
 #else
        /*
@@ -494,27 +570,30 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
                 * benefit in doing so.
                 */
                if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
-                    printk(KERN_DEBUG "tseg: %010llx\n", tseg);
+                        printk(KERN_DEBUG "tseg: %010llx\n", tseg);
-                    if ((tseg>>PMD_SHIFT) <
+                        if ((tseg>>PMD_SHIFT) <
                                (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
-                        ((tseg>>PMD_SHIFT) <
+                                ((tseg>>PMD_SHIFT) <
                                (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
-                         (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
+                                (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
-                        set_memory_4k((unsigned long)__va(tseg), 1);
+                                set_memory_4k((unsigned long)__va(tseg), 1);
                }
        }
 #endif
 }
 #ifdef CONFIG_X86_32
-static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
+static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
+                                                        unsigned int size)
 {
        /* AMD errata T13 (order #21922) */
        if ((c->x86 == 6)) {
-                if (c->x86_model == 3 && c->x86_mask == 0)      /* Duron Rev A0 */
+                /* Duron Rev A0 */
+                if (c->x86_model == 3 && c->x86_mask == 0)
                        size = 64;
+                /* Tbird rev A1/A2 */
                if (c->x86_model == 4 &&
-                    (c->x86_mask == 0 || c->x86_mask == 1))     /* Tbird rev A1/A2 */
+                        (c->x86_mask == 0 || c->x86_mask == 1))
                        size = 256;
        }
        return size;
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index c8e315f1aa83..01a265212395 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -81,7 +81,7 @@ static void __init check_fpu(void)
        boot_cpu_data.fdiv_bug = fdiv_bug;
        if (boot_cpu_data.fdiv_bug)
-                printk("Hmm, FPU with FDIV bug.\n");
+                printk(KERN_WARNING "Hmm, FPU with FDIV bug.\n");
 }
 static void __init check_hlt(void)
@@ -98,7 +98,7 @@ static void __init check_hlt(void)
        halt();
        halt();
        halt();
-        printk("OK.\n");
+        printk(KERN_CONT "OK.\n");
 }
 /*
@@ -122,9 +122,9 @@ static void __init check_popad(void)
         * CPU hard. Too bad.
         */
        if (res != 12345678)
-                printk("Buggy.\n");
+                printk(KERN_CONT "Buggy.\n");
        else
-                printk("OK.\n");
+                printk(KERN_CONT "OK.\n");
 #endif
 }
@@ -156,7 +156,7 @@ void __init check_bugs(void)
 {
        identify_boot_cpu();
 #ifndef CONFIG_SMP
-        printk("CPU: ");
+        printk(KERN_INFO "CPU: ");
        print_cpu_info(&boot_cpu_data);
 #endif
        check_config();
diff --git a/arch/x86/kernel/cpu/bugs_64.c b/arch/x86/kernel/cpu/bugs_64.c
index 9a3ed0649d4e..04f0fe5af83e 100644
--- a/arch/x86/kernel/cpu/bugs_64.c
+++ b/arch/x86/kernel/cpu/bugs_64.c
@@ -15,7 +15,7 @@ void __init check_bugs(void)
 {
        identify_boot_cpu();
 #if !defined(CONFIG_SMP)
-        printk("CPU: ");
+        printk(KERN_INFO "CPU: ");
        print_cpu_info(&boot_cpu_data);
 #endif
        alternative_instructions();
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 5ce60a88027b..2055fc2b2e6b 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -18,8 +18,8 @@
 #include <asm/hypervisor.h>
 #include <asm/processor.h>
 #include <asm/sections.h>
-#include <asm/topology.h>
+#include <linux/topology.h>
-#include <asm/cpumask.h>
+#include <linux/cpumask.h>
 #include <asm/pgtable.h>
 #include <asm/atomic.h>
 #include <asm/proto.h>
@@ -28,13 +28,13 @@
 #include <asm/desc.h>
 #include <asm/i387.h>
 #include <asm/mtrr.h>
-#include <asm/numa.h>
+#include <linux/numa.h>
 #include <asm/asm.h>
 #include <asm/cpu.h>
 #include <asm/mce.h>
 #include <asm/msr.h>
 #include <asm/pat.h>
-#include <asm/smp.h>
+#include <linux/smp.h>
 #ifdef CONFIG_X86_LOCAL_APIC
 #include <asm/uv/uv.h>
@@ -94,45 +94,45 @@ DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
         * TLS descriptors are currently at a different place compared to i386.
         * Hopefully nobody expects them at a fixed place (Wine?)
         */
-        [GDT_ENTRY_KERNEL32_CS]         = { { { 0x0000ffff, 0x00cf9b00 } } },
+        [GDT_ENTRY_KERNEL32_CS]         = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
-        [GDT_ENTRY_KERNEL_CS]           = { { { 0x0000ffff, 0x00af9b00 } } },
+        [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
-        [GDT_ENTRY_KERNEL_DS]           = { { { 0x0000ffff, 0x00cf9300 } } },
+        [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
-        [GDT_ENTRY_DEFAULT_USER32_CS]   = { { { 0x0000ffff, 0x00cffb00 } } },
+        [GDT_ENTRY_DEFAULT_USER32_CS]   = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
-        [GDT_ENTRY_DEFAULT_USER_DS]     = { { { 0x0000ffff, 0x00cff300 } } },
+        [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
-        [GDT_ENTRY_DEFAULT_USER_CS]     = { { { 0x0000ffff, 0x00affb00 } } },
+        [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
 #else
-        [GDT_ENTRY_KERNEL_CS]           = { { { 0x0000ffff, 0x00cf9a00 } } },
+        [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
-        [GDT_ENTRY_KERNEL_DS]           = { { { 0x0000ffff, 0x00cf9200 } } },
+        [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
-        [GDT_ENTRY_DEFAULT_USER_CS]     = { { { 0x0000ffff, 0x00cffa00 } } },
+        [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
-        [GDT_ENTRY_DEFAULT_USER_DS]     = { { { 0x0000ffff, 0x00cff200 } } },
+        [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
        /*
         * Segments used for calling PnP BIOS have byte granularity.
         * They code segments and data segments have fixed 64k limits,
         * the transfer segment sizes are set at run time.
         */
        /* 32-bit code */
-        [GDT_ENTRY_PNPBIOS_CS32]        = { { { 0x0000ffff, 0x00409a00 } } },
+        [GDT_ENTRY_PNPBIOS_CS32]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
        /* 16-bit code */
-        [GDT_ENTRY_PNPBIOS_CS16]        = { { { 0x0000ffff, 0x00009a00 } } },
+        [GDT_ENTRY_PNPBIOS_CS16]        = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
        /* 16-bit data */
-        [GDT_ENTRY_PNPBIOS_DS]          = { { { 0x0000ffff, 0x00009200 } } },
+        [GDT_ENTRY_PNPBIOS_DS]          = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
        /* 16-bit data */
-        [GDT_ENTRY_PNPBIOS_TS1]         = { { { 0x00000000, 0x00009200 } } },
+        [GDT_ENTRY_PNPBIOS_TS1]         = GDT_ENTRY_INIT(0x0092, 0, 0),
        /* 16-bit data */
-        [GDT_ENTRY_PNPBIOS_TS2]         = { { { 0x00000000, 0x00009200 } } },
+        [GDT_ENTRY_PNPBIOS_TS2]         = GDT_ENTRY_INIT(0x0092, 0, 0),
        /*
         * The APM segments have byte granularity and their bases
         * are set at run time.  All have 64k limits.
         */
        /* 32-bit code */
-        [GDT_ENTRY_APMBIOS_BASE]        = { { { 0x0000ffff, 0x00409a00 } } },
+        [GDT_ENTRY_APMBIOS_BASE]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
        /* 16-bit code */
-        [GDT_ENTRY_APMBIOS_BASE+1]      = { { { 0x0000ffff, 0x00009a00 } } },
+        [GDT_ENTRY_APMBIOS_BASE+1]      = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
        /* data */
-        [GDT_ENTRY_APMBIOS_BASE+2]      = { { { 0x0000ffff, 0x00409200 } } },
+        [GDT_ENTRY_APMBIOS_BASE+2]      = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
-        [GDT_ENTRY_ESPFIX_SS]           = { { { 0x0000ffff, 0x00cf9200 } } },
+        [GDT_ENTRY_ESPFIX_SS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
-        [GDT_ENTRY_PERCPU]              = { { { 0x0000ffff, 0x00cf9200 } } },
+        [GDT_ENTRY_PERCPU]              = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
        GDT_STACK_CANARY_INIT
 #endif
 } };
@@ -982,18 +982,26 @@ static __init int setup_disablecpuid(char *arg)
 __setup("clearcpuid=", setup_disablecpuid);
 #ifdef CONFIG_X86_64
-struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
+struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
 DEFINE_PER_CPU_FIRST(union irq_stack_union,
                     irq_stack_union) __aligned(PAGE_SIZE);
-DEFINE_PER_CPU(char *, irq_stack_ptr) =
+/*
-        init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
+ * The following four percpu variables are hot.  Align current_task to
+ * cacheline size such that all four fall in the same cacheline.
+ */
+DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
+        &init_task;
+EXPORT_PER_CPU_SYMBOL(current_task);
 DEFINE_PER_CPU(unsigned long, kernel_stack) =
        (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
 EXPORT_PER_CPU_SYMBOL(kernel_stack);
+DEFINE_PER_CPU(char *, irq_stack_ptr) =
+        init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
 /*
@@ -1008,8 +1016,7 @@ static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
 };
 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
-        [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
+        [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
-        __aligned(PAGE_SIZE);
 /* May not be marked __init: used by software suspend */
 void syscall_init(void)
@@ -1042,8 +1049,11 @@ DEFINE_PER_CPU(struct orig_ist, orig_ist);
 #else   /* CONFIG_X86_64 */
+DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
+EXPORT_PER_CPU_SYMBOL(current_task);
 #ifdef CONFIG_CC_STACKPROTECTOR
-DEFINE_PER_CPU(unsigned long, stack_canary);
+DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
 #endif
 /* Make sure %fs and %gs are initialized properly in idle threads */
diff --git a/arch/x86/kernel/cpu/cyrix.c b/arch/x86/kernel/cpu/cyrix.c
index 593171e967ef..19807b89f058 100644
--- a/arch/x86/kernel/cpu/cyrix.c
+++ b/arch/x86/kernel/cpu/cyrix.c
@@ -3,10 +3,10 @@
 #include <linux/delay.h>
 #include <linux/pci.h>
 #include <asm/dma.h>
-#include <asm/io.h>
+#include <linux/io.h>
 #include <asm/processor-cyrix.h>
 #include <asm/processor-flags.h>
-#include <asm/timer.h>
+#include <linux/timer.h>
 #include <asm/pci-direct.h>
 #include <asm/tsc.h>
@@ -282,7 +282,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                 *  The 5510/5520 companion chips have a funky PIT.
                 */
                if (vendor == PCI_VENDOR_ID_CYRIX &&
-         (device == PCI_DEVICE_ID_CYRIX_5510 || device == PCI_DEVICE_ID_CYRIX_5520))
+                        (device == PCI_DEVICE_ID_CYRIX_5510 ||
+                                        device == PCI_DEVICE_ID_CYRIX_5520))
                        mark_tsc_unstable("cyrix 5510/5520 detected");
        }
 #endif
@@ -299,7 +300,8 @@ static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
                         *  ?  : 0x7x
                         * GX1 : 0x8x          GX1  datasheet 56
                         */
-                        if ((0x30 <= dir1 && dir1 <= 0x6f) || (0x80 <= dir1 && dir1 <= 0x8f))
+                        if ((0x30 <= dir1 && dir1 <= 0x6f) ||
+                                        (0x80 <= dir1 && dir1 <= 0x8f))
                                geode_configure();
                        return;
                } else { /* MediaGX */
@@ -427,9 +429,12 @@ static void __cpuinit cyrix_identify(struct cpuinfo_x86 *c)
                        printk(KERN_INFO "Enabling CPUID on Cyrix processor.\n");
                        local_irq_save(flags);
                        ccr3 = getCx86(CX86_CCR3);
-                        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN  */
+                        /* enable MAPEN  */
-                        setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);  /* enable cpuid  */
+                        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
-                        setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
+                        /* enable cpuid  */
+                        setCx86_old(CX86_CCR4, getCx86_old(CX86_CCR4) | 0x80);
+                        /* disable MAPEN */
+                        setCx86(CX86_CCR3, ccr3);
                        local_irq_restore(flags);
                }
        }
diff --git a/arch/x86/kernel/cpu/hypervisor.c b/arch/x86/kernel/cpu/hypervisor.c
index fb5b86af0b01..93ba8eeb100a 100644
--- a/arch/x86/kernel/cpu/hypervisor.c
+++ b/arch/x86/kernel/cpu/hypervisor.c
@@ -28,11 +28,10 @@
 static inline void __cpuinit
 detect_hypervisor_vendor(struct cpuinfo_x86 *c)
 {
-        if (vmware_platform()) {
+        if (vmware_platform())
                c->x86_hyper_vendor = X86_HYPER_VENDOR_VMWARE;
-        } else {
+        else
                c->x86_hyper_vendor = X86_HYPER_VENDOR_NONE;
-        }
 }
 unsigned long get_hypervisor_tsc_freq(void)
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 3260ab044996..80a722a071b5 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -7,17 +7,17 @@
 #include <linux/sched.h>
 #include <linux/thread_info.h>
 #include <linux/module.h>
+#include <linux/uaccess.h>
 #include <asm/processor.h>
 #include <asm/pgtable.h>
 #include <asm/msr.h>
-#include <asm/uaccess.h>
 #include <asm/ds.h>
 #include <asm/bugs.h>
 #include <asm/cpu.h>
 #ifdef CONFIG_X86_64
-#include <asm/topology.h>
+#include <linux/topology.h>
 #include <asm/numa_64.h>
 #endif
@@ -174,7 +174,8 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
 #ifdef CONFIG_X86_F00F_BUG
        /*
         * All current models of Pentium and Pentium with MMX technology CPUs
-         * have the F0 0F bug, which lets nonprivileged users lock up the system.
+         * have the F0 0F bug, which lets nonprivileged users lock up the
+         * system.
         * Note that the workaround only should be initialized once...
         */
        c->f00f_bug = 0;
@@ -207,7 +208,7 @@ static void __cpuinit intel_workarounds(struct cpuinfo_x86 *c)
                        printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
                        printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
                        lo |= MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE;
-                        wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
+                        wrmsr(MSR_IA32_MISC_ENABLE, lo, hi);
                }
        }
@@ -283,7 +284,7 @@ static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
        /* Intel has a non-standard dependency on %ecx for this CPUID level. */
        cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
        if (eax & 0x1f)
-                return ((eax >> 26) + 1);
+                return (eax >> 26) + 1;
        else
                return 1;
 }
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index 789efe217e1a..804c40e2bc3e 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -3,7 +3,7 @@
 *
 *      Changes:
 *      Venkatesh Pallipadi     : Adding cache identification through cpuid(4)
- *              Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
+ *      Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
 *      Andi Kleen / Andreas Herrmann   : CPUID4 emulation on AMD.
 */
@@ -16,7 +16,7 @@
 #include <linux/pci.h>
 #include <asm/processor.h>
-#include <asm/smp.h>
+#include <linux/smp.h>
 #include <asm/k8.h>
 #define LVL_1_INST      1
@@ -25,14 +25,15 @@
 #define LVL_3           4
 #define LVL_TRACE       5
-struct _cache_table
+struct _cache_table {
-{
        unsigned char descriptor;
        char cache_type;
        short size;
 };
-/* all the cache descriptor types we care about (no TLB or trace cache entries) */
+/* All the cache descriptor types we care about (no TLB or
+   trace cache entries) */
 static const struct _cache_table __cpuinitconst cache_table[] =
 {
        { 0x06, LVL_1_INST, 8 },        /* 4-way set assoc, 32 byte line size */
@@ -105,8 +106,7 @@ static const struct _cache_table __cpuinitconst cache_table[] =
 };
-enum _cache_type
+enum _cache_type {
-{
        CACHE_TYPE_NULL = 0,
        CACHE_TYPE_DATA = 1,
        CACHE_TYPE_INST = 2,
@@ -170,31 +170,31 @@ unsigned short			num_cache_leaves;
   Maybe later */
 union l1_cache {
        struct {
-                unsigned line_size : 8;
+                unsigned line_size:8;
-                unsigned lines_per_tag : 8;
+                unsigned lines_per_tag:8;
-                unsigned assoc : 8;
+                unsigned assoc:8;
-                unsigned size_in_kb : 8;
+                unsigned size_in_kb:8;
        };
        unsigned val;
 };
 union l2_cache {
        struct {
-                unsigned line_size : 8;
+                unsigned line_size:8;
-                unsigned lines_per_tag : 4;
+                unsigned lines_per_tag:4;
-                unsigned assoc : 4;
+                unsigned assoc:4;
-                unsigned size_in_kb : 16;
+                unsigned size_in_kb:16;
        };
        unsigned val;
 };
 union l3_cache {
        struct {
-                unsigned line_size : 8;
+                unsigned line_size:8;
-                unsigned lines_per_tag : 4;
+                unsigned lines_per_tag:4;
-                unsigned assoc : 4;
+                unsigned assoc:4;
-                unsigned res : 2;
+                unsigned res:2;
-                unsigned size_encoded : 14;
+                unsigned size_encoded:14;
        };
        unsigned val;
 };
@@ -241,7 +241,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
        case 0:
                if (!l1->val)
                        return;
-                assoc = l1->assoc;
+                assoc = assocs[l1->assoc];
                line_size = l1->line_size;
                lines_per_tag = l1->lines_per_tag;
                size_in_kb = l1->size_in_kb;
@@ -249,7 +249,7 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
        case 2:
                if (!l2.val)
                        return;
-                assoc = l2.assoc;
+                assoc = assocs[l2.assoc];
                line_size = l2.line_size;
                lines_per_tag = l2.lines_per_tag;
                /* cpu_data has errata corrections for K7 applied */
@@ -258,10 +258,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
        case 3:
                if (!l3.val)
                        return;
-                assoc = l3.assoc;
+                assoc = assocs[l3.assoc];
                line_size = l3.line_size;
                lines_per_tag = l3.lines_per_tag;
                size_in_kb = l3.size_encoded * 512;
+                if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
+                        size_in_kb = size_in_kb >> 1;
+                        assoc = assoc >> 1;
+                }
                break;
        default:
                return;
@@ -270,18 +274,14 @@ amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
        eax->split.is_self_initializing = 1;
        eax->split.type = types[leaf];
        eax->split.level = levels[leaf];
-        if (leaf == 3)
+        eax->split.num_threads_sharing = 0;
-                eax->split.num_threads_sharing =
-                        current_cpu_data.x86_max_cores - 1;
-        else
-                eax->split.num_threads_sharing = 0;
        eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
-        if (assoc == 0xf)
+        if (assoc == 0xffff)
                eax->split.is_fully_associative = 1;
        ebx->split.coherency_line_size = line_size - 1;
-        ebx->split.ways_of_associativity = assocs[assoc] - 1;
+        ebx->split.ways_of_associativity = assoc - 1;
        ebx->split.physical_line_partition = lines_per_tag - 1;
        ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
                (ebx->split.ways_of_associativity + 1) - 1;
@@ -350,7 +350,8 @@ static int __cpuinit find_num_cache_leaves(void)
 unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
 {
-        unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
+        /* Cache sizes */
+        unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
        unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
        unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
        unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
@@ -377,8 +378,8 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
                        retval = cpuid4_cache_lookup_regs(i, &this_leaf);
                        if (retval >= 0) {
-                                switch(this_leaf.eax.split.level) {
+                                switch (this_leaf.eax.split.level) {
-                                    case 1:
+                                case 1:
                                        if (this_leaf.eax.split.type ==
                                                        CACHE_TYPE_DATA)
                                                new_l1d = this_leaf.size/1024;
@@ -386,19 +387,20 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
                                                        CACHE_TYPE_INST)
                                                new_l1i = this_leaf.size/1024;
                                        break;
-                                    case 2:
+                                case 2:
                                        new_l2 = this_leaf.size/1024;
                                        num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
                                        index_msb = get_count_order(num_threads_sharing);
                                        l2_id = c->apicid >> index_msb;
                                        break;
-                                    case 3:
+                                case 3:
                                        new_l3 = this_leaf.size/1024;
                                        num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
-                                        index_msb = get_count_order(num_threads_sharing);
+                                        index_msb = get_count_order(
+                                                        num_threads_sharing);
                                        l3_id = c->apicid >> index_msb;
                                        break;
-                                    default:
+                                default:
                                        break;
                                }
                        }
@@ -421,22 +423,21 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
                /* Number of times to iterate */
                n = cpuid_eax(2) & 0xFF;
-                for ( i = 0 ; i < n ; i++ ) {
+                for (i = 0 ; i < n ; i++) {
                        cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
                        /* If bit 31 is set, this is an unknown format */
-                        for ( j = 0 ; j < 3 ; j++ ) {
+                        for (j = 0 ; j < 3 ; j++)
-                                if (regs[j] & (1 << 31)) regs[j] = 0;
+                                if (regs[j] & (1 << 31))
-                        }
+                                        regs[j] = 0;
                        /* Byte 0 is level count, not a descriptor */
-                        for ( j = 1 ; j < 16 ; j++ ) {
+                        for (j = 1 ; j < 16 ; j++) {
                                unsigned char des = dp[j];
                                unsigned char k = 0;
                                /* look up this descriptor in the table */
-                                while (cache_table[k].descriptor != 0)
+                                while (cache_table[k].descriptor != 0) {
-                                {
                                        if (cache_table[k].descriptor == des) {
                                                if (only_trace && cache_table[k].cache_type != LVL_TRACE)
                                                        break;
@@ -488,14 +489,14 @@ unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
        }
        if (trace)
-                printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
+                printk(KERN_INFO "CPU: Trace cache: %dK uops", trace);
-        else if ( l1i )
+        else if (l1i)
-                printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
+                printk(KERN_INFO "CPU: L1 I cache: %dK", l1i);
        if (l1d)
-                printk(", L1 D cache: %dK\n", l1d);
+                printk(KERN_CONT ", L1 D cache: %dK\n", l1d);
        else
-                printk("\n");
+                printk(KERN_CONT "\n");
        if (l2)
                printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
@@ -522,6 +523,18 @@ static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
        int index_msb, i;
        struct cpuinfo_x86 *c = &cpu_data(cpu);
+        if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
+                struct cpuinfo_x86 *d;
+                for_each_online_cpu(i) {
+                        if (!per_cpu(cpuid4_info, i))
+                                continue;
+                        d = &cpu_data(i);
+                        this_leaf = CPUID4_INFO_IDX(i, index);
+                        cpumask_copy(to_cpumask(this_leaf->shared_cpu_map),
+                                     d->llc_shared_map);
+                }
+                return;
+        }
        this_leaf = CPUID4_INFO_IDX(cpu, index);
        num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
@@ -558,8 +571,13 @@ static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
        }
 }
 #else
-static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index) {}
+static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
-static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index) {}
+{
+}
+static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
+{
+}
 #endif
 static void __cpuinit free_cache_attributes(unsigned int cpu)
@@ -645,7 +663,7 @@ static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
 static ssize_t show_##file_name                                         \
                        (struct _cpuid4_info *this_leaf, char *buf)     \
 {                                                                       \
-        return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \
+        return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
 }
 show_one_plus(level, eax.split.level, 0);
@@ -656,7 +674,7 @@ show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
 static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
 {
-        return sprintf (buf, "%luK\n", this_leaf->size / 1024);
+        return sprintf(buf, "%luK\n", this_leaf->size / 1024);
 }
 static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
@@ -669,7 +687,7 @@ static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
                const struct cpumask *mask;
                mask = to_cpumask(this_leaf->shared_cpu_map);
-                n = type?
+                n = type ?
                        cpulist_scnprintf(buf, len-2, mask) :
                        cpumask_scnprintf(buf, len-2, mask);
                buf[n++] = '\n';
@@ -800,7 +818,7 @@ static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
                show_cache_disable_1, store_cache_disable_1);
-static struct attribute * default_attrs[] = {
+static struct attribute *default_attrs[] = {
        &type.attr,
        &level.attr,
        &coherency_line_size.attr,
@@ -815,7 +833,7 @@ static struct attribute * default_attrs[] = {
        NULL
 };
-static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
+static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
 {
        struct _cache_attr *fattr = to_attr(attr);
        struct _index_kobject *this_leaf = to_object(kobj);
@@ -828,8 +846,8 @@ static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
        return ret;
 }
-static ssize_t store(struct kobject * kobj, struct attribute * attr,
+static ssize_t store(struct kobject *kobj, struct attribute *attr,
-                     const char * buf, size_t count)
+                     const char *buf, size_t count)
 {
        struct _cache_attr *fattr = to_attr(attr);
        struct _index_kobject *this_leaf = to_object(kobj);
@@ -883,7 +901,7 @@ static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
                goto err_out;
        per_cpu(index_kobject, cpu) = kzalloc(
-            sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL);
+            sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
        if (unlikely(per_cpu(index_kobject, cpu) == NULL))
                goto err_out;
@@ -917,7 +935,7 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
        }
        for (i = 0; i < num_cache_leaves; i++) {
-                this_object = INDEX_KOBJECT_PTR(cpu,i);
+                this_object = INDEX_KOBJECT_PTR(cpu, i);
                this_object->cpu = cpu;
                this_object->index = i;
                retval = kobject_init_and_add(&(this_object->kobj),
@@ -925,9 +943,8 @@ static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
                                              per_cpu(cache_kobject, cpu),
                                              "index%1lu", i);
                if (unlikely(retval)) {
-                        for (j = 0; j < i; j++) {
+                        for (j = 0; j < i; j++)
-                                kobject_put(&(INDEX_KOBJECT_PTR(cpu,j)->kobj));
+                                kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
-                        }
                        kobject_put(per_cpu(cache_kobject, cpu));
                        cpuid4_cache_sysfs_exit(cpu);
                        return retval;
@@ -952,7 +969,7 @@ static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
        cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
        for (i = 0; i < num_cache_leaves; i++)
-                kobject_put(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
+                kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
        kobject_put(per_cpu(cache_kobject, cpu));
        cpuid4_cache_sysfs_exit(cpu);
 }
@@ -977,8 +994,7 @@ static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
        return NOTIFY_OK;
 }
-static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier =
+static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = {
-{
        .notifier_call = cacheinfo_cpu_callback,
 };
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 01213048f62f..9bfe9d2ea615 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -183,6 +183,11 @@ void mce_log(struct mce *mce)
        set_bit(0, &mce_need_notify);
 }
+void __weak decode_mce(struct mce *m)
+{
+        return;
+}
 static void print_mce(struct mce *m)
 {
        printk(KERN_EMERG
@@ -205,6 +210,8 @@ static void print_mce(struct mce *m)
        printk(KERN_EMERG "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
                        m->cpuvendor, m->cpuid, m->time, m->socketid,
                        m->apicid);
+        decode_mce(m);
 }
 static void print_mce_head(void)
@@ -215,7 +222,10 @@ static void print_mce_head(void)
 static void print_mce_tail(void)
 {
        printk(KERN_EMERG "This is not a software problem!\n"
-               "Run through mcelog --ascii to decode and contact your hardware vendor\n");
+#if (!defined(CONFIG_EDAC) || !defined(CONFIG_CPU_SUP_AMD))
+               "Run through mcelog --ascii to decode and contact your hardware vendor\n"
+#endif
+               );
 }
 #define PANIC_TIMEOUT 5 /* 5 seconds */
diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index ddae21620bda..1fecba404fd8 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -489,12 +489,14 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
        int i, err = 0;
        struct threshold_bank *b = NULL;
        char name[32];
+        struct cpuinfo_x86 *c = &cpu_data(cpu);
        sprintf(name, "threshold_bank%i", bank);
 #ifdef CONFIG_SMP
        if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) {   /* symlink */
-                i = cpumask_first(cpu_core_mask(cpu));
+                i = cpumask_first(c->llc_shared_map);
                /* first core not up yet */
                if (cpu_data(i).cpu_core_id)
@@ -514,7 +516,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
                if (err)
                        goto out;
-                cpumask_copy(b->cpus, cpu_core_mask(cpu));
+                cpumask_copy(b->cpus, c->llc_shared_map);
                per_cpu(threshold_banks, cpu)[bank] = b;
                goto out;
@@ -539,7 +541,7 @@ static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
 #ifndef CONFIG_SMP
        cpumask_setall(b->cpus);
 #else
-        cpumask_copy(b->cpus, cpu_core_mask(cpu));
+        cpumask_copy(b->cpus, c->llc_shared_map);
 #endif
        per_cpu(threshold_banks, cpu)[bank] = b;
diff --git a/arch/x86/kernel/cpu/mtrr/amd.c b/arch/x86/kernel/cpu/mtrr/amd.c
index ee2331b0e58f..33af14110dfd 100644
--- a/arch/x86/kernel/cpu/mtrr/amd.c
+++ b/arch/x86/kernel/cpu/mtrr/amd.c
@@ -7,15 +7,15 @@
 static void
 amd_get_mtrr(unsigned int reg, unsigned long *base,
-             unsigned long *size, mtrr_type * type)
+             unsigned long *size, mtrr_type *type)
 {
        unsigned long low, high;
        rdmsr(MSR_K6_UWCCR, low, high);
-        /*  Upper dword is region 1, lower is region 0  */
+        /* Upper dword is region 1, lower is region 0 */
        if (reg == 1)
                low = high;
-        /*  The base masks off on the right alignment  */
+        /* The base masks off on the right alignment */
        *base = (low & 0xFFFE0000) >> PAGE_SHIFT;
        *type = 0;
        if (low & 1)
@@ -27,74 +27,81 @@ amd_get_mtrr(unsigned int reg, unsigned long *base,
                return;
        }
        /*
-         *  This needs a little explaining. The size is stored as an
+         * This needs a little explaining. The size is stored as an
-         *  inverted mask of bits of 128K granularity 15 bits long offset
+         * inverted mask of bits of 128K granularity 15 bits long offset
-         *  2 bits
+         * 2 bits.
         *
-         *  So to get a size we do invert the mask and add 1 to the lowest
+         * So to get a size we do invert the mask and add 1 to the lowest
-         *  mask bit (4 as its 2 bits in). This gives us a size we then shift
+         * mask bit (4 as its 2 bits in). This gives us a size we then shift
-         *  to turn into 128K blocks
+         * to turn into 128K blocks.
         *
-         *  eg              111 1111 1111 1100      is 512K
+         * eg              111 1111 1111 1100      is 512K
         *
-         *  invert          000 0000 0000 0011
+         * invert          000 0000 0000 0011
-         *  +1              000 0000 0000 0100
+         * +1              000 0000 0000 0100
-         *  *128K   ...
+         * *128K   ...
         */
        low = (~low) & 0x1FFFC;
        *size = (low + 4) << (15 - PAGE_SHIFT);
-        return;
 }
-static void amd_set_mtrr(unsigned int reg, unsigned long base,
+/**
-                         unsigned long size, mtrr_type type)
+ * amd_set_mtrr - Set variable MTRR register on the local CPU.
-/*  [SUMMARY] Set variable MTRR register on the local CPU.
+ *
-    <reg> The register to set.
+ * @reg The register to set.
-    <base> The base address of the region.
+ * @base The base address of the region.
-    <size> The size of the region. If this is 0 the region is disabled.
+ * @size The size of the region. If this is 0 the region is disabled.
-    <type> The type of the region.
+ * @type The type of the region.
-    [RETURNS] Nothing.
+ *
-*/
+ * Returns nothing.
+ */
+static void
+amd_set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
 {
        u32 regs[2];
        /*
-         *  Low is MTRR0 , High MTRR 1
+         * Low is MTRR0, High MTRR 1
         */
        rdmsr(MSR_K6_UWCCR, regs[0], regs[1]);
        /*
-         *  Blank to disable
+         * Blank to disable
         */
-        if (size == 0)
+        if (size == 0) {
                regs[reg] = 0;
-        else
+        } else {
-                /* Set the register to the base, the type (off by one) and an
+                /*
-                   inverted bitmask of the size The size is the only odd
+                 * Set the register to the base, the type (off by one) and an
-                   bit. We are fed say 512K We invert this and we get 111 1111
+                 * inverted bitmask of the size The size is the only odd
-                   1111 1011 but if you subtract one and invert you get the   
+                 * bit. We are fed say 512K We invert this and we get 111 1111
-                   desired 111 1111 1111 1100 mask
+                 * 1111 1011 but if you subtract one and invert you get the
+                 * desired 111 1111 1111 1100 mask
-                   But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!  */
+                 *
+                 *  But ~(x - 1) == ~x + 1 == -x. Two's complement rocks!
+                 */
                regs[reg] = (-size >> (15 - PAGE_SHIFT) & 0x0001FFFC)
                    | (base << PAGE_SHIFT) | (type + 1);
+        }
        /*
-         *  The writeback rule is quite specific. See the manual. Its
+         * The writeback rule is quite specific. See the manual. Its
-         *  disable local interrupts, write back the cache, set the mtrr
+         * disable local interrupts, write back the cache, set the mtrr
         */
        wbinvd();
        wrmsr(MSR_K6_UWCCR, regs[0], regs[1]);
 }
-static int amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
+static int
+amd_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
 {
-        /* Apply the K6 block alignment and size rules
+        /*
-           In order
+         * Apply the K6 block alignment and size rules
-           o Uncached or gathering only
+         * In order
-           o 128K or bigger block
+         * o Uncached or gathering only
-           o Power of 2 block
+         * o 128K or bigger block
-           o base suitably aligned to the power
+         * o Power of 2 block
-        */
+         * o base suitably aligned to the power
+         */
        if (type > MTRR_TYPE_WRCOMB || size < (1 << (17 - PAGE_SHIFT))
            || (size & ~(size - 1)) - size || (base & (size - 1)))
                return -EINVAL;
@@ -115,5 +122,3 @@ int __init amd_init_mtrr(void)
        set_mtrr_ops(&amd_mtrr_ops);
        return 0;
 }
-//arch_initcall(amd_mtrr_init);
diff --git a/arch/x86/kernel/cpu/mtrr/centaur.c b/arch/x86/kernel/cpu/mtrr/centaur.c
index cb9aa3a7a7ab..de89f14eff3a 100644
--- a/arch/x86/kernel/cpu/mtrr/centaur.c
+++ b/arch/x86/kernel/cpu/mtrr/centaur.c
@@ -1,7 +1,9 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <asm/mtrr.h>
 #include <asm/msr.h>
 #include "mtrr.h"
 static struct {
@@ -12,25 +14,25 @@ static struct {
 static u8 centaur_mcr_reserved;
 static u8 centaur_mcr_type;     /* 0 for winchip, 1 for winchip2 */
-/*
+/**
- *      Report boot time MCR setups 
+ * centaur_get_free_region - Get a free MTRR.
+ *
+ * @base: The starting (base) address of the region.
+ * @size: The size (in bytes) of the region.
+ *
+ * Returns: the index of the region on success, else -1 on error.
 */
 static int
 centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg)
-/*  [SUMMARY] Get a free MTRR.
-    <base> The starting (base) address of the region.
-    <size> The size (in bytes) of the region.
-    [RETURNS] The index of the region on success, else -1 on error.
-*/
 {
-        int i, max;
-        mtrr_type ltype;
        unsigned long lbase, lsize;
+        mtrr_type ltype;
+        int i, max;
        max = num_var_ranges;
        if (replace_reg >= 0 && replace_reg < max)
                return replace_reg;
        for (i = 0; i < max; ++i) {
                if (centaur_mcr_reserved & (1 << i))
                        continue;
@@ -38,11 +40,14 @@ centaur_get_free_region(unsigned long base, unsigned long size, int replace_reg)
                if (lsize == 0)
                        return i;
        }
        return -ENOSPC;
 }
-void
+/*
-mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
+ * Report boot time MCR setups
+ */
+void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
 {
        centaur_mcr[mcr].low = lo;
        centaur_mcr[mcr].high = hi;
@@ -54,33 +59,35 @@ centaur_get_mcr(unsigned int reg, unsigned long *base,
 {
        *base = centaur_mcr[reg].high >> PAGE_SHIFT;
        *size = -(centaur_mcr[reg].low & 0xfffff000) >> PAGE_SHIFT;
-        *type = MTRR_TYPE_WRCOMB;       /*  If it is there, it is write-combining  */
+        *type = MTRR_TYPE_WRCOMB;               /* write-combining  */
        if (centaur_mcr_type == 1 && ((centaur_mcr[reg].low & 31) & 2))
                *type = MTRR_TYPE_UNCACHABLE;
        if (centaur_mcr_type == 1 && (centaur_mcr[reg].low & 31) == 25)
                *type = MTRR_TYPE_WRBACK;
        if (centaur_mcr_type == 0 && (centaur_mcr[reg].low & 31) == 31)
                *type = MTRR_TYPE_WRBACK;
 }
-static void centaur_set_mcr(unsigned int reg, unsigned long base,
+static void
-                            unsigned long size, mtrr_type type)
+centaur_set_mcr(unsigned int reg, unsigned long base,
+                unsigned long size, mtrr_type type)
 {
        unsigned long low, high;
        if (size == 0) {
-                /*  Disable  */
+                /* Disable */
                high = low = 0;
        } else {
                high = base << PAGE_SHIFT;
-                if (centaur_mcr_type == 0)
+                if (centaur_mcr_type == 0) {
-                        low = -size << PAGE_SHIFT | 0x1f;       /* only support write-combining... */
+                        /* Only support write-combining... */
-                else {
+                        low = -size << PAGE_SHIFT | 0x1f;
+                } else {
                        if (type == MTRR_TYPE_UNCACHABLE)
-                                low = -size << PAGE_SHIFT | 0x02;       /* NC */
+                                low = -size << PAGE_SHIFT | 0x02; /* NC */
                        else
-                                low = -size << PAGE_SHIFT | 0x09;       /* WWO,WC */
+                                low = -size << PAGE_SHIFT | 0x09; /* WWO, WC */
                }
        }
        centaur_mcr[reg].high = high;
@@ -88,118 +95,16 @@ static void centaur_set_mcr(unsigned int reg, unsigned long base,
        wrmsr(MSR_IDT_MCR0 + reg, low, high);
 }
-#if 0
+static int
-/*
+centaur_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
- *      Initialise the later (saner) Winchip MCR variant. In this version
- *      the BIOS can pass us the registers it has used (but not their values)
- *      and the control register is read/write
- */
-static void __init
-centaur_mcr1_init(void)
-{
-        unsigned i;
-        u32 lo, hi;
-        /* Unfortunately, MCR's are read-only, so there is no way to
-         * find out what the bios might have done.
-         */
-        rdmsr(MSR_IDT_MCR_CTRL, lo, hi);
-        if (((lo >> 17) & 7) == 1) {    /* Type 1 Winchip2 MCR */
-                lo &= ~0x1C0;   /* clear key */
-                lo |= 0x040;    /* set key to 1 */
-                wrmsr(MSR_IDT_MCR_CTRL, lo, hi);        /* unlock MCR */
-        }
-        centaur_mcr_type = 1;
-        /*
-         *  Clear any unconfigured MCR's.
-         */
-        for (i = 0; i < 8; ++i) {
-                if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0) {
-                        if (!(lo & (1 << (9 + i))))
-                                wrmsr(MSR_IDT_MCR0 + i, 0, 0);
-                        else
-                                /*
-                                 *      If the BIOS set up an MCR we cannot see it
-                                 *      but we don't wish to obliterate it
-                                 */
-                                centaur_mcr_reserved |= (1 << i);
-                }
-        }
-        /*  
-         *  Throw the main write-combining switch... 
-         *  However if OOSTORE is enabled then people have already done far
-         *  cleverer things and we should behave. 
-         */
-        lo |= 15;               /* Write combine enables */
-        wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
-}
-/*
- *      Initialise the original winchip with read only MCR registers
- *      no used bitmask for the BIOS to pass on and write only control
- */
-static void __init
-centaur_mcr0_init(void)
-{
-        unsigned i;
-        /* Unfortunately, MCR's are read-only, so there is no way to
-         * find out what the bios might have done.
-         */
-        /* Clear any unconfigured MCR's.
-         * This way we are sure that the centaur_mcr array contains the actual
-         * values. The disadvantage is that any BIOS tweaks are thus undone.
-         *
-         */
-        for (i = 0; i < 8; ++i) {
-                if (centaur_mcr[i].high == 0 && centaur_mcr[i].low == 0)
-                        wrmsr(MSR_IDT_MCR0 + i, 0, 0);
-        }
-        wrmsr(MSR_IDT_MCR_CTRL, 0x01F0001F, 0); /* Write only */
-}
-/*
- *      Initialise Winchip series MCR registers
- */
-static void __init
-centaur_mcr_init(void)
-{
-        struct set_mtrr_context ctxt;
-        set_mtrr_prepare_save(&ctxt);
-        set_mtrr_cache_disable(&ctxt);
-        if (boot_cpu_data.x86_model == 4)
-                centaur_mcr0_init();
-        else if (boot_cpu_data.x86_model == 8 || boot_cpu_data.x86_model == 9)
-                centaur_mcr1_init();
-        set_mtrr_done(&ctxt);
-}
-#endif
-static int centaur_validate_add_page(unsigned long base, 
-                                     unsigned long size, unsigned int type)
 {
        /*
-         *  FIXME: Winchip2 supports uncached
+         * FIXME: Winchip2 supports uncached
         */
-        if (type != MTRR_TYPE_WRCOMB && 
+        if (type != MTRR_TYPE_WRCOMB &&
            (centaur_mcr_type == 0 || type != MTRR_TYPE_UNCACHABLE)) {
-                printk(KERN_WARNING
+                pr_warning("mtrr: only write-combining%s supported\n",
-                       "mtrr: only write-combining%s supported\n",
+                           centaur_mcr_type ? " and uncacheable are" : " is");
-                       centaur_mcr_type ? " and uncacheable are"
-                       : " is");
                return -EINVAL;
        }
        return 0;
@@ -207,7 +112,6 @@ static int centaur_validate_add_page(unsigned long base,
 static struct mtrr_ops centaur_mtrr_ops = {
        .vendor            = X86_VENDOR_CENTAUR,
-//      .init              = centaur_mcr_init,
        .set               = centaur_set_mcr,
        .get               = centaur_get_mcr,
        .get_free_region   = centaur_get_free_region,
@@ -220,5 +124,3 @@ int __init centaur_init_mtrr(void)
        set_mtrr_ops(&centaur_mtrr_ops);
        return 0;
 }
-//arch_initcall(centaur_init_mtrr);
diff --git a/arch/x86/kernel/cpu/mtrr/cleanup.c b/arch/x86/kernel/cpu/mtrr/cleanup.c
index 1d584a18a50d..315738c74aad 100644
--- a/arch/x86/kernel/cpu/mtrr/cleanup.c
+++ b/arch/x86/kernel/cpu/mtrr/cleanup.c
@@ -1,51 +1,75 @@
-/*  MTRR (Memory Type Range Register) cleanup
+/*
+ * MTRR (Memory Type Range Register) cleanup
-    Copyright (C) 2009 Yinghai Lu
+ *
+ *  Copyright (C) 2009 Yinghai Lu
-    This library is free software; you can redistribute it and/or
+ *
-    modify it under the terms of the GNU Library General Public
+ * This library is free software; you can redistribute it and/or
-    License as published by the Free Software Foundation; either
+ * modify it under the terms of the GNU Library General Public
-    version 2 of the License, or (at your option) any later version.
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
-    This library is distributed in the hope that it will be useful,
+ *
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * This library is distributed in the hope that it will be useful,
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-    Library General Public License for more details.
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Library General Public License for more details.
-    You should have received a copy of the GNU Library General Public
+ *
-    License along with this library; if not, write to the Free
+ * You should have received a copy of the GNU Library General Public
-    Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * License along with this library; if not, write to the Free
-*/
+ * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/pci.h>
 #include <linux/smp.h>
 #include <linux/cpu.h>
-#include <linux/mutex.h>
 #include <linux/sort.h>
+#include <linux/mutex.h>
+#include <linux/uaccess.h>
+#include <linux/kvm_para.h>
+#include <asm/processor.h>
 #include <asm/e820.h>
 #include <asm/mtrr.h>
-#include <asm/uaccess.h>
-#include <asm/processor.h>
 #include <asm/msr.h>
-#include <asm/kvm_para.h>
-#include "mtrr.h"
-/* should be related to MTRR_VAR_RANGES nums */
+#include "mtrr.h"
-#define RANGE_NUM 256
 struct res_range {
-        unsigned long start;
+        unsigned long   start;
-        unsigned long end;
+        unsigned long   end;
+};
+struct var_mtrr_range_state {
+        unsigned long   base_pfn;
+        unsigned long   size_pfn;
+        mtrr_type       type;
+};
+struct var_mtrr_state {
+        unsigned long   range_startk;
+        unsigned long   range_sizek;
+        unsigned long   chunk_sizek;
+        unsigned long   gran_sizek;
+        unsigned int    reg;
 };
+/* Should be related to MTRR_VAR_RANGES nums */
+#define RANGE_NUM                               256
+static struct res_range __initdata              range[RANGE_NUM];
+static int __initdata                           nr_range;
+static struct var_mtrr_range_state __initdata   range_state[RANGE_NUM];
+static int __initdata debug_print;
+#define Dprintk(x...) do { if (debug_print) printk(KERN_DEBUG x); } while (0)
 static int __init
-add_range(struct res_range *range, int nr_range, unsigned long start,
+add_range(struct res_range *range, int nr_range,
-                              unsigned long end)
+          unsigned long start, unsigned long end)
 {
-        /* out of slots */
+        /* Out of slots: */
        if (nr_range >= RANGE_NUM)
                return nr_range;
@@ -58,12 +82,12 @@ add_range(struct res_range *range, int nr_range, unsigned long start,
 }
 static int __init
-add_range_with_merge(struct res_range *range, int nr_range, unsigned long start,
+add_range_with_merge(struct res_range *range, int nr_range,
-                              unsigned long end)
+                     unsigned long start, unsigned long end)
 {
        int i;
-        /* try to merge it with old one */
+        /* Try to merge it with old one: */
        for (i = 0; i < nr_range; i++) {
                unsigned long final_start, final_end;
                unsigned long common_start, common_end;
@@ -84,7 +108,7 @@ add_range_with_merge(struct res_range *range, int nr_range, unsigned long start,
                return nr_range;
        }
-        /* need to add that */
+        /* Need to add it: */
        return add_range(range, nr_range, start, end);
 }
@@ -117,7 +141,7 @@ subtract_range(struct res_range *range, unsigned long start, unsigned long end)
                }
                if (start > range[j].start && end < range[j].end) {
-                        /* find the new spare */
+                        /* Find the new spare: */
                        for (i = 0; i < RANGE_NUM; i++) {
                                if (range[i].end == 0)
                                        break;
@@ -146,14 +170,8 @@ static int __init cmp_range(const void *x1, const void *x2)
        return start1 - start2;
 }
-struct var_mtrr_range_state {
+#define BIOS_BUG_MSG KERN_WARNING \
-        unsigned long base_pfn;
+        "WARNING: BIOS bug: VAR MTRR %d contains strange UC entry under 1M, check with your system vendor!\n"
-        unsigned long size_pfn;
-        mtrr_type type;
-};
-static struct var_mtrr_range_state __initdata range_state[RANGE_NUM];
-static int __initdata debug_print;
 static int __init
 x86_get_mtrr_mem_range(struct res_range *range, int nr_range,
@@ -180,7 +198,7 @@ x86_get_mtrr_mem_range(struct res_range *range, int nr_range,
                                 range[i].start, range[i].end + 1);
        }
-        /* take out UC ranges */
+        /* Take out UC ranges: */
        for (i = 0; i < num_var_ranges; i++) {
                type = range_state[i].type;
                if (type != MTRR_TYPE_UNCACHABLE &&
@@ -193,9 +211,7 @@ x86_get_mtrr_mem_range(struct res_range *range, int nr_range,
                if (base < (1<<(20-PAGE_SHIFT)) && mtrr_state.have_fixed &&
                    (mtrr_state.enabled & 1)) {
                        /* Var MTRR contains UC entry below 1M? Skip it: */
-                        printk(KERN_WARNING "WARNING: BIOS bug: VAR MTRR %d "
+                        printk(BIOS_BUG_MSG, i);
-                                "contains strange UC entry under 1M, check "
-                                "with your system vendor!\n", i);
                        if (base + size <= (1<<(20-PAGE_SHIFT)))
                                continue;
                        size -= (1<<(20-PAGE_SHIFT)) - base;
@@ -237,17 +253,13 @@ x86_get_mtrr_mem_range(struct res_range *range, int nr_range,
        return nr_range;
 }
-static struct res_range __initdata range[RANGE_NUM];
-static int __initdata nr_range;
 #ifdef CONFIG_MTRR_SANITIZER
 static unsigned long __init sum_ranges(struct res_range *range, int nr_range)
 {
-        unsigned long sum;
+        unsigned long sum = 0;
        int i;
-        sum = 0;
        for (i = 0; i < nr_range; i++)
                sum += range[i].end + 1 - range[i].start;
@@ -278,17 +290,9 @@ static int __init mtrr_cleanup_debug_setup(char *str)
 }
 early_param("mtrr_cleanup_debug", mtrr_cleanup_debug_setup);
-struct var_mtrr_state {
-        unsigned long   range_startk;
-        unsigned long   range_sizek;
-        unsigned long   chunk_sizek;
-        unsigned long   gran_sizek;
-        unsigned int    reg;
-};
 static void __init
 set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
-                unsigned char type, unsigned int address_bits)
+             unsigned char type, unsigned int address_bits)
 {
        u32 base_lo, base_hi, mask_lo, mask_hi;
        u64 base, mask;
@@ -301,7 +305,7 @@ set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
        mask = (1ULL << address_bits) - 1;
        mask &= ~((((u64)sizek) << 10) - 1);
-        base  = ((u64)basek) << 10;
+        base = ((u64)basek) << 10;
        base |= type;
        mask |= 0x800;
@@ -317,15 +321,14 @@ set_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
 static void __init
 save_var_mtrr(unsigned int reg, unsigned long basek, unsigned long sizek,
-                unsigned char type)
+              unsigned char type)
 {
        range_state[reg].base_pfn = basek >> (PAGE_SHIFT - 10);
        range_state[reg].size_pfn = sizek >> (PAGE_SHIFT - 10);
        range_state[reg].type = type;
 }
-static void __init
+static void __init set_var_mtrr_all(unsigned int address_bits)
-set_var_mtrr_all(unsigned int address_bits)
 {
        unsigned long basek, sizek;
        unsigned char type;
@@ -342,11 +345,11 @@ set_var_mtrr_all(unsigned int address_bits)
 static unsigned long to_size_factor(unsigned long sizek, char *factorp)
 {
-        char factor;
        unsigned long base = sizek;
+        char factor;
        if (base & ((1<<10) - 1)) {
-                /* not MB alignment */
+                /* Not MB-aligned: */
                factor = 'K';
        } else if (base & ((1<<20) - 1)) {
                factor = 'M';
@@ -372,11 +375,12 @@ range_to_mtrr(unsigned int reg, unsigned long range_startk,
                unsigned long max_align, align;
                unsigned long sizek;
-                /* Compute the maximum size I can make a range */
+                /* Compute the maximum size with which we can make a range: */
                if (range_startk)
                        max_align = ffs(range_startk) - 1;
                else
                        max_align = 32;
                align = fls(range_sizek) - 1;
                if (align > max_align)
                        align = max_align;
@@ -386,11 +390,10 @@ range_to_mtrr(unsigned int reg, unsigned long range_startk,
                        char start_factor = 'K', size_factor = 'K';
                        unsigned long start_base, size_base;
-                        start_base = to_size_factor(range_startk,
+                        start_base = to_size_factor(range_startk, &start_factor);
-                                                         &start_factor),
+                        size_base = to_size_factor(sizek, &size_factor);
-                        size_base = to_size_factor(sizek, &size_factor),
-                        printk(KERN_DEBUG "Setting variable MTRR %d, "
+                        Dprintk("Setting variable MTRR %d, "
                                "base: %ld%cB, range: %ld%cB, type %s\n",
                                reg, start_base, start_factor,
                                size_base, size_factor,
@@ -425,10 +428,11 @@ range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
        chunk_sizek = state->chunk_sizek;
        gran_sizek = state->gran_sizek;
-        /* align with gran size, prevent small block used up MTRRs */
+        /* Align with gran size, prevent small block used up MTRRs: */
        range_basek = ALIGN(state->range_startk, gran_sizek);
        if ((range_basek > basek) && basek)
                return second_sizek;
        state->range_sizek -= (range_basek - state->range_startk);
        range_sizek = ALIGN(state->range_sizek, gran_sizek);
@@ -439,22 +443,21 @@ range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
        }
        state->range_sizek = range_sizek;
-        /* try to append some small hole */
+        /* Try to append some small hole: */
        range0_basek = state->range_startk;
        range0_sizek = ALIGN(state->range_sizek, chunk_sizek);
-        /* no increase */
+        /* No increase: */
        if (range0_sizek == state->range_sizek) {
-                if (debug_print)
+                Dprintk("rangeX: %016lx - %016lx\n",
-                        printk(KERN_DEBUG "rangeX: %016lx - %016lx\n",
+                        range0_basek<<10,
-                                range0_basek<<10,
+                        (range0_basek + state->range_sizek)<<10);
-                                (range0_basek + state->range_sizek)<<10);
                state->reg = range_to_mtrr(state->reg, range0_basek,
                                state->range_sizek, MTRR_TYPE_WRBACK);
                return 0;
        }
-        /* only cut back, when it is not the last */
+        /* Only cut back when it is not the last: */
        if (sizek) {
                while (range0_basek + range0_sizek > (basek + sizek)) {
                        if (range0_sizek >= chunk_sizek)
@@ -470,16 +473,16 @@ range_to_mtrr_with_hole(struct var_mtrr_state *state, unsigned long basek,
 second_try:
        range_basek = range0_basek + range0_sizek;
-        /* one hole in the middle */
+        /* One hole in the middle: */
        if (range_basek > basek && range_basek <= (basek + sizek))
                second_sizek = range_basek - basek;
        if (range0_sizek > state->range_sizek) {
-                /* one hole in middle or at end */
+                /* One hole in middle or at the end: */
                hole_sizek = range0_sizek - state->range_sizek - second_sizek;
-                /* hole size should be less than half of range0 size */
+                /* Hole size should be less than half of range0 size: */
                if (hole_sizek >= (range0_sizek >> 1) &&
                    range0_sizek >= chunk_sizek) {
                        range0_sizek -= chunk_sizek;
@@ -491,32 +494,30 @@ second_try:
        }
        if (range0_sizek) {
-                if (debug_print)
+                Dprintk("range0: %016lx - %016lx\n",
-                        printk(KERN_DEBUG "range0: %016lx - %016lx\n",
+                        range0_basek<<10,
-                                range0_basek<<10,
+                        (range0_basek + range0_sizek)<<10);
-                                (range0_basek + range0_sizek)<<10);
                state->reg = range_to_mtrr(state->reg, range0_basek,
                                range0_sizek, MTRR_TYPE_WRBACK);
        }
        if (range0_sizek < state->range_sizek) {
-                /* need to handle left over */
+                /* Need to handle left over range: */
                range_sizek = state->range_sizek - range0_sizek;
-                if (debug_print)
+                Dprintk("range: %016lx - %016lx\n",
-                        printk(KERN_DEBUG "range: %016lx - %016lx\n",
+                         range_basek<<10,
-                                 range_basek<<10,
+                         (range_basek + range_sizek)<<10);
-                                 (range_basek + range_sizek)<<10);
                state->reg = range_to_mtrr(state->reg, range_basek,
                                 range_sizek, MTRR_TYPE_WRBACK);
        }
        if (hole_sizek) {
                hole_basek = range_basek - hole_sizek - second_sizek;
-                if (debug_print)
+                Dprintk("hole: %016lx - %016lx\n",
-                        printk(KERN_DEBUG "hole: %016lx - %016lx\n",
+                         hole_basek<<10,
-                                 hole_basek<<10,
+                         (hole_basek + hole_sizek)<<10);
-                                 (hole_basek + hole_sizek)<<10);
                state->reg = range_to_mtrr(state->reg, hole_basek,
                                 hole_sizek, MTRR_TYPE_UNCACHABLE);
        }
@@ -537,23 +538,23 @@ set_var_mtrr_range(struct var_mtrr_state *state, unsigned long base_pfn,
        basek = base_pfn << (PAGE_SHIFT - 10);
        sizek = size_pfn << (PAGE_SHIFT - 10);
-        /* See if I can merge with the last range */
+        /* See if I can merge with the last range: */
        if ((basek <= 1024) ||
            (state->range_startk + state->range_sizek == basek)) {
                unsigned long endk = basek + sizek;
                state->range_sizek = endk - state->range_startk;
                return;
        }
-        /* Write the range mtrrs */
+        /* Write the range mtrrs: */
        if (state->range_sizek != 0)
                second_sizek = range_to_mtrr_with_hole(state, basek, sizek);
-        /* Allocate an msr */
+        /* Allocate an msr: */
        state->range_startk = basek + second_sizek;
        state->range_sizek  = sizek - second_sizek;
 }
-/* mininum size of mtrr block that can take hole */
+/* Mininum size of mtrr block that can take hole: */
 static u64 mtrr_chunk_size __initdata = (256ULL<<20);
 static int __init parse_mtrr_chunk_size_opt(char *p)
@@ -565,7 +566,7 @@ static int __init parse_mtrr_chunk_size_opt(char *p)
 }
 early_param("mtrr_chunk_size", parse_mtrr_chunk_size_opt);
-/* granity of mtrr of block */
+/* Granularity of mtrr of block: */
 static u64 mtrr_gran_size __initdata;
 static int __init parse_mtrr_gran_size_opt(char *p)
@@ -577,7 +578,7 @@ static int __init parse_mtrr_gran_size_opt(char *p)
 }
 early_param("mtrr_gran_size", parse_mtrr_gran_size_opt);
-static int nr_mtrr_spare_reg __initdata =
+static unsigned long nr_mtrr_spare_reg __initdata =
                                 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT;
 static int __init parse_mtrr_spare_reg(char *arg)
@@ -586,7 +587,6 @@ static int __init parse_mtrr_spare_reg(char *arg)
                nr_mtrr_spare_reg = simple_strtoul(arg, NULL, 0);
        return 0;
 }
 early_param("mtrr_spare_reg_nr", parse_mtrr_spare_reg);
 static int __init
@@ -594,8 +594,8 @@ x86_setup_var_mtrrs(struct res_range *range, int nr_range,
                    u64 chunk_size, u64 gran_size)
 {
        struct var_mtrr_state var_state;
-        int i;
        int num_reg;
+        int i;
        var_state.range_startk  = 0;
        var_state.range_sizek   = 0;
@@ -605,17 +605,18 @@ x86_setup_var_mtrrs(struct res_range *range, int nr_range,
        memset(range_state, 0, sizeof(range_state));
-        /* Write the range etc */
+        /* Write the range: */
-        for (i = 0; i < nr_range; i++)
+        for (i = 0; i < nr_range; i++) {
                set_var_mtrr_range(&var_state, range[i].start,
                                   range[i].end - range[i].start + 1);
+        }
-        /* Write the last range */
+        /* Write the last range: */
        if (var_state.range_sizek != 0)
                range_to_mtrr_with_hole(&var_state, 0, 0);
        num_reg = var_state.reg;
-        /* Clear out the extra MTRR's */
+        /* Clear out the extra MTRR's: */
        while (var_state.reg < num_var_ranges) {
                save_var_mtrr(var_state.reg, 0, 0, 0);
                var_state.reg++;
@@ -625,11 +626,11 @@ x86_setup_var_mtrrs(struct res_range *range, int nr_range,
 }
 struct mtrr_cleanup_result {
-        unsigned long gran_sizek;
+        unsigned long   gran_sizek;
-        unsigned long chunk_sizek;
+        unsigned long   chunk_sizek;
-        unsigned long lose_cover_sizek;
+        unsigned long   lose_cover_sizek;
-        unsigned int num_reg;
+        unsigned int    num_reg;
-        int bad;
+        int             bad;
 };
 /*
@@ -645,10 +646,10 @@ static unsigned long __initdata min_loss_pfn[RANGE_NUM];
 static void __init print_out_mtrr_range_state(void)
 {
-        int i;
        char start_factor = 'K', size_factor = 'K';
        unsigned long start_base, size_base;
        mtrr_type type;
+        int i;
        for (i = 0; i < num_var_ranges; i++) {
@@ -676,10 +677,10 @@ static int __init mtrr_need_cleanup(void)
        int i;
        mtrr_type type;
        unsigned long size;
-        /* extra one for all 0 */
+        /* Extra one for all 0: */
        int num[MTRR_NUM_TYPES + 1];
-        /* check entries number */
+        /* Check entries number: */
        memset(num, 0, sizeof(num));
        for (i = 0; i < num_var_ranges; i++) {
                type = range_state[i].type;
@@ -693,88 +694,86 @@ static int __init mtrr_need_cleanup(void)
                num[type]++;
        }
-        /* check if we got UC entries */
+        /* Check if we got UC entries: */
        if (!num[MTRR_TYPE_UNCACHABLE])
                return 0;
-        /* check if we only had WB and UC */
+        /* Check if we only had WB and UC */
        if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=
-                num_var_ranges - num[MTRR_NUM_TYPES])
+            num_var_ranges - num[MTRR_NUM_TYPES])
                return 0;
        return 1;
 }
 static unsigned long __initdata range_sums;
-static void __init mtrr_calc_range_state(u64 chunk_size, u64 gran_size,
-                                         unsigned long extra_remove_base,
+static void __init
-                                         unsigned long extra_remove_size,
+mtrr_calc_range_state(u64 chunk_size, u64 gran_size,
-                                         int i)
+                      unsigned long x_remove_base,
+                      unsigned long x_remove_size, int i)
 {
-        int num_reg;
        static struct res_range range_new[RANGE_NUM];
-        static int nr_range_new;
        unsigned long range_sums_new;
+        static int nr_range_new;
+        int num_reg;
-        /* convert ranges to var ranges state */
+        /* Convert ranges to var ranges state: */
-        num_reg = x86_setup_var_mtrrs(range, nr_range,
+        num_reg = x86_setup_var_mtrrs(range, nr_range, chunk_size, gran_size);
-                                                chunk_size, gran_size);
-        /* we got new setting in range_state, check it */
+        /* We got new setting in range_state, check it: */
        memset(range_new, 0, sizeof(range_new));
        nr_range_new = x86_get_mtrr_mem_range(range_new, 0,
-                                extra_remove_base, extra_remove_size);
+                                x_remove_base, x_remove_size);
        range_sums_new = sum_ranges(range_new, nr_range_new);
        result[i].chunk_sizek = chunk_size >> 10;
        result[i].gran_sizek = gran_size >> 10;
        result[i].num_reg = num_reg;
        if (range_sums < range_sums_new) {
-                result[i].lose_cover_sizek =
+                result[i].lose_cover_sizek = (range_sums_new - range_sums) << PSHIFT;
-                        (range_sums_new - range_sums) << PSHIFT;
                result[i].bad = 1;
-        } else
+        } else {
-                result[i].lose_cover_sizek =
+                result[i].lose_cover_sizek = (range_sums - range_sums_new) << PSHIFT;
-                        (range_sums - range_sums_new) << PSHIFT;
+        }
-        /* double check it */
+        /* Double check it: */
        if (!result[i].bad && !result[i].lose_cover_sizek) {
-                if (nr_range_new != nr_range ||
+                if (nr_range_new != nr_range || memcmp(range, range_new, sizeof(range)))
-                        memcmp(range, range_new, sizeof(range)))
+                        result[i].bad = 1;
-                                result[i].bad = 1;
        }
-        if (!result[i].bad && (range_sums - range_sums_new <
+        if (!result[i].bad && (range_sums - range_sums_new < min_loss_pfn[num_reg]))
-                                min_loss_pfn[num_reg])) {
+                min_loss_pfn[num_reg] = range_sums - range_sums_new;
-                min_loss_pfn[num_reg] =
-                        range_sums - range_sums_new;
-        }
 }
 static void __init mtrr_print_out_one_result(int i)
 {
-        char gran_factor, chunk_factor, lose_factor;
        unsigned long gran_base, chunk_base, lose_base;
+        char gran_factor, chunk_factor, lose_factor;
        gran_base = to_size_factor(result[i].gran_sizek, &gran_factor),
        chunk_base = to_size_factor(result[i].chunk_sizek, &chunk_factor),
        lose_base = to_size_factor(result[i].lose_cover_sizek, &lose_factor),
-        printk(KERN_INFO "%sgran_size: %ld%c \tchunk_size: %ld%c \t",
-                        result[i].bad ? "*BAD*" : " ",
+        pr_info("%sgran_size: %ld%c \tchunk_size: %ld%c \t",
-                        gran_base, gran_factor, chunk_base, chunk_factor);
+                result[i].bad ? "*BAD*" : " ",
-        printk(KERN_CONT "num_reg: %d  \tlose cover RAM: %s%ld%c\n",
+                gran_base, gran_factor, chunk_base, chunk_factor);
-                        result[i].num_reg, result[i].bad ? "-" : "",
+        pr_cont("num_reg: %d  \tlose cover RAM: %s%ld%c\n",
-                        lose_base, lose_factor);
+                result[i].num_reg, result[i].bad ? "-" : "",
+                lose_base, lose_factor);
 }
 static int __init mtrr_search_optimal_index(void)
 {
-        int i;
        int num_reg_good;
        int index_good;
+        int i;
        if (nr_mtrr_spare_reg >= num_var_ranges)
                nr_mtrr_spare_reg = num_var_ranges - 1;
        num_reg_good = -1;
        for (i = num_var_ranges - nr_mtrr_spare_reg; i > 0; i--) {
                if (!min_loss_pfn[i])
@@ -796,24 +795,24 @@ static int __init mtrr_search_optimal_index(void)
        return index_good;
 }
 int __init mtrr_cleanup(unsigned address_bits)
 {
-        unsigned long extra_remove_base, extra_remove_size;
+        unsigned long x_remove_base, x_remove_size;
        unsigned long base, size, def, dummy;
-        mtrr_type type;
        u64 chunk_size, gran_size;
+        mtrr_type type;
        int index_good;
        int i;
        if (!is_cpu(INTEL) || enable_mtrr_cleanup < 1)
                return 0;
        rdmsr(MSR_MTRRdefType, def, dummy);
        def &= 0xff;
        if (def != MTRR_TYPE_UNCACHABLE)
                return 0;
-        /* get it and store it aside */
+        /* Get it and store it aside: */
        memset(range_state, 0, sizeof(range_state));
        for (i = 0; i < num_var_ranges; i++) {
                mtrr_if->get(i, &base, &size, &type);
@@ -822,29 +821,28 @@ int __init mtrr_cleanup(unsigned address_bits)
                range_state[i].type = type;
        }
-        /* check if we need handle it and can handle it */
+        /* Check if we need handle it and can handle it: */
        if (!mtrr_need_cleanup())
                return 0;
-        /* print original var MTRRs at first, for debugging: */
+        /* Print original var MTRRs at first, for debugging: */
        printk(KERN_DEBUG "original variable MTRRs\n");
        print_out_mtrr_range_state();
        memset(range, 0, sizeof(range));
-        extra_remove_size = 0;
+        x_remove_size = 0;
-        extra_remove_base = 1 << (32 - PAGE_SHIFT);
+        x_remove_base = 1 << (32 - PAGE_SHIFT);
        if (mtrr_tom2)
-                extra_remove_size =
+                x_remove_size = (mtrr_tom2 >> PAGE_SHIFT) - x_remove_base;
-                        (mtrr_tom2 >> PAGE_SHIFT) - extra_remove_base;
-        nr_range = x86_get_mtrr_mem_range(range, 0, extra_remove_base,
+        nr_range = x86_get_mtrr_mem_range(range, 0, x_remove_base, x_remove_size);
-                                          extra_remove_size);
        /*
-         * [0, 1M) should always be coverred by var mtrr with WB
+         * [0, 1M) should always be covered by var mtrr with WB
-         * and fixed mtrrs should take effective before var mtrr for it
+         * and fixed mtrrs should take effect before var mtrr for it:
         */
        nr_range = add_range_with_merge(range, nr_range, 0,
                                        (1ULL<<(20 - PAGE_SHIFT)) - 1);
-        /* sort the ranges */
+        /* Sort the ranges: */
        sort(range, nr_range, sizeof(struct res_range), cmp_range, NULL);
        range_sums = sum_ranges(range, nr_range);
@@ -854,7 +852,7 @@ int __init mtrr_cleanup(unsigned address_bits)
        if (mtrr_chunk_size && mtrr_gran_size) {
                i = 0;
                mtrr_calc_range_state(mtrr_chunk_size, mtrr_gran_size,
-                                      extra_remove_base, extra_remove_size, i);
+                                      x_remove_base, x_remove_size, i);
                mtrr_print_out_one_result(i);
@@ -880,7 +878,7 @@ int __init mtrr_cleanup(unsigned address_bits)
                                continue;
                        mtrr_calc_range_state(chunk_size, gran_size,
-                                      extra_remove_base, extra_remove_size, i);
+                                      x_remove_base, x_remove_size, i);
                        if (debug_print) {
                                mtrr_print_out_one_result(i);
                                printk(KERN_INFO "\n");
@@ -890,7 +888,7 @@ int __init mtrr_cleanup(unsigned address_bits)
                }
        }
-        /* try to find the optimal index */
+        /* Try to find the optimal index: */
        index_good = mtrr_search_optimal_index();
        if (index_good != -1) {
@@ -898,7 +896,7 @@ int __init mtrr_cleanup(unsigned address_bits)
                i = index_good;
                mtrr_print_out_one_result(i);
-                /* convert ranges to var ranges state */
+                /* Convert ranges to var ranges state: */
                chunk_size = result[i].chunk_sizek;
                chunk_size <<= 10;
                gran_size = result[i].gran_sizek;
@@ -941,8 +939,8 @@ early_param("disable_mtrr_trim", disable_mtrr_trim_setup);
 * Note this won't check if the MTRRs < 4GB where the magic bit doesn't
 * apply to are wrong, but so far we don't know of any such case in the wild.
 */
-#define Tom2Enabled (1U << 21)
+#define Tom2Enabled             (1U << 21)
-#define Tom2ForceMemTypeWB (1U << 22)
+#define Tom2ForceMemTypeWB      (1U << 22)
 int __init amd_special_default_mtrr(void)
 {
@@ -952,7 +950,7 @@ int __init amd_special_default_mtrr(void)
                return 0;
        if (boot_cpu_data.x86 < 0xf || boot_cpu_data.x86 > 0x11)
                return 0;
-        /* In case some hypervisor doesn't pass SYSCFG through */
+        /* In case some hypervisor doesn't pass SYSCFG through: */
        if (rdmsr_safe(MSR_K8_SYSCFG, &l, &h) < 0)
                return 0;
        /*
@@ -965,19 +963,21 @@ int __init amd_special_default_mtrr(void)
        return 0;
 }
-static u64 __init real_trim_memory(unsigned long start_pfn,
+static u64 __init
-                                   unsigned long limit_pfn)
+real_trim_memory(unsigned long start_pfn, unsigned long limit_pfn)
 {
        u64 trim_start, trim_size;
        trim_start = start_pfn;
        trim_start <<= PAGE_SHIFT;
        trim_size = limit_pfn;
        trim_size <<= PAGE_SHIFT;
        trim_size -= trim_start;
-        return e820_update_range(trim_start, trim_size, E820_RAM,
+        return e820_update_range(trim_start, trim_size, E820_RAM, E820_RESERVED);
-                                E820_RESERVED);
 }
 /**
 * mtrr_trim_uncached_memory - trim RAM not covered by MTRRs
 * @end_pfn: ending page frame number
@@ -985,7 +985,7 @@ static u64 __init real_trim_memory(unsigned long start_pfn,
 * Some buggy BIOSes don't setup the MTRRs properly for systems with certain
 * memory configurations.  This routine checks that the highest MTRR matches
 * the end of memory, to make sure the MTRRs having a write back type cover
- * all of the memory the kernel is intending to use. If not, it'll trim any
+ * all of the memory the kernel is intending to use.  If not, it'll trim any
 * memory off the end by adjusting end_pfn, removing it from the kernel's
 * allocation pools, warning the user with an obnoxious message.
 */
@@ -994,21 +994,22 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
        unsigned long i, base, size, highest_pfn = 0, def, dummy;
        mtrr_type type;
        u64 total_trim_size;
        /* extra one for all 0 */
        int num[MTRR_NUM_TYPES + 1];
        /*
         * Make sure we only trim uncachable memory on machines that
         * support the Intel MTRR architecture:
         */
        if (!is_cpu(INTEL) || disable_mtrr_trim)
                return 0;
        rdmsr(MSR_MTRRdefType, def, dummy);
        def &= 0xff;
        if (def != MTRR_TYPE_UNCACHABLE)
                return 0;
-        /* get it and store it aside */
+        /* Get it and store it aside: */
        memset(range_state, 0, sizeof(range_state));
        for (i = 0; i < num_var_ranges; i++) {
                mtrr_if->get(i, &base, &size, &type);
@@ -1017,7 +1018,7 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
                range_state[i].type = type;
        }
-        /* Find highest cached pfn */
+        /* Find highest cached pfn: */
        for (i = 0; i < num_var_ranges; i++) {
                type = range_state[i].type;
                if (type != MTRR_TYPE_WRBACK)
@@ -1028,13 +1029,13 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
                        highest_pfn = base + size;
        }
-        /* kvm/qemu doesn't have mtrr set right, don't trim them all */
+        /* kvm/qemu doesn't have mtrr set right, don't trim them all: */
        if (!highest_pfn) {
                printk(KERN_INFO "CPU MTRRs all blank - virtualized system.\n");
                return 0;
        }
-        /* check entries number */
+        /* Check entries number: */
        memset(num, 0, sizeof(num));
        for (i = 0; i < num_var_ranges; i++) {
                type = range_state[i].type;
@@ -1046,11 +1047,11 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
                num[type]++;
        }
-        /* no entry for WB? */
+        /* No entry for WB? */
        if (!num[MTRR_TYPE_WRBACK])
                return 0;
-        /* check if we only had WB and UC */
+        /* Check if we only had WB and UC: */
        if (num[MTRR_TYPE_WRBACK] + num[MTRR_TYPE_UNCACHABLE] !=
                num_var_ranges - num[MTRR_NUM_TYPES])
                return 0;
@@ -1066,31 +1067,31 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
        }
        nr_range = x86_get_mtrr_mem_range(range, nr_range, 0, 0);
+        /* Check the head: */
        total_trim_size = 0;
-        /* check the head */
        if (range[0].start)
                total_trim_size += real_trim_memory(0, range[0].start);
-        /* check the holes */
+        /* Check the holes: */
        for (i = 0; i < nr_range - 1; i++) {
                if (range[i].end + 1 < range[i+1].start)
                        total_trim_size += real_trim_memory(range[i].end + 1,
                                                            range[i+1].start);
        }
-        /* check the top */
+        /* Check the top: */
        i = nr_range - 1;
        if (range[i].end + 1 < end_pfn)
                total_trim_size += real_trim_memory(range[i].end + 1,
                                                         end_pfn);
        if (total_trim_size) {
-                printk(KERN_WARNING "WARNING: BIOS bug: CPU MTRRs don't cover"
+                pr_warning("WARNING: BIOS bug: CPU MTRRs don't cover all of memory, losing %lluMB of RAM.\n", total_trim_size >> 20);
-                        " all of memory, losing %lluMB of RAM.\n",
-                        total_trim_size >> 20);
                if (!changed_by_mtrr_cleanup)
                        WARN_ON(1);
-                printk(KERN_INFO "update e820 for mtrr\n");
+                pr_info("update e820 for mtrr\n");
                update_e820();
                return 1;
@@ -1098,4 +1099,3 @@ int __init mtrr_trim_uncached_memory(unsigned long end_pfn)
        return 0;
 }
diff --git a/arch/x86/kernel/cpu/mtrr/cyrix.c b/arch/x86/kernel/cpu/mtrr/cyrix.c
index ff14c320040c..228d982ce09c 100644
--- a/arch/x86/kernel/cpu/mtrr/cyrix.c
+++ b/arch/x86/kernel/cpu/mtrr/cyrix.c
@@ -1,38 +1,40 @@
 #include <linux/init.h>
+#include <linux/io.h>
 #include <linux/mm.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-#include <asm/io.h>
 #include <asm/processor-cyrix.h>
 #include <asm/processor-flags.h>
+#include <asm/mtrr.h>
+#include <asm/msr.h>
 #include "mtrr.h"
 static void
 cyrix_get_arr(unsigned int reg, unsigned long *base,
              unsigned long *size, mtrr_type * type)
 {
-        unsigned long flags;
        unsigned char arr, ccr3, rcr, shift;
+        unsigned long flags;
        arr = CX86_ARR_BASE + (reg << 1) + reg; /* avoid multiplication by 3 */
-        /* Save flags and disable interrupts */
        local_irq_save(flags);
        ccr3 = getCx86(CX86_CCR3);
        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);       /* enable MAPEN */
-        ((unsigned char *) base)[3] = getCx86(arr);
+        ((unsigned char *)base)[3] = getCx86(arr);
-        ((unsigned char *) base)[2] = getCx86(arr + 1);
+        ((unsigned char *)base)[2] = getCx86(arr + 1);
-        ((unsigned char *) base)[1] = getCx86(arr + 2);
+        ((unsigned char *)base)[1] = getCx86(arr + 2);
        rcr = getCx86(CX86_RCR_BASE + reg);
-        setCx86(CX86_CCR3, ccr3);       /* disable MAPEN */
+        setCx86(CX86_CCR3, ccr3);                       /* disable MAPEN */
-        /* Enable interrupts if it was enabled previously */
        local_irq_restore(flags);
        shift = ((unsigned char *) base)[1] & 0x0f;
        *base >>= PAGE_SHIFT;
-        /* Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
+        /*
+         * Power of two, at least 4K on ARR0-ARR6, 256K on ARR7
         * Note: shift==0xf means 4G, this is unsupported.
         */
        if (shift)
@@ -76,17 +78,20 @@ cyrix_get_arr(unsigned int reg, unsigned long *base,
        }
 }
+/*
+ * cyrix_get_free_region - get a free ARR.
+ *
+ * @base: the starting (base) address of the region.
+ * @size: the size (in bytes) of the region.
+ *
+ * Returns: the index of the region on success, else -1 on error.
+*/
 static int
 cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
-/*  [SUMMARY] Get a free ARR.
-    <base> The starting (base) address of the region.
-    <size> The size (in bytes) of the region.
-    [RETURNS] The index of the region on success, else -1 on error.
-*/
 {
-        int i;
-        mtrr_type ltype;
        unsigned long lbase, lsize;
+        mtrr_type ltype;
+        int i;
        switch (replace_reg) {
        case 7:
@@ -107,14 +112,17 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
                cyrix_get_arr(7, &lbase, &lsize, &ltype);
                if (lsize == 0)
                        return 7;
-                /*  Else try ARR0-ARR6 first  */
+                /* Else try ARR0-ARR6 first  */
        } else {
                for (i = 0; i < 7; i++) {
                        cyrix_get_arr(i, &lbase, &lsize, &ltype);
                        if (lsize == 0)
                                return i;
                }
-                /* ARR0-ARR6 isn't free, try ARR7 but its size must be at least 256K */
+                /*
+                 * ARR0-ARR6 isn't free
+                 * try ARR7 but its size must be at least 256K
+                 */
                cyrix_get_arr(i, &lbase, &lsize, &ltype);
                if ((lsize == 0) && (size >= 0x40))
                        return i;
@@ -122,21 +130,22 @@ cyrix_get_free_region(unsigned long base, unsigned long size, int replace_reg)
        return -ENOSPC;
 }
-static u32 cr4 = 0;
+static u32 cr4, ccr3;
-static u32 ccr3;
 static void prepare_set(void)
 {
        u32 cr0;
        /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
-        if ( cpu_has_pge ) {
+        if (cpu_has_pge) {
                cr4 = read_cr4();
                write_cr4(cr4 & ~X86_CR4_PGE);
        }
-        /*  Disable and flush caches. Note that wbinvd flushes the TLBs as
+        /*
-            a side-effect  */
+         * Disable and flush caches.
+         * Note that wbinvd flushes the TLBs as a side-effect
+         */
        cr0 = read_cr0() | X86_CR0_CD;
        wbinvd();
        write_cr0(cr0);
@@ -147,22 +156,21 @@ static void prepare_set(void)
        /* Cyrix ARRs - everything else was excluded at the top */
        setCx86(CX86_CCR3, (ccr3 & 0x0f) | 0x10);
 }
 static void post_set(void)
 {
-        /*  Flush caches and TLBs  */
+        /* Flush caches and TLBs */
        wbinvd();
        /* Cyrix ARRs - everything else was excluded at the top */
        setCx86(CX86_CCR3, ccr3);
-                
-        /*  Enable caches  */
+        /* Enable caches */
        write_cr0(read_cr0() & 0xbfffffff);
-        /*  Restore value of CR4  */
+        /* Restore value of CR4 */
-        if ( cpu_has_pge )
+        if (cpu_has_pge)
                write_cr4(cr4);
 }
@@ -178,7 +186,8 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base,
                size >>= 6;
        size &= 0x7fff;         /* make sure arr_size <= 14 */
-        for (arr_size = 0; size; arr_size++, size >>= 1) ;
+        for (arr_size = 0; size; arr_size++, size >>= 1)
+                ;
        if (reg < 7) {
                switch (type) {
@@ -215,18 +224,18 @@ static void cyrix_set_arr(unsigned int reg, unsigned long base,
        prepare_set();
        base <<= PAGE_SHIFT;
-        setCx86(arr, ((unsigned char *) &base)[3]);
+        setCx86(arr + 0,  ((unsigned char *)&base)[3]);
-        setCx86(arr + 1, ((unsigned char *) &base)[2]);
+        setCx86(arr + 1,  ((unsigned char *)&base)[2]);
-        setCx86(arr + 2, (((unsigned char *) &base)[1]) | arr_size);
+        setCx86(arr + 2, (((unsigned char *)&base)[1]) | arr_size);
        setCx86(CX86_RCR_BASE + reg, arr_type);
        post_set();
 }
 typedef struct {
-        unsigned long base;
+        unsigned long   base;
-        unsigned long size;
+        unsigned long   size;
-        mtrr_type type;
+        mtrr_type       type;
 } arr_state_t;
 static arr_state_t arr_state[8] = {
@@ -247,16 +256,17 @@ static void cyrix_set_all(void)
                setCx86(CX86_CCR0 + i, ccr_state[i]);
        for (; i < 7; i++)
                setCx86(CX86_CCR4 + i, ccr_state[i]);
-        for (i = 0; i < 8; i++)
-                cyrix_set_arr(i, arr_state[i].base, 
+        for (i = 0; i < 8; i++) {
+                cyrix_set_arr(i, arr_state[i].base,
                              arr_state[i].size, arr_state[i].type);
+        }
        post_set();
 }
 static struct mtrr_ops cyrix_mtrr_ops = {
        .vendor            = X86_VENDOR_CYRIX,
-//      .init              = cyrix_arr_init,
        .set_all           = cyrix_set_all,
        .set               = cyrix_set_arr,
        .get               = cyrix_get_arr,
@@ -270,5 +280,3 @@ int __init cyrix_init_mtrr(void)
        set_mtrr_ops(&cyrix_mtrr_ops);
        return 0;
 }
-//arch_initcall(cyrix_init_mtrr);
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c b/arch/x86/kernel/cpu/mtrr/generic.c
index 0543f69f0b27..55da0c5f68dd 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -1,28 +1,34 @@
-/* This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
+/*
-   because MTRRs can span upto 40 bits (36bits on most modern x86) */ 
+ * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong
+ * because MTRRs can span upto 40 bits (36bits on most modern x86)
+ */
+#define DEBUG
+#include <linux/module.h>
 #include <linux/init.h>
 #include <linux/slab.h>
+#include <linux/io.h>
 #include <linux/mm.h>
-#include <linux/module.h>
-#include <asm/io.h>
-#include <asm/mtrr.h>
-#include <asm/msr.h>
-#include <asm/system.h>
-#include <asm/cpufeature.h>
 #include <asm/processor-flags.h>
+#include <asm/cpufeature.h>
 #include <asm/tlbflush.h>
+#include <asm/system.h>
+#include <asm/mtrr.h>
+#include <asm/msr.h>
 #include <asm/pat.h>
 #include "mtrr.h"
 struct fixed_range_block {
-        int base_msr; /* start address of an MTRR block */
+        int base_msr;           /* start address of an MTRR block */
-        int ranges;   /* number of MTRRs in this block  */
+        int ranges;             /* number of MTRRs in this block  */
 };
 static struct fixed_range_block fixed_range_blocks[] = {
-        { MSR_MTRRfix64K_00000, 1 }, /* one  64k MTRR  */
+        { MSR_MTRRfix64K_00000, 1 }, /* one   64k MTRR  */
-        { MSR_MTRRfix16K_80000, 2 }, /* two  16k MTRRs */
+        { MSR_MTRRfix16K_80000, 2 }, /* two   16k MTRRs */
-        { MSR_MTRRfix4K_C0000,  8 }, /* eight 4k MTRRs */
+        { MSR_MTRRfix4K_C0000,  8 }, /* eight  4k MTRRs */
        {}
 };
@@ -30,10 +36,10 @@ static unsigned long smp_changes_mask;
 static int mtrr_state_set;
 u64 mtrr_tom2;
-struct mtrr_state_type mtrr_state = {};
+struct mtrr_state_type mtrr_state;
 EXPORT_SYMBOL_GPL(mtrr_state);
-/**
+/*
 * BIOS is expected to clear MtrrFixDramModEn bit, see for example
 * "BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD
 * Opteron Processors" (26094 Rev. 3.30 February 2006), section
@@ -104,9 +110,8 @@ u8 mtrr_type_lookup(u64 start, u64 end)
         * Look of multiple ranges matching this address and pick type
         * as per MTRR precedence
         */
-        if (!(mtrr_state.enabled & 2)) {
+        if (!(mtrr_state.enabled & 2))
                return mtrr_state.def_type;
-        }
        prev_match = 0xFF;
        for (i = 0; i < num_var_ranges; ++i) {
@@ -125,9 +130,8 @@ u8 mtrr_type_lookup(u64 start, u64 end)
                if (start_state != end_state)
                        return 0xFE;
-                if ((start & mask) != (base & mask)) {
+                if ((start & mask) != (base & mask))
                        continue;
-                }
                curr_match = mtrr_state.var_ranges[i].base_lo & 0xff;
                if (prev_match == 0xFF) {
@@ -148,9 +152,8 @@ u8 mtrr_type_lookup(u64 start, u64 end)
                        curr_match = MTRR_TYPE_WRTHROUGH;
                }
-                if (prev_match != curr_match) {
+                if (prev_match != curr_match)
                        return MTRR_TYPE_UNCACHABLE;
-                }
        }
        if (mtrr_tom2) {
@@ -164,7 +167,7 @@ u8 mtrr_type_lookup(u64 start, u64 end)
        return mtrr_state.def_type;
 }
-/*  Get the MSR pair relating to a var range  */
+/* Get the MSR pair relating to a var range */
 static void
 get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
 {
@@ -172,7 +175,7 @@ get_mtrr_var_range(unsigned int index, struct mtrr_var_range *vr)
        rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi);
 }
-/*  fill the MSR pair relating to a var range  */
+/* Fill the MSR pair relating to a var range */
 void fill_mtrr_var_range(unsigned int index,
                u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi)
 {
@@ -186,10 +189,9 @@ void fill_mtrr_var_range(unsigned int index,
        vr[index].mask_hi = mask_hi;
 }
-static void
+static void get_fixed_ranges(mtrr_type *frs)
-get_fixed_ranges(mtrr_type * frs)
 {
-        unsigned int *p = (unsigned int *) frs;
+        unsigned int *p = (unsigned int *)frs;
        int i;
        k8_check_syscfg_dram_mod_en();
@@ -217,22 +219,22 @@ static void __init print_fixed_last(void)
        if (!last_fixed_end)
                return;
-        printk(KERN_DEBUG "  %05X-%05X %s\n", last_fixed_start,
+        pr_debug("  %05X-%05X %s\n", last_fixed_start,
-                last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
+                 last_fixed_end - 1, mtrr_attrib_to_str(last_fixed_type));
        last_fixed_end = 0;
 }
 static void __init update_fixed_last(unsigned base, unsigned end,
-                                       mtrr_type type)
+                                     mtrr_type type)
 {
        last_fixed_start = base;
        last_fixed_end = end;
        last_fixed_type = type;
 }
-static void __init print_fixed(unsigned base, unsigned step,
+static void __init
-                               const mtrr_type *types)
+print_fixed(unsigned base, unsigned step, const mtrr_type *types)
 {
        unsigned i;
@@ -259,54 +261,55 @@ static void __init print_mtrr_state(void)
        unsigned int i;
        int high_width;
-        printk(KERN_DEBUG "MTRR default type: %s\n",
+        pr_debug("MTRR default type: %s\n",
-                         mtrr_attrib_to_str(mtrr_state.def_type));
+                 mtrr_attrib_to_str(mtrr_state.def_type));
        if (mtrr_state.have_fixed) {
-                printk(KERN_DEBUG "MTRR fixed ranges %sabled:\n",
+                pr_debug("MTRR fixed ranges %sabled:\n",
-                       mtrr_state.enabled & 1 ? "en" : "dis");
+                         mtrr_state.enabled & 1 ? "en" : "dis");
                print_fixed(0x00000, 0x10000, mtrr_state.fixed_ranges + 0);
                for (i = 0; i < 2; ++i)
-                        print_fixed(0x80000 + i * 0x20000, 0x04000, mtrr_state.fixed_ranges + (i + 1) * 8);
+                        print_fixed(0x80000 + i * 0x20000, 0x04000,
+                                    mtrr_state.fixed_ranges + (i + 1) * 8);
                for (i = 0; i < 8; ++i)
-                        print_fixed(0xC0000 + i * 0x08000, 0x01000, mtrr_state.fixed_ranges + (i + 3) * 8);
+                        print_fixed(0xC0000 + i * 0x08000, 0x01000,
+                                    mtrr_state.fixed_ranges + (i + 3) * 8);
                /* tail */
                print_fixed_last();
        }
-        printk(KERN_DEBUG "MTRR variable ranges %sabled:\n",
+        pr_debug("MTRR variable ranges %sabled:\n",
-               mtrr_state.enabled & 2 ? "en" : "dis");
+                 mtrr_state.enabled & 2 ? "en" : "dis");
        if (size_or_mask & 0xffffffffUL)
                high_width = ffs(size_or_mask & 0xffffffffUL) - 1;
        else
                high_width = ffs(size_or_mask>>32) + 32 - 1;
        high_width = (high_width - (32 - PAGE_SHIFT) + 3) / 4;
        for (i = 0; i < num_var_ranges; ++i) {
                if (mtrr_state.var_ranges[i].mask_lo & (1 << 11))
-                        printk(KERN_DEBUG "  %u base %0*X%05X000 mask %0*X%05X000 %s\n",
+                        pr_debug("  %u base %0*X%05X000 mask %0*X%05X000 %s\n",
-                               i,
+                                 i,
-                               high_width,
+                                 high_width,
-                               mtrr_state.var_ranges[i].base_hi,
+                                 mtrr_state.var_ranges[i].base_hi,
-                               mtrr_state.var_ranges[i].base_lo >> 12,
+                                 mtrr_state.var_ranges[i].base_lo >> 12,
-                               high_width,
+                                 high_width,
-                               mtrr_state.var_ranges[i].mask_hi,
+                                 mtrr_state.var_ranges[i].mask_hi,
-                               mtrr_state.var_ranges[i].mask_lo >> 12,
+                                 mtrr_state.var_ranges[i].mask_lo >> 12,
-                               mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
+                                 mtrr_attrib_to_str(mtrr_state.var_ranges[i].base_lo & 0xff));
                else
-                        printk(KERN_DEBUG "  %u disabled\n", i);
+                        pr_debug("  %u disabled\n", i);
-        }
-        if (mtrr_tom2) {
-                printk(KERN_DEBUG "TOM2: %016llx aka %lldM\n",
-                                  mtrr_tom2, mtrr_tom2>>20);
        }
+        if (mtrr_tom2)
+                pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
 }
-/*  Grab all of the MTRR state for this CPU into *state  */
+/* Grab all of the MTRR state for this CPU into *state */
 void __init get_mtrr_state(void)
 {
-        unsigned int i;
        struct mtrr_var_range *vrs;
-        unsigned lo, dummy;
        unsigned long flags;
+        unsigned lo, dummy;
+        unsigned int i;
        vrs = mtrr_state.var_ranges;
@@ -324,6 +327,7 @@ void __init get_mtrr_state(void)
        if (amd_special_default_mtrr()) {
                unsigned low, high;
                /* TOP_MEM2 */
                rdmsr(MSR_K8_TOP_MEM2, low, high);
                mtrr_tom2 = high;
@@ -344,10 +348,9 @@ void __init get_mtrr_state(void)
        post_set();
        local_irq_restore(flags);
 }
-/*  Some BIOS's are fucked and don't set all MTRRs the same!  */
+/* Some BIOS's are messed up and don't set all MTRRs the same! */
 void __init mtrr_state_warn(void)
 {
        unsigned long mask = smp_changes_mask;
@@ -355,28 +358,33 @@ void __init mtrr_state_warn(void)
        if (!mask)
                return;
        if (mask & MTRR_CHANGE_MASK_FIXED)
-                printk(KERN_WARNING "mtrr: your CPUs had inconsistent fixed MTRR settings\n");
+                pr_warning("mtrr: your CPUs had inconsistent fixed MTRR settings\n");
        if (mask & MTRR_CHANGE_MASK_VARIABLE)
-                printk(KERN_WARNING "mtrr: your CPUs had inconsistent variable MTRR settings\n");
+                pr_warning("mtrr: your CPUs had inconsistent variable MTRR settings\n");
        if (mask & MTRR_CHANGE_MASK_DEFTYPE)
-                printk(KERN_WARNING "mtrr: your CPUs had inconsistent MTRRdefType settings\n");
+                pr_warning("mtrr: your CPUs had inconsistent MTRRdefType settings\n");
        printk(KERN_INFO "mtrr: probably your BIOS does not setup all CPUs.\n");
        printk(KERN_INFO "mtrr: corrected configuration.\n");
 }
-/* Doesn't attempt to pass an error out to MTRR users
+/*
-   because it's quite complicated in some cases and probably not
+ * Doesn't attempt to pass an error out to MTRR users
-   worth it because the best error handling is to ignore it. */
+ * because it's quite complicated in some cases and probably not
+ * worth it because the best error handling is to ignore it.
+ */
 void mtrr_wrmsr(unsigned msr, unsigned a, unsigned b)
 {
-        if (wrmsr_safe(msr, a, b) < 0)
+        if (wrmsr_safe(msr, a, b) < 0) {
                printk(KERN_ERR
                        "MTRR: CPU %u: Writing MSR %x to %x:%x failed\n",
                        smp_processor_id(), msr, a, b);
+        }
 }
 /**
- * set_fixed_range - checks & updates a fixed-range MTRR if it differs from the value it should have
+ * set_fixed_range - checks & updates a fixed-range MTRR if it
+ *                   differs from the value it should have
 * @msr: MSR address of the MTTR which should be checked and updated
 * @changed: pointer which indicates whether the MTRR needed to be changed
 * @msrwords: pointer to the MSR values which the MSR should have
@@ -401,20 +409,23 @@ static void set_fixed_range(int msr, bool *changed, unsigned int *msrwords)
 *
 * Returns: The index of the region on success, else negative on error.
 */
-int generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
+int
+generic_get_free_region(unsigned long base, unsigned long size, int replace_reg)
 {
-        int i, max;
-        mtrr_type ltype;
        unsigned long lbase, lsize;
+        mtrr_type ltype;
+        int i, max;
        max = num_var_ranges;
        if (replace_reg >= 0 && replace_reg < max)
                return replace_reg;
        for (i = 0; i < max; ++i) {
                mtrr_if->get(i, &lbase, &lsize, &ltype);
                if (lsize == 0)
                        return i;
        }
        return -ENOSPC;
 }
@@ -434,7 +445,7 @@ static void generic_get_mtrr(unsigned int reg, unsigned long *base,
        rdmsr(MTRRphysMask_MSR(reg), mask_lo, mask_hi);
        if ((mask_lo & 0x800) == 0) {
-                /*  Invalid (i.e. free) range  */
+                /*  Invalid (i.e. free) range */
                *base = 0;
                *size = 0;
                *type = 0;
@@ -471,27 +482,31 @@ out_put_cpu:
 }
 /**
- * set_fixed_ranges - checks & updates the fixed-range MTRRs if they differ from the saved set
+ * set_fixed_ranges - checks & updates the fixed-range MTRRs if they
+ *                    differ from the saved set
 * @frs: pointer to fixed-range MTRR values, saved by get_fixed_ranges()
 */
-static int set_fixed_ranges(mtrr_type * frs)
+static int set_fixed_ranges(mtrr_type *frs)
 {
-        unsigned long long *saved = (unsigned long long *) frs;
+        unsigned long long *saved = (unsigned long long *)frs;
        bool changed = false;
-        int block=-1, range;
+        int block = -1, range;
        k8_check_syscfg_dram_mod_en();
-        while (fixed_range_blocks[++block].ranges)
+        while (fixed_range_blocks[++block].ranges) {
-            for (range=0; range < fixed_range_blocks[block].ranges; range++)
+                for (range = 0; range < fixed_range_blocks[block].ranges; range++)
-                set_fixed_range(fixed_range_blocks[block].base_msr + range,
+                        set_fixed_range(fixed_range_blocks[block].base_msr + range,
-                    &changed, (unsigned int *) saved++);
+                                        &changed, (unsigned int *)saved++);
+        }
        return changed;
 }
-/*  Set the MSR pair relating to a var range. Returns TRUE if
+/*
-    changes are made  */
+ * Set the MSR pair relating to a var range.
+ * Returns true if changes are made.
+ */
 static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
 {
        unsigned int lo, hi;
@@ -501,6 +516,7 @@ static bool set_mtrr_var_ranges(unsigned int index, struct mtrr_var_range *vr)
        if ((vr->base_lo & 0xfffff0ffUL) != (lo & 0xfffff0ffUL)
            || (vr->base_hi & (size_and_mask >> (32 - PAGE_SHIFT))) !=
                (hi & (size_and_mask >> (32 - PAGE_SHIFT)))) {
                mtrr_wrmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi);
                changed = true;
        }
@@ -526,21 +542,26 @@ static u32 deftype_lo, deftype_hi;
 */
 static unsigned long set_mtrr_state(void)
 {
-        unsigned int i;
        unsigned long change_mask = 0;
+        unsigned int i;
-        for (i = 0; i < num_var_ranges; i++)
+        for (i = 0; i < num_var_ranges; i++) {
                if (set_mtrr_var_ranges(i, &mtrr_state.var_ranges[i]))
                        change_mask |= MTRR_CHANGE_MASK_VARIABLE;
+        }
        if (mtrr_state.have_fixed && set_fixed_ranges(mtrr_state.fixed_ranges))
                change_mask |= MTRR_CHANGE_MASK_FIXED;
-        /*  Set_mtrr_restore restores the old value of MTRRdefType,
+        /*
-           so to set it we fiddle with the saved value  */
+         * Set_mtrr_restore restores the old value of MTRRdefType,
+         * so to set it we fiddle with the saved value:
+         */
        if ((deftype_lo & 0xff) != mtrr_state.def_type
            || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
-                deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type | (mtrr_state.enabled << 10);
+                deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
+                             (mtrr_state.enabled << 10);
                change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
        }
@@ -548,33 +569,36 @@ static unsigned long set_mtrr_state(void)
 }
-static unsigned long cr4 = 0;
+static unsigned long cr4;
 static DEFINE_SPINLOCK(set_atomicity_lock);
 /*
- * Since we are disabling the cache don't allow any interrupts - they
+ * Since we are disabling the cache don't allow any interrupts,
- * would run extremely slow and would only increase the pain.  The caller must
+ * they would run extremely slow and would only increase the pain.
- * ensure that local interrupts are disabled and are reenabled after post_set()
+ *
- * has been called.
+ * The caller must ensure that local interrupts are disabled and
+ * are reenabled after post_set() has been called.
 */
 static void prepare_set(void) __acquires(set_atomicity_lock)
 {
        unsigned long cr0;
-        /*  Note that this is not ideal, since the cache is only flushed/disabled
+        /*
-           for this CPU while the MTRRs are changed, but changing this requires
+         * Note that this is not ideal
-           more invasive changes to the way the kernel boots  */
+         * since the cache is only flushed/disabled for this CPU while the
+         * MTRRs are changed, but changing this requires more invasive
+         * changes to the way the kernel boots
+         */
        spin_lock(&set_atomicity_lock);
-        /*  Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
+        /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
        cr0 = read_cr0() | X86_CR0_CD;
        write_cr0(cr0);
        wbinvd();
-        /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
+        /* Save value of CR4 and clear Page Global Enable (bit 7) */
-        if ( cpu_has_pge ) {
+        if (cpu_has_pge) {
                cr4 = read_cr4();
                write_cr4(cr4 & ~X86_CR4_PGE);
        }
@@ -582,26 +606,26 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
        /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */
        __flush_tlb();
-        /*  Save MTRR state */
+        /* Save MTRR state */
        rdmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
-        /*  Disable MTRRs, and set the default type to uncached  */
+        /* Disable MTRRs, and set the default type to uncached */
        mtrr_wrmsr(MSR_MTRRdefType, deftype_lo & ~0xcff, deftype_hi);
 }
 static void post_set(void) __releases(set_atomicity_lock)
 {
-        /*  Flush TLBs (no need to flush caches - they are disabled)  */
+        /* Flush TLBs (no need to flush caches - they are disabled) */
        __flush_tlb();
        /* Intel (P6) standard MTRRs */
        mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi);
-                
-        /*  Enable caches  */
+        /* Enable caches */
        write_cr0(read_cr0() & 0xbfffffff);
-        /*  Restore value of CR4  */
+        /* Restore value of CR4 */
-        if ( cpu_has_pge )
+        if (cpu_has_pge)
                write_cr4(cr4);
        spin_unlock(&set_atomicity_lock);
 }
@@ -623,24 +647,27 @@ static void generic_set_all(void)
        post_set();
        local_irq_restore(flags);
-        /*  Use the atomic bitops to update the global mask  */
+        /* Use the atomic bitops to update the global mask */
        for (count = 0; count < sizeof mask * 8; ++count) {
                if (mask & 0x01)
                        set_bit(count, &smp_changes_mask);
                mask >>= 1;
        }
-        
 }
+/**
+ * generic_set_mtrr - set variable MTRR register on the local CPU.
+ *
+ * @reg: The register to set.
+ * @base: The base address of the region.
+ * @size: The size of the region. If this is 0 the region is disabled.
+ * @type: The type of the region.
+ *
+ * Returns nothing.
+ */
 static void generic_set_mtrr(unsigned int reg, unsigned long base,
                             unsigned long size, mtrr_type type)
-/*  [SUMMARY] Set variable MTRR register on the local CPU.
-    <reg> The register to set.
-    <base> The base address of the region.
-    <size> The size of the region. If this is 0 the region is disabled.
-    <type> The type of the region.
-    [RETURNS] Nothing.
-*/
 {
        unsigned long flags;
        struct mtrr_var_range *vr;
@@ -651,8 +678,10 @@ static void generic_set_mtrr(unsigned int reg, unsigned long base,
        prepare_set();
        if (size == 0) {
-                /* The invalid bit is kept in the mask, so we simply clear the
+                /*
-                   relevant mask register to disable a range. */
+                 * The invalid bit is kept in the mask, so we simply
+                 * clear the relevant mask register to disable a range.
+                 */
                mtrr_wrmsr(MTRRphysMask_MSR(reg), 0, 0);
                memset(vr, 0, sizeof(struct mtrr_var_range));
        } else {
@@ -669,46 +698,50 @@ static void generic_set_mtrr(unsigned int reg, unsigned long base,
        local_irq_restore(flags);
 }
-int generic_validate_add_page(unsigned long base, unsigned long size, unsigned int type)
+int generic_validate_add_page(unsigned long base, unsigned long size,
+                              unsigned int type)
 {
        unsigned long lbase, last;
-        /*  For Intel PPro stepping <= 7, must be 4 MiB aligned 
+        /*
-            and not touch 0x70000000->0x7003FFFF */
+         * For Intel PPro stepping <= 7
+         * must be 4 MiB aligned and not touch 0x70000000 -> 0x7003FFFF
+         */
        if (is_cpu(INTEL) && boot_cpu_data.x86 == 6 &&
            boot_cpu_data.x86_model == 1 &&
            boot_cpu_data.x86_mask <= 7) {
                if (base & ((1 << (22 - PAGE_SHIFT)) - 1)) {
-                        printk(KERN_WARNING "mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
+                        pr_warning("mtrr: base(0x%lx000) is not 4 MiB aligned\n", base);
                        return -EINVAL;
                }
                if (!(base + size < 0x70000 || base > 0x7003F) &&
                    (type == MTRR_TYPE_WRCOMB
                     || type == MTRR_TYPE_WRBACK)) {
-                        printk(KERN_WARNING "mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
+                        pr_warning("mtrr: writable mtrr between 0x70000000 and 0x7003FFFF may hang the CPU.\n");
                        return -EINVAL;
                }
        }
-        /*  Check upper bits of base and last are equal and lower bits are 0
+        /*
-            for base and 1 for last  */
+         * Check upper bits of base and last are equal and lower bits are 0
+         * for base and 1 for last
+         */
        last = base + size - 1;
        for (lbase = base; !(lbase & 1) && (last & 1);
-             lbase = lbase >> 1, last = last >> 1) ;
+             lbase = lbase >> 1, last = last >> 1)
+                ;
        if (lbase != last) {
-                printk(KERN_WARNING "mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n",
+                pr_warning("mtrr: base(0x%lx000) is not aligned on a size(0x%lx000) boundary\n", base, size);
-                       base, size);
                return -EINVAL;
        }
        return 0;
 }
 static int generic_have_wrcomb(void)
 {
        unsigned long config, dummy;
        rdmsr(MSR_MTRRcap, config, dummy);
-        return (config & (1 << 10));
+        return config & (1 << 10);
 }
 int positive_have_wrcomb(void)
@@ -716,14 +749,15 @@ int positive_have_wrcomb(void)
        return 1;
 }
-/* generic structure...
+/*
+ * Generic structure...
 */
 struct mtrr_ops generic_mtrr_ops = {
-        .use_intel_if      = 1,
+        .use_intel_if           = 1,
-        .set_all           = generic_set_all,
+        .set_all                = generic_set_all,
-        .get               = generic_get_mtrr,
+        .get                    = generic_get_mtrr,
-        .get_free_region   = generic_get_free_region,
+        .get_free_region        = generic_get_free_region,
-        .set               = generic_set_mtrr,
+        .set                    = generic_set_mtrr,
-        .validate_add_page = generic_validate_add_page,
+        .validate_add_page      = generic_validate_add_page,
-        .have_wrcomb       = generic_have_wrcomb,
+        .have_wrcomb            = generic_have_wrcomb,
 };
diff --git a/arch/x86/kernel/cpu/mtrr/if.c b/arch/x86/kernel/cpu/mtrr/if.c
index fb73a52913a4..08b6ea4c62b4 100644
--- a/arch/x86/kernel/cpu/mtrr/if.c
+++ b/arch/x86/kernel/cpu/mtrr/if.c
@@ -1,27 +1,28 @@
-#include <linux/init.h>
-#include <linux/proc_fs.h>
 #include <linux/capability.h>
-#include <linux/ctype.h>
-#include <linux/module.h>
 #include <linux/seq_file.h>
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
+#include <linux/proc_fs.h>
+#include <linux/module.h>
+#include <linux/ctype.h>
+#include <linux/init.h>
 #define LINE_SIZE 80
 #include <asm/mtrr.h>
 #include "mtrr.h"
 #define FILE_FCOUNT(f) (((struct seq_file *)((f)->private_data))->private)
 static const char *const mtrr_strings[MTRR_NUM_TYPES] =
 {
-    "uncachable",               /* 0 */
+        "uncachable",           /* 0 */
-    "write-combining",          /* 1 */
+        "write-combining",      /* 1 */
-    "?",                        /* 2 */
+        "?",                    /* 2 */
-    "?",                        /* 3 */
+        "?",                    /* 3 */
-    "write-through",            /* 4 */
+        "write-through",        /* 4 */
-    "write-protect",            /* 5 */
+        "write-protect",        /* 5 */
-    "write-back",               /* 6 */
+        "write-back",           /* 6 */
 };
 const char *mtrr_attrib_to_str(int x)
@@ -35,8 +36,8 @@ static int
 mtrr_file_add(unsigned long base, unsigned long size,
              unsigned int type, bool increment, struct file *file, int page)
 {
+        unsigned int *fcount = FILE_FCOUNT(file);
        int reg, max;
-        unsigned int *fcount = FILE_FCOUNT(file); 
        max = num_var_ranges;
        if (fcount == NULL) {
@@ -61,8 +62,8 @@ static int
 mtrr_file_del(unsigned long base, unsigned long size,
              struct file *file, int page)
 {
-        int reg;
        unsigned int *fcount = FILE_FCOUNT(file);
+        int reg;
        if (!page) {
                if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1)))
@@ -81,13 +82,14 @@ mtrr_file_del(unsigned long base, unsigned long size,
        return reg;
 }
-/* RED-PEN: seq_file can seek now. this is ignored. */
+/*
+ * seq_file can seek but we ignore it.
+ *
+ * Format of control line:
+ *    "base=%Lx size=%Lx type=%s" or "disable=%d"
+ */
 static ssize_t
 mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
-/*  Format of control line:
-    "base=%Lx size=%Lx type=%s"     OR:
-    "disable=%d"
-*/
 {
        int i, err;
        unsigned long reg;
@@ -100,15 +102,18 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
                return -EPERM;
        if (!len)
                return -EINVAL;
        memset(line, 0, LINE_SIZE);
        if (len > LINE_SIZE)
                len = LINE_SIZE;
        if (copy_from_user(line, buf, len - 1))
                return -EFAULT;
        linelen = strlen(line);
        ptr = line + linelen - 1;
        if (linelen && *ptr == '\n')
                *ptr = '\0';
        if (!strncmp(line, "disable=", 8)) {
                reg = simple_strtoul(line + 8, &ptr, 0);
                err = mtrr_del_page(reg, 0, 0);
@@ -116,28 +121,35 @@ mtrr_write(struct file *file, const char __user *buf, size_t len, loff_t * ppos)
                        return err;
                return len;
        }
        if (strncmp(line, "base=", 5))
                return -EINVAL;
        base = simple_strtoull(line + 5, &ptr, 0);
-        for (; isspace(*ptr); ++ptr) ;
+        for (; isspace(*ptr); ++ptr)
+                ;
        if (strncmp(ptr, "size=", 5))
                return -EINVAL;
        size = simple_strtoull(ptr + 5, &ptr, 0);
        if ((base & 0xfff) || (size & 0xfff))
                return -EINVAL;
-        for (; isspace(*ptr); ++ptr) ;
+        for (; isspace(*ptr); ++ptr)
+                ;
        if (strncmp(ptr, "type=", 5))
                return -EINVAL;
        ptr += 5;
-        for (; isspace(*ptr); ++ptr) ;
+        for (; isspace(*ptr); ++ptr)
+                ;
        for (i = 0; i < MTRR_NUM_TYPES; ++i) {
                if (strcmp(ptr, mtrr_strings[i]))
                        continue;
                base >>= PAGE_SHIFT;
                size >>= PAGE_SHIFT;
-                err =
+                err = mtrr_add_page((unsigned long)base, (unsigned long)size, i, true);
-                    mtrr_add_page((unsigned long) base, (unsigned long) size, i,
-                                  true);
                if (err < 0)
                        return err;
                return len;
@@ -181,7 +193,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
        case MTRRIOC32_SET_PAGE_ENTRY:
        case MTRRIOC32_DEL_PAGE_ENTRY:
        case MTRRIOC32_KILL_PAGE_ENTRY: {
-                struct mtrr_sentry32 __user *s32 = (struct mtrr_sentry32 __user *)__arg;
+                struct mtrr_sentry32 __user *s32;
+                s32 = (struct mtrr_sentry32 __user *)__arg;
                err = get_user(sentry.base, &s32->base);
                err |= get_user(sentry.size, &s32->size);
                err |= get_user(sentry.type, &s32->type);
@@ -191,7 +205,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
        }
        case MTRRIOC32_GET_ENTRY:
        case MTRRIOC32_GET_PAGE_ENTRY: {
-                struct mtrr_gentry32 __user *g32 = (struct mtrr_gentry32 __user *)__arg;
+                struct mtrr_gentry32 __user *g32;
+                g32 = (struct mtrr_gentry32 __user *)__arg;
                err = get_user(gentry.regnum, &g32->regnum);
                err |= get_user(gentry.base, &g32->base);
                err |= get_user(gentry.size, &g32->size);
@@ -314,7 +330,7 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
        if (err)
                return err;
-        switch(cmd) {
+        switch (cmd) {
        case MTRRIOC_GET_ENTRY:
        case MTRRIOC_GET_PAGE_ENTRY:
                if (copy_to_user(arg, &gentry, sizeof gentry))
@@ -323,7 +339,9 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
 #ifdef CONFIG_COMPAT
        case MTRRIOC32_GET_ENTRY:
        case MTRRIOC32_GET_PAGE_ENTRY: {
-                struct mtrr_gentry32 __user *g32 = (struct mtrr_gentry32 __user *)__arg;
+                struct mtrr_gentry32 __user *g32;
+                g32 = (struct mtrr_gentry32 __user *)__arg;
                err = put_user(gentry.base, &g32->base);
                err |= put_user(gentry.size, &g32->size);
                err |= put_user(gentry.regnum, &g32->regnum);
@@ -335,11 +353,10 @@ mtrr_ioctl(struct file *file, unsigned int cmd, unsigned long __arg)
        return err;
 }
-static int
+static int mtrr_close(struct inode *ino, struct file *file)
-mtrr_close(struct inode *ino, struct file *file)
 {
-        int i, max;
        unsigned int *fcount = FILE_FCOUNT(file);
+        int i, max;
        if (fcount != NULL) {
                max = num_var_ranges;
@@ -359,22 +376,22 @@ static int mtrr_seq_show(struct seq_file *seq, void *offset);
 static int mtrr_open(struct inode *inode, struct file *file)
 {
-        if (!mtrr_if) 
+        if (!mtrr_if)
                return -EIO;
-        if (!mtrr_if->get) 
+        if (!mtrr_if->get)
-                return -ENXIO; 
+                return -ENXIO;
        return single_open(file, mtrr_seq_show, NULL);
 }
 static const struct file_operations mtrr_fops = {
-        .owner   = THIS_MODULE,
+        .owner                  = THIS_MODULE,
-        .open    = mtrr_open, 
+        .open                   = mtrr_open,
-        .read    = seq_read,
+        .read                   = seq_read,
-        .llseek  = seq_lseek,
+        .llseek                 = seq_lseek,
-        .write   = mtrr_write,
+        .write                  = mtrr_write,
-        .unlocked_ioctl = mtrr_ioctl,
+        .unlocked_ioctl         = mtrr_ioctl,
-        .compat_ioctl = mtrr_ioctl,
+        .compat_ioctl           = mtrr_ioctl,
-        .release = mtrr_close,
+        .release                = mtrr_close,
 };
 static int mtrr_seq_show(struct seq_file *seq, void *offset)
@@ -388,23 +405,24 @@ static int mtrr_seq_show(struct seq_file *seq, void *offset)
        max = num_var_ranges;
        for (i = 0; i < max; i++) {
                mtrr_if->get(i, &base, &size, &type);
-                if (size == 0)
+                if (size == 0) {
                        mtrr_usage_table[i] = 0;
-                else {
+                        continue;
-                        if (size < (0x100000 >> PAGE_SHIFT)) {
-                                /* less than 1MB */
-                                factor = 'K';
-                                size <<= PAGE_SHIFT - 10;
-                        } else {
-                                factor = 'M';
-                                size >>= 20 - PAGE_SHIFT;
-                        }
-                        /* RED-PEN: base can be > 32bit */ 
-                        len += seq_printf(seq, 
-                                   "reg%02i: base=0x%06lx000 (%5luMB), size=%5lu%cB, count=%d: %s\n",
-                             i, base, base >> (20 - PAGE_SHIFT), size, factor,
-                             mtrr_usage_table[i], mtrr_attrib_to_str(type));
                }
+                if (size < (0x100000 >> PAGE_SHIFT)) {
+                        /* less than 1MB */
+                        factor = 'K';
+                        size <<= PAGE_SHIFT - 10;
+                } else {
+                        factor = 'M';
+                        size >>= 20 - PAGE_SHIFT;
+                }
+                /* Base can be > 32bit */
+                len += seq_printf(seq, "reg%02i: base=0x%06lx000 "
+                        "(%5luMB), size=%5lu%cB, count=%d: %s\n",
+                        i, base, base >> (20 - PAGE_SHIFT), size,
+                        factor, mtrr_usage_table[i],
+                        mtrr_attrib_to_str(type));
        }
        return 0;
 }
@@ -422,6 +440,5 @@ static int __init mtrr_if_init(void)
        proc_create("mtrr", S_IWUSR | S_IRUGO, NULL, &mtrr_fops);
        return 0;
 }
 arch_initcall(mtrr_if_init);
 #endif                  /*  CONFIG_PROC_FS  */
diff --git a/arch/x86/kernel/cpu/mtrr/main.c b/arch/x86/kernel/cpu/mtrr/main.c
index 8fc248b5aeaf..7af0f88a4163 100644
--- a/arch/x86/kernel/cpu/mtrr/main.c
+++ b/arch/x86/kernel/cpu/mtrr/main.c
@@ -25,43 +25,48 @@
    Operating System Writer's Guide" (Intel document number 242692),
    section 11.11.7
-    This was cleaned and made readable by Patrick Mochel <mochel@osdl.org> 
+    This was cleaned and made readable by Patrick Mochel <mochel@osdl.org>
-    on 6-7 March 2002. 
+    on 6-7 March 2002.
-    Source: Intel Architecture Software Developers Manual, Volume 3: 
+    Source: Intel Architecture Software Developers Manual, Volume 3:
    System Programming Guide; Section 9.11. (1997 edition - PPro).
 */
+#define DEBUG
+#include <linux/types.h> /* FIXME: kvm_para.h needs this */
+#include <linux/kvm_para.h>
+#include <linux/uaccess.h>
 #include <linux/module.h>
+#include <linux/mutex.h>
 #include <linux/init.h>
+#include <linux/sort.h>
+#include <linux/cpu.h>
 #include <linux/pci.h>
 #include <linux/smp.h>
-#include <linux/cpu.h>
-#include <linux/mutex.h>
-#include <linux/sort.h>
+#include <asm/processor.h>
 #include <asm/e820.h>
 #include <asm/mtrr.h>
-#include <asm/uaccess.h>
-#include <asm/processor.h>
 #include <asm/msr.h>
-#include <asm/kvm_para.h>
 #include "mtrr.h"
-u32 num_var_ranges = 0;
+u32 num_var_ranges;
 unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
 static DEFINE_MUTEX(mtrr_mutex);
 u64 size_or_mask, size_and_mask;
-static struct mtrr_ops * mtrr_ops[X86_VENDOR_NUM] = {};
+static struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM];
-struct mtrr_ops * mtrr_if = NULL;
+struct mtrr_ops *mtrr_if;
 static void set_mtrr(unsigned int reg, unsigned long base,
                     unsigned long size, mtrr_type type);
-void set_mtrr_ops(struct mtrr_ops * ops)
+void set_mtrr_ops(struct mtrr_ops *ops)
 {
        if (ops->vendor && ops->vendor < X86_VENDOR_NUM)
                mtrr_ops[ops->vendor] = ops;
@@ -72,30 +77,36 @@ static int have_wrcomb(void)
 {
        struct pci_dev *dev;
        u8 rev;
-        
-        if ((dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL)) != NULL) {
+        dev = pci_get_class(PCI_CLASS_BRIDGE_HOST << 8, NULL);
-                /* ServerWorks LE chipsets < rev 6 have problems with write-combining
+        if (dev != NULL) {
-                   Don't allow it and leave room for other chipsets to be tagged */
+                /*
+                 * ServerWorks LE chipsets < rev 6 have problems with
+                 * write-combining. Don't allow it and leave room for other
+                 * chipsets to be tagged
+                 */
                if (dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
                    dev->device == PCI_DEVICE_ID_SERVERWORKS_LE) {
                        pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
                        if (rev <= 5) {
-                                printk(KERN_INFO "mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
+                                pr_info("mtrr: Serverworks LE rev < 6 detected. Write-combining disabled.\n");
                                pci_dev_put(dev);
                                return 0;
                        }
                }
-                /* Intel 450NX errata # 23. Non ascending cacheline evictions to
+                /*
-                   write combining memory may resulting in data corruption */
+                 * Intel 450NX errata # 23. Non ascending cacheline evictions to
+                 * write combining memory may resulting in data corruption
+                 */
                if (dev->vendor == PCI_VENDOR_ID_INTEL &&
                    dev->device == PCI_DEVICE_ID_INTEL_82451NX) {
-                        printk(KERN_INFO "mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
+                        pr_info("mtrr: Intel 450NX MMC detected. Write-combining disabled.\n");
                        pci_dev_put(dev);
                        return 0;
                }
                pci_dev_put(dev);
-        }               
+        }
-        return (mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0);
+        return mtrr_if->have_wrcomb ? mtrr_if->have_wrcomb() : 0;
 }
 /*  This function returns the number of variable MTRRs  */
@@ -103,12 +114,13 @@ static void __init set_num_var_ranges(void)
 {
        unsigned long config = 0, dummy;
-        if (use_intel()) {
+        if (use_intel())
                rdmsr(MSR_MTRRcap, config, dummy);
-        } else if (is_cpu(AMD))
+        else if (is_cpu(AMD))
                config = 2;
        else if (is_cpu(CYRIX) || is_cpu(CENTAUR))
                config = 8;
        num_var_ranges = config & 0xff;
 }
@@ -130,10 +142,12 @@ struct set_mtrr_data {
        mtrr_type       smp_type;
 };
+/**
+ * ipi_handler - Synchronisation handler. Executed by "other" CPUs.
+ *
+ * Returns nothing.
+ */
 static void ipi_handler(void *info)
-/*  [SUMMARY] Synchronisation handler. Executed by "other" CPUs.
-    [RETURNS] Nothing.
-*/
 {
 #ifdef CONFIG_SMP
        struct set_mtrr_data *data = info;
@@ -142,18 +156,19 @@ static void ipi_handler(void *info)
        local_irq_save(flags);
        atomic_dec(&data->count);
-        while(!atomic_read(&data->gate))
+        while (!atomic_read(&data->gate))
                cpu_relax();
        /*  The master has cleared me to execute  */
-        if (data->smp_reg != ~0U) 
+        if (data->smp_reg != ~0U) {
-                mtrr_if->set(data->smp_reg, data->smp_base, 
+                mtrr_if->set(data->smp_reg, data->smp_base,
                             data->smp_size, data->smp_type);
-        else
+        } else {
                mtrr_if->set_all();
+        }
        atomic_dec(&data->count);
-        while(atomic_read(&data->gate))
+        while (atomic_read(&data->gate))
                cpu_relax();
        atomic_dec(&data->count);
@@ -161,7 +176,8 @@ static void ipi_handler(void *info)
 #endif
 }
-static inline int types_compatible(mtrr_type type1, mtrr_type type2) {
+static inline int types_compatible(mtrr_type type1, mtrr_type type2)
+{
        return type1 == MTRR_TYPE_UNCACHABLE ||
               type2 == MTRR_TYPE_UNCACHABLE ||
               (type1 == MTRR_TYPE_WRTHROUGH && type2 == MTRR_TYPE_WRBACK) ||
@@ -176,10 +192,10 @@ static inline int types_compatible(mtrr_type type1, mtrr_type type2) {
 * @type:       mtrr type
 *
 * This is kinda tricky, but fortunately, Intel spelled it out for us cleanly:
- * 
+ *
 * 1. Send IPI to do the following:
 * 2. Disable Interrupts
- * 3. Wait for all procs to do so 
+ * 3. Wait for all procs to do so
 * 4. Enter no-fill cache mode
 * 5. Flush caches
 * 6. Clear PGE bit
@@ -189,26 +205,27 @@ static inline int types_compatible(mtrr_type type1, mtrr_type type2) {
 * 10. Enable all range registers
 * 11. Flush all TLBs and caches again
 * 12. Enter normal cache mode and reenable caching
- * 13. Set PGE 
+ * 13. Set PGE
 * 14. Wait for buddies to catch up
 * 15. Enable interrupts.
- * 
+ *
 * What does that mean for us? Well, first we set data.count to the number
 * of CPUs. As each CPU disables interrupts, it'll decrement it once. We wait
 * until it hits 0 and proceed. We set the data.gate flag and reset data.count.
- * Meanwhile, they are waiting for that flag to be set. Once it's set, each 
+ * Meanwhile, they are waiting for that flag to be set. Once it's set, each
- * CPU goes through the transition of updating MTRRs. The CPU vendors may each do it 
+ * CPU goes through the transition of updating MTRRs.
- * differently, so we call mtrr_if->set() callback and let them take care of it.
+ * The CPU vendors may each do it differently,
- * When they're done, they again decrement data->count and wait for data.gate to 
+ * so we call mtrr_if->set() callback and let them take care of it.
- * be reset. 
+ * When they're done, they again decrement data->count and wait for data.gate
- * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag.
+ * to be reset.
+ * When we finish, we wait for data.count to hit 0 and toggle the data.gate flag
 * Everyone then enables interrupts and we all continue on.
 *
 * Note that the mechanism is the same for UP systems, too; all the SMP stuff
 * becomes nops.
 */
-static void set_mtrr(unsigned int reg, unsigned long base,
+static void
-                     unsigned long size, mtrr_type type)
+set_mtrr(unsigned int reg, unsigned long base, unsigned long size, mtrr_type type)
 {
        struct set_mtrr_data data;
        unsigned long flags;
@@ -218,121 +235,122 @@ static void set_mtrr(unsigned int reg, unsigned long base,
        data.smp_size = size;
        data.smp_type = type;
        atomic_set(&data.count, num_booting_cpus() - 1);
-        /* make sure data.count is visible before unleashing other CPUs */
+        /* Make sure data.count is visible before unleashing other CPUs */
        smp_wmb();
-        atomic_set(&data.gate,0);
+        atomic_set(&data.gate, 0);
-        /*  Start the ball rolling on other CPUs  */
+        /* Start the ball rolling on other CPUs */
        if (smp_call_function(ipi_handler, &data, 0) != 0)
                panic("mtrr: timed out waiting for other CPUs\n");
        local_irq_save(flags);
-        while(atomic_read(&data.count))
+        while (atomic_read(&data.count))
                cpu_relax();
-        /* ok, reset count and toggle gate */
+        /* Ok, reset count and toggle gate */
        atomic_set(&data.count, num_booting_cpus() - 1);
        smp_wmb();
-        atomic_set(&data.gate,1);
+        atomic_set(&data.gate, 1);
-        /* do our MTRR business */
+        /* Do our MTRR business */
-        /* HACK!
+        /*
+         * HACK!
         * We use this same function to initialize the mtrrs on boot.
         * The state of the boot cpu's mtrrs has been saved, and we want
-         * to replicate across all the APs. 
+         * to replicate across all the APs.
         * If we're doing that @reg is set to something special...
         */
-        if (reg != ~0U) 
+        if (reg != ~0U)
-                mtrr_if->set(reg,base,size,type);
+                mtrr_if->set(reg, base, size, type);
-        /* wait for the others */
+        /* Wait for the others */
-        while(atomic_read(&data.count))
+        while (atomic_read(&data.count))
                cpu_relax();
        atomic_set(&data.count, num_booting_cpus() - 1);
        smp_wmb();
-        atomic_set(&data.gate,0);
+        atomic_set(&data.gate, 0);
        /*
         * Wait here for everyone to have seen the gate change
         * So we're the last ones to touch 'data'
         */
-        while(atomic_read(&data.count))
+        while (atomic_read(&data.count))
                cpu_relax();
        local_irq_restore(flags);
 }
 /**
- *      mtrr_add_page - Add a memory type region
+ * mtrr_add_page - Add a memory type region
- *      @base: Physical base address of region in pages (in units of 4 kB!)
+ * @base: Physical base address of region in pages (in units of 4 kB!)
- *      @size: Physical size of region in pages (4 kB)
+ * @size: Physical size of region in pages (4 kB)
- *      @type: Type of MTRR desired
+ * @type: Type of MTRR desired
- *      @increment: If this is true do usage counting on the region
+ * @increment: If this is true do usage counting on the region
 *
- *      Memory type region registers control the caching on newer Intel and
+ * Memory type region registers control the caching on newer Intel and
- *      non Intel processors. This function allows drivers to request an
+ * non Intel processors. This function allows drivers to request an
- *      MTRR is added. The details and hardware specifics of each processor's
+ * MTRR is added. The details and hardware specifics of each processor's
- *      implementation are hidden from the caller, but nevertheless the 
+ * implementation are hidden from the caller, but nevertheless the
- *      caller should expect to need to provide a power of two size on an
+ * caller should expect to need to provide a power of two size on an
- *      equivalent power of two boundary.
+ * equivalent power of two boundary.
 *
- *      If the region cannot be added either because all regions are in use
+ * If the region cannot be added either because all regions are in use
- *      or the CPU cannot support it a negative value is returned. On success
+ * or the CPU cannot support it a negative value is returned. On success
- *      the register number for this entry is returned, but should be treated
+ * the register number for this entry is returned, but should be treated
- *      as a cookie only.
+ * as a cookie only.
 *
- *      On a multiprocessor machine the changes are made to all processors.
+ * On a multiprocessor machine the changes are made to all processors.
- *      This is required on x86 by the Intel processors.
+ * This is required on x86 by the Intel processors.
 *
- *      The available types are
+ * The available types are
 *
- *      %MTRR_TYPE_UNCACHABLE   -       No caching
+ * %MTRR_TYPE_UNCACHABLE - No caching
 *
- *      %MTRR_TYPE_WRBACK       -       Write data back in bursts whenever
+ * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
 *
- *      %MTRR_TYPE_WRCOMB       -       Write data back soon but allow bursts
+ * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
 *
- *      %MTRR_TYPE_WRTHROUGH    -       Cache reads but not writes
+ * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
 *
- *      BUGS: Needs a quiet flag for the cases where drivers do not mind
+ * BUGS: Needs a quiet flag for the cases where drivers do not mind
- *      failures and do not wish system log messages to be sent.
+ * failures and do not wish system log messages to be sent.
 */
+int mtrr_add_page(unsigned long base, unsigned long size,
-int mtrr_add_page(unsigned long base, unsigned long size, 
                  unsigned int type, bool increment)
 {
+        unsigned long lbase, lsize;
        int i, replace, error;
        mtrr_type ltype;
-        unsigned long lbase, lsize;
        if (!mtrr_if)
                return -ENXIO;
-                
-        if ((error = mtrr_if->validate_add_page(base,size,type)))
+        error = mtrr_if->validate_add_page(base, size, type);
+        if (error)
                return error;
        if (type >= MTRR_NUM_TYPES) {
-                printk(KERN_WARNING "mtrr: type: %u invalid\n", type);
+                pr_warning("mtrr: type: %u invalid\n", type);
                return -EINVAL;
        }
-        /*  If the type is WC, check that this processor supports it  */
+        /* If the type is WC, check that this processor supports it */
        if ((type == MTRR_TYPE_WRCOMB) && !have_wrcomb()) {
-                printk(KERN_WARNING
+                pr_warning("mtrr: your processor doesn't support write-combining\n");
-                       "mtrr: your processor doesn't support write-combining\n");
                return -ENOSYS;
        }
        if (!size) {
-                printk(KERN_WARNING "mtrr: zero sized request\n");
+                pr_warning("mtrr: zero sized request\n");
                return -EINVAL;
        }
        if (base & size_or_mask || size & size_or_mask) {
-                printk(KERN_WARNING "mtrr: base or size exceeds the MTRR width\n");
+                pr_warning("mtrr: base or size exceeds the MTRR width\n");
                return -EINVAL;
        }
@@ -341,36 +359,40 @@ int mtrr_add_page(unsigned long base, unsigned long size,
        /* No CPU hotplug when we change MTRR entries */
        get_online_cpus();
-        /*  Search for existing MTRR  */
+        /* Search for existing MTRR  */
        mutex_lock(&mtrr_mutex);
        for (i = 0; i < num_var_ranges; ++i) {
                mtrr_if->get(i, &lbase, &lsize, &ltype);
-                if (!lsize || base > lbase + lsize - 1 || base + size - 1 < lbase)
+                if (!lsize || base > lbase + lsize - 1 ||
+                    base + size - 1 < lbase)
                        continue;
-                /*  At this point we know there is some kind of overlap/enclosure  */
+                /*
+                 * At this point we know there is some kind of
+                 * overlap/enclosure
+                 */
                if (base < lbase || base + size - 1 > lbase + lsize - 1) {
-                        if (base <= lbase && base + size - 1 >= lbase + lsize - 1) {
+                        if (base <= lbase &&
+                            base + size - 1 >= lbase + lsize - 1) {
                                /*  New region encloses an existing region  */
                                if (type == ltype) {
                                        replace = replace == -1 ? i : -2;
                                        continue;
-                                }
+                                } else if (types_compatible(type, ltype))
-                                else if (types_compatible(type, ltype))
                                        continue;
                        }
-                        printk(KERN_WARNING
+                        pr_warning("mtrr: 0x%lx000,0x%lx000 overlaps existing"
-                               "mtrr: 0x%lx000,0x%lx000 overlaps existing"
+                                " 0x%lx000,0x%lx000\n", base, size, lbase,
-                               " 0x%lx000,0x%lx000\n", base, size, lbase,
+                                lsize);
-                               lsize);
                        goto out;
                }
-                /*  New region is enclosed by an existing region  */
+                /* New region is enclosed by an existing region */
                if (ltype != type) {
                        if (types_compatible(type, ltype))
                                continue;
-                        printk (KERN_WARNING "mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
+                        pr_warning("mtrr: type mismatch for %lx000,%lx000 old: %s new: %s\n",
-                             base, size, mtrr_attrib_to_str(ltype),
+                                base, size, mtrr_attrib_to_str(ltype),
-                             mtrr_attrib_to_str(type));
+                                mtrr_attrib_to_str(type));
                        goto out;
                }
                if (increment)
@@ -378,7 +400,7 @@ int mtrr_add_page(unsigned long base, unsigned long size,
                error = i;
                goto out;
        }
-        /*  Search for an empty MTRR  */
+        /* Search for an empty MTRR */
        i = mtrr_if->get_free_region(base, size, replace);
        if (i >= 0) {
                set_mtrr(i, base, size, type);
@@ -393,8 +415,9 @@ int mtrr_add_page(unsigned long base, unsigned long size,
                                mtrr_usage_table[replace] = 0;
                        }
                }
-        } else
+        } else {
-                printk(KERN_INFO "mtrr: no more MTRRs available\n");
+                pr_info("mtrr: no more MTRRs available\n");
+        }
        error = i;
 out:
        mutex_unlock(&mtrr_mutex);
@@ -405,10 +428,8 @@ int mtrr_add_page(unsigned long base, unsigned long size,
 static int mtrr_check(unsigned long base, unsigned long size)
 {
        if ((base & (PAGE_SIZE - 1)) || (size & (PAGE_SIZE - 1))) {
-                printk(KERN_WARNING
+                pr_warning("mtrr: size and base must be multiples of 4 kiB\n");
-                        "mtrr: size and base must be multiples of 4 kiB\n");
+                pr_debug("mtrr: size: 0x%lx  base: 0x%lx\n", size, base);
-                printk(KERN_DEBUG
-                        "mtrr: size: 0x%lx  base: 0x%lx\n", size, base);
                dump_stack();
                return -1;
        }
@@ -416,66 +437,64 @@ static int mtrr_check(unsigned long base, unsigned long size)
 }
 /**
- *      mtrr_add - Add a memory type region
+ * mtrr_add - Add a memory type region
- *      @base: Physical base address of region
+ * @base: Physical base address of region
- *      @size: Physical size of region
+ * @size: Physical size of region
- *      @type: Type of MTRR desired
+ * @type: Type of MTRR desired
- *      @increment: If this is true do usage counting on the region
+ * @increment: If this is true do usage counting on the region
 *
- *      Memory type region registers control the caching on newer Intel and
+ * Memory type region registers control the caching on newer Intel and
- *      non Intel processors. This function allows drivers to request an
+ * non Intel processors. This function allows drivers to request an
- *      MTRR is added. The details and hardware specifics of each processor's
+ * MTRR is added. The details and hardware specifics of each processor's
- *      implementation are hidden from the caller, but nevertheless the 
+ * implementation are hidden from the caller, but nevertheless the
- *      caller should expect to need to provide a power of two size on an
+ * caller should expect to need to provide a power of two size on an
- *      equivalent power of two boundary.
+ * equivalent power of two boundary.
 *
- *      If the region cannot be added either because all regions are in use
+ * If the region cannot be added either because all regions are in use
- *      or the CPU cannot support it a negative value is returned. On success
+ * or the CPU cannot support it a negative value is returned. On success
- *      the register number for this entry is returned, but should be treated
+ * the register number for this entry is returned, but should be treated
- *      as a cookie only.
+ * as a cookie only.
 *
- *      On a multiprocessor machine the changes are made to all processors.
+ * On a multiprocessor machine the changes are made to all processors.
- *      This is required on x86 by the Intel processors.
+ * This is required on x86 by the Intel processors.
 *
- *      The available types are
+ * The available types are
 *
- *      %MTRR_TYPE_UNCACHABLE   -       No caching
+ * %MTRR_TYPE_UNCACHABLE - No caching
 *
- *      %MTRR_TYPE_WRBACK       -       Write data back in bursts whenever
+ * %MTRR_TYPE_WRBACK - Write data back in bursts whenever
 *
- *      %MTRR_TYPE_WRCOMB       -       Write data back soon but allow bursts
+ * %MTRR_TYPE_WRCOMB - Write data back soon but allow bursts
 *
- *      %MTRR_TYPE_WRTHROUGH    -       Cache reads but not writes
+ * %MTRR_TYPE_WRTHROUGH - Cache reads but not writes
 *
- *      BUGS: Needs a quiet flag for the cases where drivers do not mind
+ * BUGS: Needs a quiet flag for the cases where drivers do not mind
- *      failures and do not wish system log messages to be sent.
+ * failures and do not wish system log messages to be sent.
 */
+int mtrr_add(unsigned long base, unsigned long size, unsigned int type,
-int
+             bool increment)
-mtrr_add(unsigned long base, unsigned long size, unsigned int type,
-         bool increment)
 {
        if (mtrr_check(base, size))
                return -EINVAL;
        return mtrr_add_page(base >> PAGE_SHIFT, size >> PAGE_SHIFT, type,
                             increment);
 }
+EXPORT_SYMBOL(mtrr_add);
 /**
- *      mtrr_del_page - delete a memory type region
+ * mtrr_del_page - delete a memory type region
- *      @reg: Register returned by mtrr_add
+ * @reg: Register returned by mtrr_add
- *      @base: Physical base address
+ * @base: Physical base address
- *      @size: Size of region
+ * @size: Size of region
 *
- *      If register is supplied then base and size are ignored. This is
+ * If register is supplied then base and size are ignored. This is
- *      how drivers should call it.
+ * how drivers should call it.
 *
- *      Releases an MTRR region. If the usage count drops to zero the 
+ * Releases an MTRR region. If the usage count drops to zero the
- *      register is freed and the region returns to default state.
+ * register is freed and the region returns to default state.
- *      On success the register is returned, on failure a negative error
+ * On success the register is returned, on failure a negative error
- *      code.
+ * code.
 */
 int mtrr_del_page(int reg, unsigned long base, unsigned long size)
 {
        int i, max;
@@ -500,22 +519,22 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size)
                        }
                }
                if (reg < 0) {
-                        printk(KERN_DEBUG "mtrr: no MTRR for %lx000,%lx000 found\n", base,
+                        pr_debug("mtrr: no MTRR for %lx000,%lx000 found\n",
-                               size);
+                                 base, size);
                        goto out;
                }
        }
        if (reg >= max) {
-                printk(KERN_WARNING "mtrr: register: %d too big\n", reg);
+                pr_warning("mtrr: register: %d too big\n", reg);
                goto out;
        }
        mtrr_if->get(reg, &lbase, &lsize, &ltype);
        if (lsize < 1) {
-                printk(KERN_WARNING "mtrr: MTRR %d not used\n", reg);
+                pr_warning("mtrr: MTRR %d not used\n", reg);
                goto out;
        }
        if (mtrr_usage_table[reg] < 1) {
-                printk(KERN_WARNING "mtrr: reg: %d has count=0\n", reg);
+                pr_warning("mtrr: reg: %d has count=0\n", reg);
                goto out;
        }
        if (--mtrr_usage_table[reg] < 1)
@@ -526,33 +545,31 @@ int mtrr_del_page(int reg, unsigned long base, unsigned long size)
        put_online_cpus();
        return error;
 }
 /**
- *      mtrr_del - delete a memory type region
+ * mtrr_del - delete a memory type region
- *      @reg: Register returned by mtrr_add
+ * @reg: Register returned by mtrr_add
- *      @base: Physical base address
+ * @base: Physical base address
- *      @size: Size of region
+ * @size: Size of region
 *
- *      If register is supplied then base and size are ignored. This is
+ * If register is supplied then base and size are ignored. This is
- *      how drivers should call it.
+ * how drivers should call it.
 *
- *      Releases an MTRR region. If the usage count drops to zero the 
+ * Releases an MTRR region. If the usage count drops to zero the
- *      register is freed and the region returns to default state.
+ * register is freed and the region returns to default state.
- *      On success the register is returned, on failure a negative error
+ * On success the register is returned, on failure a negative error
- *      code.
+ * code.
 */
+int mtrr_del(int reg, unsigned long base, unsigned long size)
-int
-mtrr_del(int reg, unsigned long base, unsigned long size)
 {
        if (mtrr_check(base, size))
                return -EINVAL;
        return mtrr_del_page(reg, base >> PAGE_SHIFT, size >> PAGE_SHIFT);
 }
-EXPORT_SYMBOL(mtrr_add);
 EXPORT_SYMBOL(mtrr_del);
-/* HACK ALERT!
+/*
+ * HACK ALERT!
 * These should be called implicitly, but we can't yet until all the initcall
 * stuff is done...
 */
@@ -576,29 +593,28 @@ struct mtrr_value {
 static struct mtrr_value mtrr_value[MTRR_MAX_VAR_RANGES];
-static int mtrr_save(struct sys_device * sysdev, pm_message_t state)
+static int mtrr_save(struct sys_device *sysdev, pm_message_t state)
 {
        int i;
        for (i = 0; i < num_var_ranges; i++) {
-                mtrr_if->get(i,
+                mtrr_if->get(i, &mtrr_value[i].lbase,
-                             &mtrr_value[i].lbase,
+                                &mtrr_value[i].lsize,
-                             &mtrr_value[i].lsize,
+                                &mtrr_value[i].ltype);
-                             &mtrr_value[i].ltype);
        }
        return 0;
 }
-static int mtrr_restore(struct sys_device * sysdev)
+static int mtrr_restore(struct sys_device *sysdev)
 {
        int i;
        for (i = 0; i < num_var_ranges; i++) {
-                if (mtrr_value[i].lsize)
+                if (mtrr_value[i].lsize) {
-                        set_mtrr(i,
+                        set_mtrr(i, mtrr_value[i].lbase,
-                                 mtrr_value[i].lbase,
+                                    mtrr_value[i].lsize,
-                                 mtrr_value[i].lsize,
+                                    mtrr_value[i].ltype);
-                                 mtrr_value[i].ltype);
+                }
        }
        return 0;
 }
@@ -615,26 +631,29 @@ int __initdata changed_by_mtrr_cleanup;
 /**
 * mtrr_bp_init - initialize mtrrs on the boot CPU
 *
- * This needs to be called early; before any of the other CPUs are 
+ * This needs to be called early; before any of the other CPUs are
 * initialized (i.e. before smp_init()).
- * 
+ *
 */
 void __init mtrr_bp_init(void)
 {
        u32 phys_addr;
        init_ifs();
        phys_addr = 32;
        if (cpu_has_mtrr) {
                mtrr_if = &generic_mtrr_ops;
-                size_or_mask = 0xff000000;      /* 36 bits */
+                size_or_mask = 0xff000000;                      /* 36 bits */
                size_and_mask = 0x00f00000;
                phys_addr = 36;
-                /* This is an AMD specific MSR, but we assume(hope?) that
+                /*
-                   Intel will implement it to when they extend the address
+                 * This is an AMD specific MSR, but we assume(hope?) that
-                   bus of the Xeon. */
+                 * Intel will implement it to when they extend the address
+                 * bus of the Xeon.
+                 */
                if (cpuid_eax(0x80000000) >= 0x80000008) {
                        phys_addr = cpuid_eax(0x80000008) & 0xff;
                        /* CPUID workaround for Intel 0F33/0F34 CPU */
@@ -649,9 +668,11 @@ void __init mtrr_bp_init(void)
                        size_and_mask = ~size_or_mask & 0xfffff00000ULL;
                } else if (boot_cpu_data.x86_vendor == X86_VENDOR_CENTAUR &&
                           boot_cpu_data.x86 == 6) {
-                        /* VIA C* family have Intel style MTRRs, but
+                        /*
-                           don't support PAE */
+                         * VIA C* family have Intel style MTRRs,
-                        size_or_mask = 0xfff00000;      /* 32 bits */
+                         * but don't support PAE
+                         */
+                        size_or_mask = 0xfff00000;              /* 32 bits */
                        size_and_mask = 0;
                        phys_addr = 32;
                }
@@ -694,7 +715,6 @@ void __init mtrr_bp_init(void)
                                changed_by_mtrr_cleanup = 1;
                                mtrr_if->set_all();
                        }
                }
        }
 }
@@ -706,12 +726,17 @@ void mtrr_ap_init(void)
        if (!mtrr_if || !use_intel())
                return;
        /*
-         * Ideally we should hold mtrr_mutex here to avoid mtrr entries changed,
+         * Ideally we should hold mtrr_mutex here to avoid mtrr entries
-         * but this routine will be called in cpu boot time, holding the lock
+         * changed, but this routine will be called in cpu boot time,
-         * breaks it. This routine is called in two cases: 1.very earily time
+         * holding the lock breaks it.
-         * of software resume, when there absolutely isn't mtrr entry changes;
+         *
-         * 2.cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug lock to
+         * This routine is called in two cases:
-         * prevent mtrr entry changes
+         *
+         *   1. very earily time of software resume, when there absolutely
+         *      isn't mtrr entry changes;
+         *
+         *   2. cpu hotadd time. We let mtrr_add/del_page hold cpuhotplug
+         *      lock to prevent mtrr entry changes
         */
        local_irq_save(flags);
@@ -732,19 +757,23 @@ static int __init mtrr_init_finialize(void)
 {
        if (!mtrr_if)
                return 0;
        if (use_intel()) {
                if (!changed_by_mtrr_cleanup)
                        mtrr_state_warn();
-        } else {
+                return 0;
-                /* The CPUs haven't MTRR and seem to not support SMP. They have
-                 * specific drivers, we use a tricky method to support
-                 * suspend/resume for them.
-                 * TBD: is there any system with such CPU which supports
-                 * suspend/resume?  if no, we should remove the code.
-                 */
-                sysdev_driver_register(&cpu_sysdev_class,
-                        &mtrr_sysdev_driver);
        }
+        /*
+         * The CPU has no MTRR and seems to not support SMP. They have
+         * specific drivers, we use a tricky method to support
+         * suspend/resume for them.
+         *
+         * TBD: is there any system with such CPU which supports
+         * suspend/resume? If no, we should remove the code.
+         */
+        sysdev_driver_register(&cpu_sysdev_class, &mtrr_sysdev_driver);
        return 0;
 }
 subsys_initcall(mtrr_init_finialize);
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.h b/arch/x86/kernel/cpu/mtrr/mtrr.h
index 7538b767f206..a501dee9a87a 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.h
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.h
@@ -1,5 +1,5 @@
 /*
- * local mtrr defines.
+ * local MTRR defines.
 */
 #include <linux/types.h>
@@ -14,13 +14,12 @@ extern unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
 struct mtrr_ops {
        u32     vendor;
        u32     use_intel_if;
-//      void    (*init)(void);
        void    (*set)(unsigned int reg, unsigned long base,
                       unsigned long size, mtrr_type type);
        void    (*set_all)(void);
        void    (*get)(unsigned int reg, unsigned long *base,
-                       unsigned long *size, mtrr_type * type);
+                       unsigned long *size, mtrr_type *type);
        int     (*get_free_region)(unsigned long base, unsigned long size,
                                   int replace_reg);
        int     (*validate_add_page)(unsigned long base, unsigned long size,
@@ -39,11 +38,11 @@ extern int positive_have_wrcomb(void);
 /* library functions for processor-specific routines */
 struct set_mtrr_context {
-        unsigned long flags;
+        unsigned long   flags;
-        unsigned long cr4val;
+        unsigned long   cr4val;
-        u32 deftype_lo;
+        u32             deftype_lo;
-        u32 deftype_hi;
+        u32             deftype_hi;
-        u32 ccr3;
+        u32             ccr3;
 };
 void set_mtrr_done(struct set_mtrr_context *ctxt);
@@ -54,10 +53,10 @@ void fill_mtrr_var_range(unsigned int index,
                u32 base_lo, u32 base_hi, u32 mask_lo, u32 mask_hi);
 void get_mtrr_state(void);
-extern void set_mtrr_ops(struct mtrr_ops * ops);
+extern void set_mtrr_ops(struct mtrr_ops *ops);
 extern u64 size_or_mask, size_and_mask;
-extern struct mtrr_ops * mtrr_if;
+extern struct mtrr_ops *mtrr_if;
 #define is_cpu(vnd)     (mtrr_if && mtrr_if->vendor == X86_VENDOR_##vnd)
 #define use_intel()     (mtrr_if && mtrr_if->use_intel_if == 1)
diff --git a/arch/x86/kernel/cpu/mtrr/state.c b/arch/x86/kernel/cpu/mtrr/state.c
index 1f5fb1588d1f..dfc80b4e6b0d 100644
--- a/arch/x86/kernel/cpu/mtrr/state.c
+++ b/arch/x86/kernel/cpu/mtrr/state.c
@@ -1,24 +1,25 @@
-#include <linux/mm.h>
 #include <linux/init.h>
-#include <asm/io.h>
+#include <linux/io.h>
-#include <asm/mtrr.h>
+#include <linux/mm.h>
-#include <asm/msr.h>
 #include <asm/processor-cyrix.h>
 #include <asm/processor-flags.h>
-#include "mtrr.h"
+#include <asm/mtrr.h>
+#include <asm/msr.h>
+#include "mtrr.h"
-/*  Put the processor into a state where MTRRs can be safely set  */
+/* Put the processor into a state where MTRRs can be safely set */
 void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
 {
        unsigned int cr0;
-        /*  Disable interrupts locally  */
+        /* Disable interrupts locally */
        local_irq_save(ctxt->flags);
        if (use_intel() || is_cpu(CYRIX)) {
-                /*  Save value of CR4 and clear Page Global Enable (bit 7)  */
+                /* Save value of CR4 and clear Page Global Enable (bit 7) */
                if (cpu_has_pge) {
                        ctxt->cr4val = read_cr4();
                        write_cr4(ctxt->cr4val & ~X86_CR4_PGE);
@@ -33,50 +34,61 @@ void set_mtrr_prepare_save(struct set_mtrr_context *ctxt)
                write_cr0(cr0);
                wbinvd();
-                if (use_intel())
+                if (use_intel()) {
-                        /*  Save MTRR state */
+                        /* Save MTRR state */
                        rdmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
-                else
+                } else {
-                        /* Cyrix ARRs - everything else were excluded at the top */
+                        /*
+                         * Cyrix ARRs -
+                         * everything else were excluded at the top
+                         */
                        ctxt->ccr3 = getCx86(CX86_CCR3);
+                }
        }
 }
 void set_mtrr_cache_disable(struct set_mtrr_context *ctxt)
 {
-        if (use_intel())
+        if (use_intel()) {
-                /*  Disable MTRRs, and set the default type to uncached  */
+                /* Disable MTRRs, and set the default type to uncached */
                mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo & 0xf300UL,
                      ctxt->deftype_hi);
-        else if (is_cpu(CYRIX))
+        } else {
-                /* Cyrix ARRs - everything else were excluded at the top */
+                if (is_cpu(CYRIX)) {
-                setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
+                        /* Cyrix ARRs - everything else were excluded at the top */
+                        setCx86(CX86_CCR3, (ctxt->ccr3 & 0x0f) | 0x10);
+                }
+        }
 }
-/*  Restore the processor after a set_mtrr_prepare  */
+/* Restore the processor after a set_mtrr_prepare */
 void set_mtrr_done(struct set_mtrr_context *ctxt)
 {
        if (use_intel() || is_cpu(CYRIX)) {
-                /*  Flush caches and TLBs  */
+                /* Flush caches and TLBs */
                wbinvd();
-                /*  Restore MTRRdefType  */
+                /* Restore MTRRdefType */
-                if (use_intel())
+                if (use_intel()) {
                        /* Intel (P6) standard MTRRs */
-                        mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo, ctxt->deftype_hi);
+                        mtrr_wrmsr(MSR_MTRRdefType, ctxt->deftype_lo,
-                else
+                                   ctxt->deftype_hi);
-                        /* Cyrix ARRs - everything else was excluded at the top */
+                } else {
+                        /*
+                         * Cyrix ARRs -
+                         * everything else was excluded at the top
+                         */
                        setCx86(CX86_CCR3, ctxt->ccr3);
+                }
-                /*  Enable caches  */
+                /* Enable caches */
                write_cr0(read_cr0() & 0xbfffffff);
-                /*  Restore value of CR4  */
+                /* Restore value of CR4 */
                if (cpu_has_pge)
                        write_cr4(ctxt->cr4val);
        }
-        /*  Re-enable interrupts locally (if enabled previously)  */
+        /* Re-enable interrupts locally (if enabled previously) */
        local_irq_restore(ctxt->flags);
 }
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 900332b800f8..f9cd0849bd42 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -6,6 +6,7 @@
 *  Copyright (C) 2009 Jaswinder Singh Rajput
 *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
 *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ *  Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
 *
 *  For licencing details see kernel-base/COPYING
 */
@@ -20,6 +21,7 @@
 #include <linux/sched.h>
 #include <linux/uaccess.h>
 #include <linux/highmem.h>
+#include <linux/cpu.h>
 #include <asm/apic.h>
 #include <asm/stacktrace.h>
@@ -27,12 +29,52 @@
 static u64 perf_counter_mask __read_mostly;
+/* The maximal number of PEBS counters: */
+#define MAX_PEBS_COUNTERS       4
+/* The size of a BTS record in bytes: */
+#define BTS_RECORD_SIZE         24
+/* The size of a per-cpu BTS buffer in bytes: */
+#define BTS_BUFFER_SIZE         (BTS_RECORD_SIZE * 1024)
+/* The BTS overflow threshold in bytes from the end of the buffer: */
+#define BTS_OVFL_TH             (BTS_RECORD_SIZE * 64)
+/*
+ * Bits in the debugctlmsr controlling branch tracing.
+ */
+#define X86_DEBUGCTL_TR                 (1 << 6)
+#define X86_DEBUGCTL_BTS                (1 << 7)
+#define X86_DEBUGCTL_BTINT              (1 << 8)
+#define X86_DEBUGCTL_BTS_OFF_OS         (1 << 9)
+#define X86_DEBUGCTL_BTS_OFF_USR        (1 << 10)
+/*
+ * A debug store configuration.
+ *
+ * We only support architectures that use 64bit fields.
+ */
+struct debug_store {
+        u64     bts_buffer_base;
+        u64     bts_index;
+        u64     bts_absolute_maximum;
+        u64     bts_interrupt_threshold;
+        u64     pebs_buffer_base;
+        u64     pebs_index;
+        u64     pebs_absolute_maximum;
+        u64     pebs_interrupt_threshold;
+        u64     pebs_counter_reset[MAX_PEBS_COUNTERS];
+};
 struct cpu_hw_counters {
        struct perf_counter     *counters[X86_PMC_IDX_MAX];
        unsigned long           used_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
        unsigned long           active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
        unsigned long           interrupts;
        int                     enabled;
+        struct debug_store      *ds;
 };
 /*
@@ -58,6 +100,8 @@ struct x86_pmu {
        int             apic;
        u64             max_period;
        u64             intel_ctrl;
+        void            (*enable_bts)(u64 config);
+        void            (*disable_bts)(void);
 };
 static struct x86_pmu x86_pmu __read_mostly;
@@ -577,6 +621,9 @@ x86_perf_counter_update(struct perf_counter *counter,
        u64 prev_raw_count, new_raw_count;
        s64 delta;
+        if (idx == X86_PMC_IDX_FIXED_BTS)
+                return 0;
        /*
         * Careful: an NMI might modify the previous counter value.
         *
@@ -666,10 +713,110 @@ static void release_pmc_hardware(void)
 #endif
 }
+static inline bool bts_available(void)
+{
+        return x86_pmu.enable_bts != NULL;
+}
+static inline void init_debug_store_on_cpu(int cpu)
+{
+        struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds;
+        if (!ds)
+                return;
+        wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
+                     (u32)((u64)(unsigned long)ds),
+                     (u32)((u64)(unsigned long)ds >> 32));
+}
+static inline void fini_debug_store_on_cpu(int cpu)
+{
+        if (!per_cpu(cpu_hw_counters, cpu).ds)
+                return;
+        wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
+}
+static void release_bts_hardware(void)
+{
+        int cpu;
+        if (!bts_available())
+                return;
+        get_online_cpus();
+        for_each_online_cpu(cpu)
+                fini_debug_store_on_cpu(cpu);
+        for_each_possible_cpu(cpu) {
+                struct debug_store *ds = per_cpu(cpu_hw_counters, cpu).ds;
+                if (!ds)
+                        continue;
+                per_cpu(cpu_hw_counters, cpu).ds = NULL;
+                kfree((void *)(unsigned long)ds->bts_buffer_base);
+                kfree(ds);
+        }
+        put_online_cpus();
+}
+static int reserve_bts_hardware(void)
+{
+        int cpu, err = 0;
+        if (!bts_available())
+                return 0;
+        get_online_cpus();
+        for_each_possible_cpu(cpu) {
+                struct debug_store *ds;
+                void *buffer;
+                err = -ENOMEM;
+                buffer = kzalloc(BTS_BUFFER_SIZE, GFP_KERNEL);
+                if (unlikely(!buffer))
+                        break;
+                ds = kzalloc(sizeof(*ds), GFP_KERNEL);
+                if (unlikely(!ds)) {
+                        kfree(buffer);
+                        break;
+                }
+                ds->bts_buffer_base = (u64)(unsigned long)buffer;
+                ds->bts_index = ds->bts_buffer_base;
+                ds->bts_absolute_maximum =
+                        ds->bts_buffer_base + BTS_BUFFER_SIZE;
+                ds->bts_interrupt_threshold =
+                        ds->bts_absolute_maximum - BTS_OVFL_TH;
+                per_cpu(cpu_hw_counters, cpu).ds = ds;
+                err = 0;
+        }
+        if (err)
+                release_bts_hardware();
+        else {
+                for_each_online_cpu(cpu)
+                        init_debug_store_on_cpu(cpu);
+        }
+        put_online_cpus();
+        return err;
+}
 static void hw_perf_counter_destroy(struct perf_counter *counter)
 {
        if (atomic_dec_and_mutex_lock(&active_counters, &pmc_reserve_mutex)) {
                release_pmc_hardware();
+                release_bts_hardware();
                mutex_unlock(&pmc_reserve_mutex);
        }
 }
@@ -712,6 +859,42 @@ set_ext_hw_attr(struct hw_perf_counter *hwc, struct perf_counter_attr *attr)
        return 0;
 }
+static void intel_pmu_enable_bts(u64 config)
+{
+        unsigned long debugctlmsr;
+        debugctlmsr = get_debugctlmsr();
+        debugctlmsr |= X86_DEBUGCTL_TR;
+        debugctlmsr |= X86_DEBUGCTL_BTS;
+        debugctlmsr |= X86_DEBUGCTL_BTINT;
+        if (!(config & ARCH_PERFMON_EVENTSEL_OS))
+                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_OS;
+        if (!(config & ARCH_PERFMON_EVENTSEL_USR))
+                debugctlmsr |= X86_DEBUGCTL_BTS_OFF_USR;
+        update_debugctlmsr(debugctlmsr);
+}
+static void intel_pmu_disable_bts(void)
+{
+        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+        unsigned long debugctlmsr;
+        if (!cpuc->ds)
+                return;
+        debugctlmsr = get_debugctlmsr();
+        debugctlmsr &=
+                ~(X86_DEBUGCTL_TR | X86_DEBUGCTL_BTS | X86_DEBUGCTL_BTINT |
+                  X86_DEBUGCTL_BTS_OFF_OS | X86_DEBUGCTL_BTS_OFF_USR);
+        update_debugctlmsr(debugctlmsr);
+}
 /*
 * Setup the hardware configuration for a given attr_type
 */
@@ -728,9 +911,13 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
        err = 0;
        if (!atomic_inc_not_zero(&active_counters)) {
                mutex_lock(&pmc_reserve_mutex);
-                if (atomic_read(&active_counters) == 0 && !reserve_pmc_hardware())
+                if (atomic_read(&active_counters) == 0) {
-                        err = -EBUSY;
+                        if (!reserve_pmc_hardware())
-                else
+                                err = -EBUSY;
+                        else
+                                err = reserve_bts_hardware();
+                }
+                if (!err)
                        atomic_inc(&active_counters);
                mutex_unlock(&pmc_reserve_mutex);
        }
@@ -793,6 +980,20 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
        if (config == -1LL)
                return -EINVAL;
+        /*
+         * Branch tracing:
+         */
+        if ((attr->config == PERF_COUNT_HW_BRANCH_INSTRUCTIONS) &&
+            (hwc->sample_period == 1)) {
+                /* BTS is not supported by this architecture. */
+                if (!bts_available())
+                        return -EOPNOTSUPP;
+                /* BTS is currently only allowed for user-mode. */
+                if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
+                        return -EOPNOTSUPP;
+        }
        hwc->config |= config;
        return 0;
@@ -817,7 +1018,18 @@ static void p6_pmu_disable_all(void)
 static void intel_pmu_disable_all(void)
 {
+        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+        if (!cpuc->enabled)
+                return;
+        cpuc->enabled = 0;
+        barrier();
        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
+        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
+                intel_pmu_disable_bts();
 }
 static void amd_pmu_disable_all(void)
@@ -875,7 +1087,25 @@ static void p6_pmu_enable_all(void)
 static void intel_pmu_enable_all(void)
 {
+        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
+        if (cpuc->enabled)
+                return;
+        cpuc->enabled = 1;
+        barrier();
        wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
+        if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
+                struct perf_counter *counter =
+                        cpuc->counters[X86_PMC_IDX_FIXED_BTS];
+                if (WARN_ON_ONCE(!counter))
+                        return;
+                intel_pmu_enable_bts(counter->hw.config);
+        }
 }
 static void amd_pmu_enable_all(void)
@@ -962,6 +1192,11 @@ p6_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 static inline void
 intel_pmu_disable_counter(struct hw_perf_counter *hwc, int idx)
 {
+        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
+                intel_pmu_disable_bts();
+                return;
+        }
        if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
                intel_pmu_disable_fixed(hwc, idx);
                return;
@@ -990,6 +1225,9 @@ x86_perf_counter_set_period(struct perf_counter *counter,
        s64 period = hwc->sample_period;
        int err, ret = 0;
+        if (idx == X86_PMC_IDX_FIXED_BTS)
+                return 0;
        /*
         * If we are way outside a reasoable range then just skip forward:
         */
@@ -1072,6 +1310,14 @@ static void p6_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 static void intel_pmu_enable_counter(struct hw_perf_counter *hwc, int idx)
 {
+        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
+                if (!__get_cpu_var(cpu_hw_counters).enabled)
+                        return;
+                intel_pmu_enable_bts(hwc->config);
+                return;
+        }
        if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
                intel_pmu_enable_fixed(hwc, idx);
                return;
@@ -1093,11 +1339,16 @@ fixed_mode_idx(struct perf_counter *counter, struct hw_perf_counter *hwc)
 {
        unsigned int event;
+        event = hwc->config & ARCH_PERFMON_EVENT_MASK;
+        if (unlikely((event ==
+                      x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS)) &&
+                     (hwc->sample_period == 1)))
+                return X86_PMC_IDX_FIXED_BTS;
        if (!x86_pmu.num_counters_fixed)
                return -1;
-        event = hwc->config & ARCH_PERFMON_EVENT_MASK;
        if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_INSTRUCTIONS)))
                return X86_PMC_IDX_FIXED_INSTRUCTIONS;
        if (unlikely(event == x86_pmu.event_map(PERF_COUNT_HW_CPU_CYCLES)))
@@ -1118,7 +1369,15 @@ static int x86_pmu_enable(struct perf_counter *counter)
        int idx;
        idx = fixed_mode_idx(counter, hwc);
-        if (idx >= 0) {
+        if (idx == X86_PMC_IDX_FIXED_BTS) {
+                /* BTS is already occupied. */
+                if (test_and_set_bit(idx, cpuc->used_mask))
+                        return -EAGAIN;
+                hwc->config_base        = 0;
+                hwc->counter_base       = 0;
+                hwc->idx                = idx;
+        } else if (idx >= 0) {
                /*
                 * Try to get the fixed counter, if that is already taken
                 * then try to get a generic counter:
@@ -1229,6 +1488,44 @@ void perf_counter_print_debug(void)
        local_irq_restore(flags);
 }
+static void intel_pmu_drain_bts_buffer(struct cpu_hw_counters *cpuc,
+                                       struct perf_sample_data *data)
+{
+        struct debug_store *ds = cpuc->ds;
+        struct bts_record {
+                u64     from;
+                u64     to;
+                u64     flags;
+        };
+        struct perf_counter *counter = cpuc->counters[X86_PMC_IDX_FIXED_BTS];
+        unsigned long orig_ip = data->regs->ip;
+        struct bts_record *at, *top;
+        if (!counter)
+                return;
+        if (!ds)
+                return;
+        at  = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
+        top = (struct bts_record *)(unsigned long)ds->bts_index;
+        ds->bts_index = ds->bts_buffer_base;
+        for (; at < top; at++) {
+                data->regs->ip  = at->from;
+                data->addr      = at->to;
+                perf_counter_output(counter, 1, data);
+        }
+        data->regs->ip  = orig_ip;
+        data->addr      = 0;
+        /* There's new data available. */
+        counter->pending_kill = POLL_IN;
+}
 static void x86_pmu_disable(struct perf_counter *counter)
 {
        struct cpu_hw_counters *cpuc = &__get_cpu_var(cpu_hw_counters);
@@ -1253,6 +1550,15 @@ static void x86_pmu_disable(struct perf_counter *counter)
         * that we are disabling:
         */
        x86_perf_counter_update(counter, hwc, idx);
+        /* Drain the remaining BTS records. */
+        if (unlikely(idx == X86_PMC_IDX_FIXED_BTS)) {
+                struct perf_sample_data data;
+                struct pt_regs regs;
+                data.regs = &regs;
+                intel_pmu_drain_bts_buffer(cpuc, &data);
+        }
        cpuc->counters[idx] = NULL;
        clear_bit(idx, cpuc->used_mask);
@@ -1280,6 +1586,7 @@ static int intel_pmu_save_and_restart(struct perf_counter *counter)
 static void intel_pmu_reset(void)
 {
+        struct debug_store *ds = __get_cpu_var(cpu_hw_counters).ds;
        unsigned long flags;
        int idx;
@@ -1297,6 +1604,8 @@ static void intel_pmu_reset(void)
        for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
                checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
        }
+        if (ds)
+                ds->bts_index = ds->bts_buffer_base;
        local_irq_restore(flags);
 }
@@ -1362,6 +1671,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs)
        cpuc = &__get_cpu_var(cpu_hw_counters);
        perf_disable();
+        intel_pmu_drain_bts_buffer(cpuc, &data);
        status = intel_pmu_get_status();
        if (!status) {
                perf_enable();
@@ -1571,6 +1881,8 @@ static struct x86_pmu intel_pmu = {
         * the generic counter period:
         */
        .max_period             = (1ULL << 31) - 1,
+        .enable_bts             = intel_pmu_enable_bts,
+        .disable_bts            = intel_pmu_disable_bts,
 };
 static struct x86_pmu amd_pmu = {
@@ -1962,3 +2274,8 @@ struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
        return entry;
 }
+void hw_perf_counter_setup_online(int cpu)
+{
+        init_debug_store_on_cpu(cpu);
+}
diff --git a/arch/x86/kernel/cpu/perfctr-watchdog.c b/arch/x86/kernel/cpu/perfctr-watchdog.c
index e60ed740d2b3..392bea43b890 100644
--- a/arch/x86/kernel/cpu/perfctr-watchdog.c
+++ b/arch/x86/kernel/cpu/perfctr-watchdog.c
@@ -68,16 +68,16 @@ static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
        /* returns the bit offset of the performance counter register */
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
-                return (msr - MSR_K7_PERFCTR0);
+                return msr - MSR_K7_PERFCTR0;
        case X86_VENDOR_INTEL:
                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
-                        return (msr - MSR_ARCH_PERFMON_PERFCTR0);
+                        return msr - MSR_ARCH_PERFMON_PERFCTR0;
                switch (boot_cpu_data.x86) {
                case 6:
-                        return (msr - MSR_P6_PERFCTR0);
+                        return msr - MSR_P6_PERFCTR0;
                case 15:
-                        return (msr - MSR_P4_BPU_PERFCTR0);
+                        return msr - MSR_P4_BPU_PERFCTR0;
                }
        }
        return 0;
@@ -92,16 +92,16 @@ static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
        /* returns the bit offset of the event selection register */
        switch (boot_cpu_data.x86_vendor) {
        case X86_VENDOR_AMD:
-                return (msr - MSR_K7_EVNTSEL0);
+                return msr - MSR_K7_EVNTSEL0;
        case X86_VENDOR_INTEL:
                if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
-                        return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
+                        return msr - MSR_ARCH_PERFMON_EVENTSEL0;
                switch (boot_cpu_data.x86) {
                case 6:
-                        return (msr - MSR_P6_EVNTSEL0);
+                        return msr - MSR_P6_EVNTSEL0;
                case 15:
-                        return (msr - MSR_P4_BSU_ESCR0);
+                        return msr - MSR_P4_BSU_ESCR0;
                }
        }
        return 0;
@@ -113,7 +113,7 @@ int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 {
        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
-        return (!test_bit(counter, perfctr_nmi_owner));
+        return !test_bit(counter, perfctr_nmi_owner);
 }
 /* checks the an msr for availability */
@@ -124,7 +124,7 @@ int avail_to_resrv_perfctr_nmi(unsigned int msr)
        counter = nmi_perfctr_msr_to_bit(msr);
        BUG_ON(counter > NMI_MAX_COUNTER_BITS);
-        return (!test_bit(counter, perfctr_nmi_owner));
+        return !test_bit(counter, perfctr_nmi_owner);
 }
 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
@@ -237,7 +237,7 @@ static unsigned int adjust_for_32bit_ctr(unsigned int hz)
         */
        counter_val = (u64)cpu_khz * 1000;
        do_div(counter_val, retval);
-        if (counter_val > 0x7fffffffULL) {
+        if (counter_val > 0x7fffffffULL) {
                u64 count = (u64)cpu_khz * 1000;
                do_div(count, 0x7fffffffUL);
                retval = count + 1;
@@ -251,7 +251,7 @@ static void write_watchdog_counter(unsigned int perfctr_msr,
        u64 count = (u64)cpu_khz * 1000;
        do_div(count, nmi_hz);
-        if(descr)
+        if (descr)
                pr_debug("setting %s to -0x%08Lx\n", descr, count);
        wrmsrl(perfctr_msr, 0 - count);
 }
@@ -262,7 +262,7 @@ static void write_watchdog_counter32(unsigned int perfctr_msr,
        u64 count = (u64)cpu_khz * 1000;
        do_div(count, nmi_hz);
-        if(descr)
+        if (descr)
                pr_debug("setting %s to -0x%08Lx\n", descr, count);
        wrmsr(perfctr_msr, (u32)(-count), 0);
 }
@@ -296,7 +296,7 @@ static int setup_k7_watchdog(unsigned nmi_hz)
        /* setup the timer */
        wrmsr(evntsel_msr, evntsel, 0);
-        write_watchdog_counter(perfctr_msr, "K7_PERFCTR0",nmi_hz);
+        write_watchdog_counter(perfctr_msr, "K7_PERFCTR0", nmi_hz);
        /* initialize the wd struct before enabling */
        wd->perfctr_msr = perfctr_msr;
@@ -387,7 +387,7 @@ static int setup_p6_watchdog(unsigned nmi_hz)
        /* setup the timer */
        wrmsr(evntsel_msr, evntsel, 0);
        nmi_hz = adjust_for_32bit_ctr(nmi_hz);
-        write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0",nmi_hz);
+        write_watchdog_counter32(perfctr_msr, "P6_PERFCTR0", nmi_hz);
        /* initialize the wd struct before enabling */
        wd->perfctr_msr = perfctr_msr;
@@ -415,7 +415,7 @@ static void __kprobes p6_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
        apic_write(APIC_LVTPC, APIC_DM_NMI);
        /* P6/ARCH_PERFMON has 32 bit counter write */
-        write_watchdog_counter32(wd->perfctr_msr, NULL,nmi_hz);
+        write_watchdog_counter32(wd->perfctr_msr, NULL, nmi_hz);
 }
 static const struct wd_ops p6_wd_ops = {
@@ -490,9 +490,9 @@ static int setup_p4_watchdog(unsigned nmi_hz)
        if (smp_num_siblings == 2) {
                unsigned int ebx, apicid;
-                ebx = cpuid_ebx(1);
+                ebx = cpuid_ebx(1);
-                apicid = (ebx >> 24) & 0xff;
+                apicid = (ebx >> 24) & 0xff;
-                ht_num = apicid & 1;
+                ht_num = apicid & 1;
        } else
 #endif
                ht_num = 0;
@@ -544,7 +544,7 @@ static int setup_p4_watchdog(unsigned nmi_hz)
        }
        evntsel = P4_ESCR_EVENT_SELECT(0x3F)
-                | P4_ESCR_OS
+                | P4_ESCR_OS
                | P4_ESCR_USR;
        cccr_val |= P4_CCCR_THRESHOLD(15)
@@ -612,7 +612,7 @@ static void __kprobes p4_rearm(struct nmi_watchdog_ctlblk *wd, unsigned nmi_hz)
 {
        unsigned dummy;
        /*
-         * P4 quirks:
+         * P4 quirks:
         * - An overflown perfctr will assert its interrupt
         *   until the OVF flag in its CCCR is cleared.
         * - LVTPC is masked on interrupt and must be
@@ -662,7 +662,8 @@ static int setup_intel_arch_watchdog(unsigned nmi_hz)
         * NOTE: Corresponding bit = 0 in ebx indicates event present.
         */
        cpuid(10, &(eax.full), &ebx, &unused, &unused);
-        if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
+        if ((eax.split.mask_length <
+                        (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
            (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
                return 0;
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index d5e30397246b..62ac8cb6ba27 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -116,11 +116,9 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
 #endif
        seq_printf(m, "clflush size\t: %u\n", c->x86_clflush_size);
-#ifdef CONFIG_X86_64
        seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
        seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
                   c->x86_phys_bits, c->x86_virt_bits);
-#endif
        seq_printf(m, "power management:");
        for (i = 0; i < 32; i++) {
@@ -128,7 +126,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                        if (i < ARRAY_SIZE(x86_power_flags) &&
                            x86_power_flags[i])
                                seq_printf(m, "%s%s",
-                                           x86_power_flags[i][0]?" ":"",
+                                           x86_power_flags[i][0] ? " " : "",
                                           x86_power_flags[i]);
                        else
                                seq_printf(m, " [%d]", i);
diff --git a/arch/x86/kernel/cpu/vmware.c b/arch/x86/kernel/cpu/vmware.c
index 284c399e3234..bc24f514ec93 100644
--- a/arch/x86/kernel/cpu/vmware.c
+++ b/arch/x86/kernel/cpu/vmware.c
@@ -49,17 +49,17 @@ static inline int __vmware_platform(void)
 static unsigned long __vmware_get_tsc_khz(void)
 {
-        uint64_t tsc_hz;
+        uint64_t tsc_hz;
-        uint32_t eax, ebx, ecx, edx;
+        uint32_t eax, ebx, ecx, edx;
-        VMWARE_PORT(GETHZ, eax, ebx, ecx, edx);
+        VMWARE_PORT(GETHZ, eax, ebx, ecx, edx);
-        if (ebx == UINT_MAX)
+        if (ebx == UINT_MAX)
-                return 0;
+                return 0;
-        tsc_hz = eax | (((uint64_t)ebx) << 32);
+        tsc_hz = eax | (((uint64_t)ebx) << 32);
-        do_div(tsc_hz, 1000);
+        do_div(tsc_hz, 1000);
-        BUG_ON(tsc_hz >> 32);
+        BUG_ON(tsc_hz >> 32);
-        return tsc_hz;
+        return tsc_hz;
 }
 /*
diff --git a/arch/x86/kernel/doublefault_32.c b/arch/x86/kernel/doublefault_32.c
index b4f14c6c09d9..37250fe490b1 100644
--- a/arch/x86/kernel/doublefault_32.c
+++ b/arch/x86/kernel/doublefault_32.c
@@ -27,9 +27,7 @@ static void doublefault_fn(void)
        if (ptr_ok(gdt)) {
                gdt += GDT_ENTRY_TSS << 3;
-                tss = *(u16 *)(gdt+2);
+                tss = get_desc_base((struct desc_struct *)gdt);
-                tss += *(u8 *)(gdt+4) << 16;
-                tss += *(u8 *)(gdt+7) << 24;
                printk(KERN_EMERG "double fault, tss at %08lx\n", tss);
                if (ptr_ok(tss)) {
diff --git a/arch/x86/kernel/ds.c b/arch/x86/kernel/ds.c
index 48bfe1386038..ef42a038f1a6 100644
--- a/arch/x86/kernel/ds.c
+++ b/arch/x86/kernel/ds.c
@@ -509,15 +509,15 @@ enum bts_field {
        bts_escape              = ((unsigned long)-1 & ~bts_qual_mask)
 };
-static inline unsigned long bts_get(const char *base, enum bts_field field)
+static inline unsigned long bts_get(const char *base, unsigned long field)
 {
        base += (ds_cfg.sizeof_ptr_field * field);
        return *(unsigned long *)base;
 }
-static inline void bts_set(char *base, enum bts_field field, unsigned long val)
+static inline void bts_set(char *base, unsigned long field, unsigned long val)
 {
-        base += (ds_cfg.sizeof_ptr_field * field);;
+        base += (ds_cfg.sizeof_ptr_field * field);
        (*(unsigned long *)base) = val;
 }
diff --git a/arch/x86/kernel/dumpstack.c b/arch/x86/kernel/dumpstack.c
index c8405718a4c3..2d8a371d4339 100644
--- a/arch/x86/kernel/dumpstack.c
+++ b/arch/x86/kernel/dumpstack.c
@@ -15,7 +15,6 @@
 #include <linux/bug.h>
 #include <linux/nmi.h>
 #include <linux/sysfs.h>
-#include <linux/ftrace.h>
 #include <asm/stacktrace.h>
diff --git a/arch/x86/kernel/e820.c b/arch/x86/kernel/e820.c
index 5cb5725b2bae..147005a1cc3c 100644
--- a/arch/x86/kernel/e820.c
+++ b/arch/x86/kernel/e820.c
@@ -115,7 +115,7 @@ static void __init __e820_add_region(struct e820map *e820x, u64 start, u64 size,
 {
        int x = e820x->nr_map;
-        if (x == ARRAY_SIZE(e820x->map)) {
+        if (x >= ARRAY_SIZE(e820x->map)) {
                printk(KERN_ERR "Ooops! Too many entries in the memory map!\n");
                return;
        }
diff --git a/arch/x86/kernel/head_32.S b/arch/x86/kernel/head_32.S
index cc827ac9e8d3..7ffec6b3b331 100644
--- a/arch/x86/kernel/head_32.S
+++ b/arch/x86/kernel/head_32.S
@@ -439,7 +439,6 @@ is386:	movl $2,%ecx		# set MP
        jne 1f
        movl $per_cpu__gdt_page,%eax
        movl $per_cpu__stack_canary,%ecx
-        subl $20, %ecx
        movw %cx, 8 * GDT_ENTRY_STACK_CANARY + 2(%eax)
        shrl $16, %ecx
        movb %cl, 8 * GDT_ENTRY_STACK_CANARY + 4(%eax)
diff --git a/arch/x86/kernel/irq_32.c b/arch/x86/kernel/irq_32.c
index 3b09634a5153..7d35d0fe2329 100644
--- a/arch/x86/kernel/irq_32.c
+++ b/arch/x86/kernel/irq_32.c
@@ -218,7 +218,6 @@ bool handle_irq(unsigned irq, struct pt_regs *regs)
 void fixup_irqs(void)
 {
        unsigned int irq;
-        static int warned;
        struct irq_desc *desc;
        for_each_irq_desc(irq, desc) {
@@ -236,8 +235,8 @@ void fixup_irqs(void)
                }
                if (desc->chip->set_affinity)
                        desc->chip->set_affinity(irq, affinity);
-                else if (desc->action && !(warned++))
+                else if (desc->action)
-                        printk("Cannot set affinity for irq %i\n", irq);
+                        printk_once("Cannot set affinity for irq %i\n", irq);
        }
 #if 0
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index c664d515f613..63b0ec8d3d4a 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -34,7 +34,6 @@
 struct kvm_para_state {
        u8 mmu_queue[MMU_QUEUE_SIZE];
        int mmu_queue_len;
-        enum paravirt_lazy_mode mode;
 };
 static DEFINE_PER_CPU(struct kvm_para_state, para_state);
@@ -77,7 +76,7 @@ static void kvm_deferred_mmu_op(void *buffer, int len)
 {
        struct kvm_para_state *state = kvm_para_state();
-        if (state->mode != PARAVIRT_LAZY_MMU) {
+        if (paravirt_get_lazy_mode() != PARAVIRT_LAZY_MMU) {
                kvm_mmu_op(buffer, len);
                return;
        }
@@ -185,10 +184,7 @@ static void kvm_release_pt(unsigned long pfn)
 static void kvm_enter_lazy_mmu(void)
 {
-        struct kvm_para_state *state = kvm_para_state();
        paravirt_enter_lazy_mmu();
-        state->mode = paravirt_get_lazy_mode();
 }
 static void kvm_leave_lazy_mmu(void)
@@ -197,7 +193,6 @@ static void kvm_leave_lazy_mmu(void)
        mmu_queue_flush(state);
        paravirt_leave_lazy_mmu();
-        state->mode = paravirt_get_lazy_mode();
 }
 static void __init paravirt_ops_setup(void)
diff --git a/arch/x86/kernel/kvmclock.c b/arch/x86/kernel/kvmclock.c
index 223af43f1526..e5efcdcca31b 100644
--- a/arch/x86/kernel/kvmclock.c
+++ b/arch/x86/kernel/kvmclock.c
@@ -50,8 +50,8 @@ static unsigned long kvm_get_wallclock(void)
        struct timespec ts;
        int low, high;
-        low = (int)__pa(&wall_clock);
+        low = (int)__pa_symbol(&wall_clock);
-        high = ((u64)__pa(&wall_clock) >> 32);
+        high = ((u64)__pa_symbol(&wall_clock) >> 32);
        native_write_msr(MSR_KVM_WALL_CLOCK, low, high);
        vcpu_time = &get_cpu_var(hv_clock);
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 651c93b28862..fcd513bf2846 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -482,11 +482,11 @@ static void __init construct_ioapic_table(int mpc_default_type)
                MP_bus_info(&bus);
        }
-        ioapic.type = MP_IOAPIC;
+        ioapic.type     = MP_IOAPIC;
-        ioapic.apicid = 2;
+        ioapic.apicid   = 2;
-        ioapic.apicver = mpc_default_type > 4 ? 0x10 : 0x01;
+        ioapic.apicver  = mpc_default_type > 4 ? 0x10 : 0x01;
-        ioapic.flags = MPC_APIC_USABLE;
+        ioapic.flags    = MPC_APIC_USABLE;
-        ioapic.apicaddr = 0xFEC00000;
+        ioapic.apicaddr = IO_APIC_DEFAULT_PHYS_BASE;
        MP_ioapic_info(&ioapic);
        /*
diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c
index 98fd6cd4e3a4..7dd950094178 100644
--- a/arch/x86/kernel/msr.c
+++ b/arch/x86/kernel/msr.c
@@ -1,6 +1,7 @@
 /* ----------------------------------------------------------------------- *
 *
 *   Copyright 2000-2008 H. Peter Anvin - All Rights Reserved
+ *   Copyright 2009 Intel Corporation; author: H. Peter Anvin
 *
 *   This program is free software; you can redistribute it and/or modify
 *   it under the terms of the GNU General Public License as published by
@@ -80,11 +81,8 @@ static ssize_t msr_read(struct file *file, char __user *buf,
        for (; count; count -= 8) {
                err = rdmsr_safe_on_cpu(cpu, reg, &data[0], &data[1]);
-                if (err) {
+                if (err)
-                        if (err == -EFAULT) /* Fix idiotic error code */
-                                err = -EIO;
                        break;
-                }
                if (copy_to_user(tmp, &data, 8)) {
                        err = -EFAULT;
                        break;
@@ -115,11 +113,8 @@ static ssize_t msr_write(struct file *file, const char __user *buf,
                        break;
                }
                err = wrmsr_safe_on_cpu(cpu, reg, data[0], data[1]);
-                if (err) {
+                if (err)
-                        if (err == -EFAULT) /* Fix idiotic error code */
-                                err = -EIO;
                        break;
-                }
                tmp += 2;
                bytes += 8;
        }
@@ -127,6 +122,54 @@ static ssize_t msr_write(struct file *file, const char __user *buf,
        return bytes ? bytes : err;
 }
+static long msr_ioctl(struct file *file, unsigned int ioc, unsigned long arg)
+{
+        u32 __user *uregs = (u32 __user *)arg;
+        u32 regs[8];
+        int cpu = iminor(file->f_path.dentry->d_inode);
+        int err;
+        switch (ioc) {
+        case X86_IOC_RDMSR_REGS:
+                if (!(file->f_mode & FMODE_READ)) {
+                        err = -EBADF;
+                        break;
+                }
+                if (copy_from_user(&regs, uregs, sizeof regs)) {
+                        err = -EFAULT;
+                        break;
+                }
+                err = rdmsr_safe_regs_on_cpu(cpu, regs);
+                if (err)
+                        break;
+                if (copy_to_user(uregs, &regs, sizeof regs))
+                        err = -EFAULT;
+                break;
+        case X86_IOC_WRMSR_REGS:
+                if (!(file->f_mode & FMODE_WRITE)) {
+                        err = -EBADF;
+                        break;
+                }
+                if (copy_from_user(&regs, uregs, sizeof regs)) {
+                        err = -EFAULT;
+                        break;
+                }
+                err = wrmsr_safe_regs_on_cpu(cpu, regs);
+                if (err)
+                        break;
+                if (copy_to_user(uregs, &regs, sizeof regs))
+                        err = -EFAULT;
+                break;
+        default:
+                err = -ENOTTY;
+                break;
+        }
+        return err;
+}
 static int msr_open(struct inode *inode, struct file *file)
 {
        unsigned int cpu = iminor(file->f_path.dentry->d_inode);
@@ -157,6 +200,8 @@ static const struct file_operations msr_fops = {
        .read = msr_read,
        .write = msr_write,
        .open = msr_open,
+        .unlocked_ioctl = msr_ioctl,
+        .compat_ioctl = msr_ioctl,
 };
 static int __cpuinit msr_device_create(int cpu)
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 70ec9b951d76..f5b0b4a01fb2 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -362,8 +362,9 @@ struct pv_cpu_ops pv_cpu_ops = {
 #endif
        .wbinvd = native_wbinvd,
        .read_msr = native_read_msr_safe,
-        .read_msr_amd = native_read_msr_amd_safe,
+        .rdmsr_regs = native_rdmsr_safe_regs,
        .write_msr = native_write_msr_safe,
+        .wrmsr_regs = native_wrmsr_safe_regs,
        .read_tsc = native_read_tsc,
        .read_pmc = native_read_pmc,
        .read_tscp = native_read_tscp,
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 1a041bcf506b..d71c8655905b 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -3,6 +3,7 @@
 #include <linux/dmar.h>
 #include <linux/bootmem.h>
 #include <linux/pci.h>
+#include <linux/kmemleak.h>
 #include <asm/proto.h>
 #include <asm/dma.h>
@@ -32,7 +33,14 @@ int no_iommu __read_mostly;
 /* Set this to 1 if there is a HW IOMMU in the system */
 int iommu_detected __read_mostly = 0;
-int iommu_pass_through;
+/*
+ * This variable becomes 1 if iommu=pt is passed on the kernel command line.
+ * If this variable is 1, IOMMU implementations do no DMA ranslation for
+ * devices and allow every device to access to whole physical memory. This is
+ * useful if a user want to use an IOMMU only for KVM device assignment to
+ * guests and not for driver dma translation.
+ */
+int iommu_pass_through __read_mostly;
 dma_addr_t bad_dma_address __read_mostly = 0;
 EXPORT_SYMBOL(bad_dma_address);
@@ -88,6 +96,11 @@ void __init dma32_reserve_bootmem(void)
        size = roundup(dma32_bootmem_size, align);
        dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
                                 512ULL<<20);
+        /*
+         * Kmemleak should not scan this block as it may not be mapped via the
+         * kernel direct mapping.
+         */
+        kmemleak_ignore(dma32_bootmem_ptr);
        if (dma32_bootmem_ptr)
                dma32_bootmem_size = size;
        else
@@ -147,7 +160,7 @@ again:
                return NULL;
        addr = page_to_phys(page);
-        if (!is_buffer_dma_capable(dma_mask, addr, size)) {
+        if (addr + size > dma_mask) {
                __free_pages(page, get_order(size));
                if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index d2e56b8f48e7..98a827ee9ed7 100644
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -190,14 +190,13 @@ static void iommu_full(struct device *dev, size_t size, int dir)
 static inline int
 need_iommu(struct device *dev, unsigned long addr, size_t size)
 {
-        return force_iommu ||
+        return force_iommu || !dma_capable(dev, addr, size);
-                !is_buffer_dma_capable(*dev->dma_mask, addr, size);
 }
 static inline int
 nonforced_iommu(struct device *dev, unsigned long addr, size_t size)
 {
-        return !is_buffer_dma_capable(*dev->dma_mask, addr, size);
+        return !dma_capable(dev, addr, size);
 }
 /* Map a single continuous physical area into the IOMMU.
diff --git a/arch/x86/kernel/pci-nommu.c b/arch/x86/kernel/pci-nommu.c
index 71d412a09f30..a3933d4330cd 100644
--- a/arch/x86/kernel/pci-nommu.c
+++ b/arch/x86/kernel/pci-nommu.c
@@ -14,7 +14,7 @@
 static int
 check_addr(char *name, struct device *hwdev, dma_addr_t bus, size_t size)
 {
-        if (hwdev && !is_buffer_dma_capable(*hwdev->dma_mask, bus, size)) {
+        if (hwdev && !dma_capable(hwdev, bus, size)) {
                if (*hwdev->dma_mask >= DMA_BIT_MASK(32))
                        printk(KERN_ERR
                            "nommu_%s: overflow %Lx+%zu of device mask %Lx\n",
@@ -79,12 +79,29 @@ static void nommu_free_coherent(struct device *dev, size_t size, void *vaddr,
        free_pages((unsigned long)vaddr, get_order(size));
 }
+static void nommu_sync_single_for_device(struct device *dev,
+                        dma_addr_t addr, size_t size,
+                        enum dma_data_direction dir)
+{
+        flush_write_buffers();
+}
+static void nommu_sync_sg_for_device(struct device *dev,
+                        struct scatterlist *sg, int nelems,
+                        enum dma_data_direction dir)
+{
+        flush_write_buffers();
+}
 struct dma_map_ops nommu_dma_ops = {
-        .alloc_coherent = dma_generic_alloc_coherent,
+        .alloc_coherent         = dma_generic_alloc_coherent,
-        .free_coherent  = nommu_free_coherent,
+        .free_coherent          = nommu_free_coherent,
-        .map_sg         = nommu_map_sg,
+        .map_sg                 = nommu_map_sg,
-        .map_page       = nommu_map_page,
+        .map_page               = nommu_map_page,
-        .is_phys        = 1,
+        .sync_single_for_device = nommu_sync_single_for_device,
+        .sync_sg_for_device     = nommu_sync_sg_for_device,
+        .is_phys                = 1,
 };
 void __init no_iommu_init(void)
diff --git a/arch/x86/kernel/pci-swiotlb.c b/arch/x86/kernel/pci-swiotlb.c
index 6af96ee44200..e8a35016115f 100644
--- a/arch/x86/kernel/pci-swiotlb.c
+++ b/arch/x86/kernel/pci-swiotlb.c
@@ -13,31 +13,6 @@
 int swiotlb __read_mostly;
-void * __init swiotlb_alloc_boot(size_t size, unsigned long nslabs)
-{
-        return alloc_bootmem_low_pages(size);
-}
-void *swiotlb_alloc(unsigned order, unsigned long nslabs)
-{
-        return (void *)__get_free_pages(GFP_DMA | __GFP_NOWARN, order);
-}
-dma_addr_t swiotlb_phys_to_bus(struct device *hwdev, phys_addr_t paddr)
-{
-        return paddr;
-}
-phys_addr_t swiotlb_bus_to_phys(struct device *hwdev, dma_addr_t baddr)
-{
-        return baddr;
-}
-int __weak swiotlb_arch_range_needs_mapping(phys_addr_t paddr, size_t size)
-{
-        return 0;
-}
 static void *x86_swiotlb_alloc_coherent(struct device *hwdev, size_t size,
                                        dma_addr_t *dma_handle, gfp_t flags)
 {
diff --git a/arch/x86/kernel/process_32.c b/arch/x86/kernel/process_32.c
index 00a8fe4c58bb..209e74801763 100644
--- a/arch/x86/kernel/process_32.c
+++ b/arch/x86/kernel/process_32.c
@@ -63,9 +63,6 @@
 asmlinkage void ret_from_fork(void) __asm__("ret_from_fork");
-DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
-EXPORT_PER_CPU_SYMBOL(current_task);
 /*
 * Return saved PC of a blocked thread.
 */
@@ -361,14 +358,21 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
                                 *next = &next_p->thread;
        int cpu = smp_processor_id();
        struct tss_struct *tss = &per_cpu(init_tss, cpu);
+        bool preload_fpu;
        /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
-        __unlazy_fpu(prev_p);
+        /*
+         * If the task has used fpu the last 5 timeslices, just do a full
+         * restore of the math state immediately to avoid the trap; the
+         * chances of needing FPU soon are obviously high now
+         */
+        preload_fpu = tsk_used_math(next_p) && next_p->fpu_counter > 5;
+        __unlazy_fpu(prev_p);
        /* we're going to use this soon, after a few expensive things */
-        if (next_p->fpu_counter > 5)
+        if (preload_fpu)
                prefetch(next->xstate);
        /*
@@ -409,6 +413,11 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
                     task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT))
                __switch_to_xtra(prev_p, next_p, tss);
+        /* If we're going to preload the fpu context, make sure clts
+           is run while we're batching the cpu state updates. */
+        if (preload_fpu)
+                clts();
        /*
         * Leave lazy mode, flushing any hypercalls made here.
         * This must be done before restoring TLS segments so
@@ -418,15 +427,8 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
         */
        arch_end_context_switch(next_p);
-        /* If the task has used fpu the last 5 timeslices, just do a full
+        if (preload_fpu)
-         * restore of the math state immediately to avoid the trap; the
+                __math_state_restore();
-         * chances of needing FPU soon are obviously high now
-         *
-         * tsk_used_math() checks prevent calling math_state_restore(),
-         * which can sleep in the case of !tsk_used_math()
-         */
-        if (tsk_used_math(next_p) && next_p->fpu_counter > 5)
-                math_state_restore();
        /*
         * Restore %gs if needed (which is common)
diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 89c46f1259d3..72edac026a78 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -57,9 +57,6 @@
 asmlinkage extern void ret_from_fork(void);
-DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
-EXPORT_PER_CPU_SYMBOL(current_task);
 DEFINE_PER_CPU(unsigned long, old_rsp);
 static DEFINE_PER_CPU(unsigned char, is_idle);
@@ -399,9 +396,17 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
        int cpu = smp_processor_id();
        struct tss_struct *tss = &per_cpu(init_tss, cpu);
        unsigned fsindex, gsindex;
+        bool preload_fpu;
+        /*
+         * If the task has used fpu the last 5 timeslices, just do a full
+         * restore of the math state immediately to avoid the trap; the
+         * chances of needing FPU soon are obviously high now
+         */
+        preload_fpu = tsk_used_math(next_p) && next_p->fpu_counter > 5;
        /* we're going to use this soon, after a few expensive things */
-        if (next_p->fpu_counter > 5)
+        if (preload_fpu)
                prefetch(next->xstate);
        /*
@@ -432,6 +437,13 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
        load_TLS(next, cpu);
+        /* Must be after DS reload */
+        unlazy_fpu(prev_p);
+        /* Make sure cpu is ready for new context */
+        if (preload_fpu)
+                clts();
        /*
         * Leave lazy mode, flushing any hypercalls made here.
         * This must be done before restoring TLS segments so
@@ -472,9 +484,6 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
                wrmsrl(MSR_KERNEL_GS_BASE, next->gs);
        prev->gsindex = gsindex;
-        /* Must be after DS reload */
-        unlazy_fpu(prev_p);
        /*
         * Switch the PDA and FPU contexts.
         */
@@ -493,15 +502,12 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
                     task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV))
                __switch_to_xtra(prev_p, next_p, tss);
-        /* If the task has used fpu the last 5 timeslices, just do a full
+        /*
-         * restore of the math state immediately to avoid the trap; the
+         * Preload the FPU context, now that we've determined that the
-         * chances of needing FPU soon are obviously high now
+         * task is likely to be using it. 
-         *
-         * tsk_used_math() checks prevent calling math_state_restore(),
-         * which can sleep in the case of !tsk_used_math()
         */
-        if (tsk_used_math(next_p) && next_p->fpu_counter > 5)
+        if (preload_fpu)
-                math_state_restore();
+                __math_state_restore();
        /*
         * There's a problem with moving the arch_install_thread_hw_breakpoint()
         * call before current is updated.  Suppose a kernel breakpoint is
diff --git a/arch/x86/kernel/signal.c b/arch/x86/kernel/signal.c
index 0f89a4f20db2..baaf8052f355 100644
--- a/arch/x86/kernel/signal.c
+++ b/arch/x86/kernel/signal.c
@@ -860,6 +860,8 @@ do_notify_resume(struct pt_regs *regs, void *unused, __u32 thread_info_flags)
        if (thread_info_flags & _TIF_NOTIFY_RESUME) {
                clear_thread_flag(TIF_NOTIFY_RESUME);
                tracehook_notify_resume(regs);
+                if (current->replacement_session_keyring)
+                        key_replace_session_keyring();
        }
 #ifdef CONFIG_X86_32
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index dee0f3d814af..ec7b64c2df82 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -436,7 +436,8 @@ const struct cpumask *cpu_coregroup_mask(int cpu)
         * For perf, we return last level cache shared map.
         * And for power savings, we return cpu_core_map
         */
-        if (sched_mc_power_savings || sched_smt_power_savings)
+        if ((sched_mc_power_savings || sched_smt_power_savings) &&
+            !(cpu_has(c, X86_FEATURE_AMD_DCM)))
                return cpu_core_mask(cpu);
        else
                return c->llc_shared_map;
diff --git a/arch/x86/kernel/step.c b/arch/x86/kernel/step.c
index e8b9863ef8c4..3149032ff107 100644
--- a/arch/x86/kernel/step.c
+++ b/arch/x86/kernel/step.c
@@ -4,6 +4,7 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/ptrace.h>
+#include <asm/desc.h>
 unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs)
 {
@@ -23,7 +24,7 @@ unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_regs *re
         * and APM bios ones we just ignore here.
         */
        if ((seg & SEGMENT_TI_MASK) == SEGMENT_LDT) {
-                u32 *desc;
+                struct desc_struct *desc;
                unsigned long base;
                seg &= ~7UL;
@@ -33,12 +34,10 @@ unsigned long convert_ip_to_linear(struct task_struct *child, struct pt_regs *re
                        addr = -1L; /* bogus selector, access would fault */
                else {
                        desc = child->mm->context.ldt + seg;
-                        base = ((desc[0] >> 16) |
+                        base = get_desc_base(desc);
-                                ((desc[1] & 0xff) << 16) |
-                                (desc[1] & 0xff000000));
                        /* 16-bit code segment? */
-                        if (!((desc[1] >> 22) & 1))
+                        if (!desc->d)
                                addr &= 0xffff;
                        addr += base;
                }
diff --git a/arch/x86/kernel/tlb_uv.c b/arch/x86/kernel/tlb_uv.c
index 77b9689f8edb..503c1f2e8835 100644
--- a/arch/x86/kernel/tlb_uv.c
+++ b/arch/x86/kernel/tlb_uv.c
@@ -640,13 +640,13 @@ static int __init uv_ptc_init(void)
        if (!is_uv_system())
                return 0;
-        proc_uv_ptc = create_proc_entry(UV_PTC_BASENAME, 0444, NULL);
+        proc_uv_ptc = proc_create(UV_PTC_BASENAME, 0444, NULL,
+                                  &proc_uv_ptc_operations);
        if (!proc_uv_ptc) {
                printk(KERN_ERR "unable to create %s proc entry\n",
                       UV_PTC_BASENAME);
                return -EINVAL;
        }
-        proc_uv_ptc->proc_fops = &proc_uv_ptc_operations;
        return 0;
 }
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index ae04589a579b..49a401b1d4d7 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -76,7 +76,7 @@ char ignore_fpu_irq;
 * F0 0F bug workaround.. We have a special link segment
 * for this.
 */
-gate_desc idt_table[256]
+gate_desc idt_table[NR_VECTORS]
        __attribute__((__section__(".data.idt"))) = { { { { 0, 0 } } }, };
 #endif
@@ -765,33 +765,34 @@ do_spurious_interrupt_bug(struct pt_regs *regs, long error_code)
 #endif
 }
-#ifdef CONFIG_X86_32
+asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void)
-unsigned long patch_espfix_desc(unsigned long uesp, unsigned long kesp)
 {
-        struct desc_struct *gdt = get_cpu_gdt_table(smp_processor_id());
-        unsigned long base = (kesp - uesp) & -THREAD_SIZE;
-        unsigned long new_kesp = kesp - base;
-        unsigned long lim_pages = (new_kesp | (THREAD_SIZE - 1)) >> PAGE_SHIFT;
-        __u64 desc = *(__u64 *)&gdt[GDT_ENTRY_ESPFIX_SS];
-        /* Set up base for espfix segment */
-        desc &= 0x00f0ff0000000000ULL;
-        desc |= ((((__u64)base) << 16) & 0x000000ffffff0000ULL) |
-                ((((__u64)base) << 32) & 0xff00000000000000ULL) |
-                ((((__u64)lim_pages) << 32) & 0x000f000000000000ULL) |
-                (lim_pages & 0xffff);
-        *(__u64 *)&gdt[GDT_ENTRY_ESPFIX_SS] = desc;
-        return new_kesp;
 }
-#endif
-asmlinkage void __attribute__((weak)) smp_thermal_interrupt(void)
+asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void)
 {
 }
-asmlinkage void __attribute__((weak)) smp_threshold_interrupt(void)
+/*
+ * __math_state_restore assumes that cr0.TS is already clear and the
+ * fpu state is all ready for use.  Used during context switch.
+ */
+void __math_state_restore(void)
 {
+        struct thread_info *thread = current_thread_info();
+        struct task_struct *tsk = thread->task;
+        /*
+         * Paranoid restore. send a SIGSEGV if we fail to restore the state.
+         */
+        if (unlikely(restore_fpu_checking(tsk))) {
+                stts();
+                force_sig(SIGSEGV, tsk);
+                return;
+        }
+        thread->status |= TS_USEDFPU;   /* So we fnsave on switch_to() */
+        tsk->fpu_counter++;
 }
 /*
@@ -825,17 +826,8 @@ asmlinkage void math_state_restore(void)
        }
        clts();                         /* Allow maths ops (or we recurse) */
-        /*
-         * Paranoid restore. send a SIGSEGV if we fail to restore the state.
-         */
-        if (unlikely(restore_fpu_checking(tsk))) {
-                stts();
-                force_sig(SIGSEGV, tsk);
-                return;
-        }
-        thread->status |= TS_USEDFPU;   /* So we fnsave on switch_to() */
+        __math_state_restore();
-        tsk->fpu_counter++;
 }
 EXPORT_SYMBOL_GPL(math_state_restore);
diff --git a/arch/x86/kvm/Kconfig b/arch/x86/kvm/Kconfig
index 8600a09e0c6c..b84e571f4175 100644
--- a/arch/x86/kvm/Kconfig
+++ b/arch/x86/kvm/Kconfig
@@ -1,12 +1,8 @@
 #
 # KVM configuration
 #
-config HAVE_KVM
-       bool
-config HAVE_KVM_IRQCHIP
+source "virt/kvm/Kconfig"
-       bool
-       default y
 menuconfig VIRTUALIZATION
        bool "Virtualization"
@@ -29,6 +25,9 @@ config KVM
        select PREEMPT_NOTIFIERS
        select MMU_NOTIFIER
        select ANON_INODES
+        select HAVE_KVM_IRQCHIP
+        select HAVE_KVM_EVENTFD
+        select KVM_APIC_ARCHITECTURE
        ---help---
          Support hosting fully virtualized guest machines using hardware
          virtualization extensions.  You will need a fairly recent
@@ -63,18 +62,6 @@ config KVM_AMD
          To compile this as a module, choose M here: the module
          will be called kvm-amd.
-config KVM_TRACE
-        bool "KVM trace support"
-        depends on KVM && SYSFS
-        select MARKERS
-        select RELAY
-        select DEBUG_FS
-        default n
-        ---help---
-          This option allows reading a trace of kvm-related events through
-          relayfs.  Note the ABI is not considered stable and will be
-          modified in future updates.
 # OK, it's a little counter-intuitive to do this, but it puts it neatly under
 # the virtualization menu.
 source drivers/lguest/Kconfig
diff --git a/arch/x86/kvm/Makefile b/arch/x86/kvm/Makefile
index b43c4efafe80..0e7fe78d0f74 100644
--- a/arch/x86/kvm/Makefile
+++ b/arch/x86/kvm/Makefile
@@ -1,22 +1,19 @@
-#
-# Makefile for Kernel-based Virtual Machine module
-#
-common-objs = $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-                coalesced_mmio.o irq_comm.o)
-ifeq ($(CONFIG_KVM_TRACE),y)
-common-objs += $(addprefix ../../../virt/kvm/, kvm_trace.o)
-endif
-ifeq ($(CONFIG_IOMMU_API),y)
-common-objs += $(addprefix ../../../virt/kvm/, iommu.o)
-endif
 EXTRA_CFLAGS += -Ivirt/kvm -Iarch/x86/kvm
-kvm-objs := $(common-objs) x86.o mmu.o x86_emulate.o i8259.o irq.o lapic.o \
+CFLAGS_x86.o := -I.
-        i8254.o timer.o
+CFLAGS_svm.o := -I.
-obj-$(CONFIG_KVM) += kvm.o
+CFLAGS_vmx.o := -I.
-kvm-intel-objs = vmx.o
-obj-$(CONFIG_KVM_INTEL) += kvm-intel.o
+kvm-y                   += $(addprefix ../../../virt/kvm/, kvm_main.o ioapic.o \
-kvm-amd-objs = svm.o
+                                coalesced_mmio.o irq_comm.o eventfd.o)
-obj-$(CONFIG_KVM_AMD) += kvm-amd.o
+kvm-$(CONFIG_IOMMU_API) += $(addprefix ../../../virt/kvm/, iommu.o)
+kvm-y                   += x86.o mmu.o emulate.o i8259.o irq.o lapic.o \
+                           i8254.o timer.o
+kvm-intel-y             += vmx.o
+kvm-amd-y               += svm.o
+obj-$(CONFIG_KVM)       += kvm.o
+obj-$(CONFIG_KVM_INTEL) += kvm-intel.o
+obj-$(CONFIG_KVM_AMD)   += kvm-amd.o
diff --git a/arch/x86/kvm/x86_emulate.c b/arch/x86/kvm/emulate.c
index 616de4628d60..1be5cd640e93 100644
--- a/arch/x86/kvm/x86_emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -1,5 +1,5 @@
 /******************************************************************************
- * x86_emulate.c
+ * emulate.c
 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
@@ -30,7 +30,9 @@
 #define DPRINTF(x...) do {} while (0)
 #endif
 #include <linux/module.h>
-#include <asm/kvm_x86_emulate.h>
+#include <asm/kvm_emulate.h>
+#include "mmu.h"                /* for is_long_mode() */
 /*
 * Opcode effective-address decode tables.
@@ -60,6 +62,7 @@
 #define SrcImmByte  (6<<4)      /* 8-bit sign-extended immediate operand. */
 #define SrcOne      (7<<4)      /* Implied '1' */
 #define SrcImmUByte (8<<4)      /* 8-bit unsigned immediate operand. */
+#define SrcImmU     (9<<4)      /* Immediate operand, unsigned */
 #define SrcMask     (0xf<<4)
 /* Generic ModRM decode. */
 #define ModRM       (1<<8)
@@ -97,11 +100,11 @@ static u32 opcode_table[256] = {
        /* 0x10 - 0x17 */
        ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
        ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
-        0, 0, 0, 0,
+        ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
        /* 0x18 - 0x1F */
        ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
        ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
-        0, 0, 0, 0,
+        ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
        /* 0x20 - 0x27 */
        ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
        ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
@@ -195,7 +198,7 @@ static u32 opcode_table[256] = {
        ByteOp | SrcImmUByte, SrcImmUByte,
        /* 0xE8 - 0xEF */
        SrcImm | Stack, SrcImm | ImplicitOps,
-        SrcImm | Src2Imm16, SrcImmByte | ImplicitOps,
+        SrcImmU | Src2Imm16, SrcImmByte | ImplicitOps,
        SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
        SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
        /* 0xF0 - 0xF7 */
@@ -208,7 +211,7 @@ static u32 opcode_table[256] = {
 static u32 twobyte_table[256] = {
        /* 0x00 - 0x0F */
-        0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
+        0, Group | GroupDual | Group7, 0, 0, 0, ImplicitOps, ImplicitOps, 0,
        ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
        /* 0x10 - 0x1F */
        0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
@@ -216,7 +219,9 @@ static u32 twobyte_table[256] = {
        ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
        0, 0, 0, 0, 0, 0, 0, 0,
        /* 0x30 - 0x3F */
-        ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+        ImplicitOps, 0, ImplicitOps, 0,
+        ImplicitOps, ImplicitOps, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0,
        /* 0x40 - 0x47 */
        DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
        DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
@@ -319,8 +324,11 @@ static u32 group2_table[] = {
 };
 /* EFLAGS bit definitions. */
+#define EFLG_VM (1<<17)
+#define EFLG_RF (1<<16)
 #define EFLG_OF (1<<11)
 #define EFLG_DF (1<<10)
+#define EFLG_IF (1<<9)
 #define EFLG_SF (1<<7)
 #define EFLG_ZF (1<<6)
 #define EFLG_AF (1<<4)
@@ -1027,6 +1035,7 @@ done_prefixes:
                c->src.type = OP_MEM;
                break;
        case SrcImm:
+        case SrcImmU:
                c->src.type = OP_IMM;
                c->src.ptr = (unsigned long *)c->eip;
                c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
@@ -1044,6 +1053,19 @@ done_prefixes:
                        c->src.val = insn_fetch(s32, 4, c->eip);
                        break;
                }
+                if ((c->d & SrcMask) == SrcImmU) {
+                        switch (c->src.bytes) {
+                        case 1:
+                                c->src.val &= 0xff;
+                                break;
+                        case 2:
+                                c->src.val &= 0xffff;
+                                break;
+                        case 4:
+                                c->src.val &= 0xffffffff;
+                                break;
+                        }
+                }
                break;
        case SrcImmByte:
        case SrcImmUByte:
@@ -1375,6 +1397,217 @@ static void toggle_interruptibility(struct x86_emulate_ctxt *ctxt, u32 mask)
                ctxt->interruptibility = mask;
 }
+static inline void
+setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
+        struct kvm_segment *cs, struct kvm_segment *ss)
+{
+        memset(cs, 0, sizeof(struct kvm_segment));
+        kvm_x86_ops->get_segment(ctxt->vcpu, cs, VCPU_SREG_CS);
+        memset(ss, 0, sizeof(struct kvm_segment));
+        cs->l = 0;              /* will be adjusted later */
+        cs->base = 0;           /* flat segment */
+        cs->g = 1;              /* 4kb granularity */
+        cs->limit = 0xffffffff; /* 4GB limit */
+        cs->type = 0x0b;        /* Read, Execute, Accessed */
+        cs->s = 1;
+        cs->dpl = 0;            /* will be adjusted later */
+        cs->present = 1;
+        cs->db = 1;
+        ss->unusable = 0;
+        ss->base = 0;           /* flat segment */
+        ss->limit = 0xffffffff; /* 4GB limit */
+        ss->g = 1;              /* 4kb granularity */
+        ss->s = 1;
+        ss->type = 0x03;        /* Read/Write, Accessed */
+        ss->db = 1;             /* 32bit stack segment */
+        ss->dpl = 0;
+        ss->present = 1;
+}
+static int
+emulate_syscall(struct x86_emulate_ctxt *ctxt)
+{
+        struct decode_cache *c = &ctxt->decode;
+        struct kvm_segment cs, ss;
+        u64 msr_data;
+        /* syscall is not available in real mode */
+        if (c->lock_prefix || ctxt->mode == X86EMUL_MODE_REAL
+                || !(ctxt->vcpu->arch.cr0 & X86_CR0_PE))
+                return -1;
+        setup_syscalls_segments(ctxt, &cs, &ss);
+        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
+        msr_data >>= 32;
+        cs.selector = (u16)(msr_data & 0xfffc);
+        ss.selector = (u16)(msr_data + 8);
+        if (is_long_mode(ctxt->vcpu)) {
+                cs.db = 0;
+                cs.l = 1;
+        }
+        kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
+        kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
+        c->regs[VCPU_REGS_RCX] = c->eip;
+        if (is_long_mode(ctxt->vcpu)) {
+#ifdef CONFIG_X86_64
+                c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
+                kvm_x86_ops->get_msr(ctxt->vcpu,
+                        ctxt->mode == X86EMUL_MODE_PROT64 ?
+                        MSR_LSTAR : MSR_CSTAR, &msr_data);
+                c->eip = msr_data;
+                kvm_x86_ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
+                ctxt->eflags &= ~(msr_data | EFLG_RF);
+#endif
+        } else {
+                /* legacy mode */
+                kvm_x86_ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
+                c->eip = (u32)msr_data;
+                ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
+        }
+        return 0;
+}
+static int
+emulate_sysenter(struct x86_emulate_ctxt *ctxt)
+{
+        struct decode_cache *c = &ctxt->decode;
+        struct kvm_segment cs, ss;
+        u64 msr_data;
+        /* inject #UD if LOCK prefix is used */
+        if (c->lock_prefix)
+                return -1;
+        /* inject #GP if in real mode or paging is disabled */
+        if (ctxt->mode == X86EMUL_MODE_REAL ||
+                !(ctxt->vcpu->arch.cr0 & X86_CR0_PE)) {
+                kvm_inject_gp(ctxt->vcpu, 0);
+                return -1;
+        }
+        /* XXX sysenter/sysexit have not been tested in 64bit mode.
+        * Therefore, we inject an #UD.
+        */
+        if (ctxt->mode == X86EMUL_MODE_PROT64)
+                return -1;
+        setup_syscalls_segments(ctxt, &cs, &ss);
+        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
+        switch (ctxt->mode) {
+        case X86EMUL_MODE_PROT32:
+                if ((msr_data & 0xfffc) == 0x0) {
+                        kvm_inject_gp(ctxt->vcpu, 0);
+                        return -1;
+                }
+                break;
+        case X86EMUL_MODE_PROT64:
+                if (msr_data == 0x0) {
+                        kvm_inject_gp(ctxt->vcpu, 0);
+                        return -1;
+                }
+                break;
+        }
+        ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
+        cs.selector = (u16)msr_data;
+        cs.selector &= ~SELECTOR_RPL_MASK;
+        ss.selector = cs.selector + 8;
+        ss.selector &= ~SELECTOR_RPL_MASK;
+        if (ctxt->mode == X86EMUL_MODE_PROT64
+                || is_long_mode(ctxt->vcpu)) {
+                cs.db = 0;
+                cs.l = 1;
+        }
+        kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
+        kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
+        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
+        c->eip = msr_data;
+        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
+        c->regs[VCPU_REGS_RSP] = msr_data;
+        return 0;
+}
+static int
+emulate_sysexit(struct x86_emulate_ctxt *ctxt)
+{
+        struct decode_cache *c = &ctxt->decode;
+        struct kvm_segment cs, ss;
+        u64 msr_data;
+        int usermode;
+        /* inject #UD if LOCK prefix is used */
+        if (c->lock_prefix)
+                return -1;
+        /* inject #GP if in real mode or paging is disabled */
+        if (ctxt->mode == X86EMUL_MODE_REAL
+                || !(ctxt->vcpu->arch.cr0 & X86_CR0_PE)) {
+                kvm_inject_gp(ctxt->vcpu, 0);
+                return -1;
+        }
+        /* sysexit must be called from CPL 0 */
+        if (kvm_x86_ops->get_cpl(ctxt->vcpu) != 0) {
+                kvm_inject_gp(ctxt->vcpu, 0);
+                return -1;
+        }
+        setup_syscalls_segments(ctxt, &cs, &ss);
+        if ((c->rex_prefix & 0x8) != 0x0)
+                usermode = X86EMUL_MODE_PROT64;
+        else
+                usermode = X86EMUL_MODE_PROT32;
+        cs.dpl = 3;
+        ss.dpl = 3;
+        kvm_x86_ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
+        switch (usermode) {
+        case X86EMUL_MODE_PROT32:
+                cs.selector = (u16)(msr_data + 16);
+                if ((msr_data & 0xfffc) == 0x0) {
+                        kvm_inject_gp(ctxt->vcpu, 0);
+                        return -1;
+                }
+                ss.selector = (u16)(msr_data + 24);
+                break;
+        case X86EMUL_MODE_PROT64:
+                cs.selector = (u16)(msr_data + 32);
+                if (msr_data == 0x0) {
+                        kvm_inject_gp(ctxt->vcpu, 0);
+                        return -1;
+                }
+                ss.selector = cs.selector + 8;
+                cs.db = 0;
+                cs.l = 1;
+                break;
+        }
+        cs.selector |= SELECTOR_RPL_MASK;
+        ss.selector |= SELECTOR_RPL_MASK;
+        kvm_x86_ops->set_segment(ctxt->vcpu, &cs, VCPU_SREG_CS);
+        kvm_x86_ops->set_segment(ctxt->vcpu, &ss, VCPU_SREG_SS);
+        c->eip = ctxt->vcpu->arch.regs[VCPU_REGS_RDX];
+        c->regs[VCPU_REGS_RSP] = ctxt->vcpu->arch.regs[VCPU_REGS_RCX];
+        return 0;
+}
 int
 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
 {
@@ -1970,6 +2203,12 @@ twobyte_insn:
                        goto cannot_emulate;
                }
                break;
+        case 0x05:              /* syscall */
+                if (emulate_syscall(ctxt) == -1)
+                        goto cannot_emulate;
+                else
+                        goto writeback;
+                break;
        case 0x06:
                emulate_clts(ctxt->vcpu);
                c->dst.type = OP_NONE;
@@ -2036,6 +2275,18 @@ twobyte_insn:
                rc = X86EMUL_CONTINUE;
                c->dst.type = OP_NONE;
                break;
+        case 0x34:              /* sysenter */
+                if (emulate_sysenter(ctxt) == -1)
+                        goto cannot_emulate;
+                else
+                        goto writeback;
+                break;
+        case 0x35:              /* sysexit */
+                if (emulate_sysexit(ctxt) == -1)
+                        goto cannot_emulate;
+                else
+                        goto writeback;
+                break;
        case 0x40 ... 0x4f:     /* cmov */
                c->dst.val = c->dst.orig_val = c->src.val;
                if (!test_cc(c->b, ctxt->eflags))
diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 21f68e00524f..82ad523b4901 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -231,7 +231,7 @@ int pit_has_pending_timer(struct kvm_vcpu *vcpu)
 {
        struct kvm_pit *pit = vcpu->kvm->arch.vpit;
-        if (pit && vcpu->vcpu_id == 0 && pit->pit_state.irq_ack)
+        if (pit && kvm_vcpu_is_bsp(vcpu) && pit->pit_state.irq_ack)
                return atomic_read(&pit->pit_state.pit_timer.pending);
        return 0;
 }
@@ -252,7 +252,7 @@ void __kvm_migrate_pit_timer(struct kvm_vcpu *vcpu)
        struct kvm_pit *pit = vcpu->kvm->arch.vpit;
        struct hrtimer *timer;
-        if (vcpu->vcpu_id != 0 || !pit)
+        if (!kvm_vcpu_is_bsp(vcpu) || !pit)
                return;
        timer = &pit->pit_state.pit_timer.timer;
@@ -294,7 +294,7 @@ static void create_pit_timer(struct kvm_kpit_state *ps, u32 val, int is_period)
        pt->timer.function = kvm_timer_fn;
        pt->t_ops = &kpit_ops;
        pt->kvm = ps->pit->kvm;
-        pt->vcpu_id = 0;
+        pt->vcpu = pt->kvm->bsp_vcpu;
        atomic_set(&pt->pending, 0);
        ps->irq_ack = 1;
@@ -332,33 +332,62 @@ static void pit_load_count(struct kvm *kvm, int channel, u32 val)
        case 1:
        /* FIXME: enhance mode 4 precision */
        case 4:
-                create_pit_timer(ps, val, 0);
+                if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)) {
+                        create_pit_timer(ps, val, 0);
+                }
                break;
        case 2:
        case 3:
-                create_pit_timer(ps, val, 1);
+                if (!(ps->flags & KVM_PIT_FLAGS_HPET_LEGACY)){
+                        create_pit_timer(ps, val, 1);
+                }
                break;
        default:
                destroy_pit_timer(&ps->pit_timer);
        }
 }
-void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val)
+void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val, int hpet_legacy_start)
+{
+        u8 saved_mode;
+        if (hpet_legacy_start) {
+                /* save existing mode for later reenablement */
+                saved_mode = kvm->arch.vpit->pit_state.channels[0].mode;
+                kvm->arch.vpit->pit_state.channels[0].mode = 0xff; /* disable timer */
+                pit_load_count(kvm, channel, val);
+                kvm->arch.vpit->pit_state.channels[0].mode = saved_mode;
+        } else {
+                pit_load_count(kvm, channel, val);
+        }
+}
+static inline struct kvm_pit *dev_to_pit(struct kvm_io_device *dev)
+{
+        return container_of(dev, struct kvm_pit, dev);
+}
+static inline struct kvm_pit *speaker_to_pit(struct kvm_io_device *dev)
 {
-        mutex_lock(&kvm->arch.vpit->pit_state.lock);
+        return container_of(dev, struct kvm_pit, speaker_dev);
-        pit_load_count(kvm, channel, val);
-        mutex_unlock(&kvm->arch.vpit->pit_state.lock);
 }
-static void pit_ioport_write(struct kvm_io_device *this,
+static inline int pit_in_range(gpa_t addr)
-                             gpa_t addr, int len, const void *data)
 {
-        struct kvm_pit *pit = (struct kvm_pit *)this->private;
+        return ((addr >= KVM_PIT_BASE_ADDRESS) &&
+                (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
+}
+static int pit_ioport_write(struct kvm_io_device *this,
+                            gpa_t addr, int len, const void *data)
+{
+        struct kvm_pit *pit = dev_to_pit(this);
        struct kvm_kpit_state *pit_state = &pit->pit_state;
        struct kvm *kvm = pit->kvm;
        int channel, access;
        struct kvm_kpit_channel_state *s;
        u32 val = *(u32 *) data;
+        if (!pit_in_range(addr))
+                return -EOPNOTSUPP;
        val  &= 0xff;
        addr &= KVM_PIT_CHANNEL_MASK;
@@ -421,16 +450,19 @@ static void pit_ioport_write(struct kvm_io_device *this,
        }
        mutex_unlock(&pit_state->lock);
+        return 0;
 }
-static void pit_ioport_read(struct kvm_io_device *this,
+static int pit_ioport_read(struct kvm_io_device *this,
-                            gpa_t addr, int len, void *data)
+                           gpa_t addr, int len, void *data)
 {
-        struct kvm_pit *pit = (struct kvm_pit *)this->private;
+        struct kvm_pit *pit = dev_to_pit(this);
        struct kvm_kpit_state *pit_state = &pit->pit_state;
        struct kvm *kvm = pit->kvm;
        int ret, count;
        struct kvm_kpit_channel_state *s;
+        if (!pit_in_range(addr))
+                return -EOPNOTSUPP;
        addr &= KVM_PIT_CHANNEL_MASK;
        s = &pit_state->channels[addr];
@@ -485,37 +517,36 @@ static void pit_ioport_read(struct kvm_io_device *this,
        memcpy(data, (char *)&ret, len);
        mutex_unlock(&pit_state->lock);
+        return 0;
 }
-static int pit_in_range(struct kvm_io_device *this, gpa_t addr,
+static int speaker_ioport_write(struct kvm_io_device *this,
-                        int len, int is_write)
+                                gpa_t addr, int len, const void *data)
-{
-        return ((addr >= KVM_PIT_BASE_ADDRESS) &&
-                (addr < KVM_PIT_BASE_ADDRESS + KVM_PIT_MEM_LENGTH));
-}
-static void speaker_ioport_write(struct kvm_io_device *this,
-                                 gpa_t addr, int len, const void *data)
 {
-        struct kvm_pit *pit = (struct kvm_pit *)this->private;
+        struct kvm_pit *pit = speaker_to_pit(this);
        struct kvm_kpit_state *pit_state = &pit->pit_state;
        struct kvm *kvm = pit->kvm;
        u32 val = *(u32 *) data;
+        if (addr != KVM_SPEAKER_BASE_ADDRESS)
+                return -EOPNOTSUPP;
        mutex_lock(&pit_state->lock);
        pit_state->speaker_data_on = (val >> 1) & 1;
        pit_set_gate(kvm, 2, val & 1);
        mutex_unlock(&pit_state->lock);
+        return 0;
 }
-static void speaker_ioport_read(struct kvm_io_device *this,
+static int speaker_ioport_read(struct kvm_io_device *this,
-                                gpa_t addr, int len, void *data)
+                               gpa_t addr, int len, void *data)
 {
-        struct kvm_pit *pit = (struct kvm_pit *)this->private;
+        struct kvm_pit *pit = speaker_to_pit(this);
        struct kvm_kpit_state *pit_state = &pit->pit_state;
        struct kvm *kvm = pit->kvm;
        unsigned int refresh_clock;
        int ret;
+        if (addr != KVM_SPEAKER_BASE_ADDRESS)
+                return -EOPNOTSUPP;
        /* Refresh clock toggles at about 15us. We approximate as 2^14ns. */
        refresh_clock = ((unsigned int)ktime_to_ns(ktime_get()) >> 14) & 1;
@@ -527,12 +558,7 @@ static void speaker_ioport_read(struct kvm_io_device *this,
                len = sizeof(ret);
        memcpy(data, (char *)&ret, len);
        mutex_unlock(&pit_state->lock);
-}
+        return 0;
-static int speaker_in_range(struct kvm_io_device *this, gpa_t addr,
-                            int len, int is_write)
-{
-        return (addr == KVM_SPEAKER_BASE_ADDRESS);
 }
 void kvm_pit_reset(struct kvm_pit *pit)
@@ -541,6 +567,7 @@ void kvm_pit_reset(struct kvm_pit *pit)
        struct kvm_kpit_channel_state *c;
        mutex_lock(&pit->pit_state.lock);
+        pit->pit_state.flags = 0;
        for (i = 0; i < 3; i++) {
                c = &pit->pit_state.channels[i];
                c->mode = 0xff;
@@ -563,10 +590,22 @@ static void pit_mask_notifer(struct kvm_irq_mask_notifier *kimn, bool mask)
        }
 }
-struct kvm_pit *kvm_create_pit(struct kvm *kvm)
+static const struct kvm_io_device_ops pit_dev_ops = {
+        .read     = pit_ioport_read,
+        .write    = pit_ioport_write,
+};
+static const struct kvm_io_device_ops speaker_dev_ops = {
+        .read     = speaker_ioport_read,
+        .write    = speaker_ioport_write,
+};
+/* Caller must have writers lock on slots_lock */
+struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags)
 {
        struct kvm_pit *pit;
        struct kvm_kpit_state *pit_state;
+        int ret;
        pit = kzalloc(sizeof(struct kvm_pit), GFP_KERNEL);
        if (!pit)
@@ -582,19 +621,6 @@ struct kvm_pit *kvm_create_pit(struct kvm *kvm)
        mutex_lock(&pit->pit_state.lock);
        spin_lock_init(&pit->pit_state.inject_lock);
-        /* Initialize PIO device */
-        pit->dev.read = pit_ioport_read;
-        pit->dev.write = pit_ioport_write;
-        pit->dev.in_range = pit_in_range;
-        pit->dev.private = pit;
-        kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
-        pit->speaker_dev.read = speaker_ioport_read;
-        pit->speaker_dev.write = speaker_ioport_write;
-        pit->speaker_dev.in_range = speaker_in_range;
-        pit->speaker_dev.private = pit;
-        kvm_io_bus_register_dev(&kvm->pio_bus, &pit->speaker_dev);
        kvm->arch.vpit = pit;
        pit->kvm = kvm;
@@ -613,7 +639,30 @@ struct kvm_pit *kvm_create_pit(struct kvm *kvm)
        pit->mask_notifier.func = pit_mask_notifer;
        kvm_register_irq_mask_notifier(kvm, 0, &pit->mask_notifier);
+        kvm_iodevice_init(&pit->dev, &pit_dev_ops);
+        ret = __kvm_io_bus_register_dev(&kvm->pio_bus, &pit->dev);
+        if (ret < 0)
+                goto fail;
+        if (flags & KVM_PIT_SPEAKER_DUMMY) {
+                kvm_iodevice_init(&pit->speaker_dev, &speaker_dev_ops);
+                ret = __kvm_io_bus_register_dev(&kvm->pio_bus,
+                                                &pit->speaker_dev);
+                if (ret < 0)
+                        goto fail_unregister;
+        }
        return pit;
+fail_unregister:
+        __kvm_io_bus_unregister_dev(&kvm->pio_bus, &pit->dev);
+fail:
+        if (pit->irq_source_id >= 0)
+                kvm_free_irq_source_id(kvm, pit->irq_source_id);
+        kfree(pit);
+        return NULL;
 }
 void kvm_free_pit(struct kvm *kvm)
@@ -623,6 +672,8 @@ void kvm_free_pit(struct kvm *kvm)
        if (kvm->arch.vpit) {
                kvm_unregister_irq_mask_notifier(kvm, 0,
                                               &kvm->arch.vpit->mask_notifier);
+                kvm_unregister_irq_ack_notifier(kvm,
+                                &kvm->arch.vpit->pit_state.irq_ack_notifier);
                mutex_lock(&kvm->arch.vpit->pit_state.lock);
                timer = &kvm->arch.vpit->pit_state.pit_timer.timer;
                hrtimer_cancel(timer);
@@ -637,10 +688,10 @@ static void __inject_pit_timer_intr(struct kvm *kvm)
        struct kvm_vcpu *vcpu;
        int i;
-        mutex_lock(&kvm->lock);
+        mutex_lock(&kvm->irq_lock);
        kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 1);
        kvm_set_irq(kvm, kvm->arch.vpit->irq_source_id, 0, 0);
-        mutex_unlock(&kvm->lock);
+        mutex_unlock(&kvm->irq_lock);
        /*
         * Provides NMI watchdog support via Virtual Wire mode.
@@ -652,11 +703,8 @@ static void __inject_pit_timer_intr(struct kvm *kvm)
         * VCPU0, and only if its LVT0 is in EXTINT mode.
         */
        if (kvm->arch.vapics_in_nmi_mode > 0)
-                for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+                kvm_for_each_vcpu(i, vcpu, kvm)
-                        vcpu = kvm->vcpus[i];
+                        kvm_apic_nmi_wd_deliver(vcpu);
-                        if (vcpu)
-                                kvm_apic_nmi_wd_deliver(vcpu);
-                }
 }
 void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
@@ -665,7 +713,7 @@ void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu)
        struct kvm *kvm = vcpu->kvm;
        struct kvm_kpit_state *ps;
-        if (vcpu && pit) {
+        if (pit) {
                int inject = 0;
                ps = &pit->pit_state;
diff --git a/arch/x86/kvm/i8254.h b/arch/x86/kvm/i8254.h
index bbd863ff60b7..d4c1c7ffdc09 100644
--- a/arch/x86/kvm/i8254.h
+++ b/arch/x86/kvm/i8254.h
@@ -21,6 +21,7 @@ struct kvm_kpit_channel_state {
 struct kvm_kpit_state {
        struct kvm_kpit_channel_state channels[3];
+        u32 flags;
        struct kvm_timer pit_timer;
        bool is_periodic;
        u32    speaker_data_on;
@@ -49,8 +50,8 @@ struct kvm_pit {
 #define KVM_PIT_CHANNEL_MASK        0x3
 void kvm_inject_pit_timer_irqs(struct kvm_vcpu *vcpu);
-void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val);
+void kvm_pit_load_count(struct kvm *kvm, int channel, u32 val, int hpet_legacy_start);
-struct kvm_pit *kvm_create_pit(struct kvm *kvm);
+struct kvm_pit *kvm_create_pit(struct kvm *kvm, u32 flags);
 void kvm_free_pit(struct kvm *kvm);
 void kvm_pit_reset(struct kvm_pit *pit);
diff --git a/arch/x86/kvm/i8259.c b/arch/x86/kvm/i8259.c
index 1ccb50c74f18..01f151682802 100644
--- a/arch/x86/kvm/i8259.c
+++ b/arch/x86/kvm/i8259.c
@@ -30,50 +30,24 @@
 #include "irq.h"
 #include <linux/kvm_host.h>
+#include "trace.h"
-static void pic_lock(struct kvm_pic *s)
-        __acquires(&s->lock)
-{
-        spin_lock(&s->lock);
-}
-static void pic_unlock(struct kvm_pic *s)
-        __releases(&s->lock)
-{
-        struct kvm *kvm = s->kvm;
-        unsigned acks = s->pending_acks;
-        bool wakeup = s->wakeup_needed;
-        struct kvm_vcpu *vcpu;
-        s->pending_acks = 0;
-        s->wakeup_needed = false;
-        spin_unlock(&s->lock);
-        while (acks) {
-                kvm_notify_acked_irq(kvm, SELECT_PIC(__ffs(acks)),
-                                     __ffs(acks));
-                acks &= acks - 1;
-        }
-        if (wakeup) {
-                vcpu = s->kvm->vcpus[0];
-                if (vcpu)
-                        kvm_vcpu_kick(vcpu);
-        }
-}
 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
 {
        s->isr &= ~(1 << irq);
        s->isr_ack |= (1 << irq);
+        if (s != &s->pics_state->pics[0])
+                irq += 8;
+        kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
 }
 void kvm_pic_clear_isr_ack(struct kvm *kvm)
 {
        struct kvm_pic *s = pic_irqchip(kvm);
+        spin_lock(&s->lock);
        s->pics[0].isr_ack = 0xff;
        s->pics[1].isr_ack = 0xff;
+        spin_unlock(&s->lock);
 }
 /*
@@ -174,9 +148,9 @@ static void pic_update_irq(struct kvm_pic *s)
 void kvm_pic_update_irq(struct kvm_pic *s)
 {
-        pic_lock(s);
+        spin_lock(&s->lock);
        pic_update_irq(s);
-        pic_unlock(s);
+        spin_unlock(&s->lock);
 }
 int kvm_pic_set_irq(void *opaque, int irq, int level)
@@ -184,12 +158,14 @@ int kvm_pic_set_irq(void *opaque, int irq, int level)
        struct kvm_pic *s = opaque;
        int ret = -1;
-        pic_lock(s);
+        spin_lock(&s->lock);
        if (irq >= 0 && irq < PIC_NUM_PINS) {
                ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
                pic_update_irq(s);
+                trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
+                                      s->pics[irq >> 3].imr, ret == 0);
        }
-        pic_unlock(s);
+        spin_unlock(&s->lock);
        return ret;
 }
@@ -217,7 +193,7 @@ int kvm_pic_read_irq(struct kvm *kvm)
        int irq, irq2, intno;
        struct kvm_pic *s = pic_irqchip(kvm);
-        pic_lock(s);
+        spin_lock(&s->lock);
        irq = pic_get_irq(&s->pics[0]);
        if (irq >= 0) {
                pic_intack(&s->pics[0], irq);
@@ -242,8 +218,7 @@ int kvm_pic_read_irq(struct kvm *kvm)
                intno = s->pics[0].irq_base + irq;
        }
        pic_update_irq(s);
-        pic_unlock(s);
+        spin_unlock(&s->lock);
-        kvm_notify_acked_irq(kvm, SELECT_PIC(irq), irq);
        return intno;
 }
@@ -252,7 +227,7 @@ void kvm_pic_reset(struct kvm_kpic_state *s)
 {
        int irq, irqbase, n;
        struct kvm *kvm = s->pics_state->irq_request_opaque;
-        struct kvm_vcpu *vcpu0 = kvm->vcpus[0];
+        struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu;
        if (s == &s->pics_state->pics[0])
                irqbase = 0;
@@ -263,7 +238,7 @@ void kvm_pic_reset(struct kvm_kpic_state *s)
                if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
                        if (s->irr & (1 << irq) || s->isr & (1 << irq)) {
                                n = irq + irqbase;
-                                s->pics_state->pending_acks |= 1 << n;
+                                kvm_notify_acked_irq(kvm, SELECT_PIC(n), n);
                        }
        }
        s->last_irr = 0;
@@ -428,8 +403,7 @@ static u32 elcr_ioport_read(void *opaque, u32 addr1)
        return s->elcr;
 }
-static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
+static int picdev_in_range(gpa_t addr)
-                           int len, int is_write)
 {
        switch (addr) {
        case 0x20:
@@ -444,18 +418,25 @@ static int picdev_in_range(struct kvm_io_device *this, gpa_t addr,
        }
 }
-static void picdev_write(struct kvm_io_device *this,
+static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
+{
+        return container_of(dev, struct kvm_pic, dev);
+}
+static int picdev_write(struct kvm_io_device *this,
                         gpa_t addr, int len, const void *val)
 {
-        struct kvm_pic *s = this->private;
+        struct kvm_pic *s = to_pic(this);
        unsigned char data = *(unsigned char *)val;
+        if (!picdev_in_range(addr))
+                return -EOPNOTSUPP;
        if (len != 1) {
                if (printk_ratelimit())
                        printk(KERN_ERR "PIC: non byte write\n");
-                return;
+                return 0;
        }
-        pic_lock(s);
+        spin_lock(&s->lock);
        switch (addr) {
        case 0x20:
        case 0x21:
@@ -468,21 +449,24 @@ static void picdev_write(struct kvm_io_device *this,
                elcr_ioport_write(&s->pics[addr & 1], addr, data);
                break;
        }
-        pic_unlock(s);
+        spin_unlock(&s->lock);
+        return 0;
 }
-static void picdev_read(struct kvm_io_device *this,
+static int picdev_read(struct kvm_io_device *this,
-                        gpa_t addr, int len, void *val)
+                       gpa_t addr, int len, void *val)
 {
-        struct kvm_pic *s = this->private;
+        struct kvm_pic *s = to_pic(this);
        unsigned char data = 0;
+        if (!picdev_in_range(addr))
+                return -EOPNOTSUPP;
        if (len != 1) {
                if (printk_ratelimit())
                        printk(KERN_ERR "PIC: non byte read\n");
-                return;
+                return 0;
        }
-        pic_lock(s);
+        spin_lock(&s->lock);
        switch (addr) {
        case 0x20:
        case 0x21:
@@ -496,7 +480,8 @@ static void picdev_read(struct kvm_io_device *this,
                break;
        }
        *(unsigned char *)val = data;
-        pic_unlock(s);
+        spin_unlock(&s->lock);
+        return 0;
 }
 /*
@@ -505,20 +490,27 @@ static void picdev_read(struct kvm_io_device *this,
 static void pic_irq_request(void *opaque, int level)
 {
        struct kvm *kvm = opaque;
-        struct kvm_vcpu *vcpu = kvm->vcpus[0];
+        struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
        struct kvm_pic *s = pic_irqchip(kvm);
        int irq = pic_get_irq(&s->pics[0]);
        s->output = level;
        if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
                s->pics[0].isr_ack &= ~(1 << irq);
-                s->wakeup_needed = true;
+                kvm_vcpu_kick(vcpu);
        }
 }
+static const struct kvm_io_device_ops picdev_ops = {
+        .read     = picdev_read,
+        .write    = picdev_write,
+};
 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 {
        struct kvm_pic *s;
+        int ret;
        s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
        if (!s)
                return NULL;
@@ -534,10 +526,12 @@ struct kvm_pic *kvm_create_pic(struct kvm *kvm)
        /*
         * Initialize PIO device
         */
-        s->dev.read = picdev_read;
+        kvm_iodevice_init(&s->dev, &picdev_ops);
-        s->dev.write = picdev_write;
+        ret = kvm_io_bus_register_dev(kvm, &kvm->pio_bus, &s->dev);
-        s->dev.in_range = picdev_in_range;
+        if (ret < 0) {
-        s->dev.private = s;
+                kfree(s);
-        kvm_io_bus_register_dev(&kvm->pio_bus, &s->dev);
+                return NULL;
+        }
        return s;
 }
diff --git a/arch/x86/kvm/irq.h b/arch/x86/kvm/irq.h
index 9f593188129e..7d6058a2fd38 100644
--- a/arch/x86/kvm/irq.h
+++ b/arch/x86/kvm/irq.h
@@ -63,7 +63,6 @@ struct kvm_kpic_state {
 struct kvm_pic {
        spinlock_t lock;
-        bool wakeup_needed;
        unsigned pending_acks;
        struct kvm *kvm;
        struct kvm_kpic_state pics[2]; /* 0 is master pic, 1 is slave pic */
diff --git a/arch/x86/kvm/kvm_cache_regs.h b/arch/x86/kvm/kvm_cache_regs.h
index 1ff819dce7d3..7bcc5b6a4403 100644
--- a/arch/x86/kvm/kvm_cache_regs.h
+++ b/arch/x86/kvm/kvm_cache_regs.h
@@ -29,4 +29,13 @@ static inline void kvm_rip_write(struct kvm_vcpu *vcpu, unsigned long val)
        kvm_register_write(vcpu, VCPU_REGS_RIP, val);
 }
+static inline u64 kvm_pdptr_read(struct kvm_vcpu *vcpu, int index)
+{
+        if (!test_bit(VCPU_EXREG_PDPTR,
+                      (unsigned long *)&vcpu->arch.regs_avail))
+                kvm_x86_ops->cache_reg(vcpu, VCPU_EXREG_PDPTR);
+        return vcpu->arch.pdptrs[index];
+}
 #endif
diff --git a/arch/x86/kvm/kvm_svm.h b/arch/x86/kvm/kvm_svm.h
deleted file mode 100644
index ed66e4c078dc..000000000000
--- a/arch/x86/kvm/kvm_svm.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef __KVM_SVM_H
-#define __KVM_SVM_H
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/list.h>
-#include <linux/kvm_host.h>
-#include <asm/msr.h>
-#include <asm/svm.h>
-static const u32 host_save_user_msrs[] = {
-#ifdef CONFIG_X86_64
-        MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
-        MSR_FS_BASE,
-#endif
-        MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
-};
-#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
-struct kvm_vcpu;
-struct vcpu_svm {
-        struct kvm_vcpu vcpu;
-        struct vmcb *vmcb;
-        unsigned long vmcb_pa;
-        struct svm_cpu_data *svm_data;
-        uint64_t asid_generation;
-        u64 next_rip;
-        u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
-        u64 host_gs_base;
-        unsigned long host_cr2;
-        u32 *msrpm;
-        struct vmcb *hsave;
-        u64 hsave_msr;
-        u64 nested_vmcb;
-        /* These are the merged vectors */
-        u32 *nested_msrpm;
-        /* gpa pointers to the real vectors */
-        u64 nested_vmcb_msrpm;
-};
-#endif
diff --git a/arch/x86/kvm/kvm_timer.h b/arch/x86/kvm/kvm_timer.h
index 26bd6ba74e1c..55c7524dda54 100644
--- a/arch/x86/kvm/kvm_timer.h
+++ b/arch/x86/kvm/kvm_timer.h
@@ -6,7 +6,7 @@ struct kvm_timer {
        bool reinject;
        struct kvm_timer_ops *t_ops;
        struct kvm *kvm;
-        int vcpu_id;
+        struct kvm_vcpu *vcpu;
 };
 struct kvm_timer_ops {
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index ae99d83f81a3..1ae5ceba7eb2 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -32,8 +32,11 @@
 #include <asm/current.h>
 #include <asm/apicdef.h>
 #include <asm/atomic.h>
+#include <asm/apicdef.h>
 #include "kvm_cache_regs.h"
 #include "irq.h"
+#include "trace.h"
+#include "x86.h"
 #ifndef CONFIG_X86_64
 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
@@ -141,6 +144,26 @@ static inline int apic_lvt_nmi_mode(u32 lvt_val)
        return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 }
+void kvm_apic_set_version(struct kvm_vcpu *vcpu)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        struct kvm_cpuid_entry2 *feat;
+        u32 v = APIC_VERSION;
+        if (!irqchip_in_kernel(vcpu->kvm))
+                return;
+        feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
+        if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
+                v |= APIC_LVR_DIRECTED_EOI;
+        apic_set_reg(apic, APIC_LVR, v);
+}
+static inline int apic_x2apic_mode(struct kvm_lapic *apic)
+{
+        return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
+}
 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
        LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
        LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
@@ -165,36 +188,52 @@ static int find_highest_vector(void *bitmap)
 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 {
+        apic->irr_pending = true;
        return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 }
-static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
+static inline int apic_search_irr(struct kvm_lapic *apic)
 {
-        apic_clear_vector(vec, apic->regs + APIC_IRR);
+        return find_highest_vector(apic->regs + APIC_IRR);
 }
 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 {
        int result;
-        result = find_highest_vector(apic->regs + APIC_IRR);
+        if (!apic->irr_pending)
+                return -1;
+        result = apic_search_irr(apic);
        ASSERT(result == -1 || result >= 16);
        return result;
 }
+static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
+{
+        apic->irr_pending = false;
+        apic_clear_vector(vec, apic->regs + APIC_IRR);
+        if (apic_search_irr(apic) != -1)
+                apic->irr_pending = true;
+}
 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 {
        struct kvm_lapic *apic = vcpu->arch.apic;
        int highest_irr;
+        /* This may race with setting of irr in __apic_accept_irq() and
+         * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
+         * will cause vmexit immediately and the value will be recalculated
+         * on the next vmentry.
+         */
        if (!apic)
                return 0;
        highest_irr = apic_find_highest_irr(apic);
        return highest_irr;
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_find_highest_irr);
 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                             int vector, int level, int trig_mode);
@@ -251,7 +290,12 @@ int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 {
        int result = 0;
-        u8 logical_id;
+        u32 logical_id;
+        if (apic_x2apic_mode(apic)) {
+                logical_id = apic_get_reg(apic, APIC_LDR);
+                return logical_id & mda;
+        }
        logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
@@ -331,6 +375,8 @@ static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
                        break;
                result = !apic_test_and_set_irr(vector, apic);
+                trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
+                                          trig_mode, vector, !result);
                if (!result) {
                        if (trig_mode)
                                apic_debug("level trig mode repeatedly for "
@@ -425,7 +471,11 @@ static void apic_set_eoi(struct kvm_lapic *apic)
                trigger_mode = IOAPIC_LEVEL_TRIG;
        else
                trigger_mode = IOAPIC_EDGE_TRIG;
-        kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
+        if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)) {
+                mutex_lock(&apic->vcpu->kvm->irq_lock);
+                kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
+                mutex_unlock(&apic->vcpu->kvm->irq_lock);
+        }
 }
 static void apic_send_ipi(struct kvm_lapic *apic)
@@ -440,7 +490,12 @@ static void apic_send_ipi(struct kvm_lapic *apic)
        irq.level = icr_low & APIC_INT_ASSERT;
        irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
        irq.shorthand = icr_low & APIC_SHORT_MASK;
-        irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
+        if (apic_x2apic_mode(apic))
+                irq.dest_id = icr_high;
+        else
+                irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
+        trace_kvm_apic_ipi(icr_low, irq.dest_id);
        apic_debug("icr_high 0x%x, icr_low 0x%x, "
                   "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
@@ -449,7 +504,9 @@ static void apic_send_ipi(struct kvm_lapic *apic)
                   irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
                   irq.vector);
+        mutex_lock(&apic->vcpu->kvm->irq_lock);
        kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
+        mutex_unlock(&apic->vcpu->kvm->irq_lock);
 }
 static u32 apic_get_tmcct(struct kvm_lapic *apic)
@@ -495,12 +552,16 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 {
        u32 val = 0;
-        KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
        if (offset >= LAPIC_MMIO_LENGTH)
                return 0;
        switch (offset) {
+        case APIC_ID:
+                if (apic_x2apic_mode(apic))
+                        val = kvm_apic_id(apic);
+                else
+                        val = kvm_apic_id(apic) << 24;
+                break;
        case APIC_ARBPRI:
                printk(KERN_WARNING "Access APIC ARBPRI register "
                       "which is for P6\n");
@@ -522,21 +583,35 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
        return val;
 }
-static void apic_mmio_read(struct kvm_io_device *this,
+static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
-                           gpa_t address, int len, void *data)
+{
+        return container_of(dev, struct kvm_lapic, dev);
+}
+static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
+                void *data)
 {
-        struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
-        unsigned int offset = address - apic->base_address;
        unsigned char alignment = offset & 0xf;
        u32 result;
+        /* this bitmask has a bit cleared for each reserver register */
+        static const u64 rmask = 0x43ff01ffffffe70cULL;
        if ((alignment + len) > 4) {
-                printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
+                apic_debug("KVM_APIC_READ: alignment error %x %d\n",
-                       (unsigned long)address, len);
+                           offset, len);
-                return;
+                return 1;
        }
+        if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
+                apic_debug("KVM_APIC_READ: read reserved register %x\n",
+                           offset);
+                return 1;
+        }
        result = __apic_read(apic, offset & ~0xf);
+        trace_kvm_apic_read(offset, result);
        switch (len) {
        case 1:
        case 2:
@@ -548,6 +623,28 @@ static void apic_mmio_read(struct kvm_io_device *this,
                       "should be 1,2, or 4 instead\n", len);
                break;
        }
+        return 0;
+}
+static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
+{
+        return apic_hw_enabled(apic) &&
+            addr >= apic->base_address &&
+            addr < apic->base_address + LAPIC_MMIO_LENGTH;
+}
+static int apic_mmio_read(struct kvm_io_device *this,
+                           gpa_t address, int len, void *data)
+{
+        struct kvm_lapic *apic = to_lapic(this);
+        u32 offset = address - apic->base_address;
+        if (!apic_mmio_in_range(apic, address))
+                return -EOPNOTSUPP;
+        apic_reg_read(apic, offset, len, data);
+        return 0;
 }
 static void update_divide_count(struct kvm_lapic *apic)
@@ -573,6 +670,15 @@ static void start_apic_timer(struct kvm_lapic *apic)
        if (!apic->lapic_timer.period)
                return;
+        /*
+         * Do not allow the guest to program periodic timers with small
+         * interval, since the hrtimers are not throttled by the host
+         * scheduler.
+         */
+        if (apic_lvtt_period(apic)) {
+                if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
+                        apic->lapic_timer.period = NSEC_PER_MSEC/2;
+        }
        hrtimer_start(&apic->lapic_timer.timer,
                      ktime_add_ns(now, apic->lapic_timer.period),
@@ -603,40 +709,18 @@ static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
                apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 }
-static void apic_mmio_write(struct kvm_io_device *this,
+static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
-                            gpa_t address, int len, const void *data)
 {
-        struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
+        int ret = 0;
-        unsigned int offset = address - apic->base_address;
-        unsigned char alignment = offset & 0xf;
-        u32 val;
-        /*
-         * APIC register must be aligned on 128-bits boundary.
-         * 32/64/128 bits registers must be accessed thru 32 bits.
-         * Refer SDM 8.4.1
-         */
-        if (len != 4 || alignment) {
-                /* Don't shout loud, $infamous_os would cause only noise. */
-                apic_debug("apic write: bad size=%d %lx\n",
-                           len, (long)address);
-                return;
-        }
-        val = *(u32 *) data;
-        /* too common printing */
-        if (offset != APIC_EOI)
-                apic_debug("%s: offset 0x%x with length 0x%x, and value is "
-                           "0x%x\n", __func__, offset, len, val);
-        offset &= 0xff0;
-        KVMTRACE_1D(APIC_ACCESS, apic->vcpu, (u32)offset, handler);
+        trace_kvm_apic_write(reg, val);
-        switch (offset) {
+        switch (reg) {
        case APIC_ID:           /* Local APIC ID */
-                apic_set_reg(apic, APIC_ID, val);
+                if (!apic_x2apic_mode(apic))
+                        apic_set_reg(apic, APIC_ID, val);
+                else
+                        ret = 1;
                break;
        case APIC_TASKPRI:
@@ -649,15 +733,24 @@ static void apic_mmio_write(struct kvm_io_device *this,
                break;
        case APIC_LDR:
-                apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
+                if (!apic_x2apic_mode(apic))
+                        apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
+                else
+                        ret = 1;
                break;
        case APIC_DFR:
-                apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
+                if (!apic_x2apic_mode(apic))
+                        apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
+                else
+                        ret = 1;
                break;
-        case APIC_SPIV:
+        case APIC_SPIV: {
-                apic_set_reg(apic, APIC_SPIV, val & 0x3ff);
+                u32 mask = 0x3ff;
+                if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
+                        mask |= APIC_SPIV_DIRECTED_EOI;
+                apic_set_reg(apic, APIC_SPIV, val & mask);
                if (!(val & APIC_SPIV_APIC_ENABLED)) {
                        int i;
                        u32 lvt_val;
@@ -672,7 +765,7 @@ static void apic_mmio_write(struct kvm_io_device *this,
                }
                break;
+        }
        case APIC_ICR:
                /* No delay here, so we always clear the pending bit */
                apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
@@ -680,7 +773,9 @@ static void apic_mmio_write(struct kvm_io_device *this,
                break;
        case APIC_ICR2:
-                apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
+                if (!apic_x2apic_mode(apic))
+                        val &= 0xff000000;
+                apic_set_reg(apic, APIC_ICR2, val);
                break;
        case APIC_LVT0:
@@ -694,8 +789,8 @@ static void apic_mmio_write(struct kvm_io_device *this,
                if (!apic_sw_enabled(apic))
                        val |= APIC_LVT_MASKED;
-                val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
+                val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
-                apic_set_reg(apic, offset, val);
+                apic_set_reg(apic, reg, val);
                break;
@@ -703,7 +798,7 @@ static void apic_mmio_write(struct kvm_io_device *this,
                hrtimer_cancel(&apic->lapic_timer.timer);
                apic_set_reg(apic, APIC_TMICT, val);
                start_apic_timer(apic);
-                return;
+                break;
        case APIC_TDCR:
                if (val & 4)
@@ -712,27 +807,59 @@ static void apic_mmio_write(struct kvm_io_device *this,
                update_divide_count(apic);
                break;
+        case APIC_ESR:
+                if (apic_x2apic_mode(apic) && val != 0) {
+                        printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
+                        ret = 1;
+                }
+                break;
+        case APIC_SELF_IPI:
+                if (apic_x2apic_mode(apic)) {
+                        apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
+                } else
+                        ret = 1;
+                break;
        default:
-                apic_debug("Local APIC Write to read-only register %x\n",
+                ret = 1;
-                           offset);
                break;
        }
+        if (ret)
+                apic_debug("Local APIC Write to read-only register %x\n", reg);
+        return ret;
 }
-static int apic_mmio_range(struct kvm_io_device *this, gpa_t addr,
+static int apic_mmio_write(struct kvm_io_device *this,
-                           int len, int size)
+                            gpa_t address, int len, const void *data)
 {
-        struct kvm_lapic *apic = (struct kvm_lapic *)this->private;
+        struct kvm_lapic *apic = to_lapic(this);
-        int ret = 0;
+        unsigned int offset = address - apic->base_address;
+        u32 val;
+        if (!apic_mmio_in_range(apic, address))
+                return -EOPNOTSUPP;
-        if (apic_hw_enabled(apic) &&
+        /*
-            (addr >= apic->base_address) &&
+         * APIC register must be aligned on 128-bits boundary.
-            (addr < (apic->base_address + LAPIC_MMIO_LENGTH)))
+         * 32/64/128 bits registers must be accessed thru 32 bits.
-                ret = 1;
+         * Refer SDM 8.4.1
+         */
+        if (len != 4 || (offset & 0xf)) {
+                /* Don't shout loud, $infamous_os would cause only noise. */
+                apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
+                return 0;
+        }
-        return ret;
+        val = *(u32*)data;
+        /* too common printing */
+        if (offset != APIC_EOI)
+                apic_debug("%s: offset 0x%x with length 0x%x, and value is "
+                           "0x%x\n", __func__, offset, len, val);
+        apic_reg_write(apic, offset & 0xff0, val);
+        return 0;
 }
 void kvm_free_lapic(struct kvm_vcpu *vcpu)
@@ -763,7 +890,6 @@ void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
        apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
                     | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_set_tpr);
 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 {
@@ -776,7 +902,6 @@ u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
        return (tpr & 0xf0) >> 4;
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_get_cr8);
 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 {
@@ -787,10 +912,16 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
                vcpu->arch.apic_base = value;
                return;
        }
-        if (apic->vcpu->vcpu_id)
+        if (!kvm_vcpu_is_bsp(apic->vcpu))
                value &= ~MSR_IA32_APICBASE_BSP;
        vcpu->arch.apic_base = value;
+        if (apic_x2apic_mode(apic)) {
+                u32 id = kvm_apic_id(apic);
+                u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
+                apic_set_reg(apic, APIC_LDR, ldr);
+        }
        apic->base_address = apic->vcpu->arch.apic_base &
                             MSR_IA32_APICBASE_BASE;
@@ -800,12 +931,6 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 }
-u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu)
-{
-        return vcpu->arch.apic_base;
-}
-EXPORT_SYMBOL_GPL(kvm_lapic_get_base);
 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 {
        struct kvm_lapic *apic;
@@ -821,7 +946,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
        hrtimer_cancel(&apic->lapic_timer.timer);
        apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
-        apic_set_reg(apic, APIC_LVR, APIC_VERSION);
+        kvm_apic_set_version(apic->vcpu);
        for (i = 0; i < APIC_LVT_NUM; i++)
                apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
@@ -842,9 +967,10 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
                apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
        }
+        apic->irr_pending = false;
        update_divide_count(apic);
        atomic_set(&apic->lapic_timer.pending, 0);
-        if (vcpu->vcpu_id == 0)
+        if (kvm_vcpu_is_bsp(vcpu))
                vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
        apic_update_ppr(apic);
@@ -855,7 +981,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
                   vcpu, kvm_apic_id(apic),
                   vcpu->arch.apic_base, apic->base_address);
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_reset);
 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 {
@@ -866,7 +991,6 @@ int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 {
        return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 }
-EXPORT_SYMBOL_GPL(kvm_lapic_enabled);
 /*
 *----------------------------------------------------------------------
@@ -917,6 +1041,11 @@ static struct kvm_timer_ops lapic_timer_ops = {
        .is_periodic = lapic_is_periodic,
 };
+static const struct kvm_io_device_ops apic_mmio_ops = {
+        .read     = apic_mmio_read,
+        .write    = apic_mmio_write,
+};
 int kvm_create_lapic(struct kvm_vcpu *vcpu)
 {
        struct kvm_lapic *apic;
@@ -945,16 +1074,13 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu)
        apic->lapic_timer.timer.function = kvm_timer_fn;
        apic->lapic_timer.t_ops = &lapic_timer_ops;
        apic->lapic_timer.kvm = vcpu->kvm;
-        apic->lapic_timer.vcpu_id = vcpu->vcpu_id;
+        apic->lapic_timer.vcpu = vcpu;
        apic->base_address = APIC_DEFAULT_PHYS_BASE;
        vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
        kvm_lapic_reset(vcpu);
-        apic->dev.read = apic_mmio_read;
+        kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
-        apic->dev.write = apic_mmio_write;
-        apic->dev.in_range = apic_mmio_range;
-        apic->dev.private = apic;
        return 0;
 nomem_free_apic:
@@ -962,7 +1088,6 @@ nomem_free_apic:
 nomem:
        return -ENOMEM;
 }
-EXPORT_SYMBOL_GPL(kvm_create_lapic);
 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
 {
@@ -985,7 +1110,7 @@ int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
        u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
        int r = 0;
-        if (vcpu->vcpu_id == 0) {
+        if (kvm_vcpu_is_bsp(vcpu)) {
                if (!apic_hw_enabled(vcpu->arch.apic))
                        r = 1;
                if ((lvt0 & APIC_LVT_MASKED) == 0 &&
@@ -1025,7 +1150,8 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
        apic->base_address = vcpu->arch.apic_base &
                             MSR_IA32_APICBASE_BASE;
-        apic_set_reg(apic, APIC_LVR, APIC_VERSION);
+        kvm_apic_set_version(vcpu);
        apic_update_ppr(apic);
        hrtimer_cancel(&apic->lapic_timer.timer);
        update_divide_count(apic);
@@ -1092,3 +1218,35 @@ void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
        vcpu->arch.apic->vapic_addr = vapic_addr;
 }
+int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        u32 reg = (msr - APIC_BASE_MSR) << 4;
+        if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
+                return 1;
+        /* if this is ICR write vector before command */
+        if (msr == 0x830)
+                apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
+        return apic_reg_write(apic, reg, (u32)data);
+}
+int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
+{
+        struct kvm_lapic *apic = vcpu->arch.apic;
+        u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
+        if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
+                return 1;
+        if (apic_reg_read(apic, reg, 4, &low))
+                return 1;
+        if (msr == 0x830)
+                apic_reg_read(apic, APIC_ICR2, 4, &high);
+        *data = (((u64)high) << 32) | low;
+        return 0;
+}
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index a587f8349c46..40010b09c4aa 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -12,6 +12,7 @@ struct kvm_lapic {
        struct kvm_timer lapic_timer;
        u32 divide_count;
        struct kvm_vcpu *vcpu;
+        bool irr_pending;
        struct page *regs_page;
        void *regs;
        gpa_t vapic_addr;
@@ -28,6 +29,7 @@ u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu);
 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8);
 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value);
 u64 kvm_lapic_get_base(struct kvm_vcpu *vcpu);
+void kvm_apic_set_version(struct kvm_vcpu *vcpu);
 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest);
 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda);
@@ -44,4 +46,6 @@ void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr);
 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu);
 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu);
+int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data);
+int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data);
 #endif
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 0ef5bb2b4043..eca41ae9f453 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -18,6 +18,7 @@
 */
 #include "mmu.h"
+#include "kvm_cache_regs.h"
 #include <linux/kvm_host.h>
 #include <linux/types.h>
@@ -107,6 +108,9 @@ module_param(oos_shadow, bool, 0644);
 #define PT32_LEVEL_MASK(level) \
                (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
+#define PT32_LVL_OFFSET_MASK(level) \
+        (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
+                                                * PT32_LEVEL_BITS))) - 1))
 #define PT32_INDEX(address, level)\
        (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
@@ -115,10 +119,19 @@ module_param(oos_shadow, bool, 0644);
 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
 #define PT64_DIR_BASE_ADDR_MASK \
        (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
+#define PT64_LVL_ADDR_MASK(level) \
+        (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
+                                                * PT64_LEVEL_BITS))) - 1))
+#define PT64_LVL_OFFSET_MASK(level) \
+        (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
+                                                * PT64_LEVEL_BITS))) - 1))
 #define PT32_BASE_ADDR_MASK PAGE_MASK
 #define PT32_DIR_BASE_ADDR_MASK \
        (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
+#define PT32_LVL_ADDR_MASK(level) \
+        (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
+                                            * PT32_LEVEL_BITS))) - 1))
 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
                        | PT64_NX_MASK)
@@ -129,6 +142,7 @@ module_param(oos_shadow, bool, 0644);
 #define PFERR_RSVD_MASK (1U << 3)
 #define PFERR_FETCH_MASK (1U << 4)
+#define PT_PDPE_LEVEL 3
 #define PT_DIRECTORY_LEVEL 2
 #define PT_PAGE_TABLE_LEVEL 1
@@ -139,10 +153,13 @@ module_param(oos_shadow, bool, 0644);
 #define ACC_USER_MASK    PT_USER_MASK
 #define ACC_ALL          (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
+#define CREATE_TRACE_POINTS
+#include "mmutrace.h"
 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
 struct kvm_rmap_desc {
-        u64 *shadow_ptes[RMAP_EXT];
+        u64 *sptes[RMAP_EXT];
        struct kvm_rmap_desc *more;
 };
@@ -239,16 +256,25 @@ static int is_writeble_pte(unsigned long pte)
        return pte & PT_WRITABLE_MASK;
 }
-static int is_dirty_pte(unsigned long pte)
+static int is_dirty_gpte(unsigned long pte)
 {
-        return pte & shadow_dirty_mask;
+        return pte & PT_DIRTY_MASK;
 }
-static int is_rmap_pte(u64 pte)
+static int is_rmap_spte(u64 pte)
 {
        return is_shadow_present_pte(pte);
 }
+static int is_last_spte(u64 pte, int level)
+{
+        if (level == PT_PAGE_TABLE_LEVEL)
+                return 1;
+        if (is_large_pte(pte))
+                return 1;
+        return 0;
+}
 static pfn_t spte_to_pfn(u64 pte)
 {
        return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
@@ -261,7 +287,7 @@ static gfn_t pse36_gfn_delta(u32 gpte)
        return (gpte & PT32_DIR_PSE36_MASK) << shift;
 }
-static void set_shadow_pte(u64 *sptep, u64 spte)
+static void __set_spte(u64 *sptep, u64 spte)
 {
 #ifdef CONFIG_X86_64
        set_64bit((unsigned long *)sptep, spte);
@@ -380,37 +406,52 @@ static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
 * Return the pointer to the largepage write count for a given
 * gfn, handling slots that are not large page aligned.
 */
-static int *slot_largepage_idx(gfn_t gfn, struct kvm_memory_slot *slot)
+static int *slot_largepage_idx(gfn_t gfn,
+                               struct kvm_memory_slot *slot,
+                               int level)
 {
        unsigned long idx;
-        idx = (gfn / KVM_PAGES_PER_HPAGE) -
+        idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
-              (slot->base_gfn / KVM_PAGES_PER_HPAGE);
+              (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
-        return &slot->lpage_info[idx].write_count;
+        return &slot->lpage_info[level - 2][idx].write_count;
 }
 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
 {
+        struct kvm_memory_slot *slot;
        int *write_count;
+        int i;
        gfn = unalias_gfn(kvm, gfn);
-        write_count = slot_largepage_idx(gfn,
-                                         gfn_to_memslot_unaliased(kvm, gfn));
+        slot = gfn_to_memslot_unaliased(kvm, gfn);
-        *write_count += 1;
+        for (i = PT_DIRECTORY_LEVEL;
+             i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
+                write_count   = slot_largepage_idx(gfn, slot, i);
+                *write_count += 1;
+        }
 }
 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
 {
+        struct kvm_memory_slot *slot;
        int *write_count;
+        int i;
        gfn = unalias_gfn(kvm, gfn);
-        write_count = slot_largepage_idx(gfn,
+        for (i = PT_DIRECTORY_LEVEL;
-                                         gfn_to_memslot_unaliased(kvm, gfn));
+             i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
-        *write_count -= 1;
+                slot          = gfn_to_memslot_unaliased(kvm, gfn);
-        WARN_ON(*write_count < 0);
+                write_count   = slot_largepage_idx(gfn, slot, i);
+                *write_count -= 1;
+                WARN_ON(*write_count < 0);
+        }
 }
-static int has_wrprotected_page(struct kvm *kvm, gfn_t gfn)
+static int has_wrprotected_page(struct kvm *kvm,
+                                gfn_t gfn,
+                                int level)
 {
        struct kvm_memory_slot *slot;
        int *largepage_idx;
@@ -418,47 +459,67 @@ static int has_wrprotected_page(struct kvm *kvm, gfn_t gfn)
        gfn = unalias_gfn(kvm, gfn);
        slot = gfn_to_memslot_unaliased(kvm, gfn);
        if (slot) {
-                largepage_idx = slot_largepage_idx(gfn, slot);
+                largepage_idx = slot_largepage_idx(gfn, slot, level);
                return *largepage_idx;
        }
        return 1;
 }
-static int host_largepage_backed(struct kvm *kvm, gfn_t gfn)
+static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
 {
+        unsigned long page_size = PAGE_SIZE;
        struct vm_area_struct *vma;
        unsigned long addr;
-        int ret = 0;
+        int i, ret = 0;
        addr = gfn_to_hva(kvm, gfn);
        if (kvm_is_error_hva(addr))
-                return ret;
+                return page_size;
        down_read(&current->mm->mmap_sem);
        vma = find_vma(current->mm, addr);
-        if (vma && is_vm_hugetlb_page(vma))
+        if (!vma)
-                ret = 1;
+                goto out;
+        page_size = vma_kernel_pagesize(vma);
+out:
        up_read(&current->mm->mmap_sem);
+        for (i = PT_PAGE_TABLE_LEVEL;
+             i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
+                if (page_size >= KVM_HPAGE_SIZE(i))
+                        ret = i;
+                else
+                        break;
+        }
        return ret;
 }
-static int is_largepage_backed(struct kvm_vcpu *vcpu, gfn_t large_gfn)
+static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 {
        struct kvm_memory_slot *slot;
+        int host_level;
-        if (has_wrprotected_page(vcpu->kvm, large_gfn))
+        int level = PT_PAGE_TABLE_LEVEL;
-                return 0;
-        if (!host_largepage_backed(vcpu->kvm, large_gfn))
-                return 0;
        slot = gfn_to_memslot(vcpu->kvm, large_gfn);
        if (slot && slot->dirty_bitmap)
-                return 0;
+                return PT_PAGE_TABLE_LEVEL;
-        return 1;
+        host_level = host_mapping_level(vcpu->kvm, large_gfn);
+        if (host_level == PT_PAGE_TABLE_LEVEL)
+                return host_level;
+        for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level) {
+                if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
+                        break;
+        }
+        return level - 1;
 }
 /*
@@ -466,19 +527,19 @@ static int is_largepage_backed(struct kvm_vcpu *vcpu, gfn_t large_gfn)
 * Note: gfn must be unaliased before this function get called
 */
-static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int lpage)
+static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
 {
        struct kvm_memory_slot *slot;
        unsigned long idx;
        slot = gfn_to_memslot(kvm, gfn);
-        if (!lpage)
+        if (likely(level == PT_PAGE_TABLE_LEVEL))
                return &slot->rmap[gfn - slot->base_gfn];
-        idx = (gfn / KVM_PAGES_PER_HPAGE) -
+        idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
-              (slot->base_gfn / KVM_PAGES_PER_HPAGE);
+                (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
-        return &slot->lpage_info[idx].rmap_pde;
+        return &slot->lpage_info[level - 2][idx].rmap_pde;
 }
 /*
@@ -494,42 +555,42 @@ static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int lpage)
 * the spte was not added.
 *
 */
-static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn, int lpage)
+static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 {
        struct kvm_mmu_page *sp;
        struct kvm_rmap_desc *desc;
        unsigned long *rmapp;
        int i, count = 0;
-        if (!is_rmap_pte(*spte))
+        if (!is_rmap_spte(*spte))
                return count;
        gfn = unalias_gfn(vcpu->kvm, gfn);
        sp = page_header(__pa(spte));
        sp->gfns[spte - sp->spt] = gfn;
-        rmapp = gfn_to_rmap(vcpu->kvm, gfn, lpage);
+        rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
        if (!*rmapp) {
                rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
                *rmapp = (unsigned long)spte;
        } else if (!(*rmapp & 1)) {
                rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
                desc = mmu_alloc_rmap_desc(vcpu);
-                desc->shadow_ptes[0] = (u64 *)*rmapp;
+                desc->sptes[0] = (u64 *)*rmapp;
-                desc->shadow_ptes[1] = spte;
+                desc->sptes[1] = spte;
                *rmapp = (unsigned long)desc | 1;
        } else {
                rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
                desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
-                while (desc->shadow_ptes[RMAP_EXT-1] && desc->more) {
+                while (desc->sptes[RMAP_EXT-1] && desc->more) {
                        desc = desc->more;
                        count += RMAP_EXT;
                }
-                if (desc->shadow_ptes[RMAP_EXT-1]) {
+                if (desc->sptes[RMAP_EXT-1]) {
                        desc->more = mmu_alloc_rmap_desc(vcpu);
                        desc = desc->more;
                }
-                for (i = 0; desc->shadow_ptes[i]; ++i)
+                for (i = 0; desc->sptes[i]; ++i)
                        ;
-                desc->shadow_ptes[i] = spte;
+                desc->sptes[i] = spte;
        }
        return count;
 }
@@ -541,14 +602,14 @@ static void rmap_desc_remove_entry(unsigned long *rmapp,
 {
        int j;
-        for (j = RMAP_EXT - 1; !desc->shadow_ptes[j] && j > i; --j)
+        for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
                ;
-        desc->shadow_ptes[i] = desc->shadow_ptes[j];
+        desc->sptes[i] = desc->sptes[j];
-        desc->shadow_ptes[j] = NULL;
+        desc->sptes[j] = NULL;
        if (j != 0)
                return;
        if (!prev_desc && !desc->more)
-                *rmapp = (unsigned long)desc->shadow_ptes[0];
+                *rmapp = (unsigned long)desc->sptes[0];
        else
                if (prev_desc)
                        prev_desc->more = desc->more;
@@ -566,7 +627,7 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
        unsigned long *rmapp;
        int i;
-        if (!is_rmap_pte(*spte))
+        if (!is_rmap_spte(*spte))
                return;
        sp = page_header(__pa(spte));
        pfn = spte_to_pfn(*spte);
@@ -576,7 +637,7 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
                kvm_release_pfn_dirty(pfn);
        else
                kvm_release_pfn_clean(pfn);
-        rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], is_large_pte(*spte));
+        rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
        if (!*rmapp) {
                printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
                BUG();
@@ -593,8 +654,8 @@ static void rmap_remove(struct kvm *kvm, u64 *spte)
                desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
                prev_desc = NULL;
                while (desc) {
-                        for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i)
+                        for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
-                                if (desc->shadow_ptes[i] == spte) {
+                                if (desc->sptes[i] == spte) {
                                        rmap_desc_remove_entry(rmapp,
                                                               desc, i,
                                                               prev_desc);
@@ -625,10 +686,10 @@ static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
        prev_desc = NULL;
        prev_spte = NULL;
        while (desc) {
-                for (i = 0; i < RMAP_EXT && desc->shadow_ptes[i]; ++i) {
+                for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
                        if (prev_spte == spte)
-                                return desc->shadow_ptes[i];
+                                return desc->sptes[i];
-                        prev_spte = desc->shadow_ptes[i];
+                        prev_spte = desc->sptes[i];
                }
                desc = desc->more;
        }
@@ -639,10 +700,10 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
 {
        unsigned long *rmapp;
        u64 *spte;
-        int write_protected = 0;
+        int i, write_protected = 0;
        gfn = unalias_gfn(kvm, gfn);
-        rmapp = gfn_to_rmap(kvm, gfn, 0);
+        rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
        spte = rmap_next(kvm, rmapp, NULL);
        while (spte) {
@@ -650,7 +711,7 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
                BUG_ON(!(*spte & PT_PRESENT_MASK));
                rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
                if (is_writeble_pte(*spte)) {
-                        set_shadow_pte(spte, *spte & ~PT_WRITABLE_MASK);
+                        __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
                        write_protected = 1;
                }
                spte = rmap_next(kvm, rmapp, spte);
@@ -664,21 +725,24 @@ static int rmap_write_protect(struct kvm *kvm, u64 gfn)
        }
        /* check for huge page mappings */
-        rmapp = gfn_to_rmap(kvm, gfn, 1);
+        for (i = PT_DIRECTORY_LEVEL;
-        spte = rmap_next(kvm, rmapp, NULL);
+             i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
-        while (spte) {
+                rmapp = gfn_to_rmap(kvm, gfn, i);
-                BUG_ON(!spte);
+                spte = rmap_next(kvm, rmapp, NULL);
-                BUG_ON(!(*spte & PT_PRESENT_MASK));
+                while (spte) {
-                BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
+                        BUG_ON(!spte);
-                pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
+                        BUG_ON(!(*spte & PT_PRESENT_MASK));
-                if (is_writeble_pte(*spte)) {
+                        BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
-                        rmap_remove(kvm, spte);
+                        pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
-                        --kvm->stat.lpages;
+                        if (is_writeble_pte(*spte)) {
-                        set_shadow_pte(spte, shadow_trap_nonpresent_pte);
+                                rmap_remove(kvm, spte);
-                        spte = NULL;
+                                --kvm->stat.lpages;
-                        write_protected = 1;
+                                __set_spte(spte, shadow_trap_nonpresent_pte);
+                                spte = NULL;
+                                write_protected = 1;
+                        }
+                        spte = rmap_next(kvm, rmapp, spte);
                }
-                spte = rmap_next(kvm, rmapp, spte);
        }
        return write_protected;
@@ -693,7 +757,7 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp)
                BUG_ON(!(*spte & PT_PRESENT_MASK));
                rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
                rmap_remove(kvm, spte);
-                set_shadow_pte(spte, shadow_trap_nonpresent_pte);
+                __set_spte(spte, shadow_trap_nonpresent_pte);
                need_tlb_flush = 1;
        }
        return need_tlb_flush;
@@ -702,7 +766,7 @@ static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp)
 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
                          int (*handler)(struct kvm *kvm, unsigned long *rmapp))
 {
-        int i;
+        int i, j;
        int retval = 0;
        /*
@@ -721,11 +785,15 @@ static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
                end = start + (memslot->npages << PAGE_SHIFT);
                if (hva >= start && hva < end) {
                        gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
                        retval |= handler(kvm, &memslot->rmap[gfn_offset]);
-                        retval |= handler(kvm,
-                                          &memslot->lpage_info[
+                        for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
-                                                  gfn_offset /
+                                int idx = gfn_offset;
-                                                  KVM_PAGES_PER_HPAGE].rmap_pde);
+                                idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
+                                retval |= handler(kvm,
+                                        &memslot->lpage_info[j][idx].rmap_pde);
+                        }
                }
        }
@@ -763,12 +831,15 @@ static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp)
 #define RMAP_RECYCLE_THRESHOLD 1000
-static void rmap_recycle(struct kvm_vcpu *vcpu, gfn_t gfn, int lpage)
+static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
 {
        unsigned long *rmapp;
+        struct kvm_mmu_page *sp;
+        sp = page_header(__pa(spte));
        gfn = unalias_gfn(vcpu->kvm, gfn);
-        rmapp = gfn_to_rmap(vcpu->kvm, gfn, lpage);
+        rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
        kvm_unmap_rmapp(vcpu->kvm, rmapp);
        kvm_flush_remote_tlbs(vcpu->kvm);
@@ -1109,6 +1180,7 @@ static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
                return 1;
        }
+        trace_kvm_mmu_sync_page(sp);
        if (rmap_write_protect(vcpu->kvm, sp->gfn))
                kvm_flush_remote_tlbs(vcpu->kvm);
        kvm_unlink_unsync_page(vcpu->kvm, sp);
@@ -1231,8 +1303,6 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
                role.quadrant = quadrant;
        }
-        pgprintk("%s: looking gfn %lx role %x\n", __func__,
-                 gfn, role.word);
        index = kvm_page_table_hashfn(gfn);
        bucket = &vcpu->kvm->arch.mmu_page_hash[index];
        hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
@@ -1249,14 +1319,13 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                                set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
                                kvm_mmu_mark_parents_unsync(vcpu, sp);
                        }
-                        pgprintk("%s: found\n", __func__);
+                        trace_kvm_mmu_get_page(sp, false);
                        return sp;
                }
        ++vcpu->kvm->stat.mmu_cache_miss;
        sp = kvm_mmu_alloc_page(vcpu, parent_pte);
        if (!sp)
                return sp;
-        pgprintk("%s: adding gfn %lx role %x\n", __func__, gfn, role.word);
        sp->gfn = gfn;
        sp->role = role;
        hlist_add_head(&sp->hash_link, bucket);
@@ -1269,6 +1338,7 @@ static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
                vcpu->arch.mmu.prefetch_page(vcpu, sp);
        else
                nonpaging_prefetch_page(vcpu, sp);
+        trace_kvm_mmu_get_page(sp, true);
        return sp;
 }
@@ -1292,6 +1362,11 @@ static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
 {
        if (iterator->level < PT_PAGE_TABLE_LEVEL)
                return false;
+        if (iterator->level == PT_PAGE_TABLE_LEVEL)
+                if (is_large_pte(*iterator->sptep))
+                        return false;
        iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
        iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
        return true;
@@ -1312,25 +1387,17 @@ static void kvm_mmu_page_unlink_children(struct kvm *kvm,
        pt = sp->spt;
-        if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
-                for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
-                        if (is_shadow_present_pte(pt[i]))
-                                rmap_remove(kvm, &pt[i]);
-                        pt[i] = shadow_trap_nonpresent_pte;
-                }
-                return;
-        }
        for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
                ent = pt[i];
                if (is_shadow_present_pte(ent)) {
-                        if (!is_large_pte(ent)) {
+                        if (!is_last_spte(ent, sp->role.level)) {
                                ent &= PT64_BASE_ADDR_MASK;
                                mmu_page_remove_parent_pte(page_header(ent),
                                                           &pt[i]);
                        } else {
-                                --kvm->stat.lpages;
+                                if (is_large_pte(ent))
+                                        --kvm->stat.lpages;
                                rmap_remove(kvm, &pt[i]);
                        }
                }
@@ -1346,10 +1413,10 @@ static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
 {
        int i;
+        struct kvm_vcpu *vcpu;
-        for (i = 0; i < KVM_MAX_VCPUS; ++i)
+        kvm_for_each_vcpu(i, vcpu, kvm)
-                if (kvm->vcpus[i])
+                vcpu->arch.last_pte_updated = NULL;
-                        kvm->vcpus[i]->arch.last_pte_updated = NULL;
 }
 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
@@ -1368,7 +1435,7 @@ static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
                }
                BUG_ON(!parent_pte);
                kvm_mmu_put_page(sp, parent_pte);
-                set_shadow_pte(parent_pte, shadow_trap_nonpresent_pte);
+                __set_spte(parent_pte, shadow_trap_nonpresent_pte);
        }
 }
@@ -1400,6 +1467,8 @@ static int mmu_zap_unsync_children(struct kvm *kvm,
 static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
 {
        int ret;
+        trace_kvm_mmu_zap_page(sp);
        ++kvm->stat.mmu_shadow_zapped;
        ret = mmu_zap_unsync_children(kvm, sp);
        kvm_mmu_page_unlink_children(kvm, sp);
@@ -1516,7 +1585,7 @@ static void mmu_convert_notrap(struct kvm_mmu_page *sp)
        for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
                if (pt[i] == shadow_notrap_nonpresent_pte)
-                        set_shadow_pte(&pt[i], shadow_trap_nonpresent_pte);
+                        __set_spte(&pt[i], shadow_trap_nonpresent_pte);
        }
 }
@@ -1646,6 +1715,7 @@ static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
        struct kvm_mmu_page *s;
        struct hlist_node *node, *n;
+        trace_kvm_mmu_unsync_page(sp);
        index = kvm_page_table_hashfn(sp->gfn);
        bucket = &vcpu->kvm->arch.mmu_page_hash[index];
        /* don't unsync if pagetable is shadowed with multiple roles */
@@ -1682,9 +1752,9 @@ static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
        return 0;
 }
-static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
+static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                    unsigned pte_access, int user_fault,
-                    int write_fault, int dirty, int largepage,
+                    int write_fault, int dirty, int level,
                    gfn_t gfn, pfn_t pfn, bool speculative,
                    bool can_unsync)
 {
@@ -1707,7 +1777,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
                spte |= shadow_nx_mask;
        if (pte_access & ACC_USER_MASK)
                spte |= shadow_user_mask;
-        if (largepage)
+        if (level > PT_PAGE_TABLE_LEVEL)
                spte |= PT_PAGE_SIZE_MASK;
        if (tdp_enabled)
                spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
@@ -1718,7 +1788,8 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
        if ((pte_access & ACC_WRITE_MASK)
            || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
-                if (largepage && has_wrprotected_page(vcpu->kvm, gfn)) {
+                if (level > PT_PAGE_TABLE_LEVEL &&
+                    has_wrprotected_page(vcpu->kvm, gfn, level)) {
                        ret = 1;
                        spte = shadow_trap_nonpresent_pte;
                        goto set_pte;
@@ -1732,7 +1803,7 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
                 * is responsibility of mmu_get_page / kvm_sync_page.
                 * Same reasoning can be applied to dirty page accounting.
                 */
-                if (!can_unsync && is_writeble_pte(*shadow_pte))
+                if (!can_unsync && is_writeble_pte(*sptep))
                        goto set_pte;
                if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
@@ -1749,65 +1820,67 @@ static int set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
                mark_page_dirty(vcpu->kvm, gfn);
 set_pte:
-        set_shadow_pte(shadow_pte, spte);
+        __set_spte(sptep, spte);
        return ret;
 }
-static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
+static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
                         unsigned pt_access, unsigned pte_access,
                         int user_fault, int write_fault, int dirty,
-                         int *ptwrite, int largepage, gfn_t gfn,
+                         int *ptwrite, int level, gfn_t gfn,
                         pfn_t pfn, bool speculative)
 {
        int was_rmapped = 0;
-        int was_writeble = is_writeble_pte(*shadow_pte);
+        int was_writeble = is_writeble_pte(*sptep);
        int rmap_count;
        pgprintk("%s: spte %llx access %x write_fault %d"
                 " user_fault %d gfn %lx\n",
-                 __func__, *shadow_pte, pt_access,
+                 __func__, *sptep, pt_access,
                 write_fault, user_fault, gfn);
-        if (is_rmap_pte(*shadow_pte)) {
+        if (is_rmap_spte(*sptep)) {
                /*
                 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
                 * the parent of the now unreachable PTE.
                 */
-                if (largepage && !is_large_pte(*shadow_pte)) {
+                if (level > PT_PAGE_TABLE_LEVEL &&
+                    !is_large_pte(*sptep)) {
                        struct kvm_mmu_page *child;
-                        u64 pte = *shadow_pte;
+                        u64 pte = *sptep;
                        child = page_header(pte & PT64_BASE_ADDR_MASK);
-                        mmu_page_remove_parent_pte(child, shadow_pte);
+                        mmu_page_remove_parent_pte(child, sptep);
-                } else if (pfn != spte_to_pfn(*shadow_pte)) {
+                } else if (pfn != spte_to_pfn(*sptep)) {
                        pgprintk("hfn old %lx new %lx\n",
-                                 spte_to_pfn(*shadow_pte), pfn);
+                                 spte_to_pfn(*sptep), pfn);
-                        rmap_remove(vcpu->kvm, shadow_pte);
+                        rmap_remove(vcpu->kvm, sptep);
                } else
                        was_rmapped = 1;
        }
-        if (set_spte(vcpu, shadow_pte, pte_access, user_fault, write_fault,
-                      dirty, largepage, gfn, pfn, speculative, true)) {
+        if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
+                      dirty, level, gfn, pfn, speculative, true)) {
                if (write_fault)
                        *ptwrite = 1;
                kvm_x86_ops->tlb_flush(vcpu);
        }
-        pgprintk("%s: setting spte %llx\n", __func__, *shadow_pte);
+        pgprintk("%s: setting spte %llx\n", __func__, *sptep);
        pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
-                 is_large_pte(*shadow_pte)? "2MB" : "4kB",
+                 is_large_pte(*sptep)? "2MB" : "4kB",
-                 is_present_pte(*shadow_pte)?"RW":"R", gfn,
+                 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
-                 *shadow_pte, shadow_pte);
+                 *sptep, sptep);
-        if (!was_rmapped && is_large_pte(*shadow_pte))
+        if (!was_rmapped && is_large_pte(*sptep))
                ++vcpu->kvm->stat.lpages;
-        page_header_update_slot(vcpu->kvm, shadow_pte, gfn);
+        page_header_update_slot(vcpu->kvm, sptep, gfn);
        if (!was_rmapped) {
-                rmap_count = rmap_add(vcpu, shadow_pte, gfn, largepage);
+                rmap_count = rmap_add(vcpu, sptep, gfn);
-                if (!is_rmap_pte(*shadow_pte))
+                if (!is_rmap_spte(*sptep))
                        kvm_release_pfn_clean(pfn);
                if (rmap_count > RMAP_RECYCLE_THRESHOLD)
-                        rmap_recycle(vcpu, gfn, largepage);
+                        rmap_recycle(vcpu, sptep, gfn);
        } else {
                if (was_writeble)
                        kvm_release_pfn_dirty(pfn);
@@ -1815,7 +1888,7 @@ static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *shadow_pte,
                        kvm_release_pfn_clean(pfn);
        }
        if (speculative) {
-                vcpu->arch.last_pte_updated = shadow_pte;
+                vcpu->arch.last_pte_updated = sptep;
                vcpu->arch.last_pte_gfn = gfn;
        }
 }
@@ -1825,7 +1898,7 @@ static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
 }
 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
-                        int largepage, gfn_t gfn, pfn_t pfn)
+                        int level, gfn_t gfn, pfn_t pfn)
 {
        struct kvm_shadow_walk_iterator iterator;
        struct kvm_mmu_page *sp;
@@ -1833,11 +1906,10 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
        gfn_t pseudo_gfn;
        for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
-                if (iterator.level == PT_PAGE_TABLE_LEVEL
+                if (iterator.level == level) {
-                    || (largepage && iterator.level == PT_DIRECTORY_LEVEL)) {
                        mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
                                     0, write, 1, &pt_write,
-                                     largepage, gfn, pfn, false);
+                                     level, gfn, pfn, false);
                        ++vcpu->stat.pf_fixed;
                        break;
                }
@@ -1853,10 +1925,10 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
                                return -ENOMEM;
                        }
-                        set_shadow_pte(iterator.sptep,
+                        __set_spte(iterator.sptep,
-                                       __pa(sp->spt)
+                                   __pa(sp->spt)
-                                       | PT_PRESENT_MASK | PT_WRITABLE_MASK
+                                   | PT_PRESENT_MASK | PT_WRITABLE_MASK
-                                       | shadow_user_mask | shadow_x_mask);
+                                   | shadow_user_mask | shadow_x_mask);
                }
        }
        return pt_write;
@@ -1865,14 +1937,20 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
 {
        int r;
-        int largepage = 0;
+        int level;
        pfn_t pfn;
        unsigned long mmu_seq;
-        if (is_largepage_backed(vcpu, gfn & ~(KVM_PAGES_PER_HPAGE-1))) {
+        level = mapping_level(vcpu, gfn);
-                gfn &= ~(KVM_PAGES_PER_HPAGE-1);
-                largepage = 1;
+        /*
-        }
+         * This path builds a PAE pagetable - so we can map 2mb pages at
+         * maximum. Therefore check if the level is larger than that.
+         */
+        if (level > PT_DIRECTORY_LEVEL)
+                level = PT_DIRECTORY_LEVEL;
+        gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
        mmu_seq = vcpu->kvm->mmu_notifier_seq;
        smp_rmb();
@@ -1888,7 +1966,7 @@ static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
        if (mmu_notifier_retry(vcpu, mmu_seq))
                goto out_unlock;
        kvm_mmu_free_some_pages(vcpu);
-        r = __direct_map(vcpu, v, write, largepage, gfn, pfn);
+        r = __direct_map(vcpu, v, write, level, gfn, pfn);
        spin_unlock(&vcpu->kvm->mmu_lock);
@@ -1954,6 +2032,7 @@ static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
        gfn_t root_gfn;
        struct kvm_mmu_page *sp;
        int direct = 0;
+        u64 pdptr;
        root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
@@ -1981,11 +2060,12 @@ static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
                ASSERT(!VALID_PAGE(root));
                if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
-                        if (!is_present_pte(vcpu->arch.pdptrs[i])) {
+                        pdptr = kvm_pdptr_read(vcpu, i);
+                        if (!is_present_gpte(pdptr)) {
                                vcpu->arch.mmu.pae_root[i] = 0;
                                continue;
                        }
-                        root_gfn = vcpu->arch.pdptrs[i] >> PAGE_SHIFT;
+                        root_gfn = pdptr >> PAGE_SHIFT;
                } else if (vcpu->arch.mmu.root_level == 0)
                        root_gfn = 0;
                if (mmu_check_root(vcpu, root_gfn))
@@ -2062,7 +2142,7 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
 {
        pfn_t pfn;
        int r;
-        int largepage = 0;
+        int level;
        gfn_t gfn = gpa >> PAGE_SHIFT;
        unsigned long mmu_seq;
@@ -2073,10 +2153,10 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
        if (r)
                return r;
-        if (is_largepage_backed(vcpu, gfn & ~(KVM_PAGES_PER_HPAGE-1))) {
+        level = mapping_level(vcpu, gfn);
-                gfn &= ~(KVM_PAGES_PER_HPAGE-1);
-                largepage = 1;
+        gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
-        }
        mmu_seq = vcpu->kvm->mmu_notifier_seq;
        smp_rmb();
        pfn = gfn_to_pfn(vcpu->kvm, gfn);
@@ -2089,7 +2169,7 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
                goto out_unlock;
        kvm_mmu_free_some_pages(vcpu);
        r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
-                         largepage, gfn, pfn);
+                         level, gfn, pfn);
        spin_unlock(&vcpu->kvm->mmu_lock);
        return r;
@@ -2206,7 +2286,9 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
                context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
                        rsvd_bits(maxphyaddr, 51);
                context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
-                context->rsvd_bits_mask[1][2] = context->rsvd_bits_mask[0][2];
+                context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
+                        rsvd_bits(maxphyaddr, 51) |
+                        rsvd_bits(13, 29);
                context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
                        rsvd_bits(maxphyaddr, 51) |
                        rsvd_bits(13, 20);              /* large page */
@@ -2357,8 +2439,8 @@ int kvm_mmu_load(struct kvm_vcpu *vcpu)
        spin_unlock(&vcpu->kvm->mmu_lock);
        if (r)
                goto out;
+        /* set_cr3() should ensure TLB has been flushed */
        kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
-        kvm_mmu_flush_tlb(vcpu);
 out:
        return r;
 }
@@ -2378,15 +2460,14 @@ static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
        pte = *spte;
        if (is_shadow_present_pte(pte)) {
-                if (sp->role.level == PT_PAGE_TABLE_LEVEL ||
+                if (is_last_spte(pte, sp->role.level))
-                    is_large_pte(pte))
                        rmap_remove(vcpu->kvm, spte);
                else {
                        child = page_header(pte & PT64_BASE_ADDR_MASK);
                        mmu_page_remove_parent_pte(child, spte);
                }
        }
-        set_shadow_pte(spte, shadow_trap_nonpresent_pte);
+        __set_spte(spte, shadow_trap_nonpresent_pte);
        if (is_large_pte(pte))
                --vcpu->kvm->stat.lpages;
 }
@@ -2397,11 +2478,8 @@ static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
                                  const void *new)
 {
        if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
-                if (!vcpu->arch.update_pte.largepage ||
+                ++vcpu->kvm->stat.mmu_pde_zapped;
-                    sp->role.glevels == PT32_ROOT_LEVEL) {
+                return;
-                        ++vcpu->kvm->stat.mmu_pde_zapped;
-                        return;
-                }
        }
        ++vcpu->kvm->stat.mmu_pte_updated;
@@ -2447,8 +2525,6 @@ static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
        u64 gpte = 0;
        pfn_t pfn;
-        vcpu->arch.update_pte.largepage = 0;
        if (bytes != 4 && bytes != 8)
                return;
@@ -2472,14 +2548,10 @@ static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
                if ((bytes == 4) && (gpa % 4 == 0))
                        memcpy((void *)&gpte, new, 4);
        }
-        if (!is_present_pte(gpte))
+        if (!is_present_gpte(gpte))
                return;
        gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
-        if (is_large_pte(gpte) && is_largepage_backed(vcpu, gfn)) {
-                gfn &= ~(KVM_PAGES_PER_HPAGE-1);
-                vcpu->arch.update_pte.largepage = 1;
-        }
        vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
        smp_rmb();
        pfn = gfn_to_pfn(vcpu->kvm, gfn);
@@ -2622,6 +2694,9 @@ int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
        gpa_t gpa;
        int r;
+        if (tdp_enabled)
+                return 0;
        gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gva);
        spin_lock(&vcpu->kvm->mmu_lock);
@@ -2633,7 +2708,8 @@ EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
 {
-        while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES) {
+        while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
+               !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
                struct kvm_mmu_page *sp;
                sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
@@ -2670,8 +2746,9 @@ int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
                ++vcpu->stat.mmio_exits;
                return 0;
        case EMULATE_FAIL:
-                kvm_report_emulation_failure(vcpu, "pagetable");
+                vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
-                return 1;
+                vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
+                return 0;
        default:
                BUG();
        }
@@ -2712,12 +2789,6 @@ static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
        ASSERT(vcpu);
-        if (vcpu->kvm->arch.n_requested_mmu_pages)
-                vcpu->kvm->arch.n_free_mmu_pages =
-                                        vcpu->kvm->arch.n_requested_mmu_pages;
-        else
-                vcpu->kvm->arch.n_free_mmu_pages =
-                                        vcpu->kvm->arch.n_alloc_mmu_pages;
        /*
         * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
         * Therefore we need to allocate shadow page tables in the first
@@ -3029,6 +3100,24 @@ out:
        return r;
 }
+int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
+{
+        struct kvm_shadow_walk_iterator iterator;
+        int nr_sptes = 0;
+        spin_lock(&vcpu->kvm->mmu_lock);
+        for_each_shadow_entry(vcpu, addr, iterator) {
+                sptes[iterator.level-1] = *iterator.sptep;
+                nr_sptes++;
+                if (!is_shadow_present_pte(*iterator.sptep))
+                        break;
+        }
+        spin_unlock(&vcpu->kvm->mmu_lock);
+        return nr_sptes;
+}
+EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
 #ifdef AUDIT
 static const char *audit_msg;
@@ -3041,6 +3130,54 @@ static gva_t canonicalize(gva_t gva)
        return gva;
 }
+typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
+                                 u64 *sptep);
+static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
+                            inspect_spte_fn fn)
+{
+        int i;
+        for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
+                u64 ent = sp->spt[i];
+                if (is_shadow_present_pte(ent)) {
+                        if (!is_last_spte(ent, sp->role.level)) {
+                                struct kvm_mmu_page *child;
+                                child = page_header(ent & PT64_BASE_ADDR_MASK);
+                                __mmu_spte_walk(kvm, child, fn);
+                        } else
+                                fn(kvm, sp, &sp->spt[i]);
+                }
+        }
+}
+static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
+{
+        int i;
+        struct kvm_mmu_page *sp;
+        if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
+                return;
+        if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
+                hpa_t root = vcpu->arch.mmu.root_hpa;
+                sp = page_header(root);
+                __mmu_spte_walk(vcpu->kvm, sp, fn);
+                return;
+        }
+        for (i = 0; i < 4; ++i) {
+                hpa_t root = vcpu->arch.mmu.pae_root[i];
+                if (root && VALID_PAGE(root)) {
+                        root &= PT64_BASE_ADDR_MASK;
+                        sp = page_header(root);
+                        __mmu_spte_walk(vcpu->kvm, sp, fn);
+                }
+        }
+        return;
+}
 static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
                                gva_t va, int level)
 {
@@ -3055,20 +3192,19 @@ static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
                        continue;
                va = canonicalize(va);
-                if (level > 1) {
+                if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
-                        if (ent == shadow_notrap_nonpresent_pte)
+                        audit_mappings_page(vcpu, ent, va, level - 1);
-                                printk(KERN_ERR "audit: (%s) nontrapping pte"
+                else {
-                                       " in nonleaf level: levels %d gva %lx"
-                                       " level %d pte %llx\n", audit_msg,
-                                       vcpu->arch.mmu.root_level, va, level, ent);
-                        else
-                                audit_mappings_page(vcpu, ent, va, level - 1);
-                } else {
                        gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, va);
                        gfn_t gfn = gpa >> PAGE_SHIFT;
                        pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
                        hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
+                        if (is_error_pfn(pfn)) {
+                                kvm_release_pfn_clean(pfn);
+                                continue;
+                        }
                        if (is_shadow_present_pte(ent)
                            && (ent & PT64_BASE_ADDR_MASK) != hpa)
                                printk(KERN_ERR "xx audit error: (%s) levels %d"
@@ -3122,7 +3258,7 @@ static int count_rmaps(struct kvm_vcpu *vcpu)
                        d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
                        while (d) {
                                for (k = 0; k < RMAP_EXT; ++k)
-                                        if (d->shadow_ptes[k])
+                                        if (d->sptes[k])
                                                ++nmaps;
                                        else
                                                break;
@@ -3133,9 +3269,48 @@ static int count_rmaps(struct kvm_vcpu *vcpu)
        return nmaps;
 }
-static int count_writable_mappings(struct kvm_vcpu *vcpu)
+void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
+{
+        unsigned long *rmapp;
+        struct kvm_mmu_page *rev_sp;
+        gfn_t gfn;
+        if (*sptep & PT_WRITABLE_MASK) {
+                rev_sp = page_header(__pa(sptep));
+                gfn = rev_sp->gfns[sptep - rev_sp->spt];
+                if (!gfn_to_memslot(kvm, gfn)) {
+                        if (!printk_ratelimit())
+                                return;
+                        printk(KERN_ERR "%s: no memslot for gfn %ld\n",
+                                         audit_msg, gfn);
+                        printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
+                                        audit_msg, sptep - rev_sp->spt,
+                                        rev_sp->gfn);
+                        dump_stack();
+                        return;
+                }
+                rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
+                                    is_large_pte(*sptep));
+                if (!*rmapp) {
+                        if (!printk_ratelimit())
+                                return;
+                        printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
+                                         audit_msg, *sptep);
+                        dump_stack();
+                }
+        }
+}
+void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
+{
+        mmu_spte_walk(vcpu, inspect_spte_has_rmap);
+}
+static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
 {
-        int nmaps = 0;
        struct kvm_mmu_page *sp;
        int i;
@@ -3152,20 +3327,16 @@ static int count_writable_mappings(struct kvm_vcpu *vcpu)
                                continue;
                        if (!(ent & PT_WRITABLE_MASK))
                                continue;
-                        ++nmaps;
+                        inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
                }
        }
-        return nmaps;
+        return;
 }
 static void audit_rmap(struct kvm_vcpu *vcpu)
 {
-        int n_rmap = count_rmaps(vcpu);
+        check_writable_mappings_rmap(vcpu);
-        int n_actual = count_writable_mappings(vcpu);
+        count_rmaps(vcpu);
-        if (n_rmap != n_actual)
-                printk(KERN_ERR "%s: (%s) rmap %d actual %d\n",
-                       __func__, audit_msg, n_rmap, n_actual);
 }
 static void audit_write_protection(struct kvm_vcpu *vcpu)
@@ -3173,20 +3344,28 @@ static void audit_write_protection(struct kvm_vcpu *vcpu)
        struct kvm_mmu_page *sp;
        struct kvm_memory_slot *slot;
        unsigned long *rmapp;
+        u64 *spte;
        gfn_t gfn;
        list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
                if (sp->role.direct)
                        continue;
+                if (sp->unsync)
+                        continue;
                gfn = unalias_gfn(vcpu->kvm, sp->gfn);
                slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
                rmapp = &slot->rmap[gfn - slot->base_gfn];
-                if (*rmapp)
-                        printk(KERN_ERR "%s: (%s) shadow page has writable"
+                spte = rmap_next(vcpu->kvm, rmapp, NULL);
-                               " mappings: gfn %lx role %x\n",
+                while (spte) {
+                        if (*spte & PT_WRITABLE_MASK)
+                                printk(KERN_ERR "%s: (%s) shadow page has "
+                                "writable mappings: gfn %lx role %x\n",
                               __func__, audit_msg, sp->gfn,
                               sp->role.word);
+                        spte = rmap_next(vcpu->kvm, rmapp, spte);
+                }
        }
 }
@@ -3198,7 +3377,9 @@ static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
        audit_msg = msg;
        audit_rmap(vcpu);
        audit_write_protection(vcpu);
-        audit_mappings(vcpu);
+        if (strcmp("pre pte write", audit_msg) != 0)
+                audit_mappings(vcpu);
+        audit_writable_sptes_have_rmaps(vcpu);
        dbg = olddbg;
 }
diff --git a/arch/x86/kvm/mmu.h b/arch/x86/kvm/mmu.h
index 3494a2fb136e..61a1b3884b49 100644
--- a/arch/x86/kvm/mmu.h
+++ b/arch/x86/kvm/mmu.h
@@ -37,6 +37,8 @@
 #define PT32_ROOT_LEVEL 2
 #define PT32E_ROOT_LEVEL 3
+int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4]);
 static inline void kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
 {
        if (unlikely(vcpu->kvm->arch.n_free_mmu_pages < KVM_MIN_FREE_MMU_PAGES))
@@ -75,7 +77,7 @@ static inline int is_paging(struct kvm_vcpu *vcpu)
        return vcpu->arch.cr0 & X86_CR0_PG;
 }
-static inline int is_present_pte(unsigned long pte)
+static inline int is_present_gpte(unsigned long pte)
 {
        return pte & PT_PRESENT_MASK;
 }
diff --git a/arch/x86/kvm/mmutrace.h b/arch/x86/kvm/mmutrace.h
new file mode 100644
index 000000000000..3e4a5c6ca2a9
--- /dev/null
+++ b/arch/x86/kvm/mmutrace.h
@@ -0,0 +1,220 @@
+#if !defined(_TRACE_KVMMMU_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_KVMMMU_H
+#include <linux/tracepoint.h>
+#include <linux/ftrace_event.h>
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM kvmmmu
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE mmutrace
+#define KVM_MMU_PAGE_FIELDS \
+        __field(__u64, gfn) \
+        __field(__u32, role) \
+        __field(__u32, root_count) \
+        __field(__u32, unsync)
+#define KVM_MMU_PAGE_ASSIGN(sp)                      \
+        __entry->gfn = sp->gfn;                      \
+        __entry->role = sp->role.word;               \
+        __entry->root_count = sp->root_count;        \
+        __entry->unsync = sp->unsync;
+#define KVM_MMU_PAGE_PRINTK() ({                                        \
+        const char *ret = p->buffer + p->len;                           \
+        static const char *access_str[] = {                             \
+                "---", "--x", "w--", "w-x", "-u-", "-ux", "wu-", "wux"  \
+        };                                                              \
+        union kvm_mmu_page_role role;                                   \
+                                                                        \
+        role.word = __entry->role;                                      \
+                                                                        \
+        trace_seq_printf(p, "sp gfn %llx %u/%u q%u%s %s%s %spge"        \
+                         " %snxe root %u %s%c",                         \
+                         __entry->gfn, role.level, role.glevels,        \
+                         role.quadrant,                                 \
+                         role.direct ? " direct" : "",                  \
+                         access_str[role.access],                       \
+                         role.invalid ? " invalid" : "",                \
+                         role.cr4_pge ? "" : "!",                       \
+                         role.nxe ? "" : "!",                           \
+                         __entry->root_count,                           \
+                         __entry->unsync ? "unsync" : "sync", 0);       \
+        ret;                                                            \
+                })
+#define kvm_mmu_trace_pferr_flags       \
+        { PFERR_PRESENT_MASK, "P" },    \
+        { PFERR_WRITE_MASK, "W" },      \
+        { PFERR_USER_MASK, "U" },       \
+        { PFERR_RSVD_MASK, "RSVD" },    \
+        { PFERR_FETCH_MASK, "F" }
+/*
+ * A pagetable walk has started
+ */
+TRACE_EVENT(
+        kvm_mmu_pagetable_walk,
+        TP_PROTO(u64 addr, int write_fault, int user_fault, int fetch_fault),
+        TP_ARGS(addr, write_fault, user_fault, fetch_fault),
+        TP_STRUCT__entry(
+                __field(__u64, addr)
+                __field(__u32, pferr)
+        ),
+        TP_fast_assign(
+                __entry->addr = addr;
+                __entry->pferr = (!!write_fault << 1) | (!!user_fault << 2)
+                                 | (!!fetch_fault << 4);
+        ),
+        TP_printk("addr %llx pferr %x %s", __entry->addr, __entry->pferr,
+                  __print_flags(__entry->pferr, "|", kvm_mmu_trace_pferr_flags))
+);
+/* We just walked a paging element */
+TRACE_EVENT(
+        kvm_mmu_paging_element,
+        TP_PROTO(u64 pte, int level),
+        TP_ARGS(pte, level),
+        TP_STRUCT__entry(
+                __field(__u64, pte)
+                __field(__u32, level)
+                ),
+        TP_fast_assign(
+                __entry->pte = pte;
+                __entry->level = level;
+                ),
+        TP_printk("pte %llx level %u", __entry->pte, __entry->level)
+);
+/* We set a pte accessed bit */
+TRACE_EVENT(
+        kvm_mmu_set_accessed_bit,
+        TP_PROTO(unsigned long table_gfn, unsigned index, unsigned size),
+        TP_ARGS(table_gfn, index, size),
+        TP_STRUCT__entry(
+                __field(__u64, gpa)
+                ),
+        TP_fast_assign(
+                __entry->gpa = ((u64)table_gfn << PAGE_SHIFT)
+                                + index * size;
+                ),
+        TP_printk("gpa %llx", __entry->gpa)
+);
+/* We set a pte dirty bit */
+TRACE_EVENT(
+        kvm_mmu_set_dirty_bit,
+        TP_PROTO(unsigned long table_gfn, unsigned index, unsigned size),
+        TP_ARGS(table_gfn, index, size),
+        TP_STRUCT__entry(
+                __field(__u64, gpa)
+                ),
+        TP_fast_assign(
+                __entry->gpa = ((u64)table_gfn << PAGE_SHIFT)
+                                + index * size;
+                ),
+        TP_printk("gpa %llx", __entry->gpa)
+);
+TRACE_EVENT(
+        kvm_mmu_walker_error,
+        TP_PROTO(u32 pferr),
+        TP_ARGS(pferr),
+        TP_STRUCT__entry(
+                __field(__u32, pferr)
+                ),
+        TP_fast_assign(
+                __entry->pferr = pferr;
+                ),
+        TP_printk("pferr %x %s", __entry->pferr,
+                  __print_flags(__entry->pferr, "|", kvm_mmu_trace_pferr_flags))
+);
+TRACE_EVENT(
+        kvm_mmu_get_page,
+        TP_PROTO(struct kvm_mmu_page *sp, bool created),
+        TP_ARGS(sp, created),
+        TP_STRUCT__entry(
+                KVM_MMU_PAGE_FIELDS
+                __field(bool, created)
+                ),
+        TP_fast_assign(
+                KVM_MMU_PAGE_ASSIGN(sp)
+                __entry->created = created;
+                ),
+        TP_printk("%s %s", KVM_MMU_PAGE_PRINTK(),
+                  __entry->created ? "new" : "existing")
+);
+TRACE_EVENT(
+        kvm_mmu_sync_page,
+        TP_PROTO(struct kvm_mmu_page *sp),
+        TP_ARGS(sp),
+        TP_STRUCT__entry(
+                KVM_MMU_PAGE_FIELDS
+                ),
+        TP_fast_assign(
+                KVM_MMU_PAGE_ASSIGN(sp)
+                ),
+        TP_printk("%s", KVM_MMU_PAGE_PRINTK())
+);
+TRACE_EVENT(
+        kvm_mmu_unsync_page,
+        TP_PROTO(struct kvm_mmu_page *sp),
+        TP_ARGS(sp),
+        TP_STRUCT__entry(
+                KVM_MMU_PAGE_FIELDS
+                ),
+        TP_fast_assign(
+                KVM_MMU_PAGE_ASSIGN(sp)
+                ),
+        TP_printk("%s", KVM_MMU_PAGE_PRINTK())
+);
+TRACE_EVENT(
+        kvm_mmu_zap_page,
+        TP_PROTO(struct kvm_mmu_page *sp),
+        TP_ARGS(sp),
+        TP_STRUCT__entry(
+                KVM_MMU_PAGE_FIELDS
+                ),
+        TP_fast_assign(
+                KVM_MMU_PAGE_ASSIGN(sp)
+                ),
+        TP_printk("%s", KVM_MMU_PAGE_PRINTK())
+);
+#endif /* _TRACE_KVMMMU_H */
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
index 67785f635399..d2fec9c12d22 100644
--- a/arch/x86/kvm/paging_tmpl.h
+++ b/arch/x86/kvm/paging_tmpl.h
@@ -27,7 +27,8 @@
        #define guest_walker guest_walker64
        #define FNAME(name) paging##64_##name
        #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
-        #define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
+        #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
+        #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
        #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
        #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
        #define PT_LEVEL_BITS PT64_LEVEL_BITS
@@ -43,7 +44,8 @@
        #define guest_walker guest_walker32
        #define FNAME(name) paging##32_##name
        #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
-        #define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
+        #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
+        #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
        #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
        #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
        #define PT_LEVEL_BITS PT32_LEVEL_BITS
@@ -53,8 +55,8 @@
        #error Invalid PTTYPE value
 #endif
-#define gpte_to_gfn FNAME(gpte_to_gfn)
+#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
-#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
+#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
 /*
 * The guest_walker structure emulates the behavior of the hardware page
@@ -71,14 +73,9 @@ struct guest_walker {
        u32 error_code;
 };
-static gfn_t gpte_to_gfn(pt_element_t gpte)
+static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
 {
-        return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
+        return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
-}
-static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
-{
-        return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
 }
 static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
@@ -125,14 +122,16 @@ static int FNAME(walk_addr)(struct guest_walker *walker,
        gpa_t pte_gpa;
        int rsvd_fault = 0;
-        pgprintk("%s: addr %lx\n", __func__, addr);
+        trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
+                                     fetch_fault);
 walk:
        walker->level = vcpu->arch.mmu.root_level;
        pte = vcpu->arch.cr3;
 #if PTTYPE == 64
        if (!is_long_mode(vcpu)) {
-                pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
+                pte = kvm_pdptr_read(vcpu, (addr >> 30) & 3);
-                if (!is_present_pte(pte))
+                trace_kvm_mmu_paging_element(pte, walker->level);
+                if (!is_present_gpte(pte))
                        goto not_present;
                --walker->level;
        }
@@ -150,12 +149,11 @@ walk:
                pte_gpa += index * sizeof(pt_element_t);
                walker->table_gfn[walker->level - 1] = table_gfn;
                walker->pte_gpa[walker->level - 1] = pte_gpa;
-                pgprintk("%s: table_gfn[%d] %lx\n", __func__,
-                         walker->level - 1, table_gfn);
                kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
+                trace_kvm_mmu_paging_element(pte, walker->level);
-                if (!is_present_pte(pte))
+                if (!is_present_gpte(pte))
                        goto not_present;
                rsvd_fault = is_rsvd_bits_set(vcpu, pte, walker->level);
@@ -175,6 +173,8 @@ walk:
 #endif
                if (!(pte & PT_ACCESSED_MASK)) {
+                        trace_kvm_mmu_set_accessed_bit(table_gfn, index,
+                                                       sizeof(pte));
                        mark_page_dirty(vcpu->kvm, table_gfn);
                        if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
                            index, pte, pte|PT_ACCESSED_MASK))
@@ -186,18 +186,24 @@ walk:
                walker->ptes[walker->level - 1] = pte;
-                if (walker->level == PT_PAGE_TABLE_LEVEL) {
+                if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
-                        walker->gfn = gpte_to_gfn(pte);
+                    ((walker->level == PT_DIRECTORY_LEVEL) &&
-                        break;
+                                (pte & PT_PAGE_SIZE_MASK)  &&
-                }
+                                (PTTYPE == 64 || is_pse(vcpu))) ||
+                    ((walker->level == PT_PDPE_LEVEL) &&
-                if (walker->level == PT_DIRECTORY_LEVEL
+                                (pte & PT_PAGE_SIZE_MASK)  &&
-                    && (pte & PT_PAGE_SIZE_MASK)
+                                is_long_mode(vcpu))) {
-                    && (PTTYPE == 64 || is_pse(vcpu))) {
+                        int lvl = walker->level;
-                        walker->gfn = gpte_to_gfn_pde(pte);
-                        walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
+                        walker->gfn = gpte_to_gfn_lvl(pte, lvl);
-                        if (PTTYPE == 32 && is_cpuid_PSE36())
+                        walker->gfn += (addr & PT_LVL_OFFSET_MASK(lvl))
+                                        >> PAGE_SHIFT;
+                        if (PTTYPE == 32 &&
+                            walker->level == PT_DIRECTORY_LEVEL &&
+                            is_cpuid_PSE36())
                                walker->gfn += pse36_gfn_delta(pte);
                        break;
                }
@@ -205,9 +211,10 @@ walk:
                --walker->level;
        }
-        if (write_fault && !is_dirty_pte(pte)) {
+        if (write_fault && !is_dirty_gpte(pte)) {
                bool ret;
+                trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
                mark_page_dirty(vcpu->kvm, table_gfn);
                ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
                            pte|PT_DIRTY_MASK);
@@ -239,6 +246,7 @@ err:
                walker->error_code |= PFERR_FETCH_MASK;
        if (rsvd_fault)
                walker->error_code |= PFERR_RSVD_MASK;
+        trace_kvm_mmu_walker_error(walker->error_code);
        return 0;
 }
@@ -248,12 +256,11 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
        pt_element_t gpte;
        unsigned pte_access;
        pfn_t pfn;
-        int largepage = vcpu->arch.update_pte.largepage;
        gpte = *(const pt_element_t *)pte;
        if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
-                if (!is_present_pte(gpte))
+                if (!is_present_gpte(gpte))
-                        set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
+                        __set_spte(spte, shadow_notrap_nonpresent_pte);
                return;
        }
        pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
@@ -267,7 +274,7 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
                return;
        kvm_get_pfn(pfn);
        mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
-                     gpte & PT_DIRTY_MASK, NULL, largepage,
+                     gpte & PT_DIRTY_MASK, NULL, PT_PAGE_TABLE_LEVEL,
                     gpte_to_gfn(gpte), pfn, true);
 }
@@ -276,7 +283,7 @@ static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
 */
 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
                         struct guest_walker *gw,
-                         int user_fault, int write_fault, int largepage,
+                         int user_fault, int write_fault, int hlevel,
                         int *ptwrite, pfn_t pfn)
 {
        unsigned access = gw->pt_access;
@@ -289,19 +296,18 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
        pt_element_t curr_pte;
        struct kvm_shadow_walk_iterator iterator;
-        if (!is_present_pte(gw->ptes[gw->level - 1]))
+        if (!is_present_gpte(gw->ptes[gw->level - 1]))
                return NULL;
        for_each_shadow_entry(vcpu, addr, iterator) {
                level = iterator.level;
                sptep = iterator.sptep;
-                if (level == PT_PAGE_TABLE_LEVEL
+                if (iterator.level == hlevel) {
-                    || (largepage && level == PT_DIRECTORY_LEVEL)) {
                        mmu_set_spte(vcpu, sptep, access,
                                     gw->pte_access & access,
                                     user_fault, write_fault,
                                     gw->ptes[gw->level-1] & PT_DIRTY_MASK,
-                                     ptwrite, largepage,
+                                     ptwrite, level,
                                     gw->gfn, pfn, false);
                        break;
                }
@@ -311,16 +317,19 @@ static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
                if (is_large_pte(*sptep)) {
                        rmap_remove(vcpu->kvm, sptep);
-                        set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
+                        __set_spte(sptep, shadow_trap_nonpresent_pte);
                        kvm_flush_remote_tlbs(vcpu->kvm);
                }
-                if (level == PT_DIRECTORY_LEVEL
+                if (level <= gw->level) {
-                    && gw->level == PT_DIRECTORY_LEVEL) {
+                        int delta = level - gw->level + 1;
                        direct = 1;
-                        if (!is_dirty_pte(gw->ptes[level - 1]))
+                        if (!is_dirty_gpte(gw->ptes[level - delta]))
                                access &= ~ACC_WRITE_MASK;
-                        table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
+                        table_gfn = gpte_to_gfn(gw->ptes[level - delta]);
+                        /* advance table_gfn when emulating 1gb pages with 4k */
+                        if (delta == 0)
+                                table_gfn += PT_INDEX(addr, level);
                } else {
                        direct = 0;
                        table_gfn = gw->table_gfn[level - 2];
@@ -369,11 +378,11 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
        int user_fault = error_code & PFERR_USER_MASK;
        int fetch_fault = error_code & PFERR_FETCH_MASK;
        struct guest_walker walker;
-        u64 *shadow_pte;
+        u64 *sptep;
        int write_pt = 0;
        int r;
        pfn_t pfn;
-        int largepage = 0;
+        int level = PT_PAGE_TABLE_LEVEL;
        unsigned long mmu_seq;
        pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
@@ -399,14 +408,11 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
                return 0;
        }
-        if (walker.level == PT_DIRECTORY_LEVEL) {
+        if (walker.level >= PT_DIRECTORY_LEVEL) {
-                gfn_t large_gfn;
+                level = min(walker.level, mapping_level(vcpu, walker.gfn));
-                large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
+                walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
-                if (is_largepage_backed(vcpu, large_gfn)) {
-                        walker.gfn = large_gfn;
-                        largepage = 1;
-                }
        }
        mmu_seq = vcpu->kvm->mmu_notifier_seq;
        smp_rmb();
        pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
@@ -422,11 +428,10 @@ static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
        if (mmu_notifier_retry(vcpu, mmu_seq))
                goto out_unlock;
        kvm_mmu_free_some_pages(vcpu);
-        shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
+        sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
-                                  largepage, &write_pt, pfn);
+                             level, &write_pt, pfn);
        pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
-                 shadow_pte, *shadow_pte, write_pt);
+                 sptep, *sptep, write_pt);
        if (!write_pt)
                vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
@@ -459,8 +464,9 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
                sptep = iterator.sptep;
                /* FIXME: properly handle invlpg on large guest pages */
-                if (level == PT_PAGE_TABLE_LEVEL ||
+                if (level == PT_PAGE_TABLE_LEVEL  ||
-                    ((level == PT_DIRECTORY_LEVEL) && is_large_pte(*sptep))) {
+                    ((level == PT_DIRECTORY_LEVEL && is_large_pte(*sptep))) ||
+                    ((level == PT_PDPE_LEVEL && is_large_pte(*sptep)))) {
                        struct kvm_mmu_page *sp = page_header(__pa(sptep));
                        pte_gpa = (sp->gfn << PAGE_SHIFT);
@@ -472,7 +478,7 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
                                        --vcpu->kvm->stat.lpages;
                                need_flush = 1;
                        }
-                        set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
+                        __set_spte(sptep, shadow_trap_nonpresent_pte);
                        break;
                }
@@ -489,7 +495,7 @@ static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
        if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
                                  sizeof(pt_element_t)))
                return;
-        if (is_present_pte(gpte) && (gpte & PT_ACCESSED_MASK)) {
+        if (is_present_gpte(gpte) && (gpte & PT_ACCESSED_MASK)) {
                if (mmu_topup_memory_caches(vcpu))
                        return;
                kvm_mmu_pte_write(vcpu, pte_gpa, (const u8 *)&gpte,
@@ -536,7 +542,7 @@ static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
                r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
                pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
                for (j = 0; j < ARRAY_SIZE(pt); ++j)
-                        if (r || is_present_pte(pt[j]))
+                        if (r || is_present_gpte(pt[j]))
                                sp->spt[i+j] = shadow_trap_nonpresent_pte;
                        else
                                sp->spt[i+j] = shadow_notrap_nonpresent_pte;
@@ -574,23 +580,23 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
                                          sizeof(pt_element_t)))
                        return -EINVAL;
-                if (gpte_to_gfn(gpte) != gfn || !is_present_pte(gpte) ||
+                if (gpte_to_gfn(gpte) != gfn || !is_present_gpte(gpte) ||
                    !(gpte & PT_ACCESSED_MASK)) {
                        u64 nonpresent;
                        rmap_remove(vcpu->kvm, &sp->spt[i]);
-                        if (is_present_pte(gpte))
+                        if (is_present_gpte(gpte))
                                nonpresent = shadow_trap_nonpresent_pte;
                        else
                                nonpresent = shadow_notrap_nonpresent_pte;
-                        set_shadow_pte(&sp->spt[i], nonpresent);
+                        __set_spte(&sp->spt[i], nonpresent);
                        continue;
                }
                nr_present++;
                pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
                set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
-                         is_dirty_pte(gpte), 0, gfn,
+                         is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
                         spte_to_pfn(sp->spt[i]), true, false);
        }
@@ -603,9 +609,10 @@ static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
 #undef PT_BASE_ADDR_MASK
 #undef PT_INDEX
 #undef PT_LEVEL_MASK
-#undef PT_DIR_BASE_ADDR_MASK
+#undef PT_LVL_ADDR_MASK
+#undef PT_LVL_OFFSET_MASK
 #undef PT_LEVEL_BITS
 #undef PT_MAX_FULL_LEVELS
 #undef gpte_to_gfn
-#undef gpte_to_gfn_pde
+#undef gpte_to_gfn_lvl
 #undef CMPXCHG
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index b1f658ad2f06..944cc9c04b3c 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -15,7 +15,6 @@
 */
 #include <linux/kvm_host.h>
-#include "kvm_svm.h"
 #include "irq.h"
 #include "mmu.h"
 #include "kvm_cache_regs.h"
@@ -26,10 +25,12 @@
 #include <linux/vmalloc.h>
 #include <linux/highmem.h>
 #include <linux/sched.h>
+#include <linux/ftrace_event.h>
 #include <asm/desc.h>
 #include <asm/virtext.h>
+#include "trace.h"
 #define __ex(x) __kvm_handle_fault_on_reboot(x)
@@ -46,6 +47,10 @@ MODULE_LICENSE("GPL");
 #define SVM_FEATURE_LBRV (1 << 1)
 #define SVM_FEATURE_SVML (1 << 2)
+#define NESTED_EXIT_HOST        0       /* Exit handled on host level */
+#define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
+#define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
 /* Turn on to get debugging output*/
@@ -57,6 +62,58 @@ MODULE_LICENSE("GPL");
 #define nsvm_printk(fmt, args...) do {} while(0)
 #endif
+static const u32 host_save_user_msrs[] = {
+#ifdef CONFIG_X86_64
+        MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
+        MSR_FS_BASE,
+#endif
+        MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
+};
+#define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
+struct kvm_vcpu;
+struct nested_state {
+        struct vmcb *hsave;
+        u64 hsave_msr;
+        u64 vmcb;
+        /* These are the merged vectors */
+        u32 *msrpm;
+        /* gpa pointers to the real vectors */
+        u64 vmcb_msrpm;
+        /* cache for intercepts of the guest */
+        u16 intercept_cr_read;
+        u16 intercept_cr_write;
+        u16 intercept_dr_read;
+        u16 intercept_dr_write;
+        u32 intercept_exceptions;
+        u64 intercept;
+};
+struct vcpu_svm {
+        struct kvm_vcpu vcpu;
+        struct vmcb *vmcb;
+        unsigned long vmcb_pa;
+        struct svm_cpu_data *svm_data;
+        uint64_t asid_generation;
+        uint64_t sysenter_esp;
+        uint64_t sysenter_eip;
+        u64 next_rip;
+        u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
+        u64 host_gs_base;
+        u32 *msrpm;
+        struct nested_state nested;
+};
 /* enable NPT for AMD64 and X86 with PAE */
 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 static bool npt_enabled = true;
@@ -67,15 +124,14 @@ static int npt = 1;
 module_param(npt, int, S_IRUGO);
-static int nested = 0;
+static int nested = 1;
 module_param(nested, int, S_IRUGO);
 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
+static void svm_complete_interrupts(struct vcpu_svm *svm);
-static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
+static int nested_svm_exit_handled(struct vcpu_svm *svm);
 static int nested_svm_vmexit(struct vcpu_svm *svm);
-static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
-                             void *arg2, void *opaque);
 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
                                      bool has_error_code, u32 error_code);
@@ -86,7 +142,22 @@ static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 static inline bool is_nested(struct vcpu_svm *svm)
 {
-        return svm->nested_vmcb;
+        return svm->nested.vmcb;
+}
+static inline void enable_gif(struct vcpu_svm *svm)
+{
+        svm->vcpu.arch.hflags |= HF_GIF_MASK;
+}
+static inline void disable_gif(struct vcpu_svm *svm)
+{
+        svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
+}
+static inline bool gif_set(struct vcpu_svm *svm)
+{
+        return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 }
 static unsigned long iopm_base;
@@ -147,19 +218,6 @@ static inline void invlpga(unsigned long addr, u32 asid)
        asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 }
-static inline unsigned long kvm_read_cr2(void)
-{
-        unsigned long cr2;
-        asm volatile ("mov %%cr2, %0" : "=r" (cr2));
-        return cr2;
-}
-static inline void kvm_write_cr2(unsigned long val)
-{
-        asm volatile ("mov %0, %%cr2" :: "r" (val));
-}
 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 {
        to_svm(vcpu)->asid_generation--;
@@ -263,7 +321,7 @@ static void svm_hardware_enable(void *garbage)
        struct svm_cpu_data *svm_data;
        uint64_t efer;
-        struct desc_ptr gdt_descr;
+        struct descriptor_table gdt_descr;
        struct desc_struct *gdt;
        int me = raw_smp_processor_id();
@@ -283,8 +341,8 @@ static void svm_hardware_enable(void *garbage)
        svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
        svm_data->next_asid = svm_data->max_asid + 1;
-        asm volatile ("sgdt %0" : "=m"(gdt_descr));
+        kvm_get_gdt(&gdt_descr);
-        gdt = (struct desc_struct *)gdt_descr.address;
+        gdt = (struct desc_struct *)gdt_descr.base;
        svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
        rdmsrl(MSR_EFER, efer);
@@ -367,8 +425,6 @@ static void svm_vcpu_init_msrpm(u32 *msrpm)
 #endif
        set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
        set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
-        set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
-        set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 }
 static void svm_enable_lbrv(struct vcpu_svm *svm)
@@ -595,8 +651,10 @@ static void init_vmcb(struct vcpu_svm *svm)
        }
        force_new_asid(&svm->vcpu);
-        svm->nested_vmcb = 0;
+        svm->nested.vmcb = 0;
-        svm->vcpu.arch.hflags = HF_GIF_MASK;
+        svm->vcpu.arch.hflags = 0;
+        enable_gif(svm);
 }
 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
@@ -605,7 +663,7 @@ static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
        init_vmcb(svm);
-        if (vcpu->vcpu_id != 0) {
+        if (!kvm_vcpu_is_bsp(vcpu)) {
                kvm_rip_write(vcpu, 0);
                svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
                svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
@@ -656,9 +714,9 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
        hsave_page = alloc_page(GFP_KERNEL);
        if (!hsave_page)
                goto uninit;
-        svm->hsave = page_address(hsave_page);
+        svm->nested.hsave = page_address(hsave_page);
-        svm->nested_msrpm = page_address(nested_msrpm_pages);
+        svm->nested.msrpm = page_address(nested_msrpm_pages);
        svm->vmcb = page_address(page);
        clear_page(svm->vmcb);
@@ -669,7 +727,7 @@ static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
        fx_init(&svm->vcpu);
        svm->vcpu.fpu_active = 1;
        svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
-        if (svm->vcpu.vcpu_id == 0)
+        if (kvm_vcpu_is_bsp(&svm->vcpu))
                svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
        return &svm->vcpu;
@@ -688,8 +746,8 @@ static void svm_free_vcpu(struct kvm_vcpu *vcpu)
        __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
        __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
-        __free_page(virt_to_page(svm->hsave));
+        __free_page(virt_to_page(svm->nested.hsave));
-        __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
+        __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
        kvm_vcpu_uninit(vcpu);
        kmem_cache_free(kvm_vcpu_cache, svm);
 }
@@ -740,6 +798,18 @@ static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
        to_svm(vcpu)->vmcb->save.rflags = rflags;
 }
+static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
+{
+        switch (reg) {
+        case VCPU_EXREG_PDPTR:
+                BUG_ON(!npt_enabled);
+                load_pdptrs(vcpu, vcpu->arch.cr3);
+                break;
+        default:
+                BUG();
+        }
+}
 static void svm_set_vintr(struct vcpu_svm *svm)
 {
        svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
@@ -1061,7 +1131,6 @@ static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
                val = 0;
        }
-        KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
        return val;
 }
@@ -1070,8 +1139,6 @@ static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 {
        struct vcpu_svm *svm = to_svm(vcpu);
-        KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
        *exception = 0;
        switch (dr) {
@@ -1119,25 +1186,9 @@ static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
        fault_address  = svm->vmcb->control.exit_info_2;
        error_code = svm->vmcb->control.exit_info_1;
-        if (!npt_enabled)
+        trace_kvm_page_fault(fault_address, error_code);
-                KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
+        if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
-                            (u32)fault_address, (u32)(fault_address >> 32),
+                kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
-                            handler);
-        else
-                KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
-                            (u32)fault_address, (u32)(fault_address >> 32),
-                            handler);
-        /*
-         * FIXME: Tis shouldn't be necessary here, but there is a flush
-         * missing in the MMU code. Until we find this bug, flush the
-         * complete TLB here on an NPF
-         */
-        if (npt_enabled)
-                svm_flush_tlb(&svm->vcpu);
-        else {
-                if (kvm_event_needs_reinjection(&svm->vcpu))
-                        kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
-        }
        return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 }
@@ -1253,14 +1304,12 @@ static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 {
-        KVMTRACE_0D(NMI, &svm->vcpu, handler);
        return 1;
 }
 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 {
        ++svm->vcpu.stat.irq_exits;
-        KVMTRACE_0D(INTR, &svm->vcpu, handler);
        return 1;
 }
@@ -1303,44 +1352,39 @@ static int nested_svm_check_permissions(struct vcpu_svm *svm)
 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
                                      bool has_error_code, u32 error_code)
 {
-        if (is_nested(svm)) {
+        if (!is_nested(svm))
-                svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
+                return 0;
-                svm->vmcb->control.exit_code_hi = 0;
-                svm->vmcb->control.exit_info_1 = error_code;
-                svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
-                if (nested_svm_exit_handled(svm, false)) {
-                        nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
-                        nested_svm_vmexit(svm);
-                        return 1;
-                }
-        }
-        return 0;
+        svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
+        svm->vmcb->control.exit_code_hi = 0;
+        svm->vmcb->control.exit_info_1 = error_code;
+        svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
+        return nested_svm_exit_handled(svm);
 }
 static inline int nested_svm_intr(struct vcpu_svm *svm)
 {
-        if (is_nested(svm)) {
+        if (!is_nested(svm))
-                if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
+                return 0;
-                        return 0;
-                if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
+        if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
-                        return 0;
+                return 0;
-                svm->vmcb->control.exit_code = SVM_EXIT_INTR;
+        if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
+                return 0;
-                if (nested_svm_exit_handled(svm, false)) {
+        svm->vmcb->control.exit_code = SVM_EXIT_INTR;
-                        nsvm_printk("VMexit -> INTR\n");
-                        nested_svm_vmexit(svm);
+        if (nested_svm_exit_handled(svm)) {
-                        return 1;
+                nsvm_printk("VMexit -> INTR\n");
-                }
+                return 1;
        }
        return 0;
 }
-static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
+static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, enum km_type idx)
 {
        struct page *page;
@@ -1348,236 +1392,246 @@ static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
        page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
        up_read(&current->mm->mmap_sem);
-        if (is_error_page(page)) {
+        if (is_error_page(page))
-                printk(KERN_INFO "%s: could not find page at 0x%llx\n",
+                goto error;
-                       __func__, gpa);
-                kvm_release_page_clean(page);
+        return kmap_atomic(page, idx);
-                kvm_inject_gp(&svm->vcpu, 0);
-                return NULL;
+error:
-        }
+        kvm_release_page_clean(page);
-        return page;
+        kvm_inject_gp(&svm->vcpu, 0);
+        return NULL;
 }
-static int nested_svm_do(struct vcpu_svm *svm,
+static void nested_svm_unmap(void *addr, enum km_type idx)
-                         u64 arg1_gpa, u64 arg2_gpa, void *opaque,
-                         int (*handler)(struct vcpu_svm *svm,
-                                        void *arg1,
-                                        void *arg2,
-                                        void *opaque))
 {
-        struct page *arg1_page;
+        struct page *page;
-        struct page *arg2_page = NULL;
-        void *arg1;
-        void *arg2 = NULL;
-        int retval;
-        arg1_page = nested_svm_get_page(svm, arg1_gpa);
+        if (!addr)
-        if(arg1_page == NULL)
+                return;
-                return 1;
-        if (arg2_gpa) {
+        page = kmap_atomic_to_page(addr);
-                arg2_page = nested_svm_get_page(svm, arg2_gpa);
-                if(arg2_page == NULL) {
+        kunmap_atomic(addr, idx);
-                        kvm_release_page_clean(arg1_page);
+        kvm_release_page_dirty(page);
-                        return 1;
+}
-                }
-        }
+static bool nested_svm_exit_handled_msr(struct vcpu_svm *svm)
+{
+        u32 param = svm->vmcb->control.exit_info_1 & 1;
+        u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
+        bool ret = false;
+        u32 t0, t1;
+        u8 *msrpm;
-        arg1 = kmap_atomic(arg1_page, KM_USER0);
+        if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
-        if (arg2_gpa)
+                return false;
-                arg2 = kmap_atomic(arg2_page, KM_USER1);
-        retval = handler(svm, arg1, arg2, opaque);
+        msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
+        if (!msrpm)
+                goto out;
+        switch (msr) {
+        case 0 ... 0x1fff:
+                t0 = (msr * 2) % 8;
+                t1 = msr / 8;
+                break;
+        case 0xc0000000 ... 0xc0001fff:
+                t0 = (8192 + msr - 0xc0000000) * 2;
+                t1 = (t0 / 8);
+                t0 %= 8;
+                break;
+        case 0xc0010000 ... 0xc0011fff:
+                t0 = (16384 + msr - 0xc0010000) * 2;
+                t1 = (t0 / 8);
+                t0 %= 8;
+                break;
+        default:
+                ret = true;
+                goto out;
+        }
-        kunmap_atomic(arg1, KM_USER0);
+        ret = msrpm[t1] & ((1 << param) << t0);
-        if (arg2_gpa)
-                kunmap_atomic(arg2, KM_USER1);
-        kvm_release_page_dirty(arg1_page);
+out:
-        if (arg2_gpa)
+        nested_svm_unmap(msrpm, KM_USER0);
-                kvm_release_page_dirty(arg2_page);
-        return retval;
+        return ret;
 }
-static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
+static int nested_svm_exit_special(struct vcpu_svm *svm)
-                                        void *arg1,
-                                        void *arg2,
-                                        void *opaque)
 {
-        struct vmcb *nested_vmcb = (struct vmcb *)arg1;
-        bool kvm_overrides = *(bool *)opaque;
        u32 exit_code = svm->vmcb->control.exit_code;
-        if (kvm_overrides) {
+        switch (exit_code) {
-                switch (exit_code) {
+        case SVM_EXIT_INTR:
-                case SVM_EXIT_INTR:
+        case SVM_EXIT_NMI:
-                case SVM_EXIT_NMI:
+                return NESTED_EXIT_HOST;
-                        return 0;
                /* For now we are always handling NPFs when using them */
-                case SVM_EXIT_NPF:
+        case SVM_EXIT_NPF:
-                        if (npt_enabled)
+                if (npt_enabled)
-                                return 0;
+                        return NESTED_EXIT_HOST;
-                        break;
+                break;
-                /* When we're shadowing, trap PFs */
+        /* When we're shadowing, trap PFs */
-                case SVM_EXIT_EXCP_BASE + PF_VECTOR:
+        case SVM_EXIT_EXCP_BASE + PF_VECTOR:
-                        if (!npt_enabled)
+                if (!npt_enabled)
-                                return 0;
+                        return NESTED_EXIT_HOST;
-                        break;
+                break;
-                default:
+        default:
-                        break;
+                break;
-                }
        }
+        return NESTED_EXIT_CONTINUE;
+}
+/*
+ * If this function returns true, this #vmexit was already handled
+ */
+static int nested_svm_exit_handled(struct vcpu_svm *svm)
+{
+        u32 exit_code = svm->vmcb->control.exit_code;
+        int vmexit = NESTED_EXIT_HOST;
        switch (exit_code) {
+        case SVM_EXIT_MSR:
+                vmexit = nested_svm_exit_handled_msr(svm);
+                break;
        case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
                u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
-                if (nested_vmcb->control.intercept_cr_read & cr_bits)
+                if (svm->nested.intercept_cr_read & cr_bits)
-                        return 1;
+                        vmexit = NESTED_EXIT_DONE;
                break;
        }
        case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
                u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
-                if (nested_vmcb->control.intercept_cr_write & cr_bits)
+                if (svm->nested.intercept_cr_write & cr_bits)
-                        return 1;
+                        vmexit = NESTED_EXIT_DONE;
                break;
        }
        case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
                u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
-                if (nested_vmcb->control.intercept_dr_read & dr_bits)
+                if (svm->nested.intercept_dr_read & dr_bits)
-                        return 1;
+                        vmexit = NESTED_EXIT_DONE;
                break;
        }
        case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
                u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
-                if (nested_vmcb->control.intercept_dr_write & dr_bits)
+                if (svm->nested.intercept_dr_write & dr_bits)
-                        return 1;
+                        vmexit = NESTED_EXIT_DONE;
                break;
        }
        case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
                u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
-                if (nested_vmcb->control.intercept_exceptions & excp_bits)
+                if (svm->nested.intercept_exceptions & excp_bits)
-                        return 1;
+                        vmexit = NESTED_EXIT_DONE;
                break;
        }
        default: {
                u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
                nsvm_printk("exit code: 0x%x\n", exit_code);
-                if (nested_vmcb->control.intercept & exit_bits)
+                if (svm->nested.intercept & exit_bits)
-                        return 1;
+                        vmexit = NESTED_EXIT_DONE;
        }
        }
-        return 0;
+        if (vmexit == NESTED_EXIT_DONE) {
-}
+                nsvm_printk("#VMEXIT reason=%04x\n", exit_code);
+                nested_svm_vmexit(svm);
-static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
-                                       void *arg1, void *arg2,
-                                       void *opaque)
-{
-        struct vmcb *nested_vmcb = (struct vmcb *)arg1;
-        u8 *msrpm = (u8 *)arg2;
-        u32 t0, t1;
-        u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
-        u32 param = svm->vmcb->control.exit_info_1 & 1;
-        if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
-                return 0;
-        switch(msr) {
-        case 0 ... 0x1fff:
-                t0 = (msr * 2) % 8;
-                t1 = msr / 8;
-                break;
-        case 0xc0000000 ... 0xc0001fff:
-                t0 = (8192 + msr - 0xc0000000) * 2;
-                t1 = (t0 / 8);
-                t0 %= 8;
-                break;
-        case 0xc0010000 ... 0xc0011fff:
-                t0 = (16384 + msr - 0xc0010000) * 2;
-                t1 = (t0 / 8);
-                t0 %= 8;
-                break;
-        default:
-                return 1;
-                break;
        }
-        if (msrpm[t1] & ((1 << param) << t0))
-                return 1;
-        return 0;
+        return vmexit;
+}
+static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
+{
+        struct vmcb_control_area *dst  = &dst_vmcb->control;
+        struct vmcb_control_area *from = &from_vmcb->control;
+        dst->intercept_cr_read    = from->intercept_cr_read;
+        dst->intercept_cr_write   = from->intercept_cr_write;
+        dst->intercept_dr_read    = from->intercept_dr_read;
+        dst->intercept_dr_write   = from->intercept_dr_write;
+        dst->intercept_exceptions = from->intercept_exceptions;
+        dst->intercept            = from->intercept;
+        dst->iopm_base_pa         = from->iopm_base_pa;
+        dst->msrpm_base_pa        = from->msrpm_base_pa;
+        dst->tsc_offset           = from->tsc_offset;
+        dst->asid                 = from->asid;
+        dst->tlb_ctl              = from->tlb_ctl;
+        dst->int_ctl              = from->int_ctl;
+        dst->int_vector           = from->int_vector;
+        dst->int_state            = from->int_state;
+        dst->exit_code            = from->exit_code;
+        dst->exit_code_hi         = from->exit_code_hi;
+        dst->exit_info_1          = from->exit_info_1;
+        dst->exit_info_2          = from->exit_info_2;
+        dst->exit_int_info        = from->exit_int_info;
+        dst->exit_int_info_err    = from->exit_int_info_err;
+        dst->nested_ctl           = from->nested_ctl;
+        dst->event_inj            = from->event_inj;
+        dst->event_inj_err        = from->event_inj_err;
+        dst->nested_cr3           = from->nested_cr3;
+        dst->lbr_ctl              = from->lbr_ctl;
 }
-static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
+static int nested_svm_vmexit(struct vcpu_svm *svm)
 {
-        bool k = kvm_override;
+        struct vmcb *nested_vmcb;
+        struct vmcb *hsave = svm->nested.hsave;
-        switch (svm->vmcb->control.exit_code) {
+        struct vmcb *vmcb = svm->vmcb;
-        case SVM_EXIT_MSR:
-                return nested_svm_do(svm, svm->nested_vmcb,
-                                     svm->nested_vmcb_msrpm, NULL,
-                                     nested_svm_exit_handled_msr);
-        default: break;
-        }
-        return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
+        nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, KM_USER0);
-                             nested_svm_exit_handled_real);
+        if (!nested_vmcb)
-}
+                return 1;
-static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
-                                  void *arg2, void *opaque)
-{
-        struct vmcb *nested_vmcb = (struct vmcb *)arg1;
-        struct vmcb *hsave = svm->hsave;
-        u64 nested_save[] = { nested_vmcb->save.cr0,
-                              nested_vmcb->save.cr3,
-                              nested_vmcb->save.cr4,
-                              nested_vmcb->save.efer,
-                              nested_vmcb->control.intercept_cr_read,
-                              nested_vmcb->control.intercept_cr_write,
-                              nested_vmcb->control.intercept_dr_read,
-                              nested_vmcb->control.intercept_dr_write,
-                              nested_vmcb->control.intercept_exceptions,
-                              nested_vmcb->control.intercept,
-                              nested_vmcb->control.msrpm_base_pa,
-                              nested_vmcb->control.iopm_base_pa,
-                              nested_vmcb->control.tsc_offset };
        /* Give the current vmcb to the guest */
-        memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
+        disable_gif(svm);
-        nested_vmcb->save.cr0 = nested_save[0];
-        if (!npt_enabled)
+        nested_vmcb->save.es     = vmcb->save.es;
-                nested_vmcb->save.cr3 = nested_save[1];
+        nested_vmcb->save.cs     = vmcb->save.cs;
-        nested_vmcb->save.cr4 = nested_save[2];
+        nested_vmcb->save.ss     = vmcb->save.ss;
-        nested_vmcb->save.efer = nested_save[3];
+        nested_vmcb->save.ds     = vmcb->save.ds;
-        nested_vmcb->control.intercept_cr_read = nested_save[4];
+        nested_vmcb->save.gdtr   = vmcb->save.gdtr;
-        nested_vmcb->control.intercept_cr_write = nested_save[5];
+        nested_vmcb->save.idtr   = vmcb->save.idtr;
-        nested_vmcb->control.intercept_dr_read = nested_save[6];
+        if (npt_enabled)
-        nested_vmcb->control.intercept_dr_write = nested_save[7];
+                nested_vmcb->save.cr3    = vmcb->save.cr3;
-        nested_vmcb->control.intercept_exceptions = nested_save[8];
+        nested_vmcb->save.cr2    = vmcb->save.cr2;
-        nested_vmcb->control.intercept = nested_save[9];
+        nested_vmcb->save.rflags = vmcb->save.rflags;
-        nested_vmcb->control.msrpm_base_pa = nested_save[10];
+        nested_vmcb->save.rip    = vmcb->save.rip;
-        nested_vmcb->control.iopm_base_pa = nested_save[11];
+        nested_vmcb->save.rsp    = vmcb->save.rsp;
-        nested_vmcb->control.tsc_offset = nested_save[12];
+        nested_vmcb->save.rax    = vmcb->save.rax;
+        nested_vmcb->save.dr7    = vmcb->save.dr7;
+        nested_vmcb->save.dr6    = vmcb->save.dr6;
+        nested_vmcb->save.cpl    = vmcb->save.cpl;
+        nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
+        nested_vmcb->control.int_vector        = vmcb->control.int_vector;
+        nested_vmcb->control.int_state         = vmcb->control.int_state;
+        nested_vmcb->control.exit_code         = vmcb->control.exit_code;
+        nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
+        nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
+        nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
+        nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
+        nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
+        nested_vmcb->control.tlb_ctl           = 0;
+        nested_vmcb->control.event_inj         = 0;
+        nested_vmcb->control.event_inj_err     = 0;
        /* We always set V_INTR_MASKING and remember the old value in hflags */
        if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
                nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
-        if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
-            (nested_vmcb->control.int_vector)) {
-                nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
-                                nested_vmcb->control.int_vector);
-        }
        /* Restore the original control entries */
-        svm->vmcb->control = hsave->control;
+        copy_vmcb_control_area(vmcb, hsave);
        /* Kill any pending exceptions */
        if (svm->vcpu.arch.exception.pending == true)
                nsvm_printk("WARNING: Pending Exception\n");
-        svm->vcpu.arch.exception.pending = false;
+        kvm_clear_exception_queue(&svm->vcpu);
+        kvm_clear_interrupt_queue(&svm->vcpu);
        /* Restore selected save entries */
        svm->vmcb->save.es = hsave->save.es;
@@ -1603,19 +1657,10 @@ static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
        svm->vmcb->save.cpl = 0;
        svm->vmcb->control.exit_int_info = 0;
-        svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
        /* Exit nested SVM mode */
-        svm->nested_vmcb = 0;
+        svm->nested.vmcb = 0;
-        return 0;
+        nested_svm_unmap(nested_vmcb, KM_USER0);
-}
-static int nested_svm_vmexit(struct vcpu_svm *svm)
-{
-        nsvm_printk("VMexit\n");
-        if (nested_svm_do(svm, svm->nested_vmcb, 0,
-                          NULL, nested_svm_vmexit_real))
-                return 1;
        kvm_mmu_reset_context(&svm->vcpu);
        kvm_mmu_load(&svm->vcpu);
@@ -1623,38 +1668,63 @@ static int nested_svm_vmexit(struct vcpu_svm *svm)
        return 0;
 }
-static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
+static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
-                                  void *arg2, void *opaque)
 {
+        u32 *nested_msrpm;
        int i;
-        u32 *nested_msrpm = (u32*)arg1;
+        nested_msrpm = nested_svm_map(svm, svm->nested.vmcb_msrpm, KM_USER0);
+        if (!nested_msrpm)
+                return false;
        for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
-                svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
+                svm->nested.msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
-        svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
-        return 0;
+        svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
+        nested_svm_unmap(nested_msrpm, KM_USER0);
+        return true;
 }
-static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
+static bool nested_svm_vmrun(struct vcpu_svm *svm)
-                            void *arg2, void *opaque)
 {
-        struct vmcb *nested_vmcb = (struct vmcb *)arg1;
+        struct vmcb *nested_vmcb;
-        struct vmcb *hsave = svm->hsave;
+        struct vmcb *hsave = svm->nested.hsave;
+        struct vmcb *vmcb = svm->vmcb;
+        nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
+        if (!nested_vmcb)
+                return false;
        /* nested_vmcb is our indicator if nested SVM is activated */
-        svm->nested_vmcb = svm->vmcb->save.rax;
+        svm->nested.vmcb = svm->vmcb->save.rax;
        /* Clear internal status */
-        svm->vcpu.arch.exception.pending = false;
+        kvm_clear_exception_queue(&svm->vcpu);
+        kvm_clear_interrupt_queue(&svm->vcpu);
        /* Save the old vmcb, so we don't need to pick what we save, but
           can restore everything when a VMEXIT occurs */
-        memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
+        hsave->save.es     = vmcb->save.es;
-        /* We need to remember the original CR3 in the SPT case */
+        hsave->save.cs     = vmcb->save.cs;
-        if (!npt_enabled)
+        hsave->save.ss     = vmcb->save.ss;
-                hsave->save.cr3 = svm->vcpu.arch.cr3;
+        hsave->save.ds     = vmcb->save.ds;
-        hsave->save.cr4 = svm->vcpu.arch.cr4;
+        hsave->save.gdtr   = vmcb->save.gdtr;
-        hsave->save.rip = svm->next_rip;
+        hsave->save.idtr   = vmcb->save.idtr;
+        hsave->save.efer   = svm->vcpu.arch.shadow_efer;
+        hsave->save.cr0    = svm->vcpu.arch.cr0;
+        hsave->save.cr4    = svm->vcpu.arch.cr4;
+        hsave->save.rflags = vmcb->save.rflags;
+        hsave->save.rip    = svm->next_rip;
+        hsave->save.rsp    = vmcb->save.rsp;
+        hsave->save.rax    = vmcb->save.rax;
+        if (npt_enabled)
+                hsave->save.cr3    = vmcb->save.cr3;
+        else
+                hsave->save.cr3    = svm->vcpu.arch.cr3;
+        copy_vmcb_control_area(hsave, vmcb);
        if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
                svm->vcpu.arch.hflags |= HF_HIF_MASK;
@@ -1679,7 +1749,7 @@ static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
                kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
                kvm_mmu_reset_context(&svm->vcpu);
        }
-        svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
+        svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
        kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
        kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
        kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
@@ -1706,7 +1776,15 @@ static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
        svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
-        svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
+        svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
+        /* cache intercepts */
+        svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
+        svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
+        svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
+        svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
+        svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
+        svm->nested.intercept            = nested_vmcb->control.intercept;
        force_new_asid(&svm->vcpu);
        svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
@@ -1734,12 +1812,14 @@ static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
        svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
        svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
-        svm->vcpu.arch.hflags |= HF_GIF_MASK;
+        nested_svm_unmap(nested_vmcb, KM_USER0);
-        return 0;
+        enable_gif(svm);
+        return true;
 }
-static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
+static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
 {
        to_vmcb->save.fs = from_vmcb->save.fs;
        to_vmcb->save.gs = from_vmcb->save.gs;
@@ -1753,44 +1833,44 @@ static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
        to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
        to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
        to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
-        return 1;
-}
-static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
-                             void *arg2, void *opaque)
-{
-        return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
-}
-static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
-                             void *arg2, void *opaque)
-{
-        return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
 }
 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 {
+        struct vmcb *nested_vmcb;
        if (nested_svm_check_permissions(svm))
                return 1;
        svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
        skip_emulated_instruction(&svm->vcpu);
-        nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
+        nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
+        if (!nested_vmcb)
+                return 1;
+        nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
+        nested_svm_unmap(nested_vmcb, KM_USER0);
        return 1;
 }
 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 {
+        struct vmcb *nested_vmcb;
        if (nested_svm_check_permissions(svm))
                return 1;
        svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
        skip_emulated_instruction(&svm->vcpu);
-        nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
+        nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, KM_USER0);
+        if (!nested_vmcb)
+                return 1;
+        nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
+        nested_svm_unmap(nested_vmcb, KM_USER0);
        return 1;
 }
@@ -1798,19 +1878,29 @@ static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 {
        nsvm_printk("VMrun\n");
        if (nested_svm_check_permissions(svm))
                return 1;
        svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
        skip_emulated_instruction(&svm->vcpu);
-        if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
+        if (!nested_svm_vmrun(svm))
-                          NULL, nested_svm_vmrun))
                return 1;
-        if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
+        if (!nested_svm_vmrun_msrpm(svm))
-                      NULL, nested_svm_vmrun_msrpm))
+                goto failed;
-                return 1;
+        return 1;
+failed:
+        svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
+        svm->vmcb->control.exit_code_hi = 0;
+        svm->vmcb->control.exit_info_1  = 0;
+        svm->vmcb->control.exit_info_2  = 0;
+        nested_svm_vmexit(svm);
        return 1;
 }
@@ -1823,7 +1913,7 @@ static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
        svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
        skip_emulated_instruction(&svm->vcpu);
-        svm->vcpu.arch.hflags |= HF_GIF_MASK;
+        enable_gif(svm);
        return 1;
 }
@@ -1836,7 +1926,7 @@ static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
        svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
        skip_emulated_instruction(&svm->vcpu);
-        svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
+        disable_gif(svm);
        /* After a CLGI no interrupts should come */
        svm_clear_vintr(svm);
@@ -1845,6 +1935,19 @@ static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
        return 1;
 }
+static int invlpga_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
+{
+        struct kvm_vcpu *vcpu = &svm->vcpu;
+        nsvm_printk("INVLPGA\n");
+        /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
+        kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
+        svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
+        skip_emulated_instruction(&svm->vcpu);
+        return 1;
+}
 static int invalid_op_interception(struct vcpu_svm *svm,
                                   struct kvm_run *kvm_run)
 {
@@ -1953,7 +2056,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
        struct vcpu_svm *svm = to_svm(vcpu);
        switch (ecx) {
-        case MSR_IA32_TIME_STAMP_COUNTER: {
+        case MSR_IA32_TSC: {
                u64 tsc;
                rdtscll(tsc);
@@ -1981,10 +2084,10 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
                *data = svm->vmcb->save.sysenter_cs;
                break;
        case MSR_IA32_SYSENTER_EIP:
-                *data = svm->vmcb->save.sysenter_eip;
+                *data = svm->sysenter_eip;
                break;
        case MSR_IA32_SYSENTER_ESP:
-                *data = svm->vmcb->save.sysenter_esp;
+                *data = svm->sysenter_esp;
                break;
        /* Nobody will change the following 5 values in the VMCB so
           we can safely return them on rdmsr. They will always be 0
@@ -2005,7 +2108,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
                *data = svm->vmcb->save.last_excp_to;
                break;
        case MSR_VM_HSAVE_PA:
-                *data = svm->hsave_msr;
+                *data = svm->nested.hsave_msr;
                break;
        case MSR_VM_CR:
                *data = 0;
@@ -2027,8 +2130,7 @@ static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
        if (svm_get_msr(&svm->vcpu, ecx, &data))
                kvm_inject_gp(&svm->vcpu, 0);
        else {
-                KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
+                trace_kvm_msr_read(ecx, data);
-                            (u32)(data >> 32), handler);
                svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
                svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
@@ -2043,7 +2145,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
        struct vcpu_svm *svm = to_svm(vcpu);
        switch (ecx) {
-        case MSR_IA32_TIME_STAMP_COUNTER: {
+        case MSR_IA32_TSC: {
                u64 tsc;
                rdtscll(tsc);
@@ -2071,9 +2173,11 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
                svm->vmcb->save.sysenter_cs = data;
                break;
        case MSR_IA32_SYSENTER_EIP:
+                svm->sysenter_eip = data;
                svm->vmcb->save.sysenter_eip = data;
                break;
        case MSR_IA32_SYSENTER_ESP:
+                svm->sysenter_esp = data;
                svm->vmcb->save.sysenter_esp = data;
                break;
        case MSR_IA32_DEBUGCTLMSR:
@@ -2091,24 +2195,12 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
                else
                        svm_disable_lbrv(svm);
                break;
-        case MSR_K7_EVNTSEL0:
-        case MSR_K7_EVNTSEL1:
-        case MSR_K7_EVNTSEL2:
-        case MSR_K7_EVNTSEL3:
-        case MSR_K7_PERFCTR0:
-        case MSR_K7_PERFCTR1:
-        case MSR_K7_PERFCTR2:
-        case MSR_K7_PERFCTR3:
-                /*
-                 * Just discard all writes to the performance counters; this
-                 * should keep both older linux and windows 64-bit guests
-                 * happy
-                 */
-                pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
-                break;
        case MSR_VM_HSAVE_PA:
-                svm->hsave_msr = data;
+                svm->nested.hsave_msr = data;
+                break;
+        case MSR_VM_CR:
+        case MSR_VM_IGNNE:
+                pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
                break;
        default:
                return kvm_set_msr_common(vcpu, ecx, data);
@@ -2122,8 +2214,7 @@ static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
        u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
                | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
-        KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
+        trace_kvm_msr_write(ecx, data);
-                    handler);
        svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
        if (svm_set_msr(&svm->vcpu, ecx, data))
@@ -2144,8 +2235,6 @@ static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 static int interrupt_window_interception(struct vcpu_svm *svm,
                                   struct kvm_run *kvm_run)
 {
-        KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
        svm_clear_vintr(svm);
        svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
        /*
@@ -2201,7 +2290,7 @@ static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
        [SVM_EXIT_INVD]                         = emulate_on_interception,
        [SVM_EXIT_HLT]                          = halt_interception,
        [SVM_EXIT_INVLPG]                       = invlpg_interception,
-        [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
+        [SVM_EXIT_INVLPGA]                      = invlpga_interception,
        [SVM_EXIT_IOIO]                         = io_interception,
        [SVM_EXIT_MSR]                          = msr_interception,
        [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
@@ -2224,20 +2313,26 @@ static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
        struct vcpu_svm *svm = to_svm(vcpu);
        u32 exit_code = svm->vmcb->control.exit_code;
-        KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
+        trace_kvm_exit(exit_code, svm->vmcb->save.rip);
-                    (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
        if (is_nested(svm)) {
+                int vmexit;
                nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
                            exit_code, svm->vmcb->control.exit_info_1,
                            svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
-                if (nested_svm_exit_handled(svm, true)) {
-                        nested_svm_vmexit(svm);
+                vmexit = nested_svm_exit_special(svm);
-                        nsvm_printk("-> #VMEXIT\n");
+                if (vmexit == NESTED_EXIT_CONTINUE)
+                        vmexit = nested_svm_exit_handled(svm);
+                if (vmexit == NESTED_EXIT_DONE)
                        return 1;
-                }
        }
+        svm_complete_interrupts(svm);
        if (npt_enabled) {
                int mmu_reload = 0;
                if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
@@ -2246,12 +2341,6 @@ static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
                }
                vcpu->arch.cr0 = svm->vmcb->save.cr0;
                vcpu->arch.cr3 = svm->vmcb->save.cr3;
-                if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
-                        if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
-                                kvm_inject_gp(vcpu, 0);
-                                return 1;
-                        }
-                }
                if (mmu_reload) {
                        kvm_mmu_reset_context(vcpu);
                        kvm_mmu_load(vcpu);
@@ -2319,7 +2408,7 @@ static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
 {
        struct vmcb_control_area *control;
-        KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
+        trace_kvm_inj_virq(irq);
        ++svm->vcpu.stat.irq_injections;
        control = &svm->vmcb->control;
@@ -2329,21 +2418,14 @@ static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
                ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
 }
-static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
-{
-        struct vcpu_svm *svm = to_svm(vcpu);
-        svm->vmcb->control.event_inj = nr |
-                SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
-}
 static void svm_set_irq(struct kvm_vcpu *vcpu)
 {
        struct vcpu_svm *svm = to_svm(vcpu);
-        nested_svm_intr(svm);
+        BUG_ON(!(gif_set(svm)));
-        svm_queue_irq(vcpu, vcpu->arch.interrupt.nr);
+        svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
+                SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
 }
 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
@@ -2371,13 +2453,25 @@ static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
        struct vmcb *vmcb = svm->vmcb;
        return (vmcb->save.rflags & X86_EFLAGS_IF) &&
                !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
-                (svm->vcpu.arch.hflags & HF_GIF_MASK);
+                gif_set(svm) &&
+                !(is_nested(svm) && (svm->vcpu.arch.hflags & HF_VINTR_MASK));
 }
 static void enable_irq_window(struct kvm_vcpu *vcpu)
 {
-        svm_set_vintr(to_svm(vcpu));
+        struct vcpu_svm *svm = to_svm(vcpu);
-        svm_inject_irq(to_svm(vcpu), 0x0);
+        nsvm_printk("Trying to open IRQ window\n");
+        nested_svm_intr(svm);
+        /* In case GIF=0 we can't rely on the CPU to tell us when
+         * GIF becomes 1, because that's a separate STGI/VMRUN intercept.
+         * The next time we get that intercept, this function will be
+         * called again though and we'll get the vintr intercept. */
+        if (gif_set(svm)) {
+                svm_set_vintr(svm);
+                svm_inject_irq(svm, 0x0);
+        }
 }
 static void enable_nmi_window(struct kvm_vcpu *vcpu)
@@ -2456,6 +2550,8 @@ static void svm_complete_interrupts(struct vcpu_svm *svm)
        case SVM_EXITINTINFO_TYPE_EXEPT:
                /* In case of software exception do not reinject an exception
                   vector, but re-execute and instruction instead */
+                if (is_nested(svm))
+                        break;
                if (kvm_exception_is_soft(vector))
                        break;
                if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
@@ -2498,9 +2594,7 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        fs_selector = kvm_read_fs();
        gs_selector = kvm_read_gs();
        ldt_selector = kvm_read_ldt();
-        svm->host_cr2 = kvm_read_cr2();
+        svm->vmcb->save.cr2 = vcpu->arch.cr2;
-        if (!is_nested(svm))
-                svm->vmcb->save.cr2 = vcpu->arch.cr2;
        /* required for live migration with NPT */
        if (npt_enabled)
                svm->vmcb->save.cr3 = vcpu->arch.cr3;
@@ -2585,8 +2679,6 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
        vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
-        kvm_write_cr2(svm->host_cr2);
        kvm_load_fs(fs_selector);
        kvm_load_gs(gs_selector);
        kvm_load_ldt(ldt_selector);
@@ -2602,7 +2694,10 @@ static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        svm->next_rip = 0;
-        svm_complete_interrupts(svm);
+        if (npt_enabled) {
+                vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
+                vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
+        }
 }
 #undef R
@@ -2673,6 +2768,64 @@ static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
        return 0;
 }
+static const struct trace_print_flags svm_exit_reasons_str[] = {
+        { SVM_EXIT_READ_CR0,                    "read_cr0" },
+        { SVM_EXIT_READ_CR3,                    "read_cr3" },
+        { SVM_EXIT_READ_CR4,                    "read_cr4" },
+        { SVM_EXIT_READ_CR8,                    "read_cr8" },
+        { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
+        { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
+        { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
+        { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
+        { SVM_EXIT_READ_DR0,                    "read_dr0" },
+        { SVM_EXIT_READ_DR1,                    "read_dr1" },
+        { SVM_EXIT_READ_DR2,                    "read_dr2" },
+        { SVM_EXIT_READ_DR3,                    "read_dr3" },
+        { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
+        { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
+        { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
+        { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
+        { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
+        { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
+        { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
+        { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
+        { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
+        { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
+        { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
+        { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
+        { SVM_EXIT_INTR,                        "interrupt" },
+        { SVM_EXIT_NMI,                         "nmi" },
+        { SVM_EXIT_SMI,                         "smi" },
+        { SVM_EXIT_INIT,                        "init" },
+        { SVM_EXIT_VINTR,                       "vintr" },
+        { SVM_EXIT_CPUID,                       "cpuid" },
+        { SVM_EXIT_INVD,                        "invd" },
+        { SVM_EXIT_HLT,                         "hlt" },
+        { SVM_EXIT_INVLPG,                      "invlpg" },
+        { SVM_EXIT_INVLPGA,                     "invlpga" },
+        { SVM_EXIT_IOIO,                        "io" },
+        { SVM_EXIT_MSR,                         "msr" },
+        { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
+        { SVM_EXIT_SHUTDOWN,                    "shutdown" },
+        { SVM_EXIT_VMRUN,                       "vmrun" },
+        { SVM_EXIT_VMMCALL,                     "hypercall" },
+        { SVM_EXIT_VMLOAD,                      "vmload" },
+        { SVM_EXIT_VMSAVE,                      "vmsave" },
+        { SVM_EXIT_STGI,                        "stgi" },
+        { SVM_EXIT_CLGI,                        "clgi" },
+        { SVM_EXIT_SKINIT,                      "skinit" },
+        { SVM_EXIT_WBINVD,                      "wbinvd" },
+        { SVM_EXIT_MONITOR,                     "monitor" },
+        { SVM_EXIT_MWAIT,                       "mwait" },
+        { SVM_EXIT_NPF,                         "npf" },
+        { -1, NULL }
+};
+static bool svm_gb_page_enable(void)
+{
+        return true;
+}
 static struct kvm_x86_ops svm_x86_ops = {
        .cpu_has_kvm_support = has_svm,
        .disabled_by_bios = is_disabled,
@@ -2710,6 +2863,7 @@ static struct kvm_x86_ops svm_x86_ops = {
        .set_gdt = svm_set_gdt,
        .get_dr = svm_get_dr,
        .set_dr = svm_set_dr,
+        .cache_reg = svm_cache_reg,
        .get_rflags = svm_get_rflags,
        .set_rflags = svm_set_rflags,
@@ -2733,6 +2887,9 @@ static struct kvm_x86_ops svm_x86_ops = {
        .set_tss_addr = svm_set_tss_addr,
        .get_tdp_level = get_npt_level,
        .get_mt_mask = svm_get_mt_mask,
+        .exit_reasons_str = svm_exit_reasons_str,
+        .gb_page_enable = svm_gb_page_enable,
 };
 static int __init svm_init(void)
diff --git a/arch/x86/kvm/timer.c b/arch/x86/kvm/timer.c
index 86dbac072d0c..eea40439066c 100644
--- a/arch/x86/kvm/timer.c
+++ b/arch/x86/kvm/timer.c
@@ -9,12 +9,16 @@ static int __kvm_timer_fn(struct kvm_vcpu *vcpu, struct kvm_timer *ktimer)
        int restart_timer = 0;
        wait_queue_head_t *q = &vcpu->wq;
-        /* FIXME: this code should not know anything about vcpus */
+        /*
-        if (!atomic_inc_and_test(&ktimer->pending))
+         * There is a race window between reading and incrementing, but we do
+         * not care about potentially loosing timer events in the !reinject
+         * case anyway.
+         */
+        if (ktimer->reinject || !atomic_read(&ktimer->pending)) {
+                atomic_inc(&ktimer->pending);
+                /* FIXME: this code should not know anything about vcpus */
                set_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
+        }
-        if (!ktimer->reinject)
-                atomic_set(&ktimer->pending, 1);
        if (waitqueue_active(q))
                wake_up_interruptible(q);
@@ -33,7 +37,7 @@ enum hrtimer_restart kvm_timer_fn(struct hrtimer *data)
        struct kvm_vcpu *vcpu;
        struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
-        vcpu = ktimer->kvm->vcpus[ktimer->vcpu_id];
+        vcpu = ktimer->vcpu;
        if (!vcpu)
                return HRTIMER_NORESTART;
diff --git a/arch/x86/kvm/trace.h b/arch/x86/kvm/trace.h
new file mode 100644
index 000000000000..0d480e77eacf
--- /dev/null
+++ b/arch/x86/kvm/trace.h
@@ -0,0 +1,355 @@
+#if !defined(_TRACE_KVM_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_KVM_H
+#include <linux/tracepoint.h>
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM kvm
+#define TRACE_INCLUDE_PATH arch/x86/kvm
+#define TRACE_INCLUDE_FILE trace
+/*
+ * Tracepoint for guest mode entry.
+ */
+TRACE_EVENT(kvm_entry,
+        TP_PROTO(unsigned int vcpu_id),
+        TP_ARGS(vcpu_id),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   vcpu_id         )
+        ),
+        TP_fast_assign(
+                __entry->vcpu_id        = vcpu_id;
+        ),
+        TP_printk("vcpu %u", __entry->vcpu_id)
+);
+/*
+ * Tracepoint for hypercall.
+ */
+TRACE_EVENT(kvm_hypercall,
+        TP_PROTO(unsigned long nr, unsigned long a0, unsigned long a1,
+                 unsigned long a2, unsigned long a3),
+        TP_ARGS(nr, a0, a1, a2, a3),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  nr              )
+                __field(        unsigned long,  a0              )
+                __field(        unsigned long,  a1              )
+                __field(        unsigned long,  a2              )
+                __field(        unsigned long,  a3              )
+        ),
+        TP_fast_assign(
+                __entry->nr             = nr;
+                __entry->a0             = a0;
+                __entry->a1             = a1;
+                __entry->a2             = a2;
+                __entry->a3             = a3;
+        ),
+        TP_printk("nr 0x%lx a0 0x%lx a1 0x%lx a2 0x%lx a3 0x%lx",
+                 __entry->nr, __entry->a0, __entry->a1,  __entry->a2,
+                 __entry->a3)
+);
+/*
+ * Tracepoint for PIO.
+ */
+TRACE_EVENT(kvm_pio,
+        TP_PROTO(unsigned int rw, unsigned int port, unsigned int size,
+                 unsigned int count),
+        TP_ARGS(rw, port, size, count),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   rw              )
+                __field(        unsigned int,   port            )
+                __field(        unsigned int,   size            )
+                __field(        unsigned int,   count           )
+        ),
+        TP_fast_assign(
+                __entry->rw             = rw;
+                __entry->port           = port;
+                __entry->size           = size;
+                __entry->count          = count;
+        ),
+        TP_printk("pio_%s at 0x%x size %d count %d",
+                  __entry->rw ? "write" : "read",
+                  __entry->port, __entry->size, __entry->count)
+);
+/*
+ * Tracepoint for cpuid.
+ */
+TRACE_EVENT(kvm_cpuid,
+        TP_PROTO(unsigned int function, unsigned long rax, unsigned long rbx,
+                 unsigned long rcx, unsigned long rdx),
+        TP_ARGS(function, rax, rbx, rcx, rdx),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   function        )
+                __field(        unsigned long,  rax             )
+                __field(        unsigned long,  rbx             )
+                __field(        unsigned long,  rcx             )
+                __field(        unsigned long,  rdx             )
+        ),
+        TP_fast_assign(
+                __entry->function       = function;
+                __entry->rax            = rax;
+                __entry->rbx            = rbx;
+                __entry->rcx            = rcx;
+                __entry->rdx            = rdx;
+        ),
+        TP_printk("func %x rax %lx rbx %lx rcx %lx rdx %lx",
+                  __entry->function, __entry->rax,
+                  __entry->rbx, __entry->rcx, __entry->rdx)
+);
+#define AREG(x) { APIC_##x, "APIC_" #x }
+#define kvm_trace_symbol_apic                                               \
+        AREG(ID), AREG(LVR), AREG(TASKPRI), AREG(ARBPRI), AREG(PROCPRI),    \
+        AREG(EOI), AREG(RRR), AREG(LDR), AREG(DFR), AREG(SPIV), AREG(ISR),  \
+        AREG(TMR), AREG(IRR), AREG(ESR), AREG(ICR), AREG(ICR2), AREG(LVTT), \
+        AREG(LVTTHMR), AREG(LVTPC), AREG(LVT0), AREG(LVT1), AREG(LVTERR),   \
+        AREG(TMICT), AREG(TMCCT), AREG(TDCR), AREG(SELF_IPI), AREG(EFEAT),  \
+        AREG(ECTRL)
+/*
+ * Tracepoint for apic access.
+ */
+TRACE_EVENT(kvm_apic,
+        TP_PROTO(unsigned int rw, unsigned int reg, unsigned int val),
+        TP_ARGS(rw, reg, val),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   rw              )
+                __field(        unsigned int,   reg             )
+                __field(        unsigned int,   val             )
+        ),
+        TP_fast_assign(
+                __entry->rw             = rw;
+                __entry->reg            = reg;
+                __entry->val            = val;
+        ),
+        TP_printk("apic_%s %s = 0x%x",
+                  __entry->rw ? "write" : "read",
+                  __print_symbolic(__entry->reg, kvm_trace_symbol_apic),
+                  __entry->val)
+);
+#define trace_kvm_apic_read(reg, val)           trace_kvm_apic(0, reg, val)
+#define trace_kvm_apic_write(reg, val)          trace_kvm_apic(1, reg, val)
+/*
+ * Tracepoint for kvm guest exit:
+ */
+TRACE_EVENT(kvm_exit,
+        TP_PROTO(unsigned int exit_reason, unsigned long guest_rip),
+        TP_ARGS(exit_reason, guest_rip),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   exit_reason     )
+                __field(        unsigned long,  guest_rip       )
+        ),
+        TP_fast_assign(
+                __entry->exit_reason    = exit_reason;
+                __entry->guest_rip      = guest_rip;
+        ),
+        TP_printk("reason %s rip 0x%lx",
+                 ftrace_print_symbols_seq(p, __entry->exit_reason,
+                                          kvm_x86_ops->exit_reasons_str),
+                 __entry->guest_rip)
+);
+/*
+ * Tracepoint for kvm interrupt injection:
+ */
+TRACE_EVENT(kvm_inj_virq,
+        TP_PROTO(unsigned int irq),
+        TP_ARGS(irq),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   irq             )
+        ),
+        TP_fast_assign(
+                __entry->irq            = irq;
+        ),
+        TP_printk("irq %u", __entry->irq)
+);
+/*
+ * Tracepoint for page fault.
+ */
+TRACE_EVENT(kvm_page_fault,
+        TP_PROTO(unsigned long fault_address, unsigned int error_code),
+        TP_ARGS(fault_address, error_code),
+        TP_STRUCT__entry(
+                __field(        unsigned long,  fault_address   )
+                __field(        unsigned int,   error_code      )
+        ),
+        TP_fast_assign(
+                __entry->fault_address  = fault_address;
+                __entry->error_code     = error_code;
+        ),
+        TP_printk("address %lx error_code %x",
+                  __entry->fault_address, __entry->error_code)
+);
+/*
+ * Tracepoint for guest MSR access.
+ */
+TRACE_EVENT(kvm_msr,
+        TP_PROTO(unsigned int rw, unsigned int ecx, unsigned long data),
+        TP_ARGS(rw, ecx, data),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   rw              )
+                __field(        unsigned int,   ecx             )
+                __field(        unsigned long,  data            )
+        ),
+        TP_fast_assign(
+                __entry->rw             = rw;
+                __entry->ecx            = ecx;
+                __entry->data           = data;
+        ),
+        TP_printk("msr_%s %x = 0x%lx",
+                  __entry->rw ? "write" : "read",
+                  __entry->ecx, __entry->data)
+);
+#define trace_kvm_msr_read(ecx, data)           trace_kvm_msr(0, ecx, data)
+#define trace_kvm_msr_write(ecx, data)          trace_kvm_msr(1, ecx, data)
+/*
+ * Tracepoint for guest CR access.
+ */
+TRACE_EVENT(kvm_cr,
+        TP_PROTO(unsigned int rw, unsigned int cr, unsigned long val),
+        TP_ARGS(rw, cr, val),
+        TP_STRUCT__entry(
+                __field(        unsigned int,   rw              )
+                __field(        unsigned int,   cr              )
+                __field(        unsigned long,  val             )
+        ),
+        TP_fast_assign(
+                __entry->rw             = rw;
+                __entry->cr             = cr;
+                __entry->val            = val;
+        ),
+        TP_printk("cr_%s %x = 0x%lx",
+                  __entry->rw ? "write" : "read",
+                  __entry->cr, __entry->val)
+);
+#define trace_kvm_cr_read(cr, val)              trace_kvm_cr(0, cr, val)
+#define trace_kvm_cr_write(cr, val)             trace_kvm_cr(1, cr, val)
+TRACE_EVENT(kvm_pic_set_irq,
+            TP_PROTO(__u8 chip, __u8 pin, __u8 elcr, __u8 imr, bool coalesced),
+            TP_ARGS(chip, pin, elcr, imr, coalesced),
+        TP_STRUCT__entry(
+                __field(        __u8,           chip            )
+                __field(        __u8,           pin             )
+                __field(        __u8,           elcr            )
+                __field(        __u8,           imr             )
+                __field(        bool,           coalesced       )
+        ),
+        TP_fast_assign(
+                __entry->chip           = chip;
+                __entry->pin            = pin;
+                __entry->elcr           = elcr;
+                __entry->imr            = imr;
+                __entry->coalesced      = coalesced;
+        ),
+        TP_printk("chip %u pin %u (%s%s)%s",
+                  __entry->chip, __entry->pin,
+                  (__entry->elcr & (1 << __entry->pin)) ? "level":"edge",
+                  (__entry->imr & (1 << __entry->pin)) ? "|masked":"",
+                  __entry->coalesced ? " (coalesced)" : "")
+);
+#define kvm_apic_dst_shorthand          \
+        {0x0, "dst"},                   \
+        {0x1, "self"},                  \
+        {0x2, "all"},                   \
+        {0x3, "all-but-self"}
+TRACE_EVENT(kvm_apic_ipi,
+            TP_PROTO(__u32 icr_low, __u32 dest_id),
+            TP_ARGS(icr_low, dest_id),
+        TP_STRUCT__entry(
+                __field(        __u32,          icr_low         )
+                __field(        __u32,          dest_id         )
+        ),
+        TP_fast_assign(
+                __entry->icr_low        = icr_low;
+                __entry->dest_id        = dest_id;
+        ),
+        TP_printk("dst %x vec %u (%s|%s|%s|%s|%s)",
+                  __entry->dest_id, (u8)__entry->icr_low,
+                  __print_symbolic((__entry->icr_low >> 8 & 0x7),
+                                   kvm_deliver_mode),
+                  (__entry->icr_low & (1<<11)) ? "logical" : "physical",
+                  (__entry->icr_low & (1<<14)) ? "assert" : "de-assert",
+                  (__entry->icr_low & (1<<15)) ? "level" : "edge",
+                  __print_symbolic((__entry->icr_low >> 18 & 0x3),
+                                   kvm_apic_dst_shorthand))
+);
+TRACE_EVENT(kvm_apic_accept_irq,
+            TP_PROTO(__u32 apicid, __u16 dm, __u8 tm, __u8 vec, bool coalesced),
+            TP_ARGS(apicid, dm, tm, vec, coalesced),
+        TP_STRUCT__entry(
+                __field(        __u32,          apicid          )
+                __field(        __u16,          dm              )
+                __field(        __u8,           tm              )
+                __field(        __u8,           vec             )
+                __field(        bool,           coalesced       )
+        ),
+        TP_fast_assign(
+                __entry->apicid         = apicid;
+                __entry->dm             = dm;
+                __entry->tm             = tm;
+                __entry->vec            = vec;
+                __entry->coalesced      = coalesced;
+        ),
+        TP_printk("apicid %x vec %u (%s|%s)%s",
+                  __entry->apicid, __entry->vec,
+                  __print_symbolic((__entry->dm >> 8 & 0x7), kvm_deliver_mode),
+                  __entry->tm ? "level" : "edge",
+                  __entry->coalesced ? " (coalesced)" : "")
+);
+#endif /* _TRACE_KVM_H */
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 29f912927a58..f3812014bd0b 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -25,6 +25,7 @@
 #include <linux/highmem.h>
 #include <linux/sched.h>
 #include <linux/moduleparam.h>
+#include <linux/ftrace_event.h>
 #include "kvm_cache_regs.h"
 #include "x86.h"
@@ -34,6 +35,8 @@
 #include <asm/virtext.h>
 #include <asm/mce.h>
+#include "trace.h"
 #define __ex(x) __kvm_handle_fault_on_reboot(x)
 MODULE_AUTHOR("Qumranet");
@@ -51,6 +54,10 @@ module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
 static int __read_mostly enable_ept = 1;
 module_param_named(ept, enable_ept, bool, S_IRUGO);
+static int __read_mostly enable_unrestricted_guest = 1;
+module_param_named(unrestricted_guest,
+                        enable_unrestricted_guest, bool, S_IRUGO);
 static int __read_mostly emulate_invalid_guest_state = 0;
 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
@@ -84,6 +91,14 @@ struct vcpu_vmx {
                int           guest_efer_loaded;
        } host_state;
        struct {
+                int vm86_active;
+                u8 save_iopl;
+                struct kvm_save_segment {
+                        u16 selector;
+                        unsigned long base;
+                        u32 limit;
+                        u32 ar;
+                } tr, es, ds, fs, gs;
                struct {
                        bool pending;
                        u8 vector;
@@ -161,6 +176,8 @@ static struct kvm_vmx_segment_field {
        VMX_SEGMENT_FIELD(LDTR),
 };
+static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 /*
 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 * away by decrementing the array size.
@@ -256,6 +273,26 @@ static inline bool cpu_has_vmx_flexpriority(void)
                cpu_has_vmx_virtualize_apic_accesses();
 }
+static inline bool cpu_has_vmx_ept_execute_only(void)
+{
+        return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
+}
+static inline bool cpu_has_vmx_eptp_uncacheable(void)
+{
+        return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
+}
+static inline bool cpu_has_vmx_eptp_writeback(void)
+{
+        return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
+}
+static inline bool cpu_has_vmx_ept_2m_page(void)
+{
+        return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
+}
 static inline int cpu_has_vmx_invept_individual_addr(void)
 {
        return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
@@ -277,6 +314,12 @@ static inline int cpu_has_vmx_ept(void)
                SECONDARY_EXEC_ENABLE_EPT;
 }
+static inline int cpu_has_vmx_unrestricted_guest(void)
+{
+        return vmcs_config.cpu_based_2nd_exec_ctrl &
+                SECONDARY_EXEC_UNRESTRICTED_GUEST;
+}
 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 {
        return flexpriority_enabled &&
@@ -497,14 +540,16 @@ static void update_exception_bitmap(struct kvm_vcpu *vcpu)
        eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
        if (!vcpu->fpu_active)
                eb |= 1u << NM_VECTOR;
+        /*
+         * Unconditionally intercept #DB so we can maintain dr6 without
+         * reading it every exit.
+         */
+        eb |= 1u << DB_VECTOR;
        if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
-                if (vcpu->guest_debug &
-                    (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
-                        eb |= 1u << DB_VECTOR;
                if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
                        eb |= 1u << BP_VECTOR;
        }
-        if (vcpu->arch.rmode.vm86_active)
+        if (to_vmx(vcpu)->rmode.vm86_active)
                eb = ~0;
        if (enable_ept)
                eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
@@ -528,12 +573,15 @@ static void reload_tss(void)
 static void load_transition_efer(struct vcpu_vmx *vmx)
 {
        int efer_offset = vmx->msr_offset_efer;
-        u64 host_efer = vmx->host_msrs[efer_offset].data;
+        u64 host_efer;
-        u64 guest_efer = vmx->guest_msrs[efer_offset].data;
+        u64 guest_efer;
        u64 ignore_bits;
        if (efer_offset < 0)
                return;
+        host_efer = vmx->host_msrs[efer_offset].data;
+        guest_efer = vmx->guest_msrs[efer_offset].data;
        /*
         * NX is emulated; LMA and LME handled by hardware; SCE meaninless
         * outside long mode
@@ -735,12 +783,17 @@ static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 {
-        return vmcs_readl(GUEST_RFLAGS);
+        unsigned long rflags;
+        rflags = vmcs_readl(GUEST_RFLAGS);
+        if (to_vmx(vcpu)->rmode.vm86_active)
+                rflags &= ~(unsigned long)(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
+        return rflags;
 }
 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 {
-        if (vcpu->arch.rmode.vm86_active)
+        if (to_vmx(vcpu)->rmode.vm86_active)
                rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
        vmcs_writel(GUEST_RFLAGS, rflags);
 }
@@ -797,12 +850,13 @@ static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
                intr_info |= INTR_INFO_DELIVER_CODE_MASK;
        }
-        if (vcpu->arch.rmode.vm86_active) {
+        if (vmx->rmode.vm86_active) {
                vmx->rmode.irq.pending = true;
                vmx->rmode.irq.vector = nr;
                vmx->rmode.irq.rip = kvm_rip_read(vcpu);
-                if (nr == BP_VECTOR || nr == OF_VECTOR)
+                if (kvm_exception_is_soft(nr))
-                        vmx->rmode.irq.rip++;
+                        vmx->rmode.irq.rip +=
+                                vmx->vcpu.arch.event_exit_inst_len;
                intr_info |= INTR_TYPE_SOFT_INTR;
                vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
                vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
@@ -940,7 +994,7 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
        case MSR_EFER:
                return kvm_get_msr_common(vcpu, msr_index, pdata);
 #endif
-        case MSR_IA32_TIME_STAMP_COUNTER:
+        case MSR_IA32_TSC:
                data = guest_read_tsc();
                break;
        case MSR_IA32_SYSENTER_CS:
@@ -953,9 +1007,9 @@ static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
                data = vmcs_readl(GUEST_SYSENTER_ESP);
                break;
        default:
-                vmx_load_host_state(to_vmx(vcpu));
                msr = find_msr_entry(to_vmx(vcpu), msr_index);
                if (msr) {
+                        vmx_load_host_state(to_vmx(vcpu));
                        data = msr->data;
                        break;
                }
@@ -1000,22 +1054,10 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
        case MSR_IA32_SYSENTER_ESP:
                vmcs_writel(GUEST_SYSENTER_ESP, data);
                break;
-        case MSR_IA32_TIME_STAMP_COUNTER:
+        case MSR_IA32_TSC:
                rdtscll(host_tsc);
                guest_write_tsc(data, host_tsc);
                break;
-        case MSR_P6_PERFCTR0:
-        case MSR_P6_PERFCTR1:
-        case MSR_P6_EVNTSEL0:
-        case MSR_P6_EVNTSEL1:
-                /*
-                 * Just discard all writes to the performance counters; this
-                 * should keep both older linux and windows 64-bit guests
-                 * happy
-                 */
-                pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", msr_index, data);
-                break;
        case MSR_IA32_CR_PAT:
                if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
                        vmcs_write64(GUEST_IA32_PAT, data);
@@ -1024,9 +1066,9 @@ static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
                }
                /* Otherwise falls through to kvm_set_msr_common */
        default:
-                vmx_load_host_state(vmx);
                msr = find_msr_entry(vmx, msr_index);
                if (msr) {
+                        vmx_load_host_state(vmx);
                        msr->data = data;
                        break;
                }
@@ -1046,6 +1088,10 @@ static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
        case VCPU_REGS_RIP:
                vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
                break;
+        case VCPU_EXREG_PDPTR:
+                if (enable_ept)
+                        ept_save_pdptrs(vcpu);
+                break;
        default:
                break;
        }
@@ -1203,7 +1249,8 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
                opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
                        SECONDARY_EXEC_WBINVD_EXITING |
                        SECONDARY_EXEC_ENABLE_VPID |
-                        SECONDARY_EXEC_ENABLE_EPT;
+                        SECONDARY_EXEC_ENABLE_EPT |
+                        SECONDARY_EXEC_UNRESTRICTED_GUEST;
                if (adjust_vmx_controls(min2, opt2,
                                        MSR_IA32_VMX_PROCBASED_CTLS2,
                                        &_cpu_based_2nd_exec_control) < 0)
@@ -1217,12 +1264,9 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
        if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
                /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
                   enabled */
-                min &= ~(CPU_BASED_CR3_LOAD_EXITING |
+                _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
-                         CPU_BASED_CR3_STORE_EXITING |
+                                             CPU_BASED_CR3_STORE_EXITING |
-                         CPU_BASED_INVLPG_EXITING);
+                                             CPU_BASED_INVLPG_EXITING);
-                if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
-                                        &_cpu_based_exec_control) < 0)
-                        return -EIO;
                rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
                      vmx_capability.ept, vmx_capability.vpid);
        }
@@ -1333,8 +1377,13 @@ static __init int hardware_setup(void)
        if (!cpu_has_vmx_vpid())
                enable_vpid = 0;
-        if (!cpu_has_vmx_ept())
+        if (!cpu_has_vmx_ept()) {
                enable_ept = 0;
+                enable_unrestricted_guest = 0;
+        }
+        if (!cpu_has_vmx_unrestricted_guest())
+                enable_unrestricted_guest = 0;
        if (!cpu_has_vmx_flexpriority())
                flexpriority_enabled = 0;
@@ -1342,6 +1391,9 @@ static __init int hardware_setup(void)
        if (!cpu_has_vmx_tpr_shadow())
                kvm_x86_ops->update_cr8_intercept = NULL;
+        if (enable_ept && !cpu_has_vmx_ept_2m_page())
+                kvm_disable_largepages();
        return alloc_kvm_area();
 }
@@ -1372,15 +1424,15 @@ static void enter_pmode(struct kvm_vcpu *vcpu)
        struct vcpu_vmx *vmx = to_vmx(vcpu);
        vmx->emulation_required = 1;
-        vcpu->arch.rmode.vm86_active = 0;
+        vmx->rmode.vm86_active = 0;
-        vmcs_writel(GUEST_TR_BASE, vcpu->arch.rmode.tr.base);
+        vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
-        vmcs_write32(GUEST_TR_LIMIT, vcpu->arch.rmode.tr.limit);
+        vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
-        vmcs_write32(GUEST_TR_AR_BYTES, vcpu->arch.rmode.tr.ar);
+        vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
        flags = vmcs_readl(GUEST_RFLAGS);
        flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
-        flags |= (vcpu->arch.rmode.save_iopl << IOPL_SHIFT);
+        flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
        vmcs_writel(GUEST_RFLAGS, flags);
        vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
@@ -1391,10 +1443,10 @@ static void enter_pmode(struct kvm_vcpu *vcpu)
        if (emulate_invalid_guest_state)
                return;
-        fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
+        fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
-        fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
+        fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
-        fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
+        fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
-        fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
+        fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
        vmcs_write16(GUEST_SS_SELECTOR, 0);
        vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
@@ -1433,20 +1485,23 @@ static void enter_rmode(struct kvm_vcpu *vcpu)
        unsigned long flags;
        struct vcpu_vmx *vmx = to_vmx(vcpu);
+        if (enable_unrestricted_guest)
+                return;
        vmx->emulation_required = 1;
-        vcpu->arch.rmode.vm86_active = 1;
+        vmx->rmode.vm86_active = 1;
-        vcpu->arch.rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
+        vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
        vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
-        vcpu->arch.rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
+        vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
        vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
-        vcpu->arch.rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
+        vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
        vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
        flags = vmcs_readl(GUEST_RFLAGS);
-        vcpu->arch.rmode.save_iopl
+        vmx->rmode.save_iopl
                = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
        flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
@@ -1468,10 +1523,10 @@ static void enter_rmode(struct kvm_vcpu *vcpu)
                vmcs_writel(GUEST_CS_BASE, 0xf0000);
        vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
-        fix_rmode_seg(VCPU_SREG_ES, &vcpu->arch.rmode.es);
+        fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
-        fix_rmode_seg(VCPU_SREG_DS, &vcpu->arch.rmode.ds);
+        fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
-        fix_rmode_seg(VCPU_SREG_GS, &vcpu->arch.rmode.gs);
+        fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
-        fix_rmode_seg(VCPU_SREG_FS, &vcpu->arch.rmode.fs);
+        fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
 continue_rmode:
        kvm_mmu_reset_context(vcpu);
@@ -1545,11 +1600,11 @@ static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
 {
+        if (!test_bit(VCPU_EXREG_PDPTR,
+                      (unsigned long *)&vcpu->arch.regs_dirty))
+                return;
        if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
-                if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
-                        printk(KERN_ERR "EPT: Fail to load pdptrs!\n");
-                        return;
-                }
                vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
                vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
                vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
@@ -1557,6 +1612,21 @@ static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
        }
 }
+static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
+{
+        if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
+                vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
+                vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
+                vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
+                vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
+        }
+        __set_bit(VCPU_EXREG_PDPTR,
+                  (unsigned long *)&vcpu->arch.regs_avail);
+        __set_bit(VCPU_EXREG_PDPTR,
+                  (unsigned long *)&vcpu->arch.regs_dirty);
+}
 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
@@ -1571,8 +1641,6 @@ static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
                              CPU_BASED_CR3_STORE_EXITING));
                vcpu->arch.cr0 = cr0;
                vmx_set_cr4(vcpu, vcpu->arch.cr4);
-                *hw_cr0 |= X86_CR0_PE | X86_CR0_PG;
-                *hw_cr0 &= ~X86_CR0_WP;
        } else if (!is_paging(vcpu)) {
                /* From nonpaging to paging */
                vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
@@ -1581,9 +1649,10 @@ static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
                               CPU_BASED_CR3_STORE_EXITING));
                vcpu->arch.cr0 = cr0;
                vmx_set_cr4(vcpu, vcpu->arch.cr4);
-                if (!(vcpu->arch.cr0 & X86_CR0_WP))
-                        *hw_cr0 &= ~X86_CR0_WP;
        }
+        if (!(cr0 & X86_CR0_WP))
+                *hw_cr0 &= ~X86_CR0_WP;
 }
 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
@@ -1598,15 +1667,21 @@ static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 {
-        unsigned long hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) |
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
-                                KVM_VM_CR0_ALWAYS_ON;
+        unsigned long hw_cr0;
+        if (enable_unrestricted_guest)
+                hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
+                        | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
+        else
+                hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
        vmx_fpu_deactivate(vcpu);
-        if (vcpu->arch.rmode.vm86_active && (cr0 & X86_CR0_PE))
+        if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
                enter_pmode(vcpu);
-        if (!vcpu->arch.rmode.vm86_active && !(cr0 & X86_CR0_PE))
+        if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
                enter_rmode(vcpu);
 #ifdef CONFIG_X86_64
@@ -1650,10 +1725,8 @@ static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
        if (enable_ept) {
                eptp = construct_eptp(cr3);
                vmcs_write64(EPT_POINTER, eptp);
-                ept_sync_context(eptp);
-                ept_load_pdptrs(vcpu);
                guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
-                        VMX_EPT_IDENTITY_PAGETABLE_ADDR;
+                        vcpu->kvm->arch.ept_identity_map_addr;
        }
        vmx_flush_tlb(vcpu);
@@ -1664,7 +1737,7 @@ static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 {
-        unsigned long hw_cr4 = cr4 | (vcpu->arch.rmode.vm86_active ?
+        unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
                    KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
        vcpu->arch.cr4 = cr4;
@@ -1707,16 +1780,13 @@ static void vmx_get_segment(struct kvm_vcpu *vcpu,
 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
 {
-        struct kvm_segment kvm_seg;
        if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
                return 0;
        if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
                return 3;
-        vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
+        return vmcs_read16(GUEST_CS_SELECTOR) & 3;
-        return kvm_seg.selector & 3;
 }
 static u32 vmx_segment_access_rights(struct kvm_segment *var)
@@ -1744,20 +1814,21 @@ static u32 vmx_segment_access_rights(struct kvm_segment *var)
 static void vmx_set_segment(struct kvm_vcpu *vcpu,
                            struct kvm_segment *var, int seg)
 {
+        struct vcpu_vmx *vmx = to_vmx(vcpu);
        struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
        u32 ar;
-        if (vcpu->arch.rmode.vm86_active && seg == VCPU_SREG_TR) {
+        if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
-                vcpu->arch.rmode.tr.selector = var->selector;
+                vmx->rmode.tr.selector = var->selector;
-                vcpu->arch.rmode.tr.base = var->base;
+                vmx->rmode.tr.base = var->base;
-                vcpu->arch.rmode.tr.limit = var->limit;
+                vmx->rmode.tr.limit = var->limit;
-                vcpu->arch.rmode.tr.ar = vmx_segment_access_rights(var);
+                vmx->rmode.tr.ar = vmx_segment_access_rights(var);
                return;
        }
        vmcs_writel(sf->base, var->base);
        vmcs_write32(sf->limit, var->limit);
        vmcs_write16(sf->selector, var->selector);
-        if (vcpu->arch.rmode.vm86_active && var->s) {
+        if (vmx->rmode.vm86_active && var->s) {
                /*
                 * Hack real-mode segments into vm86 compatibility.
                 */
@@ -1766,6 +1837,21 @@ static void vmx_set_segment(struct kvm_vcpu *vcpu,
                ar = 0xf3;
        } else
                ar = vmx_segment_access_rights(var);
+        /*
+         *   Fix the "Accessed" bit in AR field of segment registers for older
+         * qemu binaries.
+         *   IA32 arch specifies that at the time of processor reset the
+         * "Accessed" bit in the AR field of segment registers is 1. And qemu
+         * is setting it to 0 in the usedland code. This causes invalid guest
+         * state vmexit when "unrestricted guest" mode is turned on.
+         *    Fix for this setup issue in cpu_reset is being pushed in the qemu
+         * tree. Newer qemu binaries with that qemu fix would not need this
+         * kvm hack.
+         */
+        if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
+                ar |= 0x1; /* Accessed */
        vmcs_write32(sf->ar_bytes, ar);
 }
@@ -2040,7 +2126,7 @@ static int init_rmode_identity_map(struct kvm *kvm)
        if (likely(kvm->arch.ept_identity_pagetable_done))
                return 1;
        ret = 0;
-        identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
+        identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
        r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
        if (r < 0)
                goto out;
@@ -2062,11 +2148,19 @@ out:
 static void seg_setup(int seg)
 {
        struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
+        unsigned int ar;
        vmcs_write16(sf->selector, 0);
        vmcs_writel(sf->base, 0);
        vmcs_write32(sf->limit, 0xffff);
-        vmcs_write32(sf->ar_bytes, 0xf3);
+        if (enable_unrestricted_guest) {
+                ar = 0x93;
+                if (seg == VCPU_SREG_CS)
+                        ar |= 0x08; /* code segment */
+        } else
+                ar = 0xf3;
+        vmcs_write32(sf->ar_bytes, ar);
 }
 static int alloc_apic_access_page(struct kvm *kvm)
@@ -2101,14 +2195,15 @@ static int alloc_identity_pagetable(struct kvm *kvm)
                goto out;
        kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
        kvm_userspace_mem.flags = 0;
-        kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
+        kvm_userspace_mem.guest_phys_addr =
+                kvm->arch.ept_identity_map_addr;
        kvm_userspace_mem.memory_size = PAGE_SIZE;
        r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
        if (r)
                goto out;
        kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
-                        VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
+                        kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
 out:
        up_write(&kvm->slots_lock);
        return r;
@@ -2209,6 +2304,8 @@ static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
                        exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
                if (!enable_ept)
                        exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
+                if (!enable_unrestricted_guest)
+                        exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
                vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
        }
@@ -2326,14 +2423,14 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
                goto out;
        }
-        vmx->vcpu.arch.rmode.vm86_active = 0;
+        vmx->rmode.vm86_active = 0;
        vmx->soft_vnmi_blocked = 0;
        vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
        kvm_set_cr8(&vmx->vcpu, 0);
        msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
-        if (vmx->vcpu.vcpu_id == 0)
+        if (kvm_vcpu_is_bsp(&vmx->vcpu))
                msr |= MSR_IA32_APICBASE_BSP;
        kvm_set_apic_base(&vmx->vcpu, msr);
@@ -2344,7 +2441,7 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
         * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
         * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
         */
-        if (vmx->vcpu.vcpu_id == 0) {
+        if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
                vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
                vmcs_writel(GUEST_CS_BASE, 0x000f0000);
        } else {
@@ -2373,7 +2470,7 @@ static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
        vmcs_writel(GUEST_SYSENTER_EIP, 0);
        vmcs_writel(GUEST_RFLAGS, 0x02);
-        if (vmx->vcpu.vcpu_id == 0)
+        if (kvm_vcpu_is_bsp(&vmx->vcpu))
                kvm_rip_write(vcpu, 0xfff0);
        else
                kvm_rip_write(vcpu, 0);
@@ -2461,13 +2558,16 @@ static void vmx_inject_irq(struct kvm_vcpu *vcpu)
        uint32_t intr;
        int irq = vcpu->arch.interrupt.nr;
-        KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
+        trace_kvm_inj_virq(irq);
        ++vcpu->stat.irq_injections;
-        if (vcpu->arch.rmode.vm86_active) {
+        if (vmx->rmode.vm86_active) {
                vmx->rmode.irq.pending = true;
                vmx->rmode.irq.vector = irq;
                vmx->rmode.irq.rip = kvm_rip_read(vcpu);
+                if (vcpu->arch.interrupt.soft)
+                        vmx->rmode.irq.rip +=
+                                vmx->vcpu.arch.event_exit_inst_len;
                vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
                             irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
                vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
@@ -2502,7 +2602,7 @@ static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
        }
        ++vcpu->stat.nmi_injections;
-        if (vcpu->arch.rmode.vm86_active) {
+        if (vmx->rmode.vm86_active) {
                vmx->rmode.irq.pending = true;
                vmx->rmode.irq.vector = NMI_VECTOR;
                vmx->rmode.irq.rip = kvm_rip_read(vcpu);
@@ -2659,14 +2759,14 @@ static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                if (enable_ept)
                        BUG();
                cr2 = vmcs_readl(EXIT_QUALIFICATION);
-                KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
+                trace_kvm_page_fault(cr2, error_code);
-                            (u32)((u64)cr2 >> 32), handler);
                if (kvm_event_needs_reinjection(vcpu))
                        kvm_mmu_unprotect_page_virt(vcpu, cr2);
                return kvm_mmu_page_fault(vcpu, cr2, error_code);
        }
-        if (vcpu->arch.rmode.vm86_active &&
+        if (vmx->rmode.vm86_active &&
            handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
                                                                error_code)) {
                if (vcpu->arch.halt_request) {
@@ -2707,7 +2807,6 @@ static int handle_external_interrupt(struct kvm_vcpu *vcpu,
                                     struct kvm_run *kvm_run)
 {
        ++vcpu->stat.irq_exits;
-        KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
        return 1;
 }
@@ -2755,7 +2854,7 @@ vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 {
-        unsigned long exit_qualification;
+        unsigned long exit_qualification, val;
        int cr;
        int reg;
@@ -2764,21 +2863,19 @@ static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        reg = (exit_qualification >> 8) & 15;
        switch ((exit_qualification >> 4) & 3) {
        case 0: /* mov to cr */
-                KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
+                val = kvm_register_read(vcpu, reg);
-                            (u32)kvm_register_read(vcpu, reg),
+                trace_kvm_cr_write(cr, val);
-                            (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
-                            handler);
                switch (cr) {
                case 0:
-                        kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
+                        kvm_set_cr0(vcpu, val);
                        skip_emulated_instruction(vcpu);
                        return 1;
                case 3:
-                        kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
+                        kvm_set_cr3(vcpu, val);
                        skip_emulated_instruction(vcpu);
                        return 1;
                case 4:
-                        kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
+                        kvm_set_cr4(vcpu, val);
                        skip_emulated_instruction(vcpu);
                        return 1;
                case 8: {
@@ -2800,23 +2897,19 @@ static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                vcpu->arch.cr0 &= ~X86_CR0_TS;
                vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
                vmx_fpu_activate(vcpu);
-                KVMTRACE_0D(CLTS, vcpu, handler);
                skip_emulated_instruction(vcpu);
                return 1;
        case 1: /*mov from cr*/
                switch (cr) {
                case 3:
                        kvm_register_write(vcpu, reg, vcpu->arch.cr3);
-                        KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
+                        trace_kvm_cr_read(cr, vcpu->arch.cr3);
-                                    (u32)kvm_register_read(vcpu, reg),
-                                    (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
-                                    handler);
                        skip_emulated_instruction(vcpu);
                        return 1;
                case 8:
-                        kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
+                        val = kvm_get_cr8(vcpu);
-                        KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
+                        kvm_register_write(vcpu, reg, val);
-                                    (u32)kvm_register_read(vcpu, reg), handler);
+                        trace_kvm_cr_read(cr, val);
                        skip_emulated_instruction(vcpu);
                        return 1;
                }
@@ -2841,6 +2934,8 @@ static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        unsigned long val;
        int dr, reg;
+        if (!kvm_require_cpl(vcpu, 0))
+                return 1;
        dr = vmcs_readl(GUEST_DR7);
        if (dr & DR7_GD) {
                /*
@@ -2884,7 +2979,6 @@ static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                        val = 0;
                }
                kvm_register_write(vcpu, reg, val);
-                KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
        } else {
                val = vcpu->arch.regs[reg];
                switch (dr) {
@@ -2917,7 +3011,6 @@ static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                        }
                        break;
                }
-                KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
        }
        skip_emulated_instruction(vcpu);
        return 1;
@@ -2939,8 +3032,7 @@ static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                return 1;
        }
-        KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
+        trace_kvm_msr_read(ecx, data);
-                    handler);
        /* FIXME: handling of bits 32:63 of rax, rdx */
        vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
@@ -2955,8 +3047,7 @@ static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
                | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
-        KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
+        trace_kvm_msr_write(ecx, data);
-                    handler);
        if (vmx_set_msr(vcpu, ecx, data) != 0) {
                kvm_inject_gp(vcpu, 0);
@@ -2983,7 +3074,6 @@ static int handle_interrupt_window(struct kvm_vcpu *vcpu,
        cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
        vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
-        KVMTRACE_0D(PEND_INTR, vcpu, handler);
        ++vcpu->stat.irq_window_exits;
        /*
@@ -3049,7 +3139,7 @@ static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                printk(KERN_ERR
                       "Fail to handle apic access vmexit! Offset is 0x%lx\n",
                       offset);
-                return -ENOTSUPP;
+                return -ENOEXEC;
        }
        return 1;
 }
@@ -3118,7 +3208,7 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        if (exit_qualification & (1 << 6)) {
                printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
-                return -ENOTSUPP;
+                return -EINVAL;
        }
        gla_validity = (exit_qualification >> 7) & 0x3;
@@ -3130,14 +3220,98 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
                        (long unsigned int)exit_qualification);
                kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
-                kvm_run->hw.hardware_exit_reason = 0;
+                kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
-                return -ENOTSUPP;
+                return 0;
        }
        gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
+        trace_kvm_page_fault(gpa, exit_qualification);
        return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
 }
+static u64 ept_rsvd_mask(u64 spte, int level)
+{
+        int i;
+        u64 mask = 0;
+        for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
+                mask |= (1ULL << i);
+        if (level > 2)
+                /* bits 7:3 reserved */
+                mask |= 0xf8;
+        else if (level == 2) {
+                if (spte & (1ULL << 7))
+                        /* 2MB ref, bits 20:12 reserved */
+                        mask |= 0x1ff000;
+                else
+                        /* bits 6:3 reserved */
+                        mask |= 0x78;
+        }
+        return mask;
+}
+static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
+                                       int level)
+{
+        printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
+        /* 010b (write-only) */
+        WARN_ON((spte & 0x7) == 0x2);
+        /* 110b (write/execute) */
+        WARN_ON((spte & 0x7) == 0x6);
+        /* 100b (execute-only) and value not supported by logical processor */
+        if (!cpu_has_vmx_ept_execute_only())
+                WARN_ON((spte & 0x7) == 0x4);
+        /* not 000b */
+        if ((spte & 0x7)) {
+                u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
+                if (rsvd_bits != 0) {
+                        printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
+                                         __func__, rsvd_bits);
+                        WARN_ON(1);
+                }
+                if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
+                        u64 ept_mem_type = (spte & 0x38) >> 3;
+                        if (ept_mem_type == 2 || ept_mem_type == 3 ||
+                            ept_mem_type == 7) {
+                                printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
+                                                __func__, ept_mem_type);
+                                WARN_ON(1);
+                        }
+                }
+        }
+}
+static int handle_ept_misconfig(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
+{
+        u64 sptes[4];
+        int nr_sptes, i;
+        gpa_t gpa;
+        gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
+        printk(KERN_ERR "EPT: Misconfiguration.\n");
+        printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
+        nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
+        for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
+                ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
+        kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
+        kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
+        return 0;
+}
 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 {
        u32 cpu_based_vm_exec_control;
@@ -3217,8 +3391,9 @@ static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
        [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
        [EXIT_REASON_WBINVD]                  = handle_wbinvd,
        [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
-        [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
        [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
+        [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
+        [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
 };
 static const int kvm_vmx_max_exit_handlers =
@@ -3234,8 +3409,7 @@ static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
        u32 exit_reason = vmx->exit_reason;
        u32 vectoring_info = vmx->idt_vectoring_info;
-        KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
+        trace_kvm_exit(exit_reason, kvm_rip_read(vcpu));
-                    (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
        /* If we need to emulate an MMIO from handle_invalid_guest_state
         * we just return 0 */
@@ -3247,10 +3421,8 @@ static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
        /* Access CR3 don't cause VMExit in paging mode, so we need
         * to sync with guest real CR3. */
-        if (enable_ept && is_paging(vcpu)) {
+        if (enable_ept && is_paging(vcpu))
                vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
-                ept_load_pdptrs(vcpu);
-        }
        if (unlikely(vmx->fail)) {
                kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
@@ -3326,10 +3498,8 @@ static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
        /* We need to handle NMIs before interrupts are enabled */
        if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
-            (exit_intr_info & INTR_INFO_VALID_MASK)) {
+            (exit_intr_info & INTR_INFO_VALID_MASK))
-                KVMTRACE_0D(NMI, &vmx->vcpu, handler);
                asm("int $2");
-        }
        idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
@@ -3434,6 +3604,10 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 {
        struct vcpu_vmx *vmx = to_vmx(vcpu);
+        if (enable_ept && is_paging(vcpu)) {
+                vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
+                ept_load_pdptrs(vcpu);
+        }
        /* Record the guest's net vcpu time for enforced NMI injections. */
        if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
                vmx->entry_time = ktime_get();
@@ -3449,12 +3623,21 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
                vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
+        /* When single-stepping over STI and MOV SS, we must clear the
+         * corresponding interruptibility bits in the guest state. Otherwise
+         * vmentry fails as it then expects bit 14 (BS) in pending debug
+         * exceptions being set, but that's not correct for the guest debugging
+         * case. */
+        if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
+                vmx_set_interrupt_shadow(vcpu, 0);
        /*
         * Loading guest fpu may have cleared host cr0.ts
         */
        vmcs_writel(HOST_CR0, read_cr0());
-        set_debugreg(vcpu->arch.dr6, 6);
+        if (vcpu->arch.switch_db_regs)
+                set_debugreg(vcpu->arch.dr6, 6);
        asm(
                /* Store host registers */
@@ -3465,11 +3648,16 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                "mov %%"R"sp, %c[host_rsp](%0) \n\t"
                __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
                "1: \n\t"
+                /* Reload cr2 if changed */
+                "mov %c[cr2](%0), %%"R"ax \n\t"
+                "mov %%cr2, %%"R"dx \n\t"
+                "cmp %%"R"ax, %%"R"dx \n\t"
+                "je 2f \n\t"
+                "mov %%"R"ax, %%cr2 \n\t"
+                "2: \n\t"
                /* Check if vmlaunch of vmresume is needed */
                "cmpl $0, %c[launched](%0) \n\t"
                /* Load guest registers.  Don't clobber flags. */
-                "mov %c[cr2](%0), %%"R"ax \n\t"
-                "mov %%"R"ax, %%cr2 \n\t"
                "mov %c[rax](%0), %%"R"ax \n\t"
                "mov %c[rbx](%0), %%"R"bx \n\t"
                "mov %c[rdx](%0), %%"R"dx \n\t"
@@ -3547,10 +3735,12 @@ static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 #endif
              );
-        vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
+        vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
+                                  | (1 << VCPU_EXREG_PDPTR));
        vcpu->arch.regs_dirty = 0;
-        get_debugreg(vcpu->arch.dr6, 6);
+        if (vcpu->arch.switch_db_regs)
+                get_debugreg(vcpu->arch.dr6, 6);
        vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
        if (vmx->rmode.irq.pending)
@@ -3633,9 +3823,13 @@ static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
                if (alloc_apic_access_page(kvm) != 0)
                        goto free_vmcs;
-        if (enable_ept)
+        if (enable_ept) {
+                if (!kvm->arch.ept_identity_map_addr)
+                        kvm->arch.ept_identity_map_addr =
+                                VMX_EPT_IDENTITY_PAGETABLE_ADDR;
                if (alloc_identity_pagetable(kvm) != 0)
                        goto free_vmcs;
+        }
        return &vmx->vcpu;
@@ -3699,6 +3893,34 @@ static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
        return ret;
 }
+static const struct trace_print_flags vmx_exit_reasons_str[] = {
+        { EXIT_REASON_EXCEPTION_NMI,           "exception" },
+        { EXIT_REASON_EXTERNAL_INTERRUPT,      "ext_irq" },
+        { EXIT_REASON_TRIPLE_FAULT,            "triple_fault" },
+        { EXIT_REASON_NMI_WINDOW,              "nmi_window" },
+        { EXIT_REASON_IO_INSTRUCTION,          "io_instruction" },
+        { EXIT_REASON_CR_ACCESS,               "cr_access" },
+        { EXIT_REASON_DR_ACCESS,               "dr_access" },
+        { EXIT_REASON_CPUID,                   "cpuid" },
+        { EXIT_REASON_MSR_READ,                "rdmsr" },
+        { EXIT_REASON_MSR_WRITE,               "wrmsr" },
+        { EXIT_REASON_PENDING_INTERRUPT,       "interrupt_window" },
+        { EXIT_REASON_HLT,                     "halt" },
+        { EXIT_REASON_INVLPG,                  "invlpg" },
+        { EXIT_REASON_VMCALL,                  "hypercall" },
+        { EXIT_REASON_TPR_BELOW_THRESHOLD,     "tpr_below_thres" },
+        { EXIT_REASON_APIC_ACCESS,             "apic_access" },
+        { EXIT_REASON_WBINVD,                  "wbinvd" },
+        { EXIT_REASON_TASK_SWITCH,             "task_switch" },
+        { EXIT_REASON_EPT_VIOLATION,           "ept_violation" },
+        { -1, NULL }
+};
+static bool vmx_gb_page_enable(void)
+{
+        return false;
+}
 static struct kvm_x86_ops vmx_x86_ops = {
        .cpu_has_kvm_support = cpu_has_kvm_support,
        .disabled_by_bios = vmx_disabled_by_bios,
@@ -3758,6 +3980,9 @@ static struct kvm_x86_ops vmx_x86_ops = {
        .set_tss_addr = vmx_set_tss_addr,
        .get_tdp_level = get_ept_level,
        .get_mt_mask = vmx_get_mt_mask,
+        .exit_reasons_str = vmx_exit_reasons_str,
+        .gb_page_enable = vmx_gb_page_enable,
 };
 static int __init vmx_init(void)
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 3d4529011828..74029f50b26a 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -37,11 +37,16 @@
 #include <linux/iommu.h>
 #include <linux/intel-iommu.h>
 #include <linux/cpufreq.h>
+#include <trace/events/kvm.h>
+#undef TRACE_INCLUDE_FILE
+#define CREATE_TRACE_POINTS
+#include "trace.h"
 #include <asm/uaccess.h>
 #include <asm/msr.h>
 #include <asm/desc.h>
 #include <asm/mtrr.h>
+#include <asm/mce.h>
 #define MAX_IO_MSRS 256
 #define CR0_RESERVED_BITS                                               \
@@ -55,6 +60,10 @@
                          | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
 #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
+#define KVM_MAX_MCE_BANKS 32
+#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
 /* EFER defaults:
 * - enable syscall per default because its emulated by KVM
 * - enable LME and LMA per default on 64 bit KVM
@@ -68,14 +77,16 @@ static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
 #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
 #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
+static void update_cr8_intercept(struct kvm_vcpu *vcpu);
 static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
                                    struct kvm_cpuid_entry2 __user *entries);
-struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
-                                              u32 function, u32 index);
 struct kvm_x86_ops *kvm_x86_ops;
 EXPORT_SYMBOL_GPL(kvm_x86_ops);
+int ignore_msrs = 0;
+module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
 struct kvm_stats_debugfs_item debugfs_entries[] = {
        { "pf_fixed", VCPU_STAT(pf_fixed) },
        { "pf_guest", VCPU_STAT(pf_guest) },
@@ -122,18 +133,16 @@ unsigned long segment_base(u16 selector)
        if (selector == 0)
                return 0;
-        asm("sgdt %0" : "=m"(gdt));
+        kvm_get_gdt(&gdt);
        table_base = gdt.base;
        if (selector & 4) {           /* from ldt */
-                u16 ldt_selector;
+                u16 ldt_selector = kvm_read_ldt();
-                asm("sldt %0" : "=g"(ldt_selector));
                table_base = segment_base(ldt_selector);
        }
        d = (struct desc_struct *)(table_base + (selector & ~7));
-        v = d->base0 | ((unsigned long)d->base1 << 16) |
+        v = get_desc_base(d);
-                ((unsigned long)d->base2 << 24);
 #ifdef CONFIG_X86_64
        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
@@ -176,16 +185,22 @@ void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
        ++vcpu->stat.pf_guest;
        if (vcpu->arch.exception.pending) {
-                if (vcpu->arch.exception.nr == PF_VECTOR) {
+                switch(vcpu->arch.exception.nr) {
-                        printk(KERN_DEBUG "kvm: inject_page_fault:"
+                case DF_VECTOR:
-                                        " double fault 0x%lx\n", addr);
-                        vcpu->arch.exception.nr = DF_VECTOR;
-                        vcpu->arch.exception.error_code = 0;
-                } else if (vcpu->arch.exception.nr == DF_VECTOR) {
                        /* triple fault -> shutdown */
                        set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
+                        return;
+                case PF_VECTOR:
+                        vcpu->arch.exception.nr = DF_VECTOR;
+                        vcpu->arch.exception.error_code = 0;
+                        return;
+                default:
+                        /* replace previous exception with a new one in a hope
+                           that instruction re-execution will regenerate lost
+                           exception */
+                        vcpu->arch.exception.pending = false;
+                        break;
                }
-                return;
        }
        vcpu->arch.cr2 = addr;
        kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
@@ -207,12 +222,18 @@ void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
 }
 EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
-static void __queue_exception(struct kvm_vcpu *vcpu)
+/*
+ * Checks if cpl <= required_cpl; if true, return true.  Otherwise queue
+ * a #GP and return false.
+ */
+bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
 {
-        kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
+        if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
-                                     vcpu->arch.exception.has_error_code,
+                return true;
-                                     vcpu->arch.exception.error_code);
+        kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
+        return false;
 }
+EXPORT_SYMBOL_GPL(kvm_require_cpl);
 /*
 * Load the pae pdptrs.  Return true is they are all valid.
@@ -232,7 +253,7 @@ int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
                goto out;
        }
        for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
-                if (is_present_pte(pdpte[i]) &&
+                if (is_present_gpte(pdpte[i]) &&
                    (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
                        ret = 0;
                        goto out;
@@ -241,6 +262,10 @@ int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
        ret = 1;
        memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
+        __set_bit(VCPU_EXREG_PDPTR,
+                  (unsigned long *)&vcpu->arch.regs_avail);
+        __set_bit(VCPU_EXREG_PDPTR,
+                  (unsigned long *)&vcpu->arch.regs_dirty);
 out:
        return ret;
@@ -256,6 +281,10 @@ static bool pdptrs_changed(struct kvm_vcpu *vcpu)
        if (is_long_mode(vcpu) || !is_pae(vcpu))
                return false;
+        if (!test_bit(VCPU_EXREG_PDPTR,
+                      (unsigned long *)&vcpu->arch.regs_avail))
+                return true;
        r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
        if (r < 0)
                goto out;
@@ -328,9 +357,6 @@ EXPORT_SYMBOL_GPL(kvm_set_cr0);
 void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
 {
        kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
-        KVMTRACE_1D(LMSW, vcpu,
-                    (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
-                    handler);
 }
 EXPORT_SYMBOL_GPL(kvm_lmsw);
@@ -466,7 +492,7 @@ static u32 msrs_to_save[] = {
 #ifdef CONFIG_X86_64
        MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
 #endif
-        MSR_IA32_TIME_STAMP_COUNTER, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
+        MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
        MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
 };
@@ -644,8 +670,7 @@ static void kvm_write_guest_time(struct kvm_vcpu *v)
        /* Keep irq disabled to prevent changes to the clock */
        local_irq_save(flags);
-        kvm_get_msr(v, MSR_IA32_TIME_STAMP_COUNTER,
+        kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
-                          &vcpu->hv_clock.tsc_timestamp);
        ktime_get_ts(&ts);
        local_irq_restore(flags);
@@ -778,23 +803,60 @@ static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
        return 0;
 }
+static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
+{
+        u64 mcg_cap = vcpu->arch.mcg_cap;
+        unsigned bank_num = mcg_cap & 0xff;
+        switch (msr) {
+        case MSR_IA32_MCG_STATUS:
+                vcpu->arch.mcg_status = data;
+                break;
+        case MSR_IA32_MCG_CTL:
+                if (!(mcg_cap & MCG_CTL_P))
+                        return 1;
+                if (data != 0 && data != ~(u64)0)
+                        return -1;
+                vcpu->arch.mcg_ctl = data;
+                break;
+        default:
+                if (msr >= MSR_IA32_MC0_CTL &&
+                    msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
+                        u32 offset = msr - MSR_IA32_MC0_CTL;
+                        /* only 0 or all 1s can be written to IA32_MCi_CTL */
+                        if ((offset & 0x3) == 0 &&
+                            data != 0 && data != ~(u64)0)
+                                return -1;
+                        vcpu->arch.mce_banks[offset] = data;
+                        break;
+                }
+                return 1;
+        }
+        return 0;
+}
 int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
 {
        switch (msr) {
        case MSR_EFER:
                set_efer(vcpu, data);
                break;
-        case MSR_IA32_MC0_STATUS:
+        case MSR_K7_HWCR:
-                pr_unimpl(vcpu, "%s: MSR_IA32_MC0_STATUS 0x%llx, nop\n",
+                data &= ~(u64)0x40;     /* ignore flush filter disable */
-                       __func__, data);
+                if (data != 0) {
+                        pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
+                                data);
+                        return 1;
+                }
                break;
-        case MSR_IA32_MCG_STATUS:
+        case MSR_FAM10H_MMIO_CONF_BASE:
-                pr_unimpl(vcpu, "%s: MSR_IA32_MCG_STATUS 0x%llx, nop\n",
+                if (data != 0) {
-                        __func__, data);
+                        pr_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
+                                "0x%llx\n", data);
+                        return 1;
+                }
                break;
-        case MSR_IA32_MCG_CTL:
+        case MSR_AMD64_NB_CFG:
-                pr_unimpl(vcpu, "%s: MSR_IA32_MCG_CTL 0x%llx, nop\n",
-                        __func__, data);
                break;
        case MSR_IA32_DEBUGCTLMSR:
                if (!data) {
@@ -811,12 +873,15 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
        case MSR_IA32_UCODE_REV:
        case MSR_IA32_UCODE_WRITE:
        case MSR_VM_HSAVE_PA:
+        case MSR_AMD64_PATCH_LOADER:
                break;
        case 0x200 ... 0x2ff:
                return set_msr_mtrr(vcpu, msr, data);
        case MSR_IA32_APICBASE:
                kvm_set_apic_base(vcpu, data);
                break;
+        case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
+                return kvm_x2apic_msr_write(vcpu, msr, data);
        case MSR_IA32_MISC_ENABLE:
                vcpu->arch.ia32_misc_enable_msr = data;
                break;
@@ -850,9 +915,50 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
                kvm_request_guest_time_update(vcpu);
                break;
        }
+        case MSR_IA32_MCG_CTL:
+        case MSR_IA32_MCG_STATUS:
+        case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
+                return set_msr_mce(vcpu, msr, data);
+        /* Performance counters are not protected by a CPUID bit,
+         * so we should check all of them in the generic path for the sake of
+         * cross vendor migration.
+         * Writing a zero into the event select MSRs disables them,
+         * which we perfectly emulate ;-). Any other value should be at least
+         * reported, some guests depend on them.
+         */
+        case MSR_P6_EVNTSEL0:
+        case MSR_P6_EVNTSEL1:
+        case MSR_K7_EVNTSEL0:
+        case MSR_K7_EVNTSEL1:
+        case MSR_K7_EVNTSEL2:
+        case MSR_K7_EVNTSEL3:
+                if (data != 0)
+                        pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
+                                "0x%x data 0x%llx\n", msr, data);
+                break;
+        /* at least RHEL 4 unconditionally writes to the perfctr registers,
+         * so we ignore writes to make it happy.
+         */
+        case MSR_P6_PERFCTR0:
+        case MSR_P6_PERFCTR1:
+        case MSR_K7_PERFCTR0:
+        case MSR_K7_PERFCTR1:
+        case MSR_K7_PERFCTR2:
+        case MSR_K7_PERFCTR3:
+                pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
+                        "0x%x data 0x%llx\n", msr, data);
+                break;
        default:
-                pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
+                if (!ignore_msrs) {
-                return 1;
+                        pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
+                                msr, data);
+                        return 1;
+                } else {
+                        pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
+                                msr, data);
+                        break;
+                }
        }
        return 0;
 }
@@ -905,26 +1011,47 @@ static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
        return 0;
 }
-int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
+static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
 {
        u64 data;
+        u64 mcg_cap = vcpu->arch.mcg_cap;
+        unsigned bank_num = mcg_cap & 0xff;
        switch (msr) {
-        case 0xc0010010: /* SYSCFG */
-        case 0xc0010015: /* HWCR */
-        case MSR_IA32_PLATFORM_ID:
        case MSR_IA32_P5_MC_ADDR:
        case MSR_IA32_P5_MC_TYPE:
-        case MSR_IA32_MC0_CTL:
+                data = 0;
-        case MSR_IA32_MCG_STATUS:
+                break;
        case MSR_IA32_MCG_CAP:
+                data = vcpu->arch.mcg_cap;
+                break;
        case MSR_IA32_MCG_CTL:
-        case MSR_IA32_MC0_MISC:
+                if (!(mcg_cap & MCG_CTL_P))
-        case MSR_IA32_MC0_MISC+4:
+                        return 1;
-        case MSR_IA32_MC0_MISC+8:
+                data = vcpu->arch.mcg_ctl;
-        case MSR_IA32_MC0_MISC+12:
+                break;
-        case MSR_IA32_MC0_MISC+16:
+        case MSR_IA32_MCG_STATUS:
-        case MSR_IA32_MC0_MISC+20:
+                data = vcpu->arch.mcg_status;
+                break;
+        default:
+                if (msr >= MSR_IA32_MC0_CTL &&
+                    msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
+                        u32 offset = msr - MSR_IA32_MC0_CTL;
+                        data = vcpu->arch.mce_banks[offset];
+                        break;
+                }
+                return 1;
+        }
+        *pdata = data;
+        return 0;
+}
+int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
+{
+        u64 data;
+        switch (msr) {
+        case MSR_IA32_PLATFORM_ID:
        case MSR_IA32_UCODE_REV:
        case MSR_IA32_EBL_CR_POWERON:
        case MSR_IA32_DEBUGCTLMSR:
@@ -932,10 +1059,18 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
        case MSR_IA32_LASTBRANCHTOIP:
        case MSR_IA32_LASTINTFROMIP:
        case MSR_IA32_LASTINTTOIP:
+        case MSR_K8_SYSCFG:
+        case MSR_K7_HWCR:
        case MSR_VM_HSAVE_PA:
+        case MSR_P6_PERFCTR0:
+        case MSR_P6_PERFCTR1:
        case MSR_P6_EVNTSEL0:
        case MSR_P6_EVNTSEL1:
        case MSR_K7_EVNTSEL0:
+        case MSR_K7_PERFCTR0:
+        case MSR_K8_INT_PENDING_MSG:
+        case MSR_AMD64_NB_CFG:
+        case MSR_FAM10H_MMIO_CONF_BASE:
                data = 0;
                break;
        case MSR_MTRRcap:
@@ -949,6 +1084,9 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
        case MSR_IA32_APICBASE:
                data = kvm_get_apic_base(vcpu);
                break;
+        case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
+                return kvm_x2apic_msr_read(vcpu, msr, pdata);
+                break;
        case MSR_IA32_MISC_ENABLE:
                data = vcpu->arch.ia32_misc_enable_msr;
                break;
@@ -967,9 +1105,22 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
        case MSR_KVM_SYSTEM_TIME:
                data = vcpu->arch.time;
                break;
+        case MSR_IA32_P5_MC_ADDR:
+        case MSR_IA32_P5_MC_TYPE:
+        case MSR_IA32_MCG_CAP:
+        case MSR_IA32_MCG_CTL:
+        case MSR_IA32_MCG_STATUS:
+        case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
+                return get_msr_mce(vcpu, msr, pdata);
        default:
-                pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
+                if (!ignore_msrs) {
-                return 1;
+                        pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
+                        return 1;
+                } else {
+                        pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
+                        data = 0;
+                }
+                break;
        }
        *pdata = data;
        return 0;
@@ -1068,6 +1219,11 @@ int kvm_dev_ioctl_check_extension(long ext)
        case KVM_CAP_REINJECT_CONTROL:
        case KVM_CAP_IRQ_INJECT_STATUS:
        case KVM_CAP_ASSIGN_DEV_IRQ:
+        case KVM_CAP_IRQFD:
+        case KVM_CAP_IOEVENTFD:
+        case KVM_CAP_PIT2:
+        case KVM_CAP_PIT_STATE2:
+        case KVM_CAP_SET_IDENTITY_MAP_ADDR:
                r = 1;
                break;
        case KVM_CAP_COALESCED_MMIO:
@@ -1088,6 +1244,9 @@ int kvm_dev_ioctl_check_extension(long ext)
        case KVM_CAP_IOMMU:
                r = iommu_found();
                break;
+        case KVM_CAP_MCE:
+                r = KVM_MAX_MCE_BANKS;
+                break;
        default:
                r = 0;
                break;
@@ -1147,6 +1306,16 @@ long kvm_arch_dev_ioctl(struct file *filp,
                r = 0;
                break;
        }
+        case KVM_X86_GET_MCE_CAP_SUPPORTED: {
+                u64 mce_cap;
+                mce_cap = KVM_MCE_CAP_SUPPORTED;
+                r = -EFAULT;
+                if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
+                        goto out;
+                r = 0;
+                break;
+        }
        default:
                r = -EINVAL;
        }
@@ -1227,6 +1396,7 @@ static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
        vcpu->arch.cpuid_nent = cpuid->nent;
        cpuid_fix_nx_cap(vcpu);
        r = 0;
+        kvm_apic_set_version(vcpu);
 out_free:
        vfree(cpuid_entries);
@@ -1248,6 +1418,7 @@ static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
                           cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
                goto out;
        vcpu->arch.cpuid_nent = cpuid->nent;
+        kvm_apic_set_version(vcpu);
        return 0;
 out:
@@ -1290,6 +1461,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                         u32 index, int *nent, int maxnent)
 {
        unsigned f_nx = is_efer_nx() ? F(NX) : 0;
+        unsigned f_gbpages = kvm_x86_ops->gb_page_enable() ? F(GBPAGES) : 0;
 #ifdef CONFIG_X86_64
        unsigned f_lm = F(LM);
 #else
@@ -1314,7 +1486,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
                F(PAT) | F(PSE36) | 0 /* Reserved */ |
                f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
-                F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
+                F(FXSR) | F(FXSR_OPT) | f_gbpages | 0 /* RDTSCP */ |
                0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
        /* cpuid 1.ecx */
        const u32 kvm_supported_word4_x86_features =
@@ -1323,7 +1495,7 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
                0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
                0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
                0 /* Reserved, DCA */ | F(XMM4_1) |
-                F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
+                F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
                0 /* Reserved, XSAVE, OSXSAVE */;
        /* cpuid 0x80000001.ecx */
        const u32 kvm_supported_word6_x86_features =
@@ -1344,6 +1516,9 @@ static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
        case 1:
                entry->edx &= kvm_supported_word0_x86_features;
                entry->ecx &= kvm_supported_word4_x86_features;
+                /* we support x2apic emulation even if host does not support
+                 * it since we emulate x2apic in software */
+                entry->ecx |= F(X2APIC);
                break;
        /* function 2 entries are STATEFUL. That is, repeated cpuid commands
         * may return different values. This forces us to get_cpu() before
@@ -1435,6 +1610,10 @@ static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
        for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
                do_cpuid_ent(&cpuid_entries[nent], func, 0,
                             &nent, cpuid->nent);
+        r = -E2BIG;
+        if (nent >= cpuid->nent)
+                goto out_free;
        r = -EFAULT;
        if (copy_to_user(entries, cpuid_entries,
                         nent * sizeof(struct kvm_cpuid_entry2)))
@@ -1464,6 +1643,7 @@ static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
        vcpu_load(vcpu);
        memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
        kvm_apic_post_state_restore(vcpu);
+        update_cr8_intercept(vcpu);
        vcpu_put(vcpu);
        return 0;
@@ -1503,6 +1683,80 @@ static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
        return 0;
 }
+static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
+                                        u64 mcg_cap)
+{
+        int r;
+        unsigned bank_num = mcg_cap & 0xff, bank;
+        r = -EINVAL;
+        if (!bank_num)
+                goto out;
+        if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
+                goto out;
+        r = 0;
+        vcpu->arch.mcg_cap = mcg_cap;
+        /* Init IA32_MCG_CTL to all 1s */
+        if (mcg_cap & MCG_CTL_P)
+                vcpu->arch.mcg_ctl = ~(u64)0;
+        /* Init IA32_MCi_CTL to all 1s */
+        for (bank = 0; bank < bank_num; bank++)
+                vcpu->arch.mce_banks[bank*4] = ~(u64)0;
+out:
+        return r;
+}
+static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
+                                      struct kvm_x86_mce *mce)
+{
+        u64 mcg_cap = vcpu->arch.mcg_cap;
+        unsigned bank_num = mcg_cap & 0xff;
+        u64 *banks = vcpu->arch.mce_banks;
+        if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
+                return -EINVAL;
+        /*
+         * if IA32_MCG_CTL is not all 1s, the uncorrected error
+         * reporting is disabled
+         */
+        if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
+            vcpu->arch.mcg_ctl != ~(u64)0)
+                return 0;
+        banks += 4 * mce->bank;
+        /*
+         * if IA32_MCi_CTL is not all 1s, the uncorrected error
+         * reporting is disabled for the bank
+         */
+        if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
+                return 0;
+        if (mce->status & MCI_STATUS_UC) {
+                if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
+                    !(vcpu->arch.cr4 & X86_CR4_MCE)) {
+                        printk(KERN_DEBUG "kvm: set_mce: "
+                               "injects mce exception while "
+                               "previous one is in progress!\n");
+                        set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
+                        return 0;
+                }
+                if (banks[1] & MCI_STATUS_VAL)
+                        mce->status |= MCI_STATUS_OVER;
+                banks[2] = mce->addr;
+                banks[3] = mce->misc;
+                vcpu->arch.mcg_status = mce->mcg_status;
+                banks[1] = mce->status;
+                kvm_queue_exception(vcpu, MC_VECTOR);
+        } else if (!(banks[1] & MCI_STATUS_VAL)
+                   || !(banks[1] & MCI_STATUS_UC)) {
+                if (banks[1] & MCI_STATUS_VAL)
+                        mce->status |= MCI_STATUS_OVER;
+                banks[2] = mce->addr;
+                banks[3] = mce->misc;
+                banks[1] = mce->status;
+        } else
+                banks[1] |= MCI_STATUS_OVER;
+        return 0;
+}
 long kvm_arch_vcpu_ioctl(struct file *filp,
                         unsigned int ioctl, unsigned long arg)
 {
@@ -1636,6 +1890,24 @@ long kvm_arch_vcpu_ioctl(struct file *filp,
                kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
                break;
        }
+        case KVM_X86_SETUP_MCE: {
+                u64 mcg_cap;
+                r = -EFAULT;
+                if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
+                        goto out;
+                r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
+                break;
+        }
+        case KVM_X86_SET_MCE: {
+                struct kvm_x86_mce mce;
+                r = -EFAULT;
+                if (copy_from_user(&mce, argp, sizeof mce))
+                        goto out;
+                r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
+                break;
+        }
        default:
                r = -EINVAL;
        }
@@ -1654,6 +1926,13 @@ static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
        return ret;
 }
+static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
+                                              u64 ident_addr)
+{
+        kvm->arch.ept_identity_map_addr = ident_addr;
+        return 0;
+}
 static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
                                          u32 kvm_nr_mmu_pages)
 {
@@ -1775,19 +2054,25 @@ static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
        r = 0;
        switch (chip->chip_id) {
        case KVM_IRQCHIP_PIC_MASTER:
+                spin_lock(&pic_irqchip(kvm)->lock);
                memcpy(&pic_irqchip(kvm)->pics[0],
                        &chip->chip.pic,
                        sizeof(struct kvm_pic_state));
+                spin_unlock(&pic_irqchip(kvm)->lock);
                break;
        case KVM_IRQCHIP_PIC_SLAVE:
+                spin_lock(&pic_irqchip(kvm)->lock);
                memcpy(&pic_irqchip(kvm)->pics[1],
                        &chip->chip.pic,
                        sizeof(struct kvm_pic_state));
+                spin_unlock(&pic_irqchip(kvm)->lock);
                break;
        case KVM_IRQCHIP_IOAPIC:
+                mutex_lock(&kvm->irq_lock);
                memcpy(ioapic_irqchip(kvm),
                        &chip->chip.ioapic,
                        sizeof(struct kvm_ioapic_state));
+                mutex_unlock(&kvm->irq_lock);
                break;
        default:
                r = -EINVAL;
@@ -1801,7 +2086,9 @@ static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
 {
        int r = 0;
+        mutex_lock(&kvm->arch.vpit->pit_state.lock);
        memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
+        mutex_unlock(&kvm->arch.vpit->pit_state.lock);
        return r;
 }
@@ -1809,8 +2096,39 @@ static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
 {
        int r = 0;
+        mutex_lock(&kvm->arch.vpit->pit_state.lock);
        memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
-        kvm_pit_load_count(kvm, 0, ps->channels[0].count);
+        kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
+        mutex_unlock(&kvm->arch.vpit->pit_state.lock);
+        return r;
+}
+static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
+{
+        int r = 0;
+        mutex_lock(&kvm->arch.vpit->pit_state.lock);
+        memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
+                sizeof(ps->channels));
+        ps->flags = kvm->arch.vpit->pit_state.flags;
+        mutex_unlock(&kvm->arch.vpit->pit_state.lock);
+        return r;
+}
+static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
+{
+        int r = 0, start = 0;
+        u32 prev_legacy, cur_legacy;
+        mutex_lock(&kvm->arch.vpit->pit_state.lock);
+        prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
+        cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
+        if (!prev_legacy && cur_legacy)
+                start = 1;
+        memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
+               sizeof(kvm->arch.vpit->pit_state.channels));
+        kvm->arch.vpit->pit_state.flags = ps->flags;
+        kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
+        mutex_unlock(&kvm->arch.vpit->pit_state.lock);
        return r;
 }
@@ -1819,7 +2137,9 @@ static int kvm_vm_ioctl_reinject(struct kvm *kvm,
 {
        if (!kvm->arch.vpit)
                return -ENXIO;
+        mutex_lock(&kvm->arch.vpit->pit_state.lock);
        kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
+        mutex_unlock(&kvm->arch.vpit->pit_state.lock);
        return 0;
 }
@@ -1845,7 +2165,6 @@ int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
                spin_lock(&kvm->mmu_lock);
                kvm_mmu_slot_remove_write_access(kvm, log->slot);
                spin_unlock(&kvm->mmu_lock);
-                kvm_flush_remote_tlbs(kvm);
                memslot = &kvm->memslots[log->slot];
                n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
                memset(memslot->dirty_bitmap, 0, n);
@@ -1869,7 +2188,9 @@ long kvm_arch_vm_ioctl(struct file *filp,
         */
        union {
                struct kvm_pit_state ps;
+                struct kvm_pit_state2 ps2;
                struct kvm_memory_alias alias;
+                struct kvm_pit_config pit_config;
        } u;
        switch (ioctl) {
@@ -1878,6 +2199,17 @@ long kvm_arch_vm_ioctl(struct file *filp,
                if (r < 0)
                        goto out;
                break;
+        case KVM_SET_IDENTITY_MAP_ADDR: {
+                u64 ident_addr;
+                r = -EFAULT;
+                if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
+                        goto out;
+                r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
+                if (r < 0)
+                        goto out;
+                break;
+        }
        case KVM_SET_MEMORY_REGION: {
                struct kvm_memory_region kvm_mem;
                struct kvm_userspace_memory_region kvm_userspace_mem;
@@ -1930,16 +2262,24 @@ long kvm_arch_vm_ioctl(struct file *filp,
                }
                break;
        case KVM_CREATE_PIT:
-                mutex_lock(&kvm->lock);
+                u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
+                goto create_pit;
+        case KVM_CREATE_PIT2:
+                r = -EFAULT;
+                if (copy_from_user(&u.pit_config, argp,
+                                   sizeof(struct kvm_pit_config)))
+                        goto out;
+        create_pit:
+                down_write(&kvm->slots_lock);
                r = -EEXIST;
                if (kvm->arch.vpit)
                        goto create_pit_unlock;
                r = -ENOMEM;
-                kvm->arch.vpit = kvm_create_pit(kvm);
+                kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
                if (kvm->arch.vpit)
                        r = 0;
        create_pit_unlock:
-                mutex_unlock(&kvm->lock);
+                up_write(&kvm->slots_lock);
                break;
        case KVM_IRQ_LINE_STATUS:
        case KVM_IRQ_LINE: {
@@ -1950,10 +2290,10 @@ long kvm_arch_vm_ioctl(struct file *filp,
                        goto out;
                if (irqchip_in_kernel(kvm)) {
                        __s32 status;
-                        mutex_lock(&kvm->lock);
+                        mutex_lock(&kvm->irq_lock);
                        status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
                                        irq_event.irq, irq_event.level);
-                        mutex_unlock(&kvm->lock);
+                        mutex_unlock(&kvm->irq_lock);
                        if (ioctl == KVM_IRQ_LINE_STATUS) {
                                irq_event.status = status;
                                if (copy_to_user(argp, &irq_event,
@@ -2042,6 +2382,32 @@ long kvm_arch_vm_ioctl(struct file *filp,
                r = 0;
                break;
        }
+        case KVM_GET_PIT2: {
+                r = -ENXIO;
+                if (!kvm->arch.vpit)
+                        goto out;
+                r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
+                if (r)
+                        goto out;
+                r = -EFAULT;
+                if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
+                        goto out;
+                r = 0;
+                break;
+        }
+        case KVM_SET_PIT2: {
+                r = -EFAULT;
+                if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
+                        goto out;
+                r = -ENXIO;
+                if (!kvm->arch.vpit)
+                        goto out;
+                r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
+                if (r)
+                        goto out;
+                r = 0;
+                break;
+        }
        case KVM_REINJECT_CONTROL: {
                struct kvm_reinject_control control;
                r =  -EFAULT;
@@ -2075,35 +2441,23 @@ static void kvm_init_msr_list(void)
        num_msrs_to_save = j;
 }
-/*
+static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
- * Only apic need an MMIO device hook, so shortcut now..
+                           const void *v)
- */
-static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
-                                                gpa_t addr, int len,
-                                                int is_write)
 {
-        struct kvm_io_device *dev;
+        if (vcpu->arch.apic &&
+            !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
+                return 0;
-        if (vcpu->arch.apic) {
+        return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
-                dev = &vcpu->arch.apic->dev;
-                if (dev->in_range(dev, addr, len, is_write))
-                        return dev;
-        }
-        return NULL;
 }
+static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
-static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
-                                                gpa_t addr, int len,
-                                                int is_write)
 {
-        struct kvm_io_device *dev;
+        if (vcpu->arch.apic &&
+            !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
+                return 0;
-        dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
+        return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
-        if (dev == NULL)
-                dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
-                                          is_write);
-        return dev;
 }
 static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
@@ -2172,11 +2526,12 @@ static int emulator_read_emulated(unsigned long addr,
                                  unsigned int bytes,
                                  struct kvm_vcpu *vcpu)
 {
-        struct kvm_io_device *mmio_dev;
        gpa_t                 gpa;
        if (vcpu->mmio_read_completed) {
                memcpy(val, vcpu->mmio_data, bytes);
+                trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
+                               vcpu->mmio_phys_addr, *(u64 *)val);
                vcpu->mmio_read_completed = 0;
                return X86EMUL_CONTINUE;
        }
@@ -2197,14 +2552,12 @@ mmio:
        /*
         * Is this MMIO handled locally?
         */
-        mutex_lock(&vcpu->kvm->lock);
+        if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
-        mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
+                trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
-        if (mmio_dev) {
-                kvm_iodevice_read(mmio_dev, gpa, bytes, val);
-                mutex_unlock(&vcpu->kvm->lock);
                return X86EMUL_CONTINUE;
        }
-        mutex_unlock(&vcpu->kvm->lock);
+        trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
        vcpu->mmio_needed = 1;
        vcpu->mmio_phys_addr = gpa;
@@ -2231,7 +2584,6 @@ static int emulator_write_emulated_onepage(unsigned long addr,
                                           unsigned int bytes,
                                           struct kvm_vcpu *vcpu)
 {
-        struct kvm_io_device *mmio_dev;
        gpa_t                 gpa;
        gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
@@ -2249,17 +2601,12 @@ static int emulator_write_emulated_onepage(unsigned long addr,
                return X86EMUL_CONTINUE;
 mmio:
+        trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
        /*
         * Is this MMIO handled locally?
         */
-        mutex_lock(&vcpu->kvm->lock);
+        if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
-        mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
-        if (mmio_dev) {
-                kvm_iodevice_write(mmio_dev, gpa, bytes, val);
-                mutex_unlock(&vcpu->kvm->lock);
                return X86EMUL_CONTINUE;
-        }
-        mutex_unlock(&vcpu->kvm->lock);
        vcpu->mmio_needed = 1;
        vcpu->mmio_phys_addr = gpa;
@@ -2297,12 +2644,7 @@ static int emulator_cmpxchg_emulated(unsigned long addr,
                                     unsigned int bytes,
                                     struct kvm_vcpu *vcpu)
 {
-        static int reported;
+        printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
-        if (!reported) {
-                reported = 1;
-                printk(KERN_WARNING "kvm: emulating exchange as write\n");
-        }
 #ifndef CONFIG_X86_64
        /* guests cmpxchg8b have to be emulated atomically */
        if (bytes == 8) {
@@ -2348,7 +2690,6 @@ int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
 int emulate_clts(struct kvm_vcpu *vcpu)
 {
-        KVMTRACE_0D(CLTS, vcpu, handler);
        kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
        return X86EMUL_CONTINUE;
 }
@@ -2425,7 +2766,7 @@ int emulate_instruction(struct kvm_vcpu *vcpu,
        kvm_clear_exception_queue(vcpu);
        vcpu->arch.mmio_fault_cr2 = cr2;
        /*
-         * TODO: fix x86_emulate.c to use guest_read/write_register
+         * TODO: fix emulate.c to use guest_read/write_register
         * instead of direct ->regs accesses, can save hundred cycles
         * on Intel for instructions that don't read/change RSP, for
         * for example.
@@ -2449,14 +2790,33 @@ int emulate_instruction(struct kvm_vcpu *vcpu,
                r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
-                /* Reject the instructions other than VMCALL/VMMCALL when
+                /* Only allow emulation of specific instructions on #UD
-                 * try to emulate invalid opcode */
+                 * (namely VMMCALL, sysenter, sysexit, syscall)*/
                c = &vcpu->arch.emulate_ctxt.decode;
-                if ((emulation_type & EMULTYPE_TRAP_UD) &&
+                if (emulation_type & EMULTYPE_TRAP_UD) {
-                    (!(c->twobyte && c->b == 0x01 &&
+                        if (!c->twobyte)
-                      (c->modrm_reg == 0 || c->modrm_reg == 3) &&
+                                return EMULATE_FAIL;
-                       c->modrm_mod == 3 && c->modrm_rm == 1)))
+                        switch (c->b) {
-                        return EMULATE_FAIL;
+                        case 0x01: /* VMMCALL */
+                                if (c->modrm_mod != 3 || c->modrm_rm != 1)
+                                        return EMULATE_FAIL;
+                                break;
+                        case 0x34: /* sysenter */
+                        case 0x35: /* sysexit */
+                                if (c->modrm_mod != 0 || c->modrm_rm != 0)
+                                        return EMULATE_FAIL;
+                                break;
+                        case 0x05: /* syscall */
+                                if (c->modrm_mod != 0 || c->modrm_rm != 0)
+                                        return EMULATE_FAIL;
+                                break;
+                        default:
+                                return EMULATE_FAIL;
+                        }
+                        if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
+                                return EMULATE_FAIL;
+                }
                ++vcpu->stat.insn_emulation;
                if (r)  {
@@ -2576,52 +2936,40 @@ int complete_pio(struct kvm_vcpu *vcpu)
        return 0;
 }
-static void kernel_pio(struct kvm_io_device *pio_dev,
+static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
-                       struct kvm_vcpu *vcpu,
-                       void *pd)
 {
        /* TODO: String I/O for in kernel device */
+        int r;
-        mutex_lock(&vcpu->kvm->lock);
        if (vcpu->arch.pio.in)
-                kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
+                r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
-                                  vcpu->arch.pio.size,
+                                    vcpu->arch.pio.size, pd);
-                                  pd);
        else
-                kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
+                r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
-                                   vcpu->arch.pio.size,
+                                     vcpu->arch.pio.size, pd);
-                                   pd);
+        return r;
-        mutex_unlock(&vcpu->kvm->lock);
 }
-static void pio_string_write(struct kvm_io_device *pio_dev,
+static int pio_string_write(struct kvm_vcpu *vcpu)
-                             struct kvm_vcpu *vcpu)
 {
        struct kvm_pio_request *io = &vcpu->arch.pio;
        void *pd = vcpu->arch.pio_data;
-        int i;
+        int i, r = 0;
-        mutex_lock(&vcpu->kvm->lock);
        for (i = 0; i < io->cur_count; i++) {
-                kvm_iodevice_write(pio_dev, io->port,
+                if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
-                                   io->size,
+                                     io->port, io->size, pd)) {
-                                   pd);
+                        r = -EOPNOTSUPP;
+                        break;
+                }
                pd += io->size;
        }
-        mutex_unlock(&vcpu->kvm->lock);
+        return r;
-}
-static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
-                                               gpa_t addr, int len,
-                                               int is_write)
-{
-        return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
 }
 int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
                  int size, unsigned port)
 {
-        struct kvm_io_device *pio_dev;
        unsigned long val;
        vcpu->run->exit_reason = KVM_EXIT_IO;
@@ -2635,19 +2983,13 @@ int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
        vcpu->arch.pio.down = 0;
        vcpu->arch.pio.rep = 0;
-        if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
+        trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
-                KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
+                      size, 1);
-                            handler);
-        else
-                KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
-                            handler);
        val = kvm_register_read(vcpu, VCPU_REGS_RAX);
        memcpy(vcpu->arch.pio_data, &val, 4);
-        pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
+        if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
-        if (pio_dev) {
-                kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
                complete_pio(vcpu);
                return 1;
        }
@@ -2661,7 +3003,6 @@ int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
 {
        unsigned now, in_page;
        int ret = 0;
-        struct kvm_io_device *pio_dev;
        vcpu->run->exit_reason = KVM_EXIT_IO;
        vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
@@ -2674,12 +3015,8 @@ int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
        vcpu->arch.pio.down = down;
        vcpu->arch.pio.rep = rep;
-        if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
+        trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
-                KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
+                      size, count);
-                            handler);
-        else
-                KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
-                            handler);
        if (!count) {
                kvm_x86_ops->skip_emulated_instruction(vcpu);
@@ -2709,9 +3046,6 @@ int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
        vcpu->arch.pio.guest_gva = address;
-        pio_dev = vcpu_find_pio_dev(vcpu, port,
-                                    vcpu->arch.pio.cur_count,
-                                    !vcpu->arch.pio.in);
        if (!vcpu->arch.pio.in) {
                /* string PIO write */
                ret = pio_copy_data(vcpu);
@@ -2719,16 +3053,13 @@ int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
                        kvm_inject_gp(vcpu, 0);
                        return 1;
                }
-                if (ret == 0 && pio_dev) {
+                if (ret == 0 && !pio_string_write(vcpu)) {
-                        pio_string_write(pio_dev, vcpu);
                        complete_pio(vcpu);
                        if (vcpu->arch.pio.count == 0)
                                ret = 1;
                }
-        } else if (pio_dev)
+        }
-                pr_unimpl(vcpu, "no string pio read support yet, "
+        /* no string PIO read support yet */
-                       "port %x size %d count %ld\n",
-                        port, size, count);
        return ret;
 }
@@ -2761,10 +3092,7 @@ static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long va
        spin_lock(&kvm_lock);
        list_for_each_entry(kvm, &vm_list, vm_list) {
-                for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+                kvm_for_each_vcpu(i, vcpu, kvm) {
-                        vcpu = kvm->vcpus[i];
-                        if (!vcpu)
-                                continue;
                        if (vcpu->cpu != freq->cpu)
                                continue;
                        if (!kvm_request_guest_time_update(vcpu))
@@ -2857,7 +3185,6 @@ void kvm_arch_exit(void)
 int kvm_emulate_halt(struct kvm_vcpu *vcpu)
 {
        ++vcpu->stat.halt_exits;
-        KVMTRACE_0D(HLT, vcpu, handler);
        if (irqchip_in_kernel(vcpu->kvm)) {
                vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
                return 1;
@@ -2888,7 +3215,7 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
        a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
        a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
-        KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
+        trace_kvm_hypercall(nr, a0, a1, a2, a3);
        if (!is_long_mode(vcpu)) {
                nr &= 0xFFFFFFFF;
@@ -2898,6 +3225,11 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
                a3 &= 0xFFFFFFFF;
        }
+        if (kvm_x86_ops->get_cpl(vcpu) != 0) {
+                ret = -KVM_EPERM;
+                goto out;
+        }
        switch (nr) {
        case KVM_HC_VAPIC_POLL_IRQ:
                ret = 0;
@@ -2909,6 +3241,7 @@ int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
                ret = -KVM_ENOSYS;
                break;
        }
+out:
        kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
        ++vcpu->stat.hypercalls;
        return r;
@@ -2988,8 +3321,6 @@ unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
                vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
                return 0;
        }
-        KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
-                    (u32)((u64)value >> 32), handler);
        return value;
 }
@@ -2997,9 +3328,6 @@ unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
 void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
                     unsigned long *rflags)
 {
-        KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
-                    (u32)((u64)val >> 32), handler);
        switch (cr) {
        case 0:
                kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
@@ -3109,11 +3437,11 @@ void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
                kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
        }
        kvm_x86_ops->skip_emulated_instruction(vcpu);
-        KVMTRACE_5D(CPUID, vcpu, function,
+        trace_kvm_cpuid(function,
-                    (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
+                        kvm_register_read(vcpu, VCPU_REGS_RAX),
-                    (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
+                        kvm_register_read(vcpu, VCPU_REGS_RBX),
-                    (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
+                        kvm_register_read(vcpu, VCPU_REGS_RCX),
-                    (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
+                        kvm_register_read(vcpu, VCPU_REGS_RDX));
 }
 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
@@ -3179,6 +3507,9 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu)
        if (!kvm_x86_ops->update_cr8_intercept)
                return;
+        if (!vcpu->arch.apic)
+                return;
        if (!vcpu->arch.apic->vapic_addr)
                max_irr = kvm_lapic_find_highest_irr(vcpu);
        else
@@ -3192,12 +3523,16 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu)
        kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
 }
-static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
+static void inject_pending_event(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
 {
-        if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
-                kvm_x86_ops->set_interrupt_shadow(vcpu, 0);
        /* try to reinject previous events if any */
+        if (vcpu->arch.exception.pending) {
+                kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
+                                          vcpu->arch.exception.has_error_code,
+                                          vcpu->arch.exception.error_code);
+                return;
+        }
        if (vcpu->arch.nmi_injected) {
                kvm_x86_ops->set_nmi(vcpu);
                return;
@@ -3271,16 +3606,14 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        smp_mb__after_clear_bit();
        if (vcpu->requests || need_resched() || signal_pending(current)) {
+                set_bit(KVM_REQ_KICK, &vcpu->requests);
                local_irq_enable();
                preempt_enable();
                r = 1;
                goto out;
        }
-        if (vcpu->arch.exception.pending)
+        inject_pending_event(vcpu, kvm_run);
-                __queue_exception(vcpu);
-        else
-                inject_pending_irq(vcpu, kvm_run);
        /* enable NMI/IRQ window open exits if needed */
        if (vcpu->arch.nmi_pending)
@@ -3297,14 +3630,7 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
        kvm_guest_enter();
-        get_debugreg(vcpu->arch.host_dr6, 6);
-        get_debugreg(vcpu->arch.host_dr7, 7);
        if (unlikely(vcpu->arch.switch_db_regs)) {
-                get_debugreg(vcpu->arch.host_db[0], 0);
-                get_debugreg(vcpu->arch.host_db[1], 1);
-                get_debugreg(vcpu->arch.host_db[2], 2);
-                get_debugreg(vcpu->arch.host_db[3], 3);
                set_debugreg(0, 7);
                set_debugreg(vcpu->arch.eff_db[0], 0);
                set_debugreg(vcpu->arch.eff_db[1], 1);
@@ -3312,18 +3638,17 @@ static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
                set_debugreg(vcpu->arch.eff_db[3], 3);
        }
-        KVMTRACE_0D(VMENTRY, vcpu, entryexit);
+        trace_kvm_entry(vcpu->vcpu_id);
        kvm_x86_ops->run(vcpu, kvm_run);
-        if (unlikely(vcpu->arch.switch_db_regs)) {
+        if (unlikely(vcpu->arch.switch_db_regs || test_thread_flag(TIF_DEBUG))) {
-                set_debugreg(0, 7);
+                set_debugreg(current->thread.debugreg[0], 0);
-                set_debugreg(vcpu->arch.host_db[0], 0);
+                set_debugreg(current->thread.debugreg[1], 1);
-                set_debugreg(vcpu->arch.host_db[1], 1);
+                set_debugreg(current->thread.debugreg[2], 2);
-                set_debugreg(vcpu->arch.host_db[2], 2);
+                set_debugreg(current->thread.debugreg[3], 3);
-                set_debugreg(vcpu->arch.host_db[3], 3);
+                set_debugreg(current->thread.debugreg6, 6);
+                set_debugreg(current->thread.debugreg7, 7);
        }
-        set_debugreg(vcpu->arch.host_dr6, 6);
-        set_debugreg(vcpu->arch.host_dr7, 7);
        set_bit(KVM_REQ_KICK, &vcpu->requests);
        local_irq_enable();
@@ -3653,11 +3978,8 @@ static void kvm_set_segment(struct kvm_vcpu *vcpu,
 static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
                                   struct kvm_segment *kvm_desct)
 {
-        kvm_desct->base = seg_desc->base0;
+        kvm_desct->base = get_desc_base(seg_desc);
-        kvm_desct->base |= seg_desc->base1 << 16;
+        kvm_desct->limit = get_desc_limit(seg_desc);
-        kvm_desct->base |= seg_desc->base2 << 24;
-        kvm_desct->limit = seg_desc->limit0;
-        kvm_desct->limit |= seg_desc->limit << 16;
        if (seg_desc->g) {
                kvm_desct->limit <<= 12;
                kvm_desct->limit |= 0xfff;
@@ -3701,7 +4023,6 @@ static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
 static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
                                         struct desc_struct *seg_desc)
 {
-        gpa_t gpa;
        struct descriptor_table dtable;
        u16 index = selector >> 3;
@@ -3711,16 +4032,13 @@ static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
                kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
                return 1;
        }
-        gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
+        return kvm_read_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
-        gpa += index * 8;
-        return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
 }
 /* allowed just for 8 bytes segments */
 static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
                                         struct desc_struct *seg_desc)
 {
-        gpa_t gpa;
        struct descriptor_table dtable;
        u16 index = selector >> 3;
@@ -3728,19 +4046,13 @@ static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
        if (dtable.limit < index * 8 + 7)
                return 1;
-        gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
+        return kvm_write_guest_virt(dtable.base + index*8, seg_desc, sizeof(*seg_desc), vcpu);
-        gpa += index * 8;
-        return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
 }
 static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
                             struct desc_struct *seg_desc)
 {
-        u32 base_addr;
+        u32 base_addr = get_desc_base(seg_desc);
-        base_addr = seg_desc->base0;
-        base_addr |= (seg_desc->base1 << 16);
-        base_addr |= (seg_desc->base2 << 24);
        return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
 }
@@ -3785,12 +4097,19 @@ static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int se
        return 0;
 }
+static int is_vm86_segment(struct kvm_vcpu *vcpu, int seg)
+{
+        return (seg != VCPU_SREG_LDTR) &&
+                (seg != VCPU_SREG_TR) &&
+                (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_VM);
+}
 int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
                                int type_bits, int seg)
 {
        struct kvm_segment kvm_seg;
-        if (!(vcpu->arch.cr0 & X86_CR0_PE))
+        if (is_vm86_segment(vcpu, seg) || !(vcpu->arch.cr0 & X86_CR0_PE))
                return kvm_load_realmode_segment(vcpu, selector, seg);
        if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
                return 1;
@@ -4029,7 +4348,7 @@ int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
                }
        }
-        if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
+        if (!nseg_desc.p || get_desc_limit(&nseg_desc) < 0x67) {
                kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
                return 1;
        }
@@ -4099,13 +4418,7 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
        vcpu->arch.cr2 = sregs->cr2;
        mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
+        vcpu->arch.cr3 = sregs->cr3;
-        down_read(&vcpu->kvm->slots_lock);
-        if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
-                vcpu->arch.cr3 = sregs->cr3;
-        else
-                set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
-        up_read(&vcpu->kvm->slots_lock);
        kvm_set_cr8(vcpu, sregs->cr8);
@@ -4147,8 +4460,10 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
        kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
        kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
+        update_cr8_intercept(vcpu);
        /* Older userspace won't unhalt the vcpu on reset. */
-        if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
+        if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
            sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
            !(vcpu->arch.cr0 & X86_CR0_PE))
                vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
@@ -4419,7 +4734,7 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
        kvm = vcpu->kvm;
        vcpu->arch.mmu.root_hpa = INVALID_PAGE;
-        if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
+        if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
                vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
        else
                vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
@@ -4441,6 +4756,14 @@ int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
                        goto fail_mmu_destroy;
        }
+        vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
+                                       GFP_KERNEL);
+        if (!vcpu->arch.mce_banks) {
+                r = -ENOMEM;
+                goto fail_mmu_destroy;
+        }
+        vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
        return 0;
 fail_mmu_destroy:
@@ -4488,20 +4811,22 @@ static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
 static void kvm_free_vcpus(struct kvm *kvm)
 {
        unsigned int i;
+        struct kvm_vcpu *vcpu;
        /*
         * Unpin any mmu pages first.
         */
-        for (i = 0; i < KVM_MAX_VCPUS; ++i)
+        kvm_for_each_vcpu(i, vcpu, kvm)
-                if (kvm->vcpus[i])
+                kvm_unload_vcpu_mmu(vcpu);
-                        kvm_unload_vcpu_mmu(kvm->vcpus[i]);
+        kvm_for_each_vcpu(i, vcpu, kvm)
-        for (i = 0; i < KVM_MAX_VCPUS; ++i) {
+                kvm_arch_vcpu_free(vcpu);
-                if (kvm->vcpus[i]) {
-                        kvm_arch_vcpu_free(kvm->vcpus[i]);
+        mutex_lock(&kvm->lock);
-                        kvm->vcpus[i] = NULL;
+        for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
-                }
+                kvm->vcpus[i] = NULL;
-        }
+        atomic_set(&kvm->online_vcpus, 0);
+        mutex_unlock(&kvm->lock);
 }
 void kvm_arch_sync_events(struct kvm *kvm)
@@ -4578,7 +4903,6 @@ int kvm_arch_set_memory_region(struct kvm *kvm,
        kvm_mmu_slot_remove_write_access(kvm, mem->slot);
        spin_unlock(&kvm->mmu_lock);
-        kvm_flush_remote_tlbs(kvm);
        return 0;
 }
@@ -4592,8 +4916,10 @@ void kvm_arch_flush_shadow(struct kvm *kvm)
 int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
 {
        return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
-               || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
+                || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
-               || vcpu->arch.nmi_pending;
+                || vcpu->arch.nmi_pending ||
+                (kvm_arch_interrupt_allowed(vcpu) &&
+                 kvm_cpu_has_interrupt(vcpu));
 }
 void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
@@ -4617,3 +4943,9 @@ int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
 {
        return kvm_x86_ops->interrupt_allowed(vcpu);
 }
+EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
+EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
+EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
+EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
+EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
diff --git a/arch/x86/kvm/x86.h b/arch/x86/kvm/x86.h
index 4c8e10af78e8..5eadea585d2a 100644
--- a/arch/x86/kvm/x86.h
+++ b/arch/x86/kvm/x86.h
@@ -31,4 +31,8 @@ static inline bool kvm_exception_is_soft(unsigned int nr)
 {
        return (nr == BP_VECTOR) || (nr == OF_VECTOR);
 }
+struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
+                                             u32 function, u32 index);
 #endif
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 07c31899c9c2..9e609206fac9 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -9,6 +9,8 @@ lib-y += thunk_$(BITS).o
 lib-y += usercopy_$(BITS).o getuser.o putuser.o
 lib-y += memcpy_$(BITS).o
+obj-y += msr-reg.o msr-reg-export.o
 ifeq ($(CONFIG_X86_32),y)
        obj-y += atomic64_32.o
        lib-y += checksum_32.o
diff --git a/arch/x86/lib/msr-reg-export.c b/arch/x86/lib/msr-reg-export.c
new file mode 100644
index 000000000000..a311cc59b65d
--- /dev/null
+++ b/arch/x86/lib/msr-reg-export.c
@@ -0,0 +1,5 @@
+#include <linux/module.h>
+#include <asm/msr.h>
+EXPORT_SYMBOL(native_rdmsr_safe_regs);
+EXPORT_SYMBOL(native_wrmsr_safe_regs);
diff --git a/arch/x86/lib/msr-reg.S b/arch/x86/lib/msr-reg.S
new file mode 100644
index 000000000000..69fa10623f21
--- /dev/null
+++ b/arch/x86/lib/msr-reg.S
@@ -0,0 +1,102 @@
+#include <linux/linkage.h>
+#include <linux/errno.h>
+#include <asm/dwarf2.h>
+#include <asm/asm.h>
+#include <asm/msr.h>
+#ifdef CONFIG_X86_64
+/*
+ * int native_{rdmsr,wrmsr}_safe_regs(u32 gprs[8]);
+ *
+ * reg layout: u32 gprs[eax, ecx, edx, ebx, esp, ebp, esi, edi]
+ *
+ */
+.macro op_safe_regs op
+ENTRY(native_\op\()_safe_regs)
+        CFI_STARTPROC
+        pushq_cfi %rbx
+        pushq_cfi %rbp
+        movq    %rdi, %r10      /* Save pointer */
+        xorl    %r11d, %r11d    /* Return value */
+        movl    (%rdi), %eax
+        movl    4(%rdi), %ecx
+        movl    8(%rdi), %edx
+        movl    12(%rdi), %ebx
+        movl    20(%rdi), %ebp
+        movl    24(%rdi), %esi
+        movl    28(%rdi), %edi
+        CFI_REMEMBER_STATE
+1:      \op
+2:      movl    %eax, (%r10)
+        movl    %r11d, %eax     /* Return value */
+        movl    %ecx, 4(%r10)
+        movl    %edx, 8(%r10)
+        movl    %ebx, 12(%r10)
+        movl    %ebp, 20(%r10)
+        movl    %esi, 24(%r10)
+        movl    %edi, 28(%r10)
+        popq_cfi %rbp
+        popq_cfi %rbx
+        ret
+3:
+        CFI_RESTORE_STATE
+        movl    $-EIO, %r11d
+        jmp     2b
+        _ASM_EXTABLE(1b, 3b)
+        CFI_ENDPROC
+ENDPROC(native_\op\()_safe_regs)
+.endm
+#else /* X86_32 */
+.macro op_safe_regs op
+ENTRY(native_\op\()_safe_regs)
+        CFI_STARTPROC
+        pushl_cfi %ebx
+        pushl_cfi %ebp
+        pushl_cfi %esi
+        pushl_cfi %edi
+        pushl_cfi $0              /* Return value */
+        pushl_cfi %eax
+        movl    4(%eax), %ecx
+        movl    8(%eax), %edx
+        movl    12(%eax), %ebx
+        movl    20(%eax), %ebp
+        movl    24(%eax), %esi
+        movl    28(%eax), %edi
+        movl    (%eax), %eax
+        CFI_REMEMBER_STATE
+1:      \op
+2:      pushl_cfi %eax
+        movl    4(%esp), %eax
+        popl_cfi (%eax)
+        addl    $4, %esp
+        CFI_ADJUST_CFA_OFFSET -4
+        movl    %ecx, 4(%eax)
+        movl    %edx, 8(%eax)
+        movl    %ebx, 12(%eax)
+        movl    %ebp, 20(%eax)
+        movl    %esi, 24(%eax)
+        movl    %edi, 28(%eax)
+        popl_cfi %eax
+        popl_cfi %edi
+        popl_cfi %esi
+        popl_cfi %ebp
+        popl_cfi %ebx
+        ret
+3:
+        CFI_RESTORE_STATE
+        movl    $-EIO, 4(%esp)
+        jmp     2b
+        _ASM_EXTABLE(1b, 3b)
+        CFI_ENDPROC
+ENDPROC(native_\op\()_safe_regs)
+.endm
+#endif
+op_safe_regs rdmsr
+op_safe_regs wrmsr
diff --git a/arch/x86/lib/msr.c b/arch/x86/lib/msr.c
index caa24aca8115..33a1e3ca22d8 100644
--- a/arch/x86/lib/msr.c
+++ b/arch/x86/lib/msr.c
@@ -175,3 +175,52 @@ int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
        return err ? err : rv.err;
 }
 EXPORT_SYMBOL(wrmsr_safe_on_cpu);
+/*
+ * These variants are significantly slower, but allows control over
+ * the entire 32-bit GPR set.
+ */
+struct msr_regs_info {
+        u32 *regs;
+        int err;
+};
+static void __rdmsr_safe_regs_on_cpu(void *info)
+{
+        struct msr_regs_info *rv = info;
+        rv->err = rdmsr_safe_regs(rv->regs);
+}
+static void __wrmsr_safe_regs_on_cpu(void *info)
+{
+        struct msr_regs_info *rv = info;
+        rv->err = wrmsr_safe_regs(rv->regs);
+}
+int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 *regs)
+{
+        int err;
+        struct msr_regs_info rv;
+        rv.regs   = regs;
+        rv.err    = -EIO;
+        err = smp_call_function_single(cpu, __rdmsr_safe_regs_on_cpu, &rv, 1);
+        return err ? err : rv.err;
+}
+EXPORT_SYMBOL(rdmsr_safe_regs_on_cpu);
+int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 *regs)
+{
+        int err;
+        struct msr_regs_info rv;
+        rv.regs = regs;
+        rv.err  = -EIO;
+        err = smp_call_function_single(cpu, __wrmsr_safe_regs_on_cpu, &rv, 1);
+        return err ? err : rv.err;
+}
+EXPORT_SYMBOL(wrmsr_safe_regs_on_cpu);
diff --git a/arch/x86/mm/Makefile b/arch/x86/mm/Makefile
index eefdeee8a871..9b5a9f59a478 100644
--- a/arch/x86/mm/Makefile
+++ b/arch/x86/mm/Makefile
@@ -1,5 +1,9 @@
 obj-y   :=  init.o init_$(BITS).o fault.o ioremap.o extable.o pageattr.o mmap.o \
-            pat.o pgtable.o gup.o
+            pat.o pgtable.o physaddr.o gup.o
+# Make sure __phys_addr has no stackprotector
+nostackp := $(call cc-option, -fno-stack-protector)
+CFLAGS_physaddr.o               := $(nostackp)
 obj-$(CONFIG_SMP)               += tlb.o
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index bfae139182ff..775a020990a5 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -285,26 +285,25 @@ check_v8086_mode(struct pt_regs *regs, unsigned long address,
                tsk->thread.screen_bitmap |= 1 << bit;
 }
-static void dump_pagetable(unsigned long address)
+static bool low_pfn(unsigned long pfn)
 {
-        __typeof__(pte_val(__pte(0))) page;
+        return pfn < max_low_pfn;
+}
-        page = read_cr3();
+static void dump_pagetable(unsigned long address)
-        page = ((__typeof__(page) *) __va(page))[address >> PGDIR_SHIFT];
+{
+        pgd_t *base = __va(read_cr3());
+        pgd_t *pgd = &base[pgd_index(address)];
+        pmd_t *pmd;
+        pte_t *pte;
 #ifdef CONFIG_X86_PAE
-        printk("*pdpt = %016Lx ", page);
+        printk("*pdpt = %016Lx ", pgd_val(*pgd));
-        if ((page >> PAGE_SHIFT) < max_low_pfn
+        if (!low_pfn(pgd_val(*pgd) >> PAGE_SHIFT) || !pgd_present(*pgd))
-            && page & _PAGE_PRESENT) {
+                goto out;
-                page &= PAGE_MASK;
-                page = ((__typeof__(page) *) __va(page))[(address >> PMD_SHIFT)
-                                                        & (PTRS_PER_PMD - 1)];
-                printk(KERN_CONT "*pde = %016Lx ", page);
-                page &= ~_PAGE_NX;
-        }
-#else
-        printk("*pde = %08lx ", page);
 #endif
+        pmd = pmd_offset(pud_offset(pgd, address), address);
+        printk(KERN_CONT "*pde = %0*Lx ", sizeof(*pmd) * 2, (u64)pmd_val(*pmd));
        /*
         * We must not directly access the pte in the highpte
@@ -312,16 +311,12 @@ static void dump_pagetable(unsigned long address)
         * And let's rather not kmap-atomic the pte, just in case
         * it's allocated already:
         */
-        if ((page >> PAGE_SHIFT) < max_low_pfn
+        if (!low_pfn(pmd_pfn(*pmd)) || !pmd_present(*pmd) || pmd_large(*pmd))
-            && (page & _PAGE_PRESENT)
+                goto out;
-            && !(page & _PAGE_PSE)) {
-                page &= PAGE_MASK;
-                page = ((__typeof__(page) *) __va(page))[(address >> PAGE_SHIFT)
-                                                        & (PTRS_PER_PTE - 1)];
-                printk("*pte = %0*Lx ", sizeof(page)*2, (u64)page);
-        }
+        pte = pte_offset_kernel(pmd, address);
+        printk("*pte = %0*Lx ", sizeof(*pte) * 2, (u64)pte_val(*pte));
+out:
        printk("\n");
 }
@@ -450,16 +445,12 @@ static int bad_address(void *p)
 static void dump_pagetable(unsigned long address)
 {
-        pgd_t *pgd;
+        pgd_t *base = __va(read_cr3() & PHYSICAL_PAGE_MASK);
+        pgd_t *pgd = base + pgd_index(address);
        pud_t *pud;
        pmd_t *pmd;
        pte_t *pte;
-        pgd = (pgd_t *)read_cr3();
-        pgd = __va((unsigned long)pgd & PHYSICAL_PAGE_MASK);
-        pgd += pgd_index(address);
        if (bad_address(pgd))
                goto bad;
diff --git a/arch/x86/mm/highmem_32.c b/arch/x86/mm/highmem_32.c
index 2112ed55e7ea..63a6ba66cbe0 100644
--- a/arch/x86/mm/highmem_32.c
+++ b/arch/x86/mm/highmem_32.c
@@ -24,7 +24,7 @@ void kunmap(struct page *page)
 * no global lock is needed and because the kmap code must perform a global TLB
 * invalidation when the kmap pool wraps.
 *
- * However when holding an atomic kmap is is not legal to sleep, so atomic
+ * However when holding an atomic kmap it is not legal to sleep, so atomic
 * kmaps are appropriate for short, tight code paths only.
 */
 void *kmap_atomic_prot(struct page *page, enum km_type type, pgprot_t prot)
@@ -104,6 +104,7 @@ EXPORT_SYMBOL(kunmap);
 EXPORT_SYMBOL(kmap_atomic);
 EXPORT_SYMBOL(kunmap_atomic);
 EXPORT_SYMBOL(kmap_atomic_prot);
+EXPORT_SYMBOL(kmap_atomic_to_page);
 void __init set_highmem_pages_init(void)
 {
diff --git a/arch/x86/mm/ioremap.c b/arch/x86/mm/ioremap.c
index 8a450930834f..04e1ad60c63a 100644
--- a/arch/x86/mm/ioremap.c
+++ b/arch/x86/mm/ioremap.c
@@ -22,77 +22,7 @@
 #include <asm/pgalloc.h>
 #include <asm/pat.h>
-static inline int phys_addr_valid(resource_size_t addr)
+#include "physaddr.h"
-{
-#ifdef CONFIG_PHYS_ADDR_T_64BIT
-        return !(addr >> boot_cpu_data.x86_phys_bits);
-#else
-        return 1;
-#endif
-}
-#ifdef CONFIG_X86_64
-unsigned long __phys_addr(unsigned long x)
-{
-        if (x >= __START_KERNEL_map) {
-                x -= __START_KERNEL_map;
-                VIRTUAL_BUG_ON(x >= KERNEL_IMAGE_SIZE);
-                x += phys_base;
-        } else {
-                VIRTUAL_BUG_ON(x < PAGE_OFFSET);
-                x -= PAGE_OFFSET;
-                VIRTUAL_BUG_ON(!phys_addr_valid(x));
-        }
-        return x;
-}
-EXPORT_SYMBOL(__phys_addr);
-bool __virt_addr_valid(unsigned long x)
-{
-        if (x >= __START_KERNEL_map) {
-                x -= __START_KERNEL_map;
-                if (x >= KERNEL_IMAGE_SIZE)
-                        return false;
-                x += phys_base;
-        } else {
-                if (x < PAGE_OFFSET)
-                        return false;
-                x -= PAGE_OFFSET;
-                if (!phys_addr_valid(x))
-                        return false;
-        }
-        return pfn_valid(x >> PAGE_SHIFT);
-}
-EXPORT_SYMBOL(__virt_addr_valid);
-#else
-#ifdef CONFIG_DEBUG_VIRTUAL
-unsigned long __phys_addr(unsigned long x)
-{
-        /* VMALLOC_* aren't constants  */
-        VIRTUAL_BUG_ON(x < PAGE_OFFSET);
-        VIRTUAL_BUG_ON(__vmalloc_start_set && is_vmalloc_addr((void *) x));
-        return x - PAGE_OFFSET;
-}
-EXPORT_SYMBOL(__phys_addr);
-#endif
-bool __virt_addr_valid(unsigned long x)
-{
-        if (x < PAGE_OFFSET)
-                return false;
-        if (__vmalloc_start_set && is_vmalloc_addr((void *) x))
-                return false;
-        if (x >= FIXADDR_START)
-                return false;
-        return pfn_valid((x - PAGE_OFFSET) >> PAGE_SHIFT);
-}
-EXPORT_SYMBOL(__virt_addr_valid);
-#endif
 int page_is_ram(unsigned long pagenr)
 {
diff --git a/arch/x86/mm/kmemcheck/kmemcheck.c b/arch/x86/mm/kmemcheck/kmemcheck.c
index 2c55ed098654..528bf954eb74 100644
--- a/arch/x86/mm/kmemcheck/kmemcheck.c
+++ b/arch/x86/mm/kmemcheck/kmemcheck.c
@@ -331,6 +331,20 @@ static void kmemcheck_read_strict(struct pt_regs *regs,
        kmemcheck_shadow_set(shadow, size);
 }
+bool kmemcheck_is_obj_initialized(unsigned long addr, size_t size)
+{
+        enum kmemcheck_shadow status;
+        void *shadow;
+        shadow = kmemcheck_shadow_lookup(addr);
+        if (!shadow)
+                return true;
+        status = kmemcheck_shadow_test(shadow, size);
+        return status == KMEMCHECK_SHADOW_INITIALIZED;
+}
 /* Access may cross page boundary */
 static void kmemcheck_read(struct pt_regs *regs,
        unsigned long addr, unsigned int size)
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index 352aa9e927e2..b2f7d3e59b86 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -827,7 +827,7 @@ static int memtype_seq_show(struct seq_file *seq, void *v)
        return 0;
 }
-static struct seq_operations memtype_seq_ops = {
+static const struct seq_operations memtype_seq_ops = {
        .start = memtype_seq_start,
        .next  = memtype_seq_next,
        .stop  = memtype_seq_stop,
diff --git a/arch/x86/mm/physaddr.c b/arch/x86/mm/physaddr.c
new file mode 100644
index 000000000000..d2e2735327b4
--- /dev/null
+++ b/arch/x86/mm/physaddr.c
@@ -0,0 +1,70 @@
+#include <linux/mmdebug.h>
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <asm/page.h>
+#include "physaddr.h"
+#ifdef CONFIG_X86_64
+unsigned long __phys_addr(unsigned long x)
+{
+        if (x >= __START_KERNEL_map) {
+                x -= __START_KERNEL_map;
+                VIRTUAL_BUG_ON(x >= KERNEL_IMAGE_SIZE);
+                x += phys_base;
+        } else {
+                VIRTUAL_BUG_ON(x < PAGE_OFFSET);
+                x -= PAGE_OFFSET;
+                VIRTUAL_BUG_ON(!phys_addr_valid(x));
+        }
+        return x;
+}
+EXPORT_SYMBOL(__phys_addr);
+bool __virt_addr_valid(unsigned long x)
+{
+        if (x >= __START_KERNEL_map) {
+                x -= __START_KERNEL_map;
+                if (x >= KERNEL_IMAGE_SIZE)
+                        return false;
+                x += phys_base;
+        } else {
+                if (x < PAGE_OFFSET)
+                        return false;
+                x -= PAGE_OFFSET;
+                if (!phys_addr_valid(x))
+                        return false;
+        }
+        return pfn_valid(x >> PAGE_SHIFT);
+}
+EXPORT_SYMBOL(__virt_addr_valid);
+#else
+#ifdef CONFIG_DEBUG_VIRTUAL
+unsigned long __phys_addr(unsigned long x)
+{
+        /* VMALLOC_* aren't constants  */
+        VIRTUAL_BUG_ON(x < PAGE_OFFSET);
+        VIRTUAL_BUG_ON(__vmalloc_start_set && is_vmalloc_addr((void *) x));
+        return x - PAGE_OFFSET;
+}
+EXPORT_SYMBOL(__phys_addr);
+#endif
+bool __virt_addr_valid(unsigned long x)
+{
+        if (x < PAGE_OFFSET)
+                return false;
+        if (__vmalloc_start_set && is_vmalloc_addr((void *) x))
+                return false;
+        if (x >= FIXADDR_START)
+                return false;
+        return pfn_valid((x - PAGE_OFFSET) >> PAGE_SHIFT);
+}
+EXPORT_SYMBOL(__virt_addr_valid);
+#endif  /* CONFIG_X86_64 */
diff --git a/arch/x86/mm/physaddr.h b/arch/x86/mm/physaddr.h
new file mode 100644
index 000000000000..a3cd5a0c97b3
--- /dev/null
+++ b/arch/x86/mm/physaddr.h
@@ -0,0 +1,10 @@
+#include <asm/processor.h>
+static inline int phys_addr_valid(resource_size_t addr)
+{
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+        return !(addr >> boot_cpu_data.x86_phys_bits);
+#else
+        return 1;
+#endif
+}
diff --git a/arch/x86/mm/srat_32.c b/arch/x86/mm/srat_32.c
index 29a0e37114f8..6f8aa33031c7 100644
--- a/arch/x86/mm/srat_32.c
+++ b/arch/x86/mm/srat_32.c
@@ -215,7 +215,7 @@ int __init get_memcfg_from_srat(void)
                goto out_fail;
        if (num_memory_chunks == 0) {
-                printk(KERN_WARNING
+                printk(KERN_DEBUG
                         "could not find any ACPI SRAT memory areas.\n");
                goto out_fail;
        }
@@ -277,7 +277,7 @@ int __init get_memcfg_from_srat(void)
        }
        return 1;
 out_fail:
-        printk(KERN_ERR "failed to get NUMA memory information from SRAT"
+        printk(KERN_DEBUG "failed to get NUMA memory information from SRAT"
                        " table\n");
        return 0;
 }
diff --git a/arch/x86/oprofile/nmi_int.c b/arch/x86/oprofile/nmi_int.c
index 89b9a5cd63da..cb88b1a0bd5f 100644
--- a/arch/x86/oprofile/nmi_int.c
+++ b/arch/x86/oprofile/nmi_int.c
@@ -1,11 +1,14 @@
 /**
 * @file nmi_int.c
 *
- * @remark Copyright 2002-2008 OProfile authors
+ * @remark Copyright 2002-2009 OProfile authors
 * @remark Read the file COPYING
 *
 * @author John Levon <levon@movementarian.org>
 * @author Robert Richter <robert.richter@amd.com>
+ * @author Barry Kasindorf <barry.kasindorf@amd.com>
+ * @author Jason Yeh <jason.yeh@amd.com>
+ * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 */
 #include <linux/init.h>
@@ -24,13 +27,35 @@
 #include "op_counter.h"
 #include "op_x86_model.h"
-static struct op_x86_model_spec const *model;
+static struct op_x86_model_spec *model;
 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
 /* 0 == registered but off, 1 == registered and on */
 static int nmi_enabled = 0;
+struct op_counter_config counter_config[OP_MAX_COUNTER];
+/* common functions */
+u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
+                    struct op_counter_config *counter_config)
+{
+        u64 val = 0;
+        u16 event = (u16)counter_config->event;
+        val |= ARCH_PERFMON_EVENTSEL_INT;
+        val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
+        val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
+        val |= (counter_config->unit_mask & 0xFF) << 8;
+        event &= model->event_mask ? model->event_mask : 0xFF;
+        val |= event & 0xFF;
+        val |= (event & 0x0F00) << 24;
+        return val;
+}
 static int profile_exceptions_notify(struct notifier_block *self,
                                     unsigned long val, void *data)
 {
@@ -52,36 +77,214 @@ static int profile_exceptions_notify(struct notifier_block *self,
 static void nmi_cpu_save_registers(struct op_msrs *msrs)
 {
-        unsigned int const nr_ctrs = model->num_counters;
-        unsigned int const nr_ctrls = model->num_controls;
        struct op_msr *counters = msrs->counters;
        struct op_msr *controls = msrs->controls;
        unsigned int i;
-        for (i = 0; i < nr_ctrs; ++i) {
+        for (i = 0; i < model->num_counters; ++i) {
-                if (counters[i].addr) {
+                if (counters[i].addr)
-                        rdmsr(counters[i].addr,
+                        rdmsrl(counters[i].addr, counters[i].saved);
-                                counters[i].saved.low,
+        }
-                                counters[i].saved.high);
-                }
+        for (i = 0; i < model->num_controls; ++i) {
+                if (controls[i].addr)
+                        rdmsrl(controls[i].addr, controls[i].saved);
+        }
+}
+static void nmi_cpu_start(void *dummy)
+{
+        struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
+        model->start(msrs);
+}
+static int nmi_start(void)
+{
+        on_each_cpu(nmi_cpu_start, NULL, 1);
+        return 0;
+}
+static void nmi_cpu_stop(void *dummy)
+{
+        struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
+        model->stop(msrs);
+}
+static void nmi_stop(void)
+{
+        on_each_cpu(nmi_cpu_stop, NULL, 1);
+}
+#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+static DEFINE_PER_CPU(int, switch_index);
+static inline int has_mux(void)
+{
+        return !!model->switch_ctrl;
+}
+inline int op_x86_phys_to_virt(int phys)
+{
+        return __get_cpu_var(switch_index) + phys;
+}
+inline int op_x86_virt_to_phys(int virt)
+{
+        return virt % model->num_counters;
+}
+static void nmi_shutdown_mux(void)
+{
+        int i;
+        if (!has_mux())
+                return;
+        for_each_possible_cpu(i) {
+                kfree(per_cpu(cpu_msrs, i).multiplex);
+                per_cpu(cpu_msrs, i).multiplex = NULL;
+                per_cpu(switch_index, i) = 0;
        }
+}
+static int nmi_setup_mux(void)
+{
+        size_t multiplex_size =
+                sizeof(struct op_msr) * model->num_virt_counters;
+        int i;
+        if (!has_mux())
+                return 1;
+        for_each_possible_cpu(i) {
+                per_cpu(cpu_msrs, i).multiplex =
+                        kmalloc(multiplex_size, GFP_KERNEL);
+                if (!per_cpu(cpu_msrs, i).multiplex)
+                        return 0;
+        }
+        return 1;
+}
+static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
+{
+        int i;
+        struct op_msr *multiplex = msrs->multiplex;
+        if (!has_mux())
+                return;
-        for (i = 0; i < nr_ctrls; ++i) {
+        for (i = 0; i < model->num_virt_counters; ++i) {
-                if (controls[i].addr) {
+                if (counter_config[i].enabled) {
-                        rdmsr(controls[i].addr,
+                        multiplex[i].saved = -(u64)counter_config[i].count;
-                                controls[i].saved.low,
+                } else {
-                                controls[i].saved.high);
+                        multiplex[i].addr  = 0;
+                        multiplex[i].saved = 0;
                }
        }
+        per_cpu(switch_index, cpu) = 0;
+}
+static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
+{
+        struct op_msr *multiplex = msrs->multiplex;
+        int i;
+        for (i = 0; i < model->num_counters; ++i) {
+                int virt = op_x86_phys_to_virt(i);
+                if (multiplex[virt].addr)
+                        rdmsrl(multiplex[virt].addr, multiplex[virt].saved);
+        }
+}
+static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
+{
+        struct op_msr *multiplex = msrs->multiplex;
+        int i;
+        for (i = 0; i < model->num_counters; ++i) {
+                int virt = op_x86_phys_to_virt(i);
+                if (multiplex[virt].addr)
+                        wrmsrl(multiplex[virt].addr, multiplex[virt].saved);
+        }
 }
-static void nmi_save_registers(void *dummy)
+static void nmi_cpu_switch(void *dummy)
 {
        int cpu = smp_processor_id();
+        int si = per_cpu(switch_index, cpu);
        struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
-        nmi_cpu_save_registers(msrs);
+        nmi_cpu_stop(NULL);
+        nmi_cpu_save_mpx_registers(msrs);
+        /* move to next set */
+        si += model->num_counters;
+        if ((si > model->num_virt_counters) || (counter_config[si].count == 0))
+                per_cpu(switch_index, cpu) = 0;
+        else
+                per_cpu(switch_index, cpu) = si;
+        model->switch_ctrl(model, msrs);
+        nmi_cpu_restore_mpx_registers(msrs);
+        nmi_cpu_start(NULL);
+}
+/*
+ * Quick check to see if multiplexing is necessary.
+ * The check should be sufficient since counters are used
+ * in ordre.
+ */
+static int nmi_multiplex_on(void)
+{
+        return counter_config[model->num_counters].count ? 0 : -EINVAL;
+}
+static int nmi_switch_event(void)
+{
+        if (!has_mux())
+                return -ENOSYS;         /* not implemented */
+        if (nmi_multiplex_on() < 0)
+                return -EINVAL;         /* not necessary */
+        on_each_cpu(nmi_cpu_switch, NULL, 1);
+        return 0;
+}
+static inline void mux_init(struct oprofile_operations *ops)
+{
+        if (has_mux())
+                ops->switch_events = nmi_switch_event;
+}
+static void mux_clone(int cpu)
+{
+        if (!has_mux())
+                return;
+        memcpy(per_cpu(cpu_msrs, cpu).multiplex,
+               per_cpu(cpu_msrs, 0).multiplex,
+               sizeof(struct op_msr) * model->num_virt_counters);
 }
+#else
+inline int op_x86_phys_to_virt(int phys) { return phys; }
+inline int op_x86_virt_to_phys(int virt) { return virt; }
+static inline void nmi_shutdown_mux(void) { }
+static inline int nmi_setup_mux(void) { return 1; }
+static inline void
+nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
+static inline void mux_init(struct oprofile_operations *ops) { }
+static void mux_clone(int cpu) { }
+#endif
 static void free_msrs(void)
 {
        int i;
@@ -95,38 +298,32 @@ static void free_msrs(void)
 static int allocate_msrs(void)
 {
-        int success = 1;
        size_t controls_size = sizeof(struct op_msr) * model->num_controls;
        size_t counters_size = sizeof(struct op_msr) * model->num_counters;
        int i;
        for_each_possible_cpu(i) {
                per_cpu(cpu_msrs, i).counters = kmalloc(counters_size,
-                                                                GFP_KERNEL);
+                                                        GFP_KERNEL);
-                if (!per_cpu(cpu_msrs, i).counters) {
+                if (!per_cpu(cpu_msrs, i).counters)
-                        success = 0;
+                        return 0;
-                        break;
-                }
                per_cpu(cpu_msrs, i).controls = kmalloc(controls_size,
-                                                                GFP_KERNEL);
+                                                        GFP_KERNEL);
-                if (!per_cpu(cpu_msrs, i).controls) {
+                if (!per_cpu(cpu_msrs, i).controls)
-                        success = 0;
+                        return 0;
-                        break;
-                }
        }
-        if (!success)
+        return 1;
-                free_msrs();
-        return success;
 }
 static void nmi_cpu_setup(void *dummy)
 {
        int cpu = smp_processor_id();
        struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
+        nmi_cpu_save_registers(msrs);
        spin_lock(&oprofilefs_lock);
-        model->setup_ctrs(msrs);
+        model->setup_ctrs(model, msrs);
+        nmi_cpu_setup_mux(cpu, msrs);
        spin_unlock(&oprofilefs_lock);
        per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
        apic_write(APIC_LVTPC, APIC_DM_NMI);
@@ -144,11 +341,15 @@ static int nmi_setup(void)
        int cpu;
        if (!allocate_msrs())
-                return -ENOMEM;
+                err = -ENOMEM;
+        else if (!nmi_setup_mux())
+                err = -ENOMEM;
+        else
+                err = register_die_notifier(&profile_exceptions_nb);
-        err = register_die_notifier(&profile_exceptions_nb);
        if (err) {
                free_msrs();
+                nmi_shutdown_mux();
                return err;
        }
@@ -159,45 +360,38 @@ static int nmi_setup(void)
        /* Assume saved/restored counters are the same on all CPUs */
        model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
        for_each_possible_cpu(cpu) {
-                if (cpu != 0) {
+                if (!cpu)
-                        memcpy(per_cpu(cpu_msrs, cpu).counters,
+                        continue;
-                                per_cpu(cpu_msrs, 0).counters,
-                                sizeof(struct op_msr) * model->num_counters);
+                memcpy(per_cpu(cpu_msrs, cpu).counters,
+                       per_cpu(cpu_msrs, 0).counters,
-                        memcpy(per_cpu(cpu_msrs, cpu).controls,
+                       sizeof(struct op_msr) * model->num_counters);
-                                per_cpu(cpu_msrs, 0).controls,
-                                sizeof(struct op_msr) * model->num_controls);
+                memcpy(per_cpu(cpu_msrs, cpu).controls,
-                }
+                       per_cpu(cpu_msrs, 0).controls,
+                       sizeof(struct op_msr) * model->num_controls);
+                mux_clone(cpu);
        }
-        on_each_cpu(nmi_save_registers, NULL, 1);
        on_each_cpu(nmi_cpu_setup, NULL, 1);
        nmi_enabled = 1;
        return 0;
 }
-static void nmi_restore_registers(struct op_msrs *msrs)
+static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 {
-        unsigned int const nr_ctrs = model->num_counters;
-        unsigned int const nr_ctrls = model->num_controls;
        struct op_msr *counters = msrs->counters;
        struct op_msr *controls = msrs->controls;
        unsigned int i;
-        for (i = 0; i < nr_ctrls; ++i) {
+        for (i = 0; i < model->num_controls; ++i) {
-                if (controls[i].addr) {
+                if (controls[i].addr)
-                        wrmsr(controls[i].addr,
+                        wrmsrl(controls[i].addr, controls[i].saved);
-                                controls[i].saved.low,
-                                controls[i].saved.high);
-                }
        }
-        for (i = 0; i < nr_ctrs; ++i) {
+        for (i = 0; i < model->num_counters; ++i) {
-                if (counters[i].addr) {
+                if (counters[i].addr)
-                        wrmsr(counters[i].addr,
+                        wrmsrl(counters[i].addr, counters[i].saved);
-                                counters[i].saved.low,
-                                counters[i].saved.high);
-                }
        }
 }
@@ -205,7 +399,7 @@ static void nmi_cpu_shutdown(void *dummy)
 {
        unsigned int v;
        int cpu = smp_processor_id();
-        struct op_msrs *msrs = &__get_cpu_var(cpu_msrs);
+        struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
        /* restoring APIC_LVTPC can trigger an apic error because the delivery
         * mode and vector nr combination can be illegal. That's by design: on
@@ -216,7 +410,7 @@ static void nmi_cpu_shutdown(void *dummy)
        apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
        apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
        apic_write(APIC_LVTERR, v);
-        nmi_restore_registers(msrs);
+        nmi_cpu_restore_registers(msrs);
 }
 static void nmi_shutdown(void)
@@ -226,42 +420,18 @@ static void nmi_shutdown(void)
        nmi_enabled = 0;
        on_each_cpu(nmi_cpu_shutdown, NULL, 1);
        unregister_die_notifier(&profile_exceptions_nb);
+        nmi_shutdown_mux();
        msrs = &get_cpu_var(cpu_msrs);
        model->shutdown(msrs);
        free_msrs();
        put_cpu_var(cpu_msrs);
 }
-static void nmi_cpu_start(void *dummy)
-{
-        struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
-        model->start(msrs);
-}
-static int nmi_start(void)
-{
-        on_each_cpu(nmi_cpu_start, NULL, 1);
-        return 0;
-}
-static void nmi_cpu_stop(void *dummy)
-{
-        struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
-        model->stop(msrs);
-}
-static void nmi_stop(void)
-{
-        on_each_cpu(nmi_cpu_stop, NULL, 1);
-}
-struct op_counter_config counter_config[OP_MAX_COUNTER];
 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 {
        unsigned int i;
-        for (i = 0; i < model->num_counters; ++i) {
+        for (i = 0; i < model->num_virt_counters; ++i) {
                struct dentry *dir;
                char buf[4];
@@ -270,7 +440,7 @@ static int nmi_create_files(struct super_block *sb, struct dentry *root)
                 * NOTE:  assumes 1:1 mapping here (that counters are organized
                 *        sequentially in their struct assignment).
                 */
-                if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
+                if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
                        continue;
                snprintf(buf,  sizeof(buf), "%d", i);
@@ -402,6 +572,7 @@ module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 static int __init ppro_init(char **cpu_type)
 {
        __u8 cpu_model = boot_cpu_data.x86_model;
+        struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
        if (force_arch_perfmon && cpu_has_arch_perfmon)
                return 0;
@@ -428,7 +599,7 @@ static int __init ppro_init(char **cpu_type)
                *cpu_type = "i386/core_2";
                break;
        case 26:
-                arch_perfmon_setup_counters();
+                spec = &op_arch_perfmon_spec;
                *cpu_type = "i386/core_i7";
                break;
        case 28:
@@ -439,17 +610,7 @@ static int __init ppro_init(char **cpu_type)
                return 0;
        }
-        model = &op_ppro_spec;
+        model = spec;
-        return 1;
-}
-static int __init arch_perfmon_init(char **cpu_type)
-{
-        if (!cpu_has_arch_perfmon)
-                return 0;
-        *cpu_type = "i386/arch_perfmon";
-        model = &op_arch_perfmon_spec;
-        arch_perfmon_setup_counters();
        return 1;
 }
@@ -471,27 +632,26 @@ int __init op_nmi_init(struct oprofile_operations *ops)
                /* Needs to be at least an Athlon (or hammer in 32bit mode) */
                switch (family) {
-                default:
-                        return -ENODEV;
                case 6:
-                        model = &op_amd_spec;
                        cpu_type = "i386/athlon";
                        break;
                case 0xf:
-                        model = &op_amd_spec;
+                        /*
-                        /* Actually it could be i386/hammer too, but give
+                         * Actually it could be i386/hammer too, but
-                         user space an consistent name. */
+                         * give user space an consistent name.
+                         */
                        cpu_type = "x86-64/hammer";
                        break;
                case 0x10:
-                        model = &op_amd_spec;
                        cpu_type = "x86-64/family10";
                        break;
                case 0x11:
-                        model = &op_amd_spec;
                        cpu_type = "x86-64/family11h";
                        break;
+                default:
+                        return -ENODEV;
                }
+                model = &op_amd_spec;
                break;
        case X86_VENDOR_INTEL:
@@ -510,8 +670,15 @@ int __init op_nmi_init(struct oprofile_operations *ops)
                        break;
                }
-                if (!cpu_type && !arch_perfmon_init(&cpu_type))
+                if (cpu_type)
+                        break;
+                if (!cpu_has_arch_perfmon)
                        return -ENODEV;
+                /* use arch perfmon as fallback */
+                cpu_type = "i386/arch_perfmon";
+                model = &op_arch_perfmon_spec;
                break;
        default:
@@ -522,18 +689,23 @@ int __init op_nmi_init(struct oprofile_operations *ops)
        register_cpu_notifier(&oprofile_cpu_nb);
 #endif
        /* default values, can be overwritten by model */
-        ops->create_files = nmi_create_files;
+        ops->create_files       = nmi_create_files;
-        ops->setup = nmi_setup;
+        ops->setup              = nmi_setup;
-        ops->shutdown = nmi_shutdown;
+        ops->shutdown           = nmi_shutdown;
-        ops->start = nmi_start;
+        ops->start              = nmi_start;
-        ops->stop = nmi_stop;
+        ops->stop               = nmi_stop;
-        ops->cpu_type = cpu_type;
+        ops->cpu_type           = cpu_type;
        if (model->init)
                ret = model->init(ops);
        if (ret)
                return ret;
+        if (!model->num_virt_counters)
+                model->num_virt_counters = model->num_counters;
+        mux_init(ops);
        init_sysfs();
        using_nmi = 1;
        printk(KERN_INFO "oprofile: using NMI interrupt.\n");
diff --git a/arch/x86/oprofile/op_counter.h b/arch/x86/oprofile/op_counter.h
index 91b6a116165e..e28398df0df2 100644
--- a/arch/x86/oprofile/op_counter.h
+++ b/arch/x86/oprofile/op_counter.h
@@ -10,7 +10,7 @@
 #ifndef OP_COUNTER_H
 #define OP_COUNTER_H
-#define OP_MAX_COUNTER 8
+#define OP_MAX_COUNTER 32
 /* Per-perfctr configuration as set via
 * oprofilefs.
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c
index 8fdf06e4edf9..39686c29f03a 100644
--- a/arch/x86/oprofile/op_model_amd.c
+++ b/arch/x86/oprofile/op_model_amd.c
@@ -9,12 +9,15 @@
 * @author Philippe Elie
 * @author Graydon Hoare
 * @author Robert Richter <robert.richter@amd.com>
- * @author Barry Kasindorf
+ * @author Barry Kasindorf <barry.kasindorf@amd.com>
+ * @author Jason Yeh <jason.yeh@amd.com>
+ * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
 */
 #include <linux/oprofile.h>
 #include <linux/device.h>
 #include <linux/pci.h>
+#include <linux/percpu.h>
 #include <asm/ptrace.h>
 #include <asm/msr.h>
@@ -25,43 +28,36 @@
 #define NUM_COUNTERS 4
 #define NUM_CONTROLS 4
+#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+#define NUM_VIRT_COUNTERS 32
+#define NUM_VIRT_CONTROLS 32
+#else
+#define NUM_VIRT_COUNTERS NUM_COUNTERS
+#define NUM_VIRT_CONTROLS NUM_CONTROLS
+#endif
+#define OP_EVENT_MASK                   0x0FFF
+#define OP_CTR_OVERFLOW                 (1ULL<<31)
-#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
+#define MSR_AMD_EVENTSEL_RESERVED       ((0xFFFFFCF0ULL<<32)|(1ULL<<21))
-#define CTR_READ(l, h, msrs, c) do {rdmsr(msrs->counters[(c)].addr, (l), (h)); } while (0)
-#define CTR_WRITE(l, msrs, c) do {wrmsr(msrs->counters[(c)].addr, -(unsigned int)(l), -1); } while (0)
+static unsigned long reset_value[NUM_VIRT_COUNTERS];
-#define CTR_OVERFLOWED(n) (!((n) & (1U<<31)))
-#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
-#define CTRL_READ(l, h, msrs, c) do {rdmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
-#define CTRL_WRITE(l, h, msrs, c) do {wrmsr(msrs->controls[(c)].addr, (l), (h)); } while (0)
-#define CTRL_SET_ACTIVE(n) (n |= (1<<22))
-#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
-#define CTRL_CLEAR_LO(x) (x &= (1<<21))
-#define CTRL_CLEAR_HI(x) (x &= 0xfffffcf0)
-#define CTRL_SET_ENABLE(val) (val |= 1<<20)
-#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
-#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
-#define CTRL_SET_UM(val, m) (val |= (m << 8))
-#define CTRL_SET_EVENT_LOW(val, e) (val |= (e & 0xff))
-#define CTRL_SET_EVENT_HIGH(val, e) (val |= ((e >> 8) & 0xf))
-#define CTRL_SET_HOST_ONLY(val, h) (val |= ((h & 1) << 9))
-#define CTRL_SET_GUEST_ONLY(val, h) (val |= ((h & 1) << 8))
-static unsigned long reset_value[NUM_COUNTERS];
 #ifdef CONFIG_OPROFILE_IBS
 /* IbsFetchCtl bits/masks */
-#define IBS_FETCH_HIGH_VALID_BIT        (1UL << 17)     /* bit 49 */
+#define IBS_FETCH_RAND_EN               (1ULL<<57)
-#define IBS_FETCH_HIGH_ENABLE           (1UL << 16)     /* bit 48 */
+#define IBS_FETCH_VAL                   (1ULL<<49)
-#define IBS_FETCH_LOW_MAX_CNT_MASK      0x0000FFFFUL    /* MaxCnt mask */
+#define IBS_FETCH_ENABLE                (1ULL<<48)
+#define IBS_FETCH_CNT_MASK              0xFFFF0000ULL
 /*IbsOpCtl bits */
-#define IBS_OP_LOW_VALID_BIT            (1ULL<<18)      /* bit 18 */
+#define IBS_OP_CNT_CTL                  (1ULL<<19)
-#define IBS_OP_LOW_ENABLE               (1ULL<<17)      /* bit 17 */
+#define IBS_OP_VAL                      (1ULL<<18)
+#define IBS_OP_ENABLE                   (1ULL<<17)
-#define IBS_FETCH_SIZE  6
+#define IBS_FETCH_SIZE                  6
-#define IBS_OP_SIZE     12
+#define IBS_OP_SIZE                     12
 static int has_ibs;     /* AMD Family10h and later */
@@ -78,6 +74,45 @@ static struct op_ibs_config ibs_config;
 #endif
+#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+static void op_mux_fill_in_addresses(struct op_msrs * const msrs)
+{
+        int i;
+        for (i = 0; i < NUM_VIRT_COUNTERS; i++) {
+                int hw_counter = op_x86_virt_to_phys(i);
+                if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i))
+                        msrs->multiplex[i].addr = MSR_K7_PERFCTR0 + hw_counter;
+                else
+                        msrs->multiplex[i].addr = 0;
+        }
+}
+static void op_mux_switch_ctrl(struct op_x86_model_spec const *model,
+                               struct op_msrs const * const msrs)
+{
+        u64 val;
+        int i;
+        /* enable active counters */
+        for (i = 0; i < NUM_COUNTERS; ++i) {
+                int virt = op_x86_phys_to_virt(i);
+                if (!counter_config[virt].enabled)
+                        continue;
+                rdmsrl(msrs->controls[i].addr, val);
+                val &= model->reserved;
+                val |= op_x86_get_ctrl(model, &counter_config[virt]);
+                wrmsrl(msrs->controls[i].addr, val);
+        }
+}
+#else
+static inline void op_mux_fill_in_addresses(struct op_msrs * const msrs) { }
+#endif
 /* functions for op_amd_spec */
 static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
@@ -97,150 +132,174 @@ static void op_amd_fill_in_addresses(struct op_msrs * const msrs)
                else
                        msrs->controls[i].addr = 0;
        }
-}
+        op_mux_fill_in_addresses(msrs);
+}
-static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
+static void op_amd_setup_ctrs(struct op_x86_model_spec const *model,
+                              struct op_msrs const * const msrs)
 {
-        unsigned int low, high;
+        u64 val;
        int i;
+        /* setup reset_value */
+        for (i = 0; i < NUM_VIRT_COUNTERS; ++i) {
+                if (counter_config[i].enabled)
+                        reset_value[i] = counter_config[i].count;
+                else
+                        reset_value[i] = 0;
+        }
        /* clear all counters */
-        for (i = 0 ; i < NUM_CONTROLS; ++i) {
+        for (i = 0; i < NUM_CONTROLS; ++i) {
-                if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
+                if (unlikely(!msrs->controls[i].addr))
                        continue;
-                CTRL_READ(low, high, msrs, i);
+                rdmsrl(msrs->controls[i].addr, val);
-                CTRL_CLEAR_LO(low);
+                val &= model->reserved;
-                CTRL_CLEAR_HI(high);
+                wrmsrl(msrs->controls[i].addr, val);
-                CTRL_WRITE(low, high, msrs, i);
        }
        /* avoid a false detection of ctr overflows in NMI handler */
        for (i = 0; i < NUM_COUNTERS; ++i) {
-                if (unlikely(!CTR_IS_RESERVED(msrs, i)))
+                if (unlikely(!msrs->counters[i].addr))
                        continue;
-                CTR_WRITE(1, msrs, i);
+                wrmsrl(msrs->counters[i].addr, -1LL);
        }
        /* enable active counters */
        for (i = 0; i < NUM_COUNTERS; ++i) {
-                if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
+                int virt = op_x86_phys_to_virt(i);
-                        reset_value[i] = counter_config[i].count;
+                if (!counter_config[virt].enabled)
+                        continue;
+                if (!msrs->counters[i].addr)
+                        continue;
-                        CTR_WRITE(counter_config[i].count, msrs, i);
+                /* setup counter registers */
+                wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
-                        CTRL_READ(low, high, msrs, i);
-                        CTRL_CLEAR_LO(low);
+                /* setup control registers */
-                        CTRL_CLEAR_HI(high);
+                rdmsrl(msrs->controls[i].addr, val);
-                        CTRL_SET_ENABLE(low);
+                val &= model->reserved;
-                        CTRL_SET_USR(low, counter_config[i].user);
+                val |= op_x86_get_ctrl(model, &counter_config[virt]);
-                        CTRL_SET_KERN(low, counter_config[i].kernel);
+                wrmsrl(msrs->controls[i].addr, val);
-                        CTRL_SET_UM(low, counter_config[i].unit_mask);
-                        CTRL_SET_EVENT_LOW(low, counter_config[i].event);
-                        CTRL_SET_EVENT_HIGH(high, counter_config[i].event);
-                        CTRL_SET_HOST_ONLY(high, 0);
-                        CTRL_SET_GUEST_ONLY(high, 0);
-                        CTRL_WRITE(low, high, msrs, i);
-                } else {
-                        reset_value[i] = 0;
-                }
        }
 }
 #ifdef CONFIG_OPROFILE_IBS
-static inline int
+static inline void
 op_amd_handle_ibs(struct pt_regs * const regs,
                  struct op_msrs const * const msrs)
 {
-        u32 low, high;
+        u64 val, ctl;
-        u64 msr;
        struct op_entry entry;
        if (!has_ibs)
-                return 1;
+                return;
        if (ibs_config.fetch_enabled) {
-                rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
+                rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
-                if (high & IBS_FETCH_HIGH_VALID_BIT) {
+                if (ctl & IBS_FETCH_VAL) {
-                        rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr);
+                        rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);
-                        oprofile_write_reserve(&entry, regs, msr,
+                        oprofile_write_reserve(&entry, regs, val,
                                               IBS_FETCH_CODE, IBS_FETCH_SIZE);
-                        oprofile_add_data(&entry, (u32)msr);
+                        oprofile_add_data64(&entry, val);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
+                        oprofile_add_data64(&entry, ctl);
-                        oprofile_add_data(&entry, low);
+                        rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);
-                        oprofile_add_data(&entry, high);
+                        oprofile_add_data64(&entry, val);
-                        rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr);
-                        oprofile_add_data(&entry, (u32)msr);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
                        oprofile_write_commit(&entry);
                        /* reenable the IRQ */
-                        high &= ~IBS_FETCH_HIGH_VALID_BIT;
+                        ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT_MASK);
-                        high |= IBS_FETCH_HIGH_ENABLE;
+                        ctl |= IBS_FETCH_ENABLE;
-                        low &= IBS_FETCH_LOW_MAX_CNT_MASK;
+                        wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl);
-                        wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
                }
        }
        if (ibs_config.op_enabled) {
-                rdmsr(MSR_AMD64_IBSOPCTL, low, high);
+                rdmsrl(MSR_AMD64_IBSOPCTL, ctl);
-                if (low & IBS_OP_LOW_VALID_BIT) {
+                if (ctl & IBS_OP_VAL) {
-                        rdmsrl(MSR_AMD64_IBSOPRIP, msr);
+                        rdmsrl(MSR_AMD64_IBSOPRIP, val);
-                        oprofile_write_reserve(&entry, regs, msr,
+                        oprofile_write_reserve(&entry, regs, val,
                                               IBS_OP_CODE, IBS_OP_SIZE);
-                        oprofile_add_data(&entry, (u32)msr);
+                        oprofile_add_data64(&entry, val);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
+                        rdmsrl(MSR_AMD64_IBSOPDATA, val);
-                        rdmsrl(MSR_AMD64_IBSOPDATA, msr);
+                        oprofile_add_data64(&entry, val);
-                        oprofile_add_data(&entry, (u32)msr);
+                        rdmsrl(MSR_AMD64_IBSOPDATA2, val);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
+                        oprofile_add_data64(&entry, val);
-                        rdmsrl(MSR_AMD64_IBSOPDATA2, msr);
+                        rdmsrl(MSR_AMD64_IBSOPDATA3, val);
-                        oprofile_add_data(&entry, (u32)msr);
+                        oprofile_add_data64(&entry, val);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
+                        rdmsrl(MSR_AMD64_IBSDCLINAD, val);
-                        rdmsrl(MSR_AMD64_IBSOPDATA3, msr);
+                        oprofile_add_data64(&entry, val);
-                        oprofile_add_data(&entry, (u32)msr);
+                        rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
+                        oprofile_add_data64(&entry, val);
-                        rdmsrl(MSR_AMD64_IBSDCLINAD, msr);
-                        oprofile_add_data(&entry, (u32)msr);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
-                        rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr);
-                        oprofile_add_data(&entry, (u32)msr);
-                        oprofile_add_data(&entry, (u32)(msr >> 32));
                        oprofile_write_commit(&entry);
                        /* reenable the IRQ */
-                        high = 0;
+                        ctl &= ~IBS_OP_VAL & 0xFFFFFFFF;
-                        low &= ~IBS_OP_LOW_VALID_BIT;
+                        ctl |= IBS_OP_ENABLE;
-                        low |= IBS_OP_LOW_ENABLE;
+                        wrmsrl(MSR_AMD64_IBSOPCTL, ctl);
-                        wrmsr(MSR_AMD64_IBSOPCTL, low, high);
                }
        }
+}
-        return 1;
+static inline void op_amd_start_ibs(void)
+{
+        u64 val;
+        if (has_ibs && ibs_config.fetch_enabled) {
+                val = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
+                val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;
+                val |= IBS_FETCH_ENABLE;
+                wrmsrl(MSR_AMD64_IBSFETCHCTL, val);
+        }
+        if (has_ibs && ibs_config.op_enabled) {
+                val = (ibs_config.max_cnt_op >> 4) & 0xFFFF;
+                val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;
+                val |= IBS_OP_ENABLE;
+                wrmsrl(MSR_AMD64_IBSOPCTL, val);
+        }
+}
+static void op_amd_stop_ibs(void)
+{
+        if (has_ibs && ibs_config.fetch_enabled)
+                /* clear max count and enable */
+                wrmsrl(MSR_AMD64_IBSFETCHCTL, 0);
+        if (has_ibs && ibs_config.op_enabled)
+                /* clear max count and enable */
+                wrmsrl(MSR_AMD64_IBSOPCTL, 0);
 }
+#else
+static inline void op_amd_handle_ibs(struct pt_regs * const regs,
+                                    struct op_msrs const * const msrs) { }
+static inline void op_amd_start_ibs(void) { }
+static inline void op_amd_stop_ibs(void) { }
 #endif
 static int op_amd_check_ctrs(struct pt_regs * const regs,
                             struct op_msrs const * const msrs)
 {
-        unsigned int low, high;
+        u64 val;
        int i;
-        for (i = 0 ; i < NUM_COUNTERS; ++i) {
+        for (i = 0; i < NUM_COUNTERS; ++i) {
-                if (!reset_value[i])
+                int virt = op_x86_phys_to_virt(i);
+                if (!reset_value[virt])
                        continue;
-                CTR_READ(low, high, msrs, i);
+                rdmsrl(msrs->counters[i].addr, val);
-                if (CTR_OVERFLOWED(low)) {
+                /* bit is clear if overflowed: */
-                        oprofile_add_sample(regs, i);
+                if (val & OP_CTR_OVERFLOW)
-                        CTR_WRITE(reset_value[i], msrs, i);
+                        continue;
-                }
+                oprofile_add_sample(regs, virt);
+                wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]);
        }
-#ifdef CONFIG_OPROFILE_IBS
        op_amd_handle_ibs(regs, msrs);
-#endif
        /* See op_model_ppro.c */
        return 1;
@@ -248,79 +307,50 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
 static void op_amd_start(struct op_msrs const * const msrs)
 {
-        unsigned int low, high;
+        u64 val;
        int i;
-        for (i = 0 ; i < NUM_COUNTERS ; ++i) {
-                if (reset_value[i]) {
-                        CTRL_READ(low, high, msrs, i);
-                        CTRL_SET_ACTIVE(low);
-                        CTRL_WRITE(low, high, msrs, i);
-                }
-        }
-#ifdef CONFIG_OPROFILE_IBS
+        for (i = 0; i < NUM_COUNTERS; ++i) {
-        if (has_ibs && ibs_config.fetch_enabled) {
+                if (!reset_value[op_x86_phys_to_virt(i)])
-                low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF;
+                        continue;
-                high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */
+                rdmsrl(msrs->controls[i].addr, val);
-                        + IBS_FETCH_HIGH_ENABLE;
+                val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-                wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
+                wrmsrl(msrs->controls[i].addr, val);
        }
-        if (has_ibs && ibs_config.op_enabled) {
+        op_amd_start_ibs();
-                low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF)
-                        + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */
-                        + IBS_OP_LOW_ENABLE;
-                high = 0;
-                wrmsr(MSR_AMD64_IBSOPCTL, low, high);
-        }
-#endif
 }
 static void op_amd_stop(struct op_msrs const * const msrs)
 {
-        unsigned int low, high;
+        u64 val;
        int i;
        /*
         * Subtle: stop on all counters to avoid race with setting our
         * pm callback
         */
-        for (i = 0 ; i < NUM_COUNTERS ; ++i) {
+        for (i = 0; i < NUM_COUNTERS; ++i) {
-                if (!reset_value[i])
+                if (!reset_value[op_x86_phys_to_virt(i)])
                        continue;
-                CTRL_READ(low, high, msrs, i);
+                rdmsrl(msrs->controls[i].addr, val);
-                CTRL_SET_INACTIVE(low);
+                val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
-                CTRL_WRITE(low, high, msrs, i);
+                wrmsrl(msrs->controls[i].addr, val);
-        }
-#ifdef CONFIG_OPROFILE_IBS
-        if (has_ibs && ibs_config.fetch_enabled) {
-                /* clear max count and enable */
-                low = 0;
-                high = 0;
-                wrmsr(MSR_AMD64_IBSFETCHCTL, low, high);
        }
-        if (has_ibs && ibs_config.op_enabled) {
+        op_amd_stop_ibs();
-                /* clear max count and enable */
-                low = 0;
-                high = 0;
-                wrmsr(MSR_AMD64_IBSOPCTL, low, high);
-        }
-#endif
 }
 static void op_amd_shutdown(struct op_msrs const * const msrs)
 {
        int i;
-        for (i = 0 ; i < NUM_COUNTERS ; ++i) {
+        for (i = 0; i < NUM_COUNTERS; ++i) {
-                if (CTR_IS_RESERVED(msrs, i))
+                if (msrs->counters[i].addr)
                        release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
        }
-        for (i = 0 ; i < NUM_CONTROLS ; ++i) {
+        for (i = 0; i < NUM_CONTROLS; ++i) {
-                if (CTRL_IS_RESERVED(msrs, i))
+                if (msrs->controls[i].addr)
                        release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
        }
 }
@@ -490,15 +520,21 @@ static void op_amd_exit(void) {}
 #endif /* CONFIG_OPROFILE_IBS */
-struct op_x86_model_spec const op_amd_spec = {
+struct op_x86_model_spec op_amd_spec = {
-        .init                   = op_amd_init,
-        .exit                   = op_amd_exit,
        .num_counters           = NUM_COUNTERS,
        .num_controls           = NUM_CONTROLS,
+        .num_virt_counters      = NUM_VIRT_COUNTERS,
+        .reserved               = MSR_AMD_EVENTSEL_RESERVED,
+        .event_mask             = OP_EVENT_MASK,
+        .init                   = op_amd_init,
+        .exit                   = op_amd_exit,
        .fill_in_addresses      = &op_amd_fill_in_addresses,
        .setup_ctrs             = &op_amd_setup_ctrs,
        .check_ctrs             = &op_amd_check_ctrs,
        .start                  = &op_amd_start,
        .stop                   = &op_amd_stop,
-        .shutdown               = &op_amd_shutdown
+        .shutdown               = &op_amd_shutdown,
+#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+        .switch_ctrl            = &op_mux_switch_ctrl,
+#endif
 };
diff --git a/arch/x86/oprofile/op_model_p4.c b/arch/x86/oprofile/op_model_p4.c
index 819b131fd752..ac6b354becdf 100644
--- a/arch/x86/oprofile/op_model_p4.c
+++ b/arch/x86/oprofile/op_model_p4.c
@@ -32,6 +32,8 @@
 #define NUM_CCCRS_HT2 9
 #define NUM_CONTROLS_HT2 (NUM_ESCRS_HT2 + NUM_CCCRS_HT2)
+#define OP_CTR_OVERFLOW                 (1ULL<<31)
 static unsigned int num_counters = NUM_COUNTERS_NON_HT;
 static unsigned int num_controls = NUM_CONTROLS_NON_HT;
@@ -350,8 +352,6 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
 #define ESCR_SET_OS_1(escr, os) ((escr) |= (((os) & 1) << 1))
 #define ESCR_SET_EVENT_SELECT(escr, sel) ((escr) |= (((sel) & 0x3f) << 25))
 #define ESCR_SET_EVENT_MASK(escr, mask) ((escr) |= (((mask) & 0xffff) << 9))
-#define ESCR_READ(escr, high, ev, i) do {rdmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
-#define ESCR_WRITE(escr, high, ev, i) do {wrmsr(ev->bindings[(i)].escr_address, (escr), (high)); } while (0)
 #define CCCR_RESERVED_BITS 0x38030FFF
 #define CCCR_CLEAR(cccr) ((cccr) &= CCCR_RESERVED_BITS)
@@ -361,17 +361,9 @@ static struct p4_event_binding p4_events[NUM_EVENTS] = {
 #define CCCR_SET_PMI_OVF_1(cccr) ((cccr) |= (1<<27))
 #define CCCR_SET_ENABLE(cccr) ((cccr) |= (1<<12))
 #define CCCR_SET_DISABLE(cccr) ((cccr) &= ~(1<<12))
-#define CCCR_READ(low, high, i) do {rdmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
-#define CCCR_WRITE(low, high, i) do {wrmsr(p4_counters[(i)].cccr_address, (low), (high)); } while (0)
 #define CCCR_OVF_P(cccr) ((cccr) & (1U<<31))
 #define CCCR_CLEAR_OVF(cccr) ((cccr) &= (~(1U<<31)))
-#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
-#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
-#define CTR_READ(l, h, i) do {rdmsr(p4_counters[(i)].counter_address, (l), (h)); } while (0)
-#define CTR_WRITE(l, i) do {wrmsr(p4_counters[(i)].counter_address, -(u32)(l), -1); } while (0)
-#define CTR_OVERFLOW_P(ctr) (!((ctr) & 0x80000000))
 /* this assigns a "stagger" to the current CPU, which is used throughout
   the code in this module as an extra array offset, to select the "even"
@@ -515,7 +507,7 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
                if (ev->bindings[i].virt_counter & counter_bit) {
                        /* modify ESCR */
-                        ESCR_READ(escr, high, ev, i);
+                        rdmsr(ev->bindings[i].escr_address, escr, high);
                        ESCR_CLEAR(escr);
                        if (stag == 0) {
                                ESCR_SET_USR_0(escr, counter_config[ctr].user);
@@ -526,10 +518,11 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
                        }
                        ESCR_SET_EVENT_SELECT(escr, ev->event_select);
                        ESCR_SET_EVENT_MASK(escr, counter_config[ctr].unit_mask);
-                        ESCR_WRITE(escr, high, ev, i);
+                        wrmsr(ev->bindings[i].escr_address, escr, high);
                        /* modify CCCR */
-                        CCCR_READ(cccr, high, VIRT_CTR(stag, ctr));
+                        rdmsr(p4_counters[VIRT_CTR(stag, ctr)].cccr_address,
+                              cccr, high);
                        CCCR_CLEAR(cccr);
                        CCCR_SET_REQUIRED_BITS(cccr);
                        CCCR_SET_ESCR_SELECT(cccr, ev->escr_select);
@@ -537,7 +530,8 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
                                CCCR_SET_PMI_OVF_0(cccr);
                        else
                                CCCR_SET_PMI_OVF_1(cccr);
-                        CCCR_WRITE(cccr, high, VIRT_CTR(stag, ctr));
+                        wrmsr(p4_counters[VIRT_CTR(stag, ctr)].cccr_address,
+                              cccr, high);
                        return;
                }
        }
@@ -548,7 +542,8 @@ static void pmc_setup_one_p4_counter(unsigned int ctr)
 }
-static void p4_setup_ctrs(struct op_msrs const * const msrs)
+static void p4_setup_ctrs(struct op_x86_model_spec const *model,
+                          struct op_msrs const * const msrs)
 {
        unsigned int i;
        unsigned int low, high;
@@ -563,8 +558,8 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
        }
        /* clear the cccrs we will use */
-        for (i = 0 ; i < num_counters ; i++) {
+        for (i = 0; i < num_counters; i++) {
-                if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
+                if (unlikely(!msrs->controls[i].addr))
                        continue;
                rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
                CCCR_CLEAR(low);
@@ -574,17 +569,18 @@ static void p4_setup_ctrs(struct op_msrs const * const msrs)
        /* clear all escrs (including those outside our concern) */
        for (i = num_counters; i < num_controls; i++) {
-                if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
+                if (unlikely(!msrs->controls[i].addr))
                        continue;
                wrmsr(msrs->controls[i].addr, 0, 0);
        }
        /* setup all counters */
-        for (i = 0 ; i < num_counters ; ++i) {
+        for (i = 0; i < num_counters; ++i) {
-                if ((counter_config[i].enabled) && (CTRL_IS_RESERVED(msrs, i))) {
+                if (counter_config[i].enabled && msrs->controls[i].addr) {
                        reset_value[i] = counter_config[i].count;
                        pmc_setup_one_p4_counter(i);
-                        CTR_WRITE(counter_config[i].count, VIRT_CTR(stag, i));
+                        wrmsrl(p4_counters[VIRT_CTR(stag, i)].counter_address,
+                               -(u64)counter_config[i].count);
                } else {
                        reset_value[i] = 0;
                }
@@ -624,14 +620,16 @@ static int p4_check_ctrs(struct pt_regs * const regs,
                real = VIRT_CTR(stag, i);
-                CCCR_READ(low, high, real);
+                rdmsr(p4_counters[real].cccr_address, low, high);
-                CTR_READ(ctr, high, real);
+                rdmsr(p4_counters[real].counter_address, ctr, high);
-                if (CCCR_OVF_P(low) || CTR_OVERFLOW_P(ctr)) {
+                if (CCCR_OVF_P(low) || !(ctr & OP_CTR_OVERFLOW)) {
                        oprofile_add_sample(regs, i);
-                        CTR_WRITE(reset_value[i], real);
+                        wrmsrl(p4_counters[real].counter_address,
+                               -(u64)reset_value[i]);
                        CCCR_CLEAR_OVF(low);
-                        CCCR_WRITE(low, high, real);
+                        wrmsr(p4_counters[real].cccr_address, low, high);
-                        CTR_WRITE(reset_value[i], real);
+                        wrmsrl(p4_counters[real].counter_address,
+                               -(u64)reset_value[i]);
                }
        }
@@ -653,9 +651,9 @@ static void p4_start(struct op_msrs const * const msrs)
        for (i = 0; i < num_counters; ++i) {
                if (!reset_value[i])
                        continue;
-                CCCR_READ(low, high, VIRT_CTR(stag, i));
+                rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
                CCCR_SET_ENABLE(low);
-                CCCR_WRITE(low, high, VIRT_CTR(stag, i));
+                wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
        }
 }
@@ -670,9 +668,9 @@ static void p4_stop(struct op_msrs const * const msrs)
        for (i = 0; i < num_counters; ++i) {
                if (!reset_value[i])
                        continue;
-                CCCR_READ(low, high, VIRT_CTR(stag, i));
+                rdmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
                CCCR_SET_DISABLE(low);
-                CCCR_WRITE(low, high, VIRT_CTR(stag, i));
+                wrmsr(p4_counters[VIRT_CTR(stag, i)].cccr_address, low, high);
        }
 }
@@ -680,8 +678,8 @@ static void p4_shutdown(struct op_msrs const * const msrs)
 {
        int i;
-        for (i = 0 ; i < num_counters ; ++i) {
+        for (i = 0; i < num_counters; ++i) {
-                if (CTR_IS_RESERVED(msrs, i))
+                if (msrs->counters[i].addr)
                        release_perfctr_nmi(msrs->counters[i].addr);
        }
        /*
@@ -689,15 +687,15 @@ static void p4_shutdown(struct op_msrs const * const msrs)
         * conjunction with the counter registers (hence the starting offset).
         * This saves a few bits.
         */
-        for (i = num_counters ; i < num_controls ; ++i) {
+        for (i = num_counters; i < num_controls; ++i) {
-                if (CTRL_IS_RESERVED(msrs, i))
+                if (msrs->controls[i].addr)
                        release_evntsel_nmi(msrs->controls[i].addr);
        }
 }
 #ifdef CONFIG_SMP
-struct op_x86_model_spec const op_p4_ht2_spec = {
+struct op_x86_model_spec op_p4_ht2_spec = {
        .num_counters           = NUM_COUNTERS_HT2,
        .num_controls           = NUM_CONTROLS_HT2,
        .fill_in_addresses      = &p4_fill_in_addresses,
@@ -709,7 +707,7 @@ struct op_x86_model_spec const op_p4_ht2_spec = {
 };
 #endif
-struct op_x86_model_spec const op_p4_spec = {
+struct op_x86_model_spec op_p4_spec = {
        .num_counters           = NUM_COUNTERS_NON_HT,
        .num_controls           = NUM_CONTROLS_NON_HT,
        .fill_in_addresses      = &p4_fill_in_addresses,
diff --git a/arch/x86/oprofile/op_model_ppro.c b/arch/x86/oprofile/op_model_ppro.c
index 4da7230b3d17..4899215999de 100644
--- a/arch/x86/oprofile/op_model_ppro.c
+++ b/arch/x86/oprofile/op_model_ppro.c
@@ -10,6 +10,7 @@
 * @author Philippe Elie
 * @author Graydon Hoare
 * @author Andi Kleen
+ * @author Robert Richter <robert.richter@amd.com>
 */
 #include <linux/oprofile.h>
@@ -18,7 +19,6 @@
 #include <asm/msr.h>
 #include <asm/apic.h>
 #include <asm/nmi.h>
-#include <asm/perf_counter.h>
 #include "op_x86_model.h"
 #include "op_counter.h"
@@ -26,20 +26,7 @@
 static int num_counters = 2;
 static int counter_width = 32;
-#define CTR_IS_RESERVED(msrs, c) (msrs->counters[(c)].addr ? 1 : 0)
+#define MSR_PPRO_EVENTSEL_RESERVED      ((0xFFFFFFFFULL<<32)|(1ULL<<21))
-#define CTR_OVERFLOWED(n) (!((n) & (1ULL<<(counter_width-1))))
-#define CTRL_IS_RESERVED(msrs, c) (msrs->controls[(c)].addr ? 1 : 0)
-#define CTRL_READ(l, h, msrs, c) do {rdmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
-#define CTRL_WRITE(l, h, msrs, c) do {wrmsr((msrs->controls[(c)].addr), (l), (h)); } while (0)
-#define CTRL_SET_ACTIVE(n) (n |= (1<<22))
-#define CTRL_SET_INACTIVE(n) (n &= ~(1<<22))
-#define CTRL_CLEAR(x) (x &= (1<<21))
-#define CTRL_SET_ENABLE(val) (val |= 1<<20)
-#define CTRL_SET_USR(val, u) (val |= ((u & 1) << 16))
-#define CTRL_SET_KERN(val, k) (val |= ((k & 1) << 17))
-#define CTRL_SET_UM(val, m) (val |= (m << 8))
-#define CTRL_SET_EVENT(val, e) (val |= e)
 static u64 *reset_value;
@@ -63,9 +50,10 @@ static void ppro_fill_in_addresses(struct op_msrs * const msrs)
 }
-static void ppro_setup_ctrs(struct op_msrs const * const msrs)
+static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
+                            struct op_msrs const * const msrs)
 {
-        unsigned int low, high;
+        u64 val;
        int i;
        if (!reset_value) {
@@ -93,36 +81,30 @@ static void ppro_setup_ctrs(struct op_msrs const * const msrs)
        }
        /* clear all counters */
-        for (i = 0 ; i < num_counters; ++i) {
+        for (i = 0; i < num_counters; ++i) {
-                if (unlikely(!CTRL_IS_RESERVED(msrs, i)))
+                if (unlikely(!msrs->controls[i].addr))
                        continue;
-                CTRL_READ(low, high, msrs, i);
+                rdmsrl(msrs->controls[i].addr, val);
-                CTRL_CLEAR(low);
+                val &= model->reserved;
-                CTRL_WRITE(low, high, msrs, i);
+                wrmsrl(msrs->controls[i].addr, val);
        }
        /* avoid a false detection of ctr overflows in NMI handler */
        for (i = 0; i < num_counters; ++i) {
-                if (unlikely(!CTR_IS_RESERVED(msrs, i)))
+                if (unlikely(!msrs->counters[i].addr))
                        continue;
                wrmsrl(msrs->counters[i].addr, -1LL);
        }
        /* enable active counters */
        for (i = 0; i < num_counters; ++i) {
-                if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) {
+                if (counter_config[i].enabled && msrs->counters[i].addr) {
                        reset_value[i] = counter_config[i].count;
                        wrmsrl(msrs->counters[i].addr, -reset_value[i]);
+                        rdmsrl(msrs->controls[i].addr, val);
-                        CTRL_READ(low, high, msrs, i);
+                        val &= model->reserved;
-                        CTRL_CLEAR(low);
+                        val |= op_x86_get_ctrl(model, &counter_config[i]);
-                        CTRL_SET_ENABLE(low);
+                        wrmsrl(msrs->controls[i].addr, val);
-                        CTRL_SET_USR(low, counter_config[i].user);
-                        CTRL_SET_KERN(low, counter_config[i].kernel);
-                        CTRL_SET_UM(low, counter_config[i].unit_mask);
-                        CTRL_SET_EVENT(low, counter_config[i].event);
-                        CTRL_WRITE(low, high, msrs, i);
                } else {
                        reset_value[i] = 0;
                }
@@ -143,14 +125,14 @@ static int ppro_check_ctrs(struct pt_regs * const regs,
        if (unlikely(!reset_value))
                goto out;
-        for (i = 0 ; i < num_counters; ++i) {
+        for (i = 0; i < num_counters; ++i) {
                if (!reset_value[i])
                        continue;
                rdmsrl(msrs->counters[i].addr, val);
-                if (CTR_OVERFLOWED(val)) {
+                if (val & (1ULL << (counter_width - 1)))
-                        oprofile_add_sample(regs, i);
+                        continue;
-                        wrmsrl(msrs->counters[i].addr, -reset_value[i]);
+                oprofile_add_sample(regs, i);
-                }
+                wrmsrl(msrs->counters[i].addr, -reset_value[i]);
        }
 out:
@@ -171,16 +153,16 @@ out:
 static void ppro_start(struct op_msrs const * const msrs)
 {
-        unsigned int low, high;
+        u64 val;
        int i;
        if (!reset_value)
                return;
        for (i = 0; i < num_counters; ++i) {
                if (reset_value[i]) {
-                        CTRL_READ(low, high, msrs, i);
+                        rdmsrl(msrs->controls[i].addr, val);
-                        CTRL_SET_ACTIVE(low);
+                        val |= ARCH_PERFMON_EVENTSEL0_ENABLE;
-                        CTRL_WRITE(low, high, msrs, i);
+                        wrmsrl(msrs->controls[i].addr, val);
                }
        }
 }
@@ -188,7 +170,7 @@ static void ppro_start(struct op_msrs const * const msrs)
 static void ppro_stop(struct op_msrs const * const msrs)
 {
-        unsigned int low, high;
+        u64 val;
        int i;
        if (!reset_value)
@@ -196,9 +178,9 @@ static void ppro_stop(struct op_msrs const * const msrs)
        for (i = 0; i < num_counters; ++i) {
                if (!reset_value[i])
                        continue;
-                CTRL_READ(low, high, msrs, i);
+                rdmsrl(msrs->controls[i].addr, val);
-                CTRL_SET_INACTIVE(low);
+                val &= ~ARCH_PERFMON_EVENTSEL0_ENABLE;
-                CTRL_WRITE(low, high, msrs, i);
+                wrmsrl(msrs->controls[i].addr, val);
        }
 }
@@ -206,12 +188,12 @@ static void ppro_shutdown(struct op_msrs const * const msrs)
 {
        int i;
-        for (i = 0 ; i < num_counters ; ++i) {
+        for (i = 0; i < num_counters; ++i) {
-                if (CTR_IS_RESERVED(msrs, i))
+                if (msrs->counters[i].addr)
                        release_perfctr_nmi(MSR_P6_PERFCTR0 + i);
        }
-        for (i = 0 ; i < num_counters ; ++i) {
+        for (i = 0; i < num_counters; ++i) {
-                if (CTRL_IS_RESERVED(msrs, i))
+                if (msrs->controls[i].addr)
                        release_evntsel_nmi(MSR_P6_EVNTSEL0 + i);
        }
        if (reset_value) {
@@ -222,8 +204,9 @@ static void ppro_shutdown(struct op_msrs const * const msrs)
 struct op_x86_model_spec op_ppro_spec = {
-        .num_counters           = 2,    /* can be overriden */
+        .num_counters           = 2,
-        .num_controls           = 2,    /* dito */
+        .num_controls           = 2,
+        .reserved               = MSR_PPRO_EVENTSEL_RESERVED,
        .fill_in_addresses      = &ppro_fill_in_addresses,
        .setup_ctrs             = &ppro_setup_ctrs,
        .check_ctrs             = &ppro_check_ctrs,
@@ -241,7 +224,7 @@ struct op_x86_model_spec op_ppro_spec = {
 * the specific CPU.
 */
-void arch_perfmon_setup_counters(void)
+static void arch_perfmon_setup_counters(void)
 {
        union cpuid10_eax eax;
@@ -259,11 +242,17 @@ void arch_perfmon_setup_counters(void)
        op_arch_perfmon_spec.num_counters = num_counters;
        op_arch_perfmon_spec.num_controls = num_counters;
-        op_ppro_spec.num_counters = num_counters;
+}
-        op_ppro_spec.num_controls = num_counters;
+static int arch_perfmon_init(struct oprofile_operations *ignore)
+{
+        arch_perfmon_setup_counters();
+        return 0;
 }
 struct op_x86_model_spec op_arch_perfmon_spec = {
+        .reserved               = MSR_PPRO_EVENTSEL_RESERVED,
+        .init                   = &arch_perfmon_init,
        /* num_counters/num_controls filled in at runtime */
        .fill_in_addresses      = &ppro_fill_in_addresses,
        /* user space does the cpuid check for available events */
diff --git a/arch/x86/oprofile/op_x86_model.h b/arch/x86/oprofile/op_x86_model.h
index 825e79064d64..b83776180c7f 100644
--- a/arch/x86/oprofile/op_x86_model.h
+++ b/arch/x86/oprofile/op_x86_model.h
@@ -6,51 +6,66 @@
 * @remark Read the file COPYING
 *
 * @author Graydon Hoare
+ * @author Robert Richter <robert.richter@amd.com>
 */
 #ifndef OP_X86_MODEL_H
 #define OP_X86_MODEL_H
-struct op_saved_msr {
+#include <asm/types.h>
-        unsigned int high;
+#include <asm/perf_counter.h>
-        unsigned int low;
-};
 struct op_msr {
-        unsigned long addr;
+        unsigned long   addr;
-        struct op_saved_msr saved;
+        u64             saved;
 };
 struct op_msrs {
        struct op_msr *counters;
        struct op_msr *controls;
+        struct op_msr *multiplex;
 };
 struct pt_regs;
+struct oprofile_operations;
 /* The model vtable abstracts the differences between
 * various x86 CPU models' perfctr support.
 */
 struct op_x86_model_spec {
-        int (*init)(struct oprofile_operations *ops);
+        unsigned int    num_counters;
-        void (*exit)(void);
+        unsigned int    num_controls;
-        unsigned int num_counters;
+        unsigned int    num_virt_counters;
-        unsigned int num_controls;
+        u64             reserved;
-        void (*fill_in_addresses)(struct op_msrs * const msrs);
+        u16             event_mask;
-        void (*setup_ctrs)(struct op_msrs const * const msrs);
+        int             (*init)(struct oprofile_operations *ops);
-        int (*check_ctrs)(struct pt_regs * const regs,
+        void            (*exit)(void);
-                struct op_msrs const * const msrs);
+        void            (*fill_in_addresses)(struct op_msrs * const msrs);
-        void (*start)(struct op_msrs const * const msrs);
+        void            (*setup_ctrs)(struct op_x86_model_spec const *model,
-        void (*stop)(struct op_msrs const * const msrs);
+                                      struct op_msrs const * const msrs);
-        void (*shutdown)(struct op_msrs const * const msrs);
+        int             (*check_ctrs)(struct pt_regs * const regs,
+                                      struct op_msrs const * const msrs);
+        void            (*start)(struct op_msrs const * const msrs);
+        void            (*stop)(struct op_msrs const * const msrs);
+        void            (*shutdown)(struct op_msrs const * const msrs);
+#ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
+        void            (*switch_ctrl)(struct op_x86_model_spec const *model,
+                                       struct op_msrs const * const msrs);
+#endif
 };
+struct op_counter_config;
+extern u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
+                           struct op_counter_config *counter_config);
+extern int op_x86_phys_to_virt(int phys);
+extern int op_x86_virt_to_phys(int virt);
 extern struct op_x86_model_spec op_ppro_spec;
-extern struct op_x86_model_spec const op_p4_spec;
+extern struct op_x86_model_spec op_p4_spec;
-extern struct op_x86_model_spec const op_p4_ht2_spec;
+extern struct op_x86_model_spec op_p4_ht2_spec;
-extern struct op_x86_model_spec const op_amd_spec;
+extern struct op_x86_model_spec op_amd_spec;
 extern struct op_x86_model_spec op_arch_perfmon_spec;
-extern void arch_perfmon_setup_counters(void);
 #endif /* OP_X86_MODEL_H */
diff --git a/arch/x86/pci/direct.c b/arch/x86/pci/direct.c
index bd13c3e4c6db..347d882b3bb3 100644
--- a/arch/x86/pci/direct.c
+++ b/arch/x86/pci/direct.c
@@ -192,13 +192,14 @@ struct pci_raw_ops pci_direct_conf2 = {
 static int __init pci_sanity_check(struct pci_raw_ops *o)
 {
        u32 x = 0;
-        int devfn;
+        int year, devfn;
        if (pci_probe & PCI_NO_CHECKS)
                return 1;
        /* Assume Type 1 works for newer systems.
           This handles machines that don't have anything on PCI Bus 0. */
-        if (dmi_get_year(DMI_BIOS_DATE) >= 2001)
+        dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL);
+        if (year >= 2001)
                return 1;
        for (devfn = 0; devfn < 0x100; devfn++) {
diff --git a/arch/x86/xen/Makefile b/arch/x86/xen/Makefile
index 7410640db173..3bb4fc21f4f2 100644
--- a/arch/x86/xen/Makefile
+++ b/arch/x86/xen/Makefile
@@ -8,6 +8,7 @@ endif
 # Make sure early boot has no stackprotector
 nostackp := $(call cc-option, -fno-stack-protector)
 CFLAGS_enlighten.o              := $(nostackp)
+CFLAGS_mmu.o                    := $(nostackp)
 obj-y           := enlighten.o setup.o multicalls.o mmu.o irq.o \
                        time.o xen-asm.o xen-asm_$(BITS).o \
@@ -16,3 +17,4 @@ obj-y		:= enlighten.o setup.o multicalls.o mmu.o irq.o \
 obj-$(CONFIG_SMP)               += smp.o
 obj-$(CONFIG_PARAVIRT_SPINLOCKS)+= spinlock.o
 obj-$(CONFIG_XEN_DEBUG_FS)      += debugfs.o
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index eb33aaa8415d..0dd0c2c6cae0 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -51,6 +51,7 @@
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 #include <asm/reboot.h>
+#include <asm/stackprotector.h>
 #include "xen-ops.h"
 #include "mmu.h"
@@ -330,18 +331,28 @@ static void xen_load_gdt(const struct desc_ptr *dtr)
        unsigned long frames[pages];
        int f;
-        /* A GDT can be up to 64k in size, which corresponds to 8192
+        /*
-           8-byte entries, or 16 4k pages.. */
+         * A GDT can be up to 64k in size, which corresponds to 8192
+         * 8-byte entries, or 16 4k pages..
+         */
        BUG_ON(size > 65536);
        BUG_ON(va & ~PAGE_MASK);
        for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
                int level;
-                pte_t *ptep = lookup_address(va, &level);
+                pte_t *ptep;
                unsigned long pfn, mfn;
                void *virt;
+                /*
+                 * The GDT is per-cpu and is in the percpu data area.
+                 * That can be virtually mapped, so we need to do a
+                 * page-walk to get the underlying MFN for the
+                 * hypercall.  The page can also be in the kernel's
+                 * linear range, so we need to RO that mapping too.
+                 */
+                ptep = lookup_address(va, &level);
                BUG_ON(ptep == NULL);
                pfn = pte_pfn(*ptep);
@@ -358,6 +369,44 @@ static void xen_load_gdt(const struct desc_ptr *dtr)
                BUG();
 }
+/*
+ * load_gdt for early boot, when the gdt is only mapped once
+ */
+static __init void xen_load_gdt_boot(const struct desc_ptr *dtr)
+{
+        unsigned long va = dtr->address;
+        unsigned int size = dtr->size + 1;
+        unsigned pages = (size + PAGE_SIZE - 1) / PAGE_SIZE;
+        unsigned long frames[pages];
+        int f;
+        /*
+         * A GDT can be up to 64k in size, which corresponds to 8192
+         * 8-byte entries, or 16 4k pages..
+         */
+        BUG_ON(size > 65536);
+        BUG_ON(va & ~PAGE_MASK);
+        for (f = 0; va < dtr->address + size; va += PAGE_SIZE, f++) {
+                pte_t pte;
+                unsigned long pfn, mfn;
+                pfn = virt_to_pfn(va);
+                mfn = pfn_to_mfn(pfn);
+                pte = pfn_pte(pfn, PAGE_KERNEL_RO);
+                if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0))
+                        BUG();
+                frames[f] = mfn;
+        }
+        if (HYPERVISOR_set_gdt(frames, size / sizeof(struct desc_struct)))
+                BUG();
+}
 static void load_TLS_descriptor(struct thread_struct *t,
                                unsigned int cpu, unsigned int i)
 {
@@ -581,6 +630,29 @@ static void xen_write_gdt_entry(struct desc_struct *dt, int entry,
        preempt_enable();
 }
+/*
+ * Version of write_gdt_entry for use at early boot-time needed to
+ * update an entry as simply as possible.
+ */
+static __init void xen_write_gdt_entry_boot(struct desc_struct *dt, int entry,
+                                            const void *desc, int type)
+{
+        switch (type) {
+        case DESC_LDT:
+        case DESC_TSS:
+                /* ignore */
+                break;
+        default: {
+                xmaddr_t maddr = virt_to_machine(&dt[entry]);
+                if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc))
+                        dt[entry] = *(struct desc_struct *)desc;
+        }
+        }
+}
 static void xen_load_sp0(struct tss_struct *tss,
                         struct thread_struct *thread)
 {
@@ -714,7 +786,7 @@ static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
        set:
                base = ((u64)high << 32) | low;
                if (HYPERVISOR_set_segment_base(which, base) != 0)
-                        ret = -EFAULT;
+                        ret = -EIO;
                break;
 #endif
@@ -965,6 +1037,23 @@ static const struct machine_ops __initdata xen_machine_ops = {
        .emergency_restart = xen_emergency_restart,
 };
+/*
+ * Set up the GDT and segment registers for -fstack-protector.  Until
+ * we do this, we have to be careful not to call any stack-protected
+ * function, which is most of the kernel.
+ */
+static void __init xen_setup_stackprotector(void)
+{
+        pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry_boot;
+        pv_cpu_ops.load_gdt = xen_load_gdt_boot;
+        setup_stack_canary_segment(0);
+        switch_to_new_gdt(0);
+        pv_cpu_ops.write_gdt_entry = xen_write_gdt_entry;
+        pv_cpu_ops.load_gdt = xen_load_gdt;
+}
 /* First C function to be called on Xen boot */
 asmlinkage void __init xen_start_kernel(void)
 {
@@ -983,13 +1072,28 @@ asmlinkage void __init xen_start_kernel(void)
        pv_apic_ops = xen_apic_ops;
        pv_mmu_ops = xen_mmu_ops;
-#ifdef CONFIG_X86_64
        /*
-         * Setup percpu state.  We only need to do this for 64-bit
+         * Set up some pagetable state before starting to set any ptes.
-         * because 32-bit already has %fs set properly.
         */
-        load_percpu_segment(0);
-#endif
+        /* Prevent unwanted bits from being set in PTEs. */
+        __supported_pte_mask &= ~_PAGE_GLOBAL;
+        if (!xen_initial_domain())
+                __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
+        __supported_pte_mask |= _PAGE_IOMAP;
+        xen_setup_features();
+        /* Get mfn list */
+        if (!xen_feature(XENFEAT_auto_translated_physmap))
+                xen_build_dynamic_phys_to_machine();
+        /*
+         * Set up kernel GDT and segment registers, mainly so that
+         * -fstack-protector code can be executed.
+         */
+        xen_setup_stackprotector();
        xen_init_irq_ops();
        xen_init_cpuid_mask();
@@ -1001,8 +1105,6 @@ asmlinkage void __init xen_start_kernel(void)
        set_xen_basic_apic_ops();
 #endif
-        xen_setup_features();
        if (xen_feature(XENFEAT_mmu_pt_update_preserve_ad)) {
                pv_mmu_ops.ptep_modify_prot_start = xen_ptep_modify_prot_start;
                pv_mmu_ops.ptep_modify_prot_commit = xen_ptep_modify_prot_commit;
@@ -1019,17 +1121,8 @@ asmlinkage void __init xen_start_kernel(void)
        xen_smp_init();
-        /* Get mfn list */
-        if (!xen_feature(XENFEAT_auto_translated_physmap))
-                xen_build_dynamic_phys_to_machine();
        pgd = (pgd_t *)xen_start_info->pt_base;
-        /* Prevent unwanted bits from being set in PTEs. */
-        __supported_pte_mask &= ~_PAGE_GLOBAL;
-        if (!xen_initial_domain())
-                __supported_pte_mask &= ~(_PAGE_PWT | _PAGE_PCD);
 #ifdef CONFIG_X86_64
        /* Work out if we support NX */
        check_efer();
diff --git a/arch/x86/xen/smp.c b/arch/x86/xen/smp.c
index 429834ec1687..fe03eeed7b48 100644
--- a/arch/x86/xen/smp.c
+++ b/arch/x86/xen/smp.c
@@ -236,6 +236,7 @@ cpu_initialize_context(unsigned int cpu, struct task_struct *idle)
        ctxt->user_regs.ss = __KERNEL_DS;
 #ifdef CONFIG_X86_32
        ctxt->user_regs.fs = __KERNEL_PERCPU;
+        ctxt->user_regs.gs = __KERNEL_STACK_CANARY;
 #else
        ctxt->gs_base_kernel = per_cpu_offset(cpu);
 #endif
diff --git a/arch/x86/xen/spinlock.c b/arch/x86/xen/spinlock.c
index 5601506f2dd9..36a5141108df 100644
--- a/arch/x86/xen/spinlock.c
+++ b/arch/x86/xen/spinlock.c
@@ -187,7 +187,6 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
        struct xen_spinlock *prev;
        int irq = __get_cpu_var(lock_kicker_irq);
        int ret;
-        unsigned long flags;
        u64 start;
        /* If kicker interrupts not initialized yet, just spin */
@@ -199,16 +198,12 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
        /* announce we're spinning */
        prev = spinning_lock(xl);
-        flags = __raw_local_save_flags();
-        if (irq_enable) {
-                ADD_STATS(taken_slow_irqenable, 1);
-                raw_local_irq_enable();
-        }
        ADD_STATS(taken_slow, 1);
        ADD_STATS(taken_slow_nested, prev != NULL);
        do {
+                unsigned long flags;
                /* clear pending */
                xen_clear_irq_pending(irq);
@@ -228,6 +223,12 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
                        goto out;
                }
+                flags = __raw_local_save_flags();
+                if (irq_enable) {
+                        ADD_STATS(taken_slow_irqenable, 1);
+                        raw_local_irq_enable();
+                }
                /*
                 * Block until irq becomes pending.  If we're
                 * interrupted at this point (after the trylock but
@@ -238,13 +239,15 @@ static noinline int xen_spin_lock_slow(struct raw_spinlock *lock, bool irq_enabl
                 * pending.
                 */
                xen_poll_irq(irq);
+                raw_local_irq_restore(flags);
                ADD_STATS(taken_slow_spurious, !xen_test_irq_pending(irq));
        } while (!xen_test_irq_pending(irq)); /* check for spurious wakeups */
        kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq));
 out:
-        raw_local_irq_restore(flags);
        unspinning_lock(xl, prev);
        spin_time_accum_blocked(start);
@@ -323,8 +326,13 @@ static void xen_spin_unlock(struct raw_spinlock *lock)
        smp_wmb();              /* make sure no writes get moved after unlock */
        xl->lock = 0;           /* release lock */
-        /* make sure unlock happens before kick */
+        /*
-        barrier();
+         * Make sure unlock happens before checking for waiting
+         * spinners.  We need a strong barrier to enforce the
+         * write-read ordering to different memory locations, as the
+         * CPU makes no implied guarantees about their ordering.
+         */
+        mb();
        if (unlikely(xl->spinners))
                xen_spin_unlock_slow(xl);
diff --git a/arch/xtensa/include/asm/socket.h b/arch/xtensa/include/asm/socket.h
index dd1a7a4a1cea..beb3a6bdb61d 100644
--- a/arch/xtensa/include/asm/socket.h
+++ b/arch/xtensa/include/asm/socket.h
@@ -68,4 +68,7 @@
 #define SO_TIMESTAMPING         37
 #define SCM_TIMESTAMPING        SO_TIMESTAMPING
+#define SO_PROTOCOL             38
+#define SO_DOMAIN               39
 #endif  /* _XTENSA_SOCKET_H */
diff --git a/arch/xtensa/platforms/iss/network.c b/arch/xtensa/platforms/iss/network.c
index edad4156d89a..2f0b86b37cf9 100644
--- a/arch/xtensa/platforms/iss/network.c
+++ b/arch/xtensa/platforms/iss/network.c
@@ -545,7 +545,7 @@ static int iss_net_start_xmit(struct sk_buff *skb, struct net_device *dev)
        spin_unlock_irqrestore(&lp->lock, flags);
        dev_kfree_skb(skb);
-        return 0;
+        return NETDEV_TX_OK;
 }
author	Ingo Molnar <mingo@elte.hu>	2009-09-15 06:18:15 -0400
committer	Ingo Molnar <mingo@elte.hu>	2009-09-15 06:18:15 -0400
commit	dca2d6ac09d9ef59ff46820d4f0c94b08a671202 (patch)
tree	fdec753b842dad09e3a4151954fab3eb5c43500d /arch
parent	d6a65dffb30d8636b1e5d4c201564ef401a246cf (diff)
parent	18240904960a39e582ced8ba8ececb10b8c22dd3 (diff)