powerpc: sysdev/xilinx_intc irq_data conversion.

Signed-off-by: Lennert Buytenhek <buytenh@secretlab.ca>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

1 files changed, 25 insertions, 23 deletions

diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index 1e0ccfaf403e..7436f3ed4df6 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -69,17 +69,17 @@ static unsigned char xilinx_intc_map_senses[] = {
  *
  * IRQ Chip common (across level and edge) operations
  */
-static void xilinx_intc_mask(unsigned int virq)
+static void xilinx_intc_mask(struct irq_data *d)
 {
-        int irq = virq_to_hw(virq);
-        void * regs = get_irq_chip_data(virq);
+        int irq = virq_to_hw(d->irq);
+        void * regs = irq_data_get_irq_chip_data(d);
         pr_debug("mask: %d\n", irq);
         out_be32(regs + XINTC_CIE, 1 << irq);
 }
 
-static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type)
+static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        struct irq_desc *desc = irq_to_desc(virq);
+        struct irq_desc *desc = irq_to_desc(d->irq);
 
         desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
         desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
@@ -91,10 +91,10 @@ static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type)
 /*
  * IRQ Chip level operations
  */
-static void xilinx_intc_level_unmask(unsigned int virq)
+static void xilinx_intc_level_unmask(struct irq_data *d)
 {
-        int irq = virq_to_hw(virq);
-        void * regs = get_irq_chip_data(virq);
+        int irq = virq_to_hw(d->irq);
+        void * regs = irq_data_get_irq_chip_data(d);
         pr_debug("unmask: %d\n", irq);
         out_be32(regs + XINTC_SIE, 1 << irq);
 
@@ -107,37 +107,37 @@ static void xilinx_intc_level_unmask(unsigned int virq)
 
 static struct irq_chip xilinx_intc_level_irqchip = {
         .name = "Xilinx Level INTC",
-        .mask = xilinx_intc_mask,
-        .mask_ack = xilinx_intc_mask,
-        .unmask = xilinx_intc_level_unmask,
-        .set_type = xilinx_intc_set_type,
+        .irq_mask = xilinx_intc_mask,
+        .irq_mask_ack = xilinx_intc_mask,
+        .irq_unmask = xilinx_intc_level_unmask,
+        .irq_set_type = xilinx_intc_set_type,
 };
 
 /*
  * IRQ Chip edge operations
  */
-static void xilinx_intc_edge_unmask(unsigned int virq)
+static void xilinx_intc_edge_unmask(struct irq_data *d)
 {
-        int irq = virq_to_hw(virq);
-        void *regs = get_irq_chip_data(virq);
+        int irq = virq_to_hw(d->irq);
+        void *regs = irq_data_get_irq_chip_data(d);
         pr_debug("unmask: %d\n", irq);
         out_be32(regs + XINTC_SIE, 1 << irq);
 }
 
-static void xilinx_intc_edge_ack(unsigned int virq)
+static void xilinx_intc_edge_ack(struct irq_data *d)
 {
-        int irq = virq_to_hw(virq);
-        void * regs = get_irq_chip_data(virq);
+        int irq = virq_to_hw(d->irq);
+        void * regs = irq_data_get_irq_chip_data(d);
         pr_debug("ack: %d\n", irq);
         out_be32(regs + XINTC_IAR, 1 << irq);
 }
 
 static struct irq_chip xilinx_intc_edge_irqchip = {
         .name = "Xilinx Edge  INTC",
-        .mask = xilinx_intc_mask,
-        .unmask = xilinx_intc_edge_unmask,
-        .ack = xilinx_intc_edge_ack,
-        .set_type = xilinx_intc_set_type,
+        .irq_mask = xilinx_intc_mask,
+        .irq_unmask = xilinx_intc_edge_unmask,
+        .irq_ack = xilinx_intc_edge_ack,
+        .irq_set_type = xilinx_intc_set_type,
 };
 
 /*
@@ -229,12 +229,14 @@ int xilinx_intc_get_irq(void)
  */
 static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
 {
+        struct irq_chip *chip = get_irq_desc_chip(desc);
         unsigned int cascade_irq = i8259_irq();
+
         if (cascade_irq)
                 generic_handle_irq(cascade_irq);
 
         /* Let xilinx_intc end the interrupt */
-        desc->chip->unmask(irq);
+        chip->irq_unmask(&desc->irq_data);
 }
 
 static void __init xilinx_i8259_setup_cascade(void)