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authorJesper Nilsson <jesper.nilsson@axis.com>2008-01-25 12:00:48 -0500
committerJesper Nilsson <jesper.nilsson@axis.com>2008-02-08 05:06:36 -0500
commit0836c6d26f3512db5fa9698376846c5cec4fae13 (patch)
treed669cafbfa971c411f2742f7d7ef07b03300d846 /arch
parentea0af95b1c7e17541365b555a43f5e8d51ef3dff (diff)
CRIS v32: Change name of simulator config to CONFIG_ETRAX_VCS_SIM in mm/init.c
- Remove unneded code for ETRAX FS and ARTPEC-3
Diffstat (limited to 'arch')
-rw-r--r--arch/cris/arch-v32/mm/init.c8
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/cris/arch-v32/mm/init.c b/arch/cris/arch-v32/mm/init.c
index a84ba7ff22d2..5a9ac5834647 100644
--- a/arch/cris/arch-v32/mm/init.c
+++ b/arch/cris/arch-v32/mm/init.c
@@ -65,7 +65,7 @@ cris_mmu_init(void)
65 REG_STATE(mmu, rw_mm_cfg, seg_d, page) | 65 REG_STATE(mmu, rw_mm_cfg, seg_d, page) |
66 REG_STATE(mmu, rw_mm_cfg, seg_c, linear) | 66 REG_STATE(mmu, rw_mm_cfg, seg_c, linear) |
67 REG_STATE(mmu, rw_mm_cfg, seg_b, linear) | 67 REG_STATE(mmu, rw_mm_cfg, seg_b, linear) |
68#ifndef CONFIG_ETRAXFS_SIM 68#ifndef CONFIG_ETRAX_VCS_SIM
69 REG_STATE(mmu, rw_mm_cfg, seg_a, page) | 69 REG_STATE(mmu, rw_mm_cfg, seg_a, page) |
70#else 70#else
71 REG_STATE(mmu, rw_mm_cfg, seg_a, linear) | 71 REG_STATE(mmu, rw_mm_cfg, seg_a, linear) |
@@ -84,13 +84,9 @@ cris_mmu_init(void)
84 mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) | 84 mmu_kbase_hi = ( REG_FIELD(mmu, rw_mm_kbase_hi, base_f, 0x0) |
85 REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) | 85 REG_FIELD(mmu, rw_mm_kbase_hi, base_e, 0x8) |
86 REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) | 86 REG_FIELD(mmu, rw_mm_kbase_hi, base_d, 0x0) |
87#ifndef CONFIG_ETRAXFS_SIM
88 REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) | 87 REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x4) |
89#else
90 REG_FIELD(mmu, rw_mm_kbase_hi, base_c, 0x0) |
91#endif
92 REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) | 88 REG_FIELD(mmu, rw_mm_kbase_hi, base_b, 0xb) |
93#ifndef CONFIG_ETRAXFS_SIM 89#ifndef CONFIG_ETRAX_VCS_SIM
94 REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) | 90 REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0x0) |
95#else 91#else
96 REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa) | 92 REG_FIELD(mmu, rw_mm_kbase_hi, base_a, 0xa) |