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authorRussell King <rmk+kernel@arm.linux.org.uk>2010-10-28 15:14:38 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2010-10-28 15:14:38 -0400
commitb3773301c4290f054aa2aa5379e59a1bf4f78bdf (patch)
treeaac1619d32800393b587bf034c7dadb9e3c24f7b /arch
parentbe6786ac738801d39cfd264ec88c352efd029578 (diff)
parent1a0b1eac5012326e52d1dcf78695ac08f41c37d7 (diff)
Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/genesis-2.6 into devel-stable
Conflicts: drivers/video/sh_mobile_hdmi.c
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c326
-rw-r--r--arch/arm/mach-shmobile/clock-sh7367.c2
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c78
-rw-r--r--arch/arm/mach-shmobile/clock-sh7377.c2
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h10
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c28
-rw-r--r--arch/arm/mach-shmobile/pfc-sh7372.c8
-rw-r--r--arch/arm/mach-shmobile/setup-sh7367.c1
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c94
-rw-r--r--arch/arm/mach-shmobile/setup-sh7377.c1
-rw-r--r--arch/sh/boards/mach-ap325rxa/setup.c29
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c60
-rw-r--r--arch/sh/boards/mach-kfr2r09/setup.c29
-rw-r--r--arch/sh/boards/mach-migor/setup.c58
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c54
15 files changed, 527 insertions, 253 deletions
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 14923989ea05..f5d55efda386 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -30,7 +30,6 @@
30#include <linux/mtd/mtd.h> 30#include <linux/mtd/mtd.h>
31#include <linux/mtd/partitions.h> 31#include <linux/mtd/partitions.h>
32#include <linux/mtd/physmap.h> 32#include <linux/mtd/physmap.h>
33#include <linux/mmc/host.h>
34#include <linux/mmc/sh_mmcif.h> 33#include <linux/mmc/sh_mmcif.h>
35#include <linux/i2c.h> 34#include <linux/i2c.h>
36#include <linux/i2c/tsc2007.h> 35#include <linux/i2c/tsc2007.h>
@@ -44,6 +43,10 @@
44#include <linux/input/sh_keysc.h> 43#include <linux/input/sh_keysc.h>
45#include <linux/usb/r8a66597.h> 44#include <linux/usb/r8a66597.h>
46 45
46#include <media/sh_mobile_ceu.h>
47#include <media/sh_mobile_csi2.h>
48#include <media/soc_camera.h>
49
47#include <sound/sh_fsi.h> 50#include <sound/sh_fsi.h>
48 51
49#include <video/sh_mobile_hdmi.h> 52#include <video/sh_mobile_hdmi.h>
@@ -238,7 +241,7 @@ static struct platform_device smc911x_device = {
238/* SH_MMCIF */ 241/* SH_MMCIF */
239static struct resource sh_mmcif_resources[] = { 242static struct resource sh_mmcif_resources[] = {
240 [0] = { 243 [0] = {
241 .name = "SH_MMCIF", 244 .name = "MMCIF",
242 .start = 0xE6BD0000, 245 .start = 0xE6BD0000,
243 .end = 0xE6BD00FF, 246 .end = 0xE6BD00FF,
244 .flags = IORESOURCE_MEM, 247 .flags = IORESOURCE_MEM,
@@ -375,10 +378,40 @@ static struct platform_device usb1_host_device = {
375 .resource = usb1_host_resources, 378 .resource = usb1_host_resources,
376}; 379};
377 380
381const static struct fb_videomode ap4evb_lcdc_modes[] = {
382 {
383#ifdef CONFIG_AP4EVB_QHD
384 .name = "R63302(QHD)",
385 .xres = 544,
386 .yres = 961,
387 .left_margin = 72,
388 .right_margin = 600,
389 .hsync_len = 16,
390 .upper_margin = 8,
391 .lower_margin = 8,
392 .vsync_len = 2,
393 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
394#else
395 .name = "WVGA Panel",
396 .xres = 800,
397 .yres = 480,
398 .left_margin = 220,
399 .right_margin = 110,
400 .hsync_len = 70,
401 .upper_margin = 20,
402 .lower_margin = 5,
403 .vsync_len = 5,
404 .sync = 0,
405#endif
406 },
407};
408
378static struct sh_mobile_lcdc_info lcdc_info = { 409static struct sh_mobile_lcdc_info lcdc_info = {
379 .ch[0] = { 410 .ch[0] = {
380 .chan = LCDC_CHAN_MAINLCD, 411 .chan = LCDC_CHAN_MAINLCD,
381 .bpp = 16, 412 .bpp = 16,
413 .lcd_cfg = ap4evb_lcdc_modes,
414 .num_cfg = ARRAY_SIZE(ap4evb_lcdc_modes),
382 } 415 }
383}; 416};
384 417
@@ -517,27 +550,6 @@ static struct platform_device *qhd_devices[] __initdata = {
517 550
518/* FSI */ 551/* FSI */
519#define IRQ_FSI evt2irq(0x1840) 552#define IRQ_FSI evt2irq(0x1840)
520#define FSIACKCR 0xE6150018
521static void fsiackcr_init(struct clk *clk)
522{
523 u32 status = __raw_readl(clk->enable_reg);
524
525 /* use external clock */
526 status &= ~0x000000ff;
527 status |= 0x00000080;
528 __raw_writel(status, clk->enable_reg);
529}
530
531static struct clk_ops fsiackcr_clk_ops = {
532 .init = fsiackcr_init,
533};
534
535static struct clk fsiackcr_clk = {
536 .ops = &fsiackcr_clk_ops,
537 .enable_reg = (void __iomem *)FSIACKCR,
538 .rate = 0, /* unknown */
539};
540
541static struct sh_fsi_platform_info fsi_info = { 553static struct sh_fsi_platform_info fsi_info = {
542 .porta_flags = SH_FSI_BRS_INV | 554 .porta_flags = SH_FSI_BRS_INV |
543 SH_FSI_OUT_SLAVE_MODE | 555 SH_FSI_OUT_SLAVE_MODE |
@@ -577,26 +589,6 @@ static struct sh_mobile_lcdc_info sh_mobile_lcdc1_info = {
577 .interface_type = RGB24, 589 .interface_type = RGB24,
578 .clock_divider = 1, 590 .clock_divider = 1,
579 .flags = LCDC_FLAGS_DWPOL, 591 .flags = LCDC_FLAGS_DWPOL,
580 .lcd_cfg = {
581 .name = "HDMI",
582 /* So far only 720p is supported */
583 .xres = 1280,
584 .yres = 720,
585 /*
586 * If left and right margins are not multiples of 8,
587 * LDHAJR will be adjusted accordingly by the LCDC
588 * driver. Until we start using EDID, these values
589 * might have to be adjusted for different monitors.
590 */
591 .left_margin = 200,
592 .right_margin = 88,
593 .hsync_len = 48,
594 .upper_margin = 20,
595 .lower_margin = 5,
596 .vsync_len = 5,
597 .pixclock = 13468,
598 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
599 },
600 } 592 }
601}; 593};
602 594
@@ -608,7 +600,7 @@ static struct resource lcdc1_resources[] = {
608 .flags = IORESOURCE_MEM, 600 .flags = IORESOURCE_MEM,
609 }, 601 },
610 [1] = { 602 [1] = {
611 .start = intcs_evt2irq(0x17a0), 603 .start = intcs_evt2irq(0x1780),
612 .flags = IORESOURCE_IRQ, 604 .flags = IORESOURCE_IRQ,
613 }, 605 },
614}; 606};
@@ -689,6 +681,95 @@ static struct platform_device leds_device = {
689 }, 681 },
690}; 682};
691 683
684static struct i2c_board_info imx074_info = {
685 I2C_BOARD_INFO("imx074", 0x1a),
686};
687
688struct soc_camera_link imx074_link = {
689 .bus_id = 0,
690 .board_info = &imx074_info,
691 .i2c_adapter_id = 0,
692 .module_name = "imx074",
693};
694
695static struct platform_device ap4evb_camera = {
696 .name = "soc-camera-pdrv",
697 .id = 0,
698 .dev = {
699 .platform_data = &imx074_link,
700 },
701};
702
703static struct sh_csi2_client_config csi2_clients[] = {
704 {
705 .phy = SH_CSI2_PHY_MAIN,
706 .lanes = 3,
707 .channel = 0,
708 .pdev = &ap4evb_camera,
709 },
710};
711
712static struct sh_csi2_pdata csi2_info = {
713 .type = SH_CSI2C,
714 .clients = csi2_clients,
715 .num_clients = ARRAY_SIZE(csi2_clients),
716 .flags = SH_CSI2_ECC | SH_CSI2_CRC,
717};
718
719static struct resource csi2_resources[] = {
720 [0] = {
721 .name = "CSI2",
722 .start = 0xffc90000,
723 .end = 0xffc90fff,
724 .flags = IORESOURCE_MEM,
725 },
726 [1] = {
727 .start = intcs_evt2irq(0x17a0),
728 .flags = IORESOURCE_IRQ,
729 },
730};
731
732static struct platform_device csi2_device = {
733 .name = "sh-mobile-csi2",
734 .id = 0,
735 .num_resources = ARRAY_SIZE(csi2_resources),
736 .resource = csi2_resources,
737 .dev = {
738 .platform_data = &csi2_info,
739 },
740};
741
742static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
743 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
744 .csi2_dev = &csi2_device.dev,
745};
746
747static struct resource ceu_resources[] = {
748 [0] = {
749 .name = "CEU",
750 .start = 0xfe910000,
751 .end = 0xfe91009f,
752 .flags = IORESOURCE_MEM,
753 },
754 [1] = {
755 .start = intcs_evt2irq(0x880),
756 .flags = IORESOURCE_IRQ,
757 },
758 [2] = {
759 /* place holder for contiguous memory */
760 },
761};
762
763static struct platform_device ceu_device = {
764 .name = "sh_mobile_ceu",
765 .id = 0, /* "ceu0" clock */
766 .num_resources = ARRAY_SIZE(ceu_resources),
767 .resource = ceu_resources,
768 .dev = {
769 .platform_data = &sh_mobile_ceu_info,
770 },
771};
772
692static struct platform_device *ap4evb_devices[] __initdata = { 773static struct platform_device *ap4evb_devices[] __initdata = {
693 &leds_device, 774 &leds_device,
694 &nor_flash_device, 775 &nor_flash_device,
@@ -701,6 +782,9 @@ static struct platform_device *ap4evb_devices[] __initdata = {
701 &lcdc1_device, 782 &lcdc1_device,
702 &lcdc_device, 783 &lcdc_device,
703 &hdmi_device, 784 &hdmi_device,
785 &csi2_device,
786 &ceu_device,
787 &ap4evb_camera,
704}; 788};
705 789
706static int __init hdmi_init_pm_clock(void) 790static int __init hdmi_init_pm_clock(void)
@@ -715,22 +799,22 @@ static int __init hdmi_init_pm_clock(void)
715 goto out; 799 goto out;
716 } 800 }
717 801
718 ret = clk_set_parent(&pllc2_clk, &dv_clki_div2_clk); 802 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
719 if (ret < 0) { 803 if (ret < 0) {
720 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, pllc2_clk.usecount); 804 pr_err("Cannot set PLLC2 parent: %d, %d users\n", ret, sh7372_pllc2_clk.usecount);
721 goto out; 805 goto out;
722 } 806 }
723 807
724 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&pllc2_clk)); 808 pr_debug("PLLC2 initial frequency %lu\n", clk_get_rate(&sh7372_pllc2_clk));
725 809
726 rate = clk_round_rate(&pllc2_clk, 594000000); 810 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
727 if (rate < 0) { 811 if (rate < 0) {
728 pr_err("Cannot get suitable rate: %ld\n", rate); 812 pr_err("Cannot get suitable rate: %ld\n", rate);
729 ret = rate; 813 ret = rate;
730 goto out; 814 goto out;
731 } 815 }
732 816
733 ret = clk_set_rate(&pllc2_clk, rate); 817 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
734 if (ret < 0) { 818 if (ret < 0) {
735 pr_err("Cannot set rate %ld: %d\n", rate, ret); 819 pr_err("Cannot set rate %ld: %d\n", rate, ret);
736 goto out; 820 goto out;
@@ -738,7 +822,7 @@ static int __init hdmi_init_pm_clock(void)
738 822
739 pr_debug("PLLC2 set frequency %lu\n", rate); 823 pr_debug("PLLC2 set frequency %lu\n", rate);
740 824
741 ret = clk_set_parent(hdmi_ick, &pllc2_clk); 825 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
742 if (ret < 0) { 826 if (ret < 0) {
743 pr_err("Cannot set HDMI parent: %d\n", ret); 827 pr_err("Cannot set HDMI parent: %d\n", ret);
744 goto out; 828 goto out;
@@ -752,11 +836,51 @@ out:
752 836
753device_initcall(hdmi_init_pm_clock); 837device_initcall(hdmi_init_pm_clock);
754 838
839#define FSIACK_DUMMY_RATE 48000
840static int __init fsi_init_pm_clock(void)
841{
842 struct clk *fsia_ick;
843 int ret;
844
845 /*
846 * FSIACK is connected to AK4642,
847 * and the rate is depend on playing sound rate.
848 * So, set dummy rate (= 48k) here
849 */
850 ret = clk_set_rate(&sh7372_fsiack_clk, FSIACK_DUMMY_RATE);
851 if (ret < 0) {
852 pr_err("Cannot set FSIACK dummy rate: %d\n", ret);
853 return ret;
854 }
855
856 fsia_ick = clk_get(&fsi_device.dev, "icka");
857 if (IS_ERR(fsia_ick)) {
858 ret = PTR_ERR(fsia_ick);
859 pr_err("Cannot get FSI ICK: %d\n", ret);
860 return ret;
861 }
862
863 ret = clk_set_parent(fsia_ick, &sh7372_fsiack_clk);
864 if (ret < 0) {
865 pr_err("Cannot set FSI-A parent: %d\n", ret);
866 goto out;
867 }
868
869 ret = clk_set_rate(fsia_ick, FSIACK_DUMMY_RATE);
870 if (ret < 0)
871 pr_err("Cannot set FSI-A rate: %d\n", ret);
872
873out:
874 clk_put(fsia_ick);
875
876 return ret;
877}
878device_initcall(fsi_init_pm_clock);
879
755/* 880/*
756 * FIXME !! 881 * FIXME !!
757 * 882 *
758 * gpio_no_direction 883 * gpio_no_direction
759 * gpio_pull_up
760 * are quick_hack. 884 * are quick_hack.
761 * 885 *
762 * current gpio frame work doesn't have 886 * current gpio frame work doesn't have
@@ -768,49 +892,37 @@ static void __init gpio_no_direction(u32 addr)
768 __raw_writeb(0x00, addr); 892 __raw_writeb(0x00, addr);
769} 893}
770 894
771static void __init gpio_pull_up(u32 addr)
772{
773 u8 data = __raw_readb(addr);
774
775 data &= 0x0F;
776 data |= 0xC0;
777 __raw_writeb(data, addr);
778}
779
780/* TouchScreen */ 895/* TouchScreen */
896#ifdef CONFIG_AP4EVB_QHD
897# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
898# define GPIO_TSC_PORT GPIO_PORT123
899#else /* WVGA */
900# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
901# define GPIO_TSC_PORT GPIO_PORT40
902#endif
903
781#define IRQ28 evt2irq(0x3380) /* IRQ28A */ 904#define IRQ28 evt2irq(0x3380) /* IRQ28A */
782#define IRQ7 evt2irq(0x02e0) /* IRQ7A */ 905#define IRQ7 evt2irq(0x02e0) /* IRQ7A */
783static int ts_get_pendown_state(void) 906static int ts_get_pendown_state(void)
784{ 907{
785 int val1, val2; 908 int val;
786 909
787 gpio_free(GPIO_FN_IRQ28_123); 910 gpio_free(GPIO_TSC_IRQ);
788 gpio_free(GPIO_FN_IRQ7_40);
789 911
790 gpio_request(GPIO_PORT123, NULL); 912 gpio_request(GPIO_TSC_PORT, NULL);
791 gpio_request(GPIO_PORT40, NULL);
792 913
793 gpio_direction_input(GPIO_PORT123); 914 gpio_direction_input(GPIO_TSC_PORT);
794 gpio_direction_input(GPIO_PORT40);
795 915
796 val1 = gpio_get_value(GPIO_PORT123); 916 val = gpio_get_value(GPIO_TSC_PORT);
797 val2 = gpio_get_value(GPIO_PORT40);
798 917
799 gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */ 918 gpio_request(GPIO_TSC_IRQ, NULL);
800 gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */
801 919
802 return val1 ^ val2; 920 return !val;
803} 921}
804 922
805#define PORT40CR 0xE6051028
806#define PORT123CR 0xE605007B
807static int ts_init(void) 923static int ts_init(void)
808{ 924{
809 gpio_request(GPIO_FN_IRQ28_123, NULL); /* for QHD */ 925 gpio_request(GPIO_TSC_IRQ, NULL);
810 gpio_request(GPIO_FN_IRQ7_40, NULL); /* for WVGA */
811
812 gpio_pull_up(PORT40CR);
813 gpio_pull_up(PORT123CR);
814 926
815 return 0; 927 return 0;
816} 928}
@@ -955,14 +1067,6 @@ static void __init ap4evb_init(void)
955 clk_put(clk); 1067 clk_put(clk);
956 } 1068 }
957 1069
958 /* change parent of FSI A */
959 clk = clk_get(NULL, "fsia_clk");
960 if (!IS_ERR(clk)) {
961 clk_register(&fsiackcr_clk);
962 clk_set_parent(clk, &fsiackcr_clk);
963 clk_put(clk);
964 }
965
966 /* 1070 /*
967 * set irq priority, to avoid sound chopping 1071 * set irq priority, to avoid sound chopping
968 * when NFS rootfs is used 1072 * when NFS rootfs is used
@@ -977,8 +1081,10 @@ static void __init ap4evb_init(void)
977 ARRAY_SIZE(i2c1_devices)); 1081 ARRAY_SIZE(i2c1_devices));
978 1082
979#ifdef CONFIG_AP4EVB_QHD 1083#ifdef CONFIG_AP4EVB_QHD
1084
980 /* 1085 /*
981 * QHD 1086 * For QHD Panel (MIPI-DSI, CONFIG_AP4EVB_QHD=y) and
1087 * IRQ28 for Touch Panel, set dip switches S3, S43 as OFF, ON.
982 */ 1088 */
983 1089
984 /* enable KEYSC */ 1090 /* enable KEYSC */
@@ -1004,17 +1110,6 @@ static void __init ap4evb_init(void)
1004 lcdc_info.ch[0].interface_type = RGB24; 1110 lcdc_info.ch[0].interface_type = RGB24;
1005 lcdc_info.ch[0].clock_divider = 1; 1111 lcdc_info.ch[0].clock_divider = 1;
1006 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; 1112 lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL;
1007 lcdc_info.ch[0].lcd_cfg.name = "R63302(QHD)";
1008 lcdc_info.ch[0].lcd_cfg.xres = 544;
1009 lcdc_info.ch[0].lcd_cfg.yres = 961;
1010 lcdc_info.ch[0].lcd_cfg.left_margin = 72;
1011 lcdc_info.ch[0].lcd_cfg.right_margin = 600;
1012 lcdc_info.ch[0].lcd_cfg.hsync_len = 16;
1013 lcdc_info.ch[0].lcd_cfg.upper_margin = 8;
1014 lcdc_info.ch[0].lcd_cfg.lower_margin = 8;
1015 lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
1016 lcdc_info.ch[0].lcd_cfg.sync = FB_SYNC_VERT_HIGH_ACT |
1017 FB_SYNC_HOR_HIGH_ACT;
1018 lcdc_info.ch[0].lcd_size_cfg.width = 44; 1113 lcdc_info.ch[0].lcd_size_cfg.width = 44;
1019 lcdc_info.ch[0].lcd_size_cfg.height = 79; 1114 lcdc_info.ch[0].lcd_size_cfg.height = 79;
1020 1115
@@ -1022,8 +1117,10 @@ static void __init ap4evb_init(void)
1022 1117
1023#else 1118#else
1024 /* 1119 /*
1025 * WVGA 1120 * For WVGA Panel (18-bit RGB, CONFIG_AP4EVB_WVGA=y) and
1121 * IRQ7 for Touch Panel, set dip switches S3, S43 to ON, OFF.
1026 */ 1122 */
1123
1027 gpio_request(GPIO_FN_LCDD17, NULL); 1124 gpio_request(GPIO_FN_LCDD17, NULL);
1028 gpio_request(GPIO_FN_LCDD16, NULL); 1125 gpio_request(GPIO_FN_LCDD16, NULL);
1029 gpio_request(GPIO_FN_LCDD15, NULL); 1126 gpio_request(GPIO_FN_LCDD15, NULL);
@@ -1055,16 +1152,6 @@ static void __init ap4evb_init(void)
1055 lcdc_info.ch[0].interface_type = RGB18; 1152 lcdc_info.ch[0].interface_type = RGB18;
1056 lcdc_info.ch[0].clock_divider = 2; 1153 lcdc_info.ch[0].clock_divider = 2;
1057 lcdc_info.ch[0].flags = 0; 1154 lcdc_info.ch[0].flags = 0;
1058 lcdc_info.ch[0].lcd_cfg.name = "WVGA Panel";
1059 lcdc_info.ch[0].lcd_cfg.xres = 800;
1060 lcdc_info.ch[0].lcd_cfg.yres = 480;
1061 lcdc_info.ch[0].lcd_cfg.left_margin = 220;
1062 lcdc_info.ch[0].lcd_cfg.right_margin = 110;
1063 lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
1064 lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
1065 lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
1066 lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
1067 lcdc_info.ch[0].lcd_cfg.sync = 0;
1068 lcdc_info.ch[0].lcd_size_cfg.width = 152; 1155 lcdc_info.ch[0].lcd_size_cfg.width = 152;
1069 lcdc_info.ch[0].lcd_size_cfg.height = 91; 1156 lcdc_info.ch[0].lcd_size_cfg.height = 91;
1070 1157
@@ -1075,6 +1162,23 @@ static void __init ap4evb_init(void)
1075 i2c_register_board_info(0, &tsc_device, 1); 1162 i2c_register_board_info(0, &tsc_device, 1);
1076#endif /* CONFIG_AP4EVB_QHD */ 1163#endif /* CONFIG_AP4EVB_QHD */
1077 1164
1165 /* CEU */
1166
1167 /*
1168 * TODO: reserve memory for V4L2 DMA buffers, when a suitable API
1169 * becomes available
1170 */
1171
1172 /* MIPI-CSI stuff */
1173 gpio_request(GPIO_FN_VIO_CKO, NULL);
1174
1175 clk = clk_get(NULL, "vck1_clk");
1176 if (!IS_ERR(clk)) {
1177 clk_set_rate(clk, clk_round_rate(clk, 13000000));
1178 clk_enable(clk);
1179 clk_put(clk);
1180 }
1181
1078 sh7372_add_standard_devices(); 1182 sh7372_add_standard_devices();
1079 1183
1080 /* HDMI */ 1184 /* HDMI */
@@ -1097,7 +1201,7 @@ static void __init ap4evb_timer_init(void)
1097 shmobile_timer.init(); 1201 shmobile_timer.init();
1098 1202
1099 /* External clock source */ 1203 /* External clock source */
1100 clk_set_rate(&dv_clki_clk, 27000000); 1204 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1101} 1205}
1102 1206
1103static struct sys_timer ap4evb_timer = { 1207static struct sys_timer ap4evb_timer = {
diff --git a/arch/arm/mach-shmobile/clock-sh7367.c b/arch/arm/mach-shmobile/clock-sh7367.c
index b6454c9f2abb..9f78729098f2 100644
--- a/arch/arm/mach-shmobile/clock-sh7367.c
+++ b/arch/arm/mach-shmobile/clock-sh7367.c
@@ -321,7 +321,7 @@ static struct clk_lookup lookups[] = {
321 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */ 321 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[SYMSTP001]), /* SCIFA3 */
322 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */ 322 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[SYMSTP000]), /* SCIFA4 */
323 CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */ 323 CLKDEV_DEV_ID("sh_siu", &mstp_clks[SYMSTP231]), /* SIU */
324 CLKDEV_CON_ID("cmt1", &mstp_clks[SYMSTP229]), /* CMT10 */ 324 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[SYMSTP229]), /* CMT10 */
325 CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */ 325 CLKDEV_DEV_ID("sh_irda", &mstp_clks[SYMSTP225]), /* IRDA */
326 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */ 326 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[SYMSTP223]), /* IIC1 */
327 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */ 327 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[SYMSTP222]), /* USBHS */
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 759468992ad2..8565aefa21fd 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -51,7 +51,7 @@
51#define SMSTPCR4 0xe6150140 51#define SMSTPCR4 0xe6150140
52 52
53/* Platforms must set frequency on their DV_CLKI pin */ 53/* Platforms must set frequency on their DV_CLKI pin */
54struct clk dv_clki_clk = { 54struct clk sh7372_dv_clki_clk = {
55}; 55};
56 56
57/* Fixed 32 KHz root clock from EXTALR pin */ 57/* Fixed 32 KHz root clock from EXTALR pin */
@@ -86,9 +86,9 @@ static struct clk_ops div2_clk_ops = {
86}; 86};
87 87
88/* Divide dv_clki by two */ 88/* Divide dv_clki by two */
89struct clk dv_clki_div2_clk = { 89struct clk sh7372_dv_clki_div2_clk = {
90 .ops = &div2_clk_ops, 90 .ops = &div2_clk_ops,
91 .parent = &dv_clki_clk, 91 .parent = &sh7372_dv_clki_clk,
92}; 92};
93 93
94/* Divide extal1 by two */ 94/* Divide extal1 by two */
@@ -150,7 +150,7 @@ static struct clk pllc1_div2_clk = {
150static struct clk *pllc2_parent[] = { 150static struct clk *pllc2_parent[] = {
151 [0] = &extal1_div2_clk, 151 [0] = &extal1_div2_clk,
152 [1] = &extal2_div2_clk, 152 [1] = &extal2_div2_clk,
153 [2] = &dv_clki_div2_clk, 153 [2] = &sh7372_dv_clki_div2_clk,
154}; 154};
155 155
156/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */ 156/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
@@ -284,7 +284,7 @@ static struct clk_ops pllc2_clk_ops = {
284 .set_parent = pllc2_set_parent, 284 .set_parent = pllc2_set_parent,
285}; 285};
286 286
287struct clk pllc2_clk = { 287struct clk sh7372_pllc2_clk = {
288 .ops = &pllc2_clk_ops, 288 .ops = &pllc2_clk_ops,
289 .parent = &extal1_div2_clk, 289 .parent = &extal1_div2_clk,
290 .freq_table = pllc2_freq_table, 290 .freq_table = pllc2_freq_table,
@@ -292,19 +292,28 @@ struct clk pllc2_clk = {
292 .parent_num = ARRAY_SIZE(pllc2_parent), 292 .parent_num = ARRAY_SIZE(pllc2_parent),
293}; 293};
294 294
295/* External input clock (pin name: FSIACK/FSIBCK ) */
296struct clk sh7372_fsiack_clk = {
297};
298
299struct clk sh7372_fsibck_clk = {
300};
301
295static struct clk *main_clks[] = { 302static struct clk *main_clks[] = {
296 &dv_clki_clk, 303 &sh7372_dv_clki_clk,
297 &r_clk, 304 &r_clk,
298 &sh7372_extal1_clk, 305 &sh7372_extal1_clk,
299 &sh7372_extal2_clk, 306 &sh7372_extal2_clk,
300 &dv_clki_div2_clk, 307 &sh7372_dv_clki_div2_clk,
301 &extal1_div2_clk, 308 &extal1_div2_clk,
302 &extal2_div2_clk, 309 &extal2_div2_clk,
303 &extal2_div4_clk, 310 &extal2_div4_clk,
304 &pllc0_clk, 311 &pllc0_clk,
305 &pllc1_clk, 312 &pllc1_clk,
306 &pllc1_div2_clk, 313 &pllc1_div2_clk,
307 &pllc2_clk, 314 &sh7372_pllc2_clk,
315 &sh7372_fsiack_clk,
316 &sh7372_fsibck_clk,
308}; 317};
309 318
310static void div4_kick(struct clk *clk) 319static void div4_kick(struct clk *clk)
@@ -357,7 +366,7 @@ static struct clk div4_clks[DIV4_NR] = {
357}; 366};
358 367
359enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO, 368enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
360 DIV6_FSIA, DIV6_FSIB, DIV6_SUB, DIV6_SPU, 369 DIV6_SUB, DIV6_SPU,
361 DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P, 370 DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
362 DIV6_NR }; 371 DIV6_NR };
363 372
@@ -367,8 +376,6 @@ static struct clk div6_clks[DIV6_NR] = {
367 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0), 376 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
368 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0), 377 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
369 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0), 378 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
370 [DIV6_FSIA] = SH_CLK_DIV6(&pllc1_div2_clk, FSIACKCR, 0),
371 [DIV6_FSIB] = SH_CLK_DIV6(&pllc1_div2_clk, FSIBCKCR, 0),
372 [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0), 379 [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
373 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0), 380 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
374 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0), 381 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
@@ -377,24 +384,42 @@ static struct clk div6_clks[DIV6_NR] = {
377 [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0), 384 [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
378}; 385};
379 386
380enum { DIV6_HDMI, DIV6_REPARENT_NR }; 387enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
381 388
382/* Indices are important - they are the actual src selecting values */ 389/* Indices are important - they are the actual src selecting values */
383static struct clk *hdmi_parent[] = { 390static struct clk *hdmi_parent[] = {
384 [0] = &pllc1_div2_clk, 391 [0] = &pllc1_div2_clk,
385 [1] = &pllc2_clk, 392 [1] = &sh7372_pllc2_clk,
386 [2] = &dv_clki_clk, 393 [2] = &sh7372_dv_clki_clk,
387 [3] = NULL, /* pllc2_div4 not implemented yet */ 394 [3] = NULL, /* pllc2_div4 not implemented yet */
388}; 395};
389 396
397static struct clk *fsiackcr_parent[] = {
398 [0] = &pllc1_div2_clk,
399 [1] = &sh7372_pllc2_clk,
400 [2] = &sh7372_fsiack_clk, /* external input for FSI A */
401 [3] = NULL, /* setting prohibited */
402};
403
404static struct clk *fsibckcr_parent[] = {
405 [0] = &pllc1_div2_clk,
406 [1] = &sh7372_pllc2_clk,
407 [2] = &sh7372_fsibck_clk, /* external input for FSI B */
408 [3] = NULL, /* setting prohibited */
409};
410
390static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = { 411static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
391 [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0, 412 [DIV6_HDMI] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, HDMICKCR, 0,
392 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2), 413 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
414 [DIV6_FSIA] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIACKCR, 0,
415 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
416 [DIV6_FSIB] = SH_CLK_DIV6_EXT(&pllc1_div2_clk, FSIBCKCR, 0,
417 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
393}; 418};
394 419
395enum { MSTP001, 420enum { MSTP001,
396 MSTP131, MSTP130, 421 MSTP131, MSTP130,
397 MSTP129, MSTP128, MSTP127, MSTP126, 422 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
398 MSTP118, MSTP117, MSTP116, 423 MSTP118, MSTP117, MSTP116,
399 MSTP106, MSTP101, MSTP100, 424 MSTP106, MSTP101, MSTP100,
400 MSTP223, 425 MSTP223,
@@ -414,6 +439,7 @@ static struct clk mstp_clks[MSTP_NR] = {
414 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */ 439 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
415 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */ 440 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
416 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */ 441 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
442 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
417 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */ 443 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
418 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */ 444 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
419 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */ 445 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
@@ -429,7 +455,7 @@ static struct clk mstp_clks[MSTP_NR] = {
429 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */ 455 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
430 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */ 456 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
431 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */ 457 [MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
432 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSIA */ 458 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
433 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */ 459 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
434 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */ 460 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
435 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */ 461 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
@@ -445,10 +471,11 @@ static struct clk mstp_clks[MSTP_NR] = {
445 471
446#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk } 472#define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
447#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk } 473#define CLKDEV_DEV_ID(_id, _clk) { .dev_id = _id, .clk = _clk }
474#define CLKDEV_ICK_ID(_cid, _did, _clk) { .con_id = _cid, .dev_id = _did, .clk = _clk }
448 475
449static struct clk_lookup lookups[] = { 476static struct clk_lookup lookups[] = {
450 /* main clocks */ 477 /* main clocks */
451 CLKDEV_CON_ID("dv_clki_div2_clk", &dv_clki_div2_clk), 478 CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
452 CLKDEV_CON_ID("r_clk", &r_clk), 479 CLKDEV_CON_ID("r_clk", &r_clk),
453 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk), 480 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
454 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk), 481 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
@@ -458,7 +485,7 @@ static struct clk_lookup lookups[] = {
458 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk), 485 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
459 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk), 486 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
460 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk), 487 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
461 CLKDEV_CON_ID("pllc2_clk", &pllc2_clk), 488 CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
462 489
463 /* DIV4 clocks */ 490 /* DIV4 clocks */
464 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]), 491 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
@@ -483,8 +510,8 @@ static struct clk_lookup lookups[] = {
483 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]), 510 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
484 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]), 511 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
485 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]), 512 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
486 CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FSIA]), 513 CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FSIA]),
487 CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FSIB]), 514 CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FSIB]),
488 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]), 515 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
489 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]), 516 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
490 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]), 517 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
@@ -501,6 +528,8 @@ static struct clk_lookup lookups[] = {
501 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */ 528 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
502 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */ 529 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
503 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */ 530 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
531 CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP125]), /* TMU00 */
532 CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP125]), /* TMU01 */
504 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */ 533 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX */
505 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */ 534 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
506 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */ 535 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
@@ -516,7 +545,7 @@ static struct clk_lookup lookups[] = {
516 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */ 545 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
517 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ 546 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
518 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ 547 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
519 CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */ 548 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
520 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */ 549 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
521 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ 550 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
522 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */ 551 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP323]), /* USB0 */
@@ -531,7 +560,10 @@ static struct clk_lookup lookups[] = {
531 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */ 560 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
532 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */ 561 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
533 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */ 562 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
534 {.con_id = "ick", .dev_id = "sh-mobile-hdmi", .clk = &div6_reparent_clks[DIV6_HDMI]}, 563
564 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
565 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
566 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
535}; 567};
536 568
537void __init sh7372_clock_init(void) 569void __init sh7372_clock_init(void)
@@ -548,7 +580,7 @@ void __init sh7372_clock_init(void)
548 ret = sh_clk_div6_register(div6_clks, DIV6_NR); 580 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
549 581
550 if (!ret) 582 if (!ret)
551 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_NR); 583 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
552 584
553 if (!ret) 585 if (!ret)
554 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR); 586 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
diff --git a/arch/arm/mach-shmobile/clock-sh7377.c b/arch/arm/mach-shmobile/clock-sh7377.c
index e007c28cf0a8..f91395aeb9ab 100644
--- a/arch/arm/mach-shmobile/clock-sh7377.c
+++ b/arch/arm/mach-shmobile/clock-sh7377.c
@@ -333,7 +333,7 @@ static struct clk_lookup lookups[] = {
333 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */ 333 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
334 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */ 334 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
335 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */ 335 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP331]), /* SCIFA6 */
336 CLKDEV_CON_ID("cmt1", &mstp_clks[MSTP329]), /* CMT10 */ 336 CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
337 CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */ 337 CLKDEV_DEV_ID("sh_irda", &mstp_clks[MSTP325]), /* IRDA */
338 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */ 338 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
339 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */ 339 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USBHS */
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 33e9700ded7e..147775a94bce 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -457,8 +457,12 @@ enum {
457 SHDMA_SLAVE_SDHI2_TX, 457 SHDMA_SLAVE_SDHI2_TX,
458}; 458};
459 459
460extern struct clk dv_clki_clk; 460extern struct clk sh7372_extal1_clk;
461extern struct clk dv_clki_div2_clk; 461extern struct clk sh7372_extal2_clk;
462extern struct clk pllc2_clk; 462extern struct clk sh7372_dv_clki_clk;
463extern struct clk sh7372_dv_clki_div2_clk;
464extern struct clk sh7372_pllc2_clk;
465extern struct clk sh7372_fsiack_clk;
466extern struct clk sh7372_fsibck_clk;
463 467
464#endif /* __ASM_SH7372_H__ */ 468#endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index e3551b56cd03..4cd3cae38e72 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -369,9 +369,13 @@ enum {
369 INTCS, 369 INTCS,
370 370
371 /* interrupt sources INTCS */ 371 /* interrupt sources INTCS */
372
373 /* IRQ0S - IRQ31S */
372 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3, 374 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
373 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3, 375 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
374 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2, 376 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
377 /* MFI */
378 /* BBIF2 */
375 VPU, 379 VPU,
376 TSIF1, 380 TSIF1,
377 _3DG_SGX530, 381 _3DG_SGX530,
@@ -379,13 +383,17 @@ enum {
379 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2, 383 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
380 IPMMU_IPMMUR, IPMMU_IPMMUR2, 384 IPMMU_IPMMUR, IPMMU_IPMMUR2,
381 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR, 385 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
386 /* KEYSC */
387 /* TTI20 */
382 MSIOF, 388 MSIOF,
383 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0, 389 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
384 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2, 390 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
385 CMT0, 391 CMT0,
386 TSIF0, 392 TSIF0,
393 /* CMT2 */
387 LMB, 394 LMB,
388 CTI, 395 CTI,
396 /* RWDT0 */
389 ICB, 397 ICB,
390 JPU_JPEG, 398 JPU_JPEG,
391 LCDC, 399 LCDC,
@@ -397,11 +405,17 @@ enum {
397 CSIRX, 405 CSIRX,
398 DSITX_DSITX0, 406 DSITX_DSITX0,
399 DSITX_DSITX1, 407 DSITX_DSITX1,
408 /* SPU2 */
409 /* FSI */
410 /* FMSI */
411 /* HDMI */
400 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2, 412 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
401 CMT4, 413 CMT4,
402 DSITX1_DSITX1_0, 414 DSITX1_DSITX1_0,
403 DSITX1_DSITX1_1, 415 DSITX1_DSITX1_1,
416 /* MFIS2 */
404 CPORTS2R, 417 CPORTS2R,
418 /* CEC */
405 JPU6E, 419 JPU6E,
406 420
407 /* interrupt groups INTCS */ 421 /* interrupt groups INTCS */
@@ -410,12 +424,15 @@ enum {
410}; 424};
411 425
412static struct intc_vect intcs_vectors[] = { 426static struct intc_vect intcs_vectors[] = {
427 /* IRQ0S - IRQ31S */
413 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720), 428 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
414 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760), 429 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
415 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820), 430 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
416 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860), 431 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
417 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0), 432 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
418 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0), 433 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
434 /* MFI */
435 /* BBIF2 */
419 INTCS_VECT(VPU, 0x980), 436 INTCS_VECT(VPU, 0x980),
420 INTCS_VECT(TSIF1, 0x9a0), 437 INTCS_VECT(TSIF1, 0x9a0),
421 INTCS_VECT(_3DG_SGX530, 0x9e0), 438 INTCS_VECT(_3DG_SGX530, 0x9e0),
@@ -425,14 +442,19 @@ static struct intc_vect intcs_vectors[] = {
425 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20), 442 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
426 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0), 443 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
427 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0), 444 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
445 /* KEYSC */
446 /* TTI20 */
447 INTCS_VECT(MSIOF, 0x0d20),
428 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20), 448 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
429 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60), 449 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
430 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0), 450 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
431 INTCS_VECT(TMU_TUNI2, 0xec0), 451 INTCS_VECT(TMU_TUNI2, 0xec0),
432 INTCS_VECT(CMT0, 0xf00), 452 INTCS_VECT(CMT0, 0xf00),
433 INTCS_VECT(TSIF0, 0xf20), 453 INTCS_VECT(TSIF0, 0xf20),
454 /* CMT2 */
434 INTCS_VECT(LMB, 0xf60), 455 INTCS_VECT(LMB, 0xf60),
435 INTCS_VECT(CTI, 0x400), 456 INTCS_VECT(CTI, 0x400),
457 /* RWDT0 */
436 INTCS_VECT(ICB, 0x480), 458 INTCS_VECT(ICB, 0x480),
437 INTCS_VECT(JPU_JPEG, 0x560), 459 INTCS_VECT(JPU_JPEG, 0x560),
438 INTCS_VECT(LCDC, 0x580), 460 INTCS_VECT(LCDC, 0x580),
@@ -446,12 +468,18 @@ static struct intc_vect intcs_vectors[] = {
446 INTCS_VECT(CSIRX, 0x17a0), 468 INTCS_VECT(CSIRX, 0x17a0),
447 INTCS_VECT(DSITX_DSITX0, 0x17c0), 469 INTCS_VECT(DSITX_DSITX0, 0x17c0),
448 INTCS_VECT(DSITX_DSITX1, 0x17e0), 470 INTCS_VECT(DSITX_DSITX1, 0x17e0),
471 /* SPU2 */
472 /* FSI */
473 /* FMSI */
474 /* HDMI */
449 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920), 475 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
450 INTCS_VECT(TMU1_TUNI2, 0x1940), 476 INTCS_VECT(TMU1_TUNI2, 0x1940),
451 INTCS_VECT(CMT4, 0x1980), 477 INTCS_VECT(CMT4, 0x1980),
452 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0), 478 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
453 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0), 479 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
480 /* MFIS2 */
454 INTCS_VECT(CPORTS2R, 0x1a20), 481 INTCS_VECT(CPORTS2R, 0x1a20),
482 /* CEC */
455 INTCS_VECT(JPU6E, 0x1a80), 483 INTCS_VECT(JPU6E, 0x1a80),
456 484
457 INTC_VECT(INTCS, 0xf80), 485 INTC_VECT(INTCS, 0xf80),
diff --git a/arch/arm/mach-shmobile/pfc-sh7372.c b/arch/arm/mach-shmobile/pfc-sh7372.c
index ec420353f8e3..9c265dae138a 100644
--- a/arch/arm/mach-shmobile/pfc-sh7372.c
+++ b/arch/arm/mach-shmobile/pfc-sh7372.c
@@ -166,12 +166,12 @@ enum {
166 MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK, 166 MSIOF2_TSYNC_MARK, MSIOF2_TSCK_MARK, MSIOF2_RXD_MARK,
167 MSIOF2_TXD_MARK, 167 MSIOF2_TXD_MARK,
168 168
169 /* MSIOF3 */ 169 /* BBIF1 */
170 BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK, 170 BBIF1_RXD_MARK, BBIF1_TSYNC_MARK, BBIF1_TSCK_MARK,
171 BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, 171 BBIF1_TXD_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
172 BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK, 172 BBIF1_FLOW_MARK, BB_RX_FLOW_N_MARK,
173 173
174 /* MSIOF4 */ 174 /* BBIF2 */
175 BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK, 175 BBIF2_TSCK1_MARK, BBIF2_TSYNC1_MARK,
176 BBIF2_TXD1_MARK, BBIF2_RXD_MARK, 176 BBIF2_TXD1_MARK, BBIF2_RXD_MARK,
177 177
@@ -976,12 +976,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
976 GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD), 976 GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_TSCK), GPIO_FN(MSIOF2_RXD),
977 GPIO_FN(MSIOF2_TXD), 977 GPIO_FN(MSIOF2_TXD),
978 978
979 /* MSIOF3 */ 979 /* BBIF1 */
980 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK), 980 GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TSYNC), GPIO_FN(BBIF1_TSCK),
981 GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), 981 GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC),
982 GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N), 982 GPIO_FN(BBIF1_FLOW), GPIO_FN(BB_RX_FLOW_N),
983 983
984 /* MSIOF4 */ 984 /* BBIF2 */
985 GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1), 985 GPIO_FN(BBIF2_TSCK1), GPIO_FN(BBIF2_TSYNC1),
986 GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD), 986 GPIO_FN(BBIF2_TXD1), GPIO_FN(BBIF2_RXD),
987 987
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index 3148c11a550e..003008c18360 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -154,7 +154,6 @@ static struct sh_timer_config cmt10_platform_data = {
154 .name = "CMT10", 154 .name = "CMT10",
155 .channel_offset = 0x10, 155 .channel_offset = 0x10,
156 .timer_bit = 0, 156 .timer_bit = 0,
157 .clk = "r_clk",
158 .clockevent_rating = 125, 157 .clockevent_rating = 125,
159 .clocksource_rating = 125, 158 .clocksource_rating = 125,
160}; 159};
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index e26686c9d0b6..564a6d0be473 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -158,7 +158,6 @@ static struct sh_timer_config cmt10_platform_data = {
158 .name = "CMT10", 158 .name = "CMT10",
159 .channel_offset = 0x10, 159 .channel_offset = 0x10,
160 .timer_bit = 0, 160 .timer_bit = 0,
161 .clk = "cmt1",
162 .clockevent_rating = 125, 161 .clockevent_rating = 125,
163 .clocksource_rating = 125, 162 .clocksource_rating = 125,
164}; 163};
@@ -186,6 +185,67 @@ static struct platform_device cmt10_device = {
186 .num_resources = ARRAY_SIZE(cmt10_resources), 185 .num_resources = ARRAY_SIZE(cmt10_resources),
187}; 186};
188 187
188/* TMU */
189static struct sh_timer_config tmu00_platform_data = {
190 .name = "TMU00",
191 .channel_offset = 0x4,
192 .timer_bit = 0,
193 .clockevent_rating = 200,
194};
195
196static struct resource tmu00_resources[] = {
197 [0] = {
198 .name = "TMU00",
199 .start = 0xfff60008,
200 .end = 0xfff60013,
201 .flags = IORESOURCE_MEM,
202 },
203 [1] = {
204 .start = intcs_evt2irq(0xe80), /* TMU_TUNI0 */
205 .flags = IORESOURCE_IRQ,
206 },
207};
208
209static struct platform_device tmu00_device = {
210 .name = "sh_tmu",
211 .id = 0,
212 .dev = {
213 .platform_data = &tmu00_platform_data,
214 },
215 .resource = tmu00_resources,
216 .num_resources = ARRAY_SIZE(tmu00_resources),
217};
218
219static struct sh_timer_config tmu01_platform_data = {
220 .name = "TMU01",
221 .channel_offset = 0x10,
222 .timer_bit = 1,
223 .clocksource_rating = 200,
224};
225
226static struct resource tmu01_resources[] = {
227 [0] = {
228 .name = "TMU01",
229 .start = 0xfff60014,
230 .end = 0xfff6001f,
231 .flags = IORESOURCE_MEM,
232 },
233 [1] = {
234 .start = intcs_evt2irq(0xea0), /* TMU_TUNI1 */
235 .flags = IORESOURCE_IRQ,
236 },
237};
238
239static struct platform_device tmu01_device = {
240 .name = "sh_tmu",
241 .id = 1,
242 .dev = {
243 .platform_data = &tmu01_platform_data,
244 },
245 .resource = tmu01_resources,
246 .num_resources = ARRAY_SIZE(tmu01_resources),
247};
248
189/* I2C */ 249/* I2C */
190static struct resource iic0_resources[] = { 250static struct resource iic0_resources[] = {
191 [0] = { 251 [0] = {
@@ -419,14 +479,14 @@ static struct resource sh7372_dmae0_resources[] = {
419 }, 479 },
420 { 480 {
421 /* DMA error IRQ */ 481 /* DMA error IRQ */
422 .start = 246, 482 .start = evt2irq(0x20c0),
423 .end = 246, 483 .end = evt2irq(0x20c0),
424 .flags = IORESOURCE_IRQ, 484 .flags = IORESOURCE_IRQ,
425 }, 485 },
426 { 486 {
427 /* IRQ for channels 0-5 */ 487 /* IRQ for channels 0-5 */
428 .start = 240, 488 .start = evt2irq(0x2000),
429 .end = 245, 489 .end = evt2irq(0x20a0),
430 .flags = IORESOURCE_IRQ, 490 .flags = IORESOURCE_IRQ,
431 }, 491 },
432}; 492};
@@ -447,14 +507,14 @@ static struct resource sh7372_dmae1_resources[] = {
447 }, 507 },
448 { 508 {
449 /* DMA error IRQ */ 509 /* DMA error IRQ */
450 .start = 254, 510 .start = evt2irq(0x21c0),
451 .end = 254, 511 .end = evt2irq(0x21c0),
452 .flags = IORESOURCE_IRQ, 512 .flags = IORESOURCE_IRQ,
453 }, 513 },
454 { 514 {
455 /* IRQ for channels 0-5 */ 515 /* IRQ for channels 0-5 */
456 .start = 248, 516 .start = evt2irq(0x2100),
457 .end = 253, 517 .end = evt2irq(0x21a0),
458 .flags = IORESOURCE_IRQ, 518 .flags = IORESOURCE_IRQ,
459 }, 519 },
460}; 520};
@@ -475,14 +535,14 @@ static struct resource sh7372_dmae2_resources[] = {
475 }, 535 },
476 { 536 {
477 /* DMA error IRQ */ 537 /* DMA error IRQ */
478 .start = 262, 538 .start = evt2irq(0x22c0),
479 .end = 262, 539 .end = evt2irq(0x22c0),
480 .flags = IORESOURCE_IRQ, 540 .flags = IORESOURCE_IRQ,
481 }, 541 },
482 { 542 {
483 /* IRQ for channels 0-5 */ 543 /* IRQ for channels 0-5 */
484 .start = 256, 544 .start = evt2irq(0x2200),
485 .end = 261, 545 .end = evt2irq(0x22a0),
486 .flags = IORESOURCE_IRQ, 546 .flags = IORESOURCE_IRQ,
487 }, 547 },
488}; 548};
@@ -526,6 +586,11 @@ static struct platform_device *sh7372_early_devices[] __initdata = {
526 &scif5_device, 586 &scif5_device,
527 &scif6_device, 587 &scif6_device,
528 &cmt10_device, 588 &cmt10_device,
589 &tmu00_device,
590 &tmu01_device,
591};
592
593static struct platform_device *sh7372_late_devices[] __initdata = {
529 &iic0_device, 594 &iic0_device,
530 &iic1_device, 595 &iic1_device,
531 &dma0_device, 596 &dma0_device,
@@ -537,6 +602,9 @@ void __init sh7372_add_standard_devices(void)
537{ 602{
538 platform_add_devices(sh7372_early_devices, 603 platform_add_devices(sh7372_early_devices,
539 ARRAY_SIZE(sh7372_early_devices)); 604 ARRAY_SIZE(sh7372_early_devices));
605
606 platform_add_devices(sh7372_late_devices,
607 ARRAY_SIZE(sh7372_late_devices));
540} 608}
541 609
542void __init sh7372_add_early_devices(void) 610void __init sh7372_add_early_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index bb4adf17dbf4..575dbd6c2f1d 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -172,7 +172,6 @@ static struct sh_timer_config cmt10_platform_data = {
172 .name = "CMT10", 172 .name = "CMT10",
173 .channel_offset = 0x10, 173 .channel_offset = 0x10,
174 .timer_bit = 0, 174 .timer_bit = 0,
175 .clk = "r_clk",
176 .clockevent_rating = 125, 175 .clockevent_rating = 125,
177 .clocksource_rating = 125, 176 .clocksource_rating = 125,
178}; 177};
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 3da116f47f01..00553233a7c5 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -176,6 +176,21 @@ static void ap320_wvga_power_off(void *board_data)
176 __raw_writew(0, FPGA_LCDREG); 176 __raw_writew(0, FPGA_LCDREG);
177} 177}
178 178
179const static struct fb_videomode ap325rxa_lcdc_modes[] = {
180 {
181 .name = "LB070WV1",
182 .xres = 800,
183 .yres = 480,
184 .left_margin = 32,
185 .right_margin = 160,
186 .hsync_len = 8,
187 .upper_margin = 63,
188 .lower_margin = 80,
189 .vsync_len = 1,
190 .sync = 0, /* hsync and vsync are active low */
191 },
192};
193
179static struct sh_mobile_lcdc_info lcdc_info = { 194static struct sh_mobile_lcdc_info lcdc_info = {
180 .clock_source = LCDC_CLK_EXTERNAL, 195 .clock_source = LCDC_CLK_EXTERNAL,
181 .ch[0] = { 196 .ch[0] = {
@@ -183,18 +198,8 @@ static struct sh_mobile_lcdc_info lcdc_info = {
183 .bpp = 16, 198 .bpp = 16,
184 .interface_type = RGB18, 199 .interface_type = RGB18,
185 .clock_divider = 1, 200 .clock_divider = 1,
186 .lcd_cfg = { 201 .lcd_cfg = ap325rxa_lcdc_modes,
187 .name = "LB070WV1", 202 .num_cfg = ARRAY_SIZE(ap325rxa_lcdc_modes),
188 .xres = 800,
189 .yres = 480,
190 .left_margin = 32,
191 .right_margin = 160,
192 .hsync_len = 8,
193 .upper_margin = 63,
194 .lower_margin = 80,
195 .vsync_len = 1,
196 .sync = 0, /* hsync and vsync are active low */
197 },
198 .lcd_size_cfg = { /* 7.0 inch */ 203 .lcd_size_cfg = { /* 7.0 inch */
199 .width = 152, 204 .width = 152,
200 .height = 91, 205 .height = 91,
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 71a3368ab1fc..0161deb770cc 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -231,14 +231,41 @@ static struct platform_device usb1_common_device = {
231}; 231};
232 232
233/* LCDC */ 233/* LCDC */
234const static struct fb_videomode ecovec_lcd_modes[] = {
235 {
236 .name = "Panel",
237 .xres = 800,
238 .yres = 480,
239 .left_margin = 220,
240 .right_margin = 110,
241 .hsync_len = 70,
242 .upper_margin = 20,
243 .lower_margin = 5,
244 .vsync_len = 5,
245 .sync = 0, /* hsync and vsync are active low */
246 },
247};
248
249const static struct fb_videomode ecovec_dvi_modes[] = {
250 {
251 .name = "DVI",
252 .xres = 1280,
253 .yres = 720,
254 .left_margin = 220,
255 .right_margin = 110,
256 .hsync_len = 40,
257 .upper_margin = 20,
258 .lower_margin = 5,
259 .vsync_len = 5,
260 .sync = 0, /* hsync and vsync are active low */
261 },
262};
263
234static struct sh_mobile_lcdc_info lcdc_info = { 264static struct sh_mobile_lcdc_info lcdc_info = {
235 .ch[0] = { 265 .ch[0] = {
236 .interface_type = RGB18, 266 .interface_type = RGB18,
237 .chan = LCDC_CHAN_MAINLCD, 267 .chan = LCDC_CHAN_MAINLCD,
238 .bpp = 16, 268 .bpp = 16,
239 .lcd_cfg = {
240 .sync = 0, /* hsync and vsync are active low */
241 },
242 .lcd_size_cfg = { /* 7.0 inch */ 269 .lcd_size_cfg = { /* 7.0 inch */
243 .width = 152, 270 .width = 152,
244 .height = 91, 271 .height = 91,
@@ -1079,33 +1106,18 @@ static int __init arch_setup(void)
1079 if (gpio_get_value(GPIO_PTE6)) { 1106 if (gpio_get_value(GPIO_PTE6)) {
1080 /* DVI */ 1107 /* DVI */
1081 lcdc_info.clock_source = LCDC_CLK_EXTERNAL; 1108 lcdc_info.clock_source = LCDC_CLK_EXTERNAL;
1082 lcdc_info.ch[0].clock_divider = 1, 1109 lcdc_info.ch[0].clock_divider = 1;
1083 lcdc_info.ch[0].lcd_cfg.name = "DVI"; 1110 lcdc_info.ch[0].lcd_cfg = ecovec_dvi_modes;
1084 lcdc_info.ch[0].lcd_cfg.xres = 1280; 1111 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_dvi_modes);
1085 lcdc_info.ch[0].lcd_cfg.yres = 720;
1086 lcdc_info.ch[0].lcd_cfg.left_margin = 220;
1087 lcdc_info.ch[0].lcd_cfg.right_margin = 110;
1088 lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
1089 lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
1090 lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
1091 lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
1092 1112
1093 gpio_set_value(GPIO_PTA2, 1); 1113 gpio_set_value(GPIO_PTA2, 1);
1094 gpio_set_value(GPIO_PTU1, 1); 1114 gpio_set_value(GPIO_PTU1, 1);
1095 } else { 1115 } else {
1096 /* Panel */ 1116 /* Panel */
1097
1098 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; 1117 lcdc_info.clock_source = LCDC_CLK_PERIPHERAL;
1099 lcdc_info.ch[0].clock_divider = 2, 1118 lcdc_info.ch[0].clock_divider = 2;
1100 lcdc_info.ch[0].lcd_cfg.name = "Panel"; 1119 lcdc_info.ch[0].lcd_cfg = ecovec_lcd_modes;
1101 lcdc_info.ch[0].lcd_cfg.xres = 800; 1120 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(ecovec_lcd_modes);
1102 lcdc_info.ch[0].lcd_cfg.yres = 480;
1103 lcdc_info.ch[0].lcd_cfg.left_margin = 220;
1104 lcdc_info.ch[0].lcd_cfg.right_margin = 110;
1105 lcdc_info.ch[0].lcd_cfg.hsync_len = 70;
1106 lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
1107 lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
1108 lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
1109 1121
1110 gpio_set_value(GPIO_PTR1, 1); 1122 gpio_set_value(GPIO_PTR1, 1);
1111 1123
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 68994a163f6c..87d4b90e368c 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -126,6 +126,21 @@ static struct platform_device kfr2r09_sh_keysc_device = {
126 }, 126 },
127}; 127};
128 128
129const static struct fb_videomode kfr2r09_lcdc_modes[] = {
130 {
131 .name = "TX07D34VM0AAA",
132 .xres = 240,
133 .yres = 400,
134 .left_margin = 0,
135 .right_margin = 16,
136 .hsync_len = 8,
137 .upper_margin = 0,
138 .lower_margin = 1,
139 .vsync_len = 1,
140 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
141 },
142};
143
129static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = { 144static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
130 .clock_source = LCDC_CLK_BUS, 145 .clock_source = LCDC_CLK_BUS,
131 .ch[0] = { 146 .ch[0] = {
@@ -134,18 +149,8 @@ static struct sh_mobile_lcdc_info kfr2r09_sh_lcdc_info = {
134 .interface_type = SYS18, 149 .interface_type = SYS18,
135 .clock_divider = 6, 150 .clock_divider = 6,
136 .flags = LCDC_FLAGS_DWPOL, 151 .flags = LCDC_FLAGS_DWPOL,
137 .lcd_cfg = { 152 .lcd_cfg = kfr2r09_lcdc_modes,
138 .name = "TX07D34VM0AAA", 153 .num_cfg = ARRAY_SIZE(kfr2r09_lcdc_modes),
139 .xres = 240,
140 .yres = 400,
141 .left_margin = 0,
142 .right_margin = 16,
143 .hsync_len = 8,
144 .upper_margin = 0,
145 .lower_margin = 1,
146 .vsync_len = 1,
147 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
148 },
149 .lcd_size_cfg = { 154 .lcd_size_cfg = {
150 .width = 35, 155 .width = 35,
151 .height = 58, 156 .height = 58,
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 662debe4ead2..9204cbb87147 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -213,51 +213,55 @@ static struct platform_device migor_nand_flash_device = {
213 } 213 }
214}; 214};
215 215
216const static struct fb_videomode migor_lcd_modes[] = {
217 {
218#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
219 .name = "LB070WV1",
220 .xres = 800,
221 .yres = 480,
222 .left_margin = 64,
223 .right_margin = 16,
224 .hsync_len = 120,
225 .sync = 0,
226#elif defined(CONFIG_SH_MIGOR_QVGA)
227 .name = "PH240320T",
228 .xres = 320,
229 .yres = 240,
230 .left_margin = 0,
231 .right_margin = 16,
232 .hsync_len = 8,
233 .sync = FB_SYNC_HOR_HIGH_ACT,
234#endif
235 .upper_margin = 1,
236 .lower_margin = 17,
237 .vsync_len = 2,
238 },
239};
240
216static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = { 241static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
217#ifdef CONFIG_SH_MIGOR_RTA_WVGA 242#if defined(CONFIG_SH_MIGOR_RTA_WVGA)
218 .clock_source = LCDC_CLK_BUS, 243 .clock_source = LCDC_CLK_BUS,
219 .ch[0] = { 244 .ch[0] = {
220 .chan = LCDC_CHAN_MAINLCD, 245 .chan = LCDC_CHAN_MAINLCD,
221 .bpp = 16, 246 .bpp = 16,
222 .interface_type = RGB16, 247 .interface_type = RGB16,
223 .clock_divider = 2, 248 .clock_divider = 2,
224 .lcd_cfg = { 249 .lcd_cfg = migor_lcd_modes,
225 .name = "LB070WV1", 250 .num_cfg = ARRAY_SIZE(migor_lcd_modes),
226 .xres = 800,
227 .yres = 480,
228 .left_margin = 64,
229 .right_margin = 16,
230 .hsync_len = 120,
231 .upper_margin = 1,
232 .lower_margin = 17,
233 .vsync_len = 2,
234 .sync = 0,
235 },
236 .lcd_size_cfg = { /* 7.0 inch */ 251 .lcd_size_cfg = { /* 7.0 inch */
237 .width = 152, 252 .width = 152,
238 .height = 91, 253 .height = 91,
239 }, 254 },
240 } 255 }
241#endif 256#elif defined(CONFIG_SH_MIGOR_QVGA)
242#ifdef CONFIG_SH_MIGOR_QVGA
243 .clock_source = LCDC_CLK_PERIPHERAL, 257 .clock_source = LCDC_CLK_PERIPHERAL,
244 .ch[0] = { 258 .ch[0] = {
245 .chan = LCDC_CHAN_MAINLCD, 259 .chan = LCDC_CHAN_MAINLCD,
246 .bpp = 16, 260 .bpp = 16,
247 .interface_type = SYS16A, 261 .interface_type = SYS16A,
248 .clock_divider = 10, 262 .clock_divider = 10,
249 .lcd_cfg = { 263 .lcd_cfg = migor_lcd_modes,
250 .name = "PH240320T", 264 .num_cfg = ARRAY_SIZE(migor_lcd_modes),
251 .xres = 320,
252 .yres = 240,
253 .left_margin = 0,
254 .right_margin = 16,
255 .hsync_len = 8,
256 .upper_margin = 1,
257 .lower_margin = 17,
258 .vsync_len = 2,
259 .sync = FB_SYNC_HOR_HIGH_ACT,
260 },
261 .lcd_size_cfg = { /* 2.4 inch */ 265 .lcd_size_cfg = { /* 2.4 inch */
262 .width = 49, 266 .width = 49,
263 .height = 37, 267 .height = 37,
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index 552ebd9ba82b..fe208d6c8ed0 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -144,16 +144,42 @@ static struct platform_device nor_flash_device = {
144}; 144};
145 145
146/* LCDC */ 146/* LCDC */
147const static struct fb_videomode lcdc_720p_modes[] = {
148 {
149 .name = "LB070WV1",
150 .sync = 0, /* hsync and vsync are active low */
151 .xres = 1280,
152 .yres = 720,
153 .left_margin = 220,
154 .right_margin = 110,
155 .hsync_len = 40,
156 .upper_margin = 20,
157 .lower_margin = 5,
158 .vsync_len = 5,
159 },
160};
161
162const static struct fb_videomode lcdc_vga_modes[] = {
163 {
164 .name = "LB070WV1",
165 .sync = 0, /* hsync and vsync are active low */
166 .xres = 640,
167 .yres = 480,
168 .left_margin = 105,
169 .right_margin = 50,
170 .hsync_len = 96,
171 .upper_margin = 33,
172 .lower_margin = 10,
173 .vsync_len = 2,
174 },
175};
176
147static struct sh_mobile_lcdc_info lcdc_info = { 177static struct sh_mobile_lcdc_info lcdc_info = {
148 .clock_source = LCDC_CLK_EXTERNAL, 178 .clock_source = LCDC_CLK_EXTERNAL,
149 .ch[0] = { 179 .ch[0] = {
150 .chan = LCDC_CHAN_MAINLCD, 180 .chan = LCDC_CHAN_MAINLCD,
151 .bpp = 16, 181 .bpp = 16,
152 .clock_divider = 1, 182 .clock_divider = 1,
153 .lcd_cfg = {
154 .name = "LB070WV1",
155 .sync = 0, /* hsync and vsync are active low */
156 },
157 .lcd_size_cfg = { /* 7.0 inch */ 183 .lcd_size_cfg = { /* 7.0 inch */
158 .width = 152, 184 .width = 152,
159 .height = 91, 185 .height = 91,
@@ -909,24 +935,12 @@ static int __init devices_setup(void)
909 935
910 if (sw & SW41_B) { 936 if (sw & SW41_B) {
911 /* 720p */ 937 /* 720p */
912 lcdc_info.ch[0].lcd_cfg.xres = 1280; 938 lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes;
913 lcdc_info.ch[0].lcd_cfg.yres = 720; 939 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes);
914 lcdc_info.ch[0].lcd_cfg.left_margin = 220;
915 lcdc_info.ch[0].lcd_cfg.right_margin = 110;
916 lcdc_info.ch[0].lcd_cfg.hsync_len = 40;
917 lcdc_info.ch[0].lcd_cfg.upper_margin = 20;
918 lcdc_info.ch[0].lcd_cfg.lower_margin = 5;
919 lcdc_info.ch[0].lcd_cfg.vsync_len = 5;
920 } else { 940 } else {
921 /* VGA */ 941 /* VGA */
922 lcdc_info.ch[0].lcd_cfg.xres = 640; 942 lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes;
923 lcdc_info.ch[0].lcd_cfg.yres = 480; 943 lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes);
924 lcdc_info.ch[0].lcd_cfg.left_margin = 105;
925 lcdc_info.ch[0].lcd_cfg.right_margin = 50;
926 lcdc_info.ch[0].lcd_cfg.hsync_len = 96;
927 lcdc_info.ch[0].lcd_cfg.upper_margin = 33;
928 lcdc_info.ch[0].lcd_cfg.lower_margin = 10;
929 lcdc_info.ch[0].lcd_cfg.vsync_len = 2;
930 } 944 }
931 945
932 if (sw & SW41_A) { 946 if (sw & SW41_A) {
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-13 10:46:30 -0500