Merge commit 'v2.6.39-rc1' into perf/urgent

Merge reason: use the post-merge-window tree.

Signed-off-by: Ingo Molnar <mingo@elte.hu>

391 files changed, 2940 insertions, 3767 deletions

diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index cc31bec2e316..bd4160c57196 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -11,6 +11,7 @@ config ALPHA
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
         select AUTO_IRQ_AFFINITY if SMP
+        select GENERIC_IRQ_SHOW
         select GENERIC_HARDIRQS_NO_DEPRECATED
         help
           The Alpha is a 64-bit general-purpose processor designed and
diff --git a/arch/alpha/kernel/irq.c b/arch/alpha/kernel/irq.c
index a19d60082299..381431a2d6d9 100644
--- a/arch/alpha/kernel/irq.c
+++ b/arch/alpha/kernel/irq.c
@@ -67,68 +67,21 @@ int irq_select_affinity(unsigned int irq)
 }
 #endif /* CONFIG_SMP */
 
-int
-show_interrupts(struct seq_file *p, void *v)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
         int j;
-        int irq = *(loff_t *) v;
-        struct irqaction * action;
-        struct irq_desc *desc;
-        unsigned long flags;
 
 #ifdef CONFIG_SMP
-        if (irq == 0) {
-                seq_puts(p, "           ");
-                for_each_online_cpu(j)
-                        seq_printf(p, "CPU%d       ", j);
-                seq_putc(p, '\n');
-        }
-#endif
-
-        if (irq < ACTUAL_NR_IRQS) {
-                desc = irq_to_desc(irq);
-
-                if (!desc)
-                        return 0;
-
-                raw_spin_lock_irqsave(&desc->lock, flags);
-                action = desc->action;
-                if (!action) 
-                        goto unlock;
-                seq_printf(p, "%3d: ", irq);
-#ifndef CONFIG_SMP
-                seq_printf(p, "%10u ", kstat_irqs(irq));
-#else
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(irq, j));
+        seq_puts(p, "IPI: ");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
+        seq_putc(p, '\n');
 #endif
-                seq_printf(p, " %14s", get_irq_desc_chip(desc)->name);
-                seq_printf(p, "  %c%s",
-                        (action->flags & IRQF_DISABLED)?'+':' ',
-                        action->name);
-
-                for (action=action->next; action; action = action->next) {
-                        seq_printf(p, ", %c%s",
-                                  (action->flags & IRQF_DISABLED)?'+':' ',
-                                   action->name);
-                }
-
-                seq_putc(p, '\n');
-unlock:
-                raw_spin_unlock_irqrestore(&desc->lock, flags);
-        } else if (irq == ACTUAL_NR_IRQS) {
-#ifdef CONFIG_SMP
-                seq_puts(p, "IPI: ");
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10lu ", cpu_data[j].ipi_count);
-                seq_putc(p, '\n');
-#endif
-                seq_puts(p, "PMI: ");
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
-                seq_puts(p, "          Performance Monitoring\n");
-                seq_printf(p, "ERR: %10lu\n", irq_err_count);
-        }
+        seq_puts(p, "PMI: ");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10lu ", per_cpu(irq_pmi_count, j));
+        seq_puts(p, "          Performance Monitoring\n");
+        seq_printf(p, "ERR: %10lu\n", irq_err_count);
         return 0;
 }
 
diff --git a/arch/alpha/kernel/irq_alpha.c b/arch/alpha/kernel/irq_alpha.c
index 411ca11d0a18..1479dc6ebd97 100644
--- a/arch/alpha/kernel/irq_alpha.c
+++ b/arch/alpha/kernel/irq_alpha.c
@@ -228,7 +228,7 @@ struct irqaction timer_irqaction = {
 void __init
 init_rtc_irq(void)
 {
-        set_irq_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
+        irq_set_chip_and_handler_name(RTC_IRQ, &no_irq_chip,
                                       handle_simple_irq, "RTC");
         setup_irq(RTC_IRQ, &timer_irqaction);
 }
diff --git a/arch/alpha/kernel/irq_i8259.c b/arch/alpha/kernel/irq_i8259.c
index c7cc9813e45f..e1861c77dabc 100644
--- a/arch/alpha/kernel/irq_i8259.c
+++ b/arch/alpha/kernel/irq_i8259.c
@@ -92,7 +92,7 @@ init_i8259a_irqs(void)
         outb(0xff, 0xA1);       /* mask all of 8259A-2 */
 
         for (i = 0; i < 16; i++) {
-                set_irq_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &i8259a_irq_type, handle_level_irq);
         }
 
         setup_irq(2, &cascade);
diff --git a/arch/alpha/kernel/irq_pyxis.c b/arch/alpha/kernel/irq_pyxis.c
index b30227fa7f5f..13c97a5b31e8 100644
--- a/arch/alpha/kernel/irq_pyxis.c
+++ b/arch/alpha/kernel/irq_pyxis.c
@@ -102,7 +102,7 @@ init_pyxis_irqs(unsigned long ignore_mask)
         for (i = 16; i < 48; ++i) {
                 if ((ignore_mask >> i) & 1)
                         continue;
-                set_irq_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &pyxis_irq_type, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/irq_srm.c b/arch/alpha/kernel/irq_srm.c
index 82a47bba41c4..a79fa30e7552 100644
--- a/arch/alpha/kernel/irq_srm.c
+++ b/arch/alpha/kernel/irq_srm.c
@@ -51,7 +51,7 @@ init_srm_irqs(long max, unsigned long ignore_mask)
         for (i = 16; i < max; ++i) {
                 if (i < 64 && ((ignore_mask >> i) & 1))
                         continue;
-                set_irq_chip_and_handler(i, &srm_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &srm_irq_type, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
diff --git a/arch/alpha/kernel/sys_alcor.c b/arch/alpha/kernel/sys_alcor.c
index 88d95e872f55..0e1439904cdb 100644
--- a/arch/alpha/kernel/sys_alcor.c
+++ b/arch/alpha/kernel/sys_alcor.c
@@ -125,7 +125,7 @@ alcor_init_irq(void)
                    on while IRQ probing.  */
                 if (i >= 16+20 && i <= 16+30)
                         continue;
-                set_irq_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &alcor_irq_type, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
         i8259a_irq_type.irq_ack = alcor_isa_mask_and_ack_irq;
diff --git a/arch/alpha/kernel/sys_cabriolet.c b/arch/alpha/kernel/sys_cabriolet.c
index 57eb6307bc27..c8c112d51584 100644
--- a/arch/alpha/kernel/sys_cabriolet.c
+++ b/arch/alpha/kernel/sys_cabriolet.c
@@ -105,8 +105,8 @@ common_init_irq(void (*srm_dev_int)(unsigned long v))
                 outb(0xff, 0x806);
 
                 for (i = 16; i < 35; ++i) {
-                        set_irq_chip_and_handler(i, &cabriolet_irq_type,
-                                handle_level_irq);
+                        irq_set_chip_and_handler(i, &cabriolet_irq_type,
+                                                 handle_level_irq);
                         irq_set_status_flags(i, IRQ_LEVEL);
                 }
         }
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
index 481df4ecb651..5ac00fd4cd0c 100644
--- a/arch/alpha/kernel/sys_dp264.c
+++ b/arch/alpha/kernel/sys_dp264.c
@@ -270,7 +270,7 @@ init_tsunami_irqs(struct irq_chip * ops, int imin, int imax)
 {
         long i;
         for (i = imin; i <= imax; ++i) {
-                set_irq_chip_and_handler(i, ops, handle_level_irq);
+                irq_set_chip_and_handler(i, ops, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
diff --git a/arch/alpha/kernel/sys_eb64p.c b/arch/alpha/kernel/sys_eb64p.c
index 402e908ffb3e..a7a23b40eec5 100644
--- a/arch/alpha/kernel/sys_eb64p.c
+++ b/arch/alpha/kernel/sys_eb64p.c
@@ -118,7 +118,7 @@ eb64p_init_irq(void)
         init_i8259a_irqs();
 
         for (i = 16; i < 32; ++i) {
-                set_irq_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &eb64p_irq_type, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/sys_eiger.c b/arch/alpha/kernel/sys_eiger.c
index 0b44a54c1522..a60cd5b2621e 100644
--- a/arch/alpha/kernel/sys_eiger.c
+++ b/arch/alpha/kernel/sys_eiger.c
@@ -138,7 +138,7 @@ eiger_init_irq(void)
         init_i8259a_irqs();
 
         for (i = 16; i < 128; ++i) {
-                set_irq_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &eiger_irq_type, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
diff --git a/arch/alpha/kernel/sys_jensen.c b/arch/alpha/kernel/sys_jensen.c
index 00341b75c8b2..7f1a87f176e2 100644
--- a/arch/alpha/kernel/sys_jensen.c
+++ b/arch/alpha/kernel/sys_jensen.c
@@ -171,11 +171,11 @@ jensen_init_irq(void)
 {
         init_i8259a_irqs();
 
-        set_irq_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
-        set_irq_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
-        set_irq_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
-        set_irq_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
-        set_irq_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(1, &jensen_local_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(4, &jensen_local_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(3, &jensen_local_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(7, &jensen_local_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(9, &jensen_local_irq_type, handle_level_irq);
 
         common_init_isa_dma();
 }
diff --git a/arch/alpha/kernel/sys_marvel.c b/arch/alpha/kernel/sys_marvel.c
index e61910734e41..388b99d1779d 100644
--- a/arch/alpha/kernel/sys_marvel.c
+++ b/arch/alpha/kernel/sys_marvel.c
@@ -276,7 +276,7 @@ init_io7_irqs(struct io7 *io7,
 
         /* Set up the lsi irqs.  */
         for (i = 0; i < 128; ++i) {
-                set_irq_chip_and_handler(base + i, lsi_ops, handle_level_irq);
+                irq_set_chip_and_handler(base + i, lsi_ops, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
@@ -290,7 +290,7 @@ init_io7_irqs(struct io7 *io7,
 
         /* Set up the msi irqs.  */
         for (i = 128; i < (128 + 512); ++i) {
-                set_irq_chip_and_handler(base + i, msi_ops, handle_level_irq);
+                irq_set_chip_and_handler(base + i, msi_ops, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
@@ -308,8 +308,8 @@ marvel_init_irq(void)
 
         /* Reserve the legacy irqs.  */
         for (i = 0; i < 16; ++i) {
-                set_irq_chip_and_handler(i, &marvel_legacy_irq_type,
-                        handle_level_irq);
+                irq_set_chip_and_handler(i, &marvel_legacy_irq_type,
+                                         handle_level_irq);
         }
 
         /* Init the io7 irqs.  */
diff --git a/arch/alpha/kernel/sys_mikasa.c b/arch/alpha/kernel/sys_mikasa.c
index cf7f43dd3147..0e6e4697a025 100644
--- a/arch/alpha/kernel/sys_mikasa.c
+++ b/arch/alpha/kernel/sys_mikasa.c
@@ -98,7 +98,8 @@ mikasa_init_irq(void)
         mikasa_update_irq_hw(0);
 
         for (i = 16; i < 32; ++i) {
-                set_irq_chip_and_handler(i, &mikasa_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &mikasa_irq_type,
+                                         handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/sys_noritake.c b/arch/alpha/kernel/sys_noritake.c
index 92bc188e94a9..a00ac7087167 100644
--- a/arch/alpha/kernel/sys_noritake.c
+++ b/arch/alpha/kernel/sys_noritake.c
@@ -127,7 +127,8 @@ noritake_init_irq(void)
         outw(0, 0x54c);
 
         for (i = 16; i < 48; ++i) {
-                set_irq_chip_and_handler(i, &noritake_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &noritake_irq_type,
+                                         handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/sys_rawhide.c b/arch/alpha/kernel/sys_rawhide.c
index 936d4140ed5f..7f52161f3d88 100644
--- a/arch/alpha/kernel/sys_rawhide.c
+++ b/arch/alpha/kernel/sys_rawhide.c
@@ -180,7 +180,8 @@ rawhide_init_irq(void)
         }
 
         for (i = 16; i < 128; ++i) {
-                set_irq_chip_and_handler(i, &rawhide_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &rawhide_irq_type,
+                                         handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/sys_rx164.c b/arch/alpha/kernel/sys_rx164.c
index cea22a62913b..216d94d9c0c1 100644
--- a/arch/alpha/kernel/sys_rx164.c
+++ b/arch/alpha/kernel/sys_rx164.c
@@ -99,7 +99,7 @@ rx164_init_irq(void)
 
         rx164_update_irq_hw(0);
         for (i = 16; i < 40; ++i) {
-                set_irq_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &rx164_irq_type, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/sys_sable.c b/arch/alpha/kernel/sys_sable.c
index a349538aabc9..da714e427c5f 100644
--- a/arch/alpha/kernel/sys_sable.c
+++ b/arch/alpha/kernel/sys_sable.c
@@ -518,8 +518,8 @@ sable_lynx_init_irq(int nr_of_irqs)
         long i;
 
         for (i = 0; i < nr_of_irqs; ++i) {
-                set_irq_chip_and_handler(i, &sable_lynx_irq_type,
-                        handle_level_irq);
+                irq_set_chip_and_handler(i, &sable_lynx_irq_type,
+                                         handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/sys_takara.c b/arch/alpha/kernel/sys_takara.c
index 42a5331f13c4..a31f8cd9bd6b 100644
--- a/arch/alpha/kernel/sys_takara.c
+++ b/arch/alpha/kernel/sys_takara.c
@@ -138,7 +138,8 @@ takara_init_irq(void)
                 takara_update_irq_hw(i, -1);
 
         for (i = 16; i < 128; ++i) {
-                set_irq_chip_and_handler(i, &takara_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &takara_irq_type,
+                                         handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index 8c13a0c77830..fea0e4620994 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -179,7 +179,7 @@ init_titan_irqs(struct irq_chip * ops, int imin, int imax)
 {
         long i;
         for (i = imin; i <= imax; ++i) {
-                set_irq_chip_and_handler(i, ops, handle_level_irq);
+                irq_set_chip_and_handler(i, ops, handle_level_irq);
                 irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
diff --git a/arch/alpha/kernel/sys_wildfire.c b/arch/alpha/kernel/sys_wildfire.c
index ca60a387ef0a..d3cb28bb8eb0 100644
--- a/arch/alpha/kernel/sys_wildfire.c
+++ b/arch/alpha/kernel/sys_wildfire.c
@@ -183,17 +183,17 @@ wildfire_init_irq_per_pca(int qbbno, int pcano)
         for (i = 0; i < 16; ++i) {
                 if (i == 2)
                         continue;
-                set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
-                        handle_level_irq);
+                irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
+                                         handle_level_irq);
                 irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
         }
 
-        set_irq_chip_and_handler(36+irq_bias, &wildfire_irq_type,
-                handle_level_irq);
+        irq_set_chip_and_handler(36 + irq_bias, &wildfire_irq_type,
+                                 handle_level_irq);
         irq_set_status_flags(36 + irq_bias, IRQ_LEVEL);
         for (i = 40; i < 64; ++i) {
-                set_irq_chip_and_handler(i+irq_bias, &wildfire_irq_type,
-                        handle_level_irq);
+                irq_set_chip_and_handler(i + irq_bias, &wildfire_irq_type,
+                                         handle_level_irq);
                 irq_set_status_flags(i + irq_bias, IRQ_LEVEL);
         }
 
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 93d595a7477a..7c0effb69fc7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -28,6 +28,7 @@ config ARM
         select HAVE_C_RECORDMCOUNT
         select HAVE_GENERIC_HARDIRQS
         select HAVE_SPARSE_IRQ
+        select GENERIC_IRQ_SHOW
         help
           The ARM series is a line of low-power-consumption RISC chip designs
           licensed by ARM Ltd and targeted at embedded applications and
@@ -2009,6 +2010,7 @@ menu "Power management options"
 source "kernel/power/Kconfig"
 
 config ARCH_SUSPEND_POSSIBLE
+        depends on !ARCH_S5P64X0 && !ARCH_S5P6442
         def_bool y
 
 endmenu
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index cb6b041c39d2..f70ec7dadebb 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
 
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
-        struct gic_chip_data *chip_data = get_irq_data(irq);
-        struct irq_chip *chip = get_irq_chip(irq);
+        struct gic_chip_data *chip_data = irq_get_handler_data(irq);
+        struct irq_chip *chip = irq_get_chip(irq);
         unsigned int cascade_irq, gic_irq;
         unsigned long status;
 
@@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 {
         if (gic_nr >= MAX_GIC_NR)
                 BUG();
-        if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
+        if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
                 BUG();
-        set_irq_chained_handler(irq, gic_handle_cascade_irq);
+        irq_set_chained_handler(irq, gic_handle_cascade_irq);
 }
 
 static void __init gic_dist_init(struct gic_chip_data *gic,
@@ -319,9 +319,8 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
          * Setup the Linux IRQ subsystem.
          */
         for (i = irq_start; i < irq_limit; i++) {
-                set_irq_chip(i, &gic_chip);
-                set_irq_chip_data(i, gic);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
+                irq_set_chip_data(i, gic);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 
@@ -382,7 +381,7 @@ void __cpuinit gic_enable_ppi(unsigned int irq)
         unsigned long flags;
 
         local_irq_save(flags);
-        irq_to_desc(irq)->status |= IRQ_NOPROBE;
+        irq_set_status_flags(irq, IRQ_NOPROBE);
         gic_unmask_irq(irq_get_irq_data(irq));
         local_irq_restore(flags);
 }
diff --git a/arch/arm/common/it8152.c b/arch/arm/common/it8152.c
index fcddd48fe9da..7a21927c52e1 100644
--- a/arch/arm/common/it8152.c
+++ b/arch/arm/common/it8152.c
@@ -88,8 +88,8 @@ void it8152_init_irq(void)
         __raw_writel((0), IT8152_INTC_LDCNIRR);
 
         for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
-                set_irq_chip(irq, &it8152_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &it8152_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 }
diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c
index a026a6bf4892..b55c3625d7ee 100644
--- a/arch/arm/common/locomo.c
+++ b/arch/arm/common/locomo.c
@@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = {
 
 static void locomo_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct locomo *lchip = get_irq_chip_data(irq);
+        struct locomo *lchip = irq_get_chip_data(irq);
         int req, i;
 
         /* Acknowledge the parent IRQ */
@@ -197,15 +197,14 @@ static void locomo_setup_irq(struct locomo *lchip)
         /*
          * Install handler for IRQ_LOCOMO_HW.
          */
-        set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
-        set_irq_chip_data(lchip->irq, lchip);
-        set_irq_chained_handler(lchip->irq, locomo_handler);
+        irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
+        irq_set_chip_data(lchip->irq, lchip);
+        irq_set_chained_handler(lchip->irq, locomo_handler);
 
         /* Install handlers for IRQ_LOCOMO_* */
         for ( ; irq <= lchip->irq_base + 3; irq++) {
-                set_irq_chip(irq, &locomo_chip);
-                set_irq_chip_data(irq, lchip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &locomo_chip, handle_level_irq);
+                irq_set_chip_data(irq, lchip);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 }
@@ -476,8 +475,8 @@ static void __locomo_remove(struct locomo *lchip)
         device_for_each_child(lchip->dev, NULL, locomo_remove_child);
 
         if (lchip->irq != NO_IRQ) {
-                set_irq_chained_handler(lchip->irq, NULL);
-                set_irq_data(lchip->irq, NULL);
+                irq_set_chained_handler(lchip->irq, NULL);
+                irq_set_handler_data(lchip->irq, NULL);
         }
 
         iounmap(lchip->base);
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index eb9796b0dab2..a12b33c0dc42 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -202,7 +202,7 @@ static void
 sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
         unsigned int stat0, stat1, i;
-        struct sa1111 *sachip = get_irq_data(irq);
+        struct sa1111 *sachip = irq_get_handler_data(irq);
         void __iomem *mapbase = sachip->base + SA1111_INTC;
 
         stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
@@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
         sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
 
         for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
-                set_irq_chip(irq, &sa1111_low_chip);
-                set_irq_chip_data(irq, sachip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &sa1111_low_chip,
+                                         handle_edge_irq);
+                irq_set_chip_data(irq, sachip);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
-                set_irq_chip(irq, &sa1111_high_chip);
-                set_irq_chip_data(irq, sachip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &sa1111_high_chip,
+                                         handle_edge_irq);
+                irq_set_chip_data(irq, sachip);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         /*
          * Register SA1111 interrupt
          */
-        set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
-        set_irq_data(sachip->irq, sachip);
-        set_irq_chained_handler(sachip->irq, sa1111_irq_handler);
+        irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
+        irq_set_handler_data(sachip->irq, sachip);
+        irq_set_chained_handler(sachip->irq, sa1111_irq_handler);
 }
 
 /*
@@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip)
         clk_disable(sachip->clk);
 
         if (sachip->irq != NO_IRQ) {
-                set_irq_chained_handler(sachip->irq, NULL);
-                set_irq_data(sachip->irq, NULL);
+                irq_set_chained_handler(sachip->irq, NULL);
+                irq_set_handler_data(sachip->irq, NULL);
 
                 release_mem_region(sachip->phys + SA1111_INTC, 512);
         }
diff --git a/arch/arm/common/vic.c b/arch/arm/common/vic.c
index ae5fe7292e0d..113085a77123 100644
--- a/arch/arm/common/vic.c
+++ b/arch/arm/common/vic.c
@@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base,
                 if (vic_sources & (1 << i)) {
                         unsigned int irq = irq_start + i;
 
-                        set_irq_chip(irq, &vic_chip);
-                        set_irq_chip_data(irq, base);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &vic_chip,
+                                                 handle_level_irq);
+                        irq_set_chip_data(irq, base);
                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                 }
         }
diff --git a/arch/arm/include/asm/hw_irq.h b/arch/arm/include/asm/hw_irq.h
index 5586b7c8ef6f..a71b417b1856 100644
--- a/arch/arm/include/asm/hw_irq.h
+++ b/arch/arm/include/asm/hw_irq.h
@@ -10,14 +10,6 @@ static inline void ack_bad_irq(int irq)
         irq_err_count++;
 }
 
-/*
- * Obsolete inline function for calling irq descriptor handlers.
- */
-static inline void desc_handle_irq(unsigned int irq, struct irq_desc *desc)
-{
-        desc->handle_irq(irq, desc);
-}
-
 void set_irq_flags(unsigned int irq, unsigned int flags);
 
 #define IRQF_VALID      (1 << 0)
diff --git a/arch/arm/kernel/bios32.c b/arch/arm/kernel/bios32.c
index d86fcd44b220..e4ee050aad7d 100644
--- a/arch/arm/kernel/bios32.c
+++ b/arch/arm/kernel/bios32.c
@@ -159,31 +159,6 @@ static void __devinit pci_fixup_dec21285(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
 
 /*
- * Same as above. The PrPMC800 carrier board for the PrPMC1100 
- * card maps the host-bridge @ 00:01:00 for some reason and it
- * ends up getting scanned. Note that we only want to do this
- * fixup when we find the IXP4xx on a PrPMC system, which is why
- * we check the machine type. We could be running on a board
- * with an IXP4xx target device and we don't want to kill the
- * resources in that case.
- */
-static void __devinit pci_fixup_prpmc1100(struct pci_dev *dev)
-{
-        int i;
-
-        if (machine_is_prpmc1100()) {
-                dev->class &= 0xff;
-                dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
-                for (i = 0; i < PCI_NUM_RESOURCES; i++) {
-                        dev->resource[i].start = 0;
-                        dev->resource[i].end   = 0;
-                        dev->resource[i].flags = 0;
-                }
-        }
-}
-DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP4XX, pci_fixup_prpmc1100);
-
-/*
  * PCI IDE controllers use non-standard I/O port decoding, respect it.
  */
 static void __devinit pci_fixup_ide_bases(struct pci_dev *dev)
diff --git a/arch/arm/kernel/ecard.c b/arch/arm/kernel/ecard.c
index 2ad62df37730..d16500110ee9 100644
--- a/arch/arm/kernel/ecard.c
+++ b/arch/arm/kernel/ecard.c
@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type)
          */
         if (slot < 8) {
                 ec->irq = 32 + slot;
-                set_irq_chip(ec->irq, &ecard_chip);
-                set_irq_handler(ec->irq, handle_level_irq);
+                irq_set_chip_and_handler(ec->irq, &ecard_chip,
+                                         handle_level_irq);
                 set_irq_flags(ec->irq, IRQF_VALID);
         }
 
@@ -1103,7 +1103,7 @@ static int __init ecard_init(void)
 
         irqhw = ecard_probeirqhw();
 
-        set_irq_chained_handler(IRQ_EXPANSIONCARD,
+        irq_set_chained_handler(IRQ_EXPANSIONCARD,
                                 irqhw ? ecard_irqexp_handler : ecard_irq_handler);
 
         ecard_proc_init();
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 3535d3793e65..83bbad03fcc6 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -51,63 +51,18 @@
 
 unsigned long irq_err_count;
 
-int show_interrupts(struct seq_file *p, void *v)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
-        int i = *(loff_t *) v, cpu;
-        struct irq_desc *desc;
-        struct irqaction * action;
-        unsigned long flags;
-        int prec, n;
-
-        for (prec = 3, n = 1000; prec < 10 && n <= nr_irqs; prec++)
-                n *= 10;
-
-#ifdef CONFIG_SMP
-        if (prec < 4)
-                prec = 4;
-#endif
-
-        if (i == 0) {
-                char cpuname[12];
-
-                seq_printf(p, "%*s ", prec, "");
-                for_each_present_cpu(cpu) {
-                        sprintf(cpuname, "CPU%d", cpu);
-                        seq_printf(p, " %10s", cpuname);
-                }
-                seq_putc(p, '\n');
-        }
-
-        if (i < nr_irqs) {
-                desc = irq_to_desc(i);
-                raw_spin_lock_irqsave(&desc->lock, flags);
-                action = desc->action;
-                if (!action)
-                        goto unlock;
-
-                seq_printf(p, "%*d: ", prec, i);
-                for_each_present_cpu(cpu)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-                seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
-                seq_printf(p, "  %s", action->name);
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-unlock:
-                raw_spin_unlock_irqrestore(&desc->lock, flags);
-        } else if (i == nr_irqs) {
 #ifdef CONFIG_FIQ
-                show_fiq_list(p, prec);
+        show_fiq_list(p, prec);
 #endif
 #ifdef CONFIG_SMP
-                show_ipi_list(p, prec);
+        show_ipi_list(p, prec);
 #endif
 #ifdef CONFIG_LOCAL_TIMERS
-                show_local_irqs(p, prec);
+        show_local_irqs(p, prec);
 #endif
-                seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
-        }
+        seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
         return 0;
 }
 
@@ -144,24 +99,21 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
 
 void set_irq_flags(unsigned int irq, unsigned int iflags)
 {
-        struct irq_desc *desc;
-        unsigned long flags;
+        unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
 
         if (irq >= nr_irqs) {
                 printk(KERN_ERR "Trying to set irq flags for IRQ%d\n", irq);
                 return;
         }
 
-        desc = irq_to_desc(irq);
-        raw_spin_lock_irqsave(&desc->lock, flags);
-        desc->status |= IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
         if (iflags & IRQF_VALID)
-                desc->status &= ~IRQ_NOREQUEST;
+                clr |= IRQ_NOREQUEST;
         if (iflags & IRQF_PROBE)
-                desc->status &= ~IRQ_NOPROBE;
+                clr |= IRQ_NOPROBE;
         if (!(iflags & IRQF_NOAUTOEN))
-                desc->status &= ~IRQ_NOAUTOEN;
-        raw_spin_unlock_irqrestore(&desc->lock, flags);
+                clr |= IRQ_NOAUTOEN;
+        /* Order is clear bits in "clr" then set bits in "set" */
+        irq_modify_status(irq, clr, set & ~clr);
 }
 
 void __init init_IRQ(void)
diff --git a/arch/arm/mach-at91/at91cap9_devices.c b/arch/arm/mach-at91/at91cap9_devices.c
index d1f775e86353..9ffbf3a2dfea 100644
--- a/arch/arm/mach-at91/at91cap9_devices.c
+++ b/arch/arm/mach-at91/at91cap9_devices.c
@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
                 return;
 
         if (cpu_is_at91cap9_revB())
-                set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
+                irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
 
         /* Enable VBus control for UHP ports */
         for (i = 0; i < data->ports; i++) {
@@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = {
 void __init at91_add_device_usba(struct usba_platform_data *data)
 {
         if (cpu_is_at91cap9_revB()) {
-                set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
+                irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
                 at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
                                                   AT91_MATRIX_UDPHS_BYPASS_LOCK);
         }
@@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
                 return;
 
         if (cpu_is_at91cap9_revB())
-                set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
+                irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
 
         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index af818a21587c..4615528205c8 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
         else
                 wakeups[bank] &= ~mask;
 
-        set_irq_wake(gpio_chip[bank].bank->id, state);
+        irq_set_irq_wake(gpio_chip[bank].bank->id, state);
 
         return 0;
 }
@@ -375,6 +375,7 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
 
 static struct irq_chip gpio_irqchip = {
         .name           = "GPIO",
+        .irq_disable    = gpio_irq_mask,
         .irq_mask       = gpio_irq_mask,
         .irq_unmask     = gpio_irq_unmask,
         .irq_set_type   = gpio_irq_type,
@@ -384,16 +385,14 @@ static struct irq_chip gpio_irqchip = {
 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
 {
         unsigned        pin;
-        struct irq_desc *gpio;
-        struct at91_gpio_chip *at91_gpio;
-        void __iomem    *pio;
+        struct irq_data *idata = irq_desc_get_irq_data(desc);
+        struct irq_chip *chip = irq_data_get_irq_chip(idata);
+        struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
+        void __iomem    *pio = at91_gpio->regbase;
         u32             isr;
 
-        at91_gpio = get_irq_chip_data(irq);
-        pio = at91_gpio->regbase;
-
         /* temporarily mask (level sensitive) parent IRQ */
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
+        chip->irq_ack(idata);
         for (;;) {
                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
                  * When there none are pending, we're finished unless we need
@@ -409,27 +408,15 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                 }
 
                 pin = at91_gpio->chip.base;
-                gpio = &irq_desc[pin];
 
                 while (isr) {
-                        if (isr & 1) {
-                                if (unlikely(gpio->depth)) {
-                                        /*
-                                         * The core ARM interrupt handler lazily disables IRQs so
-                                         * another IRQ must be generated before it actually gets
-                                         * here to be disabled on the GPIO controller.
-                                         */
-                                        gpio_irq_mask(irq_get_irq_data(pin));
-                                }
-                                else
-                                        generic_handle_irq(pin);
-                        }
+                        if (isr & 1)
+                                generic_handle_irq(pin);
                         pin++;
-                        gpio++;
                         isr >>= 1;
                 }
         }
-        desc->irq_data.chip->irq_unmask(&desc->irq_data);
+        chip->irq_unmask(idata);
         /* now it may re-trigger */
 }
 
@@ -518,14 +505,14 @@ void __init at91_gpio_irq_setup(void)
                 __raw_writel(~0, this->regbase + PIO_IDR);
 
                 for (i = 0, pin = this->chip.base; i < 32; i++, pin++) {
-                        lockdep_set_class(&irq_desc[pin].lock, &gpio_lock_class);
+                        irq_set_lockdep_class(pin, &gpio_lock_class);
 
                         /*
                          * Can use the "simple" and not "edge" handler since it's
                          * shorter, and the AIC handles interrupts sanely.
                          */
-                        set_irq_chip(pin, &gpio_irqchip);
-                        set_irq_handler(pin, handle_simple_irq);
+                        irq_set_chip_and_handler(pin, &gpio_irqchip,
+                                                 handle_simple_irq);
                         set_irq_flags(pin, IRQF_VALID);
                 }
 
@@ -536,8 +523,8 @@ void __init at91_gpio_irq_setup(void)
                 if (prev && prev->next == this)
                         continue;
 
-                set_irq_chip_data(id, this);
-                set_irq_chained_handler(id, gpio_irq_handler);
+                irq_set_chip_data(id, this);
+                irq_set_chained_handler(id, gpio_irq_handler);
         }
         pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
 }
diff --git a/arch/arm/mach-at91/include/mach/at572d940hf.h b/arch/arm/mach-at91/include/mach/at572d940hf.h
index 2d9b0af9c4d5..be510cfc56be 100644
--- a/arch/arm/mach-at91/include/mach/at572d940hf.h
+++ b/arch/arm/mach-at91/include/mach/at572d940hf.h
@@ -89,7 +89,7 @@
 /*
  * System Peripherals (offset from AT91_BASE_SYS)
  */
-#define AT91_SDRAMC     (0xffffea00 - AT91_BASE_SYS)
+#define AT91_SDRAMC0    (0xffffea00 - AT91_BASE_SYS)
 #define AT91_SMC        (0xffffec00 - AT91_BASE_SYS)
 #define AT91_MATRIX     (0xffffee00 - AT91_BASE_SYS)
 #define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)
diff --git a/arch/arm/mach-at91/irq.c b/arch/arm/mach-at91/irq.c
index b56d6b3a4087..9665265ec757 100644
--- a/arch/arm/mach-at91/irq.c
+++ b/arch/arm/mach-at91/irq.c
@@ -143,8 +143,7 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
                 /* Active Low interrupt, with the specified priority */
                 at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
 
-                set_irq_chip(i, &at91_aic_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &at91_aic_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 
                 /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
diff --git a/arch/arm/mach-bcmring/irq.c b/arch/arm/mach-bcmring/irq.c
index 84dcda0d1d9a..c48feaf4e8e9 100644
--- a/arch/arm/mach-bcmring/irq.c
+++ b/arch/arm/mach-bcmring/irq.c
@@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip,
         unsigned int i;
         for (i = 0; i < 32; i++) {
                 unsigned int irq = irq_start + i;
-                set_irq_chip(irq, chip);
-                set_irq_chip_data(irq, base);
+                irq_set_chip(irq, chip);
+                irq_set_chip_data(irq, base);
 
                 if (vic_sources & (1 << i)) {
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_handler(irq, handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                 }
         }
@@ -119,9 +119,9 @@ void __init bcmring_init_irq(void)
 
         /* special cases */
         if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
-                set_irq_handler(IRQ_GPIO0, handle_simple_irq);
+                irq_set_handler(IRQ_GPIO0, handle_simple_irq);
         }
         if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
-                set_irq_handler(IRQ_GPIO1, handle_simple_irq);
+                irq_set_handler(IRQ_GPIO1, handle_simple_irq);
         }
 }
diff --git a/arch/arm/mach-clps711x/irq.c b/arch/arm/mach-clps711x/irq.c
index 86da7a1b2bbe..c2eceee645e3 100644
--- a/arch/arm/mach-clps711x/irq.c
+++ b/arch/arm/mach-clps711x/irq.c
@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void)
 
         for (i = 0; i < NR_IRQS; i++) {
                 if (INT1_IRQS & (1 << i)) {
-                        set_irq_handler(i, handle_level_irq);
-                        set_irq_chip(i, &int1_chip);
+                        irq_set_chip_and_handler(i, &int1_chip,
+                                                 handle_level_irq);
                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                 }
                 if (INT2_IRQS & (1 << i)) {
-                        set_irq_handler(i, handle_level_irq);
-                        set_irq_chip(i, &int2_chip);
+                        irq_set_chip_and_handler(i, &int2_chip,
+                                                 handle_level_irq);
                         set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                 }                       
         }
diff --git a/arch/arm/mach-davinci/cp_intc.c b/arch/arm/mach-davinci/cp_intc.c
index 9abc80a86a22..f83152d643c5 100644
--- a/arch/arm/mach-davinci/cp_intc.c
+++ b/arch/arm/mach-davinci/cp_intc.c
@@ -167,9 +167,9 @@ void __init cp_intc_init(void)
 
         /* Set up genirq dispatching for cp_intc */
         for (i = 0; i < num_irq; i++) {
-                set_irq_chip(i, &cp_intc_irq_chip);
+                irq_set_chip(i, &cp_intc_irq_chip);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
-                set_irq_handler(i, handle_edge_irq);
+                irq_set_handler(i, handle_edge_irq);
         }
 
         /* Enable global interrupt */
diff --git a/arch/arm/mach-davinci/gpio.c b/arch/arm/mach-davinci/gpio.c
index 20d66e5e4663..a0b838894ac9 100644
--- a/arch/arm/mach-davinci/gpio.c
+++ b/arch/arm/mach-davinci/gpio.c
@@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
 {
         struct davinci_gpio_regs __iomem *g;
 
-        g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq);
+        g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
 
         return g;
 }
@@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup);
 static void gpio_irq_disable(struct irq_data *d)
 {
         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
-        u32 mask = (u32) irq_data_get_irq_data(d);
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
         __raw_writel(mask, &g->clr_falling);
         __raw_writel(mask, &g->clr_rising);
@@ -217,8 +217,8 @@ static void gpio_irq_disable(struct irq_data *d)
 static void gpio_irq_enable(struct irq_data *d)
 {
         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
-        u32 mask = (u32) irq_data_get_irq_data(d);
-        unsigned status = irq_desc[d->irq].status;
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
+        unsigned status = irqd_get_trigger_type(d);
 
         status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
         if (!status)
@@ -233,21 +233,11 @@ static void gpio_irq_enable(struct irq_data *d)
 static int gpio_irq_type(struct irq_data *d, unsigned trigger)
 {
         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
-        u32 mask = (u32) irq_data_get_irq_data(d);
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 return -EINVAL;
 
-        irq_desc[d->irq].status &= ~IRQ_TYPE_SENSE_MASK;
-        irq_desc[d->irq].status |= trigger;
-
-        /* don't enable the IRQ if it's currently disabled */
-        if (irq_desc[d->irq].depth == 0) {
-                __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
-                             ? &g->set_falling : &g->clr_falling);
-                __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING)
-                             ? &g->set_rising : &g->clr_rising);
-        }
         return 0;
 }
 
@@ -256,6 +246,7 @@ static struct irq_chip gpio_irqchip = {
         .irq_enable     = gpio_irq_enable,
         .irq_disable    = gpio_irq_disable,
         .irq_set_type   = gpio_irq_type,
+        .flags          = IRQCHIP_SET_TYPE_MASKED,
 };
 
 static void
@@ -285,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
                         status >>= 16;
 
                 /* now demux them to the right lowlevel handler */
-                n = (int)get_irq_data(irq);
+                n = (int)irq_get_handler_data(irq);
                 while (status) {
                         res = ffs(status);
                         n += res;
@@ -323,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
 static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
 {
         struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
-        u32 mask = (u32) irq_data_get_irq_data(d);
+        u32 mask = (u32) irq_data_get_irq_handler_data(d);
 
         if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
                 return -EINVAL;
@@ -395,7 +386,7 @@ static int __init davinci_gpio_irq_setup(void)
 
                 /* AINTC handles mask/unmask; GPIO handles triggering */
                 irq = bank_irq;
-                gpio_irqchip_unbanked = *get_irq_desc_chip(irq_to_desc(irq));
+                gpio_irqchip_unbanked = *irq_get_chip(irq);
                 gpio_irqchip_unbanked.name = "GPIO-AINTC";
                 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked;
 
@@ -406,10 +397,10 @@ static int __init davinci_gpio_irq_setup(void)
 
                 /* set the direct IRQs up to use that irqchip */
                 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
-                        set_irq_chip(irq, &gpio_irqchip_unbanked);
-                        set_irq_data(irq, (void *) __gpio_mask(gpio));
-                        set_irq_chip_data(irq, (__force void *) g);
-                        irq_desc[irq].status |= IRQ_TYPE_EDGE_BOTH;
+                        irq_set_chip(irq, &gpio_irqchip_unbanked);
+                        irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
+                        irq_set_chip_data(irq, (__force void *)g);
+                        irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
                 }
 
                 goto done;
@@ -430,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void)
                 __raw_writel(~0, &g->clr_rising);
 
                 /* set up all irqs in this bank */
-                set_irq_chained_handler(bank_irq, gpio_irq_handler);
-                set_irq_chip_data(bank_irq, (__force void *) g);
-                set_irq_data(bank_irq, (void *) irq);
+                irq_set_chained_handler(bank_irq, gpio_irq_handler);
+                irq_set_chip_data(bank_irq, (__force void *)g);
+                irq_set_handler_data(bank_irq, (void *)irq);
 
                 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
-                        set_irq_chip(irq, &gpio_irqchip);
-                        set_irq_chip_data(irq, (__force void *) g);
-                        set_irq_data(irq, (void *) __gpio_mask(gpio));
-                        set_irq_handler(irq, handle_simple_irq);
+                        irq_set_chip(irq, &gpio_irqchip);
+                        irq_set_chip_data(irq, (__force void *)g);
+                        irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
+                        irq_set_handler(irq, handle_simple_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 }
 
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index 5e05c9b64e1f..e6269a6e0014 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -154,11 +154,11 @@ void __init davinci_irq_init(void)
 
         /* set up genirq dispatch for ARM INTC */
         for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
-                set_irq_chip(i, &davinci_irq_chip_0);
+                irq_set_chip(i, &davinci_irq_chip_0);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
                 if (i != IRQ_TINT1_TINT34)
-                        set_irq_handler(i, handle_edge_irq);
+                        irq_set_handler(i, handle_edge_irq);
                 else
-                        set_irq_handler(i, handle_level_irq);
+                        irq_set_handler(i, handle_level_irq);
         }
 }
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index e5fcdd3f5bf5..b20ec9af7882 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -136,7 +136,7 @@
 #define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
-#define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_VIRT_BASE + 0x40)
+#define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
 #define  DOVE_SPI_GPIO_SEL              (1 << 5)
 #define  DOVE_UART1_GPIO_SEL            (1 << 4)
 #define  DOVE_AU1_GPIO_SEL              (1 << 3)
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 101707fa2e2c..f07fd16e0c9b 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -86,8 +86,7 @@ static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
                 if (!(cause & (1 << irq)))
                         continue;
                 irq = pmu_to_irq(irq);
-                desc = irq_desc + irq;
-                desc_handle_irq(irq, desc);
+                generic_handle_irq(irq);
         }
 }
 
@@ -103,14 +102,14 @@ void __init dove_init_irq(void)
          */
         orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
 
         orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 32);
-        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
 
         orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 64);
@@ -122,10 +121,9 @@ void __init dove_init_irq(void)
         writel(0, PMU_INTERRUPT_CAUSE);
 
         for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &pmu_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
+                irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
+                irq_set_status_flags(i, IRQ_LEVEL);
                 set_irq_flags(i, IRQF_VALID);
         }
-        set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
+        irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
 }
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index 71db2bdf2f28..c66c76346904 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -147,9 +147,6 @@ void __init dove_mpp_conf(unsigned int *mpp_list)
         u32 pmu_sig_ctrl[PMU_SIG_REGS];
         int i;
 
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         for (i = 0; i < MPP_NR_REGS; i++)
                 mpp_ctrl[i] = readl(MPP_CTRL(i));
 
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 7df083f37fa7..087bc771ac23 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void)
         local_irq_restore(flags);
 
         for (irq = 0; irq < NR_IRQS; irq++) {
-                set_irq_chip(irq, &ebsa110_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 }
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index 34e071d79761..180b8a9d0d21 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -117,7 +117,7 @@ static void ep93xx_gpio_irq_ack(struct irq_data *d)
         int port = line >> 3;
         int port_mask = 1 << (line & 7);
 
-        if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+        if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
                 ep93xx_gpio_update_int_params(port);
         }
@@ -131,7 +131,7 @@ static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
         int port = line >> 3;
         int port_mask = 1 << (line & 7);
 
-        if ((irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
+        if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
                 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
 
         gpio_int_unmasked[port] &= ~port_mask;
@@ -165,10 +165,10 @@ static void ep93xx_gpio_irq_unmask(struct irq_data *d)
  */
 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
 {
-        struct irq_desc *desc = irq_desc + d->irq;
         const int gpio = irq_to_gpio(d->irq);
         const int port = gpio >> 3;
         const int port_mask = 1 << (gpio & 7);
+        irq_flow_handler_t handler;
 
         gpio_direction_input(gpio);
 
@@ -176,22 +176,22 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
         case IRQ_TYPE_EDGE_RISING:
                 gpio_int_type1[port] |= port_mask;
                 gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_edge_irq;
+                handler = handle_edge_irq;
                 break;
         case IRQ_TYPE_EDGE_FALLING:
                 gpio_int_type1[port] |= port_mask;
                 gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_edge_irq;
+                handler = handle_edge_irq;
                 break;
         case IRQ_TYPE_LEVEL_HIGH:
                 gpio_int_type1[port] &= ~port_mask;
                 gpio_int_type2[port] |= port_mask;
-                desc->handle_irq = handle_level_irq;
+                handler = handle_level_irq;
                 break;
         case IRQ_TYPE_LEVEL_LOW:
                 gpio_int_type1[port] &= ~port_mask;
                 gpio_int_type2[port] &= ~port_mask;
-                desc->handle_irq = handle_level_irq;
+                handler = handle_level_irq;
                 break;
         case IRQ_TYPE_EDGE_BOTH:
                 gpio_int_type1[port] |= port_mask;
@@ -200,17 +200,16 @@ static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
                         gpio_int_type2[port] &= ~port_mask; /* falling */
                 else
                         gpio_int_type2[port] |= port_mask; /* rising */
-                desc->handle_irq = handle_edge_irq;
+                handler = handle_edge_irq;
                 break;
         default:
                 pr_err("failed to set irq type %d for gpio %d\n", type, gpio);
                 return -EINVAL;
         }
 
-        gpio_int_enabled[port] |= port_mask;
+        __irq_set_handler_locked(d->irq, handler);
 
-        desc->status &= ~IRQ_TYPE_SENSE_MASK;
-        desc->status |= type & IRQ_TYPE_SENSE_MASK;
+        gpio_int_enabled[port] |= port_mask;
 
         ep93xx_gpio_update_int_params(port);
 
@@ -232,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void)
 
         for (gpio_irq = gpio_to_irq(0);
              gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
-                set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
-                set_irq_handler(gpio_irq, handle_level_irq);
+                irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(gpio_irq, IRQF_VALID);
         }
 
-        set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
-        set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
+                                ep93xx_gpio_ab_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
+                                ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
+                                ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
+                                ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
+                                ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
+                                ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
+                                ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
+                                ep93xx_gpio_f_irq_handler);
+        irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
+                                ep93xx_gpio_f_irq_handler);
 }
 
 
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index a021b5240bba..e849f67be47d 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -20,6 +20,11 @@ config EXYNOS4_MCT
         help
           Use MCT (Multi Core Timer) as kernel timers
 
+config EXYNOS4_DEV_AHCI
+        bool
+        help
+          Compile in platform device definitions for AHCI
+
 config EXYNOS4_DEV_PD
         bool
         help
@@ -134,9 +139,9 @@ config MACH_ARMLEX4210
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
+        select EXYNOS4_DEV_AHCI
         select EXYNOS4_DEV_SYSMMU
         select EXYNOS4_SETUP_SDHCI
-        select SATA_AHCI_PLATFORM
         help
           Machine support for Samsung ARMLEX4210 based on EXYNOS4210
 
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index b8f0e7d82d7e..9be104f63c0b 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -39,6 +39,7 @@ obj-$(CONFIG_MACH_NURI)			+= mach-nuri.o
 # device support
 
 obj-y                                   += dev-audio.o
+obj-$(CONFIG_EXYNOS4_DEV_AHCI)          += dev-ahci.o
 obj-$(CONFIG_EXYNOS4_DEV_PD)            += dev-pd.o
 obj-$(CONFIG_EXYNOS4_DEV_SYSMMU)        += dev-sysmmu.o
 
@@ -53,4 +54,3 @@ obj-$(CONFIG_EXYNOS4_SETUP_I2C7)	+= setup-i2c7.o
 obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD)      += setup-keypad.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI)       += setup-sdhci.o
 obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO)  += setup-sdhci-gpio.o
-obj-$(CONFIG_SATA_AHCI_PLATFORM)        += dev-ahci.o
diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S
index 58bbd049a6c4..a442ef861167 100644
--- a/arch/arm/mach-exynos4/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S
@@ -21,8 +21,8 @@
          */
 
         .macro addruart, rp, rv
-                ldreq   \rp, = S3C_PA_UART
-                ldrne   \rv, = S3C_VA_UART
+                ldr     \rp, = S3C_PA_UART
+                ldr     \rv, = S3C_VA_UART
 #if CONFIG_DEBUG_S3C_UART != 0
                 add     \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
                 add     \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index 31618d91ce15..f488b66d6806 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data)
 
 static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
-        struct combiner_chip_data *chip_data = get_irq_data(irq);
-        struct irq_chip *chip = get_irq_chip(irq);
+        struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
+        struct irq_chip *chip = irq_get_chip(irq);
         unsigned int cascade_irq, combiner_irq;
         unsigned long status;
 
@@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
 {
         if (combiner_nr >= MAX_COMBINER_NR)
                 BUG();
-        if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0)
+        if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
                 BUG();
-        set_irq_chained_handler(irq, combiner_handle_cascade_irq);
+        irq_set_chained_handler(irq, combiner_handle_cascade_irq);
 }
 
 void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
@@ -119,9 +119,8 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 
         for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
                                 + MAX_IRQ_IN_COMBINER; i++) {
-                set_irq_chip(i, &combiner_chip);
-                set_irq_chip_data(i, &combiner_data[combiner_nr]);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
+                irq_set_chip_data(i, &combiner_data[combiner_nr]);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 }
diff --git a/arch/arm/mach-exynos4/irq-eint.c b/arch/arm/mach-exynos4/irq-eint.c
index 4f7ad4a796e4..9d87d2ac7f68 100644
--- a/arch/arm/mach-exynos4/irq-eint.c
+++ b/arch/arm/mach-exynos4/irq-eint.c
@@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
 
 static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
 {
-        u32 *irq_data = get_irq_data(irq);
-        struct irq_chip *chip = get_irq_chip(irq);
+        u32 *irq_data = irq_get_handler_data(irq);
+        struct irq_chip *chip = irq_get_chip(irq);
 
         chip->irq_mask(&desc->irq_data);
 
@@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void)
         int irq;
 
         for (irq = 0 ; irq <= 31 ; irq++) {
-                set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
-                set_irq_handler(IRQ_EINT(irq), handle_level_irq);
+                irq_set_chip_and_handler(IRQ_EINT(irq), &exynos4_irq_eint,
+                                         handle_level_irq);
                 set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
         }
 
-        set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
+        irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
 
         for (irq = 0 ; irq <= 15 ; irq++) {
                 eint0_15_data[irq] = IRQ_EINT(irq);
 
-                set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
-                set_irq_chained_handler(exynos4_get_irq_nr(irq),
+                irq_set_handler_data(exynos4_get_irq_nr(irq),
+                                     &eint0_15_data[irq]);
+                irq_set_chained_handler(exynos4_get_irq_nr(irq),
                                         exynos4_irq_eint0_15);
         }
 
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index 25a256818122..e645f7a955f0 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -125,7 +125,7 @@ static struct resource smdkc210_smsc911x_resources[] = {
 };
 
 static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
         .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
         .phy_interface  = PHY_INTERFACE_MODE_MII,
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 88e0275143be..152676471b67 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -127,7 +127,7 @@ static struct resource smdkv310_smsc911x_resources[] = {
 };
 
 static struct smsc911x_platform_config smsc9215_config = {
-        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+        .irq_polarity   = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
         .irq_type       = SMSC911X_IRQ_TYPE_PUSH_PULL,
         .flags          = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
         .phy_interface  = PHY_INTERFACE_MODE_MII,
diff --git a/arch/arm/mach-footbridge/common.c b/arch/arm/mach-footbridge/common.c
index 84c5f258f2d8..38a44f9b9da2 100644
--- a/arch/arm/mach-footbridge/common.c
+++ b/arch/arm/mach-footbridge/common.c
@@ -102,8 +102,7 @@ static void __init __fb_init_irq(void)
         *CSR_FIQ_DISABLE = -1;
 
         for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
-                set_irq_chip(irq, &fb_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &fb_chip, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 }
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index a921fe92b858..5f1f9867fc70 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -30,7 +30,7 @@ static int cksrc_dc21285_enable(struct clocksource *cs)
         return 0;
 }
 
-static int cksrc_dc21285_disable(struct clocksource *cs)
+static void cksrc_dc21285_disable(struct clocksource *cs)
 {
         *CSR_TIMER2_CNTL = 0;
 }
diff --git a/arch/arm/mach-footbridge/isa-irq.c b/arch/arm/mach-footbridge/isa-irq.c
index de7a5cb5dbe1..c3a0abbc9049 100644
--- a/arch/arm/mach-footbridge/isa-irq.c
+++ b/arch/arm/mach-footbridge/isa-irq.c
@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq)
 
         if (host_irq != (unsigned int)-1) {
                 for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
-                        set_irq_chip(irq, &isa_lo_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &isa_lo_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                 }
 
                 for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
-                        set_irq_chip(irq, &isa_hi_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &isa_hi_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                 }
 
@@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq)
                 request_resource(&ioport_resource, &pic2_resource);
                 setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
 
-                set_irq_chained_handler(host_irq, isa_irq_handler);
+                irq_set_chained_handler(host_irq, isa_irq_handler);
 
                 /*
                  * On the NetWinder, don't automatically
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index fa3d333f21e1..fdc7ef1391d3 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -127,8 +127,8 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
 
 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
+        unsigned int port = (unsigned int)irq_desc_get_handler_data(desc);
         unsigned int gpio_irq_no, irq_stat;
-        unsigned int port = (unsigned int)get_irq_data(irq);
 
         irq_stat = __raw_readl(GPIO_BASE(port) + GPIO_INT_STAT);
 
@@ -138,9 +138,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                 if ((irq_stat & 1) == 0)
                         continue;
 
-                BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
-                irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
-                                &irq_desc[gpio_irq_no]);
+                generic_handle_irq(gpio_irq_no);
         }
 }
 
@@ -219,13 +217,13 @@ void __init gemini_gpio_init(void)
 
                 for (j = GPIO_IRQ_BASE + i * 32;
                      j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
-                        set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_edge_irq);
+                        irq_set_chip_and_handler(j, &gpio_irq_chip,
+                                                 handle_edge_irq);
                         set_irq_flags(j, IRQF_VALID);
                 }
 
-                set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
-                set_irq_data(IRQ_GPIO(i), (void *)i);
+                irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
+                irq_set_handler_data(IRQ_GPIO(i), (void *)i);
         }
 
         BUG_ON(gpiochip_add(&gemini_gpio_chip));
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 96bc227dd849..9485a8fdf851 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -81,13 +81,13 @@ void __init gemini_init_irq(void)
         request_resource(&iomem_resource, &irq_resource);
 
         for (i = 0; i < NR_IRQS; i++) {
-                set_irq_chip(i, &gemini_irq_chip);
+                irq_set_chip(i, &gemini_irq_chip);
                 if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
-                        set_irq_handler(i, handle_edge_irq);
+                        irq_set_handler(i, handle_edge_irq);
                         mode |= 1 << i;
                         level |= 1 << i;
                 } else {                        
-                        set_irq_handler(i, handle_level_irq);
+                        irq_set_handler(i, handle_level_irq);
                 }
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
index 1f28c90932c7..51d4e44ab973 100644
--- a/arch/arm/mach-h720x/common.c
+++ b/arch/arm/mach-h720x/common.c
@@ -199,29 +199,29 @@ void __init h720x_init_irq (void)
 
         /* Initialize global IRQ's, fast path */
         for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
-                set_irq_chip(irq, &h720x_global_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &h720x_global_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         /* Initialize multiplexed IRQ's, slow path */
         for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
-                set_irq_chip(irq, &h720x_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &h720x_gpio_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID );
         }
-        set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
-        set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
-        set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
-        set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
+        irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
+        irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
+        irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
+        irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
 
 #ifdef CONFIG_CPU_H7202
         for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
-                set_irq_chip(irq, &h720x_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &h720x_gpio_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID );
         }
-        set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
+        irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
 #endif
 
         /* Enable multiplexed irq's */
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
index ac3f91442376..c37d570b852d 100644
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ b/arch/arm/mach-h720x/cpu-h7202.c
@@ -141,13 +141,18 @@ h7202_timer_interrupt(int irq, void *dev_id)
 /*
  * mask multiplexed timer IRQs
  */
-static void inline mask_timerx_irq(struct irq_data *d)
+static void inline __mask_timerx_irq(unsigned int irq)
 {
         unsigned int bit;
-        bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
+        bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
         CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
 }
 
+static void inline mask_timerx_irq(struct irq_data *d)
+{
+        __mask_timerx_irq(d->irq);
+}
+
 /*
  * unmask multiplexed timer IRQs
  */
@@ -196,12 +201,12 @@ void __init h7202_init_irq (void)
 
         for (irq = IRQ_TIMER1;
                           irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
-                mask_timerx_irq(irq);
-                set_irq_chip(irq, &h7202_timerx_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                __mask_timerx_irq(irq);
+                irq_set_chip_and_handler(irq, &h7202_timerx_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID );
         }
-        set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
+        irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
 
         h720x_init_irq();
 }
diff --git a/arch/arm/mach-iop13xx/irq.c b/arch/arm/mach-iop13xx/irq.c
index a233470dd10c..bc739701c301 100644
--- a/arch/arm/mach-iop13xx/irq.c
+++ b/arch/arm/mach-iop13xx/irq.c
@@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void)
 
         for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
                 if (i < 32)
-                        set_irq_chip(i, &iop13xx_irqchip1);
+                        irq_set_chip(i, &iop13xx_irqchip1);
                 else if (i < 64)
-                        set_irq_chip(i, &iop13xx_irqchip2);
+                        irq_set_chip(i, &iop13xx_irqchip2);
                 else if (i < 96)
-                        set_irq_chip(i, &iop13xx_irqchip3);
+                        irq_set_chip(i, &iop13xx_irqchip3);
                 else
-                        set_irq_chip(i, &iop13xx_irqchip4);
+                        irq_set_chip(i, &iop13xx_irqchip4);
 
-                set_irq_handler(i, handle_level_irq);
+                irq_set_handler(i, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 
diff --git a/arch/arm/mach-iop13xx/msi.c b/arch/arm/mach-iop13xx/msi.c
index c9c02e3698bc..560d5b2dec22 100644
--- a/arch/arm/mach-iop13xx/msi.c
+++ b/arch/arm/mach-iop13xx/msi.c
@@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init iop13xx_msi_init(void)
 {
-        set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
+        irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
 }
 
 /*
@@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
         if (irq < 0)
                 return irq;
 
-        set_irq_msi(irq, desc);
+        irq_set_msi_desc(irq, desc);
 
         msg.address_hi = 0x0;
         msg.address_lo = IOP13XX_MU_MIMR_PCI;
@@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
         msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
 
         write_msi_msg(irq, &msg);
-        set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
+        irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
 
         return 0;
 }
diff --git a/arch/arm/mach-iop32x/irq.c b/arch/arm/mach-iop32x/irq.c
index d3426a120599..d7ee2789d890 100644
--- a/arch/arm/mach-iop32x/irq.c
+++ b/arch/arm/mach-iop32x/irq.c
@@ -68,8 +68,7 @@ void __init iop32x_init_irq(void)
                 *IOP3XX_PCIIRSR = 0x0f;
 
         for (i = 0; i < NR_IRQS; i++) {
-                set_irq_chip(i, &ext_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &ext_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 }
diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index 0ff2f74363a5..f7f5d3e451c7 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -110,8 +110,9 @@ void __init iop33x_init_irq(void)
                 *IOP3XX_PCIIRSR = 0x0f;
 
         for (i = 0; i < NR_IRQS; i++) {
-                set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i,
+                                         (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 }
diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c
index 5fc4e064b650..4068166c8993 100644
--- a/arch/arm/mach-ixp2000/core.c
+++ b/arch/arm/mach-ixp2000/core.c
@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void)
          */
         for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
                 if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
-                        set_irq_chip(irq, &ixp2000_irq_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &ixp2000_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 } else set_irq_flags(irq, 0);
         }
@@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void)
         for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
                 if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
                                 IXP2000_VALID_ERR_IRQ_MASK) {
-                        set_irq_chip(irq, &ixp2000_err_irq_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 }
                 else
                         set_irq_flags(irq, 0);
         }
-        set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
+        irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
 
         for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
-                set_irq_chip(irq, &ixp2000_GPIO_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
-        set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
+        irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
 
         /*
          * Enable PCI irqs.  The actual PCI[AB] decoding is done in
@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void)
          */
         ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
         for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
-                set_irq_chip(irq, &ixp2000_pci_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c
index 7d90d3f13ee8..235638f800e5 100644
--- a/arch/arm/mach-ixp2000/ixdp2x00.c
+++ b/arch/arm/mach-ixp2000/ixdp2x00.c
@@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
         *board_irq_mask = 0xffffffff;
 
         for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
-                set_irq_chip(irq, &ixdp2x00_cpld_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
         /* Hook into PCI interrupt */
-        set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
+        irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
 }
 
 /*************************************************************************
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index 34b1b2af37c8..84835b209557 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void)
 
         for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
                 if (irq & valid_irq_mask) {
-                        set_irq_chip(irq, &ixdp2x01_irq_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID);
                 } else {
                         set_irq_flags(irq, 0);
@@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void)
         }
 
         /* Hook into PCI interrupts */
-        set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
+        irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
 }
 
 
diff --git a/arch/arm/mach-ixp23xx/core.c b/arch/arm/mach-ixp23xx/core.c
index 9c8a33903216..a1bee33d183e 100644
--- a/arch/arm/mach-ixp23xx/core.c
+++ b/arch/arm/mach-ixp23xx/core.c
@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
 {
         switch (type) {
         case IXP23XX_IRQ_LEVEL:
-                set_irq_chip(irq, &ixp23xx_irq_level_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &ixp23xx_irq_level_chip,
+                                         handle_level_irq);
                 break;
         case IXP23XX_IRQ_EDGE:
-                set_irq_chip(irq, &ixp23xx_irq_edge_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &ixp23xx_irq_edge_chip,
+                                         handle_edge_irq);
                 break;
         }
         set_irq_flags(irq, IRQF_VALID);
@@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void)
         }
 
         for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
-                set_irq_chip(irq, &ixp23xx_pci_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &ixp23xx_pci_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
+        irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
 }
 
 
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index 181116aa6591..8dcba17c81e7 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void)
              irq++) {
                 if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
                         set_irq_flags(irq, IRQF_VALID);
-                        set_irq_handler(irq, handle_level_irq);
-                        set_irq_chip(irq, &ixdp2351_inta_chip);
+                        irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
+                                                 handle_level_irq);
                 }
         }
 
@@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void)
              irq++) {
                 if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
                         set_irq_flags(irq, IRQF_VALID);
-                        set_irq_handler(irq, handle_level_irq);
-                        set_irq_chip(irq, &ixdp2351_intb_chip);
+                        irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
+                                                 handle_level_irq);
                 }
         }
 
-        set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
-        set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
+        irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
+        irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
 }
 
 /*
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 76c61ba73218..8fe0c6273262 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
 
 static void __init roadrunner_pci_preinit(void)
 {
-        set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
 
         ixp23xx_pci_preinit();
 }
diff --git a/arch/arm/mach-ixp4xx/avila-pci.c b/arch/arm/mach-ixp4xx/avila-pci.c
index 845e1b500548..162043ff29ff 100644
--- a/arch/arm/mach-ixp4xx/avila-pci.c
+++ b/arch/arm/mach-ixp4xx/avila-pci.c
@@ -39,10 +39,10 @@
 
 void __init avila_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 9fd894271d5d..ed19bc314318 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void)
 
         /* Default to all level triggered */
         for(i = 0; i < NR_IRQS; i++) {
-                set_irq_chip(i, &ixp4xx_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-ixp4xx/coyote-pci.c b/arch/arm/mach-ixp4xx/coyote-pci.c
index b978ea8bd6f0..37fda7d6e83d 100644
--- a/arch/arm/mach-ixp4xx/coyote-pci.c
+++ b/arch/arm/mach-ixp4xx/coyote-pci.c
@@ -32,8 +32,8 @@
 
 void __init coyote_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/dsmg600-pci.c b/arch/arm/mach-ixp4xx/dsmg600-pci.c
index fa70fed462ba..c7612010b3fc 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-pci.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-pci.c
@@ -35,12 +35,12 @@
 
 void __init dsmg600_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/fsg-pci.c b/arch/arm/mach-ixp4xx/fsg-pci.c
index 5a810c930624..44ccde9d4879 100644
--- a/arch/arm/mach-ixp4xx/fsg-pci.c
+++ b/arch/arm/mach-ixp4xx/fsg-pci.c
@@ -32,9 +32,9 @@
 
 void __init fsg_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/gateway7001-pci.c b/arch/arm/mach-ixp4xx/gateway7001-pci.c
index 7e93a0975c4d..fc1124168874 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-pci.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-pci.c
@@ -29,8 +29,8 @@
 
 void __init gateway7001_pci_preinit(void)
 {
-        set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
 
         ixp4xx_pci_preinit();
 }
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index d0e4861ac03d..3e8c0e33b59c 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -420,8 +420,8 @@ static void __init gmlr_init(void)
         gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
         gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
         gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
-        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
-        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
 
         set_control(CONTROL_HSS0_DTR_N, 1);
         set_control(CONTROL_HSS1_DTR_N, 1);
@@ -441,10 +441,10 @@ static void __init gmlr_init(void)
 #ifdef CONFIG_PCI
 static void __init gmlr_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-pci.c b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
index 25d2c333c204..38cc0725dbd8 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-pci.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-pci.c
@@ -43,8 +43,8 @@
  */
 void __init gtwx5715_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/ixdp425-pci.c b/arch/arm/mach-ixp4xx/ixdp425-pci.c
index 1ba165a6edac..58f400417eaf 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-pci.c
@@ -36,10 +36,10 @@
 
 void __init ixdp425_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/ixdpg425-pci.c b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
index 4ed7ac614920..e64f6d041488 100644
--- a/arch/arm/mach-ixp4xx/ixdpg425-pci.c
+++ b/arch/arm/mach-ixp4xx/ixdpg425-pci.c
@@ -25,8 +25,8 @@
 
 void __init ixdpg425_pci_preinit(void)
 {
-        set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
 
         ixp4xx_pci_preinit();
 }
diff --git a/arch/arm/mach-ixp4xx/nas100d-pci.c b/arch/arm/mach-ixp4xx/nas100d-pci.c
index d0cea34cf61e..428d1202b799 100644
--- a/arch/arm/mach-ixp4xx/nas100d-pci.c
+++ b/arch/arm/mach-ixp4xx/nas100d-pci.c
@@ -33,11 +33,11 @@
 
 void __init nas100d_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/nslu2-pci.c b/arch/arm/mach-ixp4xx/nslu2-pci.c
index 1eb5a90470bc..2e85f76b950d 100644
--- a/arch/arm/mach-ixp4xx/nslu2-pci.c
+++ b/arch/arm/mach-ixp4xx/nslu2-pci.c
@@ -32,9 +32,9 @@
 
 void __init nslu2_pci_preinit(void)
 {
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/vulcan-pci.c b/arch/arm/mach-ixp4xx/vulcan-pci.c
index f3111c6840ef..03bdec5140a7 100644
--- a/arch/arm/mach-ixp4xx/vulcan-pci.c
+++ b/arch/arm/mach-ixp4xx/vulcan-pci.c
@@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void)
         pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
                 (int)(pci_cardbus_mem_size >> 20));
 #endif
-        set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
         ixp4xx_pci_preinit();
 }
 
diff --git a/arch/arm/mach-ixp4xx/wg302v2-pci.c b/arch/arm/mach-ixp4xx/wg302v2-pci.c
index 9b59ed03b151..17f3cf59a31b 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-pci.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-pci.c
@@ -29,8 +29,8 @@
 
 void __init wg302v2_pci_preinit(void)
 {
-        set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
-        set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
 
         ixp4xx_pci_preinit();
 }
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index cbdb5863d13b..05d193a25b25 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void)
          */
         orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START);
-        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
 
         orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START + 32);
-        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23,
+                                gpio_irq_handler);
 }
diff --git a/arch/arm/mach-ks8695/gpio.c b/arch/arm/mach-ks8695/gpio.c
index 55fbf7111a5b..31e456508a6f 100644
--- a/arch/arm/mach-ks8695/gpio.c
+++ b/arch/arm/mach-ks8695/gpio.c
@@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
         local_irq_restore(flags);
 
         /* Set IRQ triggering type */
-        set_irq_type(gpio_irq[pin], type);
+        irq_set_irq_type(gpio_irq[pin], type);
 
         /* enable interrupt mode */
         ks8695_gpio_mode(pin, 0);
diff --git a/arch/arm/mach-ks8695/irq.c b/arch/arm/mach-ks8695/irq.c
index 7998ccaa6333..a78092dcd6fb 100644
--- a/arch/arm/mach-ks8695/irq.c
+++ b/arch/arm/mach-ks8695/irq.c
@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
         }
 
         if (level_triggered) {
-                set_irq_chip(d->irq, &ks8695_irq_level_chip);
-                set_irq_handler(d->irq, handle_level_irq);
+                irq_set_chip_and_handler(d->irq, &ks8695_irq_level_chip,
+                                         handle_level_irq);
         }
         else {
-                set_irq_chip(d->irq, &ks8695_irq_edge_chip);
-                set_irq_handler(d->irq, handle_edge_irq);
+                irq_set_chip_and_handler(d->irq, &ks8695_irq_edge_chip,
+                                         handle_edge_irq);
         }
 
         __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
@@ -158,16 +158,18 @@ void __init ks8695_init_irq(void)
                         case KS8695_IRQ_UART_RX:
                         case KS8695_IRQ_COMM_TX:
                         case KS8695_IRQ_COMM_RX:
-                                set_irq_chip(irq, &ks8695_irq_level_chip);
-                                set_irq_handler(irq, handle_level_irq);
+                                irq_set_chip_and_handler(irq,
+                                                         &ks8695_irq_level_chip,
+                                                         handle_level_irq);
                                 break;
 
                         /* Edge-triggered interrupts */
                         default:
                                 /* clear pending bit */
                                 ks8695_irq_ack(irq_get_irq_data(irq));
-                                set_irq_chip(irq, &ks8695_irq_edge_chip);
-                                set_irq_handler(irq, handle_edge_irq);
+                                irq_set_chip_and_handler(irq,
+                                                         &ks8695_irq_edge_chip,
+                                                         handle_edge_irq);
                 }
 
                 set_irq_flags(irq, IRQF_VALID);
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 316ecbf6c586..4eae566dfdc7 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
         }
 
         /* Ok to use the level handler for all types */
-        set_irq_handler(d->irq, handle_level_irq);
+        irq_set_handler(d->irq, handle_level_irq);
 
         return 0;
 }
@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void)
 
         /* Configure supported IRQ's */
         for (i = 0; i < NR_IRQS; i++) {
-                set_irq_chip(i, &lpc32xx_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &lpc32xx_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
@@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void)
         __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
 
         /* MIC SUBIRQx interrupts will route handling to the chain handlers */
-        set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
-        set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
+        irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
+        irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
 
         /* Initially disable all wake events */
         __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
diff --git a/arch/arm/mach-mmp/irq-mmp2.c b/arch/arm/mach-mmp/irq-mmp2.c
index fa037038e7b8..d21c5441a3d0 100644
--- a/arch/arm/mach-mmp/irq-mmp2.c
+++ b/arch/arm/mach-mmp/irq-mmp2.c
@@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
                 if (chip->irq_ack)
                         chip->irq_ack(d);
 
-                set_irq_chip(irq, chip);
+                irq_set_chip(irq, chip);
                 set_irq_flags(irq, IRQF_VALID);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_handler(irq, handle_level_irq);
         }
 }
 
@@ -122,7 +122,7 @@ void __init mmp2_init_icu(void)
 
         for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
                 icu_mask_irq(irq_get_irq_data(irq));
-                set_irq_chip(irq, &icu_irq_chip);
+                irq_set_chip(irq, &icu_irq_chip);
                 set_irq_flags(irq, IRQF_VALID);
 
                 switch (irq) {
@@ -133,7 +133,7 @@ void __init mmp2_init_icu(void)
                 case IRQ_MMP2_SSP_MUX:
                         break;
                 default:
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_handler(irq, handle_level_irq);
                         break;
                 }
         }
@@ -149,9 +149,9 @@ void __init mmp2_init_icu(void)
         init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
         init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
 
-        set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
-        set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
-        set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
-        set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
-        set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
+        irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
+        irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
+        irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
+        irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
+        irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
 }
diff --git a/arch/arm/mach-mmp/irq-pxa168.c b/arch/arm/mach-mmp/irq-pxa168.c
index f86b450cb93c..89706a0d08f1 100644
--- a/arch/arm/mach-mmp/irq-pxa168.c
+++ b/arch/arm/mach-mmp/irq-pxa168.c
@@ -48,8 +48,7 @@ void __init icu_init_irq(void)
 
         for (irq = 0; irq < 64; irq++) {
                 icu_mask_irq(irq_get_irq_data(irq));
-                set_irq_chip(irq, &icu_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index 1993721d472e..35c7ceeb3f29 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void)
          */
         for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
                 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                        set_irq_handler(i, handle_percpu_irq);
+                        irq_set_handler(i, handle_percpu_irq);
         }
 }
 
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index b3c55f138fce..1163b6fd05d2 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void)
          */
         for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
                 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
-                        set_irq_handler(i, handle_percpu_irq);
+                        irq_set_handler(i, handle_percpu_irq);
         }
 }
 
diff --git a/arch/arm/mach-msm/board-trout-gpio.c b/arch/arm/mach-msm/board-trout-gpio.c
index 31117a4499c4..87e1d01edecc 100644
--- a/arch/arm/mach-msm/board-trout-gpio.c
+++ b/arch/arm/mach-msm/board-trout-gpio.c
@@ -214,17 +214,17 @@ int __init trout_init_gpio(void)
 {
         int i;
         for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
-                set_irq_chip(i, &trout_gpio_irq_chip);
-                set_irq_handler(i, handle_edge_irq);
+                irq_set_chip_and_handler(i, &trout_gpio_irq_chip,
+                                         handle_edge_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
         for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
                 gpiochip_add(&msm_gpio_banks[i].chip);
 
-        set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
-        set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
-        set_irq_wake(MSM_GPIO_TO_INT(17), 1);
+        irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
+        irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
+        irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
 
         return 0;
 }
diff --git a/arch/arm/mach-msm/board-trout-mmc.c b/arch/arm/mach-msm/board-trout-mmc.c
index 44be8464657b..f7a9724788b0 100644
--- a/arch/arm/mach-msm/board-trout-mmc.c
+++ b/arch/arm/mach-msm/board-trout-mmc.c
@@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev)
         if (IS_ERR(vreg_sdslot))
                 return PTR_ERR(vreg_sdslot);
 
-        set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
+        irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
 
         if (!opt_disable_sdcard)
                 msm_add_sdcc(2, &trout_sdslot_data,
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 0de19ec74e34..56a964e52ad3 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -230,18 +230,18 @@ static void msm_gpio_update_dual_edge_pos(unsigned gpio)
                val, val2);
 }
 
-static void msm_gpio_irq_ack(unsigned int irq)
+static void msm_gpio_irq_ack(struct irq_data *d)
 {
-        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
 
         writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio));
         if (test_bit(gpio, msm_gpio.dual_edge_irqs))
                 msm_gpio_update_dual_edge_pos(gpio);
 }
 
-static void msm_gpio_irq_mask(unsigned int irq)
+static void msm_gpio_irq_mask(struct irq_data *d)
 {
-        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
         unsigned long irq_flags;
 
         spin_lock_irqsave(&tlmm_lock, irq_flags);
@@ -251,9 +251,9 @@ static void msm_gpio_irq_mask(unsigned int irq)
         spin_unlock_irqrestore(&tlmm_lock, irq_flags);
 }
 
-static void msm_gpio_irq_unmask(unsigned int irq)
+static void msm_gpio_irq_unmask(struct irq_data *d)
 {
-        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
         unsigned long irq_flags;
 
         spin_lock_irqsave(&tlmm_lock, irq_flags);
@@ -263,9 +263,9 @@ static void msm_gpio_irq_unmask(unsigned int irq)
         spin_unlock_irqrestore(&tlmm_lock, irq_flags);
 }
 
-static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
+static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
         unsigned long irq_flags;
         uint32_t bits;
 
@@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
 
         if (flow_type & IRQ_TYPE_EDGE_BOTH) {
                 bits |= BIT(INTR_DECT_CTL);
-                irq_desc[irq].handle_irq = handle_edge_irq;
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
                 if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
                         __set_bit(gpio, msm_gpio.dual_edge_irqs);
                 else
                         __clear_bit(gpio, msm_gpio.dual_edge_irqs);
         } else {
                 bits &= ~BIT(INTR_DECT_CTL);
-                irq_desc[irq].handle_irq = handle_level_irq;
+                __irq_set_handler_locked(d->irq, handle_level_irq);
                 __clear_bit(gpio, msm_gpio.dual_edge_irqs);
         }
 
@@ -309,6 +309,7 @@ static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
  */
 static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
+        struct irq_data *data = irq_desc_get_irq_data(desc);
         unsigned long i;
 
         for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
@@ -318,21 +319,21 @@ static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
                         generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
                                                            i));
         }
-        desc->chip->ack(irq);
+        data->chip->irq_ack(data);
 }
 
-static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
+static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq);
+        int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, d->irq);
 
         if (on) {
                 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
-                        set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
+                        irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
                 set_bit(gpio, msm_gpio.wake_irqs);
         } else {
                 clear_bit(gpio, msm_gpio.wake_irqs);
                 if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
-                        set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
+                        irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
         }
 
         return 0;
@@ -340,11 +341,11 @@ static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on)
 
 static struct irq_chip msm_gpio_irq_chip = {
         .name           = "msmgpio",
-        .mask           = msm_gpio_irq_mask,
-        .unmask         = msm_gpio_irq_unmask,
-        .ack            = msm_gpio_irq_ack,
-        .set_type       = msm_gpio_irq_set_type,
-        .set_wake       = msm_gpio_irq_set_wake,
+        .irq_mask       = msm_gpio_irq_mask,
+        .irq_unmask     = msm_gpio_irq_unmask,
+        .irq_ack        = msm_gpio_irq_ack,
+        .irq_set_type   = msm_gpio_irq_set_type,
+        .irq_set_wake   = msm_gpio_irq_set_wake,
 };
 
 static int __devinit msm_gpio_probe(struct platform_device *dev)
@@ -361,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
 
         for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
                 irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
-                set_irq_chip(irq, &msm_gpio_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &msm_gpio_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
+        irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
                                 msm_summary_irq_handler);
         return 0;
 }
@@ -378,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev)
         if (ret < 0)
                 return ret;
 
-        set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
+        irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
 
         return 0;
 }
diff --git a/arch/arm/mach-msm/gpio.c b/arch/arm/mach-msm/gpio.c
index 176af9dcb8ee..5ea273b00da8 100644
--- a/arch/arm/mach-msm/gpio.c
+++ b/arch/arm/mach-msm/gpio.c
@@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
         val = readl(msm_chip->regs.int_edge);
         if (flow_type & IRQ_TYPE_EDGE_BOTH) {
                 writel(val | mask, msm_chip->regs.int_edge);
-                irq_desc[d->irq].handle_irq = handle_edge_irq;
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
         } else {
                 writel(val & ~mask, msm_chip->regs.int_edge);
-                irq_desc[d->irq].handle_irq = handle_level_irq;
+                __irq_set_handler_locked(d->irq, handle_level_irq);
         }
         if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
                 msm_chip->both_edge_detect |= mask;
@@ -354,9 +354,9 @@ static int __init msm_init_gpio(void)
                         msm_gpio_chips[j].chip.base +
                         msm_gpio_chips[j].chip.ngpio)
                         j++;
-                set_irq_chip_data(i, &msm_gpio_chips[j]);
-                set_irq_chip(i, &msm_gpio_irq_chip);
-                set_irq_handler(i, handle_edge_irq);
+                irq_set_chip_data(i, &msm_gpio_chips[j]);
+                irq_set_chip_and_handler(i, &msm_gpio_irq_chip,
+                                         handle_edge_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
@@ -366,10 +366,10 @@ static int __init msm_init_gpio(void)
                 gpiochip_add(&msm_gpio_chips[i].chip);
         }
 
-        set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
-        set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
-        set_irq_wake(INT_GPIO_GROUP1, 1);
-        set_irq_wake(INT_GPIO_GROUP2, 2);
+        irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
+        irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
+        irq_set_irq_wake(INT_GPIO_GROUP1, 1);
+        irq_set_irq_wake(INT_GPIO_GROUP2, 2);
         return 0;
 }
 
diff --git a/arch/arm/mach-msm/irq-vic.c b/arch/arm/mach-msm/irq-vic.c
index 68c28bbdc969..1b54f807c2d0 100644
--- a/arch/arm/mach-msm/irq-vic.c
+++ b/arch/arm/mach-msm/irq-vic.c
@@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
         type = msm_irq_shadow_reg[index].int_type;
         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
                 type |= b;
-                irq_desc[d->irq].handle_irq = handle_edge_irq;
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
         }
         if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
                 type &= ~b;
-                irq_desc[d->irq].handle_irq = handle_level_irq;
+                __irq_set_handler_locked(d->irq, handle_level_irq);
         }
         writel(type, treg);
         msm_irq_shadow_reg[index].int_type = type;
@@ -357,8 +357,7 @@ void __init msm_init_irq(void)
         writel(3, VIC_INT_MASTEREN);
 
         for (n = 0; n < NR_MSM_IRQS; n++) {
-                set_irq_chip(n, &msm_irq_chip);
-                set_irq_handler(n, handle_level_irq);
+                irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
                 set_irq_flags(n, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-msm/irq.c b/arch/arm/mach-msm/irq.c
index 0b27d899f40e..ea514be390c6 100644
--- a/arch/arm/mach-msm/irq.c
+++ b/arch/arm/mach-msm/irq.c
@@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
 
         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
                 writel(readl(treg) | b, treg);
-                irq_desc[d->irq].handle_irq = handle_edge_irq;
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
         }
         if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
                 writel(readl(treg) & (~b), treg);
-                irq_desc[d->irq].handle_irq = handle_level_irq;
+                __irq_set_handler_locked(d->irq, handle_level_irq);
         }
         return 0;
 }
@@ -145,8 +145,7 @@ void __init msm_init_irq(void)
         writel(1, VIC_INT_MASTEREN);
 
         for (n = 0; n < NR_MSM_IRQS; n++) {
-                set_irq_chip(n, &msm_irq_chip);
-                set_irq_handler(n, handle_level_irq);
+                irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
                 set_irq_flags(n, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-msm/sirc.c b/arch/arm/mach-msm/sirc.c
index 11b54c7aeb09..689e78c95f38 100644
--- a/arch/arm/mach-msm/sirc.c
+++ b/arch/arm/mach-msm/sirc.c
@@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
         val = readl(sirc_regs.int_type);
         if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
                 val |= mask;
-                irq_desc[d->irq].handle_irq = handle_edge_irq;
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
         } else {
                 val &= ~mask;
-                irq_desc[d->irq].handle_irq = handle_level_irq;
+                __irq_set_handler_locked(d->irq, handle_level_irq);
         }
 
         writel(val, sirc_regs.int_type);
@@ -158,15 +158,14 @@ void __init msm_init_sirc(void)
         wake_enable = 0;
 
         for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
-                set_irq_chip(i, &sirc_irq_chip);
-                set_irq_handler(i, handle_edge_irq);
+                irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
         for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
-                set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
+                irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
                                         sirc_irq_handler);
-                set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
+                irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
         }
         return;
 }
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 08da497c39c2..3e24431bb5ea 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void)
         orion_gpio_init(0, 32, GPIO_VIRT_BASE,
                         mv78xx0_core_index() ? 0x18 : 0,
                         IRQ_MV78XX0_GPIO_START);
-        set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
 }
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
index 4e4b780c481d..3d095d69bc68 100644
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ b/arch/arm/mach-mx3/mach-mx31ads.c
@@ -199,12 +199,11 @@ static void __init mx31ads_init_expio(void)
         __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
         for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
              i++) {
-                set_irq_chip(i, &expio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
-        set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
-        set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
+        irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
+        irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
 }
 
 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index e83ffadb65f8..4a8550529b04 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
 
         gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
         gpio_direction_input(MBIMX51_TSC2007_GPIO);
-        set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
+        irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
         i2c_register_board_info(1, mbimx51_i2c_devices,
                                 ARRAY_SIZE(mbimx51_i2c_devices));
 
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index 51a67fc7f0ef..868af8f435fa 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -572,8 +572,10 @@ static struct mc13xxx_regulator_init_data mx51_efika_regulators[] = {
 
 static struct mc13xxx_platform_data mx51_efika_mc13892_data = {
         .flags = MC13XXX_USE_RTC | MC13XXX_USE_REGULATOR,
-        .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
-        .regulators = mx51_efika_regulators,
+        .regulators = {
+                .num_regulators = ARRAY_SIZE(mx51_efika_regulators),
+                .regulators = mx51_efika_regulators,
+        },
 };
 
 static struct spi_board_info mx51_efika_spi_board_info[] __initdata = {
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
index 56fa2ed15222..2c950fef71a8 100644
--- a/arch/arm/mach-mxs/gpio.c
+++ b/arch/arm/mach-mxs/gpio.c
@@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         u32 irq_stat;
-        struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
+        struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
         u32 gpio_irq_no_base = port->virtual_irq_start;
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
 
                 for (j = port[i].virtual_irq_start;
                         j < port[i].virtual_irq_start + 32; j++) {
-                        set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_level_irq);
+                        irq_set_chip_and_handler(j, &gpio_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(j, IRQF_VALID);
                 }
 
                 /* setup one handler for each entry */
-                set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler);
-                set_irq_data(port[i].irq, &port[i]);
+                irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
+                irq_set_handler_data(port[i].irq, &port[i]);
 
                 /* register gpio chip */
                 port[i].chip.direction_input = mxs_gpio_direction_input;
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
index 0f4c120fc169..23ca9d083b2c 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/arch/arm/mach-mxs/icoll.c
@@ -74,8 +74,7 @@ void __init icoll_init_irq(void)
         mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
 
         for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
-                set_irq_chip(i, &mxs_icoll_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &mxs_icoll_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-netx/generic.c b/arch/arm/mach-netx/generic.c
index 29ffa750fbe6..00023b5cf12b 100644
--- a/arch/arm/mach-netx/generic.c
+++ b/arch/arm/mach-netx/generic.c
@@ -171,13 +171,13 @@ void __init netx_init_irq(void)
         vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
 
         for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
-                set_irq_chip(irq, &netx_hif_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &netx_hif_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
         writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
-        set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
+        irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
 }
 
 static int __init netx_init(void)
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
index 0c0d5248c368..e27687d53504 100644
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void)
                                 __func__);
 
         for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
-                set_irq_chip(i, &a9m9750dev_fpga_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
@@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void)
         REGSET(eic, SYS_EIC, LVEDG, LEVEL);
         __raw_writel(eic, SYS_EIC(2));
 
-        set_irq_chained_handler(IRQ_NS9XXX_EXT2,
-                        a9m9750dev_fpga_demux_handler);
+        irq_set_chained_handler(IRQ_NS9XXX_EXT2,
+                                a9m9750dev_fpga_demux_handler);
 }
 
 void __init board_a9m9750dev_init_machine(void)
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h
index f7e9196eb9ab..19ca6de46a45 100644
--- a/arch/arm/mach-ns9xxx/include/mach/board.h
+++ b/arch/arm/mach-ns9xxx/include/mach/board.h
@@ -14,12 +14,10 @@
 #include <asm/mach-types.h>
 
 #define board_is_a9m9750dev()   (0                      \
-                || machine_is_cc9p9360dev()             \
                 || machine_is_cc9p9750dev()             \
                 )
 
 #define board_is_a9mvali()      (0                      \
-                || machine_is_cc9p9360val()             \
                 || machine_is_cc9p9750val()             \
                 )
 
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h
index f851a6b7da6c..628e9752589b 100644
--- a/arch/arm/mach-ns9xxx/include/mach/module.h
+++ b/arch/arm/mach-ns9xxx/include/mach/module.h
@@ -18,7 +18,6 @@
                 )
 
 #define module_is_cc9c()        (0                      \
-                || machine_is_cc9c()                    \
                 )
 
 #define module_is_cc9p9210()    (0                      \
@@ -32,21 +31,17 @@
                 )
 
 #define module_is_cc9p9360()    (0                      \
-                || machine_is_a9m9360()                 \
                 || machine_is_cc9p9360dev()             \
                 || machine_is_cc9p9360js()              \
-                || machine_is_cc9p9360val()             \
                 )
 
 #define module_is_cc9p9750()    (0                      \
                 || machine_is_a9m9750()                 \
-                || machine_is_cc9p9750dev()             \
                 || machine_is_cc9p9750js()              \
                 || machine_is_cc9p9750val()             \
                 )
 
 #define module_is_ccw9c()       (0                      \
-                || machine_is_ccw9c()                   \
                 )
 
 #define module_is_inc20otter()  (0                      \
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
index 389fa5c669de..37ab0a2b83ad 100644
--- a/arch/arm/mach-ns9xxx/irq.c
+++ b/arch/arm/mach-ns9xxx/irq.c
@@ -31,17 +31,11 @@ static void ns9xxx_mask_irq(struct irq_data *d)
         __raw_writel(ic, SYS_IC(prio / 4));
 }
 
-static void ns9xxx_ack_irq(struct irq_data *d)
+static void ns9xxx_eoi_irq(struct irq_data *d)
 {
         __raw_writel(0, SYS_ISRADDR);
 }
 
-static void ns9xxx_maskack_irq(struct irq_data *d)
-{
-        ns9xxx_mask_irq(d);
-        ns9xxx_ack_irq(d);
-}
-
 static void ns9xxx_unmask_irq(struct irq_data *d)
 {
         /* XXX: better use cpp symbols */
@@ -52,56 +46,11 @@ static void ns9xxx_unmask_irq(struct irq_data *d)
 }
 
 static struct irq_chip ns9xxx_chip = {
-        .irq_ack        = ns9xxx_ack_irq,
+        .irq_eoi        = ns9xxx_eoi_irq,
         .irq_mask       = ns9xxx_mask_irq,
-        .irq_mask_ack   = ns9xxx_maskack_irq,
         .irq_unmask     = ns9xxx_unmask_irq,
 };
 
-#if 0
-#define handle_irq handle_level_irq
-#else
-static void handle_prio_irq(unsigned int irq, struct irq_desc *desc)
-{
-        struct irqaction *action;
-        irqreturn_t action_ret;
-
-        raw_spin_lock(&desc->lock);
-
-        BUG_ON(desc->status & IRQ_INPROGRESS);
-
-        desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
-        kstat_incr_irqs_this_cpu(irq, desc);
-
-        action = desc->action;
-        if (unlikely(!action || (desc->status & IRQ_DISABLED)))
-                goto out_mask;
-
-        desc->status |= IRQ_INPROGRESS;
-        raw_spin_unlock(&desc->lock);
-
-        action_ret = handle_IRQ_event(irq, action);
-
-        /* XXX: There is no direct way to access noirqdebug, so check
-         * unconditionally for spurious irqs...
-         * Maybe this function should go to kernel/irq/chip.c? */
-        note_interrupt(irq, desc, action_ret);
-
-        raw_spin_lock(&desc->lock);
-        desc->status &= ~IRQ_INPROGRESS;
-
-        if (desc->status & IRQ_DISABLED)
-out_mask:
-                desc->irq_data.chip->irq_mask(&desc->irq_data);
-
-        /* ack unconditionally to unmask lower prio irqs */
-        desc->irq_data.chip->irq_ack(&desc->irq_data);
-
-        raw_spin_unlock(&desc->lock);
-}
-#define handle_irq handle_prio_irq
-#endif
-
 void __init ns9xxx_init_irq(void)
 {
         int i;
@@ -118,8 +67,8 @@ void __init ns9xxx_init_irq(void)
                 __raw_writel(prio2irq(i), SYS_IVA(i));
 
         for (i = 0; i <= 31; ++i) {
-                set_irq_chip(i, &ns9xxx_chip);
-                set_irq_handler(i, handle_irq);
+                irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
                 set_irq_flags(i, IRQF_VALID);
+                irq_set_status_flags(i, IRQ_LEVEL);
         }
 }
diff --git a/arch/arm/mach-nuc93x/irq.c b/arch/arm/mach-nuc93x/irq.c
index 1f8a05a22834..aa279f23e342 100644
--- a/arch/arm/mach-nuc93x/irq.c
+++ b/arch/arm/mach-nuc93x/irq.c
@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void)
         __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
 
         for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
-                set_irq_chip(irqno, &nuc93x_irq_chip);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &nuc93x_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index 7c5e2112c776..e68dfde1918e 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -276,7 +276,7 @@ static void __init osk_init_cf(void)
                 return;
         }
         /* the CF I/O IRQ is really active-low */
-        set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
 }
 
 static void __init osk_init_irq(void)
@@ -482,7 +482,7 @@ static void __init osk_mistral_init(void)
         omap_cfg_reg(P20_1610_GPIO4);   /* PENIRQ */
         gpio_request(4, "ts_int");
         gpio_direction_input(4);
-        set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
 
         spi_register_board_info(mistral_boardinfo,
                         ARRAY_SIZE(mistral_boardinfo));
@@ -500,7 +500,7 @@ static void __init osk_mistral_init(void)
                 int irq = gpio_to_irq(OMAP_MPUIO(2));
 
                 gpio_direction_input(OMAP_MPUIO(2));
-                set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
+                irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
 #ifdef  CONFIG_PM
                 /* share the IRQ in case someone wants to use the
                  * button for more than wakeup from system sleep.
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index d7bbbe721a75..45f01d2c3a7a 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id)
 {
         if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) {
                 printk(KERN_INFO "PM: Power cable connected\n");
-                set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
-                                IRQ_TYPE_EDGE_FALLING);
+                irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
+                                 IRQ_TYPE_EDGE_FALLING);
         } else {
                 printk(KERN_INFO "PM: Power cable disconnected\n");
-                set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
-                                IRQ_TYPE_EDGE_RISING);
+                irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
+                                 IRQ_TYPE_EDGE_RISING);
         }
         return IRQ_HANDLED;
 }
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index bdc0ac8dc21f..65d24204937a 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -279,10 +279,10 @@ static void __init voiceblue_init(void)
         gpio_request(13, "16C554 irq");
         gpio_request(14, "16C554 irq");
         gpio_request(15, "16C554 irq");
-        set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
 
         platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
         omap_board_config = voiceblue_config;
diff --git a/arch/arm/mach-omap1/fpga.c b/arch/arm/mach-omap1/fpga.c
index 0ace7998aaa5..cddbf8b089ce 100644
--- a/arch/arm/mach-omap1/fpga.c
+++ b/arch/arm/mach-omap1/fpga.c
@@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void)
                          * The touchscreen interrupt is level-sensitive, so
                          * we'll use the regular mask_ack routine for it.
                          */
-                        set_irq_chip(i, &omap_fpga_irq_ack);
+                        irq_set_chip(i, &omap_fpga_irq_ack);
                 }
                 else {
                         /*
                          * All FPGA interrupts except the touchscreen are
                          * edge-sensitive, so we won't mask them.
                          */
-                        set_irq_chip(i, &omap_fpga_irq);
+                        irq_set_chip(i, &omap_fpga_irq);
                 }
 
-                set_irq_handler(i, handle_edge_irq);
+                irq_set_handler(i, handle_edge_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
@@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void)
                 return;
         }
         gpio_direction_input(13);
-        set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
-        set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
+        irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
+        irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
 }
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 731dd33bff51..5d3da7a63af3 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -230,8 +230,8 @@ void __init omap_init_irq(void)
                         irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
                         omap_irq_set_cfg(j, 0, 0, irq_trigger);
 
-                        set_irq_chip(j, &omap_irq_chip);
-                        set_irq_handler(j, handle_level_irq);
+                        irq_set_chip_and_handler(j, &omap_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(j, IRQF_VALID);
                 }
         }
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 493505c3b2f5..130034bf01d5 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -743,7 +743,7 @@ static int __init gpmc_init(void)
         /* initalize the irq_chained */
         irq = OMAP_GPMC_IRQ_BASE;
         for (cs = 0; cs < GPMC_CS_NUM; cs++) {
-                set_irq_chip_and_handler(irq, &dummy_irq_chip,
+                irq_set_chip_and_handler(irq, &dummy_irq_chip,
                                                 handle_simple_irq);
                 set_irq_flags(irq, IRQF_VALID);
                 irq++;
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index bc524b94fd59..237e4530abf2 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -223,8 +223,7 @@ void __init omap_init_irq(void)
                nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
 
         for (i = 0; i < nr_of_irqs; i++) {
-                set_irq_chip(i, &omap_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index c10a11715376..b7d4591214e0 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void)
         pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
         if (gpio_request(pin, "PCI Int1") == 0) {
                 if (gpio_direction_input(pin) == 0) {
-                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
                 } else {
                         printk(KERN_ERR "db88f5281_pci_preinit faield to "
                                         "set_irq_type pin %d\n", pin);
@@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void)
         pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
         if (gpio_request(pin, "PCI Int2") == 0) {
                 if (gpio_direction_input(pin) == 0) {
-                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
                 } else {
                         printk(KERN_ERR "db88f5281_pci_preinit faield "
                                         "to set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index ed85891f8699..43cf8bc9767b 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -34,8 +34,8 @@ void __init orion5x_init_irq(void)
          * Initialize gpiolib for GPIOs 0-31.
          */
         orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
-        set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
+        irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
 }
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 67ec6959b267..4fc46772a087 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void)
         pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
         if (gpio_request(pin, "PCI IntA") == 0) {
                 if (gpio_direction_input(pin) == 0) {
-                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
                 } else {
                         printk(KERN_ERR "rd88f5182_pci_preinit faield to "
                                         "set_irq_type pin %d\n", pin);
@@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void)
         pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
         if (gpio_request(pin, "PCI IntB") == 0) {
                 if (gpio_direction_input(pin) == 0) {
-                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
                 } else {
                         printk(KERN_ERR "rd88f5182_pci_preinit faield to "
                                         "set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 5653ee6c71d8..616004143912 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void)
         pin = TSP2_PCI_SLOT0_IRQ_PIN;
         if (gpio_request(pin, "PCI Int1") == 0) {
                 if (gpio_direction_input(pin) == 0) {
-                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
                 } else {
                         printk(KERN_ERR "tsp2_pci_preinit failed "
                                         "to set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 8bbd27ea6735..f0f43e13ac87 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void)
         pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
         if (gpio_request(pin, "PCI Int1") == 0) {
                 if (gpio_direction_input(pin) == 0) {
-                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
                 } else {
                         printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
                                         "set_irq_type pin %d\n", pin);
@@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void)
         pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
         if (gpio_request(pin, "PCI Int2") == 0) {
                 if (gpio_direction_input(pin) == 0) {
-                        set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
                 } else {
                         printk(KERN_ERR "qnap_ts209_pci_preinit failed "
                                         "to set_irq_type pin %d\n", pin);
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
index c69c180aec76..7608c7a288cf 100644
--- a/arch/arm/mach-pnx4008/irq.c
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
         case IRQ_TYPE_EDGE_RISING:
                 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
                 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /*rising edge */
-                set_irq_handler(d->irq, handle_edge_irq);
+                irq_set_handler(d->irq, handle_edge_irq);
                 break;
         case IRQ_TYPE_EDGE_FALLING:
                 __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq));       /*edge sensitive */
                 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*falling edge */
-                set_irq_handler(d->irq, handle_edge_irq);
+                irq_set_handler(d->irq, handle_edge_irq);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
                 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
                 __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq));      /*low level */
-                set_irq_handler(d->irq, handle_level_irq);
+                irq_set_handler(d->irq, handle_level_irq);
                 break;
         case IRQ_TYPE_LEVEL_HIGH:
                 __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq));      /*level sensitive */
                 __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq));       /* high level */
-                set_irq_handler(d->irq, handle_level_irq);
+                irq_set_handler(d->irq, handle_level_irq);
                 break;
 
         /* IRQ_TYPE_EDGE_BOTH is not supported */
@@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void)
         /* configure IRQ's */
         for (i = 0; i < NR_IRQS; i++) {
                 set_irq_flags(i, IRQF_VALID);
-                set_irq_chip(i, &pnx4008_irq_chip);
+                irq_set_chip(i, &pnx4008_irq_chip);
                 pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
         }
 
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index d2af73321dae..38dea05df7f8 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -527,13 +527,13 @@ static void __init balloon3_init_irq(void)
         pxa27x_init_irq();
         /* setup extra Balloon3 irqs */
         for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
-                set_irq_chip(irq, &balloon3_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &balloon3_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
-        set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
+        irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
+        irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
 
         pr_debug("%s: chained handler installed - irq %d automatically "
                 "enabled\n", __func__, BALLOON3_AUX_NIRQ);
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index a2380cd76f80..8b1a30959fae 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio)
 
         cmx2xx_it8152_irq_gpio = irq_gpio;
 
-        set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
 
-        set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux);
+        irq_set_chained_handler(gpio_to_irq(irq_gpio),
+                                cmx2xx_it8152_irq_demux);
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index bfca7ed2fea3..06d0a03f462d 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void)
 {
         pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
         i2c_register_board_info(1, &cm_x300_pmic_info, 1);
-        set_irq_wake(IRQ_WAKEUP0, 1);
+        irq_set_irq_wake(IRQ_WAKEUP0, 1);
 }
 
 static void __init cm_x300_init_wi2wi(void)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 2693e3c3776f..6251e3f5c62c 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
         GEDR0 = 0x3;
 
         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
-                set_irq_chip(irq, &pxa_low_gpio_chip);
-                set_irq_chip_data(irq, irq_base(0));
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &pxa_low_gpio_chip,
+                                         handle_edge_irq);
+                irq_set_chip_data(irq, irq_base(0));
                 set_irq_flags(irq, IRQF_VALID);
         }
 
@@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
                                 __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
 
                         irq = PXA_IRQ(i);
-                        set_irq_chip(irq, &pxa_internal_irq_chip);
-                        set_irq_chip_data(irq, base);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &pxa_internal_irq_chip,
+                                                 handle_level_irq);
+                        irq_set_chip_data(irq, base);
                         set_irq_flags(irq, IRQF_VALID);
                 }
         }
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index c9a3e775c2de..6307f70ae22a 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void)
 
         /* setup extra LogicPD PXA270 irqs */
         for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
-                set_irq_chip(irq, &lpd270_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &lpd270_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
-        set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
-        set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
+        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
 }
 
 
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index dca20de306bb..0fea945dd6f2 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void)
 
         /* setup extra lubbock irqs */
         for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
-                set_irq_chip(irq, &lubbock_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &lubbock_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
-        set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
+        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index f9542220595a..29b6e7a94e11 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void)
 
         /* setup extra Mainstone irqs */
         for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
-                set_irq_chip(irq, &mainstone_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &mainstone_irq_chip,
+                                         handle_level_irq);
                 if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
                 else
@@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void)
         MST_INTMSKENA = 0;
         MST_INTSETCLR = 0;
 
-        set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
-        set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
+        irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
+        irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
 }
 
 #ifdef CONFIG_PM
diff --git a/arch/arm/mach-pxa/pcm990-baseboard.c b/arch/arm/mach-pxa/pcm990-baseboard.c
index 9dbf3ccd4150..4d0120540124 100644
--- a/arch/arm/mach-pxa/pcm990-baseboard.c
+++ b/arch/arm/mach-pxa/pcm990-baseboard.c
@@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void)
 
         /* setup extra PCM990 irqs */
         for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
-                set_irq_chip(irq, &pcm990_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &pcm990_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         PCM990_INTMSKENA = 0x00;        /* disable all Interrupts */
         PCM990_INTSETCLR = 0xFF;
 
-        set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
-        set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
+        irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
+        irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
 }
 
 static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index f374247b8466..8dd107391157 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
         int irq;
 
         for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
-                set_irq_chip(irq, &pxa_ext_wakeup_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &pxa_ext_wakeup_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 12279214c875..aa70331c0805 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -310,14 +310,14 @@ static void __init viper_init_irq(void)
         /* setup ISA IRQs */
         for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
                 isa_irq = viper_bit_to_irq(level);
-                set_irq_chip(isa_irq, &viper_irq_chip);
-                set_irq_handler(isa_irq, handle_edge_irq);
+                irq_set_chip_and_handler(isa_irq, &viper_irq_chip,
+                                         handle_edge_irq);
                 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
+        irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
                                 viper_irq_handler);
-        set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
+        irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
 }
 
 /* Flat Panel */
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 730f51e57c17..139aa7f2ed90 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -136,22 +136,23 @@ static void __init zeus_init_irq(void)
 
         /* Peripheral IRQs. It would be nice to move those inside driver
            configuration, but it is not supported at the moment. */
-        set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO),       IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO),     IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO),        IRQ_TYPE_EDGE_RISING);
-        set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),    IRQ_TYPE_EDGE_FALLING);
-        set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO),        IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
+                         IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
 
         /* Setup ISA IRQs */
         for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
                 isa_irq = zeus_bit_to_irq(level);
-                set_irq_chip(isa_irq, &zeus_irq_chip);
-                set_irq_handler(isa_irq, handle_edge_irq);
+                irq_set_chip_and_handler(isa_irq, &zeus_irq_chip,
+                                         handle_edge_irq);
                 set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
         }
 
-        set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
-        set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
+        irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
+        irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
 }
 
 
diff --git a/arch/arm/mach-rpc/irq.c b/arch/arm/mach-rpc/irq.c
index d29cd9b737fc..2e1b5309fbab 100644
--- a/arch/arm/mach-rpc/irq.c
+++ b/arch/arm/mach-rpc/irq.c
@@ -133,25 +133,25 @@ void __init rpc_init_irq(void)
 
                 switch (irq) {
                 case 0 ... 7:
-                        set_irq_chip(irq, &iomd_a_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &iomd_a_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, flags);
                         break;
 
                 case 8 ... 15:
-                        set_irq_chip(irq, &iomd_b_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &iomd_b_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, flags);
                         break;
 
                 case 16 ... 21:
-                        set_irq_chip(irq, &iomd_dma_chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_and_handler(irq, &iomd_dma_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, flags);
                         break;
 
                 case 64 ... 71:
-                        set_irq_chip(irq, &iomd_fiq_chip);
+                        irq_set_chip(irq, &iomd_fiq_chip);
                         set_irq_flags(irq, IRQF_VALID);
                         break;
                 }
diff --git a/arch/arm/mach-s3c2410/bast-irq.c b/arch/arm/mach-s3c2410/bast-irq.c
index 606cb6b1cc47..bc53d2d16d1a 100644
--- a/arch/arm/mach-s3c2410/bast-irq.c
+++ b/arch/arm/mach-s3c2410/bast-irq.c
@@ -147,15 +147,15 @@ static __init int bast_irq_init(void)
 
                 __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
 
-                set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
+                irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
 
                 /* register our IRQs */
 
                 for (i = 0; i < 4; i++) {
                         unsigned int irqno = bast_pc104_irqs[i];
 
-                        set_irq_chip(irqno, &bast_pc104_chip);
-                        set_irq_handler(irqno, handle_level_irq);
+                        irq_set_chip_and_handler(irqno, &bast_pc104_chip,
+                                                 handle_level_irq);
                         set_irq_flags(irqno, IRQF_VALID);
                 }
         }
diff --git a/arch/arm/mach-s3c2412/irq.c b/arch/arm/mach-s3c2412/irq.c
index eddb52ba5b65..f3355d2ec634 100644
--- a/arch/arm/mach-s3c2412/irq.c
+++ b/arch/arm/mach-s3c2412/irq.c
@@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
         unsigned int irqno;
 
         for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
-                set_irq_chip(irqno, &s3c2412_irq_eint0t4);
-                set_irq_handler(irqno, handle_edge_irq);
+                irq_set_chip_and_handler(irqno, &s3c2412_irq_eint0t4,
+                                         handle_edge_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
         /* add demux support for CF/SDI */
 
-        set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
+        irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
 
         for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
-                set_irq_chip(irqno, &s3c2412_irq_cfsdi);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &s3c2412_irq_cfsdi,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
@@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
         s3c2412_irq_rtc_chip = s3c_irq_chip;
         s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
 
-        set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
+        irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
 
         return 0;
 }
diff --git a/arch/arm/mach-s3c2416/irq.c b/arch/arm/mach-s3c2416/irq.c
index 680fe386aca5..77b38f2381c1 100644
--- a/arch/arm/mach-s3c2416/irq.c
+++ b/arch/arm/mach-s3c2416/irq.c
@@ -202,13 +202,11 @@ static int __init s3c2416_add_sub(unsigned int base,
 {
         unsigned int irqno;
 
-        set_irq_chip(base, &s3c_irq_level_chip);
-        set_irq_handler(base, handle_level_irq);
-        set_irq_chained_handler(base, demux);
+        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
+        irq_set_chained_handler(base, demux);
 
         for (irqno = start; irqno <= end; irqno++) {
-                set_irq_chip(irqno, chip);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
diff --git a/arch/arm/mach-s3c2440/irq.c b/arch/arm/mach-s3c2440/irq.c
index acad4428bef0..eb1cc0f0705e 100644
--- a/arch/arm/mach-s3c2440/irq.c
+++ b/arch/arm/mach-s3c2440/irq.c
@@ -100,13 +100,13 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
 
         /* add new chained handler for wdt, ac7 */
 
-        set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
-        set_irq_handler(IRQ_WDT, handle_level_irq);
-        set_irq_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
+        irq_set_chip_and_handler(IRQ_WDT, &s3c_irq_level_chip,
+                                 handle_level_irq);
+        irq_set_chained_handler(IRQ_WDT, s3c_irq_demux_wdtac97);
 
         for (irqno = IRQ_S3C2440_WDT; irqno <= IRQ_S3C2440_AC97; irqno++) {
-                set_irq_chip(irqno, &s3c_irq_wdtac97);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irq_wdtac97,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
diff --git a/arch/arm/mach-s3c2440/s3c244x-irq.c b/arch/arm/mach-s3c2440/s3c244x-irq.c
index 83daf4ece764..de07c2feaa32 100644
--- a/arch/arm/mach-s3c2440/s3c244x-irq.c
+++ b/arch/arm/mach-s3c2440/s3c244x-irq.c
@@ -95,19 +95,19 @@ static int s3c244x_irq_add(struct sys_device *sysdev)
 {
         unsigned int irqno;
 
-        set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
-        set_irq_handler(IRQ_NFCON, handle_level_irq);
+        irq_set_chip_and_handler(IRQ_NFCON, &s3c_irq_level_chip,
+                                 handle_level_irq);
         set_irq_flags(IRQ_NFCON, IRQF_VALID);
 
         /* add chained handler for camera */
 
-        set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
-        set_irq_handler(IRQ_CAM, handle_level_irq);
-        set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
+        irq_set_chip_and_handler(IRQ_CAM, &s3c_irq_level_chip,
+                                 handle_level_irq);
+        irq_set_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
 
         for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
-                set_irq_chip(irqno, &s3c_irq_cam);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irq_cam,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
diff --git a/arch/arm/mach-s3c2443/irq.c b/arch/arm/mach-s3c2443/irq.c
index c7820f9c1352..83ecb1173fb1 100644
--- a/arch/arm/mach-s3c2443/irq.c
+++ b/arch/arm/mach-s3c2443/irq.c
@@ -230,13 +230,11 @@ static int __init s3c2443_add_sub(unsigned int base,
 {
         unsigned int irqno;
 
-        set_irq_chip(base, &s3c_irq_level_chip);
-        set_irq_handler(base, handle_level_irq);
-        set_irq_chained_handler(base, demux);
+        irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
+        irq_set_chained_handler(base, demux);
 
         for (irqno = start; irqno <= end; irqno++) {
-                set_irq_chip(irqno, chip);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, chip, handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
diff --git a/arch/arm/mach-s3c64xx/irq-eint.c b/arch/arm/mach-s3c64xx/irq-eint.c
index 2ead8189da74..4d203be1f4c3 100644
--- a/arch/arm/mach-s3c64xx/irq-eint.c
+++ b/arch/arm/mach-s3c64xx/irq-eint.c
@@ -197,16 +197,15 @@ static int __init s3c64xx_init_irq_eint(void)
         int irq;
 
         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
-                set_irq_chip(irq, &s3c_irq_eint);
-                set_irq_chip_data(irq, (void *)eint_irq_to_bit(irq));
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
+                irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
-        set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
-        set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
-        set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
+        irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
+        irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
+        irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
+        irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 
         return 0;
 }
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index b8d02eb4cf30..a5c00952ea35 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -119,7 +119,7 @@ void __init s5p6450_map_io(void)
         s3c_adc_setname("s3c64xx-adc");
 
         iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
-        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6440_iodesc));
+        iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
 }
 
 /*
diff --git a/arch/arm/mach-s5pv210/include/mach/irqs.h b/arch/arm/mach-s5pv210/include/mach/irqs.h
index 26710b35ef87..b9f9ec33384d 100644
--- a/arch/arm/mach-s5pv210/include/mach/irqs.h
+++ b/arch/arm/mach-s5pv210/include/mach/irqs.h
@@ -99,9 +99,9 @@
 #define IRQ_TC                  IRQ_PENDN
 #define IRQ_KEYPAD              S5P_IRQ_VIC2(25)
 #define IRQ_CG                  S5P_IRQ_VIC2(26)
-#define IRQ_SEC                 S5P_IRQ_VIC2(27)
-#define IRQ_SECRX               S5P_IRQ_VIC2(28)
-#define IRQ_SECTX               S5P_IRQ_VIC2(29)
+#define IRQ_SSS_INT             S5P_IRQ_VIC2(27)
+#define IRQ_SSS_HASH            S5P_IRQ_VIC2(28)
+#define IRQ_PCM2                S5P_IRQ_VIC2(29)
 #define IRQ_SDMIRQ              S5P_IRQ_VIC2(30)
 #define IRQ_SDMFIQ              S5P_IRQ_VIC2(31)
 
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index bc08ac42e7cc..c6a9e86c2d5c 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -44,7 +44,6 @@
 #include <plat/keypad.h>
 #include <plat/pm.h>
 #include <plat/fb.h>
-#include <plat/gpio-cfg.h>
 #include <plat/s5p-time.h>
 
 /* Following are default values for UCON, ULCON and UFCON UART registers */
diff --git a/arch/arm/mach-sa1100/cerf.c b/arch/arm/mach-sa1100/cerf.c
index 98d780608c7e..7f3da4b11ec9 100644
--- a/arch/arm/mach-sa1100/cerf.c
+++ b/arch/arm/mach-sa1100/cerf.c
@@ -96,7 +96,7 @@ static struct resource cerf_flash_resource = {
 static void __init cerf_init_irq(void)
 {
         sa1100_init_irq();
-        set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
+        irq_set_irq_type(CERF_ETH_IRQ, IRQ_TYPE_EDGE_RISING);
 }
 
 static struct map_desc cerf_io_desc[] __initdata = {
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index 3d85dfad9c1f..423ddb3d65e9 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -323,28 +323,28 @@ void __init sa1100_init_irq(void)
         ICCR = 1;
 
         for (irq = 0; irq <= 10; irq++) {
-                set_irq_chip(irq, &sa1100_low_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &sa1100_low_gpio_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         for (irq = 12; irq <= 31; irq++) {
-                set_irq_chip(irq, &sa1100_normal_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &sa1100_normal_chip,
+                                         handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
         for (irq = 32; irq <= 48; irq++) {
-                set_irq_chip(irq, &sa1100_high_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &sa1100_high_gpio_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         /*
          * Install handler for GPIO 11-27 edge detect interrupts
          */
-        set_irq_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
-        set_irq_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
+        irq_set_chip(IRQ_GPIO11_27, &sa1100_normal_chip);
+        irq_set_chained_handler(IRQ_GPIO11_27, sa1100_high_gpio_handler);
 
         sa1100_init_gpio();
 }
diff --git a/arch/arm/mach-sa1100/neponset.c b/arch/arm/mach-sa1100/neponset.c
index 4aad01f73660..b4fa53a1427e 100644
--- a/arch/arm/mach-sa1100/neponset.c
+++ b/arch/arm/mach-sa1100/neponset.c
@@ -145,8 +145,8 @@ static int __devinit neponset_probe(struct platform_device *dev)
         /*
          * Install handler for GPIO25.
          */
-        set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
-        set_irq_chained_handler(IRQ_GPIO25, neponset_irq_handler);
+        irq_set_irq_type(IRQ_GPIO25, IRQ_TYPE_EDGE_RISING);
+        irq_set_chained_handler(IRQ_GPIO25, neponset_irq_handler);
 
         /*
          * We would set IRQ_GPIO25 to be a wake-up IRQ, but
@@ -161,9 +161,9 @@ static int __devinit neponset_probe(struct platform_device *dev)
          * Setup other Neponset IRQs.  SA1111 will be done by the
          * generic SA1111 code.
          */
-        set_irq_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
+        irq_set_handler(IRQ_NEPONSET_SMC9196, handle_simple_irq);
         set_irq_flags(IRQ_NEPONSET_SMC9196, IRQF_VALID | IRQF_PROBE);
-        set_irq_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
+        irq_set_handler(IRQ_NEPONSET_USAR, handle_simple_irq);
         set_irq_flags(IRQ_NEPONSET_USAR, IRQF_VALID | IRQF_PROBE);
 
         /*
diff --git a/arch/arm/mach-sa1100/pleb.c b/arch/arm/mach-sa1100/pleb.c
index 42b80400c100..65161f2bea29 100644
--- a/arch/arm/mach-sa1100/pleb.c
+++ b/arch/arm/mach-sa1100/pleb.c
@@ -142,7 +142,7 @@ static void __init pleb_map_io(void)
 
         GPDR &= ~GPIO_ETH0_IRQ;
 
-        set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
+        irq_set_irq_type(GPIO_ETH0_IRQ, IRQ_TYPE_EDGE_FALLING);
 }
 
 MACHINE_START(PLEB, "PLEB")
diff --git a/arch/arm/mach-shark/irq.c b/arch/arm/mach-shark/irq.c
index 831fc66dfa4d..5dce13e429f3 100644
--- a/arch/arm/mach-shark/irq.c
+++ b/arch/arm/mach-shark/irq.c
@@ -80,8 +80,7 @@ void __init shark_init_irq(void)
         int irq;
 
         for (irq = 0; irq < NR_IRQS; irq++) {
-                set_irq_chip(irq, &fb_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &fb_chip, handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index a94f29da5d30..783b66fa95fb 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -24,9 +24,9 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/delay.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
@@ -312,7 +312,7 @@ static struct resource sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0xe6850000,
-                .end    = 0xe68501ff,
+                .end    = 0xe68500ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -345,7 +345,7 @@ static struct resource sdhi1_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0xe6860000,
-                .end    = 0xe68601ff,
+                .end    = 0xe68600ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -1255,7 +1255,7 @@ static void __init ap4evb_init(void)
         gpio_request(GPIO_FN_KEYIN4,     NULL);
 
         /* enable TouchScreen */
-        set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ28, IRQ_TYPE_LEVEL_LOW);
 
         tsc_device.irq = IRQ28;
         i2c_register_board_info(1, &tsc_device, 1);
@@ -1311,7 +1311,7 @@ static void __init ap4evb_init(void)
         lcdc_info.ch[0].lcd_size_cfg.height     = 91;
 
         /* enable TouchScreen */
-        set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
         tsc_device.irq = IRQ7;
         i2c_register_board_info(0, &tsc_device, 1);
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index dee3e9231fb9..c87a7b7c5832 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -31,7 +31,7 @@
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
 #include <linux/mmc/host.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/gpio.h>
 #include <mach/sh7377.h>
 #include <mach/common.h>
@@ -205,7 +205,7 @@ static struct resource sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0xe6d50000,
-                .end    = 0xe6d501ff,
+                .end    = 0xe6d50nff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -232,7 +232,7 @@ static struct resource sdhi1_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0xe6d60000,
-                .end    = 0xe6d601ff,
+                .end    = 0xe6d600ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 49bc07482179..8184d4d4f234 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -32,10 +32,10 @@
 #include <linux/io.h>
 #include <linux/i2c.h>
 #include <linux/leds.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/partitions.h>
 #include <linux/mtd/physmap.h>
@@ -690,7 +690,7 @@ static struct resource sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0xe6850000,
-                .end    = 0xe68501ff,
+                .end    = 0xe68500ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -725,7 +725,7 @@ static struct resource sdhi1_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0xe6860000,
-                .end    = 0xe68601ff,
+                .end    = 0xe68600ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -768,7 +768,7 @@ static struct resource sdhi2_resources[] = {
         [0] = {
                 .name   = "SDHI2",
                 .start  = 0xe6870000,
-                .end    = 0xe68701ff,
+                .end    = 0xe68700ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -1124,15 +1124,15 @@ static void __init mackerel_init(void)
 
         /* enable Keypad */
         gpio_request(GPIO_FN_IRQ9_42,   NULL);
-        set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
+        irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
 
         /* enable Touchscreen */
         gpio_request(GPIO_FN_IRQ7_40,   NULL);
-        set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
+        irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
 
         /* enable Accelerometer */
         gpio_request(GPIO_FN_IRQ21,     NULL);
-        set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
+        irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
 
         /* enable SDHI0 */
         gpio_request(GPIO_FN_SDHICD0, NULL);
diff --git a/arch/arm/mach-shmobile/intc-sh7367.c b/arch/arm/mach-shmobile/intc-sh7367.c
index 2fe9704d5ea1..cc442d198cdc 100644
--- a/arch/arm/mach-shmobile/intc-sh7367.c
+++ b/arch/arm/mach-shmobile/intc-sh7367.c
@@ -421,7 +421,7 @@ static struct intc_desc intcs_desc __initdata = {
 
 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
 {
-        void __iomem *reg = (void *)get_irq_data(irq);
+        void __iomem *reg = (void *)irq_get_handler_data(irq);
         unsigned int evtcodeas = ioread32(reg);
 
         generic_handle_irq(intcs_evt2irq(evtcodeas));
@@ -435,6 +435,6 @@ void __init sh7367_init_irq(void)
         register_intc_controller(&intcs_desc);
 
         /* demux using INTEVTSA */
-        set_irq_data(evt2irq(0xf80), (void *)intevtsa);
-        set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
+        irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
+        irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
 }
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index ca5f9d17b39a..7a4960f9c1e3 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -601,7 +601,7 @@ static struct intc_desc intcs_desc __initdata = {
 
 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
 {
-        void __iomem *reg = (void *)get_irq_data(irq);
+        void __iomem *reg = (void *)irq_get_handler_data(irq);
         unsigned int evtcodeas = ioread32(reg);
 
         generic_handle_irq(intcs_evt2irq(evtcodeas));
@@ -615,6 +615,6 @@ void __init sh7372_init_irq(void)
         register_intc_controller(&intcs_desc);
 
         /* demux using INTEVTSA */
-        set_irq_data(evt2irq(0xf80), (void *)intevtsa);
-        set_irq_chained_handler(evt2irq(0xf80), intcs_demux);
+        irq_set_handler_data(evt2irq(0xf80), (void *)intevtsa);
+        irq_set_chained_handler(evt2irq(0xf80), intcs_demux);
 }
diff --git a/arch/arm/mach-shmobile/intc-sh7377.c b/arch/arm/mach-shmobile/intc-sh7377.c
index dd568382cc9f..fe45154ce660 100644
--- a/arch/arm/mach-shmobile/intc-sh7377.c
+++ b/arch/arm/mach-shmobile/intc-sh7377.c
@@ -626,7 +626,7 @@ static struct intc_desc intcs_desc __initdata = {
 
 static void intcs_demux(unsigned int irq, struct irq_desc *desc)
 {
-        void __iomem *reg = (void *)get_irq_data(irq);
+        void __iomem *reg = (void *)irq_get_handler_data(irq);
         unsigned int evtcodeas = ioread32(reg);
 
         generic_handle_irq(intcs_evt2irq(evtcodeas));
@@ -641,6 +641,6 @@ void __init sh7377_init_irq(void)
         register_intc_controller(&intcs_desc);
 
         /* demux using INTEVTSA */
-        set_irq_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
-        set_irq_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
+        irq_set_handler_data(evt2irq(INTCS_INTVECT), (void *)intevtsa);
+        irq_set_chained_handler(evt2irq(INTCS_INTVECT), intcs_demux);
 }
diff --git a/arch/arm/mach-tcc8k/irq.c b/arch/arm/mach-tcc8k/irq.c
index aa9231f4fc6e..209fa5c65d4c 100644
--- a/arch/arm/mach-tcc8k/irq.c
+++ b/arch/arm/mach-tcc8k/irq.c
@@ -102,10 +102,10 @@ void __init tcc8k_init_irq(void)
 
         for (irqno = 0; irqno < NR_IRQS; irqno++) {
                 if (irqno < 32)
-                        set_irq_chip(irqno, &tcc8000_irq_chip0);
+                        irq_set_chip(irqno, &tcc8000_irq_chip0);
                 else
-                        set_irq_chip(irqno, &tcc8000_irq_chip1);
-                set_irq_handler(irqno, handle_level_irq);
+                        irq_set_chip(irqno, &tcc8000_irq_chip1);
+                irq_set_handler(irqno, handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 12090a2cf3e0..76a3f654220f 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -208,9 +208,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
         spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
 
         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-                __set_irq_handler_unlocked(d->irq, handle_level_irq);
+                __irq_set_handler_locked(d->irq, handle_level_irq);
         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                __set_irq_handler_unlocked(d->irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
 
         return 0;
 }
@@ -224,7 +224,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
 
-        bank = get_irq_data(irq);
+        bank = irq_get_handler_data(irq);
 
         for (port = 0; port < 4; port++) {
                 int gpio = tegra_gpio_compose(bank->bank, port, 0);
@@ -275,13 +275,6 @@ void tegra_gpio_resume(void)
         }
 
         local_irq_restore(flags);
-
-        for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
-                struct irq_desc *desc = irq_to_desc(i);
-                if (!desc || (desc->status & IRQ_WAKEUP))
-                        continue;
-                enable_irq(i);
-        }
 }
 
 void tegra_gpio_suspend(void)
@@ -289,18 +282,6 @@ void tegra_gpio_suspend(void)
         unsigned long flags;
         int b, p, i;
 
-        for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
-                struct irq_desc *desc = irq_to_desc(i);
-                if (!desc)
-                        continue;
-                if (desc->status & IRQ_WAKEUP) {
-                        int gpio = i - INT_GPIO_BASE;
-                        pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7);
-                        continue;
-                }
-                disable_irq(i);
-        }
-
         local_irq_save(flags);
         for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) {
                 struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
@@ -320,7 +301,7 @@ void tegra_gpio_suspend(void)
 static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
 {
         struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
-        return set_irq_wake(bank->irq, enable);
+        return irq_set_irq_wake(bank->irq, enable);
 }
 #endif
 
@@ -359,18 +340,18 @@ static int __init tegra_gpio_init(void)
         for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) {
                 bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))];
 
-                lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class);
-                set_irq_chip_data(i, bank);
-                set_irq_chip(i, &tegra_gpio_irq_chip);
-                set_irq_handler(i, handle_simple_irq);
+                irq_set_lockdep_class(i, &gpio_lock_class);
+                irq_set_chip_data(i, bank);
+                irq_set_chip_and_handler(i, &tegra_gpio_irq_chip,
+                                         handle_simple_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
         for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) {
                 bank = &tegra_gpio_banks[i];
 
-                set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler);
-                set_irq_data(bank->irq, bank);
+                irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
+                irq_set_handler_data(bank->irq, bank);
 
                 for (j = 0; j < 4; j++)
                         spin_lock_init(&bank->lvl_lock[j]);
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index dfbc219ea492..4330d8995b27 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -144,7 +144,7 @@ void __init tegra_init_irq(void)
         gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
                  IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
 
-        gic = get_irq_chip(29);
+        gic = irq_get_chip(29);
         tegra_gic_unmask_irq = gic->irq_unmask;
         tegra_gic_mask_irq = gic->irq_mask;
         tegra_gic_ack_irq = gic->irq_ack;
@@ -154,8 +154,7 @@ void __init tegra_init_irq(void)
 
         for (i = 0; i < INT_MAIN_NR; i++) {
                 irq = INT_PRI_BASE + i;
-                set_irq_chip(irq, &tegra_irq);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 }
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 203b986280f5..58626013aa32 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -23,6 +23,7 @@ menu "Ux500 target platform"
 config MACH_U8500
         bool "U8500 Development platform"
         depends on UX500_SOC_DB8500
+        select TPS6105X
         help
           Include support for the mop500 development platform.
 
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 875c91b2f8a4..9ed0f90cfe23 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -13,6 +13,30 @@
 #include <linux/regulator/ab8500.h>
 #include "board-mop500-regulators.h"
 
+/*
+ * TPS61052 regulator
+ */
+static struct regulator_consumer_supply tps61052_vaudio_consumers[] = {
+        /*
+         * Boost converter supply to raise voltage on audio speaker, this
+         * is actually connected to three pins, VInVhfL (left amplifier)
+         * VInVhfR (right amplifier) and VIntDClassInt - all three must
+         * be connected to the same voltage.
+         */
+        REGULATOR_SUPPLY("vintdclassint", "ab8500-codec.0"),
+};
+
+struct regulator_init_data tps61052_regulator = {
+        .constraints = {
+                .name = "vaudio-hf",
+                .min_uV = 4500000,
+                .max_uV = 4500000,
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(tps61052_vaudio_consumers),
+        .consumer_supplies = tps61052_vaudio_consumers,
+};
+
 static struct regulator_consumer_supply ab8500_vaux1_consumers[] = {
         /* External displays, connector on board 2v5 power supply */
         REGULATOR_SUPPLY("vaux12v5", "mcde.0"),
@@ -62,6 +86,182 @@ static struct regulator_consumer_supply ab8500_vana_consumers[] = {
         REGULATOR_SUPPLY("vsmps2", "mcde.0"),
 };
 
+/* ab8500 regulator register initialization */
+struct ab8500_regulator_reg_init
+ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS] = {
+        /*
+         * VanaRequestCtrl          = HP/LP depending on VxRequest
+         * VextSupply1RequestCtrl   = HP/LP depending on VxRequest
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL2, 0x00),
+        /*
+         * VextSupply2RequestCtrl   = HP/LP depending on VxRequest
+         * VextSupply3RequestCtrl   = HP/LP depending on VxRequest
+         * Vaux1RequestCtrl         = HP/LP depending on VxRequest
+         * Vaux2RequestCtrl         = HP/LP depending on VxRequest
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL3, 0x00),
+        /*
+         * Vaux3RequestCtrl         = HP/LP depending on VxRequest
+         * SwHPReq                  = Control through SWValid disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUREQUESTCTRL4, 0x00),
+        /*
+         * VanaSysClkReq1HPValid    = disabled
+         * Vaux1SysClkReq1HPValid   = disabled
+         * Vaux2SysClkReq1HPValid   = disabled
+         * Vaux3SysClkReq1HPValid   = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID1, 0x00),
+        /*
+         * VextSupply1SysClkReq1HPValid = disabled
+         * VextSupply2SysClkReq1HPValid = disabled
+         * VextSupply3SysClkReq1HPValid = SysClkReq1 controlled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQ1HPVALID2, 0x40),
+        /*
+         * VanaHwHPReq1Valid        = disabled
+         * Vaux1HwHPreq1Valid       = disabled
+         * Vaux2HwHPReq1Valid       = disabled
+         * Vaux3HwHPReqValid        = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID1, 0x00),
+        /*
+         * VextSupply1HwHPReq1Valid = disabled
+         * VextSupply2HwHPReq1Valid = disabled
+         * VextSupply3HwHPReq1Valid = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ1VALID2, 0x00),
+        /*
+         * VanaHwHPReq2Valid        = disabled
+         * Vaux1HwHPReq2Valid       = disabled
+         * Vaux2HwHPReq2Valid       = disabled
+         * Vaux3HwHPReq2Valid       = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID1, 0x00),
+        /*
+         * VextSupply1HwHPReq2Valid = disabled
+         * VextSupply2HwHPReq2Valid = disabled
+         * VextSupply3HwHPReq2Valid = HWReq2 controlled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUHWHPREQ2VALID2, 0x04),
+        /*
+         * VanaSwHPReqValid         = disabled
+         * Vaux1SwHPReqValid        = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID1, 0x00),
+        /*
+         * Vaux2SwHPReqValid        = disabled
+         * Vaux3SwHPReqValid        = disabled
+         * VextSupply1SwHPReqValid  = disabled
+         * VextSupply2SwHPReqValid  = disabled
+         * VextSupply3SwHPReqValid  = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUSWHPREQVALID2, 0x00),
+        /*
+         * SysClkReq2Valid1         = SysClkReq2 controlled
+         * SysClkReq3Valid1         = disabled
+         * SysClkReq4Valid1         = SysClkReq4 controlled
+         * SysClkReq5Valid1         = disabled
+         * SysClkReq6Valid1         = SysClkReq6 controlled
+         * SysClkReq7Valid1         = disabled
+         * SysClkReq8Valid1         = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID1, 0x2a),
+        /*
+         * SysClkReq2Valid2         = disabled
+         * SysClkReq3Valid2         = disabled
+         * SysClkReq4Valid2         = disabled
+         * SysClkReq5Valid2         = disabled
+         * SysClkReq6Valid2         = SysClkReq6 controlled
+         * SysClkReq7Valid2         = disabled
+         * SysClkReq8Valid2         = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUSYSCLKREQVALID2, 0x20),
+        /*
+         * VTVoutEna                = disabled
+         * Vintcore12Ena            = disabled
+         * Vintcore12Sel            = 1.25 V
+         * Vintcore12LP             = inactive (HP)
+         * VTVoutLP                 = inactive (HP)
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUMISC1, 0x10),
+        /*
+         * VaudioEna                = disabled
+         * VdmicEna                 = disabled
+         * Vamic1Ena                = disabled
+         * Vamic2Ena                = disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VAUDIOSUPPLY, 0x00),
+        /*
+         * Vamic1_dzout             = high-Z when Vamic1 is disabled
+         * Vamic2_dzout             = high-Z when Vamic2 is disabled
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRL1VAMIC, 0x00),
+        /*
+         * VPll                     = Hw controlled
+         * VanaRegu                 = force off
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VPLLVANAREGU, 0x02),
+        /*
+         * VrefDDREna               = disabled
+         * VrefDDRSleepMode         = inactive (no pulldown)
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VREFDDR, 0x00),
+        /*
+         * VextSupply1Regu          = HW control
+         * VextSupply2Regu          = HW control
+         * VextSupply3Regu          = HW control
+         * ExtSupply2Bypass         = ExtSupply12LPn ball is 0 when Ena is 0
+         * ExtSupply3Bypass         = ExtSupply3LPn ball is 0 when Ena is 0
+         */
+        INIT_REGULATOR_REGISTER(AB8500_EXTSUPPLYREGU, 0x2a),
+        /*
+         * Vaux1Regu                = force HP
+         * Vaux2Regu                = force off
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VAUX12REGU, 0x01),
+        /*
+         * Vaux3regu                = force off
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3REGU, 0x00),
+        /*
+         * Vsmps1                   = 1.15V
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VSMPS1SEL1, 0x24),
+        /*
+         * Vaux1Sel                 = 2.5 V
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VAUX1SEL, 0x08),
+        /*
+         * Vaux2Sel                 = 2.9 V
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VAUX2SEL, 0x0d),
+        /*
+         * Vaux3Sel                 = 2.91 V
+         */
+        INIT_REGULATOR_REGISTER(AB8500_VRF1VAUX3SEL, 0x07),
+        /*
+         * VextSupply12LP           = disabled (no LP)
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRL2SPARE, 0x00),
+        /*
+         * Vaux1Disch               = short discharge time
+         * Vaux2Disch               = short discharge time
+         * Vaux3Disch               = short discharge time
+         * Vintcore12Disch          = short discharge time
+         * VTVoutDisch              = short discharge time
+         * VaudioDisch              = short discharge time
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH, 0x00),
+        /*
+         * VanaDisch                = short discharge time
+         * VdmicPullDownEna         = pulldown disabled when Vdmic is disabled
+         * VdmicDisch               = short discharge time
+         */
+        INIT_REGULATOR_REGISTER(AB8500_REGUCTRLDISCH2, 0x00),
+};
+
 /* AB8500 regulators */
 struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
         /* supplies to the display/camera */
@@ -72,6 +272,7 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
                         .max_uV = 2900000,
                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
                                           REGULATOR_CHANGE_STATUS,
+                        .boot_on = 1, /* must be on for display */
                 },
                 .num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
                 .consumer_supplies = ab8500_vaux1_consumers,
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.h b/arch/arm/mach-ux500/board-mop500-regulators.h
index f979b892e4fa..94992158d962 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.h
+++ b/arch/arm/mach-ux500/board-mop500-regulators.h
@@ -17,5 +17,6 @@
 extern struct ab8500_regulator_reg_init
 ab8500_regulator_reg_init[AB8500_NUM_REGULATOR_REGISTERS];
 extern struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS];
+extern struct regulator_init_data tps61052_regulator;
 
 #endif
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index d0076453d7ff..dc8746d7826e 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -22,6 +22,8 @@
 #include <linux/mfd/ab8500.h>
 #include <linux/regulator/ab8500.h>
 #include <linux/mfd/tc3589x.h>
+#include <linux/mfd/tps6105x.h>
+#include <linux/mfd/ab8500/gpio.h>
 #include <linux/leds-lp5521.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
@@ -42,10 +44,35 @@
 #include "board-mop500.h"
 #include "board-mop500-regulators.h"
 
+static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
+        .gpio_base              = MOP500_AB8500_GPIO(0),
+        .irq_base               = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
+        /* config_reg is the initial configuration of ab8500 pins.
+         * The pins can be configured as GPIO or alt functions based
+         * on value present in GpioSel1 to GpioSel6 and AlternatFunction
+         * register. This is the array of 7 configuration settings.
+         * One has to compile time decide these settings. Below is the
+         * explaination of these setting
+         * GpioSel1 = 0x00 => Pins GPIO1 to GPIO8 are not used as GPIO
+         * GpioSel2 = 0x1E => Pins GPIO10 to GPIO13 are configured as GPIO
+         * GpioSel3 = 0x80 => Pin GPIO24 is configured as GPIO
+         * GpioSel4 = 0x01 => Pin GPIo25 is configured as GPIO
+         * GpioSel5 = 0x7A => Pins GPIO34, GPIO36 to GPIO39 are conf as GPIO
+         * GpioSel6 = 0x00 => Pins GPIO41 & GPIo42 are not configured as GPIO
+         * AlternaFunction = 0x00 => If Pins GPIO10 to 13 are not configured
+         * as GPIO then this register selectes the alternate fucntions
+         */
+        .config_reg             = {0x00, 0x1E, 0x80, 0x01,
+                                        0x7A, 0x00, 0x00},
+};
+
 static struct ab8500_platform_data ab8500_platdata = {
         .irq_base       = MOP500_AB8500_IRQ_BASE,
+        .regulator_reg_init = ab8500_regulator_reg_init,
+        .num_regulator_reg_init = ARRAY_SIZE(ab8500_regulator_reg_init),
         .regulator      = ab8500_regulators,
         .num_regulator  = ARRAY_SIZE(ab8500_regulators),
+        .gpio           = &ab8500_gpio_pdata,
 };
 
 static struct resource ab8500_resources[] = {
@@ -67,6 +94,15 @@ struct platform_device ab8500_device = {
 };
 
 /*
+ * TPS61052
+ */
+
+static struct tps6105x_platform_data mop500_tps61052_data = {
+        .mode = TPS6105X_MODE_VOLTAGE,
+        .regulator_data = &tps61052_regulator,
+};
+
+/*
  * TC35892
  */
 
@@ -136,7 +172,7 @@ static struct lp5521_platform_data __initdata lp5521_sec_data = {
        .clock_mode     = LP5521_CLOCK_EXT,
 };
 
-static struct i2c_board_info mop500_i2c0_devices[] = {
+static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
         {
                 I2C_BOARD_INFO("tc3589x", 0x42),
                 .irq            = NOMADIK_GPIO_TO_IRQ(217),
@@ -144,6 +180,14 @@ static struct i2c_board_info mop500_i2c0_devices[] = {
         },
 };
 
+/* I2C0 devices only available prior to HREFv60 */
+static struct i2c_board_info __initdata mop500_i2c0_old_devices[] = {
+        {
+                I2C_BOARD_INFO("tps61052", 0x33),
+                .platform_data  = &mop500_tps61052_data,
+        },
+};
+
 static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
         {
                 /* lp5521 LED driver, 1st device */
@@ -406,6 +450,9 @@ static void __init mop500_init_machine(void)
 
         i2c_register_board_info(0, mop500_i2c0_devices,
                                 ARRAY_SIZE(mop500_i2c0_devices));
+        if (!machine_is_hrefv60())
+                i2c_register_board_info(0, mop500_i2c0_old_devices,
+                                        ARRAY_SIZE(mop500_i2c0_old_devices));
         i2c_register_board_info(2, mop500_i2c2_devices,
                                 ARRAY_SIZE(mop500_i2c2_devices));
 }
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 56722f4be71b..03a31cc9b084 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -27,6 +27,10 @@
 #define GPIO_BU21013_CS                 MOP500_EGPIO(13)
 #define GPIO_SDMMC_EN                   MOP500_EGPIO(17)
 #define GPIO_SDMMC_1V8_3V_SEL           MOP500_EGPIO(18)
+#define MOP500_EGPIO_END                MOP500_EGPIO(24)
+
+/* GPIOs on the AB8500 mixed-signals circuit */
+#define MOP500_AB8500_GPIO(x)           (MOP500_EGPIO_END + (x))
 
 struct i2c_board_info;
 
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 7cdeb2af0ebb..97ef55f84934 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -35,9 +35,20 @@
 #define MOP500_STMPE1601_IRQBASE        MOP500_EGPIO_IRQ_END
 #define MOP500_STMPE1601_IRQ(x)         (MOP500_STMPE1601_IRQBASE + (x))
 
-#define MOP500_NR_IRQS          MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
+#define MOP500_STMPE1601_IRQ_END        \
+        MOP500_STMPE1601_IRQ(STMPE_NR_INTERNAL_IRQS)
 
-#define MOP500_IRQ_END          MOP500_NR_IRQS
+/* AB8500 virtual gpio IRQ */
+#define AB8500_VIR_GPIO_NR_IRQS                 16
+
+#define MOP500_AB8500_VIR_GPIO_IRQ_BASE         \
+        MOP500_STMPE1601_IRQ_END
+#define MOP500_AB8500_VIR_GPIO_IRQ_END          \
+        (MOP500_AB8500_VIR_GPIO_IRQ_BASE + AB8500_VIR_GPIO_NR_IRQS)
+
+#define MOP500_NR_IRQS          MOP500_AB8500_VIR_GPIO_IRQ_END
+
+#define MOP500_IRQ_END          MOP500_NR_IRQS
 
 #if MOP500_IRQ_END > IRQ_BOARD_END
 #undef IRQ_BOARD_END
diff --git a/arch/arm/mach-ux500/modem-irq-db5500.c b/arch/arm/mach-ux500/modem-irq-db5500.c
index e1296a7447c8..6b86416c94c9 100644
--- a/arch/arm/mach-ux500/modem-irq-db5500.c
+++ b/arch/arm/mach-ux500/modem-irq-db5500.c
@@ -90,8 +90,7 @@ static irqreturn_t modem_cpu_irq_handler(int irq, void *data)
 
 static void create_virtual_irq(int irq, struct irq_chip *modem_irq_chip)
 {
-        set_irq_chip(irq, modem_irq_chip);
-        set_irq_handler(irq, handle_simple_irq);
+        irq_set_chip_and_handler(irq, modem_irq_chip, handle_simple_irq);
         set_irq_flags(irq, IRQF_VALID);
 
         pr_debug("modem_irq: Created virtual IRQ %d\n", irq);
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index eb7ffa0ee8b5..96e59e3ee4f5 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -314,7 +314,7 @@ static struct mmci_platform_data mmc0_plat_data = {
         .gpio_cd        = -1,
 };
 
-static struct resource char_lcd_resources[] = {
+static struct resource chalcd_resources[] = {
         {
                 .start = VERSATILE_CHAR_LCD_BASE,
                 .end   = (VERSATILE_CHAR_LCD_BASE + SZ_4K - 1),
diff --git a/arch/arm/mach-vt8500/irq.c b/arch/arm/mach-vt8500/irq.c
index 5f4ddde4f02a..245140c0df10 100644
--- a/arch/arm/mach-vt8500/irq.c
+++ b/arch/arm/mach-vt8500/irq.c
@@ -97,15 +97,15 @@ static int vt8500_irq_set_type(unsigned int irq, unsigned int flow_type)
                 return -EINVAL;
         case IRQF_TRIGGER_HIGH:
                 dctr |= VT8500_TRIGGER_HIGH;
-                irq_desc[orig_irq].handle_irq = handle_level_irq;
+                __irq_set_handler_locked(orig_irq, handle_level_irq);
                 break;
         case IRQF_TRIGGER_FALLING:
                 dctr |= VT8500_TRIGGER_FALLING;
-                irq_desc[orig_irq].handle_irq = handle_edge_irq;
+                __irq_set_handler_locked(orig_irq, handle_edge_irq);
                 break;
         case IRQF_TRIGGER_RISING:
                 dctr |= VT8500_TRIGGER_RISING;
-                irq_desc[orig_irq].handle_irq = handle_edge_irq;
+                __irq_set_handler_locked(orig_irq, handle_edge_irq);
                 break;
         }
         writeb(dctr, base + VT8500_IC_DCTR + irq);
@@ -136,8 +136,8 @@ void __init vt8500_init_irq(void)
                         /* Disable all interrupts and route them to IRQ */
                         writeb(0x00, ic_regbase + VT8500_IC_DCTR + i);
 
-                        set_irq_chip(i, &vt8500_irq_chip);
-                        set_irq_handler(i, handle_level_irq);
+                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(i, IRQF_VALID);
                 }
         } else {
@@ -167,8 +167,8 @@ void __init wm8505_init_irq(void)
                                 writeb(0x00, sic_regbase + VT8500_IC_DCTR
                                                                 + i - 64);
 
-                        set_irq_chip(i, &vt8500_irq_chip);
-                        set_irq_handler(i, handle_level_irq);
+                        irq_set_chip_and_handler(i, &vt8500_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(i, IRQF_VALID);
                 }
         } else {
diff --git a/arch/arm/mach-w90x900/irq.c b/arch/arm/mach-w90x900/irq.c
index 9c350103dcda..7bf143c443f1 100644
--- a/arch/arm/mach-w90x900/irq.c
+++ b/arch/arm/mach-w90x900/irq.c
@@ -207,8 +207,8 @@ void __init nuc900_init_irq(void)
         __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
 
         for (irqno = IRQ_WDT; irqno <= IRQ_ADC; irqno++) {
-                set_irq_chip(irqno, &nuc900_irq_chip);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &nuc900_irq_chip,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 }
diff --git a/arch/arm/plat-mxc/3ds_debugboard.c b/arch/arm/plat-mxc/3ds_debugboard.c
index c856fa397606..f0ba0726306c 100644
--- a/arch/arm/plat-mxc/3ds_debugboard.c
+++ b/arch/arm/plat-mxc/3ds_debugboard.c
@@ -100,14 +100,9 @@ static void mxc_expio_irq_handler(u32 irq, struct irq_desc *desc)
 
         expio_irq = MXC_BOARD_IRQ_START;
         for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
-                struct irq_desc *d;
                 if ((int_valid & 1) == 0)
                         continue;
-                d = irq_desc + expio_irq;
-                if (unlikely(!(d->handle_irq)))
-                        pr_err("\nEXPIO irq: %d unhandled\n", expio_irq);
-                else
-                        d->handle_irq(expio_irq, d);
+                generic_handle_irq(expio_irq);
         }
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
@@ -186,12 +181,11 @@ int __init mxc_expio_init(u32 base, u32 p_irq)
         __raw_writew(0x1F, brd_io + INTR_MASK_REG);
         for (i = MXC_EXP_IO_BASE;
              i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) {
-                set_irq_chip(i, &expio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
-        set_irq_type(p_irq, IRQF_TRIGGER_LOW);
-        set_irq_chained_handler(p_irq, mxc_expio_irq_handler);
+        irq_set_irq_type(p_irq, IRQF_TRIGGER_LOW);
+        irq_set_chained_handler(p_irq, mxc_expio_irq_handler);
 
         /* Register Lan device on the debugboard */
         smsc911x_resources[0].start = LAN9217_BASE_ADDR(base);
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index deb284bc7c4b..09e2bd0fcdca 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -139,8 +139,8 @@ void __init mxc_init_irq(void __iomem *irqbase)
         __raw_writel(0, avic_base + AVIC_INTTYPEH);
         __raw_writel(0, avic_base + AVIC_INTTYPEL);
         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
-                set_irq_chip(i, &mxc_avic_chip.base);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &mxc_avic_chip.base,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 57d59855f9ec..7a107246fd98 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         u32 irq_stat;
-        struct mxc_gpio_port *port = get_irq_data(irq);
+        struct mxc_gpio_port *port = irq_get_handler_data(irq);
 
         irq_stat = __raw_readl(port->base + GPIO_ISR) &
                         __raw_readl(port->base + GPIO_IMR);
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
 {
         int i;
         u32 irq_msk, irq_stat;
-        struct mxc_gpio_port *port = get_irq_data(irq);
+        struct mxc_gpio_port *port = irq_get_handler_data(irq);
 
         /* walk through all interrupt status registers */
         for (i = 0; i < gpio_table_size; i++) {
@@ -311,8 +311,8 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
                 __raw_writel(~0, port[i].base + GPIO_ISR);
                 for (j = port[i].virtual_irq_start;
                         j < port[i].virtual_irq_start + 32; j++) {
-                        set_irq_chip(j, &gpio_irq_chip);
-                        set_irq_handler(j, handle_level_irq);
+                        irq_set_chip_and_handler(j, &gpio_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(j, IRQF_VALID);
                 }
 
@@ -331,21 +331,23 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
 
                 if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25() || cpu_is_mx51()) {
                         /* setup one handler for each entry */
-                        set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
-                        set_irq_data(port[i].irq, &port[i]);
+                        irq_set_chained_handler(port[i].irq,
+                                                mx3_gpio_irq_handler);
+                        irq_set_handler_data(port[i].irq, &port[i]);
                         if (port[i].irq_high) {
                                 /* setup handler for GPIO 16 to 31 */
-                                set_irq_chained_handler(port[i].irq_high,
-                                                mx3_gpio_irq_handler);
-                                set_irq_data(port[i].irq_high, &port[i]);
+                                irq_set_chained_handler(port[i].irq_high,
+                                                        mx3_gpio_irq_handler);
+                                irq_set_handler_data(port[i].irq_high,
+                                                     &port[i]);
                         }
                 }
         }
 
         if (cpu_is_mx2()) {
                 /* setup one handler for all GPIO interrupts */
-                set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
-                set_irq_data(port[0].irq, port);
+                irq_set_chained_handler(port[0].irq, mx2_gpio_irq_handler);
+                irq_set_handler_data(port[0].irq, port);
         }
 
         return 0;
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index 0c799ac27730..e1c6eff7258a 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -29,7 +29,7 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio)
 
         ret = -ENOSYS;
 
-        base = get_irq_chip(irq);
+        base = irq_get_chip(irq);
         if (base) {
                 chip = container_of(base, struct mxc_irq_chip, base);
                 if (chip->set_priority)
@@ -48,7 +48,7 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
 
         ret = -ENOSYS;
 
-        base = get_irq_chip(irq);
+        base = irq_get_chip(irq);
         if (base) {
                 chip = container_of(base, struct mxc_irq_chip, base);
                 if (chip->set_irq_fiq)
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index bc3a6be8a27f..57f9395f87ce 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -167,8 +167,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
         /* all IRQ no FIQ Warning :: No selection */
 
         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
-                set_irq_chip(i, &mxc_tzic_chip.base);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
+                                         handle_level_irq);
                 set_irq_flags(i, IRQF_VALID);
         }
 
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 80643bc38e10..f49748eca1a3 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -54,6 +54,7 @@ struct nmk_gpio_chip {
         u32 rwimsc;
         u32 fwimsc;
         u32 slpm;
+        u32 enabled;
 };
 
 static struct nmk_gpio_chip *
@@ -318,7 +319,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep)
                 struct nmk_gpio_chip *nmk_chip;
                 int pin = PIN_NUM(cfgs[i]);
 
-                nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
+                nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin));
                 if (!nmk_chip) {
                         ret = -EINVAL;
                         break;
@@ -397,7 +398,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode)
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
 
-        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
         if (!nmk_chip)
                 return -EINVAL;
 
@@ -430,7 +431,7 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull)
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
 
-        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
         if (!nmk_chip)
                 return -EINVAL;
 
@@ -456,7 +457,7 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode)
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
 
-        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
         if (!nmk_chip)
                 return -EINVAL;
 
@@ -473,7 +474,7 @@ int nmk_gpio_get_mode(int gpio)
         struct nmk_gpio_chip *nmk_chip;
         u32 afunc, bfunc, bit;
 
-        nmk_chip = get_irq_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
+        nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio));
         if (!nmk_chip)
                 return -EINVAL;
 
@@ -541,13 +542,6 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
                                 int gpio, bool on)
 {
-#ifdef CONFIG_ARCH_U8500
-        if (cpu_is_u8500v2()) {
-                __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base,
-                                    on ? NMK_GPIO_SLPM_WAKEUP_ENABLE
-                                       : NMK_GPIO_SLPM_WAKEUP_DISABLE);
-        }
-#endif
         __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on);
 }
 
@@ -564,6 +558,11 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable)
         if (!nmk_chip)
                 return -EINVAL;
 
+        if (enable)
+                nmk_chip->enabled |= bitmask;
+        else
+                nmk_chip->enabled &= ~bitmask;
+
         spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
         spin_lock(&nmk_chip->lock);
 
@@ -590,8 +589,6 @@ static void nmk_gpio_irq_unmask(struct irq_data *d)
 
 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
-        bool enabled = !(desc->status & IRQ_DISABLED);
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
         u32 bitmask;
@@ -606,7 +603,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
         spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
         spin_lock(&nmk_chip->lock);
 
-        if (!enabled)
+        if (!(nmk_chip->enabled & bitmask))
                 __nmk_gpio_set_wake(nmk_chip, gpio, on);
 
         if (on)
@@ -622,9 +619,7 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
 
 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
-        bool enabled = !(desc->status & IRQ_DISABLED);
-        bool wake = desc->wake_depth;
+        bool enabled, wake = irqd_is_wakeup_set(d);
         int gpio;
         struct nmk_gpio_chip *nmk_chip;
         unsigned long flags;
@@ -641,6 +636,8 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type)
         if (type & IRQ_TYPE_LEVEL_LOW)
                 return -EINVAL;
 
+        enabled = nmk_chip->enabled & bitmask;
+
         spin_lock_irqsave(&nmk_chip->lock, flags);
 
         if (enabled)
@@ -681,7 +678,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
                                    u32 status)
 {
         struct nmk_gpio_chip *nmk_chip;
-        struct irq_chip *host_chip = get_irq_chip(irq);
+        struct irq_chip *host_chip = irq_get_chip(irq);
         unsigned int first_irq;
 
         if (host_chip->irq_mask_ack)
@@ -692,7 +689,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
                         host_chip->irq_ack(&desc->irq_data);
         }
 
-        nmk_chip = get_irq_data(irq);
+        nmk_chip = irq_get_handler_data(irq);
         first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
         while (status) {
                 int bit = __ffs(status);
@@ -706,7 +703,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
 
 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
+        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
         u32 status = readl(nmk_chip->addr + NMK_GPIO_IS);
 
         __nmk_gpio_irq_handler(irq, desc, status);
@@ -715,7 +712,7 @@ static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 static void nmk_gpio_secondary_irq_handler(unsigned int irq,
                                            struct irq_desc *desc)
 {
-        struct nmk_gpio_chip *nmk_chip = get_irq_data(irq);
+        struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq);
         u32 status = nmk_chip->get_secondary_status(nmk_chip->bank);
 
         __nmk_gpio_irq_handler(irq, desc, status);
@@ -728,20 +725,20 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip)
 
         first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
         for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) {
-                set_irq_chip(i, &nmk_gpio_irq_chip);
-                set_irq_handler(i, handle_edge_irq);
+                irq_set_chip_and_handler(i, &nmk_gpio_irq_chip,
+                                         handle_edge_irq);
                 set_irq_flags(i, IRQF_VALID);
-                set_irq_chip_data(i, nmk_chip);
-                set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
+                irq_set_chip_data(i, nmk_chip);
+                irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING);
         }
 
-        set_irq_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
-        set_irq_data(nmk_chip->parent_irq, nmk_chip);
+        irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler);
+        irq_set_handler_data(nmk_chip->parent_irq, nmk_chip);
 
         if (nmk_chip->secondary_parent_irq >= 0) {
-                set_irq_chained_handler(nmk_chip->secondary_parent_irq,
+                irq_set_chained_handler(nmk_chip->secondary_parent_irq,
                                         nmk_gpio_secondary_irq_handler);
-                set_irq_data(nmk_chip->secondary_parent_irq, nmk_chip);
+                irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip);
         }
 
         return 0;
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 971d18636942..d2adcdda23cf 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -755,18 +755,12 @@ static int gpio_irq_type(struct irq_data *d, unsigned type)
         bank = irq_data_get_irq_chip_data(d);
         spin_lock_irqsave(&bank->lock, flags);
         retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
-        if (retval == 0) {
-                struct irq_desc *desc = irq_to_desc(d->irq);
-
-                desc->status &= ~IRQ_TYPE_SENSE_MASK;
-                desc->status |= type;
-        }
         spin_unlock_irqrestore(&bank->lock, flags);
 
         if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
-                __set_irq_handler_unlocked(d->irq, handle_level_irq);
+                __irq_set_handler_locked(d->irq, handle_level_irq);
         else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
-                __set_irq_handler_unlocked(d->irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
 
         return retval;
 }
@@ -1146,7 +1140,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
 
-        bank = get_irq_data(irq);
+        bank = irq_get_handler_data(irq);
 #ifdef CONFIG_ARCH_OMAP1
         if (bank->method == METHOD_MPUIO)
                 isr_reg = bank->base +
@@ -1270,8 +1264,7 @@ static void gpio_unmask_irq(struct irq_data *d)
         unsigned int gpio = d->irq - IH_GPIO_BASE;
         struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
         unsigned int irq_mask = 1 << get_gpio_index(gpio);
-        struct irq_desc *desc = irq_to_desc(d->irq);
-        u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
+        u32 trigger = irqd_get_trigger_type(d);
 
         if (trigger)
                 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
@@ -1672,19 +1665,17 @@ static void __init omap_gpio_chip_init(struct gpio_bank *bank)
 
         for (j = bank->virtual_irq_start;
                      j < bank->virtual_irq_start + bank_width; j++) {
-                struct irq_desc *d = irq_to_desc(j);
-
-                lockdep_set_class(&d->lock, &gpio_lock_class);
-                set_irq_chip_data(j, bank);
+                irq_set_lockdep_class(j, &gpio_lock_class);
+                irq_set_chip_data(j, bank);
                 if (bank_is_mpuio(bank))
-                        set_irq_chip(j, &mpuio_irq_chip);
+                        irq_set_chip(j, &mpuio_irq_chip);
                 else
-                        set_irq_chip(j, &gpio_irq_chip);
-                set_irq_handler(j, handle_simple_irq);
+                        irq_set_chip(j, &gpio_irq_chip);
+                irq_set_handler(j, handle_simple_irq);
                 set_irq_flags(j, IRQF_VALID);
         }
-        set_irq_chained_handler(bank->irq, gpio_irq_handler);
-        set_irq_data(bank->irq, bank);
+        irq_set_chained_handler(bank->irq, gpio_irq_handler);
+        irq_set_handler_data(bank->irq, bank);
 }
 
 static int __devinit omap_gpio_probe(struct platform_device *pdev)
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 078894bc3b9a..a431a138f402 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -324,9 +324,8 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
 static void gpio_irq_ack(struct irq_data *d)
 {
         struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type;
+        int type = irqd_get_trigger_type(d);
 
-        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
                 int pin = d->irq - ochip->secondary_irq_base;
 
@@ -337,11 +336,10 @@ static void gpio_irq_ack(struct irq_data *d)
 static void gpio_irq_mask(struct irq_data *d)
 {
         struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type;
+        int type = irqd_get_trigger_type(d);
         void __iomem *reg;
         int pin;
 
-        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
                 reg = GPIO_EDGE_MASK(ochip);
         else
@@ -355,11 +353,10 @@ static void gpio_irq_mask(struct irq_data *d)
 static void gpio_irq_unmask(struct irq_data *d)
 {
         struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
-        int type;
+        int type = irqd_get_trigger_type(d);
         void __iomem *reg;
         int pin;
 
-        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
                 reg = GPIO_EDGE_MASK(ochip);
         else
@@ -389,9 +386,9 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
          * Set edge/level type.
          */
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                set_irq_handler(d->irq, handle_edge_irq);
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
         } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                set_irq_handler(d->irq, handle_level_irq);
+                __irq_set_handler_locked(d->irq, handle_level_irq);
         } else {
                 printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
                        d->irq, type);
@@ -477,10 +474,10 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
         for (i = 0; i < ngpio; i++) {
                 unsigned int irq = secondary_irq_base + i;
 
-                set_irq_chip(irq, &orion_gpio_irq_chip);
-                set_irq_handler(irq, handle_level_irq);
-                set_irq_chip_data(irq, ochip);
-                irq_desc[irq].status |= IRQ_LEVEL;
+                irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
+                                         handle_level_irq);
+                irq_set_chip_data(irq, ochip);
+                irq_set_status_flags(irq, IRQ_LEVEL);
                 set_irq_flags(irq, IRQF_VALID);
         }
 }
@@ -488,7 +485,7 @@ void __init orion_gpio_init(int gpio_base, int ngpio,
 void orion_gpio_irq_handler(int pinoff)
 {
         struct orion_gpio_chip *ochip;
-        u32 cause;
+        u32 cause, type;
         int i;
 
         ochip = orion_gpio_chip_find(pinoff);
@@ -500,15 +497,14 @@ void orion_gpio_irq_handler(int pinoff)
 
         for (i = 0; i < ochip->chip.ngpio; i++) {
                 int irq;
-                struct irq_desc *desc;
 
                 irq = ochip->secondary_irq_base + i;
 
                 if (!(cause & (1 << i)))
                         continue;
 
-                desc = irq_desc + irq;
-                if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+                type = irqd_get_trigger_type(irq_get_irq_data(irq));
+                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                         /* Swap polarity (race with GPIO line) */
                         u32 polarity;
 
@@ -516,7 +512,6 @@ void orion_gpio_irq_handler(int pinoff)
                         polarity ^= 1 << i;
                         writel(polarity, GPIO_IN_POL(ochip));
                 }
-
-                desc_handle_irq(irq, desc);
+                generic_handle_irq(irq);
         }
 }
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index 7d0c7eb59f09..d8d638e09f8f 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -56,10 +56,10 @@ void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
         for (i = 0; i < 32; i++) {
                 unsigned int irq = irq_start + i;
 
-                set_irq_chip(irq, &orion_irq_chip);
-                set_irq_chip_data(irq, maskaddr);
-                set_irq_handler(irq, handle_level_irq);
-                irq_desc[irq].status |= IRQ_LEVEL;
+                irq_set_chip_and_handler(irq, &orion_irq_chip,
+                                         handle_level_irq);
+                irq_set_chip_data(irq, maskaddr);
+                irq_set_status_flags(irq, IRQ_LEVEL);
                 set_irq_flags(irq, IRQF_VALID);
         }
 }
diff --git a/arch/arm/plat-pxa/gpio.c b/arch/arm/plat-pxa/gpio.c
index e7de6ae2a1e8..dce088f45678 100644
--- a/arch/arm/plat-pxa/gpio.c
+++ b/arch/arm/plat-pxa/gpio.c
@@ -284,13 +284,13 @@ void __init pxa_init_gpio(int mux_irq, int start, int end, set_wake_t fn)
         }
 
         for (irq  = gpio_to_irq(start); irq <= gpio_to_irq(end); irq++) {
-                set_irq_chip(irq, &pxa_muxed_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
         }
 
         /* Install handler for GPIO>=2 edge detect interrupts */
-        set_irq_chained_handler(mux_irq, pxa_gpio_demux_handler);
+        irq_set_chained_handler(mux_irq, pxa_gpio_demux_handler);
         pxa_muxed_gpio_chip.irq_set_wake = fn;
 }
 
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 4434cb56bd9a..9aee7e1668b1 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -592,8 +592,8 @@ void __init s3c24xx_init_irq(void)
                 case IRQ_UART1:
                 case IRQ_UART2:
                 case IRQ_ADCPARENT:
-                        set_irq_chip(irqno, &s3c_irq_level_chip);
-                        set_irq_handler(irqno, handle_level_irq);
+                        irq_set_chip_and_handler(irqno, &s3c_irq_level_chip,
+                                                 handle_level_irq);
                         break;
 
                 case IRQ_RESERVED6:
@@ -603,35 +603,35 @@ void __init s3c24xx_init_irq(void)
 
                 default:
                         //irqdbf("registering irq %d (s3c irq)\n", irqno);
-                        set_irq_chip(irqno, &s3c_irq_chip);
-                        set_irq_handler(irqno, handle_edge_irq);
+                        irq_set_chip_and_handler(irqno, &s3c_irq_chip,
+                                                 handle_edge_irq);
                         set_irq_flags(irqno, IRQF_VALID);
                 }
         }
 
         /* setup the cascade irq handlers */
 
-        set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
-        set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
+        irq_set_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7);
+        irq_set_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8);
 
-        set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
-        set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
-        set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
-        set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
+        irq_set_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
+        irq_set_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
+        irq_set_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
+        irq_set_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
 
         /* external interrupts */
 
         for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
                 irqdbf("registering irq %d (ext int)\n", irqno);
-                set_irq_chip(irqno, &s3c_irq_eint0t4);
-                set_irq_handler(irqno, handle_edge_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irq_eint0t4,
+                                         handle_edge_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
         for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
                 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
-                set_irq_chip(irqno, &s3c_irqext_chip);
-                set_irq_handler(irqno, handle_edge_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irqext_chip,
+                                         handle_edge_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
@@ -641,29 +641,28 @@ void __init s3c24xx_init_irq(void)
 
         for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
                 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
-                set_irq_chip(irqno, &s3c_irq_uart0);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irq_uart0,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
         for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
                 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
-                set_irq_chip(irqno, &s3c_irq_uart1);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irq_uart1,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
         for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
                 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
-                set_irq_chip(irqno, &s3c_irq_uart2);
-                set_irq_handler(irqno, handle_level_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irq_uart2,
+                                         handle_level_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
         for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
                 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
-                set_irq_chip(irqno, &s3c_irq_adc);
-                set_irq_handler(irqno, handle_edge_irq);
+                irq_set_chip_and_handler(irqno, &s3c_irq_adc, handle_edge_irq);
                 set_irq_flags(irqno, IRQF_VALID);
         }
 
diff --git a/arch/arm/plat-s5p/cpu.c b/arch/arm/plat-s5p/cpu.c
index c3bfe9b13acf..5cf5e721e6ca 100644
--- a/arch/arm/plat-s5p/cpu.c
+++ b/arch/arm/plat-s5p/cpu.c
@@ -39,7 +39,7 @@ static const char name_exynos4210[] = "EXYNOS4210";
 static struct cpu_table cpu_ids[] __initdata = {
         {
                 .idcode         = 0x56440100,
-                .idmask         = 0xffffff00,
+                .idmask         = 0xfffff000,
                 .map_io         = s5p6440_map_io,
                 .init_clocks    = s5p6440_init_clocks,
                 .init_uarts     = s5p6440_init_uarts,
@@ -47,7 +47,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .name           = name_s5p6440,
         }, {
                 .idcode         = 0x36442000,
-                .idmask         = 0xffffff00,
+                .idmask         = 0xfffff000,
                 .map_io         = s5p6442_map_io,
                 .init_clocks    = s5p6442_init_clocks,
                 .init_uarts     = s5p6442_init_uarts,
@@ -55,7 +55,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .name           = name_s5p6442,
         }, {
                 .idcode         = 0x36450000,
-                .idmask         = 0xffffff00,
+                .idmask         = 0xfffff000,
                 .map_io         = s5p6450_map_io,
                 .init_clocks    = s5p6450_init_clocks,
                 .init_uarts     = s5p6450_init_uarts,
@@ -79,7 +79,7 @@ static struct cpu_table cpu_ids[] __initdata = {
                 .name           = name_s5pv210,
         }, {
                 .idcode         = 0x43210000,
-                .idmask         = 0xfffff000,
+                .idmask         = 0xfffe0000,
                 .map_io         = exynos4_map_io,
                 .init_clocks    = exynos4_init_clocks,
                 .init_uarts     = exynos4_init_uarts,
diff --git a/arch/arm/plat-s5p/irq-eint.c b/arch/arm/plat-s5p/irq-eint.c
index 225aa25405db..b5bb774985b0 100644
--- a/arch/arm/plat-s5p/irq-eint.c
+++ b/arch/arm/plat-s5p/irq-eint.c
@@ -205,15 +205,14 @@ int __init s5p_init_irq_eint(void)
         int irq;
 
         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
-                set_irq_chip(irq, &s5p_irq_vic_eint);
+                irq_set_chip(irq, &s5p_irq_vic_eint);
 
         for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
-                set_irq_chip(irq, &s5p_irq_eint);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
+        irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
         return 0;
 }
 
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index cd87d3256e03..46dd078147d8 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -43,13 +43,13 @@ LIST_HEAD(banks);
 
 static int s5p_gpioint_get_offset(struct irq_data *data)
 {
-        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
+        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
         return data->irq - chip->irq_base;
 }
 
 static void s5p_gpioint_ack(struct irq_data *data)
 {
-        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
+        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
         int group, offset, pend_offset;
         unsigned int value;
 
@@ -64,7 +64,7 @@ static void s5p_gpioint_ack(struct irq_data *data)
 
 static void s5p_gpioint_mask(struct irq_data *data)
 {
-        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
+        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
         int group, offset, mask_offset;
         unsigned int value;
 
@@ -79,7 +79,7 @@ static void s5p_gpioint_mask(struct irq_data *data)
 
 static void s5p_gpioint_unmask(struct irq_data *data)
 {
-        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
+        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
         int group, offset, mask_offset;
         unsigned int value;
 
@@ -100,7 +100,7 @@ static void s5p_gpioint_mask_ack(struct irq_data *data)
 
 static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
 {
-        struct s3c_gpio_chip *chip = irq_data_get_irq_data(data);
+        struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
         int group, offset, con_offset;
         unsigned int value;
 
@@ -149,7 +149,7 @@ static struct irq_chip s5p_gpioint = {
 
 static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
 {
-        struct s5p_gpioint_bank *bank = get_irq_data(irq);
+        struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
         int group, pend_offset, mask_offset;
         unsigned int pend, mask;
 
@@ -200,8 +200,8 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
                 if (!bank->chips)
                         return -ENOMEM;
 
-                set_irq_chained_handler(bank->irq, s5p_gpioint_handler);
-                set_irq_data(bank->irq, bank);
+                irq_set_chained_handler(bank->irq, s5p_gpioint_handler);
+                irq_set_handler_data(bank->irq, bank);
                 bank->handler = s5p_gpioint_handler;
                 printk(KERN_INFO "Registered chained gpio int handler for interrupt %d.\n",
                        bank->irq);
@@ -219,9 +219,9 @@ static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
         bank->chips[group - bank->start] = chip;
         for (i = 0; i < chip->chip.ngpio; i++) {
                 irq = chip->irq_base + i;
-                set_irq_chip(irq, &s5p_gpioint);
-                set_irq_data(irq, chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip(irq, &s5p_gpioint);
+                irq_set_handler_data(irq, chip);
+                irq_set_handler(irq, handle_level_irq);
                 set_irq_flags(irq, IRQF_VALID);
         }
         return 0;
diff --git a/arch/arm/plat-samsung/init.c b/arch/arm/plat-samsung/init.c
index 6790edfaca6f..79d10fca9090 100644
--- a/arch/arm/plat-samsung/init.c
+++ b/arch/arm/plat-samsung/init.c
@@ -36,7 +36,7 @@ static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode,
                                                 unsigned int count)
 {
         for (; count != 0; count--, tab++) {
-                if ((idcode & tab->idmask) == tab->idcode)
+                if ((idcode & tab->idmask) == (tab->idcode & tab->idmask))
                         return tab;
         }
 
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 4e770355ccbc..4d4e571af553 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -107,7 +107,6 @@ static struct irq_chip s3c_irq_uart = {
 
 static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
 {
-        struct irq_desc *desc = irq_to_desc(uirq->parent_irq);
         void __iomem *reg_base = uirq->regs;
         unsigned int irq;
         int offs;
@@ -118,14 +117,13 @@ static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
         for (offs = 0; offs < 3; offs++) {
                 irq = uirq->base_irq + offs;
 
-                set_irq_chip(irq, &s3c_irq_uart);
-                set_irq_chip_data(irq, uirq);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
+                irq_set_chip_data(irq, uirq);
                 set_irq_flags(irq, IRQF_VALID);
         }
 
-        desc->irq_data.handler_data = uirq;
-        set_irq_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
+        irq_set_handler_data(uirq->parent_irq, uirq);
+        irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
 }
 
 /**
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index dd8692ae5c4c..d6ad66ab9290 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -77,14 +77,11 @@ static struct irq_chip s3c_irq_timer = {
 void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
                                    unsigned int timer_irq)
 {
-        struct irq_desc *desc = irq_to_desc(parent_irq);
 
-        set_irq_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
+        irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
+        irq_set_handler_data(parent_irq, (void *)timer_irq);
 
-        set_irq_chip(timer_irq, &s3c_irq_timer);
-        set_irq_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
-        set_irq_handler(timer_irq, handle_level_irq);
+        irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq);
+        irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
         set_irq_flags(timer_irq, IRQF_VALID);
-
-        desc->irq_data.handler_data = (void *)timer_irq;
 }
diff --git a/arch/arm/plat-samsung/wakeup-mask.c b/arch/arm/plat-samsung/wakeup-mask.c
index 2e09b6ad84ca..dc814037297b 100644
--- a/arch/arm/plat-samsung/wakeup-mask.c
+++ b/arch/arm/plat-samsung/wakeup-mask.c
@@ -22,7 +22,7 @@
 void samsung_sync_wakemask(void __iomem *reg,
                            struct samsung_wakeup_mask *mask, int nr_mask)
 {
-        struct irq_desc *desc;
+        struct irq_data *data;
         u32 val;
 
         val = __raw_readl(reg);
@@ -33,10 +33,10 @@ void samsung_sync_wakemask(void __iomem *reg,
                         continue;
                 }
 
-                desc = irq_to_desc(mask->irq);
+                data = irq_get_irq_data(mask->irq);
 
-                /* bit of a liberty to read this directly from irq_desc. */
-                if (desc->wake_depth > 0)
+                /* bit of a liberty to read this directly from irq_data. */
+                if (irqd_is_wakeup_set(data))
                         val &= ~mask->bit;
                 else
                         val |= mask->bit;
diff --git a/arch/arm/plat-spear/shirq.c b/arch/arm/plat-spear/shirq.c
index 78189035e7f1..961fb7261243 100644
--- a/arch/arm/plat-spear/shirq.c
+++ b/arch/arm/plat-spear/shirq.c
@@ -68,7 +68,7 @@ static struct irq_chip shirq_chip = {
 static void shirq_handler(unsigned irq, struct irq_desc *desc)
 {
         u32 i, val, mask;
-        struct spear_shirq *shirq = get_irq_data(irq);
+        struct spear_shirq *shirq = irq_get_handler_data(irq);
 
         desc->irq_data.chip->irq_ack(&desc->irq_data);
         while ((val = readl(shirq->regs.base + shirq->regs.status_reg) &
@@ -105,14 +105,14 @@ int spear_shirq_register(struct spear_shirq *shirq)
         if (!shirq->dev_count)
                 return -EINVAL;
 
-        set_irq_chained_handler(shirq->irq, shirq_handler);
+        irq_set_chained_handler(shirq->irq, shirq_handler);
         for (i = 0; i < shirq->dev_count; i++) {
-                set_irq_chip(shirq->dev_config[i].virq, &shirq_chip);
-                set_irq_handler(shirq->dev_config[i].virq, handle_simple_irq);
+                irq_set_chip_and_handler(shirq->dev_config[i].virq,
+                                         &shirq_chip, handle_simple_irq);
                 set_irq_flags(shirq->dev_config[i].virq, IRQF_VALID);
-                set_irq_chip_data(shirq->dev_config[i].virq, shirq);
+                irq_set_chip_data(shirq->dev_config[i].virq, shirq);
         }
 
-        set_irq_data(shirq->irq, shirq);
+        irq_set_handler_data(shirq->irq, shirq);
         return 0;
 }
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
index aaa168683d4e..6fdf9acf82ed 100644
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ b/arch/arm/plat-stmp3xxx/irq.c
@@ -35,8 +35,7 @@ void __init stmp3xxx_init_irq(struct irq_chip *chip)
         /* Disable all interrupts initially */
         for (i = 0; i < NR_REAL_IRQS; i++) {
                 chip->irq_mask(irq_get_irq_data(i));
-                set_irq_chip(i, chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip_and_handler(i, chip, handle_level_irq);
                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
         }
 
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
index 66d5bac3ace2..3def03b3217d 100644
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ b/arch/arm/plat-stmp3xxx/pinmux.c
@@ -489,14 +489,13 @@ static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
 
 static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
 {
-        struct stmp3xxx_pinmux_bank *pm = get_irq_data(irq);
+        struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
         int gpio_irq = pm->virq;
         u32 stat = __raw_readl(pm->irqstat);
 
         while (stat) {
                 if (stat & 1)
-                        irq_desc[gpio_irq].handle_irq(gpio_irq,
-                                &irq_desc[gpio_irq]);
+                        generic_handle_irq(gpio_irq);
                 gpio_irq++;
                 stat >>= 1;
         }
@@ -534,15 +533,15 @@ int __init stmp3xxx_pinmux_init(int virtual_irq_start)
 
                 for (virq = pm->virq; virq < pm->virq; virq++) {
                         gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
-                        set_irq_chip(virq, &gpio_irq_chip);
-                        set_irq_handler(virq, handle_level_irq);
+                        irq_set_chip_and_handler(virq, &gpio_irq_chip,
+                                                 handle_level_irq);
                         set_irq_flags(virq, IRQF_VALID);
                 }
                 r = gpiochip_add(&pm->chip);
                 if (r < 0)
                         break;
-                set_irq_chained_handler(pm->irq, stmp3xxx_gpio_irq);
-                set_irq_data(pm->irq, pm);
+                irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
+                irq_set_handler_data(pm->irq, pm);
         }
         return r;
 }
diff --git a/arch/arm/plat-versatile/fpga-irq.c b/arch/arm/plat-versatile/fpga-irq.c
index 31d945d37e4f..f0cc8e19b094 100644
--- a/arch/arm/plat-versatile/fpga-irq.c
+++ b/arch/arm/plat-versatile/fpga-irq.c
@@ -30,7 +30,7 @@ static void fpga_irq_unmask(struct irq_data *d)
 
 static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
 {
-        struct fpga_irq_data *f = get_irq_desc_data(desc);
+        struct fpga_irq_data *f = irq_desc_get_handler_data(desc);
         u32 status = readl(f->base + IRQ_STATUS);
 
         if (status == 0) {
@@ -55,17 +55,17 @@ void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f)
         f->chip.irq_unmask = fpga_irq_unmask;
 
         if (parent_irq != -1) {
-                set_irq_data(parent_irq, f);
-                set_irq_chained_handler(parent_irq, fpga_irq_handle);
+                irq_set_handler_data(parent_irq, f);
+                irq_set_chained_handler(parent_irq, fpga_irq_handle);
         }
 
         for (i = 0; i < 32; i++) {
                 if (valid & (1 << i)) {
                         unsigned int irq = f->irq_start + i;
 
-                        set_irq_chip_data(irq, f);
-                        set_irq_chip(irq, &f->chip);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip_data(irq, f);
+                        irq_set_chip_and_handler(irq, &f->chip,
+                                                 handle_level_irq);
                         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
                 }
         }
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 8f079392aff0..1696d34f51c2 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -48,7 +48,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_printf(p, "%3d: ", i);
                 for_each_online_cpu(j)
                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-                seq_printf(p, " %8s", get_irq_desc_chip(desc)->name);
+                seq_printf(p, " %8s", irq_desc_get_chip(desc)->name);
                 seq_printf(p, "  %s", action->name);
                 for (action = action->next; action; action = action->next)
                         seq_printf(p, "  %s", action->name);
diff --git a/arch/blackfin/kernel/trace.c b/arch/blackfin/kernel/trace.c
index 05b550891ce5..050db44fe919 100644
--- a/arch/blackfin/kernel/trace.c
+++ b/arch/blackfin/kernel/trace.c
@@ -912,10 +912,11 @@ void show_regs(struct pt_regs *fp)
         /* if no interrupts are going off, don't print this out */
         if (fp->ipend & ~0x3F) {
                 for (i = 0; i < (NR_IRQS - 1); i++) {
+                        struct irq_desc *desc = irq_to_desc(i);
                         if (!in_atomic)
-                                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
+                                raw_spin_lock_irqsave(&desc->lock, flags);
 
-                        action = irq_desc[i].action;
+                        action = desc->action;
                         if (!action)
                                 goto unlock;
 
@@ -928,7 +929,7 @@ void show_regs(struct pt_regs *fp)
                         pr_cont("\n");
 unlock:
                         if (!in_atomic)
-                                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                                raw_spin_unlock_irqrestore(&desc->lock, flags);
                 }
         }
 
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 5d68bf613b0b..7b07740cf68c 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -154,13 +154,13 @@ void platform_clear_ipi(unsigned int cpu, int irq)
 void __cpuinit bfin_local_timer_setup(void)
 {
 #if defined(CONFIG_TICKSOURCE_CORETMR)
-        struct irq_chip *chip = get_irq_chip(IRQ_CORETMR);
-        struct irq_desc *desc = irq_to_desc(IRQ_CORETMR);
+        struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
+        struct irq_chip *chip = irq_data_get_irq_chip(data);
 
         bfin_coretmr_init();
         bfin_coretmr_clockevent_init();
 
-        chip->irq_unmask(&desc->irq_data);
+        chip->irq_unmask(data);
 #else
         /* Power down the core timer, just to play safe. */
         bfin_write_TCNTL(0);
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 6cd52395a999..43d9fb195c1e 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -559,7 +559,7 @@ static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 #ifdef CONFIG_IPIPE
         handle = handle_level_irq;
 #endif
-        __set_irq_handler_unlocked(irq, handle);
+        __irq_set_handler_locked(irq, handle);
 }
 
 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
@@ -578,10 +578,9 @@ static void bfin_gpio_ack_irq(struct irq_data *d)
 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 {
         unsigned int irq = d->irq;
-        struct irq_desc *desc = irq_to_desc(irq);
         u32 gpionr = irq_to_gpio(irq);
 
-        if (desc->handle_irq == handle_edge_irq)
+        if (!irqd_is_level_type(d))
                 set_gpio_data(gpionr, 0);
 
         set_gpio_maska(gpionr, 0);
@@ -837,12 +836,11 @@ void init_pint_lut(void)
 
 static void bfin_gpio_ack_irq(struct irq_data *d)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
         u32 pintbit = PINT_BIT(pint_val);
         u32 bank = PINT_2_BANK(pint_val);
 
-        if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+        if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
                 if (pint[bank]->invert_set & pintbit)
                         pint[bank]->invert_clear = pintbit;
                 else
@@ -854,12 +852,11 @@ static void bfin_gpio_ack_irq(struct irq_data *d)
 
 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
         u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
         u32 pintbit = PINT_BIT(pint_val);
         u32 bank = PINT_2_BANK(pint_val);
 
-        if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+        if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
                 if (pint[bank]->invert_set & pintbit)
                         pint[bank]->invert_clear = pintbit;
                 else
@@ -1166,9 +1163,9 @@ int __init init_arch_irq(void)
 
         for (irq = 0; irq <= SYS_IRQS; irq++) {
                 if (irq <= IRQ_CORETMR)
-                        set_irq_chip(irq, &bfin_core_irqchip);
+                        irq_set_chip(irq, &bfin_core_irqchip);
                 else
-                        set_irq_chip(irq, &bfin_internal_irqchip);
+                        irq_set_chip(irq, &bfin_internal_irqchip);
 
                 switch (irq) {
 #if defined(CONFIG_BF53x)
@@ -1192,50 +1189,50 @@ int __init init_arch_irq(void)
 #elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
                 case IRQ_PORTF_INTA:
 #endif
-                        set_irq_chained_handler(irq,
-                                                bfin_demux_gpio_irq);
+                        irq_set_chained_handler(irq, bfin_demux_gpio_irq);
                         break;
 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
                 case IRQ_GENERIC_ERROR:
-                        set_irq_chained_handler(irq, bfin_demux_error_irq);
+                        irq_set_chained_handler(irq, bfin_demux_error_irq);
                         break;
 #endif
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
                 case IRQ_MAC_ERROR:
-                        set_irq_chained_handler(irq, bfin_demux_mac_status_irq);
+                        irq_set_chained_handler(irq,
+                                                bfin_demux_mac_status_irq);
                         break;
 #endif
 #ifdef CONFIG_SMP
                 case IRQ_SUPPLE_0:
                 case IRQ_SUPPLE_1:
-                        set_irq_handler(irq, handle_percpu_irq);
+                        irq_set_handler(irq, handle_percpu_irq);
                         break;
 #endif
 
 #ifdef CONFIG_TICKSOURCE_CORETMR
                 case IRQ_CORETMR:
 # ifdef CONFIG_SMP
-                        set_irq_handler(irq, handle_percpu_irq);
+                        irq_set_handler(irq, handle_percpu_irq);
                         break;
 # else
-                        set_irq_handler(irq, handle_simple_irq);
+                        irq_set_handler(irq, handle_simple_irq);
                         break;
 # endif
 #endif
 
 #ifdef CONFIG_TICKSOURCE_GPTMR0
                 case IRQ_TIMER0:
-                        set_irq_handler(irq, handle_simple_irq);
+                        irq_set_handler(irq, handle_simple_irq);
                         break;
 #endif
 
 #ifdef CONFIG_IPIPE
                 default:
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_handler(irq, handle_level_irq);
                         break;
 #else /* !CONFIG_IPIPE */
                 default:
-                        set_irq_handler(irq, handle_simple_irq);
+                        irq_set_handler(irq, handle_simple_irq);
                         break;
 #endif /* !CONFIG_IPIPE */
                 }
@@ -1243,22 +1240,22 @@ int __init init_arch_irq(void)
 
 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
         for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
-                set_irq_chip_and_handler(irq, &bfin_generic_error_irqchip,
+                irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
                                          handle_level_irq);
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
-        set_irq_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
+        irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
 #endif
 #endif
 
 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
-                set_irq_chip_and_handler(irq, &bfin_mac_status_irqchip,
+                irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
                                          handle_level_irq);
 #endif
         /* if configured as edge, then will be changed to do_edge_IRQ */
         for (irq = GPIO_IRQ_BASE;
                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
-                set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
+                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
                                          handle_level_irq);
 
         bfin_write_IMASK(0);
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index 04a7fc5eaf46..617925ddd142 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -296,8 +296,7 @@ config ETRAX_RTC
 choice
         prompt "RTC chip"
         depends on ETRAX_RTC
-        default ETRAX_PCF8563 if ETRAX_ARCH_V32
-        default ETRAX_DS1302 if ETRAX_ARCH_V10
+        default ETRAX_DS1302
 
 config ETRAX_DS1302
         depends on ETRAX_ARCH_V10
diff --git a/arch/cris/arch-v10/drivers/pcf8563.c b/arch/cris/arch-v10/drivers/pcf8563.c
index ea69faba9b62..1391b731ad1c 100644
--- a/arch/cris/arch-v10/drivers/pcf8563.c
+++ b/arch/cris/arch-v10/drivers/pcf8563.c
@@ -345,7 +345,7 @@ static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned
         int ret;
 
         mutex_lock(&pcf8563_mutex);
-        return pcf8563_ioctl(filp, cmd, arg);
+        ret = pcf8563_ioctl(filp, cmd, arg);
         mutex_unlock(&pcf8563_mutex);
 
         return ret;
diff --git a/arch/cris/arch-v10/kernel/signal.c b/arch/cris/arch-v10/kernel/signal.c
index b6be705c2a3e..e78fe49a9849 100644
--- a/arch/cris/arch-v10/kernel/signal.c
+++ b/arch/cris/arch-v10/kernel/signal.c
@@ -537,7 +537,7 @@ void do_signal(int canrestart, struct pt_regs *regs)
                         RESTART_CRIS_SYS(regs);
                 }
                 if (regs->r10 == -ERESTART_RESTARTBLOCK) {
-                        regs->r10 = __NR_restart_syscall;
+                        regs->r9 = __NR_restart_syscall;
                         regs->irp -= 2;
                 }
         }
diff --git a/arch/cris/arch-v32/drivers/Makefile b/arch/cris/arch-v32/drivers/Makefile
index e8c02437edaf..39aa3c117a86 100644
--- a/arch/cris/arch-v32/drivers/Makefile
+++ b/arch/cris/arch-v32/drivers/Makefile
@@ -7,7 +7,6 @@ obj-$(CONFIG_ETRAX_AXISFLASHMAP)        += axisflashmap.o
 obj-$(CONFIG_ETRAXFS)                   += mach-fs/
 obj-$(CONFIG_CRIS_MACH_ARTPEC3)         += mach-a3/
 obj-$(CONFIG_ETRAX_IOP_FW_LOAD)         += iop_fw_load.o
-obj-$(CONFIG_ETRAX_PCF8563)             += pcf8563.o
 obj-$(CONFIG_ETRAX_I2C)                 += i2c.o
 obj-$(CONFIG_ETRAX_SYNCHRONOUS_SERIAL)  += sync_serial.o
 obj-$(CONFIG_PCI)                       += pci/
diff --git a/arch/cris/arch-v32/drivers/pcf8563.c b/arch/cris/arch-v32/drivers/pcf8563.c
deleted file mode 100644
index b6e4fc0aad42..000000000000
--- a/arch/cris/arch-v32/drivers/pcf8563.c
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * PCF8563 RTC
- *
- * From Phillips' datasheet:
- *
- * The PCF8563 is a CMOS real-time clock/calendar optimized for low power
- * consumption. A programmable clock output, interrupt output and voltage
- * low detector are also provided. All address and data are transferred
- * serially via two-line bidirectional I2C-bus. Maximum bus speed is
- * 400 kbits/s. The built-in word address register is incremented
- * automatically after each written or read byte.
- *
- * Copyright (c) 2002-2007, Axis Communications AB
- * All rights reserved.
- *
- * Author: Tobias Anderberg <tobiasa@axis.com>.
- *
- */
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/sched.h>
-#include <linux/init.h>
-#include <linux/fs.h>
-#include <linux/ioctl.h>
-#include <linux/delay.h>
-#include <linux/bcd.h>
-#include <linux/mutex.h>
-
-#include <asm/uaccess.h>
-#include <asm/system.h>
-#include <asm/io.h>
-#include <asm/rtc.h>
-
-#include "i2c.h"
-
-#define PCF8563_MAJOR   121     /* Local major number. */
-#define DEVICE_NAME     "rtc"   /* Name which is registered in /proc/devices. */
-#define PCF8563_NAME    "PCF8563"
-#define DRIVER_VERSION  "$Revision: 1.17 $"
-
-/* Two simple wrapper macros, saves a few keystrokes. */
-#define rtc_read(x) i2c_readreg(RTC_I2C_READ, x)
-#define rtc_write(x,y) i2c_writereg(RTC_I2C_WRITE, x, y)
-
-static DEFINE_MUTEX(pcf8563_mutex);
-static DEFINE_MUTEX(rtc_lock); /* Protect state etc */
-
-static const unsigned char days_in_month[] =
-        { 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 };
-
-static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
-
-/* Cache VL bit value read at driver init since writing the RTC_SECOND
- * register clears the VL status.
- */
-static int voltage_low;
-
-static const struct file_operations pcf8563_fops = {
-        .owner          = THIS_MODULE,
-        .unlocked_ioctl = pcf8563_unlocked_ioctl,
-        .llseek         = noop_llseek,
-};
-
-unsigned char
-pcf8563_readreg(int reg)
-{
-        unsigned char res = rtc_read(reg);
-
-        /* The PCF8563 does not return 0 for unimplemented bits. */
-        switch (reg) {
-                case RTC_SECONDS:
-                case RTC_MINUTES:
-                        res &= 0x7F;
-                        break;
-                case RTC_HOURS:
-                case RTC_DAY_OF_MONTH:
-                        res &= 0x3F;
-                        break;
-                case RTC_WEEKDAY:
-                        res &= 0x07;
-                        break;
-                case RTC_MONTH:
-                        res &= 0x1F;
-                        break;
-                case RTC_CONTROL1:
-                        res &= 0xA8;
-                        break;
-                case RTC_CONTROL2:
-                        res &= 0x1F;
-                        break;
-                case RTC_CLOCKOUT_FREQ:
-                case RTC_TIMER_CONTROL:
-                        res &= 0x83;
-                        break;
-        }
-        return res;
-}
-
-void
-pcf8563_writereg(int reg, unsigned char val)
-{
-        rtc_write(reg, val);
-}
-
-void
-get_rtc_time(struct rtc_time *tm)
-{
-        tm->tm_sec  = rtc_read(RTC_SECONDS);
-        tm->tm_min  = rtc_read(RTC_MINUTES);
-        tm->tm_hour = rtc_read(RTC_HOURS);
-        tm->tm_mday = rtc_read(RTC_DAY_OF_MONTH);
-        tm->tm_wday = rtc_read(RTC_WEEKDAY);
-        tm->tm_mon  = rtc_read(RTC_MONTH);
-        tm->tm_year = rtc_read(RTC_YEAR);
-
-        if (tm->tm_sec & 0x80) {
-                printk(KERN_ERR "%s: RTC Voltage Low - reliable date/time "
-                       "information is no longer guaranteed!\n", PCF8563_NAME);
-        }
-
-        tm->tm_year  = bcd2bin(tm->tm_year) +
-                       ((tm->tm_mon & 0x80) ? 100 : 0);
-        tm->tm_sec  &= 0x7F;
-        tm->tm_min  &= 0x7F;
-        tm->tm_hour &= 0x3F;
-        tm->tm_mday &= 0x3F;
-        tm->tm_wday &= 0x07; /* Not coded in BCD. */
-        tm->tm_mon  &= 0x1F;
-
-        tm->tm_sec = bcd2bin(tm->tm_sec);
-        tm->tm_min = bcd2bin(tm->tm_min);
-        tm->tm_hour = bcd2bin(tm->tm_hour);
-        tm->tm_mday = bcd2bin(tm->tm_mday);
-        tm->tm_mon = bcd2bin(tm->tm_mon);
-        tm->tm_mon--; /* Month is 1..12 in RTC but 0..11 in linux */
-}
-
-int __init
-pcf8563_init(void)
-{
-        static int res;
-        static int first = 1;
-
-        if (!first)
-                return res;
-        first = 0;
-
-        /* Initiate the i2c protocol. */
-        res = i2c_init();
-        if (res < 0) {
-                printk(KERN_CRIT "pcf8563_init: Failed to init i2c.\n");
-                return res;
-        }
-
-        /*
-         * First of all we need to reset the chip. This is done by
-         * clearing control1, control2 and clk freq and resetting
-         * all alarms.
-         */
-        if (rtc_write(RTC_CONTROL1, 0x00) < 0)
-                goto err;
-
-        if (rtc_write(RTC_CONTROL2, 0x00) < 0)
-                goto err;
-
-        if (rtc_write(RTC_CLOCKOUT_FREQ, 0x00) < 0)
-                goto err;
-
-        if (rtc_write(RTC_TIMER_CONTROL, 0x03) < 0)
-                goto err;
-
-        /* Reset the alarms. */
-        if (rtc_write(RTC_MINUTE_ALARM, 0x80) < 0)
-                goto err;
-
-        if (rtc_write(RTC_HOUR_ALARM, 0x80) < 0)
-                goto err;
-
-        if (rtc_write(RTC_DAY_ALARM, 0x80) < 0)
-                goto err;
-
-        if (rtc_write(RTC_WEEKDAY_ALARM, 0x80) < 0)
-                goto err;
-
-        /* Check for low voltage, and warn about it. */
-        if (rtc_read(RTC_SECONDS) & 0x80) {
-                voltage_low = 1;
-                printk(KERN_WARNING "%s: RTC Voltage Low - reliable "
-                       "date/time information is no longer guaranteed!\n",
-                       PCF8563_NAME);
-        }
-
-        return res;
-
-err:
-        printk(KERN_INFO "%s: Error initializing chip.\n", PCF8563_NAME);
-        res = -1;
-        return res;
-}
-
-void __exit
-pcf8563_exit(void)
-{
-        unregister_chrdev(PCF8563_MAJOR, DEVICE_NAME);
-}
-
-/*
- * ioctl calls for this driver. Why return -ENOTTY upon error? Because
- * POSIX says so!
- */
-static int pcf8563_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
-        /* Some sanity checks. */
-        if (_IOC_TYPE(cmd) != RTC_MAGIC)
-                return -ENOTTY;
-
-        if (_IOC_NR(cmd) > RTC_MAX_IOCTL)
-                return -ENOTTY;
-
-        switch (cmd) {
-        case RTC_RD_TIME:
-        {
-                struct rtc_time tm;
-
-                mutex_lock(&rtc_lock);
-                memset(&tm, 0, sizeof tm);
-                get_rtc_time(&tm);
-
-                if (copy_to_user((struct rtc_time *) arg, &tm,
-                                 sizeof tm)) {
-                        mutex_unlock(&rtc_lock);
-                        return -EFAULT;
-                }
-
-                mutex_unlock(&rtc_lock);
-
-                return 0;
-        }
-        case RTC_SET_TIME:
-        {
-                int leap;
-                int year;
-                int century;
-                struct rtc_time tm;
-
-                memset(&tm, 0, sizeof tm);
-                if (!capable(CAP_SYS_TIME))
-                        return -EPERM;
-
-                if (copy_from_user(&tm, (struct rtc_time *) arg,
-                                   sizeof tm))
-                        return -EFAULT;
-
-                /* Convert from struct tm to struct rtc_time. */
-                tm.tm_year += 1900;
-                tm.tm_mon += 1;
-
-                /*
-                 * Check if tm.tm_year is a leap year. A year is a leap
-                 * year if it is divisible by 4 but not 100, except
-                 * that years divisible by 400 _are_ leap years.
-                 */
-                year = tm.tm_year;
-                leap = (tm.tm_mon == 2) &&
-                        ((year % 4 == 0 && year % 100 != 0) || year % 400 == 0);
-
-                /* Perform some sanity checks. */
-                if ((tm.tm_year < 1970) ||
-                    (tm.tm_mon > 12) ||
-                    (tm.tm_mday == 0) ||
-                    (tm.tm_mday > days_in_month[tm.tm_mon] + leap) ||
-                    (tm.tm_wday >= 7) ||
-                    (tm.tm_hour >= 24) ||
-                    (tm.tm_min >= 60) ||
-                    (tm.tm_sec >= 60))
-                        return -EINVAL;
-
-                century = (tm.tm_year >= 2000) ? 0x80 : 0;
-                tm.tm_year = tm.tm_year % 100;
-
-                tm.tm_year = bin2bcd(tm.tm_year);
-                tm.tm_mon = bin2bcd(tm.tm_mon);
-                tm.tm_mday = bin2bcd(tm.tm_mday);
-                tm.tm_hour = bin2bcd(tm.tm_hour);
-                tm.tm_min = bin2bcd(tm.tm_min);
-                tm.tm_sec = bin2bcd(tm.tm_sec);
-                tm.tm_mon |= century;
-
-                mutex_lock(&rtc_lock);
-
-                rtc_write(RTC_YEAR, tm.tm_year);
-                rtc_write(RTC_MONTH, tm.tm_mon);
-                rtc_write(RTC_WEEKDAY, tm.tm_wday); /* Not coded in BCD. */
-                rtc_write(RTC_DAY_OF_MONTH, tm.tm_mday);
-                rtc_write(RTC_HOURS, tm.tm_hour);
-                rtc_write(RTC_MINUTES, tm.tm_min);
-                rtc_write(RTC_SECONDS, tm.tm_sec);
-
-                mutex_unlock(&rtc_lock);
-
-                return 0;
-        }
-        case RTC_VL_READ:
-                if (voltage_low)
-                        printk(KERN_ERR "%s: RTC Voltage Low - "
-                               "reliable date/time information is no "
-                               "longer guaranteed!\n", PCF8563_NAME);
-
-                if (copy_to_user((int *) arg, &voltage_low, sizeof(int)))
-                        return -EFAULT;
-                return 0;
-
-        case RTC_VL_CLR:
-        {
-                /* Clear the VL bit in the seconds register in case
-                 * the time has not been set already (which would
-                 * have cleared it). This does not really matter
-                 * because of the cached voltage_low value but do it
-                 * anyway for consistency. */
-
-                int ret = rtc_read(RTC_SECONDS);
-
-                rtc_write(RTC_SECONDS, (ret & 0x7F));
-
-                /* Clear the cached value. */
-                voltage_low = 0;
-
-                return 0;
-        }
-        default:
-                return -ENOTTY;
-        }
-
-        return 0;
-}
-
-static long pcf8563_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
-{
-        int ret;
-
-        mutex_lock(&pcf8563_mutex);
-        return pcf8563_ioctl(filp, cmd, arg);
-        mutex_unlock(&pcf8563_mutex);
-
-        return ret;
-}
-
-static int __init pcf8563_register(void)
-{
-        if (pcf8563_init() < 0) {
-                printk(KERN_INFO "%s: Unable to initialize Real-Time Clock "
-                       "Driver, %s\n", PCF8563_NAME, DRIVER_VERSION);
-                return -1;
-        }
-
-        if (register_chrdev(PCF8563_MAJOR, DEVICE_NAME, &pcf8563_fops) < 0) {
-                printk(KERN_INFO "%s: Unable to get major numer %d for RTC "
-                       "device.\n", PCF8563_NAME, PCF8563_MAJOR);
-                return -1;
-        }
-
-        printk(KERN_INFO "%s Real-Time Clock Driver, %s\n", PCF8563_NAME,
-               DRIVER_VERSION);
-
-        /* Check for low voltage, and warn about it. */
-        if (voltage_low) {
-                printk(KERN_WARNING "%s: RTC Voltage Low - reliable date/time "
-                       "information is no longer guaranteed!\n", PCF8563_NAME);
-        }
-
-        return 0;
-}
-
-module_init(pcf8563_register);
-module_exit(pcf8563_exit);
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index f6037b2da25e..6db8aea5667f 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -6,6 +6,8 @@ config FRV
         select HAVE_IRQ_WORK
         select HAVE_PERF_EVENTS
         select HAVE_GENERIC_HARDIRQS
+        select GENERIC_IRQ_SHOW
+        select GENERIC_HARDIRQS_NO_DEPRECATED
 
 config ZONE_DMA
         bool
@@ -361,7 +363,6 @@ menu "Power management options"
 
 config ARCH_SUSPEND_POSSIBLE
         def_bool y
-        depends on !SMP
 
 source kernel/power/Kconfig
 endmenu
diff --git a/arch/frv/include/asm/system.h b/arch/frv/include/asm/system.h
index 0a6d8d9ca45b..6c10fd2c626d 100644
--- a/arch/frv/include/asm/system.h
+++ b/arch/frv/include/asm/system.h
@@ -45,21 +45,12 @@ do {									\
 #define wmb()                   asm volatile ("membar" : : :"memory")
 #define read_barrier_depends()  do { } while (0)
 
-#ifdef CONFIG_SMP
-#define smp_mb()                        mb()
-#define smp_rmb()                       rmb()
-#define smp_wmb()                       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#define set_mb(var, value) \
-        do { xchg(&var, (value)); } while (0)
-#else
 #define smp_mb()                        barrier()
 #define smp_rmb()                       barrier()
 #define smp_wmb()                       barrier()
 #define smp_read_barrier_depends()      do {} while(0)
 #define set_mb(var, value) \
         do { var = (value); barrier(); } while (0)
-#endif
 
 extern void die_if_kernel(const char *, ...) __attribute__((format(printf, 1, 2)));
 extern void free_initmem(void);
diff --git a/arch/frv/include/asm/thread_info.h b/arch/frv/include/asm/thread_info.h
index 8582e9c7531c..cefbe73dc119 100644
--- a/arch/frv/include/asm/thread_info.h
+++ b/arch/frv/include/asm/thread_info.h
@@ -21,6 +21,8 @@
 
 #define THREAD_SIZE             8192
 
+#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
+
 /*
  * low level task data that entry.S needs immediate access to
  * - this struct should fit entirely inside of one cache line
@@ -87,7 +89,7 @@ register struct thread_info *__current_thread_info asm("gr15");
 #define alloc_thread_info_node(tsk, node)                       \
                 kzalloc_node(THREAD_SIZE, GFP_KERNEL, node)
 #else
-#define alloc_thread_info_node(tsk)                             \
+#define alloc_thread_info_node(tsk, node)                       \
                 kmalloc_node(THREAD_SIZE, GFP_KERNEL, node)
 #endif
 
diff --git a/arch/frv/kernel/irq-mb93091.c b/arch/frv/kernel/irq-mb93091.c
index 4dd9adaf115a..9afc2ea400dc 100644
--- a/arch/frv/kernel/irq-mb93091.c
+++ b/arch/frv/kernel/irq-mb93091.c
@@ -36,45 +36,45 @@
 /*
  * on-motherboard FPGA PIC operations
  */
-static void frv_fpga_mask(unsigned int irq)
+static void frv_fpga_mask(struct irq_data *d)
 {
         uint16_t imr = __get_IMR();
 
-        imr |= 1 << (irq - IRQ_BASE_FPGA);
+        imr |= 1 << (d->irq - IRQ_BASE_FPGA);
 
         __set_IMR(imr);
 }
 
-static void frv_fpga_ack(unsigned int irq)
+static void frv_fpga_ack(struct irq_data *d)
 {
-        __clr_IFR(1 << (irq - IRQ_BASE_FPGA));
+        __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
 }
 
-static void frv_fpga_mask_ack(unsigned int irq)
+static void frv_fpga_mask_ack(struct irq_data *d)
 {
         uint16_t imr = __get_IMR();
 
-        imr |= 1 << (irq - IRQ_BASE_FPGA);
+        imr |= 1 << (d->irq - IRQ_BASE_FPGA);
         __set_IMR(imr);
 
-        __clr_IFR(1 << (irq - IRQ_BASE_FPGA));
+        __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
 }
 
-static void frv_fpga_unmask(unsigned int irq)
+static void frv_fpga_unmask(struct irq_data *d)
 {
         uint16_t imr = __get_IMR();
 
-        imr &= ~(1 << (irq - IRQ_BASE_FPGA));
+        imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
 
         __set_IMR(imr);
 }
 
 static struct irq_chip frv_fpga_pic = {
         .name           = "mb93091",
-        .ack            = frv_fpga_ack,
-        .mask           = frv_fpga_mask,
-        .mask_ack       = frv_fpga_mask_ack,
-        .unmask         = frv_fpga_unmask,
+        .irq_ack        = frv_fpga_ack,
+        .irq_mask       = frv_fpga_mask,
+        .irq_mask_ack   = frv_fpga_mask_ack,
+        .irq_unmask     = frv_fpga_unmask,
 };
 
 /*
@@ -146,9 +146,9 @@ void __init fpga_init(void)
         __clr_IFR(0x0000);
 
         for (irq = IRQ_BASE_FPGA + 1; irq <= IRQ_BASE_FPGA + 14; irq++)
-                set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
+                irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_level_irq);
 
-        set_irq_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
+        irq_set_chip_and_handler(IRQ_FPGA_NMI, &frv_fpga_pic, handle_edge_irq);
 
         /* the FPGA drives the first four external IRQ inputs on the CPU PIC */
         setup_irq(IRQ_CPU_EXTERNAL0, &fpga_irq[0]);
diff --git a/arch/frv/kernel/irq-mb93093.c b/arch/frv/kernel/irq-mb93093.c
index e45209031873..4d4ad09d3c91 100644
--- a/arch/frv/kernel/irq-mb93093.c
+++ b/arch/frv/kernel/irq-mb93093.c
@@ -35,45 +35,44 @@
 /*
  * off-CPU FPGA PIC operations
  */
-static void frv_fpga_mask(unsigned int irq)
+static void frv_fpga_mask(struct irq_data *d)
 {
         uint16_t imr = __get_IMR();
 
-        imr |= 1 << (irq - IRQ_BASE_FPGA);
+        imr |= 1 << (d->irq - IRQ_BASE_FPGA);
         __set_IMR(imr);
 }
 
-static void frv_fpga_ack(unsigned int irq)
+static void frv_fpga_ack(struct irq_data *d)
 {
-        __clr_IFR(1 << (irq - IRQ_BASE_FPGA));
+        __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
 }
 
-static void frv_fpga_mask_ack(unsigned int irq)
+static void frv_fpga_mask_ack(struct irq_data *d)
 {
         uint16_t imr = __get_IMR();
 
-        imr |= 1 << (irq - IRQ_BASE_FPGA);
+        imr |= 1 << (d->irq - IRQ_BASE_FPGA);
         __set_IMR(imr);
 
-        __clr_IFR(1 << (irq - IRQ_BASE_FPGA));
+        __clr_IFR(1 << (d->irq - IRQ_BASE_FPGA));
 }
 
-static void frv_fpga_unmask(unsigned int irq)
+static void frv_fpga_unmask(struct irq_data *d)
 {
         uint16_t imr = __get_IMR();
 
-        imr &= ~(1 << (irq - IRQ_BASE_FPGA));
+        imr &= ~(1 << (d->irq - IRQ_BASE_FPGA));
 
         __set_IMR(imr);
 }
 
 static struct irq_chip frv_fpga_pic = {
         .name           = "mb93093",
-        .ack            = frv_fpga_ack,
-        .mask           = frv_fpga_mask,
-        .mask_ack       = frv_fpga_mask_ack,
-        .unmask         = frv_fpga_unmask,
-        .end            = frv_fpga_end,
+        .irq_ack        = frv_fpga_ack,
+        .irq_mask       = frv_fpga_mask,
+        .irq_mask_ack   = frv_fpga_mask_ack,
+        .irq_unmask     = frv_fpga_unmask,
 };
 
 /*
@@ -94,7 +93,7 @@ static irqreturn_t fpga_interrupt(int irq, void *_mask)
                 irq = 31 - irq;
                 mask &= ~(1 << irq);
 
-                generic_irq_handle(IRQ_BASE_FPGA + irq);
+                generic_handle_irq(IRQ_BASE_FPGA + irq);
         }
 
         return IRQ_HANDLED;
@@ -125,7 +124,7 @@ void __init fpga_init(void)
         __clr_IFR(0x0000);
 
         for (irq = IRQ_BASE_FPGA + 8; irq <= IRQ_BASE_FPGA + 10; irq++)
-                set_irq_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &frv_fpga_pic, handle_edge_irq);
 
         /* the FPGA drives external IRQ input #2 on the CPU PIC */
         setup_irq(IRQ_CPU_EXTERNAL2, &fpga_irq[0]);
diff --git a/arch/frv/kernel/irq-mb93493.c b/arch/frv/kernel/irq-mb93493.c
index ba55ecdfb245..4d034c7840c9 100644
--- a/arch/frv/kernel/irq-mb93493.c
+++ b/arch/frv/kernel/irq-mb93493.c
@@ -45,46 +45,46 @@
  * daughter board PIC operations
  * - there is no way to ACK interrupts in the MB93493 chip
  */
-static void frv_mb93493_mask(unsigned int irq)
+static void frv_mb93493_mask(struct irq_data *d)
 {
         uint32_t iqsr;
         volatile void *piqsr;
 
-        if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
+        if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
                 piqsr = __addr_MB93493_IQSR(1);
         else
                 piqsr = __addr_MB93493_IQSR(0);
 
         iqsr = readl(piqsr);
-        iqsr &= ~(1 << (irq - IRQ_BASE_MB93493 + 16));
+        iqsr &= ~(1 << (d->irq - IRQ_BASE_MB93493 + 16));
         writel(iqsr, piqsr);
 }
 
-static void frv_mb93493_ack(unsigned int irq)
+static void frv_mb93493_ack(struct irq_data *d)
 {
 }
 
-static void frv_mb93493_unmask(unsigned int irq)
+static void frv_mb93493_unmask(struct irq_data *d)
 {
         uint32_t iqsr;
         volatile void *piqsr;
 
-        if (IRQ_ROUTING & (1 << (irq - IRQ_BASE_MB93493)))
+        if (IRQ_ROUTING & (1 << (d->irq - IRQ_BASE_MB93493)))
                 piqsr = __addr_MB93493_IQSR(1);
         else
                 piqsr = __addr_MB93493_IQSR(0);
 
         iqsr = readl(piqsr);
-        iqsr |= 1 << (irq - IRQ_BASE_MB93493 + 16);
+        iqsr |= 1 << (d->irq - IRQ_BASE_MB93493 + 16);
         writel(iqsr, piqsr);
 }
 
 static struct irq_chip frv_mb93493_pic = {
         .name           = "mb93093",
-        .ack            = frv_mb93493_ack,
-        .mask           = frv_mb93493_mask,
-        .mask_ack       = frv_mb93493_mask,
-        .unmask         = frv_mb93493_unmask,
+        .irq_ack        = frv_mb93493_ack,
+        .irq_mask       = frv_mb93493_mask,
+        .irq_mask_ack   = frv_mb93493_mask,
+        .irq_unmask     = frv_mb93493_unmask,
 };
 
 /*
@@ -139,7 +139,8 @@ void __init mb93493_init(void)
         int irq;
 
         for (irq = IRQ_BASE_MB93493 + 0; irq <= IRQ_BASE_MB93493 + 10; irq++)
-                set_irq_chip_and_handler(irq, &frv_mb93493_pic, handle_edge_irq);
+                irq_set_chip_and_handler(irq, &frv_mb93493_pic,
+                                         handle_edge_irq);
 
         /* the MB93493 drives external IRQ inputs on the CPU PIC */
         setup_irq(IRQ_CPU_MB93493_0, &mb93493_irq[0]);
diff --git a/arch/frv/kernel/irq.c b/arch/frv/kernel/irq.c
index 625136625a7f..a5f624a9f559 100644
--- a/arch/frv/kernel/irq.c
+++ b/arch/frv/kernel/irq.c
@@ -47,89 +47,45 @@ extern void __init mb93493_init(void);
 
 atomic_t irq_err_count;
 
-/*
- * Generic, controller-independent functions:
- */
-int show_interrupts(struct seq_file *p, void *v)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
-        int i = *(loff_t *) v, cpu;
-        struct irqaction * action;
-        unsigned long flags;
-
-        if (i == 0) {
-                char cpuname[12];
-
-                seq_printf(p, "    ");
-                for_each_present_cpu(cpu) {
-                        sprintf(cpuname, "CPU%d", cpu);
-                        seq_printf(p, " %10s", cpuname);
-                }
-                seq_putc(p, '\n');
-        }
-
-        if (i < NR_IRQS) {
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
-                if (action) {
-                        seq_printf(p, "%3d: ", i);
-                        for_each_present_cpu(cpu)
-                                seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-                        seq_printf(p, " %10s", irq_desc[i].chip->name ? : "-");
-                        seq_printf(p, "  %s", action->name);
-                        for (action = action->next;
-                             action;
-                             action = action->next)
-                                seq_printf(p, ", %s", action->name);
-
-                        seq_putc(p, '\n');
-                }
-
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == NR_IRQS) {
-                seq_printf(p, "Err: %10u\n", atomic_read(&irq_err_count));
-        }
-
+        seq_printf(p, "%*s: ", prec, "ERR");
+        seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
         return 0;
 }
 
 /*
  * on-CPU PIC operations
  */
-static void frv_cpupic_ack(unsigned int irqlevel)
+static void frv_cpupic_ack(struct irq_data *d)
 {
-        __clr_RC(irqlevel);
+        __clr_RC(d->irq);
         __clr_IRL();
 }
 
-static void frv_cpupic_mask(unsigned int irqlevel)
+static void frv_cpupic_mask(struct irq_data *d)
 {
-        __set_MASK(irqlevel);
+        __set_MASK(d->irq);
 }
 
-static void frv_cpupic_mask_ack(unsigned int irqlevel)
+static void frv_cpupic_mask_ack(struct irq_data *d)
 {
-        __set_MASK(irqlevel);
-        __clr_RC(irqlevel);
+        __set_MASK(d->irq);
+        __clr_RC(d->irq);
         __clr_IRL();
 }
 
-static void frv_cpupic_unmask(unsigned int irqlevel)
-{
-        __clr_MASK(irqlevel);
-}
-
-static void frv_cpupic_end(unsigned int irqlevel)
+static void frv_cpupic_unmask(struct irq_data *d)
 {
-        __clr_MASK(irqlevel);
+        __clr_MASK(d->irq);
 }
 
 static struct irq_chip frv_cpu_pic = {
         .name           = "cpu",
-        .ack            = frv_cpupic_ack,
-        .mask           = frv_cpupic_mask,
-        .mask_ack       = frv_cpupic_mask_ack,
-        .unmask         = frv_cpupic_unmask,
-        .end            = frv_cpupic_end,
+        .irq_ack        = frv_cpupic_ack,
+        .irq_mask       = frv_cpupic_mask,
+        .irq_mask_ack   = frv_cpupic_mask_ack,
+        .irq_unmask     = frv_cpupic_unmask,
 };
 
 /*
@@ -161,10 +117,10 @@ void __init init_IRQ(void)
         int level;
 
         for (level = 1; level <= 14; level++)
-                set_irq_chip_and_handler(level, &frv_cpu_pic,
+                irq_set_chip_and_handler(level, &frv_cpu_pic,
                                          handle_level_irq);
 
-        set_irq_handler(IRQ_CPU_TIMER0, handle_edge_irq);
+        irq_set_handler(IRQ_CPU_TIMER0, handle_edge_irq);
 
         /* set the trigger levels for internal interrupt sources
          * - timers all falling-edge
diff --git a/arch/ia64/Kconfig b/arch/ia64/Kconfig
index fcf3b437a2d9..c4ea0925cdbd 100644
--- a/arch/ia64/Kconfig
+++ b/arch/ia64/Kconfig
@@ -26,6 +26,7 @@ config IA64
         select GENERIC_IRQ_PROBE
         select GENERIC_PENDING_IRQ if SMP
         select IRQ_PER_CPU
+        select GENERIC_IRQ_SHOW
         default y
         help
           The Itanium Processor Family is Intel's 64-bit successor to
diff --git a/arch/ia64/hp/sim/hpsim_irq.c b/arch/ia64/hp/sim/hpsim_irq.c
index b272261d77cc..4bd9a63260ee 100644
--- a/arch/ia64/hp/sim/hpsim_irq.c
+++ b/arch/ia64/hp/sim/hpsim_irq.c
@@ -11,42 +11,41 @@
 #include <linux/irq.h>
 
 static unsigned int
-hpsim_irq_startup (unsigned int irq)
+hpsim_irq_startup(struct irq_data *data)
 {
         return 0;
 }
 
 static void
-hpsim_irq_noop (unsigned int irq)
+hpsim_irq_noop(struct irq_data *data)
 {
 }
 
 static int
-hpsim_set_affinity_noop(unsigned int a, const struct cpumask *b)
+hpsim_set_affinity_noop(struct irq_data *d, const struct cpumask *b, bool f)
 {
         return 0;
 }
 
 static struct irq_chip irq_type_hp_sim = {
-        .name =         "hpsim",
-        .startup =      hpsim_irq_startup,
-        .shutdown =     hpsim_irq_noop,
-        .enable =       hpsim_irq_noop,
-        .disable =      hpsim_irq_noop,
-        .ack =          hpsim_irq_noop,
-        .end =          hpsim_irq_noop,
-        .set_affinity = hpsim_set_affinity_noop,
+        .name =                 "hpsim",
+        .irq_startup =          hpsim_irq_startup,
+        .irq_shutdown =         hpsim_irq_noop,
+        .irq_enable =           hpsim_irq_noop,
+        .irq_disable =          hpsim_irq_noop,
+        .irq_ack =              hpsim_irq_noop,
+        .irq_set_affinity =     hpsim_set_affinity_noop,
 };
 
 void __init
 hpsim_irq_init (void)
 {
-        struct irq_desc *idesc;
         int i;
 
-        for (i = 0; i < NR_IRQS; ++i) {
-                idesc = irq_desc + i;
-                if (idesc->chip == &no_irq_chip)
-                        idesc->chip = &irq_type_hp_sim;
+        for_each_active_irq(i) {
+                struct irq_chip *chip = irq_get_chip(i);
+
+                if (chip == &no_irq_chip)
+                        irq_set_chip(i, &irq_type_hp_sim);
         }
 }
diff --git a/arch/ia64/include/asm/hw_irq.h b/arch/ia64/include/asm/hw_irq.h
index bf2e37493e04..a681d02cb324 100644
--- a/arch/ia64/include/asm/hw_irq.h
+++ b/arch/ia64/include/asm/hw_irq.h
@@ -151,9 +151,6 @@ static inline void ia64_native_resend_irq(unsigned int vector)
 /*
  * Default implementations for the irq-descriptor API:
  */
-
-extern struct irq_desc irq_desc[NR_IRQS];
-
 #ifndef CONFIG_IA64_GENERIC
 static inline ia64_vector __ia64_irq_to_vector(int irq)
 {
diff --git a/arch/ia64/kernel/iosapic.c b/arch/ia64/kernel/iosapic.c
index 22c38404f539..b0f9afebb146 100644
--- a/arch/ia64/kernel/iosapic.c
+++ b/arch/ia64/kernel/iosapic.c
@@ -257,7 +257,7 @@ set_rte (unsigned int gsi, unsigned int irq, unsigned int dest, int mask)
 }
 
 static void
-nop (unsigned int irq)
+nop (struct irq_data *data)
 {
         /* do nothing... */
 }
@@ -287,8 +287,9 @@ kexec_disable_iosapic(void)
 #endif
 
 static void
-mask_irq (unsigned int irq)
+mask_irq (struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         u32 low32;
         int rte_index;
         struct iosapic_rte_info *rte;
@@ -305,8 +306,9 @@ mask_irq (unsigned int irq)
 }
 
 static void
-unmask_irq (unsigned int irq)
+unmask_irq (struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         u32 low32;
         int rte_index;
         struct iosapic_rte_info *rte;
@@ -323,9 +325,11 @@ unmask_irq (unsigned int irq)
 
 
 static int
-iosapic_set_affinity(unsigned int irq, const struct cpumask *mask)
+iosapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
+                     bool force)
 {
 #ifdef CONFIG_SMP
+        unsigned int irq = data->irq;
         u32 high32, low32;
         int cpu, dest, rte_index;
         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
@@ -379,32 +383,33 @@ iosapic_set_affinity(unsigned int irq, const struct cpumask *mask)
  */
 
 static unsigned int
-iosapic_startup_level_irq (unsigned int irq)
+iosapic_startup_level_irq (struct irq_data *data)
 {
-        unmask_irq(irq);
+        unmask_irq(data);
         return 0;
 }
 
 static void
-iosapic_unmask_level_irq (unsigned int irq)
+iosapic_unmask_level_irq (struct irq_data *data)
 {
+        unsigned int irq = data->irq;
         ia64_vector vec = irq_to_vector(irq);
         struct iosapic_rte_info *rte;
         int do_unmask_irq = 0;
 
         irq_complete_move(irq);
-        if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
+        if (unlikely(irqd_is_setaffinity_pending(data))) {
                 do_unmask_irq = 1;
-                mask_irq(irq);
+                mask_irq(data);
         } else
-                unmask_irq(irq);
+                unmask_irq(data);
 
         list_for_each_entry(rte, &iosapic_intr_info[irq].rtes, rte_list)
                 iosapic_eoi(rte->iosapic->addr, vec);
 
         if (unlikely(do_unmask_irq)) {
-                move_masked_irq(irq);
-                unmask_irq(irq);
+                irq_move_masked_irq(data);
+                unmask_irq(data);
         }
 }
 
@@ -414,15 +419,15 @@ iosapic_unmask_level_irq (unsigned int irq)
 #define iosapic_ack_level_irq           nop
 
 static struct irq_chip irq_type_iosapic_level = {
-        .name =         "IO-SAPIC-level",
-        .startup =      iosapic_startup_level_irq,
-        .shutdown =     iosapic_shutdown_level_irq,
-        .enable =       iosapic_enable_level_irq,
-        .disable =      iosapic_disable_level_irq,
-        .ack =          iosapic_ack_level_irq,
-        .mask =         mask_irq,
-        .unmask =       iosapic_unmask_level_irq,
-        .set_affinity = iosapic_set_affinity
+        .name =                 "IO-SAPIC-level",
+        .irq_startup =          iosapic_startup_level_irq,
+        .irq_shutdown =         iosapic_shutdown_level_irq,
+        .irq_enable =           iosapic_enable_level_irq,
+        .irq_disable =          iosapic_disable_level_irq,
+        .irq_ack =              iosapic_ack_level_irq,
+        .irq_mask =             mask_irq,
+        .irq_unmask =           iosapic_unmask_level_irq,
+        .irq_set_affinity =     iosapic_set_affinity
 };
 
 /*
@@ -430,9 +435,9 @@ static struct irq_chip irq_type_iosapic_level = {
  */
 
 static unsigned int
-iosapic_startup_edge_irq (unsigned int irq)
+iosapic_startup_edge_irq (struct irq_data *data)
 {
-        unmask_irq(irq);
+        unmask_irq(data);
         /*
          * IOSAPIC simply drops interrupts pended while the
          * corresponding pin was masked, so we can't know if an
@@ -442,37 +447,25 @@ iosapic_startup_edge_irq (unsigned int irq)
 }
 
 static void
-iosapic_ack_edge_irq (unsigned int irq)
+iosapic_ack_edge_irq (struct irq_data *data)
 {
-        struct irq_desc *idesc = irq_desc + irq;
-
-        irq_complete_move(irq);
-        move_native_irq(irq);
-        /*
-         * Once we have recorded IRQ_PENDING already, we can mask the
-         * interrupt for real. This prevents IRQ storms from unhandled
-         * devices.
-         */
-        if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
-            (IRQ_PENDING|IRQ_DISABLED))
-                mask_irq(irq);
+        irq_complete_move(data->irq);
+        irq_move_irq(data);
 }
 
 #define iosapic_enable_edge_irq         unmask_irq
 #define iosapic_disable_edge_irq        nop
-#define iosapic_end_edge_irq            nop
 
 static struct irq_chip irq_type_iosapic_edge = {
-        .name =         "IO-SAPIC-edge",
-        .startup =      iosapic_startup_edge_irq,
-        .shutdown =     iosapic_disable_edge_irq,
-        .enable =       iosapic_enable_edge_irq,
-        .disable =      iosapic_disable_edge_irq,
-        .ack =          iosapic_ack_edge_irq,
-        .end =          iosapic_end_edge_irq,
-        .mask =         mask_irq,
-        .unmask =       unmask_irq,
-        .set_affinity = iosapic_set_affinity
+        .name =                 "IO-SAPIC-edge",
+        .irq_startup =          iosapic_startup_edge_irq,
+        .irq_shutdown =         iosapic_disable_edge_irq,
+        .irq_enable =           iosapic_enable_edge_irq,
+        .irq_disable =          iosapic_disable_edge_irq,
+        .irq_ack =              iosapic_ack_edge_irq,
+        .irq_mask =             mask_irq,
+        .irq_unmask =           unmask_irq,
+        .irq_set_affinity =     iosapic_set_affinity
 };
 
 static unsigned int
@@ -562,8 +555,7 @@ static int
 register_intr (unsigned int gsi, int irq, unsigned char delivery,
                unsigned long polarity, unsigned long trigger)
 {
-        struct irq_desc *idesc;
-        struct irq_chip *irq_type;
+        struct irq_chip *chip, *irq_type;
         int index;
         struct iosapic_rte_info *rte;
 
@@ -610,19 +602,18 @@ register_intr (unsigned int gsi, int irq, unsigned char delivery,
 
         irq_type = iosapic_get_irq_chip(trigger);
 
-        idesc = irq_desc + irq;
-        if (irq_type != NULL && idesc->chip != irq_type) {
-                if (idesc->chip != &no_irq_chip)
+        chip = irq_get_chip(irq);
+        if (irq_type != NULL && chip != irq_type) {
+                if (chip != &no_irq_chip)
                         printk(KERN_WARNING
                                "%s: changing vector %d from %s to %s\n",
                                __func__, irq_to_vector(irq),
-                               idesc->chip->name, irq_type->name);
-                idesc->chip = irq_type;
+                               chip->name, irq_type->name);
+                chip = irq_type;
         }
-        if (trigger == IOSAPIC_EDGE)
-                __set_irq_handler_unlocked(irq, handle_edge_irq);
-        else
-                __set_irq_handler_unlocked(irq, handle_level_irq);
+        __irq_set_chip_handler_name_locked(irq, chip, trigger == IOSAPIC_EDGE ?
+                                           handle_edge_irq : handle_level_irq,
+                                           NULL);
         return 0;
 }
 
@@ -732,6 +723,7 @@ iosapic_register_intr (unsigned int gsi,
         struct iosapic_rte_info *rte;
         u32 low32;
         unsigned char dmode;
+        struct irq_desc *desc;
 
         /*
          * If this GSI has already been registered (i.e., it's a
@@ -759,12 +751,13 @@ iosapic_register_intr (unsigned int gsi,
                         goto unlock_iosapic_lock;
         }
 
-        raw_spin_lock(&irq_desc[irq].lock);
+        desc = irq_to_desc(irq);
+        raw_spin_lock(&desc->lock);
         dest = get_target_cpu(gsi, irq);
         dmode = choose_dmode();
         err = register_intr(gsi, irq, dmode, polarity, trigger);
         if (err < 0) {
-                raw_spin_unlock(&irq_desc[irq].lock);
+                raw_spin_unlock(&desc->lock);
                 irq = err;
                 goto unlock_iosapic_lock;
         }
@@ -783,7 +776,7 @@ iosapic_register_intr (unsigned int gsi,
                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
                cpu_logical_id(dest), dest, irq_to_vector(irq));
 
-        raw_spin_unlock(&irq_desc[irq].lock);
+        raw_spin_unlock(&desc->lock);
  unlock_iosapic_lock:
         spin_unlock_irqrestore(&iosapic_lock, flags);
         return irq;
@@ -794,7 +787,6 @@ iosapic_unregister_intr (unsigned int gsi)
 {
         unsigned long flags;
         int irq, index;
-        struct irq_desc *idesc;
         u32 low32;
         unsigned long trigger, polarity;
         unsigned int dest;
@@ -824,7 +816,6 @@ iosapic_unregister_intr (unsigned int gsi)
         if (--rte->refcnt > 0)
                 goto out;
 
-        idesc = irq_desc + irq;
         rte->refcnt = NO_REF_RTE;
 
         /* Mask the interrupt */
@@ -848,7 +839,7 @@ iosapic_unregister_intr (unsigned int gsi)
         if (iosapic_intr_info[irq].count == 0) {
 #ifdef CONFIG_SMP
                 /* Clear affinity */
-                cpumask_setall(idesc->affinity);
+                cpumask_setall(irq_get_irq_data(irq)->affinity);
 #endif
                 /* Clear the interrupt information */
                 iosapic_intr_info[irq].dest = 0;
diff --git a/arch/ia64/kernel/irq.c b/arch/ia64/kernel/irq.c
index 94ee9d067cbd..ad69606613eb 100644
--- a/arch/ia64/kernel/irq.c
+++ b/arch/ia64/kernel/irq.c
@@ -53,47 +53,9 @@ atomic_t irq_err_count;
 /*
  * /proc/interrupts printing:
  */
-
-int show_interrupts(struct seq_file *p, void *v)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
-        int i = *(loff_t *) v, j;
-        struct irqaction * action;
-        unsigned long flags;
-
-        if (i == 0) {
-                char cpuname[16];
-                seq_printf(p, "     ");
-                for_each_online_cpu(j) {
-                        snprintf(cpuname, 10, "CPU%d", j);
-                        seq_printf(p, "%10s ", cpuname);
-                }
-                seq_putc(p, '\n');
-        }
-
-        if (i < NR_IRQS) {
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
-                if (!action)
-                        goto skip;
-                seq_printf(p, "%3d: ",i);
-#ifndef CONFIG_SMP
-                seq_printf(p, "%10u ", kstat_irqs(i));
-#else
-                for_each_online_cpu(j) {
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-                }
-#endif
-                seq_printf(p, " %14s", irq_desc[i].chip->name);
-                seq_printf(p, "  %s", action->name);
-
-                for (action=action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-skip:
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == NR_IRQS)
-                seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
+        seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
         return 0;
 }
 
@@ -103,7 +65,7 @@ static char irq_redir [NR_IRQS]; // = { [0 ... NR_IRQS-1] = 1 };
 void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
 {
         if (irq < NR_IRQS) {
-                cpumask_copy(irq_desc[irq].affinity,
+                cpumask_copy(irq_get_irq_data(irq)->affinity,
                              cpumask_of(cpu_logical_id(hwid)));
                 irq_redir[irq] = (char) (redir & 0xff);
         }
@@ -130,13 +92,14 @@ unsigned int vectors_in_migration[NR_IRQS];
  */
 static void migrate_irqs(void)
 {
-        struct irq_desc *desc;
         int             irq, new_cpu;
 
         for (irq=0; irq < NR_IRQS; irq++) {
-                desc = irq_desc + irq;
+                struct irq_desc *desc = irq_to_desc(irq);
+                struct irq_data *data = irq_desc_get_irq_data(desc);
+                struct irq_chip *chip = irq_data_get_irq_chip(data);
 
-                if (desc->status == IRQ_DISABLED)
+                if (irqd_irq_disabled(data))
                         continue;
 
                 /*
@@ -145,10 +108,10 @@ static void migrate_irqs(void)
                  * tell CPU not to respond to these local intr sources.
                  * such as ITV,CPEI,MCA etc.
                  */
-                if (desc->status == IRQ_PER_CPU)
+                if (irqd_is_per_cpu(data))
                         continue;
 
-                if (cpumask_any_and(irq_desc[irq].affinity, cpu_online_mask)
+                if (cpumask_any_and(data->affinity, cpu_online_mask)
                     >= nr_cpu_ids) {
                         /*
                          * Save it for phase 2 processing
@@ -160,16 +123,16 @@ static void migrate_irqs(void)
                         /*
                          * Al three are essential, currently WARN_ON.. maybe panic?
                          */
-                        if (desc->chip && desc->chip->disable &&
-                                desc->chip->enable && desc->chip->set_affinity) {
-                                desc->chip->disable(irq);
-                                desc->chip->set_affinity(irq,
-                                                         cpumask_of(new_cpu));
-                                desc->chip->enable(irq);
+                        if (chip && chip->irq_disable &&
+                                chip->irq_enable && chip->irq_set_affinity) {
+                                chip->irq_disable(data);
+                                chip->irq_set_affinity(data,
+                                                       cpumask_of(new_cpu), false);
+                                chip->irq_enable(data);
                         } else {
-                                WARN_ON((!(desc->chip) || !(desc->chip->disable) ||
-                                                !(desc->chip->enable) ||
-                                                !(desc->chip->set_affinity)));
+                                WARN_ON((!chip || !chip->irq_disable ||
+                                         !chip->irq_enable ||
+                                         !chip->irq_set_affinity));
                         }
                 }
         }
diff --git a/arch/ia64/kernel/irq_ia64.c b/arch/ia64/kernel/irq_ia64.c
index 38c07b866901..5b704740f160 100644
--- a/arch/ia64/kernel/irq_ia64.c
+++ b/arch/ia64/kernel/irq_ia64.c
@@ -343,7 +343,7 @@ static irqreturn_t smp_irq_move_cleanup_interrupt(int irq, void *dev_id)
                 if (irq < 0)
                         continue;
 
-                desc = irq_desc + irq;
+                desc = irq_to_desc(irq);
                 cfg = irq_cfg + irq;
                 raw_spin_lock(&desc->lock);
                 if (!cfg->move_cleanup_count)
@@ -626,17 +626,15 @@ static struct irqaction tlb_irqaction = {
 void
 ia64_native_register_percpu_irq (ia64_vector vec, struct irqaction *action)
 {
-        struct irq_desc *desc;
         unsigned int irq;
 
         irq = vec;
         BUG_ON(bind_irq_vector(irq, vec, CPU_MASK_ALL));
-        desc = irq_desc + irq;
-        desc->status |= IRQ_PER_CPU;
-        set_irq_chip(irq, &irq_type_ia64_lsapic);
+        irq_set_status_flags(irq, IRQ_PER_CPU);
+        irq_set_chip(irq, &irq_type_ia64_lsapic);
         if (action)
                 setup_irq(irq, action);
-        set_irq_handler(irq, handle_percpu_irq);
+        irq_set_handler(irq, handle_percpu_irq);
 }
 
 void __init
diff --git a/arch/ia64/kernel/irq_lsapic.c b/arch/ia64/kernel/irq_lsapic.c
index fc1549d4564d..1b3a776e5161 100644
--- a/arch/ia64/kernel/irq_lsapic.c
+++ b/arch/ia64/kernel/irq_lsapic.c
@@ -15,31 +15,30 @@
 #include <linux/irq.h>
 
 static unsigned int
-lsapic_noop_startup (unsigned int irq)
+lsapic_noop_startup (struct irq_data *data)
 {
         return 0;
 }
 
 static void
-lsapic_noop (unsigned int irq)
+lsapic_noop (struct irq_data *data)
 {
         /* nothing to do... */
 }
 
-static int lsapic_retrigger(unsigned int irq)
+static int lsapic_retrigger(struct irq_data *data)
 {
-        ia64_resend_irq(irq);
+        ia64_resend_irq(data->irq);
 
         return 1;
 }
 
 struct irq_chip irq_type_ia64_lsapic = {
-        .name =         "LSAPIC",
-        .startup =      lsapic_noop_startup,
-        .shutdown =     lsapic_noop,
-        .enable =       lsapic_noop,
-        .disable =      lsapic_noop,
-        .ack =          lsapic_noop,
-        .end =          lsapic_noop,
-        .retrigger =    lsapic_retrigger,
+        .name =                 "LSAPIC",
+        .irq_startup =          lsapic_noop_startup,
+        .irq_shutdown =         lsapic_noop,
+        .irq_enable =           lsapic_noop,
+        .irq_disable =          lsapic_noop,
+        .irq_ack =              lsapic_noop,
+        .irq_retrigger =        lsapic_retrigger,
 };
diff --git a/arch/ia64/kernel/mca.c b/arch/ia64/kernel/mca.c
index 80d50b83d419..84fb405eee87 100644
--- a/arch/ia64/kernel/mca.c
+++ b/arch/ia64/kernel/mca.c
@@ -2125,7 +2125,6 @@ ia64_mca_late_init(void)
         cpe_poll_timer.function = ia64_mca_cpe_poll;
 
         {
-                struct irq_desc *desc;
                 unsigned int irq;
 
                 if (cpe_vector >= 0) {
@@ -2133,8 +2132,7 @@ ia64_mca_late_init(void)
                         irq = local_vector_to_irq(cpe_vector);
                         if (irq > 0) {
                                 cpe_poll_enabled = 0;
-                                desc = irq_desc + irq;
-                                desc->status |= IRQ_PER_CPU;
+                                irq_set_status_flags(irq, IRQ_PER_CPU);
                                 setup_irq(irq, &mca_cpe_irqaction);
                                 ia64_cpe_irq = irq;
                                 ia64_mca_register_cpev(cpe_vector);
diff --git a/arch/ia64/kernel/msi_ia64.c b/arch/ia64/kernel/msi_ia64.c
index 00b19a416eab..009df5434a7a 100644
--- a/arch/ia64/kernel/msi_ia64.c
+++ b/arch/ia64/kernel/msi_ia64.c
@@ -12,12 +12,13 @@
 static struct irq_chip  ia64_msi_chip;
 
 #ifdef CONFIG_SMP
-static int ia64_set_msi_irq_affinity(unsigned int irq,
-                                      const cpumask_t *cpu_mask)
+static int ia64_set_msi_irq_affinity(struct irq_data *idata,
+                                     const cpumask_t *cpu_mask, bool force)
 {
         struct msi_msg msg;
         u32 addr, data;
         int cpu = first_cpu(*cpu_mask);
+        unsigned int irq = idata->irq;
 
         if (!cpu_online(cpu))
                 return -1;
@@ -38,7 +39,7 @@ static int ia64_set_msi_irq_affinity(unsigned int irq,
         msg.data = data;
 
         write_msi_msg(irq, &msg);
-        cpumask_copy(irq_desc[irq].affinity, cpumask_of(cpu));
+        cpumask_copy(idata->affinity, cpumask_of(cpu));
 
         return 0;
 }
@@ -55,7 +56,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
         if (irq < 0)
                 return irq;
 
-        set_irq_msi(irq, desc);
+        irq_set_msi_desc(irq, desc);
         cpus_and(mask, irq_to_domain(irq), cpu_online_map);
         dest_phys_id = cpu_physical_id(first_cpu(mask));
         vector = irq_to_vector(irq);
@@ -74,7 +75,7 @@ int ia64_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
                 MSI_DATA_VECTOR(vector);
 
         write_msi_msg(irq, &msg);
-        set_irq_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
+        irq_set_chip_and_handler(irq, &ia64_msi_chip, handle_edge_irq);
 
         return 0;
 }
@@ -84,16 +85,16 @@ void ia64_teardown_msi_irq(unsigned int irq)
         destroy_irq(irq);
 }
 
-static void ia64_ack_msi_irq(unsigned int irq)
+static void ia64_ack_msi_irq(struct irq_data *data)
 {
-        irq_complete_move(irq);
-        move_native_irq(irq);
+        irq_complete_move(data->irq);
+        irq_move_irq(data);
         ia64_eoi();
 }
 
-static int ia64_msi_retrigger_irq(unsigned int irq)
+static int ia64_msi_retrigger_irq(struct irq_data *data)
 {
-        unsigned int vector = irq_to_vector(irq);
+        unsigned int vector = irq_to_vector(data->irq);
         ia64_resend_irq(vector);
 
         return 1;
@@ -103,14 +104,14 @@ static int ia64_msi_retrigger_irq(unsigned int irq)
  * Generic ops used on most IA64 platforms.
  */
 static struct irq_chip ia64_msi_chip = {
-        .name           = "PCI-MSI",
-        .irq_mask       = mask_msi_irq,
-        .irq_unmask     = unmask_msi_irq,
-        .ack            = ia64_ack_msi_irq,
+        .name                   = "PCI-MSI",
+        .irq_mask               = mask_msi_irq,
+        .irq_unmask             = unmask_msi_irq,
+        .irq_ack                = ia64_ack_msi_irq,
 #ifdef CONFIG_SMP
-        .set_affinity   = ia64_set_msi_irq_affinity,
+        .irq_set_affinity       = ia64_set_msi_irq_affinity,
 #endif
-        .retrigger      = ia64_msi_retrigger_irq,
+        .irq_retrigger          = ia64_msi_retrigger_irq,
 };
 
 
@@ -132,8 +133,10 @@ void arch_teardown_msi_irq(unsigned int irq)
 
 #ifdef CONFIG_DMAR
 #ifdef CONFIG_SMP
-static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
+static int dmar_msi_set_affinity(struct irq_data *data,
+                                 const struct cpumask *mask, bool force)
 {
+        unsigned int irq = data->irq;
         struct irq_cfg *cfg = irq_cfg + irq;
         struct msi_msg msg;
         int cpu = cpumask_first(mask);
@@ -152,7 +155,7 @@ static int dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
         msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));
 
         dmar_msi_write(irq, &msg);
-        cpumask_copy(irq_desc[irq].affinity, mask);
+        cpumask_copy(data->affinity, mask);
 
         return 0;
 }
@@ -162,11 +165,11 @@ static struct irq_chip dmar_msi_type = {
         .name = "DMAR_MSI",
         .irq_unmask = dmar_msi_unmask,
         .irq_mask = dmar_msi_mask,
-        .ack = ia64_ack_msi_irq,
+        .irq_ack = ia64_ack_msi_irq,
 #ifdef CONFIG_SMP
-        .set_affinity = dmar_msi_set_affinity,
+        .irq_set_affinity = dmar_msi_set_affinity,
 #endif
-        .retrigger = ia64_msi_retrigger_irq,
+        .irq_retrigger = ia64_msi_retrigger_irq,
 };
 
 static int
@@ -203,8 +206,8 @@ int arch_setup_dmar_msi(unsigned int irq)
         if (ret < 0)
                 return ret;
         dmar_msi_write(irq, &msg);
-        set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
-                "edge");
+        irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
+                                      "edge");
         return 0;
 }
 #endif /* CONFIG_DMAR */
diff --git a/arch/ia64/kernel/smpboot.c b/arch/ia64/kernel/smpboot.c
index d003b502a432..44f11ee411c0 100644
--- a/arch/ia64/kernel/smpboot.c
+++ b/arch/ia64/kernel/smpboot.c
@@ -677,7 +677,7 @@ extern void fixup_irqs(void);
 int migrate_platform_irqs(unsigned int cpu)
 {
         int new_cpei_cpu;
-        struct irq_desc *desc = NULL;
+        struct irq_data *data = NULL;
         const struct cpumask *mask;
         int             retval = 0;
 
@@ -693,20 +693,20 @@ int migrate_platform_irqs(unsigned int cpu)
                         new_cpei_cpu = any_online_cpu(cpu_online_map);
                         mask = cpumask_of(new_cpei_cpu);
                         set_cpei_target_cpu(new_cpei_cpu);
-                        desc = irq_desc + ia64_cpe_irq;
+                        data = irq_get_irq_data(ia64_cpe_irq);
                         /*
                          * Switch for now, immediately, we need to do fake intr
                          * as other interrupts, but need to study CPEI behaviour with
                          * polling before making changes.
                          */
-                        if (desc) {
-                                desc->chip->disable(ia64_cpe_irq);
-                                desc->chip->set_affinity(ia64_cpe_irq, mask);
-                                desc->chip->enable(ia64_cpe_irq);
+                        if (data && data->chip) {
+                                data->chip->irq_disable(data);
+                                data->chip->irq_set_affinity(data, mask, false);
+                                data->chip->irq_enable(data);
                                 printk ("Re-targetting CPEI to cpu %d\n", new_cpei_cpu);
                         }
                 }
-                if (!desc) {
+                if (!data) {
                         printk ("Unable to retarget CPEI, offline cpu [%d] failed\n", cpu);
                         retval = -EBUSY;
                 }
diff --git a/arch/ia64/sn/kernel/irq.c b/arch/ia64/sn/kernel/irq.c
index 13c15d968098..7f399f9d99c7 100644
--- a/arch/ia64/sn/kernel/irq.c
+++ b/arch/ia64/sn/kernel/irq.c
@@ -23,11 +23,9 @@
 #include <asm/sn/sn_sal.h>
 #include <asm/sn/sn_feature_sets.h>
 
-static void force_interrupt(int irq);
 static void register_intr_pda(struct sn_irq_info *sn_irq_info);
 static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
 
-int sn_force_interrupt_flag = 1;
 extern int sn_ioif_inited;
 struct list_head **sn_irq_lh;
 static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
@@ -78,62 +76,40 @@ u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
         return ret_stuff.status;
 }
 
-static unsigned int sn_startup_irq(unsigned int irq)
+static unsigned int sn_startup_irq(struct irq_data *data)
 {
         return 0;
 }
 
-static void sn_shutdown_irq(unsigned int irq)
+static void sn_shutdown_irq(struct irq_data *data)
 {
 }
 
 extern void ia64_mca_register_cpev(int);
 
-static void sn_disable_irq(unsigned int irq)
+static void sn_disable_irq(struct irq_data *data)
 {
-        if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
+        if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
                 ia64_mca_register_cpev(0);
 }
 
-static void sn_enable_irq(unsigned int irq)
+static void sn_enable_irq(struct irq_data *data)
 {
-        if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
-                ia64_mca_register_cpev(irq);
+        if (data->irq == local_vector_to_irq(IA64_CPE_VECTOR))
+                ia64_mca_register_cpev(data->irq);
 }
 
-static void sn_ack_irq(unsigned int irq)
+static void sn_ack_irq(struct irq_data *data)
 {
         u64 event_occurred, mask;
+        unsigned int irq = data->irq & 0xff;
 
-        irq = irq & 0xff;
         event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
         mask = event_occurred & SH_ALL_INT_MASK;
         HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
         __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
 
-        move_native_irq(irq);
-}
-
-static void sn_end_irq(unsigned int irq)
-{
-        int ivec;
-        u64 event_occurred;
-
-        ivec = irq & 0xff;
-        if (ivec == SGI_UART_VECTOR) {
-                event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
-                /* If the UART bit is set here, we may have received an
-                 * interrupt from the UART that the driver missed.  To
-                 * make sure, we IPI ourselves to force us to look again.
-                 */
-                if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
-                        platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
-                                          IA64_IPI_DM_INT, 0);
-                }
-        }
-        __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
-        if (sn_force_interrupt_flag)
-                force_interrupt(irq);
+        irq_move_irq(data);
 }
 
 static void sn_irq_info_free(struct rcu_head *head);
@@ -228,9 +204,11 @@ finish_up:
         return new_irq_info;
 }
 
-static int sn_set_affinity_irq(unsigned int irq, const struct cpumask *mask)
+static int sn_set_affinity_irq(struct irq_data *data,
+                               const struct cpumask *mask, bool force)
 {
         struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
+        unsigned int irq = data->irq;
         nasid_t nasid;
         int slice;
 
@@ -259,26 +237,25 @@ void sn_set_err_irq_affinity(unsigned int irq) { }
 #endif
 
 static void
-sn_mask_irq(unsigned int irq)
+sn_mask_irq(struct irq_data *data)
 {
 }
 
 static void
-sn_unmask_irq(unsigned int irq)
+sn_unmask_irq(struct irq_data *data)
 {
 }
 
 struct irq_chip irq_type_sn = {
-        .name           = "SN hub",
-        .startup        = sn_startup_irq,
-        .shutdown       = sn_shutdown_irq,
-        .enable         = sn_enable_irq,
-        .disable        = sn_disable_irq,
-        .ack            = sn_ack_irq,
-        .end            = sn_end_irq,
-        .mask           = sn_mask_irq,
-        .unmask         = sn_unmask_irq,
-        .set_affinity   = sn_set_affinity_irq
+        .name                   = "SN hub",
+        .irq_startup            = sn_startup_irq,
+        .irq_shutdown           = sn_shutdown_irq,
+        .irq_enable             = sn_enable_irq,
+        .irq_disable            = sn_disable_irq,
+        .irq_ack                = sn_ack_irq,
+        .irq_mask               = sn_mask_irq,
+        .irq_unmask             = sn_unmask_irq,
+        .irq_set_affinity       = sn_set_affinity_irq
 };
 
 ia64_vector sn_irq_to_vector(int irq)
@@ -296,15 +273,13 @@ unsigned int sn_local_vector_to_irq(u8 vector)
 void sn_irq_init(void)
 {
         int i;
-        struct irq_desc *base_desc = irq_desc;
 
         ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
         ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
 
         for (i = 0; i < NR_IRQS; i++) {
-                if (base_desc[i].chip == &no_irq_chip) {
-                        base_desc[i].chip = &irq_type_sn;
-                }
+                if (irq_get_chip(i) == &no_irq_chip)
+                        irq_set_chip(i, &irq_type_sn);
         }
 }
 
@@ -378,7 +353,6 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
         int cpu = nasid_slice_to_cpuid(nasid, slice);
 #ifdef CONFIG_SMP
         int cpuphys;
-        struct irq_desc *desc;
 #endif
 
         pci_dev_get(pci_dev);
@@ -395,12 +369,11 @@ void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
 #ifdef CONFIG_SMP
         cpuphys = cpu_physical_id(cpu);
         set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
-        desc = irq_to_desc(sn_irq_info->irq_irq);
         /*
          * Affinity was set by the PROM, prevent it from
          * being reset by the request_irq() path.
          */
-        desc->status |= IRQ_AFFINITY_SET;
+        irqd_mark_affinity_was_set(irq_get_irq_data(sn_irq_info->irq_irq));
 #endif
 }
 
@@ -439,25 +412,11 @@ sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
         pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
 
         /* Don't force an interrupt if the irq has been disabled */
-        if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) &&
+        if (!irqd_irq_disabled(sn_irq_info->irq_irq) &&
             pci_provider && pci_provider->force_interrupt)
                 (*pci_provider->force_interrupt)(sn_irq_info);
 }
 
-static void force_interrupt(int irq)
-{
-        struct sn_irq_info *sn_irq_info;
-
-        if (!sn_ioif_inited)
-                return;
-
-        rcu_read_lock();
-        list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
-                sn_call_force_intr_provider(sn_irq_info);
-
-        rcu_read_unlock();
-}
-
 /*
  * Check for lost interrupts.  If the PIC int_status reg. says that
  * an interrupt has been sent, but not handled, and the interrupt
diff --git a/arch/ia64/sn/kernel/msi_sn.c b/arch/ia64/sn/kernel/msi_sn.c
index a5e500f02853..2b98b9e088de 100644
--- a/arch/ia64/sn/kernel/msi_sn.c
+++ b/arch/ia64/sn/kernel/msi_sn.c
@@ -144,16 +144,16 @@ int sn_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *entry)
          */
         msg.data = 0x100 + irq;
 
-        set_irq_msi(irq, entry);
+        irq_set_msi_desc(irq, entry);
         write_msi_msg(irq, &msg);
-        set_irq_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq);
+        irq_set_chip_and_handler(irq, &sn_msi_chip, handle_edge_irq);
 
         return 0;
 }
 
 #ifdef CONFIG_SMP
-static int sn_set_msi_irq_affinity(unsigned int irq,
-                                    const struct cpumask *cpu_mask)
+static int sn_set_msi_irq_affinity(struct irq_data *data,
+                                   const struct cpumask *cpu_mask, bool force)
 {
         struct msi_msg msg;
         int slice;
@@ -164,7 +164,7 @@ static int sn_set_msi_irq_affinity(unsigned int irq,
         struct sn_irq_info *sn_irq_info;
         struct sn_irq_info *new_irq_info;
         struct sn_pcibus_provider *provider;
-        unsigned int cpu;
+        unsigned int cpu, irq = data->irq;
 
         cpu = cpumask_first(cpu_mask);
         sn_irq_info = sn_msi_info[irq].sn_irq_info;
@@ -206,33 +206,33 @@ static int sn_set_msi_irq_affinity(unsigned int irq,
         msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
 
         write_msi_msg(irq, &msg);
-        cpumask_copy(irq_desc[irq].affinity, cpu_mask);
+        cpumask_copy(data->affinity, cpu_mask);
 
         return 0;
 }
 #endif /* CONFIG_SMP */
 
-static void sn_ack_msi_irq(unsigned int irq)
+static void sn_ack_msi_irq(struct irq_data *data)
 {
-        move_native_irq(irq);
+        irq_move_irq(data);
         ia64_eoi();
 }
 
-static int sn_msi_retrigger_irq(unsigned int irq)
+static int sn_msi_retrigger_irq(struct irq_data *data)
 {
-        unsigned int vector = irq;
+        unsigned int vector = data->irq;
         ia64_resend_irq(vector);
 
         return 1;
 }
 
 static struct irq_chip sn_msi_chip = {
-        .name           = "PCI-MSI",
-        .irq_mask       = mask_msi_irq,
-        .irq_unmask     = unmask_msi_irq,
-        .ack            = sn_ack_msi_irq,
+        .name                   = "PCI-MSI",
+        .irq_mask               = mask_msi_irq,
+        .irq_unmask             = unmask_msi_irq,
+        .irq_ack                = sn_ack_msi_irq,
 #ifdef CONFIG_SMP
-        .set_affinity   = sn_set_msi_irq_affinity,
+        .irq_set_affinity       = sn_set_msi_irq_affinity,
 #endif
-        .retrigger      = sn_msi_retrigger_irq,
+        .irq_retrigger          = sn_msi_retrigger_irq,
 };
diff --git a/arch/ia64/xen/irq_xen.c b/arch/ia64/xen/irq_xen.c
index a3fb7cf9ae1d..108bb858acf2 100644
--- a/arch/ia64/xen/irq_xen.c
+++ b/arch/ia64/xen/irq_xen.c
@@ -138,7 +138,6 @@ static void
 __xen_register_percpu_irq(unsigned int cpu, unsigned int vec,
                         struct irqaction *action, int save)
 {
-        struct irq_desc *desc;
         int irq = 0;
 
         if (xen_slab_ready) {
@@ -223,8 +222,7 @@ __xen_register_percpu_irq(unsigned int cpu, unsigned int vec,
                          * mark the interrupt for migrations and trigger it
                          * on cpu hotplug.
                          */
-                        desc = irq_desc + irq;
-                        desc->status |= IRQ_PER_CPU;
+                        irq_set_status_flags(irq, IRQ_PER_CPU);
                 }
         }
 
diff --git a/arch/m68k/kernel/irq.c b/arch/m68k/kernel/irq.c
index c7dd48f37bee..15dbc3e9d20c 100644
--- a/arch/m68k/kernel/irq.c
+++ b/arch/m68k/kernel/irq.c
@@ -44,7 +44,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 if (ap) {
                         seq_printf(p, "%3d: ", irq);
                         seq_printf(p, "%10u ", kstat_irqs(irq));
-                        seq_printf(p, "%14s  ", get_irq_desc_chip(desc)->name);
+                        seq_printf(p, "%14s  ", irq_desc_get_chip(desc)->name);
 
                         seq_printf(p, "%s", ap->name);
                         for (ap = ap->next; ap; ap = ap->next)
diff --git a/arch/m68k/platform/5249/intc2.c b/arch/m68k/platform/5249/intc2.c
index 8f4b63e17366..f343bf7bf5b0 100644
--- a/arch/m68k/platform/5249/intc2.c
+++ b/arch/m68k/platform/5249/intc2.c
@@ -51,8 +51,8 @@ static int __init mcf_intc2_init(void)
 
         /* GPIO interrupt sources */
         for (irq = MCFINTC2_GPIOIRQ0; (irq <= MCFINTC2_GPIOIRQ7); irq++) {
-                set_irq_chip(irq, &intc2_irq_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip(irq, &intc2_irq_gpio_chip);
+                irq_set_handler(irq, handle_edge_irq);
         }
 
         return 0;
diff --git a/arch/m68k/platform/5272/intc.c b/arch/m68k/platform/5272/intc.c
index 969ff0a467c6..43e6e96f087f 100644
--- a/arch/m68k/platform/5272/intc.c
+++ b/arch/m68k/platform/5272/intc.c
@@ -145,7 +145,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
  */
 static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
 {
-        get_irq_desc_chip(desc)->irq_ack(&desc->irq_data);
+        irq_desc_get_chip(desc)->irq_ack(&desc->irq_data);
         handle_simple_irq(irq, desc);
 }
 
@@ -171,16 +171,16 @@ void __init init_IRQ(void)
         writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
 
         for (irq = 0; (irq < NR_IRQS); irq++) {
-                set_irq_chip(irq, &intc_irq_chip);
+                irq_set_chip(irq, &intc_irq_chip);
                 edge = 0;
                 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
                         edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
                 if (edge) {
-                        set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
-                        set_irq_handler(irq, intc_external_irq);
+                        irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
+                        irq_set_handler(irq, intc_external_irq);
                 } else {
-                        set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
-                        set_irq_handler(irq, handle_level_irq);
+                        irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+                        irq_set_handler(irq, handle_level_irq);
                 }
         }
 }
diff --git a/arch/m68k/platform/68328/ints.c b/arch/m68k/platform/68328/ints.c
index e5631831a200..a90288cf7446 100644
--- a/arch/m68k/platform/68328/ints.c
+++ b/arch/m68k/platform/68328/ints.c
@@ -179,8 +179,8 @@ void __init init_IRQ(void)
         IMR = ~0;
 
         for (i = 0; (i < NR_IRQS); i++) {
-                set_irq_chip(i, &intc_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip(i, &intc_irq_chip);
+                irq_set_handler(i, handle_level_irq);
         }
 }
 
diff --git a/arch/m68k/platform/68360/ints.c b/arch/m68k/platform/68360/ints.c
index 8de3feb568c6..4af0f4e30f74 100644
--- a/arch/m68k/platform/68360/ints.c
+++ b/arch/m68k/platform/68360/ints.c
@@ -132,8 +132,8 @@ void init_IRQ(void)
         pquicc->intr_cimr = 0x00000000;
 
         for (i = 0; (i < NR_IRQS); i++) {
-                set_irq_chip(i, &intc_irq_chip);
-                set_irq_handler(i, handle_level_irq);
+                irq_set_chip(i, &intc_irq_chip);
+                irq_set_handler(i, handle_level_irq);
         }
 }
 
diff --git a/arch/m68k/platform/coldfire/intc-2.c b/arch/m68k/platform/coldfire/intc-2.c
index 2cbfbf035db9..74b55cfbc3cb 100644
--- a/arch/m68k/platform/coldfire/intc-2.c
+++ b/arch/m68k/platform/coldfire/intc-2.c
@@ -164,7 +164,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
         }
 
         if (tb)
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_handler(irq, handle_edge_irq);
 
         irq -= EINT0;
         pa = __raw_readw(MCFEPORT_EPPAR);
@@ -204,11 +204,11 @@ void __init init_IRQ(void)
 
         for (irq = MCFINT_VECBASE; (irq < MCFINT_VECBASE + NR_VECS); irq++) {
                 if ((irq >= EINT1) && (irq <=EINT7))
-                        set_irq_chip(irq, &intc_irq_chip_edge_port);
+                        irq_set_chip(irq, &intc_irq_chip_edge_port);
                 else
-                        set_irq_chip(irq, &intc_irq_chip);
-                set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
-                set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip(irq, &intc_irq_chip);
+                irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+                irq_set_handler(irq, handle_level_irq);
         }
 }
 
diff --git a/arch/m68k/platform/coldfire/intc-simr.c b/arch/m68k/platform/coldfire/intc-simr.c
index e642b24ab729..d6a4d9d53e42 100644
--- a/arch/m68k/platform/coldfire/intc-simr.c
+++ b/arch/m68k/platform/coldfire/intc-simr.c
@@ -141,7 +141,7 @@ static int intc_irq_set_type(struct irq_data *d, unsigned int type)
         }
 
         if (tb)
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_handler(irq, handle_edge_irq);
 
         ebit = irq2ebit(irq) * 2;
         pa = __raw_readw(MCFEPORT_EPPAR);
@@ -181,11 +181,11 @@ void __init init_IRQ(void)
         eirq = MCFINT_VECBASE + 64 + (MCFINTC1_ICR0 ? 64 : 0);
         for (irq = MCFINT_VECBASE; (irq < eirq); irq++) {
                 if ((irq >= EINT1) && (irq <= EINT7))
-                        set_irq_chip(irq, &intc_irq_chip_edge_port);
+                        irq_set_chip(irq, &intc_irq_chip_edge_port);
                 else
-                        set_irq_chip(irq, &intc_irq_chip);
-                set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
-                set_irq_handler(irq, handle_level_irq);
+                        irq_set_chip(irq, &intc_irq_chip);
+                irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+                irq_set_handler(irq, handle_level_irq);
         }
 }
 
diff --git a/arch/m68k/platform/coldfire/intc.c b/arch/m68k/platform/coldfire/intc.c
index d648081a63f6..c28a6ed6cb23 100644
--- a/arch/m68k/platform/coldfire/intc.c
+++ b/arch/m68k/platform/coldfire/intc.c
@@ -143,9 +143,9 @@ void __init init_IRQ(void)
         mcf_maskimr(0xffffffff);
 
         for (irq = 0; (irq < NR_IRQS); irq++) {
-                set_irq_chip(irq, &intc_irq_chip);
-                set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip(irq, &intc_irq_chip);
+                irq_set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
+                irq_set_handler(irq, handle_level_irq);
         }
 }
 
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index 5f0cf0e32653..c49c326e7af1 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -18,6 +18,7 @@ config MICROBLAZE
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_IRQ_PROBE
         select GENERIC_HARDIRQS_NO_DEPRECATED
+        select GENERIC_IRQ_SHOW
 
 config SWAP
         def_bool n
diff --git a/arch/microblaze/kernel/intc.c b/arch/microblaze/kernel/intc.c
index e4661285118e..5ba7e162833b 100644
--- a/arch/microblaze/kernel/intc.c
+++ b/arch/microblaze/kernel/intc.c
@@ -50,7 +50,7 @@ static void intc_enable_or_unmask(struct irq_data *d)
          * ack function since the handle_level_irq function
          * acks the irq before calling the interrupt handler
          */
-        if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
+        if (irqd_is_level_type(d))
                 out_be32(INTC_BASE + IAR, mask);
 }
 
@@ -157,11 +157,11 @@ void __init init_IRQ(void)
 
         for (i = 0; i < nr_irq; ++i) {
                 if (intr_type & (0x00000001 << i)) {
-                        set_irq_chip_and_handler_name(i, &intc_dev,
+                        irq_set_chip_and_handler_name(i, &intc_dev,
                                 handle_edge_irq, intc_dev.name);
                         irq_clear_status_flags(i, IRQ_LEVEL);
                 } else {
-                        set_irq_chip_and_handler_name(i, &intc_dev,
+                        irq_set_chip_and_handler_name(i, &intc_dev,
                                 handle_level_irq, intc_dev.name);
                         irq_set_status_flags(i, IRQ_LEVEL);
                 }
diff --git a/arch/microblaze/kernel/irq.c b/arch/microblaze/kernel/irq.c
index 098822413729..ce7ac8435d5c 100644
--- a/arch/microblaze/kernel/irq.c
+++ b/arch/microblaze/kernel/irq.c
@@ -47,48 +47,6 @@ next_irq:
         trace_hardirqs_on();
 }
 
-int show_interrupts(struct seq_file *p, void *v)
-{
-        int i = *(loff_t *) v, j;
-        struct irq_desc *desc;
-        struct irqaction *action;
-        unsigned long flags;
-
-        if (i == 0) {
-                seq_printf(p, "         ");
-                for_each_online_cpu(j)
-                        seq_printf(p, "CPU%-8d", j);
-                seq_putc(p, '\n');
-        }
-
-        if (i < nr_irq) {
-                desc = irq_to_desc(i);
-                raw_spin_lock_irqsave(&desc->lock, flags);
-                action = desc->action;
-                if (!action)
-                        goto skip;
-                seq_printf(p, "%3d: ", i);
-#ifndef CONFIG_SMP
-                seq_printf(p, "%10u ", kstat_irqs(i));
-#else
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
-#endif
-                seq_printf(p, " %8s", desc->status &
-                                        IRQ_LEVEL ? "level" : "edge");
-                seq_printf(p, " %8s", desc->irq_data.chip->name);
-                seq_printf(p, "  %s", action->name);
-
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-skip:
-                raw_spin_unlock_irqrestore(&desc->lock, flags);
-        }
-        return 0;
-}
-
 /* MS: There is no any advance mapping mechanism. We are using simple 32bit
   intc without any cascades or any connection that's why mapping is 1:1 */
 unsigned int irq_create_mapping(struct irq_host *host, irq_hw_number_t hwirq)
diff --git a/arch/microblaze/pci/pci-common.c b/arch/microblaze/pci/pci-common.c
index 1e01a1253631..53599067d2f9 100644
--- a/arch/microblaze/pci/pci-common.c
+++ b/arch/microblaze/pci/pci-common.c
@@ -237,7 +237,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
 
                 virq = irq_create_mapping(NULL, line);
                 if (virq != NO_IRQ)
-                        set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
         } else {
                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
                          oirq.size, oirq.specifier[0], oirq.specifier[1],
diff --git a/arch/mips/alchemy/devboards/bcsr.c b/arch/mips/alchemy/devboards/bcsr.c
index f91c43a7d5dc..596ad00e7f05 100644
--- a/arch/mips/alchemy/devboards/bcsr.c
+++ b/arch/mips/alchemy/devboards/bcsr.c
@@ -142,8 +142,8 @@ void __init bcsr_init_irq(int csc_start, int csc_end, int hook_irq)
         bcsr_csc_base = csc_start;
 
         for (irq = csc_start; irq <= csc_end; irq++)
-                set_irq_chip_and_handler_name(irq, &bcsr_irq_type,
-                        handle_level_irq, "level");
+                irq_set_chip_and_handler_name(irq, &bcsr_irq_type,
+                                              handle_level_irq, "level");
 
-        set_irq_chained_handler(hook_irq, bcsr_csc_handler);
+        irq_set_chained_handler(hook_irq, bcsr_csc_handler);
 }
diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c
index 887619547553..4a8980027ecf 100644
--- a/arch/mips/alchemy/devboards/db1200/setup.c
+++ b/arch/mips/alchemy/devboards/db1200/setup.c
@@ -63,20 +63,19 @@ void __init board_setup(void)
 static int __init db1200_arch_init(void)
 {
         /* GPIO7 is low-level triggered CPLD cascade */
-        set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
         bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
 
         /* insert/eject pairs: one of both is always screaming.  To avoid
          * issues they must not be automatically enabled when initially
          * requested.
          */
-        irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
-        irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
-        irq_to_desc(DB1200_PC0_INSERT_INT)->status |= IRQ_NOAUTOEN;
-        irq_to_desc(DB1200_PC0_EJECT_INT)->status |= IRQ_NOAUTOEN;
-        irq_to_desc(DB1200_PC1_INSERT_INT)->status |= IRQ_NOAUTOEN;
-        irq_to_desc(DB1200_PC1_EJECT_INT)->status |= IRQ_NOAUTOEN;
-
+        irq_set_status_flags(DB1200_SD0_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_SD0_EJECT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC0_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC0_EJECT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC1_INSERT_INT, IRQ_NOAUTOEN);
+        irq_set_status_flags(DB1200_PC1_EJECT_INT, IRQ_NOAUTOEN);
         return 0;
 }
 arch_initcall(db1200_arch_init);
diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 9e45971343ed..05f120ff90f9 100644
--- a/arch/mips/alchemy/devboards/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -215,35 +215,35 @@ void __init board_setup(void)
 static int __init db1x00_init_irq(void)
 {
 #if defined(CONFIG_MIPS_MIRAGE)
-        set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
+        irq_set_irq_type(AU1500_GPIO7_INT, IRQF_TRIGGER_RISING); /* TS pendown */
 #elif defined(CONFIG_MIPS_DB1550)
-        set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);  /* CD0# */
-        set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);  /* CD1# */
-        set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW);  /* CARD0# */
-        set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW);  /* CARD1# */
-        set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+        irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);  /* CD0# */
+        irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);  /* CD1# */
+        irq_set_irq_type(AU1550_GPIO3_INT, IRQF_TRIGGER_LOW);  /* CARD0# */
+        irq_set_irq_type(AU1550_GPIO5_INT, IRQF_TRIGGER_LOW);  /* CARD1# */
+        irq_set_irq_type(AU1550_GPIO21_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1550_GPIO22_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 #elif defined(CONFIG_MIPS_DB1500)
-        set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
-        set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
-        set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
-        set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
-        set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+        irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 #elif defined(CONFIG_MIPS_DB1100)
-        set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
-        set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
-        set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
-        set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
-        set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+        irq_set_irq_type(AU1100_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        irq_set_irq_type(AU1100_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        irq_set_irq_type(AU1100_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        irq_set_irq_type(AU1100_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        irq_set_irq_type(AU1100_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1100_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 #elif defined(CONFIG_MIPS_DB1000)
-        set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
-        set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
-        set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
-        set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
-        set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
-        set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
+        irq_set_irq_type(AU1000_GPIO0_INT, IRQF_TRIGGER_LOW); /* CD0# */
+        irq_set_irq_type(AU1000_GPIO3_INT, IRQF_TRIGGER_LOW); /* CD1# */
+        irq_set_irq_type(AU1000_GPIO2_INT, IRQF_TRIGGER_LOW); /* CARD0# */
+        irq_set_irq_type(AU1000_GPIO5_INT, IRQF_TRIGGER_LOW); /* CARD1# */
+        irq_set_irq_type(AU1000_GPIO1_INT, IRQF_TRIGGER_LOW); /* STSCHG0# */
+        irq_set_irq_type(AU1000_GPIO4_INT, IRQF_TRIGGER_LOW); /* STSCHG1# */
 #endif
         return 0;
 }
diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index f6540ec47a64..2d85c4b5be09 100644
--- a/arch/mips/alchemy/devboards/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -197,7 +197,7 @@ void __init board_setup(void)
 
 static int __init pb1000_init_irq(void)
 {
-        set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1000_GPIO15_INT, IRQF_TRIGGER_LOW);
         return 0;
 }
 arch_initcall(pb1000_init_irq);
diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index 90dda5f3ecc5..d108fd573aaf 100644
--- a/arch/mips/alchemy/devboards/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -117,10 +117,10 @@ void __init board_setup(void)
 
 static int __init pb1100_init_irq(void)
 {
-        set_irq_type(AU1100_GPIO9_INT,  IRQF_TRIGGER_LOW); /* PCCD# */
-        set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
-        set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
-        set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
+        irq_set_irq_type(AU1100_GPIO9_INT, IRQF_TRIGGER_LOW); /* PCCD# */
+        irq_set_irq_type(AU1100_GPIO10_INT, IRQF_TRIGGER_LOW); /* PCSTSCHG# */
+        irq_set_irq_type(AU1100_GPIO11_INT, IRQF_TRIGGER_LOW); /* PCCard# */
+        irq_set_irq_type(AU1100_GPIO13_INT, IRQF_TRIGGER_LOW); /* DC_IRQ# */
 
         return 0;
 }
diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 8b4466f2d44a..6d06b07c2381 100644
--- a/arch/mips/alchemy/devboards/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -142,7 +142,7 @@ static int __init pb1200_init_irq(void)
                 panic("Game over.  Your score is 0.");
         }
 
-        set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
         bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
 
         return 0;
diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 9cd9dfa698e7..83f46215eb0c 100644
--- a/arch/mips/alchemy/devboards/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -134,14 +134,14 @@ void __init board_setup(void)
 
 static int __init pb1500_init_irq(void)
 {
-        set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW);   /* CD0# */
-        set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW);  /* CARD0 */
-        set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW);  /* STSCHG0# */
-        set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
-        set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO9_INT, IRQF_TRIGGER_LOW);   /* CD0# */
+        irq_set_irq_type(AU1500_GPIO10_INT, IRQF_TRIGGER_LOW);  /* CARD0 */
+        irq_set_irq_type(AU1500_GPIO11_INT, IRQF_TRIGGER_LOW);  /* STSCHG0# */
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
 
         return 0;
 }
diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index 9d7d6edafa8d..b790213848bd 100644
--- a/arch/mips/alchemy/devboards/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -73,9 +73,9 @@ void __init board_setup(void)
 
 static int __init pb1550_init_irq(void)
 {
-        set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(AU1550_GPIO0_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1550_GPIO1_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1550_GPIO201_205_INT, IRQF_TRIGGER_HIGH);
 
         /* enable both PCMCIA card irqs in the shared line */
         alchemy_gpio2_enable_int(201);
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 40b84b991191..cf436ab679ae 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -123,11 +123,11 @@ mtx1_pci_idsel(unsigned int devsel, int assert)
 
 static int __init mtx1_init_irq(void)
 {
-        set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
-        set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
 
         return 0;
 }
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 80c521e5290d..febfb0fb0896 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -85,19 +85,19 @@ void __init board_setup(void)
 
 static int __init xxs1500_init_irq(void)
 {
-        set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
-        set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO204_INT, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(AU1500_GPIO201_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO202_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO203_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO205_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO207_INT, IRQF_TRIGGER_LOW);
 
-        set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
-        set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
-        set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO0_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO1_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO2_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO3_INT, IRQF_TRIGGER_LOW);
+        irq_set_irq_type(AU1500_GPIO4_INT, IRQF_TRIGGER_LOW); /* CF irq */
+        irq_set_irq_type(AU1500_GPIO5_INT, IRQF_TRIGGER_LOW);
 
         return 0;
 }
diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c
index a6484b60642f..03db3daadbd8 100644
--- a/arch/mips/ar7/irq.c
+++ b/arch/mips/ar7/irq.c
@@ -119,11 +119,11 @@ static void __init ar7_irq_init(int base)
         for (i = 0; i < 40; i++) {
                 writel(i, REG(CHNL_OFFSET(i)));
                 /* Primary IRQ's */
-                set_irq_chip_and_handler(base + i, &ar7_irq_type,
+                irq_set_chip_and_handler(base + i, &ar7_irq_type,
                                          handle_level_irq);
                 /* Secondary IRQ's */
                 if (i < 32)
-                        set_irq_chip_and_handler(base + i + 40,
+                        irq_set_chip_and_handler(base + i + 40,
                                                  &ar7_sec_irq_type,
                                                  handle_level_irq);
         }
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
index 7c02bc948a31..ac610d5fe3ba 100644
--- a/arch/mips/ath79/irq.c
+++ b/arch/mips/ath79/irq.c
@@ -124,11 +124,11 @@ static void __init ath79_misc_irq_init(void)
 
         for (i = ATH79_MISC_IRQ_BASE;
              i < ATH79_MISC_IRQ_BASE + ATH79_MISC_IRQ_COUNT; i++) {
-                set_irq_chip_and_handler(i, &ath79_misc_irq_chip,
+                irq_set_chip_and_handler(i, &ath79_misc_irq_chip,
                                          handle_level_irq);
         }
 
-        set_irq_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
+        irq_set_chained_handler(ATH79_CPU_IRQ_MISC, ath79_misc_irq_handler);
 }
 
 asmlinkage void plat_irq_dispatch(void)
diff --git a/arch/mips/bcm63xx/irq.c b/arch/mips/bcm63xx/irq.c
index 1691531aa34d..cea6021cb8d7 100644
--- a/arch/mips/bcm63xx/irq.c
+++ b/arch/mips/bcm63xx/irq.c
@@ -230,11 +230,11 @@ void __init arch_init_irq(void)
 
         mips_cpu_irq_init();
         for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
-                set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip,
+                irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
                                          handle_level_irq);
 
         for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i)
-                set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip,
+                irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
                                          handle_edge_irq);
 
         setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action);
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index ce7500cdf5b7..ffd4ae660f79 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -3,10 +3,13 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (C) 2004-2008, 2009, 2010 Cavium Networks
+ * Copyright (C) 2004-2008, 2009, 2010, 2011 Cavium Networks
  */
-#include <linux/irq.h>
+
 #include <linux/interrupt.h>
+#include <linux/bitops.h>
+#include <linux/percpu.h>
+#include <linux/irq.h>
 #include <linux/smp.h>
 
 #include <asm/octeon/octeon.h>
@@ -14,6 +17,47 @@
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock);
 static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock);
 
+static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu0_en_mirror);
+static DEFINE_PER_CPU(unsigned long, octeon_irq_ciu1_en_mirror);
+
+static __read_mostly u8 octeon_irq_ciu_to_irq[8][64];
+
+union octeon_ciu_chip_data {
+        void *p;
+        unsigned long l;
+        struct {
+                unsigned int line:6;
+                unsigned int bit:6;
+        } s;
+};
+
+struct octeon_core_chip_data {
+        struct mutex core_irq_mutex;
+        bool current_en;
+        bool desired_en;
+        u8 bit;
+};
+
+#define MIPS_CORE_IRQ_LINES 8
+
+static struct octeon_core_chip_data octeon_irq_core_chip_data[MIPS_CORE_IRQ_LINES];
+
+static void __init octeon_irq_set_ciu_mapping(int irq, int line, int bit,
+                                              struct irq_chip *chip,
+                                              irq_flow_handler_t handler)
+{
+        union octeon_ciu_chip_data cd;
+
+        irq_set_chip_and_handler(irq, chip, handler);
+
+        cd.l = 0;
+        cd.s.line = line;
+        cd.s.bit = bit;
+
+        irq_set_chip_data(irq, cd.p);
+        octeon_irq_ciu_to_irq[line][bit] = irq;
+}
+
 static int octeon_coreid_for_cpu(int cpu)
 {
 #ifdef CONFIG_SMP
@@ -23,9 +67,20 @@ static int octeon_coreid_for_cpu(int cpu)
 #endif
 }
 
-static void octeon_irq_core_ack(unsigned int irq)
+static int octeon_cpu_for_coreid(int coreid)
+{
+#ifdef CONFIG_SMP
+        return cpu_number_map(coreid);
+#else
+        return smp_processor_id();
+#endif
+}
+
+static void octeon_irq_core_ack(struct irq_data *data)
 {
-        unsigned int bit = irq - OCTEON_IRQ_SW0;
+        struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
+        unsigned int bit = cd->bit;
+
         /*
          * We don't need to disable IRQs to make these atomic since
          * they are already disabled earlier in the low level
@@ -37,131 +92,121 @@ static void octeon_irq_core_ack(unsigned int irq)
                 clear_c0_cause(0x100 << bit);
 }
 
-static void octeon_irq_core_eoi(unsigned int irq)
+static void octeon_irq_core_eoi(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
-        unsigned int bit = irq - OCTEON_IRQ_SW0;
-        /*
-         * If an IRQ is being processed while we are disabling it the
-         * handler will attempt to unmask the interrupt after it has
-         * been disabled.
-         */
-        if ((unlikely(desc->status & IRQ_DISABLED)))
-                return;
+        struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
+
         /*
          * We don't need to disable IRQs to make these atomic since
          * they are already disabled earlier in the low level
          * interrupt code.
          */
-        set_c0_status(0x100 << bit);
+        set_c0_status(0x100 << cd->bit);
 }
 
-static void octeon_irq_core_enable(unsigned int irq)
+static void octeon_irq_core_set_enable_local(void *arg)
 {
-        unsigned long flags;
-        unsigned int bit = irq - OCTEON_IRQ_SW0;
+        struct irq_data *data = arg;
+        struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
+        unsigned int mask = 0x100 << cd->bit;
 
         /*
-         * We need to disable interrupts to make sure our updates are
-         * atomic.
+         * Interrupts are already disabled, so these are atomic.
          */
-        local_irq_save(flags);
-        set_c0_status(0x100 << bit);
-        local_irq_restore(flags);
+        if (cd->desired_en)
+                set_c0_status(mask);
+        else
+                clear_c0_status(mask);
+
 }
 
-static void octeon_irq_core_disable_local(unsigned int irq)
+static void octeon_irq_core_disable(struct irq_data *data)
 {
-        unsigned long flags;
-        unsigned int bit = irq - OCTEON_IRQ_SW0;
-        /*
-         * We need to disable interrupts to make sure our updates are
-         * atomic.
-         */
-        local_irq_save(flags);
-        clear_c0_status(0x100 << bit);
-        local_irq_restore(flags);
+        struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
+        cd->desired_en = false;
 }
 
-static void octeon_irq_core_disable(unsigned int irq)
+static void octeon_irq_core_enable(struct irq_data *data)
 {
-#ifdef CONFIG_SMP
-        on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local,
-                    (void *) (long) irq, 1);
-#else
-        octeon_irq_core_disable_local(irq);
-#endif
+        struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
+        cd->desired_en = true;
 }
 
-static struct irq_chip octeon_irq_chip_core = {
-        .name = "Core",
-        .enable = octeon_irq_core_enable,
-        .disable = octeon_irq_core_disable,
-        .ack = octeon_irq_core_ack,
-        .eoi = octeon_irq_core_eoi,
-};
+static void octeon_irq_core_bus_lock(struct irq_data *data)
+{
+        struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
 
+        mutex_lock(&cd->core_irq_mutex);
+}
 
-static void octeon_irq_ciu0_ack(unsigned int irq)
+static void octeon_irq_core_bus_sync_unlock(struct irq_data *data)
 {
-        switch (irq) {
-        case OCTEON_IRQ_GMX_DRP0:
-        case OCTEON_IRQ_GMX_DRP1:
-        case OCTEON_IRQ_IPD_DRP:
-        case OCTEON_IRQ_KEY_ZERO:
-        case OCTEON_IRQ_TIMER0:
-        case OCTEON_IRQ_TIMER1:
-        case OCTEON_IRQ_TIMER2:
-        case OCTEON_IRQ_TIMER3:
-        {
-                int index = cvmx_get_core_num() * 2;
-                u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-                /*
-                 * CIU timer type interrupts must be acknoleged by
-                 * writing a '1' bit to their sum0 bit.
-                 */
-                cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
-                break;
-        }
-        default:
-                break;
+        struct octeon_core_chip_data *cd = irq_data_get_irq_chip_data(data);
+
+        if (cd->desired_en != cd->current_en) {
+                on_each_cpu(octeon_irq_core_set_enable_local, data, 1);
+
+                cd->current_en = cd->desired_en;
         }
 
-        /*
-         * In order to avoid any locking accessing the CIU, we
-         * acknowledge CIU interrupts by disabling all of them.  This
-         * way we can use a per core register and avoid any out of
-         * core locking requirements.  This has the side affect that
-         * CIU interrupts can't be processed recursively.
-         *
-         * We don't need to disable IRQs to make these atomic since
-         * they are already disabled earlier in the low level
-         * interrupt code.
-         */
-        clear_c0_status(0x100 << 2);
+        mutex_unlock(&cd->core_irq_mutex);
 }
 
-static void octeon_irq_ciu0_eoi(unsigned int irq)
+static struct irq_chip octeon_irq_chip_core = {
+        .name = "Core",
+        .irq_enable = octeon_irq_core_enable,
+        .irq_disable = octeon_irq_core_disable,
+        .irq_ack = octeon_irq_core_ack,
+        .irq_eoi = octeon_irq_core_eoi,
+        .irq_bus_lock = octeon_irq_core_bus_lock,
+        .irq_bus_sync_unlock = octeon_irq_core_bus_sync_unlock,
+
+        .irq_cpu_online = octeon_irq_core_eoi,
+        .irq_cpu_offline = octeon_irq_core_ack,
+        .flags = IRQCHIP_ONOFFLINE_ENABLED,
+};
+
+static void __init octeon_irq_init_core(void)
 {
-        /*
-         * Enable all CIU interrupts again.  We don't need to disable
-         * IRQs to make these atomic since they are already disabled
-         * earlier in the low level interrupt code.
-         */
-        set_c0_status(0x100 << 2);
+        int i;
+        int irq;
+        struct octeon_core_chip_data *cd;
+
+        for (i = 0; i < MIPS_CORE_IRQ_LINES; i++) {
+                cd = &octeon_irq_core_chip_data[i];
+                cd->current_en = false;
+                cd->desired_en = false;
+                cd->bit = i;
+                mutex_init(&cd->core_irq_mutex);
+
+                irq = OCTEON_IRQ_SW0 + i;
+                switch (irq) {
+                case OCTEON_IRQ_TIMER:
+                case OCTEON_IRQ_SW0:
+                case OCTEON_IRQ_SW1:
+                case OCTEON_IRQ_5:
+                case OCTEON_IRQ_PERF:
+                        irq_set_chip_data(irq, cd);
+                        irq_set_chip_and_handler(irq, &octeon_irq_chip_core,
+                                                 handle_percpu_irq);
+                        break;
+                default:
+                        break;
+                }
+        }
 }
 
-static int next_coreid_for_irq(struct irq_desc *desc)
+static int next_cpu_for_irq(struct irq_data *data)
 {
 
 #ifdef CONFIG_SMP
-        int coreid;
-        int weight = cpumask_weight(desc->affinity);
+        int cpu;
+        int weight = cpumask_weight(data->affinity);
 
         if (weight > 1) {
-                int cpu = smp_processor_id();
+                cpu = smp_processor_id();
                 for (;;) {
-                        cpu = cpumask_next(cpu, desc->affinity);
+                        cpu = cpumask_next(cpu, data->affinity);
                         if (cpu >= nr_cpu_ids) {
                                 cpu = -1;
                                 continue;
@@ -169,83 +214,175 @@ static int next_coreid_for_irq(struct irq_desc *desc)
                                 break;
                         }
                 }
-                coreid = octeon_coreid_for_cpu(cpu);
         } else if (weight == 1) {
-                coreid = octeon_coreid_for_cpu(cpumask_first(desc->affinity));
+                cpu = cpumask_first(data->affinity);
         } else {
-                coreid = cvmx_get_core_num();
+                cpu = smp_processor_id();
         }
-        return coreid;
+        return cpu;
 #else
-        return cvmx_get_core_num();
+        return smp_processor_id();
 #endif
 }
 
-static void octeon_irq_ciu0_enable(unsigned int irq)
+static void octeon_irq_ciu_enable(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
-        int coreid = next_coreid_for_irq(desc);
+        int cpu = next_cpu_for_irq(data);
+        int coreid = octeon_coreid_for_cpu(cpu);
+        unsigned long *pen;
         unsigned long flags;
-        uint64_t en0;
-        int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
 
-        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
-        en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-        en0 |= 1ull << bit;
-        cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
-        cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        if (cd.s.line == 0) {
+                raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+                pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
+                set_bit(cd.s.bit, pen);
+                cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        } else {
+                raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+                pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+                set_bit(cd.s.bit, pen);
+                cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+        }
 }
 
-static void octeon_irq_ciu0_enable_mbox(unsigned int irq)
+static void octeon_irq_ciu_enable_local(struct irq_data *data)
 {
-        int coreid = cvmx_get_core_num();
+        unsigned long *pen;
+        unsigned long flags;
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
+
+        if (cd.s.line == 0) {
+                raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+                pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
+                set_bit(cd.s.bit, pen);
+                cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        } else {
+                raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+                pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
+                set_bit(cd.s.bit, pen);
+                cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+        }
+}
+
+static void octeon_irq_ciu_disable_local(struct irq_data *data)
+{
+        unsigned long *pen;
         unsigned long flags;
-        uint64_t en0;
-        int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
 
-        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
-        en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-        en0 |= 1ull << bit;
-        cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
-        cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        if (cd.s.line == 0) {
+                raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+                pen = &__get_cpu_var(octeon_irq_ciu0_en_mirror);
+                clear_bit(cd.s.bit, pen);
+                cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2), *pen);
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        } else {
+                raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+                pen = &__get_cpu_var(octeon_irq_ciu1_en_mirror);
+                clear_bit(cd.s.bit, pen);
+                cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1), *pen);
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+        }
 }
 
-static void octeon_irq_ciu0_disable(unsigned int irq)
+static void octeon_irq_ciu_disable_all(struct irq_data *data)
 {
-        int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
         unsigned long flags;
-        uint64_t en0;
+        unsigned long *pen;
         int cpu;
-        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
-        for_each_online_cpu(cpu) {
-                int coreid = octeon_coreid_for_cpu(cpu);
-                en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-                en0 &= ~(1ull << bit);
-                cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+        union octeon_ciu_chip_data cd;
+
+        wmb(); /* Make sure flag changes arrive before register updates. */
+
+        cd.p = irq_data_get_irq_chip_data(data);
+
+        if (cd.s.line == 0) {
+                raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+                for_each_online_cpu(cpu) {
+                        int coreid = octeon_coreid_for_cpu(cpu);
+                        pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
+                        clear_bit(cd.s.bit, pen);
+                        cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
+                }
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        } else {
+                raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+                for_each_online_cpu(cpu) {
+                        int coreid = octeon_coreid_for_cpu(cpu);
+                        pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+                        clear_bit(cd.s.bit, pen);
+                        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
+                }
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+        }
+}
+
+static void octeon_irq_ciu_enable_all(struct irq_data *data)
+{
+        unsigned long flags;
+        unsigned long *pen;
+        int cpu;
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
+
+        if (cd.s.line == 0) {
+                raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+                for_each_online_cpu(cpu) {
+                        int coreid = octeon_coreid_for_cpu(cpu);
+                        pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
+                        set_bit(cd.s.bit, pen);
+                        cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
+                }
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        } else {
+                raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+                for_each_online_cpu(cpu) {
+                        int coreid = octeon_coreid_for_cpu(cpu);
+                        pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+                        set_bit(cd.s.bit, pen);
+                        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
+                }
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
         }
-        /*
-         * We need to do a read after the last update to make sure all
-         * of them are done.
-         */
-        cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
-        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
 }
 
 /*
  * Enable the irq on the next core in the affinity set for chips that
  * have the EN*_W1{S,C} registers.
  */
-static void octeon_irq_ciu0_enable_v2(unsigned int irq)
+static void octeon_irq_ciu_enable_v2(struct irq_data *data)
 {
-        int index;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-        struct irq_desc *desc = irq_to_desc(irq);
+        u64 mask;
+        int cpu = next_cpu_for_irq(data);
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
+        mask = 1ull << (cd.s.bit);
 
-        if ((desc->status & IRQ_DISABLED) == 0) {
-                index = next_coreid_for_irq(desc) * 2;
+        /*
+         * Called under the desc lock, so these should never get out
+         * of sync.
+         */
+        if (cd.s.line == 0) {
+                int index = octeon_coreid_for_cpu(cpu) * 2;
+                set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
                 cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        } else {
+                int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
+                set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
         }
 }
 
@@ -253,83 +390,155 @@ static void octeon_irq_ciu0_enable_v2(unsigned int irq)
  * Enable the irq on the current CPU for chips that
  * have the EN*_W1{S,C} registers.
  */
-static void octeon_irq_ciu0_enable_mbox_v2(unsigned int irq)
+static void octeon_irq_ciu_enable_local_v2(struct irq_data *data)
+{
+        u64 mask;
+        union octeon_ciu_chip_data cd;
+
+        cd.p = irq_data_get_irq_chip_data(data);
+        mask = 1ull << (cd.s.bit);
+
+        if (cd.s.line == 0) {
+                int index = cvmx_get_core_num() * 2;
+                set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror));
+                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        } else {
+                int index = cvmx_get_core_num() * 2 + 1;
+                set_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror));
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        }
+}
+
+static void octeon_irq_ciu_disable_local_v2(struct irq_data *data)
 {
-        int index;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+        u64 mask;
+        union octeon_ciu_chip_data cd;
 
-        index = cvmx_get_core_num() * 2;
-        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        cd.p = irq_data_get_irq_chip_data(data);
+        mask = 1ull << (cd.s.bit);
+
+        if (cd.s.line == 0) {
+                int index = cvmx_get_core_num() * 2;
+                clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu0_en_mirror));
+                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+        } else {
+                int index = cvmx_get_core_num() * 2 + 1;
+                clear_bit(cd.s.bit, &__get_cpu_var(octeon_irq_ciu1_en_mirror));
+                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+        }
 }
 
 /*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
+ * Write to the W1C bit in CVMX_CIU_INTX_SUM0 to clear the irq.
  */
-static void octeon_irq_ciu0_ack_v2(unsigned int irq)
-{
-        int index = cvmx_get_core_num() * 2;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-
-        switch (irq) {
-        case OCTEON_IRQ_GMX_DRP0:
-        case OCTEON_IRQ_GMX_DRP1:
-        case OCTEON_IRQ_IPD_DRP:
-        case OCTEON_IRQ_KEY_ZERO:
-        case OCTEON_IRQ_TIMER0:
-        case OCTEON_IRQ_TIMER1:
-        case OCTEON_IRQ_TIMER2:
-        case OCTEON_IRQ_TIMER3:
-                /*
-                 * CIU timer type interrupts must be acknoleged by
-                 * writing a '1' bit to their sum0 bit.
-                 */
+static void octeon_irq_ciu_ack(struct irq_data *data)
+{
+        u64 mask;
+        union octeon_ciu_chip_data cd;
+
+        cd.p = data->chip_data;
+        mask = 1ull << (cd.s.bit);
+
+        if (cd.s.line == 0) {
+                int index = cvmx_get_core_num() * 2;
                 cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
-                break;
-        default:
-                break;
+        } else {
+                cvmx_write_csr(CVMX_CIU_INT_SUM1, mask);
         }
-
-        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
 }
 
 /*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
+ * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu0_eoi_mbox_v2(unsigned int irq)
+static void octeon_irq_ciu_disable_all_v2(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
-        int index = cvmx_get_core_num() * 2;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
+        int cpu;
+        u64 mask;
+        union octeon_ciu_chip_data cd;
 
-        if (likely((desc->status & IRQ_DISABLED) == 0))
-                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+        wmb(); /* Make sure flag changes arrive before register updates. */
+
+        cd.p = data->chip_data;
+        mask = 1ull << (cd.s.bit);
+
+        if (cd.s.line == 0) {
+                for_each_online_cpu(cpu) {
+                        int index = octeon_coreid_for_cpu(cpu) * 2;
+                        clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
+                        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+                }
+        } else {
+                for_each_online_cpu(cpu) {
+                        int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
+                        clear_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
+                        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+                }
+        }
 }
 
 /*
- * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
+ * Enable the irq on the all cores for chips that have the EN*_W1{S,C}
  * registers.
  */
-static void octeon_irq_ciu0_disable_all_v2(unsigned int irq)
+static void octeon_irq_ciu_enable_all_v2(struct irq_data *data)
 {
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-        int index;
         int cpu;
-        for_each_online_cpu(cpu) {
-                index = octeon_coreid_for_cpu(cpu) * 2;
-                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+        u64 mask;
+        union octeon_ciu_chip_data cd;
+
+        cd.p = data->chip_data;
+        mask = 1ull << (cd.s.bit);
+
+        if (cd.s.line == 0) {
+                for_each_online_cpu(cpu) {
+                        int index = octeon_coreid_for_cpu(cpu) * 2;
+                        set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu0_en_mirror, cpu));
+                        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+                }
+        } else {
+                for_each_online_cpu(cpu) {
+                        int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
+                        set_bit(cd.s.bit, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
+                        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+                }
         }
 }
 
 #ifdef CONFIG_SMP
-static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
+
+static void octeon_irq_cpu_offline_ciu(struct irq_data *data)
+{
+        int cpu = smp_processor_id();
+        cpumask_t new_affinity;
+
+        if (!cpumask_test_cpu(cpu, data->affinity))
+                return;
+
+        if (cpumask_weight(data->affinity) > 1) {
+                /*
+                 * It has multi CPU affinity, just remove this CPU
+                 * from the affinity set.
+                 */
+                cpumask_copy(&new_affinity, data->affinity);
+                cpumask_clear_cpu(cpu, &new_affinity);
+        } else {
+                /* Otherwise, put it on lowest numbered online CPU. */
+                cpumask_clear(&new_affinity);
+                cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
+        }
+        __irq_set_affinity_locked(data, &new_affinity);
+}
+
+static int octeon_irq_ciu_set_affinity(struct irq_data *data,
+                                       const struct cpumask *dest, bool force)
 {
         int cpu;
-        struct irq_desc *desc = irq_to_desc(irq);
-        int enable_one = (desc->status & IRQ_DISABLED) == 0;
+        bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
         unsigned long flags;
-        int bit = irq - OCTEON_IRQ_WORKQ0;      /* Bit 0-63 of EN0 */
+        union octeon_ciu_chip_data cd;
+
+        cd.p = data->chip_data;
 
         /*
          * For non-v2 CIU, we will allow only single CPU affinity.
@@ -339,26 +548,40 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
         if (cpumask_weight(dest) != 1)
                 return -EINVAL;
 
-        raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
-        for_each_online_cpu(cpu) {
-                int coreid = octeon_coreid_for_cpu(cpu);
-                uint64_t en0 =
-                        cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
-                if (cpumask_test_cpu(cpu, dest) && enable_one) {
-                        enable_one = 0;
-                        en0 |= 1ull << bit;
-                } else {
-                        en0 &= ~(1ull << bit);
+        if (!enable_one)
+                return 0;
+
+        if (cd.s.line == 0) {
+                raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags);
+                for_each_online_cpu(cpu) {
+                        int coreid = octeon_coreid_for_cpu(cpu);
+                        unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
+
+                        if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                                enable_one = false;
+                                set_bit(cd.s.bit, pen);
+                        } else {
+                                clear_bit(cd.s.bit, pen);
+                        }
+                        cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), *pen);
                 }
-                cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
+        } else {
+                raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
+                for_each_online_cpu(cpu) {
+                        int coreid = octeon_coreid_for_cpu(cpu);
+                        unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+
+                        if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                                enable_one = false;
+                                set_bit(cd.s.bit, pen);
+                        } else {
+                                clear_bit(cd.s.bit, pen);
+                        }
+                        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
+                }
+                raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
         }
-        /*
-         * We need to do a read after the last update to make sure all
-         * of them are done.
-         */
-        cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
-        raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags);
-
         return 0;
 }
 
@@ -366,22 +589,46 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *
  * Set affinity for the irq for chips that have the EN*_W1{S,C}
  * registers.
  */
-static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
-                                           const struct cpumask *dest)
+static int octeon_irq_ciu_set_affinity_v2(struct irq_data *data,
+                                          const struct cpumask *dest,
+                                          bool force)
 {
         int cpu;
-        int index;
-        struct irq_desc *desc = irq_to_desc(irq);
-        int enable_one = (desc->status & IRQ_DISABLED) == 0;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
-
-        for_each_online_cpu(cpu) {
-                index = octeon_coreid_for_cpu(cpu) * 2;
-                if (cpumask_test_cpu(cpu, dest) && enable_one) {
-                        enable_one = 0;
-                        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
-                } else {
-                        cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+        bool enable_one = !irqd_irq_disabled(data) && !irqd_irq_masked(data);
+        u64 mask;
+        union octeon_ciu_chip_data cd;
+
+        if (!enable_one)
+                return 0;
+
+        cd.p = data->chip_data;
+        mask = 1ull << cd.s.bit;
+
+        if (cd.s.line == 0) {
+                for_each_online_cpu(cpu) {
+                        unsigned long *pen = &per_cpu(octeon_irq_ciu0_en_mirror, cpu);
+                        int index = octeon_coreid_for_cpu(cpu) * 2;
+                        if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                                enable_one = false;
+                                set_bit(cd.s.bit, pen);
+                                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1S(index), mask);
+                        } else {
+                                clear_bit(cd.s.bit, pen);
+                                cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
+                        }
+                }
+        } else {
+                for_each_online_cpu(cpu) {
+                        unsigned long *pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+                        int index = octeon_coreid_for_cpu(cpu) * 2 + 1;
+                        if (cpumask_test_cpu(cpu, dest) && enable_one) {
+                                enable_one = false;
+                                set_bit(cd.s.bit, pen);
+                                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+                        } else {
+                                clear_bit(cd.s.bit, pen);
+                                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+                        }
                 }
         }
         return 0;
@@ -389,80 +636,102 @@ static int octeon_irq_ciu0_set_affinity_v2(unsigned int irq,
 #endif
 
 /*
+ * The v1 CIU code already masks things, so supply a dummy version to
+ * the core chip code.
+ */
+static void octeon_irq_dummy_mask(struct irq_data *data)
+{
+}
+
+/*
  * Newer octeon chips have support for lockless CIU operation.
  */
-static struct irq_chip octeon_irq_chip_ciu0_v2 = {
-        .name = "CIU0",
-        .enable = octeon_irq_ciu0_enable_v2,
-        .disable = octeon_irq_ciu0_disable_all_v2,
-        .eoi = octeon_irq_ciu0_enable_v2,
+static struct irq_chip octeon_irq_chip_ciu_v2 = {
+        .name = "CIU",
+        .irq_enable = octeon_irq_ciu_enable_v2,
+        .irq_disable = octeon_irq_ciu_disable_all_v2,
+        .irq_mask = octeon_irq_ciu_disable_local_v2,
+        .irq_unmask = octeon_irq_ciu_enable_v2,
 #ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu0_set_affinity_v2,
+        .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
+        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
 };
 
-static struct irq_chip octeon_irq_chip_ciu0 = {
-        .name = "CIU0",
-        .enable = octeon_irq_ciu0_enable,
-        .disable = octeon_irq_ciu0_disable,
-        .eoi = octeon_irq_ciu0_eoi,
+static struct irq_chip octeon_irq_chip_ciu_edge_v2 = {
+        .name = "CIU-E",
+        .irq_enable = octeon_irq_ciu_enable_v2,
+        .irq_disable = octeon_irq_ciu_disable_all_v2,
+        .irq_ack = octeon_irq_ciu_ack,
+        .irq_mask = octeon_irq_ciu_disable_local_v2,
+        .irq_unmask = octeon_irq_ciu_enable_v2,
 #ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu0_set_affinity,
+        .irq_set_affinity = octeon_irq_ciu_set_affinity_v2,
+        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
 #endif
 };
 
-/* The mbox versions don't do any affinity or round-robin. */
-static struct irq_chip octeon_irq_chip_ciu0_mbox_v2 = {
-        .name = "CIU0-M",
-        .enable = octeon_irq_ciu0_enable_mbox_v2,
-        .disable = octeon_irq_ciu0_disable,
-        .eoi = octeon_irq_ciu0_eoi_mbox_v2,
+static struct irq_chip octeon_irq_chip_ciu = {
+        .name = "CIU",
+        .irq_enable = octeon_irq_ciu_enable,
+        .irq_disable = octeon_irq_ciu_disable_all,
+        .irq_mask = octeon_irq_dummy_mask,
+#ifdef CONFIG_SMP
+        .irq_set_affinity = octeon_irq_ciu_set_affinity,
+        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
+#endif
 };
 
-static struct irq_chip octeon_irq_chip_ciu0_mbox = {
-        .name = "CIU0-M",
-        .enable = octeon_irq_ciu0_enable_mbox,
-        .disable = octeon_irq_ciu0_disable,
-        .eoi = octeon_irq_ciu0_eoi,
+static struct irq_chip octeon_irq_chip_ciu_edge = {
+        .name = "CIU-E",
+        .irq_enable = octeon_irq_ciu_enable,
+        .irq_disable = octeon_irq_ciu_disable_all,
+        .irq_mask = octeon_irq_dummy_mask,
+        .irq_ack = octeon_irq_ciu_ack,
+#ifdef CONFIG_SMP
+        .irq_set_affinity = octeon_irq_ciu_set_affinity,
+        .irq_cpu_offline = octeon_irq_cpu_offline_ciu,
+#endif
 };
 
-static void octeon_irq_ciu1_ack(unsigned int irq)
-{
-        /*
-         * In order to avoid any locking accessing the CIU, we
-         * acknowledge CIU interrupts by disabling all of them.  This
-         * way we can use a per core register and avoid any out of
-         * core locking requirements.  This has the side affect that
-         * CIU interrupts can't be processed recursively.  We don't
-         * need to disable IRQs to make these atomic since they are
-         * already disabled earlier in the low level interrupt code.
-         */
-        clear_c0_status(0x100 << 3);
-}
+/* The mbox versions don't do any affinity or round-robin. */
+static struct irq_chip octeon_irq_chip_ciu_mbox_v2 = {
+        .name = "CIU-M",
+        .irq_enable = octeon_irq_ciu_enable_all_v2,
+        .irq_disable = octeon_irq_ciu_disable_all_v2,
+        .irq_ack = octeon_irq_ciu_disable_local_v2,
+        .irq_eoi = octeon_irq_ciu_enable_local_v2,
+
+        .irq_cpu_online = octeon_irq_ciu_enable_local_v2,
+        .irq_cpu_offline = octeon_irq_ciu_disable_local_v2,
+        .flags = IRQCHIP_ONOFFLINE_ENABLED,
+};
 
-static void octeon_irq_ciu1_eoi(unsigned int irq)
-{
-        /*
-         * Enable all CIU interrupts again.  We don't need to disable
-         * IRQs to make these atomic since they are already disabled
-         * earlier in the low level interrupt code.
-         */
-        set_c0_status(0x100 << 3);
-}
+static struct irq_chip octeon_irq_chip_ciu_mbox = {
+        .name = "CIU-M",
+        .irq_enable = octeon_irq_ciu_enable_all,
+        .irq_disable = octeon_irq_ciu_disable_all,
+
+        .irq_cpu_online = octeon_irq_ciu_enable_local,
+        .irq_cpu_offline = octeon_irq_ciu_disable_local,
+        .flags = IRQCHIP_ONOFFLINE_ENABLED,
+};
 
-static void octeon_irq_ciu1_enable(unsigned int irq)
+/*
+ * Watchdog interrupts are special.  They are associated with a single
+ * core, so we hardwire the affinity to that core.
+ */
+static void octeon_irq_ciu_wd_enable(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_to_desc(irq);
-        int coreid = next_coreid_for_irq(desc);
         unsigned long flags;
-        uint64_t en1;
-        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+        unsigned long *pen;
+        int coreid = data->irq - OCTEON_IRQ_WDOG0;      /* Bit 0-63 of EN1 */
+        int cpu = octeon_cpu_for_coreid(coreid);
 
         raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
-        en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
-        en1 |= 1ull << bit;
-        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
-        cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
+        pen = &per_cpu(octeon_irq_ciu1_en_mirror, cpu);
+        set_bit(coreid, pen);
+        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), *pen);
         raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
 }
 
@@ -470,286 +739,281 @@ static void octeon_irq_ciu1_enable(unsigned int irq)
  * Watchdog interrupts are special.  They are associated with a single
  * core, so we hardwire the affinity to that core.
  */
-static void octeon_irq_ciu1_wd_enable(unsigned int irq)
+static void octeon_irq_ciu1_wd_enable_v2(struct irq_data *data)
 {
-        unsigned long flags;
-        uint64_t en1;
-        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
-        int coreid = bit;
+        int coreid = data->irq - OCTEON_IRQ_WDOG0;
+        int cpu = octeon_cpu_for_coreid(coreid);
 
-        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
-        en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
-        en1 |= 1ull << bit;
-        cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
-        cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
-        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+        set_bit(coreid, &per_cpu(octeon_irq_ciu1_en_mirror, cpu));
+        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(coreid * 2 + 1), 1ull << coreid);
 }
 
-static void octeon_irq_ciu1_disable(unsigned int irq)
+
+static struct irq_chip octeon_irq_chip_ciu_wd_v2 = {
+        .name = "CIU-W",
+        .irq_enable = octeon_irq_ciu1_wd_enable_v2,
+        .irq_disable = octeon_irq_ciu_disable_all_v2,
+        .irq_mask = octeon_irq_ciu_disable_local_v2,
+        .irq_unmask = octeon_irq_ciu_enable_local_v2,
+};
+
+static struct irq_chip octeon_irq_chip_ciu_wd = {
+        .name = "CIU-W",
+        .irq_enable = octeon_irq_ciu_wd_enable,
+        .irq_disable = octeon_irq_ciu_disable_all,
+        .irq_mask = octeon_irq_dummy_mask,
+};
+
+static void octeon_irq_ip2_v1(void)
 {
-        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
-        unsigned long flags;
-        uint64_t en1;
-        int cpu;
-        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
-        for_each_online_cpu(cpu) {
-                int coreid = octeon_coreid_for_cpu(cpu);
-                en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
-                en1 &= ~(1ull << bit);
-                cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
+        const unsigned long core_id = cvmx_get_core_num();
+        u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
+
+        ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
+        clear_c0_status(STATUSF_IP2);
+        if (likely(ciu_sum)) {
+                int bit = fls64(ciu_sum) - 1;
+                int irq = octeon_irq_ciu_to_irq[0][bit];
+                if (likely(irq))
+                        do_IRQ(irq);
+                else
+                        spurious_interrupt();
+        } else {
+                spurious_interrupt();
         }
-        /*
-         * We need to do a read after the last update to make sure all
-         * of them are done.
-         */
-        cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
-        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
+        set_c0_status(STATUSF_IP2);
 }
 
-/*
- * Enable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
- */
-static void octeon_irq_ciu1_enable_v2(unsigned int irq)
+static void octeon_irq_ip2_v2(void)
 {
-        int index;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
-        struct irq_desc *desc = irq_to_desc(irq);
-
-        if ((desc->status & IRQ_DISABLED) == 0) {
-                index = next_coreid_for_irq(desc) * 2 + 1;
-                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        const unsigned long core_id = cvmx_get_core_num();
+        u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core_id * 2));
+
+        ciu_sum &= __get_cpu_var(octeon_irq_ciu0_en_mirror);
+        if (likely(ciu_sum)) {
+                int bit = fls64(ciu_sum) - 1;
+                int irq = octeon_irq_ciu_to_irq[0][bit];
+                if (likely(irq))
+                        do_IRQ(irq);
+                else
+                        spurious_interrupt();
+        } else {
+                spurious_interrupt();
         }
 }
-
-/*
- * Watchdog interrupts are special.  They are associated with a single
- * core, so we hardwire the affinity to that core.
- */
-static void octeon_irq_ciu1_wd_enable_v2(unsigned int irq)
+static void octeon_irq_ip3_v1(void)
 {
-        int index;
-        int coreid = irq - OCTEON_IRQ_WDOG0;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
-        struct irq_desc *desc = irq_to_desc(irq);
-
-        if ((desc->status & IRQ_DISABLED) == 0) {
-                index = coreid * 2 + 1;
-                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
+        u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
+
+        ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
+        clear_c0_status(STATUSF_IP3);
+        if (likely(ciu_sum)) {
+                int bit = fls64(ciu_sum) - 1;
+                int irq = octeon_irq_ciu_to_irq[1][bit];
+                if (likely(irq))
+                        do_IRQ(irq);
+                else
+                        spurious_interrupt();
+        } else {
+                spurious_interrupt();
         }
+        set_c0_status(STATUSF_IP3);
 }
 
-/*
- * Disable the irq on the current core for chips that have the EN*_W1{S,C}
- * registers.
- */
-static void octeon_irq_ciu1_ack_v2(unsigned int irq)
+static void octeon_irq_ip3_v2(void)
 {
-        int index = cvmx_get_core_num() * 2 + 1;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
-
-        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
+        u64 ciu_sum = cvmx_read_csr(CVMX_CIU_INT_SUM1);
+
+        ciu_sum &= __get_cpu_var(octeon_irq_ciu1_en_mirror);
+        if (likely(ciu_sum)) {
+                int bit = fls64(ciu_sum) - 1;
+                int irq = octeon_irq_ciu_to_irq[1][bit];
+                if (likely(irq))
+                        do_IRQ(irq);
+                else
+                        spurious_interrupt();
+        } else {
+                spurious_interrupt();
+        }
 }
 
-/*
- * Disable the irq on the all cores for chips that have the EN*_W1{S,C}
- * registers.
- */
-static void octeon_irq_ciu1_disable_all_v2(unsigned int irq)
+static void octeon_irq_ip4_mask(void)
 {
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
-        int index;
-        int cpu;
-        for_each_online_cpu(cpu) {
-                index = octeon_coreid_for_cpu(cpu) * 2 + 1;
-                cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
-        }
+        clear_c0_status(STATUSF_IP4);
+        spurious_interrupt();
 }
 
-#ifdef CONFIG_SMP
-static int octeon_irq_ciu1_set_affinity(unsigned int irq,
-                                        const struct cpumask *dest)
-{
-        int cpu;
-        struct irq_desc *desc = irq_to_desc(irq);
-        int enable_one = (desc->status & IRQ_DISABLED) == 0;
-        unsigned long flags;
-        int bit = irq - OCTEON_IRQ_WDOG0;       /* Bit 0-63 of EN1 */
+static void (*octeon_irq_ip2)(void);
+static void (*octeon_irq_ip3)(void);
+static void (*octeon_irq_ip4)(void);
 
-        /*
-         * For non-v2 CIU, we will allow only single CPU affinity.
-         * This removes the need to do locking in the .ack/.eoi
-         * functions.
-         */
-        if (cpumask_weight(dest) != 1)
-                return -EINVAL;
+void __cpuinitdata (*octeon_irq_setup_secondary)(void);
 
-        raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags);
-        for_each_online_cpu(cpu) {
-                int coreid = octeon_coreid_for_cpu(cpu);
-                uint64_t en1 =
-                        cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
-                if (cpumask_test_cpu(cpu, dest) && enable_one) {
-                        enable_one = 0;
-                        en1 |= 1ull << bit;
-                } else {
-                        en1 &= ~(1ull << bit);
-                }
-                cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
-        }
+static void __cpuinit octeon_irq_percpu_enable(void)
+{
+        irq_cpu_online();
+}
+
+static void __cpuinit octeon_irq_init_ciu_percpu(void)
+{
+        int coreid = cvmx_get_core_num();
         /*
-         * We need to do a read after the last update to make sure all
-         * of them are done.
+         * Disable All CIU Interrupts. The ones we need will be
+         * enabled later.  Read the SUM register so we know the write
+         * completed.
          */
-        cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
-        raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags);
-
-        return 0;
+        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
+        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
+        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
+        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
+        cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
 }
 
-/*
- * Set affinity for the irq for chips that have the EN*_W1{S,C}
- * registers.
- */
-static int octeon_irq_ciu1_set_affinity_v2(unsigned int irq,
-                                           const struct cpumask *dest)
+static void __cpuinit octeon_irq_setup_secondary_ciu(void)
 {
-        int cpu;
-        int index;
-        struct irq_desc *desc = irq_to_desc(irq);
-        int enable_one = (desc->status & IRQ_DISABLED) == 0;
-        u64 mask = 1ull << (irq - OCTEON_IRQ_WDOG0);
-        for_each_online_cpu(cpu) {
-                index = octeon_coreid_for_cpu(cpu) * 2 + 1;
-                if (cpumask_test_cpu(cpu, dest) && enable_one) {
-                        enable_one = 0;
-                        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1S(index), mask);
-                } else {
-                        cvmx_write_csr(CVMX_CIU_INTX_EN1_W1C(index), mask);
-                }
-        }
-        return 0;
-}
-#endif
 
-/*
- * Newer octeon chips have support for lockless CIU operation.
- */
-static struct irq_chip octeon_irq_chip_ciu1_v2 = {
-        .name = "CIU1",
-        .enable = octeon_irq_ciu1_enable_v2,
-        .disable = octeon_irq_ciu1_disable_all_v2,
-        .eoi = octeon_irq_ciu1_enable_v2,
-#ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu1_set_affinity_v2,
-#endif
-};
+        __get_cpu_var(octeon_irq_ciu0_en_mirror) = 0;
+        __get_cpu_var(octeon_irq_ciu1_en_mirror) = 0;
 
-static struct irq_chip octeon_irq_chip_ciu1 = {
-        .name = "CIU1",
-        .enable = octeon_irq_ciu1_enable,
-        .disable = octeon_irq_ciu1_disable,
-        .eoi = octeon_irq_ciu1_eoi,
-#ifdef CONFIG_SMP
-        .set_affinity = octeon_irq_ciu1_set_affinity,
-#endif
-};
+        octeon_irq_init_ciu_percpu();
+        octeon_irq_percpu_enable();
 
-static struct irq_chip octeon_irq_chip_ciu1_wd_v2 = {
-        .name = "CIU1-W",
-        .enable = octeon_irq_ciu1_wd_enable_v2,
-        .disable = octeon_irq_ciu1_disable_all_v2,
-        .eoi = octeon_irq_ciu1_wd_enable_v2,
-};
+        /* Enable the CIU lines */
+        set_c0_status(STATUSF_IP3 | STATUSF_IP2);
+        clear_c0_status(STATUSF_IP4);
+}
 
-static struct irq_chip octeon_irq_chip_ciu1_wd = {
-        .name = "CIU1-W",
-        .enable = octeon_irq_ciu1_wd_enable,
-        .disable = octeon_irq_ciu1_disable,
-        .eoi = octeon_irq_ciu1_eoi,
-};
+static void __init octeon_irq_init_ciu(void)
+{
+        unsigned int i;
+        struct irq_chip *chip;
+        struct irq_chip *chip_edge;
+        struct irq_chip *chip_mbox;
+        struct irq_chip *chip_wd;
+
+        octeon_irq_init_ciu_percpu();
+        octeon_irq_setup_secondary = octeon_irq_setup_secondary_ciu;
 
-static void (*octeon_ciu0_ack)(unsigned int);
-static void (*octeon_ciu1_ack)(unsigned int);
+        if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X) ||
+            OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
+                octeon_irq_ip2 = octeon_irq_ip2_v2;
+                octeon_irq_ip3 = octeon_irq_ip3_v2;
+                chip = &octeon_irq_chip_ciu_v2;
+                chip_edge = &octeon_irq_chip_ciu_edge_v2;
+                chip_mbox = &octeon_irq_chip_ciu_mbox_v2;
+                chip_wd = &octeon_irq_chip_ciu_wd_v2;
+        } else {
+                octeon_irq_ip2 = octeon_irq_ip2_v1;
+                octeon_irq_ip3 = octeon_irq_ip3_v1;
+                chip = &octeon_irq_chip_ciu;
+                chip_edge = &octeon_irq_chip_ciu_edge;
+                chip_mbox = &octeon_irq_chip_ciu_mbox;
+                chip_wd = &octeon_irq_chip_ciu_wd;
+        }
+        octeon_irq_ip4 = octeon_irq_ip4_mask;
+
+        /* Mips internal */
+        octeon_irq_init_core();
+
+        /* CIU_0 */
+        for (i = 0; i < 16; i++)
+                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WORKQ0, 0, i + 0, chip, handle_level_irq);
+        for (i = 0; i < 16; i++)
+                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GPIO0, 0, i + 16, chip, handle_level_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX0, 0, 32, chip_mbox, handle_percpu_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MBOX1, 0, 33, chip_mbox, handle_percpu_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART0, 0, 34, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART1, 0, 35, chip, handle_level_irq);
+
+        for (i = 0; i < 4; i++)
+                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_INT0, 0, i + 36, chip, handle_level_irq);
+        for (i = 0; i < 4; i++)
+                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_PCI_MSI0, 0, i + 40, chip, handle_level_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI, 0, 45, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_RML, 0, 46, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TRACE0, 0, 47, chip, handle_level_irq);
+
+        for (i = 0; i < 2; i++)
+                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_GMX_DRP0, 0, i + 48, chip_edge, handle_edge_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD_DRP, 0, 50, chip_edge, handle_edge_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY_ZERO, 0, 51, chip_edge, handle_edge_irq);
+
+        for (i = 0; i < 4; i++)
+                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_TIMER0, 0, i + 52, chip_edge, handle_edge_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB0, 0, 56, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PCM, 0, 57, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MPI, 0, 58, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TWSI2, 0, 59, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_POWIQ, 0, 60, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPDPPTHR, 0, 61, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII0, 0, 62, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_BOOTDMA, 0, 63, chip, handle_level_irq);
+
+        /* CIU_1 */
+        for (i = 0; i < 16; i++)
+                octeon_irq_set_ciu_mapping(i + OCTEON_IRQ_WDOG0, 1, i + 0, chip_wd, handle_level_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_UART2, 1, 16, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_USB1, 1, 17, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MII1, 1, 18, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_NAND, 1, 19, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_MIO, 1, 20, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IOB, 1, 21, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_FPA, 1, 22, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_POW, 1, 23, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_L2C, 1, 24, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_IPD, 1, 25, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PIP, 1, 26, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PKO, 1, 27, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_ZIP, 1, 28, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_TIM, 1, 29, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_RAD, 1, 30, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_KEY, 1, 31, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFA, 1, 32, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_USBCTL, 1, 33, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_SLI, 1, 34, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_DPI, 1, 35, chip, handle_level_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGX0, 1, 36, chip, handle_level_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_AGL, 1, 46, chip, handle_level_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PTP, 1, 47, chip_edge, handle_edge_irq);
+
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM0, 1, 48, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_PEM1, 1, 49, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO0, 1, 50, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_SRIO1, 1, 51, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_LMC0, 1, 52, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_DFM, 1, 56, chip, handle_level_irq);
+        octeon_irq_set_ciu_mapping(OCTEON_IRQ_RST, 1, 63, chip, handle_level_irq);
+
+        /* Enable the CIU lines */
+        set_c0_status(STATUSF_IP3 | STATUSF_IP2);
+        clear_c0_status(STATUSF_IP4);
+}
 
 void __init arch_init_irq(void)
 {
-        unsigned int irq;
-        struct irq_chip *chip0;
-        struct irq_chip *chip0_mbox;
-        struct irq_chip *chip1;
-        struct irq_chip *chip1_wd;
-
 #ifdef CONFIG_SMP
         /* Set the default affinity to the boot cpu. */
         cpumask_clear(irq_default_affinity);
         cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
 #endif
-
-        if (NR_IRQS < OCTEON_IRQ_LAST)
-                pr_err("octeon_irq_init: NR_IRQS is set too low\n");
-
-        if (OCTEON_IS_MODEL(OCTEON_CN58XX_PASS2_X) ||
-            OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
-            OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
-                octeon_ciu0_ack = octeon_irq_ciu0_ack_v2;
-                octeon_ciu1_ack = octeon_irq_ciu1_ack_v2;
-                chip0 = &octeon_irq_chip_ciu0_v2;
-                chip0_mbox = &octeon_irq_chip_ciu0_mbox_v2;
-                chip1 = &octeon_irq_chip_ciu1_v2;
-                chip1_wd = &octeon_irq_chip_ciu1_wd_v2;
-        } else {
-                octeon_ciu0_ack = octeon_irq_ciu0_ack;
-                octeon_ciu1_ack = octeon_irq_ciu1_ack;
-                chip0 = &octeon_irq_chip_ciu0;
-                chip0_mbox = &octeon_irq_chip_ciu0_mbox;
-                chip1 = &octeon_irq_chip_ciu1;
-                chip1_wd = &octeon_irq_chip_ciu1_wd;
-        }
-
-        /* 0 - 15 reserved for i8259 master and slave controller. */
-
-        /* 17 - 23 Mips internal */
-        for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
-                set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
-                                         handle_percpu_irq);
-        }
-
-        /* 24 - 87 CIU_INT_SUM0 */
-        for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
-                switch (irq) {
-                case OCTEON_IRQ_MBOX0:
-                case OCTEON_IRQ_MBOX1:
-                        set_irq_chip_and_handler(irq, chip0_mbox, handle_percpu_irq);
-                        break;
-                default:
-                        set_irq_chip_and_handler(irq, chip0, handle_fasteoi_irq);
-                        break;
-                }
-        }
-
-        /* 88 - 151 CIU_INT_SUM1 */
-        for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_WDOG15; irq++)
-                set_irq_chip_and_handler(irq, chip1_wd, handle_fasteoi_irq);
-
-        for (irq = OCTEON_IRQ_UART2; irq <= OCTEON_IRQ_RESERVED151; irq++)
-                set_irq_chip_and_handler(irq, chip1, handle_fasteoi_irq);
-
-        set_c0_status(0x300 << 2);
+        octeon_irq_init_ciu();
 }
 
 asmlinkage void plat_irq_dispatch(void)
 {
-        const unsigned long core_id = cvmx_get_core_num();
-        const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
-        const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
-        const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
-        const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
         unsigned long cop0_cause;
         unsigned long cop0_status;
-        uint64_t ciu_en;
-        uint64_t ciu_sum;
-        unsigned int irq;
 
         while (1) {
                 cop0_cause = read_c0_cause();
@@ -757,33 +1021,16 @@ asmlinkage void plat_irq_dispatch(void)
                 cop0_cause &= cop0_status;
                 cop0_cause &= ST0_IM;
 
-                if (unlikely(cop0_cause & STATUSF_IP2)) {
-                        ciu_sum = cvmx_read_csr(ciu_sum0_address);
-                        ciu_en = cvmx_read_csr(ciu_en0_address);
-                        ciu_sum &= ciu_en;
-                        if (likely(ciu_sum)) {
-                                irq = fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1;
-                                octeon_ciu0_ack(irq);
-                                do_IRQ(irq);
-                        } else {
-                                spurious_interrupt();
-                        }
-                } else if (unlikely(cop0_cause & STATUSF_IP3)) {
-                        ciu_sum = cvmx_read_csr(ciu_sum1_address);
-                        ciu_en = cvmx_read_csr(ciu_en1_address);
-                        ciu_sum &= ciu_en;
-                        if (likely(ciu_sum)) {
-                                irq = fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1;
-                                octeon_ciu1_ack(irq);
-                                do_IRQ(irq);
-                        } else {
-                                spurious_interrupt();
-                        }
-                } else if (likely(cop0_cause)) {
+                if (unlikely(cop0_cause & STATUSF_IP2))
+                        octeon_irq_ip2();
+                else if (unlikely(cop0_cause & STATUSF_IP3))
+                        octeon_irq_ip3();
+                else if (unlikely(cop0_cause & STATUSF_IP4))
+                        octeon_irq_ip4();
+                else if (likely(cop0_cause))
                         do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
-                } else {
+                else
                         break;
-                }
         }
 }
 
@@ -791,83 +1038,7 @@ asmlinkage void plat_irq_dispatch(void)
 
 void fixup_irqs(void)
 {
-        int irq;
-        struct irq_desc *desc;
-        cpumask_t new_affinity;
-        unsigned long flags;
-        int do_set_affinity;
-        int cpu;
-
-        cpu = smp_processor_id();
-
-        for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++)
-                octeon_irq_core_disable_local(irq);
-
-        for (irq = OCTEON_IRQ_WORKQ0; irq < OCTEON_IRQ_LAST; irq++) {
-                desc = irq_to_desc(irq);
-                switch (irq) {
-                case OCTEON_IRQ_MBOX0:
-                case OCTEON_IRQ_MBOX1:
-                        /* The eoi function will disable them on this CPU. */
-                        desc->chip->eoi(irq);
-                        break;
-                case OCTEON_IRQ_WDOG0:
-                case OCTEON_IRQ_WDOG1:
-                case OCTEON_IRQ_WDOG2:
-                case OCTEON_IRQ_WDOG3:
-                case OCTEON_IRQ_WDOG4:
-                case OCTEON_IRQ_WDOG5:
-                case OCTEON_IRQ_WDOG6:
-                case OCTEON_IRQ_WDOG7:
-                case OCTEON_IRQ_WDOG8:
-                case OCTEON_IRQ_WDOG9:
-                case OCTEON_IRQ_WDOG10:
-                case OCTEON_IRQ_WDOG11:
-                case OCTEON_IRQ_WDOG12:
-                case OCTEON_IRQ_WDOG13:
-                case OCTEON_IRQ_WDOG14:
-                case OCTEON_IRQ_WDOG15:
-                        /*
-                         * These have special per CPU semantics and
-                         * are handled in the watchdog driver.
-                         */
-                        break;
-                default:
-                        raw_spin_lock_irqsave(&desc->lock, flags);
-                        /*
-                         * If this irq has an action, it is in use and
-                         * must be migrated if it has affinity to this
-                         * cpu.
-                         */
-                        if (desc->action && cpumask_test_cpu(cpu, desc->affinity)) {
-                                if (cpumask_weight(desc->affinity) > 1) {
-                                        /*
-                                         * It has multi CPU affinity,
-                                         * just remove this CPU from
-                                         * the affinity set.
-                                         */
-                                        cpumask_copy(&new_affinity, desc->affinity);
-                                        cpumask_clear_cpu(cpu, &new_affinity);
-                                } else {
-                                        /*
-                                         * Otherwise, put it on lowest
-                                         * numbered online CPU.
-                                         */
-                                        cpumask_clear(&new_affinity);
-                                        cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
-                                }
-                                do_set_affinity = 1;
-                        } else {
-                                do_set_affinity = 0;
-                        }
-                        raw_spin_unlock_irqrestore(&desc->lock, flags);
-
-                        if (do_set_affinity)
-                                irq_set_affinity(irq, &new_affinity);
-
-                        break;
-                }
-        }
+        irq_cpu_offline();
 }
 
 #endif /* CONFIG_HOTPLUG_CPU */
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index b0c3686c96dd..8b139bf4a1b5 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -420,7 +420,6 @@ void octeon_user_io_init(void)
 void __init prom_init(void)
 {
         struct cvmx_sysinfo *sysinfo;
-        const int coreid = cvmx_get_core_num();
         int i;
         int argc;
 #ifdef CONFIG_CAVIUM_RESERVE32
@@ -537,17 +536,6 @@ void __init prom_init(void)
 
         octeon_uart = octeon_get_boot_uart();
 
-        /*
-         * Disable All CIU Interrupts. The ones we need will be
-         * enabled later.  Read the SUM register so we know the write
-         * completed.
-         */
-        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
-        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
-        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
-        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
-        cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
-
 #ifdef CONFIG_SMP
         octeon_write_lcd("LinuxSMP");
 #else
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
index 391cefe556b3..ba78b21cc8d0 100644
--- a/arch/mips/cavium-octeon/smp.c
+++ b/arch/mips/cavium-octeon/smp.c
@@ -171,41 +171,19 @@ static void octeon_boot_secondary(int cpu, struct task_struct *idle)
  * After we've done initial boot, this function is called to allow the
  * board code to clean up state, if needed
  */
-static void octeon_init_secondary(void)
+static void __cpuinit octeon_init_secondary(void)
 {
-        const int coreid = cvmx_get_core_num();
-        union cvmx_ciu_intx_sum0 interrupt_enable;
         unsigned int sr;
 
-#ifdef CONFIG_HOTPLUG_CPU
-        struct linux_app_boot_info *labi;
-
-        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
-
-        if (labi->labi_signature != LABI_SIGNATURE)
-                panic("The bootloader version on this board is incorrect.");
-#endif
-
         sr = set_c0_status(ST0_BEV);
         write_c0_ebase((u32)ebase);
         write_c0_status(sr);
 
         octeon_check_cpu_bist();
         octeon_init_cvmcount();
-        /*
-        pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
-        */
-        /* Enable Mailbox interrupts to this core. These are the only
-           interrupts allowed on line 3 */
-        cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
-        interrupt_enable.u64 = 0;
-        interrupt_enable.s.mbox = 0x3;
-        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
-        cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
-        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
-        cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
-        /* Enable core interrupt processing for 2,3 and 7 */
-        set_c0_status(0x8c01);
+
+        octeon_irq_setup_secondary();
+        raw_local_irq_enable();
 }
 
 /**
@@ -214,6 +192,15 @@ static void octeon_init_secondary(void)
  */
 void octeon_prepare_cpus(unsigned int max_cpus)
 {
+#ifdef CONFIG_HOTPLUG_CPU
+        struct linux_app_boot_info *labi;
+
+        labi = (struct linux_app_boot_info *)PHYS_TO_XKSEG_CACHED(LABI_ADDR_IN_BOOTLOADER);
+
+        if (labi->labi_signature != LABI_SIGNATURE)
+                panic("The bootloader version on this board is incorrect.");
+#endif
+
         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
         if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_DISABLED,
                         "mailbox0", mailbox_interrupt)) {
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 8d9a5fc607e4..824e08c73798 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -68,10 +68,10 @@ void __init init_ioasic_irqs(int base)
         fast_iob();
 
         for (i = base; i < base + IO_INR_DMA; i++)
-                set_irq_chip_and_handler(i, &ioasic_irq_type,
+                irq_set_chip_and_handler(i, &ioasic_irq_type,
                                          handle_level_irq);
         for (; i < base + IO_IRQ_LINES; i++)
-                set_irq_chip(i, &ioasic_dma_irq_type);
+                irq_set_chip(i, &ioasic_dma_irq_type);
 
         ioasic_irq_base = base;
 }
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index ef31d98c4fb8..37199f742c45 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -73,7 +73,7 @@ void __init init_kn02_irqs(int base)
         iob();
 
         for (i = base; i < base + KN02_IRQ_LINES; i++)
-                set_irq_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &kn02_irq_type, handle_level_irq);
 
         kn02_irq_base = base;
 }
diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c
index 9b1207ae2256..3dbd7a5a6ad3 100644
--- a/arch/mips/emma/markeins/irq.c
+++ b/arch/mips/emma/markeins/irq.c
@@ -69,7 +69,7 @@ void emma2rh_irq_init(void)
         u32 i;
 
         for (i = 0; i < NUM_EMMA2RH_IRQ; i++)
-                set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
+                irq_set_chip_and_handler_name(EMMA2RH_IRQ_BASE + i,
                                               &emma2rh_irq_controller,
                                               handle_level_irq, "level");
 }
@@ -105,7 +105,7 @@ void emma2rh_sw_irq_init(void)
         u32 i;
 
         for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++)
-                set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
+                irq_set_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i,
                                               &emma2rh_sw_irq_controller,
                                               handle_level_irq, "level");
 }
@@ -162,7 +162,7 @@ void emma2rh_gpio_irq_init(void)
         u32 i;
 
         for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++)
-                set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
+                irq_set_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i,
                                               &emma2rh_gpio_irq_controller,
                                               handle_edge_irq, "edge");
 }
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
index 6ddab8aef644..5b05f186e395 100644
--- a/arch/mips/include/asm/mach-cavium-octeon/irq.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -11,172 +11,91 @@
 #define NR_IRQS OCTEON_IRQ_LAST
 #define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
 
-/* 0 - 7 represent the i8259 master */
-#define OCTEON_IRQ_I8259M0      0
-#define OCTEON_IRQ_I8259M1      1
-#define OCTEON_IRQ_I8259M2      2
-#define OCTEON_IRQ_I8259M3      3
-#define OCTEON_IRQ_I8259M4      4
-#define OCTEON_IRQ_I8259M5      5
-#define OCTEON_IRQ_I8259M6      6
-#define OCTEON_IRQ_I8259M7      7
-/* 8 - 15 represent the i8259 slave */
-#define OCTEON_IRQ_I8259S0      8
-#define OCTEON_IRQ_I8259S1      9
-#define OCTEON_IRQ_I8259S2      10
-#define OCTEON_IRQ_I8259S3      11
-#define OCTEON_IRQ_I8259S4      12
-#define OCTEON_IRQ_I8259S5      13
-#define OCTEON_IRQ_I8259S6      14
-#define OCTEON_IRQ_I8259S7      15
-/* 16 - 23 represent the 8 MIPS standard interrupt sources */
-#define OCTEON_IRQ_SW0          16
-#define OCTEON_IRQ_SW1          17
-#define OCTEON_IRQ_CIU0         18
-#define OCTEON_IRQ_CIU1         19
-#define OCTEON_IRQ_CIU4         20
-#define OCTEON_IRQ_5            21
-#define OCTEON_IRQ_PERF         22
-#define OCTEON_IRQ_TIMER        23
-/* 24 - 87 represent the sources in CIU_INTX_EN0 */
-#define OCTEON_IRQ_WORKQ0       24
-#define OCTEON_IRQ_WORKQ1       25
-#define OCTEON_IRQ_WORKQ2       26
-#define OCTEON_IRQ_WORKQ3       27
-#define OCTEON_IRQ_WORKQ4       28
-#define OCTEON_IRQ_WORKQ5       29
-#define OCTEON_IRQ_WORKQ6       30
-#define OCTEON_IRQ_WORKQ7       31
-#define OCTEON_IRQ_WORKQ8       32
-#define OCTEON_IRQ_WORKQ9       33
-#define OCTEON_IRQ_WORKQ10      34
-#define OCTEON_IRQ_WORKQ11      35
-#define OCTEON_IRQ_WORKQ12      36
-#define OCTEON_IRQ_WORKQ13      37
-#define OCTEON_IRQ_WORKQ14      38
-#define OCTEON_IRQ_WORKQ15      39
-#define OCTEON_IRQ_GPIO0        40
-#define OCTEON_IRQ_GPIO1        41
-#define OCTEON_IRQ_GPIO2        42
-#define OCTEON_IRQ_GPIO3        43
-#define OCTEON_IRQ_GPIO4        44
-#define OCTEON_IRQ_GPIO5        45
-#define OCTEON_IRQ_GPIO6        46
-#define OCTEON_IRQ_GPIO7        47
-#define OCTEON_IRQ_GPIO8        48
-#define OCTEON_IRQ_GPIO9        49
-#define OCTEON_IRQ_GPIO10       50
-#define OCTEON_IRQ_GPIO11       51
-#define OCTEON_IRQ_GPIO12       52
-#define OCTEON_IRQ_GPIO13       53
-#define OCTEON_IRQ_GPIO14       54
-#define OCTEON_IRQ_GPIO15       55
-#define OCTEON_IRQ_MBOX0        56
-#define OCTEON_IRQ_MBOX1        57
-#define OCTEON_IRQ_UART0        58
-#define OCTEON_IRQ_UART1        59
-#define OCTEON_IRQ_PCI_INT0     60
-#define OCTEON_IRQ_PCI_INT1     61
-#define OCTEON_IRQ_PCI_INT2     62
-#define OCTEON_IRQ_PCI_INT3     63
-#define OCTEON_IRQ_PCI_MSI0     64
-#define OCTEON_IRQ_PCI_MSI1     65
-#define OCTEON_IRQ_PCI_MSI2     66
-#define OCTEON_IRQ_PCI_MSI3     67
-#define OCTEON_IRQ_RESERVED68   68      /* Summary of CIU_INT_SUM1 */
-#define OCTEON_IRQ_TWSI         69
-#define OCTEON_IRQ_RML          70
-#define OCTEON_IRQ_TRACE        71
-#define OCTEON_IRQ_GMX_DRP0     72
-#define OCTEON_IRQ_GMX_DRP1     73
-#define OCTEON_IRQ_IPD_DRP      74
-#define OCTEON_IRQ_KEY_ZERO     75
-#define OCTEON_IRQ_TIMER0       76
-#define OCTEON_IRQ_TIMER1       77
-#define OCTEON_IRQ_TIMER2       78
-#define OCTEON_IRQ_TIMER3       79
-#define OCTEON_IRQ_USB0         80
-#define OCTEON_IRQ_PCM          81
-#define OCTEON_IRQ_MPI          82
-#define OCTEON_IRQ_TWSI2        83
-#define OCTEON_IRQ_POWIQ        84
-#define OCTEON_IRQ_IPDPPTHR     85
-#define OCTEON_IRQ_MII0         86
-#define OCTEON_IRQ_BOOTDMA      87
-/* 88 - 151 represent the sources in CIU_INTX_EN1 */
-#define OCTEON_IRQ_WDOG0        88
-#define OCTEON_IRQ_WDOG1        89
-#define OCTEON_IRQ_WDOG2        90
-#define OCTEON_IRQ_WDOG3        91
-#define OCTEON_IRQ_WDOG4        92
-#define OCTEON_IRQ_WDOG5        93
-#define OCTEON_IRQ_WDOG6        94
-#define OCTEON_IRQ_WDOG7        95
-#define OCTEON_IRQ_WDOG8        96
-#define OCTEON_IRQ_WDOG9        97
-#define OCTEON_IRQ_WDOG10       98
-#define OCTEON_IRQ_WDOG11       99
-#define OCTEON_IRQ_WDOG12       100
-#define OCTEON_IRQ_WDOG13       101
-#define OCTEON_IRQ_WDOG14       102
-#define OCTEON_IRQ_WDOG15       103
-#define OCTEON_IRQ_UART2        104
-#define OCTEON_IRQ_USB1         105
-#define OCTEON_IRQ_MII1         106
-#define OCTEON_IRQ_RESERVED107  107
-#define OCTEON_IRQ_RESERVED108  108
-#define OCTEON_IRQ_RESERVED109  109
-#define OCTEON_IRQ_RESERVED110  110
-#define OCTEON_IRQ_RESERVED111  111
-#define OCTEON_IRQ_RESERVED112  112
-#define OCTEON_IRQ_RESERVED113  113
-#define OCTEON_IRQ_RESERVED114  114
-#define OCTEON_IRQ_RESERVED115  115
-#define OCTEON_IRQ_RESERVED116  116
-#define OCTEON_IRQ_RESERVED117  117
-#define OCTEON_IRQ_RESERVED118  118
-#define OCTEON_IRQ_RESERVED119  119
-#define OCTEON_IRQ_RESERVED120  120
-#define OCTEON_IRQ_RESERVED121  121
-#define OCTEON_IRQ_RESERVED122  122
-#define OCTEON_IRQ_RESERVED123  123
-#define OCTEON_IRQ_RESERVED124  124
-#define OCTEON_IRQ_RESERVED125  125
-#define OCTEON_IRQ_RESERVED126  126
-#define OCTEON_IRQ_RESERVED127  127
-#define OCTEON_IRQ_RESERVED128  128
-#define OCTEON_IRQ_RESERVED129  129
-#define OCTEON_IRQ_RESERVED130  130
-#define OCTEON_IRQ_RESERVED131  131
-#define OCTEON_IRQ_RESERVED132  132
-#define OCTEON_IRQ_RESERVED133  133
-#define OCTEON_IRQ_RESERVED134  134
-#define OCTEON_IRQ_RESERVED135  135
-#define OCTEON_IRQ_RESERVED136  136
-#define OCTEON_IRQ_RESERVED137  137
-#define OCTEON_IRQ_RESERVED138  138
-#define OCTEON_IRQ_RESERVED139  139
-#define OCTEON_IRQ_RESERVED140  140
-#define OCTEON_IRQ_RESERVED141  141
-#define OCTEON_IRQ_RESERVED142  142
-#define OCTEON_IRQ_RESERVED143  143
-#define OCTEON_IRQ_RESERVED144  144
-#define OCTEON_IRQ_RESERVED145  145
-#define OCTEON_IRQ_RESERVED146  146
-#define OCTEON_IRQ_RESERVED147  147
-#define OCTEON_IRQ_RESERVED148  148
-#define OCTEON_IRQ_RESERVED149  149
-#define OCTEON_IRQ_RESERVED150  150
-#define OCTEON_IRQ_RESERVED151  151
+enum octeon_irq {
+/* 1 - 8 represent the 8 MIPS standard interrupt sources */
+        OCTEON_IRQ_SW0 = 1,
+        OCTEON_IRQ_SW1,
+/* CIU0, CUI2, CIU4 are 3, 4, 5 */
+        OCTEON_IRQ_5 = 6,
+        OCTEON_IRQ_PERF,
+        OCTEON_IRQ_TIMER,
+/* sources in CIU_INTX_EN0 */
+        OCTEON_IRQ_WORKQ0,
+        OCTEON_IRQ_GPIO0 = OCTEON_IRQ_WORKQ0 + 16,
+        OCTEON_IRQ_WDOG0 = OCTEON_IRQ_GPIO0 + 16,
+        OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
+        OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
+        OCTEON_IRQ_MBOX1,
+        OCTEON_IRQ_UART0,
+        OCTEON_IRQ_UART1,
+        OCTEON_IRQ_UART2,
+        OCTEON_IRQ_PCI_INT0,
+        OCTEON_IRQ_PCI_INT1,
+        OCTEON_IRQ_PCI_INT2,
+        OCTEON_IRQ_PCI_INT3,
+        OCTEON_IRQ_PCI_MSI0,
+        OCTEON_IRQ_PCI_MSI1,
+        OCTEON_IRQ_PCI_MSI2,
+        OCTEON_IRQ_PCI_MSI3,
+
+        OCTEON_IRQ_TWSI,
+        OCTEON_IRQ_TWSI2,
+        OCTEON_IRQ_RML,
+        OCTEON_IRQ_TRACE0,
+        OCTEON_IRQ_GMX_DRP0 = OCTEON_IRQ_TRACE0 + 4,
+        OCTEON_IRQ_IPD_DRP = OCTEON_IRQ_GMX_DRP0 + 5,
+        OCTEON_IRQ_KEY_ZERO,
+        OCTEON_IRQ_TIMER0,
+        OCTEON_IRQ_TIMER1,
+        OCTEON_IRQ_TIMER2,
+        OCTEON_IRQ_TIMER3,
+        OCTEON_IRQ_USB0,
+        OCTEON_IRQ_USB1,
+        OCTEON_IRQ_PCM,
+        OCTEON_IRQ_MPI,
+        OCTEON_IRQ_POWIQ,
+        OCTEON_IRQ_IPDPPTHR,
+        OCTEON_IRQ_MII0,
+        OCTEON_IRQ_MII1,
+        OCTEON_IRQ_BOOTDMA,
+
+        OCTEON_IRQ_NAND,
+        OCTEON_IRQ_MIO,         /* Summary of MIO_BOOT_ERR */
+        OCTEON_IRQ_IOB,         /* Summary of IOB_INT_SUM */
+        OCTEON_IRQ_FPA,         /* Summary of FPA_INT_SUM */
+        OCTEON_IRQ_POW,         /* Summary of POW_ECC_ERR */
+        OCTEON_IRQ_L2C,         /* Summary of L2C_INT_STAT */
+        OCTEON_IRQ_IPD,         /* Summary of IPD_INT_SUM */
+        OCTEON_IRQ_PIP,         /* Summary of PIP_INT_REG */
+        OCTEON_IRQ_PKO,         /* Summary of PKO_REG_ERROR */
+        OCTEON_IRQ_ZIP,         /* Summary of ZIP_ERROR */
+        OCTEON_IRQ_TIM,         /* Summary of TIM_REG_ERROR */
+        OCTEON_IRQ_RAD,         /* Summary of RAD_REG_ERROR */
+        OCTEON_IRQ_KEY,         /* Summary of KEY_INT_SUM */
+        OCTEON_IRQ_DFA,         /* Summary of DFA */
+        OCTEON_IRQ_USBCTL,      /* Summary of USBN0_INT_SUM */
+        OCTEON_IRQ_SLI,         /* Summary of SLI_INT_SUM */
+        OCTEON_IRQ_DPI,         /* Summary of DPI_INT_SUM */
+        OCTEON_IRQ_AGX0,        /* Summary of GMX0*+PCS0_INT*_REG */
+        OCTEON_IRQ_AGL  = OCTEON_IRQ_AGX0 + 5,
+        OCTEON_IRQ_PTP,
+        OCTEON_IRQ_PEM0,
+        OCTEON_IRQ_PEM1,
+        OCTEON_IRQ_SRIO0,
+        OCTEON_IRQ_SRIO1,
+        OCTEON_IRQ_LMC0,
+        OCTEON_IRQ_DFM = OCTEON_IRQ_LMC0 + 4,           /* Summary of DFM */
+        OCTEON_IRQ_RST,
+};
 
 #ifdef CONFIG_PCI_MSI
-/* 152 - 215 represent the MSI interrupts 0-63 */
-#define OCTEON_IRQ_MSI_BIT0     152
-#define OCTEON_IRQ_MSI_LAST     (OCTEON_IRQ_MSI_BIT0 + 255)
+/* 152 - 407 represent the MSI interrupts 0-255 */
+#define OCTEON_IRQ_MSI_BIT0     (OCTEON_IRQ_RST + 1)
 
-#define OCTEON_IRQ_LAST         (OCTEON_IRQ_MSI_LAST + 1)
+#define OCTEON_IRQ_MSI_LAST      (OCTEON_IRQ_MSI_BIT0 + 255)
+#define OCTEON_IRQ_LAST          (OCTEON_IRQ_MSI_LAST + 1)
 #else
-#define OCTEON_IRQ_LAST         152
+#define OCTEON_IRQ_LAST         (OCTEON_IRQ_RST + 1)
 #endif
 
 #endif
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index 6b34afd0d4e7..f72f768cd3a4 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -257,4 +257,6 @@ extern struct cvmx_bootinfo *octeon_bootinfo;
 
 extern uint64_t octeon_bootloader_entry_addr;
 
+extern void (*octeon_irq_setup_secondary)(void);
+
 #endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/unistd.h b/arch/mips/include/asm/unistd.h
index dae22c1d2c82..fa2e37ea2be1 100644
--- a/arch/mips/include/asm/unistd.h
+++ b/arch/mips/include/asm/unistd.h
@@ -1005,7 +1005,7 @@
 #define __NR_name_to_handle_at          (__NR_Linux + 303)
 #define __NR_open_by_handle_at          (__NR_Linux + 304)
 #define __NR_clock_adjtime              (__NR_Linux + 305)
-#define __NR_clock_adjtime              (__NR_Linux + 306)
+#define __NR_syncfs                     (__NR_Linux + 306)
 
 /*
  * Offset of the last N32 flavoured syscall
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index 40f7c6b1e260..260df4750949 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -56,7 +56,7 @@ void __init init_r4030_ints(void)
         int i;
 
         for (i = JAZZ_IRQ_START; i <= JAZZ_IRQ_END; i++)
-                set_irq_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &r4030_irq_type, handle_level_irq);
 
         r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
         r4030_read_reg16(JAZZ_IO_IRQ_SOURCE);           /* clear pending IRQs */
diff --git a/arch/mips/jz4740/gpio.c b/arch/mips/jz4740/gpio.c
index bd2fc29b95e0..73031f7fc827 100644
--- a/arch/mips/jz4740/gpio.c
+++ b/arch/mips/jz4740/gpio.c
@@ -306,7 +306,7 @@ static void jz_gpio_irq_demux_handler(unsigned int irq, struct irq_desc *desc)
         uint32_t flag;
         unsigned int gpio_irq;
         unsigned int gpio_bank;
-        struct jz_gpio_chip *chip = get_irq_desc_data(desc);
+        struct jz_gpio_chip *chip = irq_desc_get_handler_data(desc);
 
         gpio_bank = JZ4740_IRQ_GPIO0 - irq;
 
@@ -416,7 +416,7 @@ static int jz_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
                 chip->wakeup &= ~IRQ_TO_BIT(data->irq);
         spin_unlock(&chip->lock);
 
-        set_irq_wake(chip->irq, on);
+        irq_set_irq_wake(chip->irq, on);
         return 0;
 }
 
@@ -510,14 +510,14 @@ static int jz4740_gpio_chip_init(struct jz_gpio_chip *chip, unsigned int id)
         gpiochip_add(&chip->gpio_chip);
 
         chip->irq = JZ4740_IRQ_INTC_GPIO(id);
-        set_irq_data(chip->irq, chip);
-        set_irq_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
+        irq_set_handler_data(chip->irq, chip);
+        irq_set_chained_handler(chip->irq, jz_gpio_irq_demux_handler);
 
         for (irq = chip->irq_base; irq < chip->irq_base + chip->gpio_chip.ngpio; ++irq) {
                 irq_set_lockdep_class(irq, &gpio_lock_class);
-                set_irq_chip_data(irq, chip);
-                set_irq_chip_and_handler(irq, &jz_gpio_irq_chip,
-                        handle_level_irq);
+                irq_set_chip_data(irq, chip);
+                irq_set_chip_and_handler(irq, &jz_gpio_irq_chip,
+                                         handle_level_irq);
         }
 
         return 0;
diff --git a/arch/mips/jz4740/irq.c b/arch/mips/jz4740/irq.c
index dcc5593a9389..d82c0c430e03 100644
--- a/arch/mips/jz4740/irq.c
+++ b/arch/mips/jz4740/irq.c
@@ -104,8 +104,8 @@ void __init arch_init_irq(void)
         writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);
 
         for (i = JZ4740_IRQ_BASE; i < JZ4740_IRQ_BASE + 32; i++) {
-                set_irq_chip_data(i, (void *)IRQ_BIT(i));
-                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+                irq_set_chip_data(i, (void *)IRQ_BIT(i));
+                irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
         }
 
         setup_irq(2, &jz4740_cascade_action);
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index e221662bb80c..c018696765d4 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -110,7 +110,7 @@ int i8259A_irq_pending(unsigned int irq)
 void make_8259A_irq(unsigned int irq)
 {
         disable_irq_nosync(irq);
-        set_irq_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
+        irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
         enable_irq(irq);
 }
 
@@ -336,8 +336,8 @@ void __init init_i8259_irqs(void)
         init_8259A(0);
 
         for (i = I8259A_IRQ_BASE; i < I8259A_IRQ_BASE + 16; i++) {
-                set_irq_chip_and_handler(i, &i8259A_chip, handle_level_irq);
-                set_irq_probe(i);
+                irq_set_chip_and_handler(i, &i8259A_chip, handle_level_irq);
+                irq_set_probe(i);
         }
 
         setup_irq(I8259A_IRQ_BASE + PIC_CASCADE_IR, &irq2);
diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c
index 43cd9628251a..0c527f652196 100644
--- a/arch/mips/kernel/irq-gic.c
+++ b/arch/mips/kernel/irq-gic.c
@@ -229,7 +229,7 @@ static void __init gic_basic_init(int numintrs, int numvpes,
         vpe_local_setup(numvpes);
 
         for (i = _irqbase; i < (_irqbase + numintrs); i++)
-                set_irq_chip(i, &gic_irq_controller);
+                irq_set_chip(i, &gic_irq_controller);
 }
 
 void __init gic_init(unsigned long gic_base_addr,
diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c
index 7fd176fa367a..883fc6cead36 100644
--- a/arch/mips/kernel/irq-gt641xx.c
+++ b/arch/mips/kernel/irq-gt641xx.c
@@ -126,6 +126,6 @@ void __init gt641xx_irq_init(void)
          * bit31: logical or of bits[25:1].
          */
         for (i = 1; i < 30; i++)
-                set_irq_chip_and_handler(GT641XX_IRQ_BASE + i,
-                                         &gt641xx_irq_chip, handle_level_irq);
+                irq_set_chip_and_handler(GT641XX_IRQ_BASE + i,
+                                         &gt641xx_irq_chip, handle_level_irq);
 }
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index fc800cd9947e..0c6afeed89d2 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -137,16 +137,20 @@ void __init init_msc_irqs(unsigned long icubase, unsigned int irqbase, msc_irqma
 
                 switch (imp->im_type) {
                 case MSC01_IRQ_EDGE:
-                        set_irq_chip_and_handler_name(irqbase + n,
-                                &msc_edgeirq_type, handle_edge_irq, "edge");
+                        irq_set_chip_and_handler_name(irqbase + n,
+                                                      &msc_edgeirq_type,
+                                                      handle_edge_irq,
+                                                      "edge");
                         if (cpu_has_veic)
                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
                         else
                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
                         break;
                 case MSC01_IRQ_LEVEL:
-                        set_irq_chip_and_handler_name(irqbase+n,
-                                &msc_levelirq_type, handle_level_irq, "level");
+                        irq_set_chip_and_handler_name(irqbase + n,
+                                                      &msc_levelirq_type,
+                                                      handle_level_irq,
+                                                      "level");
                         if (cpu_has_veic)
                                 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
                         else
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index fd24fd98b041..a8a8977d5887 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -45,6 +45,6 @@ void __init rm7k_cpu_irq_init(void)
         clear_c0_intcontrol(0x00000f00);                /* Mask all */
 
         for (i = base; i < base + 4; i++)
-                set_irq_chip_and_handler(i, &rm7k_irq_controller,
+                irq_set_chip_and_handler(i, &rm7k_irq_controller,
                                          handle_percpu_irq);
 }
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index ca463ec9bad5..38874a4b9255 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -98,10 +98,10 @@ void __init rm9k_cpu_irq_init(void)
         clear_c0_intcontrol(0x0000f000);                /* Mask all */
 
         for (i = base; i < base + 4; i++)
-                set_irq_chip_and_handler(i, &rm9k_irq_controller,
+                irq_set_chip_and_handler(i, &rm9k_irq_controller,
                                          handle_level_irq);
 
         rm9000_perfcount_irq = base + 1;
-        set_irq_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
+        irq_set_chip_and_handler(rm9000_perfcount_irq, &rm9k_perfcounter_irq,
                                  handle_percpu_irq);
 }
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 1b68ebe1b458..9b734d74ae8e 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -102,7 +102,7 @@ void __init init_IRQ(void)
 #endif
 
         for (i = 0; i < NR_IRQS; i++)
-                set_irq_noprobe(i);
+                irq_set_noprobe(i);
 
         arch_init_irq();
 
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index fd945c56bc33..6e71b284f6c9 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -109,10 +109,10 @@ void __init mips_cpu_irq_init(void)
          */
         if (cpu_has_mipsmt)
                 for (i = irq_base; i < irq_base + 2; i++)
-                        set_irq_chip_and_handler(i, &mips_mt_cpu_irq_controller,
+                        irq_set_chip_and_handler(i, &mips_mt_cpu_irq_controller,
                                                  handle_percpu_irq);
 
         for (i = irq_base + 2; i < irq_base + 8; i++)
-                set_irq_chip_and_handler(i, &mips_cpu_irq_controller,
+                irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
                                          handle_percpu_irq);
 }
diff --git a/arch/mips/kernel/irq_txx9.c b/arch/mips/kernel/irq_txx9.c
index 526e1581549a..b0c55b50218e 100644
--- a/arch/mips/kernel/irq_txx9.c
+++ b/arch/mips/kernel/irq_txx9.c
@@ -154,8 +154,8 @@ void __init txx9_irq_init(unsigned long baseaddr)
         for (i = 0; i < TXx9_MAX_IR; i++) {
                 txx9irq[i].level = 4; /* middle level */
                 txx9irq[i].mode = TXx9_IRCR_LOW;
-                set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
-                                         &txx9_irq_chip, handle_level_irq);
+                irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &txx9_irq_chip,
+                                         handle_level_irq);
         }
 
         /* mask all IRC interrupts */
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index f7e2c7807d7b..5a88cc4ccd5a 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1146,7 +1146,7 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe)
 
         setup_irq_smtc(cpu_ipi_irq, &irq_ipi, (0x100 << MIPS_CPU_IPI_IRQ));
 
-        set_irq_handler(cpu_ipi_irq, handle_percpu_irq);
+        irq_set_handler(cpu_ipi_irq, handle_percpu_irq);
 }
 
 /*
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index 670e3e70d198..de4c165515d7 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -128,7 +128,7 @@ void __init arch_init_irq(void)
         mips_cpu_irq_init();
 
         for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
-                set_irq_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq);
 
         setup_irq(LASAT_CASCADE_IRQ, &cascade);
 }
diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c
index 1549361696ad..f27d7ccca92a 100644
--- a/arch/mips/loongson/common/bonito-irq.c
+++ b/arch/mips/loongson/common/bonito-irq.c
@@ -44,7 +44,8 @@ void bonito_irq_init(void)
         u32 i;
 
         for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++)
-                set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &bonito_irq_type,
+                                         handle_level_irq);
 
 #ifdef CONFIG_CPU_LOONGSON2E
         setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction);
diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c
index b79b24afe3a2..9027061f0ead 100644
--- a/arch/mips/mti-malta/malta-int.c
+++ b/arch/mips/mti-malta/malta-int.c
@@ -472,7 +472,7 @@ static void __init fill_ipi_map(void)
 void __init arch_init_ipiirq(int irq, struct irqaction *action)
 {
         setup_irq(irq, action);
-        set_irq_handler(irq, handle_percpu_irq);
+        irq_set_handler(irq, handle_percpu_irq);
 }
 
 void __init arch_init_irq(void)
diff --git a/arch/mips/mti-malta/malta-time.c b/arch/mips/mti-malta/malta-time.c
index 3c6f190aa61c..1620b83cd13e 100644
--- a/arch/mips/mti-malta/malta-time.c
+++ b/arch/mips/mti-malta/malta-time.c
@@ -119,7 +119,7 @@ static void __init plat_perf_setup(void)
                         set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
                 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 #ifdef CONFIG_SMP
-                set_irq_handler(mips_cpu_perf_irq, handle_percpu_irq);
+                irq_set_handler(mips_cpu_perf_irq, handle_percpu_irq);
 #endif
         }
 }
diff --git a/arch/mips/pci/msi-octeon.c b/arch/mips/pci/msi-octeon.c
index d8080499872a..5d530f89d872 100644
--- a/arch/mips/pci/msi-octeon.c
+++ b/arch/mips/pci/msi-octeon.c
@@ -172,7 +172,7 @@ msi_irq_allocated:
         pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
                               control);
 
-        set_irq_msi(irq, desc);
+        irq_set_msi_desc(irq, desc);
         write_msi_msg(irq, &msg);
         return 0;
 }
@@ -259,11 +259,11 @@ static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock);
 static u64 msi_rcv_reg[4];
 static u64 mis_ena_reg[4];
 
-static void octeon_irq_msi_enable_pcie(unsigned int irq)
+static void octeon_irq_msi_enable_pcie(struct irq_data *data)
 {
         u64 en;
         unsigned long flags;
-        int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
+        int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
         int irq_index = msi_number >> 6;
         int irq_bit = msi_number & 0x3f;
 
@@ -275,11 +275,11 @@ static void octeon_irq_msi_enable_pcie(unsigned int irq)
         raw_spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
 }
 
-static void octeon_irq_msi_disable_pcie(unsigned int irq)
+static void octeon_irq_msi_disable_pcie(struct irq_data *data)
 {
         u64 en;
         unsigned long flags;
-        int msi_number = irq - OCTEON_IRQ_MSI_BIT0;
+        int msi_number = data->irq - OCTEON_IRQ_MSI_BIT0;
         int irq_index = msi_number >> 6;
         int irq_bit = msi_number & 0x3f;
 
@@ -293,11 +293,11 @@ static void octeon_irq_msi_disable_pcie(unsigned int irq)
 
 static struct irq_chip octeon_irq_chip_msi_pcie = {
         .name = "MSI",
-        .enable = octeon_irq_msi_enable_pcie,
-        .disable = octeon_irq_msi_disable_pcie,
+        .irq_enable = octeon_irq_msi_enable_pcie,
+        .irq_disable = octeon_irq_msi_disable_pcie,
 };
 
-static void octeon_irq_msi_enable_pci(unsigned int irq)
+static void octeon_irq_msi_enable_pci(struct irq_data *data)
 {
         /*
          * Octeon PCI doesn't have the ability to mask/unmask MSI
@@ -308,15 +308,15 @@ static void octeon_irq_msi_enable_pci(unsigned int irq)
          */
 }
 
-static void octeon_irq_msi_disable_pci(unsigned int irq)
+static void octeon_irq_msi_disable_pci(struct irq_data *data)
 {
         /* See comment in enable */
 }
 
 static struct irq_chip octeon_irq_chip_msi_pci = {
         .name = "MSI",
-        .enable = octeon_irq_msi_enable_pci,
-        .disable = octeon_irq_msi_disable_pci,
+        .irq_enable = octeon_irq_msi_enable_pci,
+        .irq_disable = octeon_irq_msi_disable_pci,
 };
 
 /*
@@ -388,7 +388,7 @@ int __init octeon_msi_initialize(void)
         }
 
         for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_LAST; irq++)
-                set_irq_chip_and_handler(irq, msi, handle_simple_irq);
+                irq_set_chip_and_handler(irq, msi, handle_simple_irq);
 
         if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
                 if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt0,
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
index 352f29d9226f..c4fa2d775d8b 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_cic.c
@@ -182,7 +182,7 @@ void __init msp_cic_irq_init(void)
 
         /* initialize all the IRQ descriptors */
         for (i = MSP_CIC_INTBASE ; i < MSP_CIC_INTBASE + 32 ; i++) {
-                set_irq_chip_and_handler(i, &msp_cic_irq_controller,
+                irq_set_chip_and_handler(i, &msp_cic_irq_controller,
                                          handle_level_irq);
 #ifdef CONFIG_MIPS_MT_SMTC
                 /* Mask of CIC interrupt */
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
index 8f51e4adc438..5bbcc47da6b9 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_irq_slp.c
@@ -77,7 +77,7 @@ void __init msp_slp_irq_init(void)
 
         /* initialize all the IRQ descriptors */
         for (i = MSP_SLP_INTBASE; i < MSP_PER_INTBASE + 32; i++)
-                set_irq_chip_and_handler(i, &msp_slp_irq_controller,
+                irq_set_chip_and_handler(i, &msp_slp_irq_controller,
                                          handle_level_irq);
 }
 
diff --git a/arch/mips/pmc-sierra/msp71xx/msp_smp.c b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
index 43a9e26e1c69..bec17901ff03 100644
--- a/arch/mips/pmc-sierra/msp71xx/msp_smp.c
+++ b/arch/mips/pmc-sierra/msp71xx/msp_smp.c
@@ -64,7 +64,7 @@ static struct irqaction irq_call = {
 void __init arch_init_ipiirq(int irq, struct irqaction *action)
 {
         setup_irq(irq, action);
-        set_irq_handler(irq, handle_percpu_irq);
+        irq_set_handler(irq, handle_percpu_irq);
 }
 
 void __init msp_vsmp_int_init(void)
diff --git a/arch/mips/pnx833x/common/interrupts.c b/arch/mips/pnx833x/common/interrupts.c
index b226bcb0a2f4..adc171c8846f 100644
--- a/arch/mips/pnx833x/common/interrupts.c
+++ b/arch/mips/pnx833x/common/interrupts.c
@@ -259,11 +259,13 @@ void __init arch_init_irq(void)
         /* Set IRQ information in irq_desc */
         for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
                 pnx833x_hard_disable_pic_irq(irq);
-                set_irq_chip_and_handler(irq, &pnx833x_pic_irq_type, handle_simple_irq);
+                irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
+                                         handle_simple_irq);
         }
 
         for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
-                set_irq_chip_and_handler(irq, &pnx833x_gpio_irq_type, handle_simple_irq);
+                irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
+                                         handle_simple_irq);
 
         /* Set PIC priority limiter register to 0 */
         PNX833X_PIC_INT_PRIORITY = 0;
diff --git a/arch/mips/pnx8550/common/int.c b/arch/mips/pnx8550/common/int.c
index dbdc35c3531d..6b93c81779c1 100644
--- a/arch/mips/pnx8550/common/int.c
+++ b/arch/mips/pnx8550/common/int.c
@@ -183,7 +183,7 @@ void __init arch_init_irq(void)
         int configPR;
 
         for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++)
-                set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
 
         /* init of GIC/IPC interrupts */
         /* should be done before cp0 since cp0 init enables the GIC int */
@@ -206,7 +206,7 @@ void __init arch_init_irq(void)
                 /* mask/priority is still 0 so we will not get any
                  * interrupts until it is unmasked */
 
-                set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
         }
 
         /* Priority level 0 */
@@ -215,20 +215,20 @@ void __init arch_init_irq(void)
         /* Set int vector table address */
         PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
 
-        set_irq_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
+        irq_set_chip_and_handler(MIPS_CPU_GIC_IRQ, &level_irq_type,
                                  handle_level_irq);
         setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
 
         /* init of Timer interrupts */
         for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
-                set_irq_chip_and_handler(i, &level_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &level_irq_type, handle_level_irq);
 
         /* Stop Timer 1-3 */
         configPR = read_c0_config7();
         configPR |= 0x00000038;
         write_c0_config7(configPR);
 
-        set_irq_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
+        irq_set_chip_and_handler(MIPS_CPU_TIMER_IRQ, &level_irq_type,
                                  handle_level_irq);
         setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
 }
diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c
index 6f1c8ef6a719..7fb97fb0931e 100644
--- a/arch/mips/powertv/asic/irq_asic.c
+++ b/arch/mips/powertv/asic/irq_asic.c
@@ -112,5 +112,5 @@ void __init asic_irq_init(void)
          * Initialize interrupt handlers.
          */
         for (i = 0; i < NR_IRQS; i++)
-                set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
+                irq_set_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
 }
diff --git a/arch/mips/rb532/irq.c b/arch/mips/rb532/irq.c
index b32a768da894..7c6db74e3fad 100644
--- a/arch/mips/rb532/irq.c
+++ b/arch/mips/rb532/irq.c
@@ -207,8 +207,8 @@ void __init arch_init_irq(void)
         pr_info("Initializing IRQ's: %d out of %d\n", RC32434_NR_IRQS, NR_IRQS);
 
         for (i = 0; i < RC32434_NR_IRQS; i++)
-                set_irq_chip_and_handler(i,  &rc32434_irq_type,
-                                        handle_level_irq);
+                irq_set_chip_and_handler(i, &rc32434_irq_type,
+                                         handle_level_irq);
 }
 
 /* Main Interrupt dispatcher */
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index e6e64750e90a..476423a01296 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -312,7 +312,7 @@ void __init arch_init_irq(void)
                 else
                         handler         = &ip22_local3_irq_type;
 
-                set_irq_chip_and_handler(i, handler, handle_level_irq);
+                irq_set_chip_and_handler(i, handler, handle_level_irq);
         }
 
         /* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index f2d09d7700dd..11488719dd97 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -337,7 +337,7 @@ static struct irq_chip bridge_irq_type = {
 
 void __devinit register_bridge_irq(unsigned int irq)
 {
-        set_irq_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(irq, &bridge_irq_type, handle_level_irq);
 }
 
 int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index c01f558a2a09..a152538d3c97 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -153,7 +153,7 @@ static void __init hub_rt_clock_event_global_init(void)
                         panic("Allocation of irq number for timer failed");
         } while (xchg(&rt_timer_irq, irq));
 
-        set_irq_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
+        irq_set_chip_and_handler(irq, &rt_irq_type, handle_percpu_irq);
         setup_irq(irq, &hub_rt_irqaction);
 }
 
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index e0a3ce4a8d48..c65ea76d56c7 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -451,43 +451,51 @@ void __init arch_init_irq(void)
         for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
                 switch (irq) {
                 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
-                        set_irq_chip_and_handler_name(irq,&ip32_mace_interrupt,
-                                handle_level_irq, "level");
+                        irq_set_chip_and_handler_name(irq,
+                                                      &ip32_mace_interrupt,
+                                                      handle_level_irq,
+                                                      "level");
                         break;
 
                 case MACEPCI_SCSI0_IRQ ...  MACEPCI_SHARED2_IRQ:
-                        set_irq_chip_and_handler_name(irq,
-                                &ip32_macepci_interrupt, handle_level_irq,
-                                "level");
+                        irq_set_chip_and_handler_name(irq,
+                                                      &ip32_macepci_interrupt,
+                                                      handle_level_irq,
+                                                      "level");
                         break;
 
                 case CRIME_CPUERR_IRQ:
                 case CRIME_MEMERR_IRQ:
-                        set_irq_chip_and_handler_name(irq,
-                                &crime_level_interrupt, handle_level_irq,
-                                "level");
+                        irq_set_chip_and_handler_name(irq,
+                                                      &crime_level_interrupt,
+                                                      handle_level_irq,
+                                                      "level");
                         break;
 
                 case CRIME_GBE0_IRQ ... CRIME_GBE3_IRQ:
                 case CRIME_RE_EMPTY_E_IRQ ... CRIME_RE_IDLE_E_IRQ:
                 case CRIME_SOFT0_IRQ ... CRIME_SOFT2_IRQ:
                 case CRIME_VICE_IRQ:
-                        set_irq_chip_and_handler_name(irq,
-                                &crime_edge_interrupt, handle_edge_irq, "edge");
+                        irq_set_chip_and_handler_name(irq,
+                                                      &crime_edge_interrupt,
+                                                      handle_edge_irq,
+                                                      "edge");
                         break;
 
                 case MACEISA_PARALLEL_IRQ:
                 case MACEISA_SERIAL1_TDMAPR_IRQ:
                 case MACEISA_SERIAL2_TDMAPR_IRQ:
-                        set_irq_chip_and_handler_name(irq,
-                                &ip32_maceisa_edge_interrupt, handle_edge_irq,
-                                "edge");
+                        irq_set_chip_and_handler_name(irq,
+                                                      &ip32_maceisa_edge_interrupt,
+                                                      handle_edge_irq,
+                                                      "edge");
                         break;
 
                 default:
-                        set_irq_chip_and_handler_name(irq,
-                                &ip32_maceisa_level_interrupt, handle_level_irq,
-                                "level");
+                        irq_set_chip_and_handler_name(irq,
+                                                      &ip32_maceisa_level_interrupt,
+                                                      handle_level_irq,
+                                                      "level");
                         break;
                 }
         }
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 89e8188a4665..09740d60e187 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -216,7 +216,8 @@ void __init init_bcm1480_irqs(void)
         int i;
 
         for (i = 0; i < BCM1480_NR_IRQS; i++) {
-                set_irq_chip_and_handler(i, &bcm1480_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &bcm1480_irq_type,
+                                         handle_level_irq);
                 bcm1480_irq_owner[i] = 0;
         }
 }
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index fd269ea8d8a8..be4460a5f6a8 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -190,7 +190,8 @@ void __init init_sb1250_irqs(void)
         int i;
 
         for (i = 0; i < SB1250_NR_IRQS; i++) {
-                set_irq_chip_and_handler(i, &sb1250_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &sb1250_irq_type,
+                                         handle_level_irq);
                 sb1250_irq_owner[i] = 0;
         }
 }
diff --git a/arch/mips/sni/a20r.c b/arch/mips/sni/a20r.c
index 72b94155778d..c48194c3073b 100644
--- a/arch/mips/sni/a20r.c
+++ b/arch/mips/sni/a20r.c
@@ -209,7 +209,7 @@ void __init sni_a20r_irq_init(void)
         int i;
 
         for (i = SNI_A20R_IRQ_BASE + 2 ; i < SNI_A20R_IRQ_BASE + 8; i++)
-                set_irq_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &a20r_irq_type, handle_level_irq);
         sni_hwint = a20r_hwint;
         change_c0_status(ST0_IM, IE_IRQ0);
         setup_irq(SNI_A20R_IRQ_BASE + 3, &sni_isa_irq);
diff --git a/arch/mips/sni/pcimt.c b/arch/mips/sni/pcimt.c
index cfcc68abc5b2..ed3b3d317358 100644
--- a/arch/mips/sni/pcimt.c
+++ b/arch/mips/sni/pcimt.c
@@ -296,7 +296,7 @@ void __init sni_pcimt_irq_init(void)
         mips_cpu_irq_init();
         /* Actually we've got more interrupts to handle ...  */
         for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
-                set_irq_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &pcimt_irq_type, handle_level_irq);
         sni_hwint = sni_pcimt_hwint;
         change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
 }
diff --git a/arch/mips/sni/pcit.c b/arch/mips/sni/pcit.c
index 0846e99a6efe..b5246373d16b 100644
--- a/arch/mips/sni/pcit.c
+++ b/arch/mips/sni/pcit.c
@@ -238,7 +238,7 @@ void __init sni_pcit_irq_init(void)
 
         mips_cpu_irq_init();
         for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
-                set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
         *(volatile u32 *)SNI_PCIT_INT_REG = 0;
         sni_hwint = sni_pcit_hwint;
         change_c0_status(ST0_IM, IE_IRQ1);
@@ -251,7 +251,7 @@ void __init sni_pcit_cplus_irq_init(void)
 
         mips_cpu_irq_init();
         for (i = SNI_PCIT_INT_START; i <= SNI_PCIT_INT_END; i++)
-                set_irq_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &pcit_irq_type, handle_level_irq);
         *(volatile u32 *)SNI_PCIT_INT_REG = 0x40000000;
         sni_hwint = sni_pcit_hwint_cplus;
         change_c0_status(ST0_IM, IE_IRQ0);
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index f05d8e593300..a7e5a6d917b1 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -413,7 +413,7 @@ void __init sni_rm200_i8259_irqs(void)
         sni_rm200_init_8259A();
 
         for (i = RM200_I8259A_IRQ_BASE; i < RM200_I8259A_IRQ_BASE + 16; i++)
-                set_irq_chip_and_handler(i, &sni_rm200_i8259A_chip,
+                irq_set_chip_and_handler(i, &sni_rm200_i8259A_chip,
                                          handle_level_irq);
 
         setup_irq(RM200_I8259A_IRQ_BASE + PIC_CASCADE_IR, &sni_rm200_irq2);
@@ -477,7 +477,7 @@ void __init sni_rm200_irq_init(void)
         mips_cpu_irq_init();
         /* Actually we've got more interrupts to handle ...  */
         for (i = SNI_RM200_INT_START; i <= SNI_RM200_INT_END; i++)
-                set_irq_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &rm200_irq_type, handle_level_irq);
         sni_hwint = sni_rm200_hwint;
         change_c0_status(ST0_IM, IE_IRQ0);
         setup_irq(SNI_RM200_INT_START + 0, &sni_rm200_i8259A_irq);
diff --git a/arch/mips/txx9/generic/irq_tx4927.c b/arch/mips/txx9/generic/irq_tx4927.c
index e1828e8bcaef..7e3ac5782da4 100644
--- a/arch/mips/txx9/generic/irq_tx4927.c
+++ b/arch/mips/txx9/generic/irq_tx4927.c
@@ -35,7 +35,7 @@ void __init tx4927_irq_init(void)
 
         mips_cpu_irq_init();
         txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
-        set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
                                 handle_simple_irq);
         /* raise priority for errors, timers, SIO */
         txx9_irq_set_pri(TX4927_IR_ECCERR, 7);
diff --git a/arch/mips/txx9/generic/irq_tx4938.c b/arch/mips/txx9/generic/irq_tx4938.c
index a6e6e805097a..aace85653329 100644
--- a/arch/mips/txx9/generic/irq_tx4938.c
+++ b/arch/mips/txx9/generic/irq_tx4938.c
@@ -23,7 +23,7 @@ void __init tx4938_irq_init(void)
 
         mips_cpu_irq_init();
         txx9_irq_init(TX4938_IRC_REG & 0xfffffffffULL);
-        set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4938_IRC_INT,
                                 handle_simple_irq);
         /* raise priority for errors, timers, SIO */
         txx9_irq_set_pri(TX4938_IR_ECCERR, 7);
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
index 93b6edbedd64..6b067dbd2ae1 100644
--- a/arch/mips/txx9/generic/irq_tx4939.c
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -176,8 +176,8 @@ void __init tx4939_irq_init(void)
         for (i = 1; i < TX4939_NUM_IR; i++) {
                 tx4939irq[i].level = 4; /* middle level */
                 tx4939irq[i].mode = TXx9_IRCR_LOW;
-                set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
-                                         &tx4939_irq_chip, handle_level_irq);
+                irq_set_chip_and_handler(TXX9_IRQ_BASE + i, &tx4939_irq_chip,
+                                         handle_level_irq);
         }
 
         /* mask all IRC interrupts */
@@ -193,7 +193,7 @@ void __init tx4939_irq_init(void)
         __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
         __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
 
-        set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
+        irq_set_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
                                 handle_simple_irq);
 
         /* raise priority for errors, timers, sio */
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 92a5c1b400f0..c22c859a2c49 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -120,8 +120,9 @@ void __init jmr3927_irq_setup(void)
 
         tx3927_irq_init();
         for (i = JMR3927_IRQ_IOC; i < JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC; i++)
-                set_irq_chip_and_handler(i, &jmr3927_irq_ioc, handle_level_irq);
+                irq_set_chip_and_handler(i, &jmr3927_irq_ioc,
+                                         handle_level_irq);
 
         /* setup IOC interrupt 1 (PCI, MODEM) */
-        set_irq_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
+        irq_set_chained_handler(JMR3927_IRQ_IOCINT, handle_simple_irq);
 }
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 7c0a048b307c..6c22c496090b 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -164,9 +164,9 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
 
         for (i = RBTX4927_IRQ_IOC;
              i < RBTX4927_IRQ_IOC + RBTX4927_NR_IRQ_IOC; i++)
-                set_irq_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
+                irq_set_chip_and_handler(i, &toshiba_rbtx4927_irq_ioc_type,
                                          handle_level_irq);
-        set_irq_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
+        irq_set_chained_handler(RBTX4927_IRQ_IOCINT, handle_simple_irq);
 }
 
 static int rbtx4927_irq_dispatch(int pending)
@@ -194,5 +194,5 @@ void __init rbtx4927_irq_setup(void)
         tx4927_irq_init();
         toshiba_rbtx4927_irq_ioc_init();
         /* Onboard 10M Ether: High Active */
-        set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
 }
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index 2ec4fe1b1670..58cd7a9272cc 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -132,10 +132,10 @@ static void __init toshiba_rbtx4938_irq_ioc_init(void)
 
         for (i = RBTX4938_IRQ_IOC;
              i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
-                set_irq_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
+                irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
                                          handle_level_irq);
 
-        set_irq_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
+        irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
 }
 
 void __init rbtx4938_irq_setup(void)
@@ -153,5 +153,5 @@ void __init rbtx4938_irq_setup(void)
         tx4938_irq_init();
         toshiba_rbtx4938_irq_ioc_init();
         /* Onboard 10M Ether: High Active */
-        set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
+        irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
 }
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
index 70074632fb99..69a80616f0c9 100644
--- a/arch/mips/txx9/rbtx4939/irq.c
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -88,8 +88,8 @@ void __init rbtx4939_irq_setup(void)
         tx4939_irq_init();
         for (i = RBTX4939_IRQ_IOC;
              i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
-                set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
+                irq_set_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
                                          handle_level_irq);
 
-        set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
+        irq_set_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
 }
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index f53156bb9aa8..a39ef3207d71 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -710,11 +710,11 @@ static int __init vr41xx_icu_init(void)
         icu2_write(MGIUINTHREG, 0xffff);
 
         for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
-                set_irq_chip_and_handler(i, &sysint1_irq_type,
+                irq_set_chip_and_handler(i, &sysint1_irq_type,
                                          handle_level_irq);
 
         for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
-                set_irq_chip_and_handler(i, &sysint2_irq_type,
+                irq_set_chip_and_handler(i, &sysint2_irq_type,
                                          handle_level_irq);
 
         cascade_irq(INT0_IRQ, icu_get_irq);
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 9ff7f397c0e1..70a3b85f3757 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -87,7 +87,7 @@ static void irq_dispatch(unsigned int irq)
                         atomic_inc(&irq_err_count);
                 else
                         irq_dispatch(irq);
-                if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
+                if (!irqd_irq_disabled(idata) && chip->irq_unmask)
                         chip->irq_unmask(idata);
         } else
                 do_IRQ(irq);
diff --git a/arch/mn10300/Kconfig b/arch/mn10300/Kconfig
index d8ab97a73db2..a523c94fa698 100644
--- a/arch/mn10300/Kconfig
+++ b/arch/mn10300/Kconfig
@@ -3,6 +3,7 @@ config MN10300
         select HAVE_OPROFILE
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_HARDIRQS_NO_DEPRECATED
+        select GENERIC_IRQ_SHOW
         select HAVE_ARCH_TRACEHOOK
         select HAVE_ARCH_KGDB
 
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c
index 5f7fc3eb45e6..86af0d7d0771 100644
--- a/arch/mn10300/kernel/irq.c
+++ b/arch/mn10300/kernel/irq.c
@@ -263,7 +263,7 @@ void set_intr_level(int irq, u16 level)
  */
 void mn10300_set_lateack_irq_type(int irq)
 {
-        set_irq_chip_and_handler(irq, &mn10300_cpu_pic_level,
+        irq_set_chip_and_handler(irq, &mn10300_cpu_pic_level,
                                  handle_level_irq);
 }
 
@@ -275,12 +275,12 @@ void __init init_IRQ(void)
         int irq;
 
         for (irq = 0; irq < NR_IRQS; irq++)
-                if (get_irq_chip(irq) == &no_irq_chip)
+                if (irq_get_chip(irq) == &no_irq_chip)
                         /* due to the PIC latching interrupt requests, even
                          * when the IRQ is disabled, IRQ_PENDING is superfluous
                          * and we can use handle_level_irq() for edge-triggered
                          * interrupts */
-                        set_irq_chip_and_handler(irq, &mn10300_cpu_pic_edge,
+                        irq_set_chip_and_handler(irq, &mn10300_cpu_pic_edge,
                                                  handle_level_irq);
 
         unit_init_IRQ();
@@ -335,91 +335,42 @@ asmlinkage void do_IRQ(void)
 /*
  * Display interrupt management information through /proc/interrupts
  */
-int show_interrupts(struct seq_file *p, void *v)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
-        int i = *(loff_t *) v, j, cpu;
-        struct irqaction *action;
-        unsigned long flags;
-
-        switch (i) {
-                /* display column title bar naming CPUs */
-        case 0:
-                seq_printf(p, "           ");
-                for (j = 0; j < NR_CPUS; j++)
-                        if (cpu_online(j))
-                                seq_printf(p, "CPU%d       ", j);
-                seq_putc(p, '\n');
-                break;
-
-                /* display information rows, one per active CPU */
-        case 1 ... NR_IRQS - 1:
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-
-                action = irq_desc[i].action;
-                if (action) {
-                        seq_printf(p, "%3d: ", i);
-                        for_each_present_cpu(cpu)
-                                seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-
-                        if (i < NR_CPU_IRQS)
-                                seq_printf(p, " %14s.%u",
-                                           irq_desc[i].irq_data.chip->name,
-                                           (GxICR(i) & GxICR_LEVEL) >>
-                                           GxICR_LEVEL_SHIFT);
-                        else
-                                seq_printf(p, " %14s",
-                                           irq_desc[i].irq_data.chip->name);
-
-                        seq_printf(p, "  %s", action->name);
-
-                        for (action = action->next;
-                             action;
-                             action = action->next)
-                                seq_printf(p, ", %s", action->name);
-
-                        seq_putc(p, '\n');
-                }
-
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-                break;
-
-                /* polish off with NMI and error counters */
-        case NR_IRQS:
 #ifdef CONFIG_MN10300_WD_TIMER
-                seq_printf(p, "NMI: ");
-                for (j = 0; j < NR_CPUS; j++)
-                        if (cpu_online(j))
-                                seq_printf(p, "%10u ", nmi_count(j));
-                seq_putc(p, '\n');
-#endif
+        int j;
 
-                seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
-                break;
-        }
+        seq_printf(p, "%*s: ", prec, "NMI");
+        for (j = 0; j < NR_CPUS; j++)
+                if (cpu_online(j))
+                        seq_printf(p, "%10u ", nmi_count(j));
+        seq_putc(p, '\n');
+#endif
 
+        seq_printf(p, "%*s: ", prec, "ERR");
+        seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
         return 0;
 }
 
 #ifdef CONFIG_HOTPLUG_CPU
 void migrate_irqs(void)
 {
-        irq_desc_t *desc;
         int irq;
         unsigned int self, new;
         unsigned long flags;
 
         self = smp_processor_id();
         for (irq = 0; irq < NR_IRQS; irq++) {
-                desc = irq_desc + irq;
+                struct irq_data *data = irq_get_irq_data(irq);
 
-                if (desc->status == IRQ_PER_CPU)
+                if (irqd_is_per_cpu(data))
                         continue;
 
-                if (cpu_isset(self, irq_desc[irq].affinity) &&
+                if (cpu_isset(self, data->affinity) &&
                     !cpus_intersects(irq_affinity[irq], cpu_online_map)) {
                         int cpu_id;
                         cpu_id = first_cpu(cpu_online_map);
-                        cpu_set(cpu_id, irq_desc[irq].affinity);
+                        cpu_set(cpu_id, data->affinity);
                 }
                 /* We need to operate irq_affinity_online atomically. */
                 arch_local_cli_save(flags);
@@ -430,7 +381,7 @@ void migrate_irqs(void)
                         GxICR(irq) = x & GxICR_LEVEL;
                         tmp = GxICR(irq);
 
-                        new = any_online_cpu(irq_desc[irq].affinity);
+                        new = any_online_cpu(data->affinity);
                         irq_affinity_online[irq] = new;
 
                         CROSS_GxICR(irq, new) =
diff --git a/arch/mn10300/kernel/mn10300-serial.c b/arch/mn10300/kernel/mn10300-serial.c
index efca426a2ed4..94901c56baf1 100644
--- a/arch/mn10300/kernel/mn10300-serial.c
+++ b/arch/mn10300/kernel/mn10300-serial.c
@@ -933,7 +933,7 @@ static int mn10300_serial_startup(struct uart_port *_port)
                 NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
         set_intr_level(port->tx_irq,
                 NUM2GxICR_LEVEL(CONFIG_MN10300_SERIAL_IRQ_LEVEL));
-        set_irq_chip(port->tm_irq, &mn10300_serial_pic);
+        irq_set_chip(port->tm_irq, &mn10300_serial_pic);
 
         if (request_irq(port->rx_irq, mn10300_serial_interrupt,
                         IRQF_DISABLED, port->rx_name, port) < 0)
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
index 51c02f97dcea..226c826a2194 100644
--- a/arch/mn10300/kernel/smp.c
+++ b/arch/mn10300/kernel/smp.c
@@ -156,15 +156,15 @@ static void init_ipi(void)
         u16 tmp16;
 
         /* set up the reschedule IPI */
-        set_irq_chip_and_handler(RESCHEDULE_IPI,
-                                 &mn10300_ipi_type, handle_percpu_irq);
+        irq_set_chip_and_handler(RESCHEDULE_IPI, &mn10300_ipi_type,
+                                 handle_percpu_irq);
         setup_irq(RESCHEDULE_IPI, &reschedule_ipi);
         set_intr_level(RESCHEDULE_IPI, RESCHEDULE_GxICR_LV);
         mn10300_ipi_enable(RESCHEDULE_IPI);
 
         /* set up the call function IPI */
-        set_irq_chip_and_handler(CALL_FUNC_SINGLE_IPI,
-                                 &mn10300_ipi_type, handle_percpu_irq);
+        irq_set_chip_and_handler(CALL_FUNC_SINGLE_IPI, &mn10300_ipi_type,
+                                 handle_percpu_irq);
         setup_irq(CALL_FUNC_SINGLE_IPI, &call_function_ipi);
         set_intr_level(CALL_FUNC_SINGLE_IPI, CALL_FUNCTION_GxICR_LV);
         mn10300_ipi_enable(CALL_FUNC_SINGLE_IPI);
@@ -172,8 +172,8 @@ static void init_ipi(void)
         /* set up the local timer IPI */
 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || \
     defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
-        set_irq_chip_and_handler(LOCAL_TIMER_IPI,
-                                 &mn10300_ipi_type, handle_percpu_irq);
+        irq_set_chip_and_handler(LOCAL_TIMER_IPI, &mn10300_ipi_type,
+                                 handle_percpu_irq);
         setup_irq(LOCAL_TIMER_IPI, &local_timer_ipi);
         set_intr_level(LOCAL_TIMER_IPI, LOCAL_TIMER_GxICR_LV);
         mn10300_ipi_enable(LOCAL_TIMER_IPI);
diff --git a/arch/mn10300/unit-asb2364/irq-fpga.c b/arch/mn10300/unit-asb2364/irq-fpga.c
index ee84e62b16ed..e16c216f31dc 100644
--- a/arch/mn10300/unit-asb2364/irq-fpga.c
+++ b/arch/mn10300/unit-asb2364/irq-fpga.c
@@ -100,7 +100,8 @@ void __init irq_fpga_init(void)
         SyncExBus();
 
         for (irq = NR_CPU_IRQS; irq < NR_IRQS; irq++)
-                set_irq_chip_and_handler(irq, &asb2364_fpga_pic, handle_level_irq);
+                irq_set_chip_and_handler(irq, &asb2364_fpga_pic,
+                                         handle_level_irq);
 
         /* the FPGA drives the XIRQ1 input on the CPU PIC */
         setup_irq(XIRQ1, &fpga_irq[0]);
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index cb450e1e79b3..c0b1affc06a8 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -113,13 +113,8 @@ int cpu_check_affinity(struct irq_data *d, const struct cpumask *dest)
         int cpu_dest;
 
         /* timer and ipi have to always be received on all CPUs */
-        if (CHECK_IRQ_PER_CPU(irq_to_desc(d->irq)->status)) {
-                /* Bad linux design decision.  The mask has already
-                 * been set; we must reset it. Will fix - tglx
-                 */
-                cpumask_setall(d->affinity);
+        if (irqd_is_per_cpu(d))
                 return -EINVAL;
-        }
 
         /* whatever mask they set, we just allow one CPU */
         cpu_dest = first_cpu(*dest);
@@ -174,10 +169,11 @@ int show_interrupts(struct seq_file *p, void *v)
         }
 
         if (i < NR_IRQS) {
+                struct irq_desc *desc = irq_to_desc(i);
                 struct irqaction *action;
 
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
+                raw_spin_lock_irqsave(&desc->lock, flags);
+                action = desc->action;
                 if (!action)
                         goto skip;
                 seq_printf(p, "%3d: ", i);
@@ -188,7 +184,7 @@ int show_interrupts(struct seq_file *p, void *v)
                 seq_printf(p, "%10u ", kstat_irqs(i));
 #endif
 
-                seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
+                seq_printf(p, " %14s", irq_desc_get_chip(desc)->name);
 #ifndef PARISC_IRQ_CR16_COUNTS
                 seq_printf(p, "  %s", action->name);
 
@@ -220,7 +216,7 @@ int show_interrupts(struct seq_file *p, void *v)
 
                 seq_putc(p, '\n');
  skip:
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 
         return 0;
@@ -238,15 +234,15 @@ int show_interrupts(struct seq_file *p, void *v)
 
 int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
 {
-        if (irq_desc[irq].action)
+        if (irq_has_action(irq))
                 return -EBUSY;
-        if (get_irq_chip(irq) != &cpu_interrupt_type)
+        if (irq_get_chip(irq) != &cpu_interrupt_type)
                 return -EBUSY;
 
         /* for iosapic interrupts */
         if (type) {
-                set_irq_chip_and_handler(irq, type, handle_percpu_irq);
-                set_irq_chip_data(irq, data);
+                irq_set_chip_and_handler(irq, type, handle_percpu_irq);
+                irq_set_chip_data(irq, data);
                 __cpu_unmask_irq(irq);
         }
         return 0;
@@ -357,7 +353,7 @@ void do_cpu_irq_mask(struct pt_regs *regs)
 #ifdef CONFIG_SMP
         desc = irq_to_desc(irq);
         cpumask_copy(&dest, desc->irq_data.affinity);
-        if (CHECK_IRQ_PER_CPU(desc->status) &&
+        if (irqd_is_per_cpu(&desc->irq_data) &&
             !cpu_isset(smp_processor_id(), dest)) {
                 int cpu = first_cpu(dest);
 
@@ -398,14 +394,14 @@ static void claim_cpu_irqs(void)
 {
         int i;
         for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
-                set_irq_chip_and_handler(i, &cpu_interrupt_type,
+                irq_set_chip_and_handler(i, &cpu_interrupt_type,
                                          handle_percpu_irq);
         }
 
-        set_irq_handler(TIMER_IRQ, handle_percpu_irq);
+        irq_set_handler(TIMER_IRQ, handle_percpu_irq);
         setup_irq(TIMER_IRQ, &timer_action);
 #ifdef CONFIG_SMP
-        set_irq_handler(IPI_IRQ, handle_percpu_irq);
+        irq_set_handler(IPI_IRQ, handle_percpu_irq);
         setup_irq(IPI_IRQ, &ipi_action);
 #endif
 }
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 3584e4d4a4ad..d0e8a1dbf822 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -139,6 +139,8 @@ config PPC
         select HAVE_SPARSE_IRQ
         select IRQ_PER_CPU
         select GENERIC_HARDIRQS_NO_DEPRECATED
+        select GENERIC_IRQ_SHOW
+        select GENERIC_IRQ_SHOW_LEVEL
 
 config EARLY_PRINTK
         bool
diff --git a/arch/powerpc/kernel/irq.c b/arch/powerpc/kernel/irq.c
index 0a5570338b96..63625e0650b5 100644
--- a/arch/powerpc/kernel/irq.c
+++ b/arch/powerpc/kernel/irq.c
@@ -195,7 +195,7 @@ notrace void arch_local_irq_restore(unsigned long en)
 EXPORT_SYMBOL(arch_local_irq_restore);
 #endif /* CONFIG_PPC64 */
 
-static int show_other_interrupts(struct seq_file *p, int prec)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
         int j;
 
@@ -231,65 +231,6 @@ static int show_other_interrupts(struct seq_file *p, int prec)
         return 0;
 }
 
-int show_interrupts(struct seq_file *p, void *v)
-{
-        unsigned long flags, any_count = 0;
-        int i = *(loff_t *) v, j, prec;
-        struct irqaction *action;
-        struct irq_desc *desc;
-        struct irq_chip *chip;
-
-        if (i > nr_irqs)
-                return 0;
-
-        for (prec = 3, j = 1000; prec < 10 && j <= nr_irqs; ++prec)
-                j *= 10;
-
-        if (i == nr_irqs)
-                return show_other_interrupts(p, prec);
-
-        /* print header */
-        if (i == 0) {
-                seq_printf(p, "%*s", prec + 8, "");
-                for_each_online_cpu(j)
-                        seq_printf(p, "CPU%-8d", j);
-                seq_putc(p, '\n');
-        }
-
-        desc = irq_to_desc(i);
-        if (!desc)
-                return 0;
-
-        raw_spin_lock_irqsave(&desc->lock, flags);
-        for_each_online_cpu(j)
-                any_count |= kstat_irqs_cpu(i, j);
-        action = desc->action;
-        if (!action && !any_count)
-                goto out;
-
-        seq_printf(p, "%*d: ", prec, i);
-        for_each_online_cpu(j)
-                seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-
-        chip = get_irq_desc_chip(desc);
-        if (chip)
-                seq_printf(p, "  %-16s", chip->name);
-        else
-                seq_printf(p, "  %-16s", "None");
-        seq_printf(p, " %-8s", (desc->status & IRQ_LEVEL) ? "Level" : "Edge");
-
-        if (action) {
-                seq_printf(p, "     %s", action->name);
-                while ((action = action->next) != NULL)
-                        seq_printf(p, ", %s", action->name);
-        }
-
-        seq_putc(p, '\n');
-out:
-        raw_spin_unlock_irqrestore(&desc->lock, flags);
-        return 0;
-}
-
 /*
  * /proc/stat helpers
  */
@@ -315,24 +256,26 @@ void fixup_irqs(const struct cpumask *map)
         alloc_cpumask_var(&mask, GFP_KERNEL);
 
         for_each_irq(irq) {
+                struct irq_data *data;
                 struct irq_chip *chip;
 
                 desc = irq_to_desc(irq);
                 if (!desc)
                         continue;
 
-                if (desc->status & IRQ_PER_CPU)
+                data = irq_desc_get_irq_data(desc);
+                if (irqd_is_per_cpu(data))
                         continue;
 
-                chip = get_irq_desc_chip(desc);
+                chip = irq_data_get_irq_chip(data);
 
-                cpumask_and(mask, desc->irq_data.affinity, map);
+                cpumask_and(mask, data->affinity, map);
                 if (cpumask_any(mask) >= nr_cpu_ids) {
                         printk("Breaking affinity for irq %i\n", irq);
                         cpumask_copy(mask, map);
                 }
                 if (chip->irq_set_affinity)
-                        chip->irq_set_affinity(&desc->irq_data, mask, true);
+                        chip->irq_set_affinity(data, mask, true);
                 else if (desc->action && !(warned++))
                         printk("Cannot set affinity for irq %i\n", irq);
         }
@@ -618,7 +561,7 @@ struct irq_host *irq_alloc_host(struct device_node *of_node,
                         smp_wmb();
 
                         /* Clear norequest flags */
-                        irq_to_desc(i)->status &= ~IRQ_NOREQUEST;
+                        irq_clear_status_flags(i, IRQ_NOREQUEST);
 
                         /* Legacy flags are left to default at this point,
                          * one can then use irq_create_mapping() to
@@ -827,8 +770,8 @@ unsigned int irq_create_of_mapping(struct device_node *controller,
 
         /* Set type if specified and different than the current one */
         if (type != IRQ_TYPE_NONE &&
-            type != (irq_to_desc(virq)->status & IRQF_TRIGGER_MASK))
-                set_irq_type(virq, type);
+            type != (irqd_get_trigger_type(irq_get_irq_data(virq))))
+                irq_set_irq_type(virq, type);
         return virq;
 }
 EXPORT_SYMBOL_GPL(irq_create_of_mapping);
@@ -851,7 +794,7 @@ void irq_dispose_mapping(unsigned int virq)
                 return;
 
         /* remove chip and handler */
-        set_irq_chip_and_handler(virq, NULL, NULL);
+        irq_set_chip_and_handler(virq, NULL, NULL);
 
         /* Make sure it's completed */
         synchronize_irq(virq);
@@ -1156,7 +1099,7 @@ static int virq_debug_show(struct seq_file *m, void *private)
                         seq_printf(m, "%5d  ", i);
                         seq_printf(m, "0x%05lx  ", virq_to_hw(i));
 
-                        chip = get_irq_desc_chip(desc);
+                        chip = irq_desc_get_chip(desc);
                         if (chip && chip->name)
                                 p = chip->name;
                         else
diff --git a/arch/powerpc/kernel/machine_kexec.c b/arch/powerpc/kernel/machine_kexec.c
index bd1e1ff17b2d..7ee50f0547cb 100644
--- a/arch/powerpc/kernel/machine_kexec.c
+++ b/arch/powerpc/kernel/machine_kexec.c
@@ -31,17 +31,17 @@ void machine_kexec_mask_interrupts(void) {
                 if (!desc)
                         continue;
 
-                chip = get_irq_desc_chip(desc);
+                chip = irq_desc_get_chip(desc);
                 if (!chip)
                         continue;
 
-                if (chip->irq_eoi && desc->status & IRQ_INPROGRESS)
+                if (chip->irq_eoi && irqd_irq_inprogress(&desc->irq_data))
                         chip->irq_eoi(&desc->irq_data);
 
                 if (chip->irq_mask)
                         chip->irq_mask(&desc->irq_data);
 
-                if (chip->irq_disable && !(desc->status & IRQ_DISABLED))
+                if (chip->irq_disable && !irqd_irq_disabled(&desc->irq_data))
                         chip->irq_disable(&desc->irq_data);
         }
 }
diff --git a/arch/powerpc/kernel/pci-common.c b/arch/powerpc/kernel/pci-common.c
index 3cd85faa8ac6..893af2a9cd03 100644
--- a/arch/powerpc/kernel/pci-common.c
+++ b/arch/powerpc/kernel/pci-common.c
@@ -261,7 +261,7 @@ int pci_read_irq_line(struct pci_dev *pci_dev)
 
                 virq = irq_create_mapping(NULL, line);
                 if (virq != NO_IRQ)
-                        set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
         } else {
                 pr_debug(" Got one, spec %d cells (0x%08x 0x%08x...) on %s\n",
                          oirq.size, oirq.specifier[0], oirq.specifier[1],
diff --git a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
index fde0ea50c97d..cfc4b2009982 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads_cpld.c
@@ -132,8 +132,8 @@ static int
 cpld_pic_host_map(struct irq_host *h, unsigned int virq,
                              irq_hw_number_t hw)
 {
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &cpld_pic, handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &cpld_pic, handle_level_irq);
         return 0;
 }
 
@@ -198,7 +198,7 @@ mpc5121_ads_cpld_pic_init(void)
                 goto end;
         }
 
-        set_irq_chained_handler(cascade_irq, cpld_pic_cascade);
+        irq_set_chained_handler(cascade_irq, cpld_pic_cascade);
 end:
         of_node_put(np);
 }
diff --git a/arch/powerpc/platforms/52xx/media5200.c b/arch/powerpc/platforms/52xx/media5200.c
index 2bd1e6cf1f58..57a6a349e932 100644
--- a/arch/powerpc/platforms/52xx/media5200.c
+++ b/arch/powerpc/platforms/52xx/media5200.c
@@ -82,7 +82,7 @@ static struct irq_chip media5200_irq_chip = {
 
 void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         int sub_virq, val;
         u32 status, enable;
 
@@ -107,7 +107,7 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
         /* Processing done; can reenable the cascade now */
         raw_spin_lock(&desc->lock);
         chip->irq_ack(&desc->irq_data);
-        if (!(desc->status & IRQ_DISABLED))
+        if (!irqd_irq_disabled(&desc->irq_data))
                 chip->irq_unmask(&desc->irq_data);
         raw_spin_unlock(&desc->lock);
 }
@@ -115,15 +115,10 @@ void media5200_irq_cascade(unsigned int virq, struct irq_desc *desc)
 static int media5200_irq_map(struct irq_host *h, unsigned int virq,
                              irq_hw_number_t hw)
 {
-        struct irq_desc *desc = irq_to_desc(virq);
-
         pr_debug("%s: h=%p, virq=%i, hwirq=%i\n", __func__, h, virq, (int)hw);
-        set_irq_chip_data(virq, &media5200_irq);
-        set_irq_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
-        set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= IRQ_TYPE_LEVEL_LOW | IRQ_LEVEL;
-
+        irq_set_chip_data(virq, &media5200_irq);
+        irq_set_chip_and_handler(virq, &media5200_irq_chip, handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
         return 0;
 }
 
@@ -187,8 +182,8 @@ static void __init media5200_init_irq(void)
 
         media5200_irq.irqhost->host_data = &media5200_irq;
 
-        set_irq_data(cascade_virq, &media5200_irq);
-        set_irq_chained_handler(cascade_virq, media5200_irq_cascade);
+        irq_set_handler_data(cascade_virq, &media5200_irq);
+        irq_set_chained_handler(cascade_virq, media5200_irq_cascade);
 
         return;
 
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
index 6da44f0f2934..6c39b9cc2fa3 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_gpt.c
@@ -192,7 +192,7 @@ static struct irq_chip mpc52xx_gpt_irq_chip = {
 
 void mpc52xx_gpt_irq_cascade(unsigned int virq, struct irq_desc *desc)
 {
-        struct mpc52xx_gpt_priv *gpt = get_irq_data(virq);
+        struct mpc52xx_gpt_priv *gpt = irq_get_handler_data(virq);
         int sub_virq;
         u32 status;
 
@@ -209,8 +209,8 @@ static int mpc52xx_gpt_irq_map(struct irq_host *h, unsigned int virq,
         struct mpc52xx_gpt_priv *gpt = h->host_data;
 
         dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
-        set_irq_chip_data(virq, gpt);
-        set_irq_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
+        irq_set_chip_data(virq, gpt);
+        irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
 
         return 0;
 }
@@ -259,8 +259,8 @@ mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
         }
 
         gpt->irqhost->host_data = gpt;
-        set_irq_data(cascade_virq, gpt);
-        set_irq_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
+        irq_set_handler_data(cascade_virq, gpt);
+        irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
 
         /* If the GPT is currently disabled, then change it to be in Input
          * Capture mode.  If the mode is non-zero, then the pin could be
diff --git a/arch/powerpc/platforms/52xx/mpc52xx_pic.c b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
index 9f3ed582d082..3ddea96273ca 100644
--- a/arch/powerpc/platforms/52xx/mpc52xx_pic.c
+++ b/arch/powerpc/platforms/52xx/mpc52xx_pic.c
@@ -214,7 +214,7 @@ static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
         ctrl_reg |= (type << (22 - (l2irq * 2)));
         out_be32(&intr->ctrl, ctrl_reg);
 
-        __set_irq_handler_unlocked(d->irq, handler);
+        __irq_set_handler_locked(d->irq, handler);
 
         return 0;
 }
@@ -414,7 +414,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
                 else
                         hndlr = handle_level_irq;
 
-                set_irq_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
+                irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
                 pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
                          __func__, l2irq, virq, (int)irq, type);
                 return 0;
@@ -431,7 +431,7 @@ static int mpc52xx_irqhost_map(struct irq_host *h, unsigned int virq,
                 return -EINVAL;
         }
 
-        set_irq_chip_and_handler(virq, irqchip, handle_level_irq);
+        irq_set_chip_and_handler(virq, irqchip, handle_level_irq);
         pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
 
         return 0;
diff --git a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
index 926dfdaaf57a..4a4eb6ffa12f 100644
--- a/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++ b/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
@@ -81,7 +81,7 @@ static struct irq_chip pq2ads_pci_ic = {
 
 static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
 {
-        struct pq2ads_pci_pic *priv = get_irq_desc_data(desc);
+        struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
         u32 stat, mask, pend;
         int bit;
 
@@ -106,17 +106,17 @@ static void pq2ads_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
 static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
                             irq_hw_number_t hw)
 {
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_data(virq, h->host_data);
-        set_irq_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
         return 0;
 }
 
 static void pci_host_unmap(struct irq_host *h, unsigned int virq)
 {
         /* remove chip and handler */
-        set_irq_chip_data(virq, NULL);
-        set_irq_chip(virq, NULL);
+        irq_set_chip_data(virq, NULL);
+        irq_set_chip(virq, NULL);
 }
 
 static struct irq_host_ops pci_pic_host_ops = {
@@ -175,8 +175,8 @@ int __init pq2ads_pci_init_irq(void)
 
         priv->host = host;
         host->host_data = priv;
-        set_irq_data(irq, priv);
-        set_irq_chained_handler(irq, pq2ads_pci_irq_demux);
+        irq_set_handler_data(irq, priv);
+        irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
 
         of_node_put(np);
         return 0;
diff --git a/arch/powerpc/platforms/85xx/ksi8560.c b/arch/powerpc/platforms/85xx/ksi8560.c
index 64447e48f3d5..c46f9359be15 100644
--- a/arch/powerpc/platforms/85xx/ksi8560.c
+++ b/arch/powerpc/platforms/85xx/ksi8560.c
@@ -56,7 +56,7 @@ static void machine_restart(char *cmd)
 
 static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         int cascade_irq;
 
         while ((cascade_irq = cpm2_get_irq()) >= 0)
@@ -106,7 +106,7 @@ static void __init ksi8560_pic_init(void)
 
         cpm2_pic_init(np);
         of_node_put(np);
-        set_irq_chained_handler(irq, cpm2_cascade);
+        irq_set_chained_handler(irq, cpm2_cascade);
 #endif
 }
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ads.c b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
index 1352d1107bfd..3b2c9bb66199 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ads.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ads.c
@@ -50,7 +50,7 @@ static int mpc85xx_exclude_device(struct pci_controller *hose,
 
 static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         int cascade_irq;
 
         while ((cascade_irq = cpm2_get_irq()) >= 0)
@@ -101,7 +101,7 @@ static void __init mpc85xx_ads_pic_init(void)
 
         cpm2_pic_init(np);
         of_node_put(np);
-        set_irq_chained_handler(irq, cpm2_cascade);
+        irq_set_chained_handler(irq, cpm2_cascade);
 #endif
 }
 
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_cds.c b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
index 458d91fba91d..6299a2a51ae8 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_cds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_cds.c
@@ -255,7 +255,7 @@ static int mpc85xx_cds_8259_attach(void)
         }
 
         /* Success. Connect our low-level cascade handler. */
-        set_irq_handler(cascade_irq, mpc85xx_8259_cascade_handler);
+        irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_ds.c b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
index 793ead7993ab..c7b97f70312e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_ds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_ds.c
@@ -47,7 +47,7 @@
 #ifdef CONFIG_PPC_I8259
 static void mpc85xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq = i8259_irq();
 
         if (cascade_irq != NO_IRQ) {
@@ -122,7 +122,7 @@ void __init mpc85xx_ds_pic_init(void)
         i8259_init(cascade_node, 0);
         of_node_put(cascade_node);
 
-        set_irq_chained_handler(cascade_irq, mpc85xx_8259_cascade);
+        irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
 #endif  /* CONFIG_PPC_I8259 */
 }
 
diff --git a/arch/powerpc/platforms/85xx/sbc8560.c b/arch/powerpc/platforms/85xx/sbc8560.c
index d7e28ec3e072..d2dfd465fbf6 100644
--- a/arch/powerpc/platforms/85xx/sbc8560.c
+++ b/arch/powerpc/platforms/85xx/sbc8560.c
@@ -41,7 +41,7 @@
 
 static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         int cascade_irq;
 
         while ((cascade_irq = cpm2_get_irq()) >= 0)
@@ -92,7 +92,7 @@ static void __init sbc8560_pic_init(void)
 
         cpm2_pic_init(np);
         of_node_put(np);
-        set_irq_chained_handler(irq, cpm2_cascade);
+        irq_set_chained_handler(irq, cpm2_cascade);
 #endif
 }
 
diff --git a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
index 79d85aca4767..db864623b4ae 100644
--- a/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
+++ b/arch/powerpc/platforms/85xx/socrates_fpga_pic.c
@@ -93,7 +93,7 @@ static inline unsigned int socrates_fpga_pic_get_irq(unsigned int irq)
 
 void socrates_fpga_pic_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq;
 
         /*
@@ -245,9 +245,9 @@ static int socrates_fpga_pic_host_map(struct irq_host *h, unsigned int virq,
                 irq_hw_number_t hwirq)
 {
         /* All interrupts are LEVEL sensitive */
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &socrates_fpga_pic_chip,
-                        handle_fasteoi_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &socrates_fpga_pic_chip,
+                                 handle_fasteoi_irq);
 
         return 0;
 }
@@ -308,8 +308,8 @@ void socrates_fpga_pic_init(struct device_node *pic)
                         pr_warning("FPGA PIC: can't get irq%d.\n", i);
                         continue;
                 }
-                set_irq_chained_handler(socrates_fpga_irqs[i],
-                                socrates_fpga_pic_cascade);
+                irq_set_chained_handler(socrates_fpga_irqs[i],
+                                        socrates_fpga_pic_cascade);
         }
 
         socrates_fpga_pic_iobase = of_iomap(pic, 0);
diff --git a/arch/powerpc/platforms/85xx/stx_gp3.c b/arch/powerpc/platforms/85xx/stx_gp3.c
index 2b62b064eac7..5387e9f06bdb 100644
--- a/arch/powerpc/platforms/85xx/stx_gp3.c
+++ b/arch/powerpc/platforms/85xx/stx_gp3.c
@@ -46,7 +46,7 @@
 
 static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         int cascade_irq;
 
         while ((cascade_irq = cpm2_get_irq()) >= 0)
@@ -102,7 +102,7 @@ static void __init stx_gp3_pic_init(void)
 
         cpm2_pic_init(np);
         of_node_put(np);
-        set_irq_chained_handler(irq, cpm2_cascade);
+        irq_set_chained_handler(irq, cpm2_cascade);
 #endif
 }
 
diff --git a/arch/powerpc/platforms/85xx/tqm85xx.c b/arch/powerpc/platforms/85xx/tqm85xx.c
index 2265b68e3279..325de772725a 100644
--- a/arch/powerpc/platforms/85xx/tqm85xx.c
+++ b/arch/powerpc/platforms/85xx/tqm85xx.c
@@ -44,7 +44,7 @@
 
 static void cpm2_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         int cascade_irq;
 
         while ((cascade_irq = cpm2_get_irq()) >= 0)
@@ -100,7 +100,7 @@ static void __init tqm85xx_pic_init(void)
 
         cpm2_pic_init(np);
         of_node_put(np);
-        set_irq_chained_handler(irq, cpm2_cascade);
+        irq_set_chained_handler(irq, cpm2_cascade);
 #endif
 }
 
diff --git a/arch/powerpc/platforms/86xx/gef_pic.c b/arch/powerpc/platforms/86xx/gef_pic.c
index 0adfe3b740cd..0beec7d5566b 100644
--- a/arch/powerpc/platforms/86xx/gef_pic.c
+++ b/arch/powerpc/platforms/86xx/gef_pic.c
@@ -95,7 +95,7 @@ static int gef_pic_cascade_irq;
 
 void gef_pic_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq;
 
         /*
@@ -163,8 +163,8 @@ static int gef_pic_host_map(struct irq_host *h, unsigned int virq,
                           irq_hw_number_t hwirq)
 {
         /* All interrupts are LEVEL sensitive */
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &gef_pic_chip, handle_level_irq);
 
         return 0;
 }
@@ -225,7 +225,7 @@ void __init gef_pic_init(struct device_node *np)
                 return;
 
         /* Chain with parent controller */
-        set_irq_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
+        irq_set_chained_handler(gef_pic_cascade_irq, gef_pic_cascade);
 }
 
 /*
diff --git a/arch/powerpc/platforms/86xx/pic.c b/arch/powerpc/platforms/86xx/pic.c
index cbe33639b478..8ef8960abda6 100644
--- a/arch/powerpc/platforms/86xx/pic.c
+++ b/arch/powerpc/platforms/86xx/pic.c
@@ -19,7 +19,7 @@
 #ifdef CONFIG_PPC_I8259
 static void mpc86xx_8259_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq = i8259_irq();
 
         if (cascade_irq != NO_IRQ)
@@ -77,6 +77,6 @@ void __init mpc86xx_init_irq(void)
         i8259_init(cascade_node, 0);
         of_node_put(cascade_node);
 
-        set_irq_chained_handler(cascade_irq, mpc86xx_8259_cascade);
+        irq_set_chained_handler(cascade_irq, mpc86xx_8259_cascade);
 #endif
 }
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
index fabb108e8744..9ecce995dd4b 100644
--- a/arch/powerpc/platforms/8xx/m8xx_setup.c
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -226,11 +226,11 @@ static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
 
                 generic_handle_irq(cascade_irq);
 
-                chip = get_irq_desc_chip(cdesc);
+                chip = irq_desc_get_chip(cdesc);
                 chip->irq_eoi(&cdesc->irq_data);
         }
 
-        chip = get_irq_desc_chip(desc);
+        chip = irq_desc_get_chip(desc);
         chip->irq_eoi(&desc->irq_data);
 }
 
@@ -251,5 +251,5 @@ void __init mpc8xx_pics_init(void)
 
         irq = cpm_pic_init();
         if (irq != NO_IRQ)
-                set_irq_chained_handler(irq, cpm_cascade);
+                irq_set_chained_handler(irq, cpm_cascade);
 }
diff --git a/arch/powerpc/platforms/cell/Kconfig b/arch/powerpc/platforms/cell/Kconfig
index 48cd7d2e1b75..81239ebed83f 100644
--- a/arch/powerpc/platforms/cell/Kconfig
+++ b/arch/powerpc/platforms/cell/Kconfig
@@ -9,6 +9,7 @@ config PPC_CELL_COMMON
         select PPC_INDIRECT_IO
         select PPC_NATIVE
         select PPC_RTAS
+        select IRQ_EDGE_EOI_HANDLER
 
 config PPC_CELL_NATIVE
         bool
diff --git a/arch/powerpc/platforms/cell/axon_msi.c b/arch/powerpc/platforms/cell/axon_msi.c
index c48b66a67e42..bb5ebf8fa80b 100644
--- a/arch/powerpc/platforms/cell/axon_msi.c
+++ b/arch/powerpc/platforms/cell/axon_msi.c
@@ -93,8 +93,8 @@ static void msic_dcr_write(struct axon_msic *msic, unsigned int dcr_n, u32 val)
 
 static void axon_msi_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
-        struct axon_msic *msic = get_irq_data(irq);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct axon_msic *msic = irq_get_handler_data(irq);
         u32 write_offset, msi;
         int idx;
         int retry = 0;
@@ -287,7 +287,7 @@ static int axon_msi_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
                 }
                 dev_dbg(&dev->dev, "axon_msi: allocated virq 0x%x\n", virq);
 
-                set_irq_msi(virq, entry);
+                irq_set_msi_desc(virq, entry);
                 msg.data = virq;
                 write_msi_msg(virq, &msg);
         }
@@ -305,7 +305,7 @@ static void axon_msi_teardown_msi_irqs(struct pci_dev *dev)
                 if (entry->irq == NO_IRQ)
                         continue;
 
-                set_irq_msi(entry->irq, NULL);
+                irq_set_msi_desc(entry->irq, NULL);
                 irq_dispose_mapping(entry->irq);
         }
 }
@@ -320,7 +320,7 @@ static struct irq_chip msic_irq_chip = {
 static int msic_host_map(struct irq_host *h, unsigned int virq,
                          irq_hw_number_t hw)
 {
-        set_irq_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
+        irq_set_chip_and_handler(virq, &msic_irq_chip, handle_simple_irq);
 
         return 0;
 }
@@ -400,8 +400,8 @@ static int axon_msi_probe(struct platform_device *device)
 
         msic->irq_host->host_data = msic;
 
-        set_irq_data(virq, msic);
-        set_irq_chained_handler(virq, axon_msi_cascade);
+        irq_set_handler_data(virq, msic);
+        irq_set_chained_handler(virq, axon_msi_cascade);
         pr_devel("axon_msi: irq 0x%x setup for axon_msi\n", virq);
 
         /* Enable the MSIC hardware */
diff --git a/arch/powerpc/platforms/cell/beat_interrupt.c b/arch/powerpc/platforms/cell/beat_interrupt.c
index 0b8f7d7135c5..4cb9e147c307 100644
--- a/arch/powerpc/platforms/cell/beat_interrupt.c
+++ b/arch/powerpc/platforms/cell/beat_interrupt.c
@@ -136,15 +136,14 @@ static void beatic_pic_host_unmap(struct irq_host *h, unsigned int virq)
 static int beatic_pic_host_map(struct irq_host *h, unsigned int virq,
                                irq_hw_number_t hw)
 {
-        struct irq_desc *desc = irq_to_desc(virq);
         int64_t err;
 
         err = beat_construct_and_connect_irq_plug(virq, hw);
         if (err < 0)
                 return -EIO;
 
-        desc->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &beatic_pic, handle_fasteoi_irq);
         return 0;
 }
 
diff --git a/arch/powerpc/platforms/cell/interrupt.c b/arch/powerpc/platforms/cell/interrupt.c
index 624d26e72f1d..a19bec078703 100644
--- a/arch/powerpc/platforms/cell/interrupt.c
+++ b/arch/powerpc/platforms/cell/interrupt.c
@@ -101,9 +101,9 @@ static void iic_ioexc_eoi(struct irq_data *d)
 
 static void iic_ioexc_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         struct cbe_iic_regs __iomem *node_iic =
-                (void __iomem *)get_irq_desc_data(desc);
+                (void __iomem *)irq_desc_get_handler_data(desc);
         unsigned int base = (irq & 0xffffff00) | IIC_IRQ_TYPE_IOEXC;
         unsigned long bits, ack;
         int cascade;
@@ -235,67 +235,19 @@ static int iic_host_match(struct irq_host *h, struct device_node *node)
                                     "IBM,CBEA-Internal-Interrupt-Controller");
 }
 
-extern int noirqdebug;
-
-static void handle_iic_irq(unsigned int irq, struct irq_desc *desc)
-{
-        struct irq_chip *chip = get_irq_desc_chip(desc);
-
-        raw_spin_lock(&desc->lock);
-
-        desc->status &= ~(IRQ_REPLAY | IRQ_WAITING);
-
-        /*
-         * If we're currently running this IRQ, or its disabled,
-         * we shouldn't process the IRQ. Mark it pending, handle
-         * the necessary masking and go out
-         */
-        if (unlikely((desc->status & (IRQ_INPROGRESS | IRQ_DISABLED)) ||
-                    !desc->action)) {
-                desc->status |= IRQ_PENDING;
-                goto out_eoi;
-        }
-
-        kstat_incr_irqs_this_cpu(irq, desc);
-
-        /* Mark the IRQ currently in progress.*/
-        desc->status |= IRQ_INPROGRESS;
-
-        do {
-                struct irqaction *action = desc->action;
-                irqreturn_t action_ret;
-
-                if (unlikely(!action))
-                        goto out_eoi;
-
-                desc->status &= ~IRQ_PENDING;
-                raw_spin_unlock(&desc->lock);
-                action_ret = handle_IRQ_event(irq, action);
-                if (!noirqdebug)
-                        note_interrupt(irq, desc, action_ret);
-                raw_spin_lock(&desc->lock);
-
-        } while ((desc->status & (IRQ_PENDING | IRQ_DISABLED)) == IRQ_PENDING);
-
-        desc->status &= ~IRQ_INPROGRESS;
-out_eoi:
-        chip->irq_eoi(&desc->irq_data);
-        raw_spin_unlock(&desc->lock);
-}
-
 static int iic_host_map(struct irq_host *h, unsigned int virq,
                         irq_hw_number_t hw)
 {
         switch (hw & IIC_IRQ_TYPE_MASK) {
         case IIC_IRQ_TYPE_IPI:
-                set_irq_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
+                irq_set_chip_and_handler(virq, &iic_chip, handle_percpu_irq);
                 break;
         case IIC_IRQ_TYPE_IOEXC:
-                set_irq_chip_and_handler(virq, &iic_ioexc_chip,
+                irq_set_chip_and_handler(virq, &iic_ioexc_chip,
                                          handle_iic_irq);
                 break;
         default:
-                set_irq_chip_and_handler(virq, &iic_chip, handle_iic_irq);
+                irq_set_chip_and_handler(virq, &iic_chip, handle_edge_eoi_irq);
         }
         return 0;
 }
@@ -412,8 +364,8 @@ static int __init setup_iic(void)
                  * irq_data is a generic pointer that gets passed back
                  * to us later, so the forced cast is fine.
                  */
-                set_irq_data(cascade, (void __force *)node_iic);
-                set_irq_chained_handler(cascade , iic_ioexc_cascade);
+                irq_set_handler_data(cascade, (void __force *)node_iic);
+                irq_set_chained_handler(cascade, iic_ioexc_cascade);
                 out_be64(&node_iic->iic_ir,
                          (1 << 12)              /* priority */ |
                          (node << 4)            /* dest node */ |
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c
index 6a28d027d959..fd57bfe00edf 100644
--- a/arch/powerpc/platforms/cell/setup.c
+++ b/arch/powerpc/platforms/cell/setup.c
@@ -187,8 +187,8 @@ machine_subsys_initcall(cell, cell_publish_devices);
 
 static void cell_mpic_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
-        struct mpic *mpic = get_irq_desc_data(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct mpic *mpic = irq_desc_get_handler_data(desc);
         unsigned int virq;
 
         virq = mpic_get_one_irq(mpic);
@@ -223,8 +223,8 @@ static void __init mpic_init_IRQ(void)
 
                 printk(KERN_INFO "%s : hooking up to IRQ %d\n",
                        dn->full_name, virq);
-                set_irq_data(virq, mpic);
-                set_irq_chained_handler(virq, cell_mpic_cascade);
+                irq_set_handler_data(virq, mpic);
+                irq_set_chained_handler(virq, cell_mpic_cascade);
         }
 }
 
diff --git a/arch/powerpc/platforms/cell/spider-pic.c b/arch/powerpc/platforms/cell/spider-pic.c
index b38cdfc1deb8..c5cf50e6b45a 100644
--- a/arch/powerpc/platforms/cell/spider-pic.c
+++ b/arch/powerpc/platforms/cell/spider-pic.c
@@ -102,7 +102,7 @@ static void spider_ack_irq(struct irq_data *d)
 
         /* Reset edge detection logic if necessary
          */
-        if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
+        if (irqd_is_level_type(d))
                 return;
 
         /* Only interrupts 47 to 50 can be set to edge */
@@ -119,7 +119,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type)
         struct spider_pic *pic = spider_virq_to_pic(d->irq);
         unsigned int hw = irq_map[d->irq].hwirq;
         void __iomem *cfg = spider_get_irq_config(pic, hw);
-        struct irq_desc *desc = irq_to_desc(d->irq);
         u32 old_mask;
         u32 ic;
 
@@ -147,12 +146,6 @@ static int spider_set_irq_type(struct irq_data *d, unsigned int type)
                 return -EINVAL;
         }
 
-        /* Update irq_desc */
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= type & IRQ_TYPE_SENSE_MASK;
-        if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
-                desc->status |= IRQ_LEVEL;
-
         /* Configure the source. One gross hack that was there before and
          * that I've kept around is the priority to the BE which I set to
          * be the same as the interrupt source number. I don't know wether
@@ -178,10 +171,10 @@ static struct irq_chip spider_pic = {
 static int spider_host_map(struct irq_host *h, unsigned int virq,
                         irq_hw_number_t hw)
 {
-        set_irq_chip_and_handler(virq, &spider_pic, handle_level_irq);
+        irq_set_chip_and_handler(virq, &spider_pic, handle_level_irq);
 
         /* Set default irq type */
-        set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
         return 0;
 }
@@ -207,8 +200,8 @@ static struct irq_host_ops spider_host_ops = {
 
 static void spider_irq_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
-        struct spider_pic *pic = get_irq_desc_data(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct spider_pic *pic = irq_desc_get_handler_data(desc);
         unsigned int cs, virq;
 
         cs = in_be32(pic->regs + TIR_CS) >> 24;
@@ -328,8 +321,8 @@ static void __init spider_init_one(struct device_node *of_node, int chip,
         virq = spider_find_cascade_and_node(pic);
         if (virq == NO_IRQ)
                 return;
-        set_irq_data(virq, pic);
-        set_irq_chained_handler(virq, spider_irq_cascade);
+        irq_set_handler_data(virq, pic);
+        irq_set_chained_handler(virq, spider_irq_cascade);
 
         printk(KERN_INFO "spider_pic: node %d, addr: 0x%lx %s\n",
                pic->node_id, addr, of_node->full_name);
diff --git a/arch/powerpc/platforms/chrp/setup.c b/arch/powerpc/platforms/chrp/setup.c
index 4c1288451a21..122786498419 100644
--- a/arch/powerpc/platforms/chrp/setup.c
+++ b/arch/powerpc/platforms/chrp/setup.c
@@ -365,7 +365,7 @@ void __init chrp_setup_arch(void)
 
 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq = i8259_irq();
 
         if (cascade_irq != NO_IRQ)
@@ -517,7 +517,7 @@ static void __init chrp_find_8259(void)
                 if (cascade_irq == NO_IRQ)
                         printk(KERN_ERR "i8259: failed to map cascade irq\n");
                 else
-                        set_irq_chained_handler(cascade_irq,
+                        irq_set_chained_handler(cascade_irq,
                                                 chrp_8259_cascade);
         }
 }
diff --git a/arch/powerpc/platforms/embedded6xx/flipper-pic.c b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
index 0aca0e28a8e5..12aa62b6f227 100644
--- a/arch/powerpc/platforms/embedded6xx/flipper-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/flipper-pic.c
@@ -101,16 +101,16 @@ static struct irq_host *flipper_irq_host;
 static int flipper_pic_map(struct irq_host *h, unsigned int virq,
                            irq_hw_number_t hwirq)
 {
-        set_irq_chip_data(virq, h->host_data);
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &flipper_pic, handle_level_irq);
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &flipper_pic, handle_level_irq);
         return 0;
 }
 
 static void flipper_pic_unmap(struct irq_host *h, unsigned int irq)
 {
-        set_irq_chip_data(irq, NULL);
-        set_irq_chip(irq, NULL);
+        irq_set_chip_data(irq, NULL);
+        irq_set_chip(irq, NULL);
 }
 
 static int flipper_pic_match(struct irq_host *h, struct device_node *np)
diff --git a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
index 35e448bd8479..2bdddfc9d520 100644
--- a/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+++ b/arch/powerpc/platforms/embedded6xx/hlwd-pic.c
@@ -94,16 +94,16 @@ static struct irq_host *hlwd_irq_host;
 static int hlwd_pic_map(struct irq_host *h, unsigned int virq,
                            irq_hw_number_t hwirq)
 {
-        set_irq_chip_data(virq, h->host_data);
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &hlwd_pic, handle_level_irq);
         return 0;
 }
 
 static void hlwd_pic_unmap(struct irq_host *h, unsigned int irq)
 {
-        set_irq_chip_data(irq, NULL);
-        set_irq_chip(irq, NULL);
+        irq_set_chip_data(irq, NULL);
+        irq_set_chip(irq, NULL);
 }
 
 static struct irq_host_ops hlwd_irq_host_ops = {
@@ -129,8 +129,8 @@ static unsigned int __hlwd_pic_get_irq(struct irq_host *h)
 static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
                                       struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
-        struct irq_host *irq_host = get_irq_data(cascade_virq);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct irq_host *irq_host = irq_get_handler_data(cascade_virq);
         unsigned int virq;
 
         raw_spin_lock(&desc->lock);
@@ -145,7 +145,7 @@ static void hlwd_pic_irq_cascade(unsigned int cascade_virq,
 
         raw_spin_lock(&desc->lock);
         chip->irq_ack(&desc->irq_data); /* IRQ_LEVEL */
-        if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
+        if (!irqd_irq_disabled(&desc->irq_data) && chip->irq_unmask)
                 chip->irq_unmask(&desc->irq_data);
         raw_spin_unlock(&desc->lock);
 }
@@ -218,8 +218,8 @@ void hlwd_pic_probe(void)
                         host = hlwd_pic_init(np);
                         BUG_ON(!host);
                         cascade_virq = irq_of_parse_and_map(np, 0);
-                        set_irq_data(cascade_virq, host);
-                        set_irq_chained_handler(cascade_virq,
+                        irq_set_handler_data(cascade_virq, host);
+                        irq_set_chained_handler(cascade_virq,
                                                 hlwd_pic_irq_cascade);
                         hlwd_irq_host = host;
                         break;
diff --git a/arch/powerpc/platforms/embedded6xx/holly.c b/arch/powerpc/platforms/embedded6xx/holly.c
index b21fde589ca7..487bda0d18d8 100644
--- a/arch/powerpc/platforms/embedded6xx/holly.c
+++ b/arch/powerpc/platforms/embedded6xx/holly.c
@@ -198,8 +198,8 @@ static void __init holly_init_IRQ(void)
         cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
         pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq);
         tsi108_pci_int_init(cascade_node);
-        set_irq_data(cascade_pci_irq, mpic);
-        set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
+        irq_set_handler_data(cascade_pci_irq, mpic);
+        irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
 #endif
         /* Configure MPIC outputs to CPU0 */
         tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
diff --git a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
index 7a2ba39d7811..1cb907c94359 100644
--- a/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
+++ b/arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
@@ -153,8 +153,8 @@ static void __init mpc7448_hpc2_init_IRQ(void)
         DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__,
             (u32) cascade_pci_irq);
         tsi108_pci_int_init(cascade_node);
-        set_irq_data(cascade_pci_irq, mpic);
-        set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
+        irq_set_handler_data(cascade_pci_irq, mpic);
+        irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
 #endif
         /* Configure MPIC outputs to CPU0 */
         tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
diff --git a/arch/powerpc/platforms/iseries/irq.c b/arch/powerpc/platforms/iseries/irq.c
index 4fb96f0b2df6..52a6889832c7 100644
--- a/arch/powerpc/platforms/iseries/irq.c
+++ b/arch/powerpc/platforms/iseries/irq.c
@@ -220,7 +220,7 @@ void __init iSeries_activate_IRQs()
                 if (!desc)
                         continue;
 
-                chip = get_irq_desc_chip(desc);
+                chip = irq_desc_get_chip(desc);
                 if (chip && chip->irq_startup) {
                         raw_spin_lock_irqsave(&desc->lock, flags);
                         chip->irq_startup(&desc->irq_data);
@@ -346,7 +346,7 @@ unsigned int iSeries_get_irq(void)
 static int iseries_irq_host_map(struct irq_host *h, unsigned int virq,
                                 irq_hw_number_t hw)
 {
-        set_irq_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq);
+        irq_set_chip_and_handler(virq, &iseries_pic, handle_fasteoi_irq);
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/maple/pci.c b/arch/powerpc/platforms/maple/pci.c
index 04296ffff8bf..dd2e48b28508 100644
--- a/arch/powerpc/platforms/maple/pci.c
+++ b/arch/powerpc/platforms/maple/pci.c
@@ -498,7 +498,7 @@ void __devinit maple_pci_irq_fixup(struct pci_dev *dev)
                 printk(KERN_DEBUG "Fixup U4 PCIe IRQ\n");
                 dev->irq = irq_create_mapping(NULL, 1);
                 if (dev->irq != NO_IRQ)
-                        set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
+                        irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
         }
 
         /* Hide AMD8111 IDE interrupt when in legacy mode so
diff --git a/arch/powerpc/platforms/pasemi/setup.c b/arch/powerpc/platforms/pasemi/setup.c
index a6067b38d2ca..7c858e6f843c 100644
--- a/arch/powerpc/platforms/pasemi/setup.c
+++ b/arch/powerpc/platforms/pasemi/setup.c
@@ -239,7 +239,7 @@ static __init void pas_init_IRQ(void)
         if (nmiprop) {
                 nmi_virq = irq_create_mapping(NULL, *nmiprop);
                 mpic_irq_set_priority(nmi_virq, 15);
-                set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
+                irq_set_irq_type(nmi_virq, IRQ_TYPE_EDGE_RISING);
                 mpic_unmask_irq(irq_get_irq_data(nmi_virq));
         }
 
diff --git a/arch/powerpc/platforms/powermac/pci.c b/arch/powerpc/platforms/powermac/pci.c
index 3bc075c788ef..ab6898942700 100644
--- a/arch/powerpc/platforms/powermac/pci.c
+++ b/arch/powerpc/platforms/powermac/pci.c
@@ -988,7 +988,7 @@ void __devinit pmac_pci_irq_fixup(struct pci_dev *dev)
             dev->vendor == PCI_VENDOR_ID_DEC &&
             dev->device == PCI_DEVICE_ID_DEC_TULIP_PLUS) {
                 dev->irq = irq_create_mapping(NULL, 60);
-                set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
+                irq_set_irq_type(dev->irq, IRQ_TYPE_LEVEL_LOW);
         }
 #endif /* CONFIG_PPC32 */
 }
diff --git a/arch/powerpc/platforms/powermac/pic.c b/arch/powerpc/platforms/powermac/pic.c
index c55812bb6a51..023f24086a0a 100644
--- a/arch/powerpc/platforms/powermac/pic.c
+++ b/arch/powerpc/platforms/powermac/pic.c
@@ -157,7 +157,7 @@ static unsigned int pmac_startup_irq(struct irq_data *d)
         int i = src >> 5;
 
         raw_spin_lock_irqsave(&pmac_pic_lock, flags);
-        if ((irq_to_desc(d->irq)->status & IRQ_LEVEL) == 0)
+        if (!irqd_is_level_type(d))
                 out_le32(&pmac_irq_hw[i]->ack, bit);
         __set_bit(src, ppc_cached_irq_mask);
         __pmac_set_irq_mask(src, 0);
@@ -289,7 +289,6 @@ static int pmac_pic_host_match(struct irq_host *h, struct device_node *node)
 static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
                              irq_hw_number_t hw)
 {
-        struct irq_desc *desc = irq_to_desc(virq);
         int level;
 
         if (hw >= max_irqs)
@@ -300,9 +299,9 @@ static int pmac_pic_host_map(struct irq_host *h, unsigned int virq,
          */
         level = !!(level_mask[hw >> 5] & (1UL << (hw & 0x1f)));
         if (level)
-                desc->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &pmac_pic, level ?
-                                 handle_level_irq : handle_edge_irq);
+                irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &pmac_pic,
+                                 level ? handle_level_irq : handle_edge_irq);
         return 0;
 }
 
@@ -472,8 +471,8 @@ int of_irq_map_oldworld(struct device_node *device, int index,
 
 static void pmac_u3_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
-        struct mpic *mpic = get_irq_desc_data(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct mpic *mpic = irq_desc_get_handler_data(desc);
         unsigned int cascade_irq = mpic_get_one_irq(mpic);
 
         if (cascade_irq != NO_IRQ)
@@ -591,8 +590,8 @@ static int __init pmac_pic_probe_mpic(void)
                 of_node_put(slave);
                 return 0;
         }
-        set_irq_data(cascade, mpic2);
-        set_irq_chained_handler(cascade, pmac_u3_cascade);
+        irq_set_handler_data(cascade, mpic2);
+        irq_set_chained_handler(cascade, pmac_u3_cascade);
 
         of_node_put(slave);
         return 0;
diff --git a/arch/powerpc/platforms/ps3/interrupt.c b/arch/powerpc/platforms/ps3/interrupt.c
index 3988c86682a5..f2f6413b81d3 100644
--- a/arch/powerpc/platforms/ps3/interrupt.c
+++ b/arch/powerpc/platforms/ps3/interrupt.c
@@ -194,7 +194,7 @@ static int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
         pr_debug("%s:%d: outlet %lu => cpu %u, virq %u\n", __func__, __LINE__,
                 outlet, cpu, *virq);
 
-        result = set_irq_chip_data(*virq, pd);
+        result = irq_set_chip_data(*virq, pd);
 
         if (result) {
                 pr_debug("%s:%d: set_irq_chip_data failed\n",
@@ -221,12 +221,12 @@ fail_create:
 
 static int ps3_virq_destroy(unsigned int virq)
 {
-        const struct ps3_private *pd = get_irq_chip_data(virq);
+        const struct ps3_private *pd = irq_get_chip_data(virq);
 
         pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
                 __LINE__, pd->ppe_id, pd->thread_id, virq);
 
-        set_irq_chip_data(virq, NULL);
+        irq_set_chip_data(virq, NULL);
         irq_dispose_mapping(virq);
 
         pr_debug("%s:%d <-\n", __func__, __LINE__);
@@ -256,7 +256,7 @@ int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
                 goto fail_setup;
         }
 
-        pd = get_irq_chip_data(*virq);
+        pd = irq_get_chip_data(*virq);
 
         /* Binds outlet to cpu + virq. */
 
@@ -291,7 +291,7 @@ EXPORT_SYMBOL_GPL(ps3_irq_plug_setup);
 int ps3_irq_plug_destroy(unsigned int virq)
 {
         int result;
-        const struct ps3_private *pd = get_irq_chip_data(virq);
+        const struct ps3_private *pd = irq_get_chip_data(virq);
 
         pr_debug("%s:%d: ppe_id %llu, thread_id %llu, virq %u\n", __func__,
                 __LINE__, pd->ppe_id, pd->thread_id, virq);
@@ -661,7 +661,7 @@ static void dump_bmp(struct ps3_private* pd) {};
 
 static void ps3_host_unmap(struct irq_host *h, unsigned int virq)
 {
-        set_irq_chip_data(virq, NULL);
+        irq_set_chip_data(virq, NULL);
 }
 
 static int ps3_host_map(struct irq_host *h, unsigned int virq,
@@ -670,7 +670,7 @@ static int ps3_host_map(struct irq_host *h, unsigned int virq,
         pr_debug("%s:%d: hwirq %lu, virq %u\n", __func__, __LINE__, hwirq,
                 virq);
 
-        set_irq_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq);
+        irq_set_chip_and_handler(virq, &ps3_irq_chip, handle_fasteoi_irq);
 
         return 0;
 }
diff --git a/arch/powerpc/platforms/pseries/msi.c b/arch/powerpc/platforms/pseries/msi.c
index 18ac801f8e90..38d24e7e7bb1 100644
--- a/arch/powerpc/platforms/pseries/msi.c
+++ b/arch/powerpc/platforms/pseries/msi.c
@@ -137,7 +137,7 @@ static void rtas_teardown_msi_irqs(struct pci_dev *pdev)
                 if (entry->irq == NO_IRQ)
                         continue;
 
-                set_irq_msi(entry->irq, NULL);
+                irq_set_msi_desc(entry->irq, NULL);
                 irq_dispose_mapping(entry->irq);
         }
 
@@ -437,7 +437,7 @@ static int rtas_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                 }
 
                 dev_dbg(&pdev->dev, "rtas_msi: allocated virq %d\n", virq);
-                set_irq_msi(virq, entry);
+                irq_set_msi_desc(virq, entry);
 
                 /* Read config space back so we can restore after reset */
                 read_msi_msg(virq, &msg);
diff --git a/arch/powerpc/platforms/pseries/setup.c b/arch/powerpc/platforms/pseries/setup.c
index 2a0089a2c829..c319d04aa799 100644
--- a/arch/powerpc/platforms/pseries/setup.c
+++ b/arch/powerpc/platforms/pseries/setup.c
@@ -114,7 +114,7 @@ static void __init fwnmi_init(void)
 
 static void pseries_8259_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq = i8259_irq();
 
         if (cascade_irq != NO_IRQ)
@@ -169,7 +169,7 @@ static void __init pseries_setup_i8259_cascade(void)
                 printk(KERN_DEBUG "pic: PCI 8259 intack at 0x%016lx\n", intack);
         i8259_init(found, intack);
         of_node_put(found);
-        set_irq_chained_handler(cascade, pseries_8259_cascade);
+        irq_set_chained_handler(cascade, pseries_8259_cascade);
 }
 
 static void __init pseries_mpic_init_IRQ(void)
diff --git a/arch/powerpc/platforms/pseries/xics.c b/arch/powerpc/platforms/pseries/xics.c
index 01fea46c0335..6c1e638f0ce9 100644
--- a/arch/powerpc/platforms/pseries/xics.c
+++ b/arch/powerpc/platforms/pseries/xics.c
@@ -470,8 +470,8 @@ static int xics_host_map(struct irq_host *h, unsigned int virq,
         /* Insert the interrupt mapping into the radix tree for fast lookup */
         irq_radix_revmap_insert(xics_host, virq, hw);
 
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
         return 0;
 }
 
@@ -600,7 +600,7 @@ static void xics_request_ipi(void)
          * IPIs are marked IRQF_DISABLED as they must run with irqs
          * disabled
          */
-        set_irq_handler(ipi, handle_percpu_irq);
+        irq_set_handler(ipi, handle_percpu_irq);
         if (firmware_has_feature(FW_FEATURE_LPAR))
                 rc = request_irq(ipi, xics_ipi_action_lpar,
                                 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
@@ -912,7 +912,7 @@ void xics_migrate_irqs_away(void)
                 if (desc == NULL || desc->action == NULL)
                         continue;
 
-                chip = get_irq_desc_chip(desc);
+                chip = irq_desc_get_chip(desc);
                 if (chip == NULL || chip->irq_set_affinity == NULL)
                         continue;
 
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 0476bcc7c3e1..8b5aba263323 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -103,8 +103,8 @@ static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
 {
         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
         return 0;
 }
 
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index 473032556715..5495c1be472b 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -115,32 +115,25 @@ static void cpm2_ack(struct irq_data *d)
 
 static void cpm2_end_irq(struct irq_data *d)
 {
-        struct irq_desc *desc;
         int     bit, word;
         unsigned int irq_nr = virq_to_hw(d->irq);
 
-        desc = irq_to_desc(irq_nr);
-        if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))
-                        && desc->action) {
-
-                bit = irq_to_siubit[irq_nr];
-                word = irq_to_siureg[irq_nr];
+        bit = irq_to_siubit[irq_nr];
+        word = irq_to_siureg[irq_nr];
 
-                ppc_cached_irq_mask[word] |= 1 << bit;
-                out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
+        ppc_cached_irq_mask[word] |= 1 << bit;
+        out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
 
-                /*
-                 * Work around large numbers of spurious IRQs on PowerPC 82xx
-                 * systems.
-                 */
-                mb();
-        }
+        /*
+         * Work around large numbers of spurious IRQs on PowerPC 82xx
+         * systems.
+         */
+        mb();
 }
 
 static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
         unsigned int src = virq_to_hw(d->irq);
-        struct irq_desc *desc = irq_to_desc(d->irq);
         unsigned int vold, vnew, edibit;
 
         /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
@@ -162,13 +155,11 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
                         goto err_sense;
         }
 
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
-        if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
-                desc->status |= IRQ_LEVEL;
-                desc->handle_irq = handle_level_irq;
-        } else
-                desc->handle_irq = handle_edge_irq;
+        irqd_set_trigger_type(d, flow_type);
+        if (flow_type & IRQ_TYPE_LEVEL_LOW)
+                __irq_set_handler_locked(d->irq, handle_level_irq);
+        else
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
 
         /* internal IRQ senses are LEVEL_LOW
          * EXT IRQ and Port C IRQ senses are programmable
@@ -179,7 +170,8 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
                 if (src >= CPM2_IRQ_PORTC15 && src <= CPM2_IRQ_PORTC0)
                         edibit = (31 - (CPM2_IRQ_PORTC0 - src));
                 else
-                        return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
+                        return (flow_type & IRQ_TYPE_LEVEL_LOW) ?
+                                IRQ_SET_MASK_OK_NOCOPY : -EINVAL;
 
         vold = in_be32(&cpm2_intctl->ic_siexr);
 
@@ -190,7 +182,7 @@ static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
 
         if (vold != vnew)
                 out_be32(&cpm2_intctl->ic_siexr, vnew);
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;
 
 err_sense:
         pr_err("CPM2 PIC: sense type 0x%x not supported\n", flow_type);
@@ -204,6 +196,7 @@ static struct irq_chip cpm2_pic = {
         .irq_ack = cpm2_ack,
         .irq_eoi = cpm2_end_irq,
         .irq_set_type = cpm2_set_irq_type,
+        .flags = IRQCHIP_EOI_IF_HANDLED,
 };
 
 unsigned int cpm2_get_irq(void)
@@ -226,8 +219,8 @@ static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
 {
         pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
 
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
         return 0;
 }
 
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 58e09b2833f2..d5679dc1e20f 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -64,10 +64,10 @@ static int fsl_msi_host_map(struct irq_host *h, unsigned int virq,
         struct fsl_msi *msi_data = h->host_data;
         struct irq_chip *chip = &fsl_msi_chip;
 
-        irq_to_desc(virq)->status |= IRQ_TYPE_EDGE_FALLING;
+        irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
 
-        set_irq_chip_data(virq, msi_data);
-        set_irq_chip_and_handler(virq, chip, handle_edge_irq);
+        irq_set_chip_data(virq, msi_data);
+        irq_set_chip_and_handler(virq, chip, handle_edge_irq);
 
         return 0;
 }
@@ -110,8 +110,8 @@ static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
         list_for_each_entry(entry, &pdev->msi_list, list) {
                 if (entry->irq == NO_IRQ)
                         continue;
-                msi_data = get_irq_data(entry->irq);
-                set_irq_msi(entry->irq, NULL);
+                msi_data = irq_get_handler_data(entry->irq);
+                irq_set_msi_desc(entry->irq, NULL);
                 msi_bitmap_free_hwirqs(&msi_data->bitmap,
                                        virq_to_hw(entry->irq), 1);
                 irq_dispose_mapping(entry->irq);
@@ -168,8 +168,8 @@ static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                         rc = -ENOSPC;
                         goto out_free;
                 }
-                set_irq_data(virq, msi_data);
-                set_irq_msi(virq, entry);
+                irq_set_handler_data(virq, msi_data);
+                irq_set_msi_desc(virq, entry);
 
                 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
                 write_msi_msg(virq, &msg);
@@ -183,7 +183,8 @@ out_free:
 
 static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct irq_data *idata = irq_desc_get_irq_data(desc);
         unsigned int cascade_irq;
         struct fsl_msi *msi_data;
         int msir_index = -1;
@@ -192,20 +193,20 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
         u32 have_shift = 0;
         struct fsl_msi_cascade_data *cascade_data;
 
-        cascade_data = (struct fsl_msi_cascade_data *)get_irq_data(irq);
+        cascade_data = (struct fsl_msi_cascade_data *)irq_get_handler_data(irq);
         msi_data = cascade_data->msi_data;
 
         raw_spin_lock(&desc->lock);
         if ((msi_data->feature &  FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
                 if (chip->irq_mask_ack)
-                        chip->irq_mask_ack(&desc->irq_data);
+                        chip->irq_mask_ack(idata);
                 else {
-                        chip->irq_mask(&desc->irq_data);
-                        chip->irq_ack(&desc->irq_data);
+                        chip->irq_mask(idata);
+                        chip->irq_ack(idata);
                 }
         }
 
-        if (unlikely(desc->status & IRQ_INPROGRESS))
+        if (unlikely(irqd_irq_inprogress(idata)))
                 goto unlock;
 
         msir_index = cascade_data->index;
@@ -213,7 +214,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
         if (msir_index >= NR_MSI_REG)
                 cascade_irq = NO_IRQ;
 
-        desc->status |= IRQ_INPROGRESS;
+        irqd_set_chained_irq_inprogress(idata);
         switch (msi_data->feature & FSL_PIC_IP_MASK) {
         case FSL_PIC_IP_MPIC:
                 msir_value = fsl_msi_read(msi_data->msi_regs,
@@ -235,15 +236,15 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
                 have_shift += intr_index + 1;
                 msir_value = msir_value >> (intr_index + 1);
         }
-        desc->status &= ~IRQ_INPROGRESS;
+        irqd_clr_chained_irq_inprogress(idata);
 
         switch (msi_data->feature & FSL_PIC_IP_MASK) {
         case FSL_PIC_IP_MPIC:
-                chip->irq_eoi(&desc->irq_data);
+                chip->irq_eoi(idata);
                 break;
         case FSL_PIC_IP_IPIC:
-                if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
-                        chip->irq_unmask(&desc->irq_data);
+                if (!irqd_irq_disabled(idata) && chip->irq_unmask)
+                        chip->irq_unmask(idata);
                 break;
         }
 unlock:
@@ -261,7 +262,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
         for (i = 0; i < NR_MSI_REG; i++) {
                 virq = msi->msi_virqs[i];
                 if (virq != NO_IRQ) {
-                        cascade_data = get_irq_data(virq);
+                        cascade_data = irq_get_handler_data(virq);
                         kfree(cascade_data);
                         irq_dispose_mapping(virq);
                 }
@@ -297,8 +298,8 @@ static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
         msi->msi_virqs[irq_index] = virt_msir;
         cascade_data->index = offset + irq_index;
         cascade_data->msi_data = msi;
-        set_irq_data(virt_msir, cascade_data);
-        set_irq_chained_handler(virt_msir, fsl_msi_cascade);
+        irq_set_handler_data(virt_msir, cascade_data);
+        irq_set_chained_handler(virt_msir, fsl_msi_cascade);
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index aeda4c8d0a0a..142770cb84b6 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -175,13 +175,13 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq,
 
         /* We block the internal cascade */
         if (hw == 2)
-                irq_to_desc(virq)->status |= IRQ_NOREQUEST;
+                irq_set_status_flags(virq, IRQ_NOREQUEST);
 
         /* We use the level handler only for now, we might want to
          * be more cautious here but that works for now
          */
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
-        set_irq_chip_and_handler(virq, &i8259_pic, handle_level_irq);
+        irq_set_status_flags(virq, IRQ_LEVEL);
+        irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
         return 0;
 }
 
@@ -191,7 +191,7 @@ static void i8259_host_unmap(struct irq_host *h, unsigned int virq)
         i8259_mask_irq(irq_get_irq_data(virq));
 
         /* remove chip and handler */
-        set_irq_chip_and_handler(virq, NULL, NULL);
+        irq_set_chip_and_handler(virq, NULL, NULL);
 
         /* Make sure it's completed */
         synchronize_irq(virq);
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index 497047dc986e..fa438be962b7 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -605,7 +605,6 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
         struct ipic *ipic = ipic_from_irq(d->irq);
         unsigned int src = ipic_irq_to_hw(d->irq);
-        struct irq_desc *desc = irq_to_desc(d->irq);
         unsigned int vold, vnew, edibit;
 
         if (flow_type == IRQ_TYPE_NONE)
@@ -623,17 +622,16 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
                 printk(KERN_ERR "ipic: edge sense not supported on internal "
                                 "interrupts\n");
                 return -EINVAL;
+
         }
 
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
+        irqd_set_trigger_type(d, flow_type);
         if (flow_type & IRQ_TYPE_LEVEL_LOW)  {
-                desc->status |= IRQ_LEVEL;
-                desc->handle_irq = handle_level_irq;
-                desc->irq_data.chip = &ipic_level_irq_chip;
+                __irq_set_handler_locked(d->irq, handle_level_irq);
+                d->chip = &ipic_level_irq_chip;
         } else {
-                desc->handle_irq = handle_edge_irq;
-                desc->irq_data.chip = &ipic_edge_irq_chip;
+                __irq_set_handler_locked(d->irq, handle_edge_irq);
+                d->chip = &ipic_edge_irq_chip;
         }
 
         /* only EXT IRQ senses are programmable on ipic
@@ -655,7 +653,7 @@ static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         }
         if (vold != vnew)
                 ipic_write(ipic->regs, IPIC_SECNR, vnew);
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;
 }
 
 /* level interrupts and edge interrupts have different ack operations */
@@ -687,11 +685,11 @@ static int ipic_host_map(struct irq_host *h, unsigned int virq,
 {
         struct ipic *ipic = h->host_data;
 
-        set_irq_chip_data(virq, ipic);
-        set_irq_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
+        irq_set_chip_data(virq, ipic);
+        irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
 
         /* Set default irq type */
-        set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index 1a75a7fb4a99..f550e23632f8 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -72,13 +72,6 @@ static void mpc8xx_end_irq(struct irq_data *d)
 
 static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
-
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
-        if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
-                desc->status |= IRQ_LEVEL;
-
         if (flow_type & IRQ_TYPE_EDGE_FALLING) {
                 irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq;
                 unsigned int siel = in_be32(&siu_reg->sc_siel);
@@ -87,7 +80,7 @@ static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
                 if ((hw & 1) == 0) {
                         siel |= (0x80000000 >> hw);
                         out_be32(&siu_reg->sc_siel, siel);
-                        desc->handle_irq = handle_edge_irq;
+                        __irq_set_handler_locked(irq, handle_edge_irq);
                 }
         }
         return 0;
@@ -124,7 +117,7 @@ static int mpc8xx_pic_host_map(struct irq_host *h, unsigned int virq,
         pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq, hw);
 
         /* Set default irq handle */
-        set_irq_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
+        irq_set_chip_and_handler(virq, &mpc8xx_pic, handle_level_irq);
         return 0;
 }
 
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index 232e701245d7..0892a2841c2b 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -145,7 +145,7 @@ static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 
 static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc);
+        struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
         struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
         unsigned int mask;
 
@@ -278,9 +278,9 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
         if (mpc8xxx_gc->of_dev_id_data)
                 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
 
-        set_irq_chip_data(virq, h->host_data);
-        set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
-        set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_chip_data(virq, h->host_data);
+        irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
         return 0;
 }
@@ -369,8 +369,8 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
         out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
         out_be32(mm_gc->regs + GPIO_IMR, 0);
 
-        set_irq_data(hwirq, mpc8xxx_gc);
-        set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
+        irq_set_handler_data(hwirq, mpc8xxx_gc);
+        irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
 
 skip_irq:
         return;
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index 0f7c6718d261..f91c065bed5a 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -361,7 +361,7 @@ static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
 }
 
 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
-                                      unsigned int irqflags)
+                                      bool level)
 {
         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
         unsigned long flags;
@@ -370,14 +370,14 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
         if (fixup->base == NULL)
                 return;
 
-        DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
-            source, irqflags, fixup->index);
+        DBG("startup_ht_interrupt(0x%x) index: %d\n",
+            source, fixup->index);
         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
         /* Enable and configure */
         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
         tmp = readl(fixup->base + 4);
         tmp &= ~(0x23U);
-        if (irqflags & IRQ_LEVEL)
+        if (level)
                 tmp |= 0x22;
         writel(tmp, fixup->base + 4);
         raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
@@ -389,8 +389,7 @@ static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
 #endif
 }
 
-static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
-                                       unsigned int irqflags)
+static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
 {
         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
         unsigned long flags;
@@ -399,7 +398,7 @@ static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
         if (fixup->base == NULL)
                 return;
 
-        DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
+        DBG("shutdown_ht_interrupt(0x%x)\n", source);
 
         /* Disable */
         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
@@ -616,7 +615,7 @@ static struct mpic *mpic_find(unsigned int irq)
         if (irq < NUM_ISA_INTERRUPTS)
                 return NULL;
 
-        return get_irq_chip_data(irq);
+        return irq_get_chip_data(irq);
 }
 
 /* Determine if the linux irq is an IPI */
@@ -650,7 +649,7 @@ static inline struct mpic * mpic_from_ipi(struct irq_data *d)
 /* Get the mpic structure from the irq number */
 static inline struct mpic * mpic_from_irq(unsigned int irq)
 {
-        return get_irq_chip_data(irq);
+        return irq_get_chip_data(irq);
 }
 
 /* Get the mpic structure from the irq data */
@@ -738,7 +737,7 @@ static void mpic_unmask_ht_irq(struct irq_data *d)
 
         mpic_unmask_irq(d);
 
-        if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
+        if (irqd_is_level_type(d))
                 mpic_ht_end_irq(mpic, src);
 }
 
@@ -748,7 +747,7 @@ static unsigned int mpic_startup_ht_irq(struct irq_data *d)
         unsigned int src = mpic_irq_to_hw(d->irq);
 
         mpic_unmask_irq(d);
-        mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
+        mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
 
         return 0;
 }
@@ -758,7 +757,7 @@ static void mpic_shutdown_ht_irq(struct irq_data *d)
         struct mpic *mpic = mpic_from_irq_data(d);
         unsigned int src = mpic_irq_to_hw(d->irq);
 
-        mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
+        mpic_shutdown_ht_interrupt(mpic, src);
         mpic_mask_irq(d);
 }
 
@@ -775,7 +774,7 @@ static void mpic_end_ht_irq(struct irq_data *d)
          * latched another edge interrupt coming in anyway
          */
 
-        if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
+        if (irqd_is_level_type(d))
                 mpic_ht_end_irq(mpic, src);
         mpic_eoi(mpic);
 }
@@ -864,7 +863,6 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
         struct mpic *mpic = mpic_from_irq_data(d);
         unsigned int src = mpic_irq_to_hw(d->irq);
-        struct irq_desc *desc = irq_to_desc(d->irq);
         unsigned int vecpri, vold, vnew;
 
         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
@@ -879,10 +877,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         if (flow_type == IRQ_TYPE_NONE)
                 flow_type = IRQ_TYPE_LEVEL_LOW;
 
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
-        if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
-                desc->status |= IRQ_LEVEL;
+        irqd_set_trigger_type(d, flow_type);
 
         if (mpic_is_ht_interrupt(mpic, src))
                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
@@ -897,7 +892,7 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         if (vold != vnew)
                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
 
-        return 0;
+        return IRQ_SET_MASK_OK_NOCOPY;;
 }
 
 void mpic_set_vector(unsigned int virq, unsigned int vector)
@@ -983,8 +978,8 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
                 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
 
                 DBG("mpic: mapping as IPI\n");
-                set_irq_chip_data(virq, mpic);
-                set_irq_chip_and_handler(virq, &mpic->hc_ipi,
+                irq_set_chip_data(virq, mpic);
+                irq_set_chip_and_handler(virq, &mpic->hc_ipi,
                                          handle_percpu_irq);
                 return 0;
         }
@@ -1006,11 +1001,11 @@ static int mpic_host_map(struct irq_host *h, unsigned int virq,
 
         DBG("mpic: mapping to irq chip @%p\n", chip);
 
-        set_irq_chip_data(virq, mpic);
-        set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
+        irq_set_chip_data(virq, mpic);
+        irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
 
         /* Set default irq type */
-        set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
         /* If the MPIC was reset, then all vectors have already been
          * initialized.  Otherwise, a per source lazy initialization
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 0b7794acfce1..38e62382070c 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -81,7 +81,7 @@ static void pasemi_msi_teardown_msi_irqs(struct pci_dev *pdev)
                 if (entry->irq == NO_IRQ)
                         continue;
 
-                set_irq_msi(entry->irq, NULL);
+                irq_set_msi_desc(entry->irq, NULL);
                 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
                                        virq_to_hw(entry->irq), ALLOC_CHUNK);
                 irq_dispose_mapping(entry->irq);
@@ -131,9 +131,9 @@ static int pasemi_msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                  */
                 mpic_set_vector(virq, 0);
 
-                set_irq_msi(virq, entry);
-                set_irq_chip(virq, &mpic_pasemi_msi_chip);
-                set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
+                irq_set_msi_desc(virq, entry);
+                irq_set_chip(virq, &mpic_pasemi_msi_chip);
+                irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
 
                 pr_debug("pasemi_msi: allocated virq 0x%x (hw 0x%x) " \
                          "addr 0x%x\n", virq, hwirq, msg.address_lo);
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index 71900ac78270..9a7aa0ed9c1c 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -129,7 +129,7 @@ static void u3msi_teardown_msi_irqs(struct pci_dev *pdev)
                 if (entry->irq == NO_IRQ)
                         continue;
 
-                set_irq_msi(entry->irq, NULL);
+                irq_set_msi_desc(entry->irq, NULL);
                 msi_bitmap_free_hwirqs(&msi_mpic->msi_bitmap,
                                        virq_to_hw(entry->irq), 1);
                 irq_dispose_mapping(entry->irq);
@@ -166,9 +166,9 @@ static int u3msi_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
                         return -ENOSPC;
                 }
 
-                set_irq_msi(virq, entry);
-                set_irq_chip(virq, &mpic_u3msi_chip);
-                set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
+                irq_set_msi_desc(virq, entry);
+                irq_set_chip(virq, &mpic_u3msi_chip);
+                irq_set_irq_type(virq, IRQ_TYPE_EDGE_RISING);
 
                 pr_debug("u3msi: allocated virq 0x%x (hw 0x%x) addr 0x%lx\n",
                           virq, hwirq, (unsigned long)addr);
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c
index bc61ebb8987c..e9c633c7c083 100644
--- a/arch/powerpc/sysdev/mv64x60_pic.c
+++ b/arch/powerpc/sysdev/mv64x60_pic.c
@@ -213,11 +213,12 @@ static int mv64x60_host_map(struct irq_host *h, unsigned int virq,
 {
         int level1;
 
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
+        irq_set_status_flags(virq, IRQ_LEVEL);
 
         level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
         BUG_ON(level1 > MV64x60_LEVEL1_GPP);
-        set_irq_chip_and_handler(virq, mv64x60_chips[level1], handle_level_irq);
+        irq_set_chip_and_handler(virq, mv64x60_chips[level1],
+                                 handle_level_irq);
 
         return 0;
 }
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 8c9ded8ea07c..832d6924ad1c 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -189,7 +189,7 @@ static inline void qe_ic_write(volatile __be32  __iomem * base, unsigned int reg
 
 static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
 {
-        return get_irq_chip_data(virq);
+        return irq_get_chip_data(virq);
 }
 
 static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
@@ -267,10 +267,10 @@ static int qe_ic_host_map(struct irq_host *h, unsigned int virq,
         /* Default chip */
         chip = &qe_ic->hc_irq;
 
-        set_irq_chip_data(virq, qe_ic);
-        irq_to_desc(virq)->status |= IRQ_LEVEL;
+        irq_set_chip_data(virq, qe_ic);
+        irq_set_status_flags(virq, IRQ_LEVEL);
 
-        set_irq_chip_and_handler(virq, chip, handle_level_irq);
+        irq_set_chip_and_handler(virq, chip, handle_level_irq);
 
         return 0;
 }
@@ -386,13 +386,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
 
         qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
 
-        set_irq_data(qe_ic->virq_low, qe_ic);
-        set_irq_chained_handler(qe_ic->virq_low, low_handler);
+        irq_set_handler_data(qe_ic->virq_low, qe_ic);
+        irq_set_chained_handler(qe_ic->virq_low, low_handler);
 
         if (qe_ic->virq_high != NO_IRQ &&
                         qe_ic->virq_high != qe_ic->virq_low) {
-                set_irq_data(qe_ic->virq_high, qe_ic);
-                set_irq_chained_handler(qe_ic->virq_high, high_handler);
+                irq_set_handler_data(qe_ic->virq_high, qe_ic);
+                irq_set_chained_handler(qe_ic->virq_high, high_handler);
         }
 }
 
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 02c91db90037..4d18658116e5 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -391,8 +391,8 @@ static int pci_irq_host_map(struct irq_host *h, unsigned int virq,
         DBG("%s(%d, 0x%lx)\n", __func__, virq, hw);
         if ((virq >= 1) && (virq <= 4)){
                 irq = virq + IRQ_PCI_INTAD_BASE - 1;
-                irq_to_desc(irq)->status |= IRQ_LEVEL;
-                set_irq_chip(irq, &tsi108_pci_irq);
+                irq_set_status_flags(irq, IRQ_LEVEL);
+                irq_set_chip(irq, &tsi108_pci_irq);
         }
         return 0;
 }
@@ -431,7 +431,7 @@ void __init tsi108_pci_int_init(struct device_node *node)
 
 void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq = get_pci_source();
 
         if (cascade_irq != NO_IRQ)
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 835f7958b237..5d9138516628 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -57,7 +57,6 @@ struct uic {
 
 static void uic_unmask_irq(struct irq_data *d)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
         struct uic *uic = irq_data_get_irq_chip_data(d);
         unsigned int src = uic_irq_to_hw(d->irq);
         unsigned long flags;
@@ -66,7 +65,7 @@ static void uic_unmask_irq(struct irq_data *d)
         sr = 1 << (31-src);
         spin_lock_irqsave(&uic->lock, flags);
         /* ack level-triggered interrupts here */
-        if (desc->status & IRQ_LEVEL)
+        if (irqd_is_level_type(d))
                 mtdcr(uic->dcrbase + UIC_SR, sr);
         er = mfdcr(uic->dcrbase + UIC_ER);
         er |= sr;
@@ -101,7 +100,6 @@ static void uic_ack_irq(struct irq_data *d)
 
 static void uic_mask_ack_irq(struct irq_data *d)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
         struct uic *uic = irq_data_get_irq_chip_data(d);
         unsigned int src = uic_irq_to_hw(d->irq);
         unsigned long flags;
@@ -120,7 +118,7 @@ static void uic_mask_ack_irq(struct irq_data *d)
          * level interrupts are ack'ed after the actual
          * isr call in the uic_unmask_irq()
          */
-        if (!(desc->status & IRQ_LEVEL))
+        if (!irqd_is_level_type(d))
                 mtdcr(uic->dcrbase + UIC_SR, sr);
         spin_unlock_irqrestore(&uic->lock, flags);
 }
@@ -129,7 +127,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 {
         struct uic *uic = irq_data_get_irq_chip_data(d);
         unsigned int src = uic_irq_to_hw(d->irq);
-        struct irq_desc *desc = irq_to_desc(d->irq);
         unsigned long flags;
         int trigger, polarity;
         u32 tr, pr, mask;
@@ -166,11 +163,6 @@ static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
         mtdcr(uic->dcrbase + UIC_PR, pr);
         mtdcr(uic->dcrbase + UIC_TR, tr);
 
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
-        if (!trigger)
-                desc->status |= IRQ_LEVEL;
-
         spin_unlock_irqrestore(&uic->lock, flags);
 
         return 0;
@@ -190,13 +182,13 @@ static int uic_host_map(struct irq_host *h, unsigned int virq,
 {
         struct uic *uic = h->host_data;
 
-        set_irq_chip_data(virq, uic);
+        irq_set_chip_data(virq, uic);
         /* Despite the name, handle_level_irq() works for both level
          * and edge irqs on UIC.  FIXME: check this is correct */
-        set_irq_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
+        irq_set_chip_and_handler(virq, &uic_irq_chip, handle_level_irq);
 
         /* Set default irq type */
-        set_irq_type(virq, IRQ_TYPE_NONE);
+        irq_set_irq_type(virq, IRQ_TYPE_NONE);
 
         return 0;
 }
@@ -220,17 +212,18 @@ static struct irq_host_ops uic_host_ops = {
 
 void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
-        struct uic *uic = get_irq_data(virq);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
+        struct irq_data *idata = irq_desc_get_irq_data(desc);
+        struct uic *uic = irq_get_handler_data(virq);
         u32 msr;
         int src;
         int subvirq;
 
         raw_spin_lock(&desc->lock);
-        if (desc->status & IRQ_LEVEL)
-                chip->irq_mask(&desc->irq_data);
+        if (irqd_is_level_type(idata))
+                chip->irq_mask(idata);
         else
-                chip->irq_mask_ack(&desc->irq_data);
+                chip->irq_mask_ack(idata);
         raw_spin_unlock(&desc->lock);
 
         msr = mfdcr(uic->dcrbase + UIC_MSR);
@@ -244,10 +237,10 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
 
 uic_irq_ret:
         raw_spin_lock(&desc->lock);
-        if (desc->status & IRQ_LEVEL)
-                chip->irq_ack(&desc->irq_data);
-        if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
-                chip->irq_unmask(&desc->irq_data);
+        if (irqd_is_level_type(idata))
+                chip->irq_ack(idata);
+        if (!irqd_irq_disabled(idata) && chip->irq_unmask)
+                chip->irq_unmask(idata);
         raw_spin_unlock(&desc->lock);
 }
 
@@ -336,8 +329,8 @@ void __init uic_init_tree(void)
 
                         cascade_virq = irq_of_parse_and_map(np, 0);
 
-                        set_irq_data(cascade_virq, uic);
-                        set_irq_chained_handler(cascade_virq, uic_irq_cascade);
+                        irq_set_handler_data(cascade_virq, uic);
+                        irq_set_chained_handler(cascade_virq, uic_irq_cascade);
 
                         /* FIXME: setup critical cascade?? */
                 }
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index 7436f3ed4df6..0a13fc19e287 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -79,12 +79,6 @@ static void xilinx_intc_mask(struct irq_data *d)
 
 static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
 {
-        struct irq_desc *desc = irq_to_desc(d->irq);
-
-        desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
-        desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
-        if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
-                desc->status |= IRQ_LEVEL;
         return 0;
 }
 
@@ -170,15 +164,15 @@ static int xilinx_intc_xlate(struct irq_host *h, struct device_node *ct,
 static int xilinx_intc_map(struct irq_host *h, unsigned int virq,
                                   irq_hw_number_t irq)
 {
-        set_irq_chip_data(virq, h->host_data);
+        irq_set_chip_data(virq, h->host_data);
 
         if (xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_HIGH ||
             xilinx_intc_typetable[irq] == IRQ_TYPE_LEVEL_LOW) {
-                set_irq_chip_and_handler(virq, &xilinx_intc_level_irqchip,
-                        handle_level_irq);
+                irq_set_chip_and_handler(virq, &xilinx_intc_level_irqchip,
+                                         handle_level_irq);
         } else {
-                set_irq_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
-                        handle_edge_irq);
+                irq_set_chip_and_handler(virq, &xilinx_intc_edge_irqchip,
+                                         handle_edge_irq);
         }
         return 0;
 }
@@ -229,7 +223,7 @@ int xilinx_intc_get_irq(void)
  */
 static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
 {
-        struct irq_chip *chip = get_irq_desc_chip(desc);
+        struct irq_chip *chip = irq_desc_get_chip(desc);
         unsigned int cascade_irq = i8259_irq();
 
         if (cascade_irq)
@@ -256,7 +250,7 @@ static void __init xilinx_i8259_setup_cascade(void)
         }
 
         i8259_init(cascade_node, 0);
-        set_irq_chained_handler(cascade_irq, xilinx_i8259_cascade);
+        irq_set_chained_handler(cascade_irq, xilinx_i8259_cascade);
 
         /* Program irq 7 (usb/audio), 14/15 (ide) to level sensitive */
         /* This looks like a dirty hack to me --gcl */
diff --git a/arch/score/Kconfig b/arch/score/Kconfig
index 27b2295f41f3..4278bbc032ce 100644
--- a/arch/score/Kconfig
+++ b/arch/score/Kconfig
@@ -3,6 +3,8 @@ menu "Machine selection"
 config SCORE
        def_bool y
        select HAVE_GENERIC_HARDIRQS
+       select GENERIC_HARDIRQS_NO_DEPRECATED
+       select GENERIC_IRQ_SHOW
 
 choice
         prompt "System type"
diff --git a/arch/score/include/asm/irqflags.h b/arch/score/include/asm/irqflags.h
index 5c7563891e28..37c6ac9dd6e8 100644
--- a/arch/score/include/asm/irqflags.h
+++ b/arch/score/include/asm/irqflags.h
@@ -29,7 +29,7 @@ static inline unsigned long arch_local_save_flags(void)
 
 static inline unsigned long arch_local_irq_save(void)
 {
-        unsigned long flags
+        unsigned long flags;
 
         asm volatile(
                 "       mfcr    r8, cr0         \n"
diff --git a/arch/score/kernel/irq.c b/arch/score/kernel/irq.c
index 47647dde09ca..d4196732c65e 100644
--- a/arch/score/kernel/irq.c
+++ b/arch/score/kernel/irq.c
@@ -52,9 +52,9 @@ asmlinkage void do_IRQ(int irq)
         irq_exit();
 }
 
-static void score_mask(unsigned int irq_nr)
+static void score_mask(struct irq_data *d)
 {
-        unsigned int irq_source = 63 - irq_nr;
+        unsigned int irq_source = 63 - d->irq;
 
         if (irq_source < 32)
                 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) | \
@@ -64,9 +64,9 @@ static void score_mask(unsigned int irq_nr)
                         (1 << (irq_source - 32))), SCORE_PIC + INT_MASKH);
 }
 
-static void score_unmask(unsigned int irq_nr)
+static void score_unmask(struct irq_data *d)
 {
-        unsigned int irq_source = 63 - irq_nr;
+        unsigned int irq_source = 63 - d->irq;
 
         if (irq_source < 32)
                 __raw_writel((__raw_readl(SCORE_PIC + INT_MASKL) & \
@@ -78,9 +78,9 @@ static void score_unmask(unsigned int irq_nr)
 
 struct irq_chip score_irq_chip = {
         .name           = "Score7-level",
-        .mask           = score_mask,
-        .mask_ack       = score_mask,
-        .unmask         = score_unmask,
+        .irq_mask       = score_mask,
+        .irq_mask_ack   = score_mask,
+        .irq_unmask     = score_unmask,
 };
 
 /*
@@ -92,7 +92,7 @@ void __init init_IRQ(void)
         unsigned long target_addr;
 
         for (index = 0; index < NR_IRQS; ++index)
-                set_irq_chip_and_handler(index, &score_irq_chip,
+                irq_set_chip_and_handler(index, &score_irq_chip,
                                          handle_level_irq);
 
         for (target_addr = IRQ_VECTOR_BASE_ADDR;
@@ -109,40 +109,3 @@ void __init init_IRQ(void)
                 : : "r" (EXCEPTION_VECTOR_BASE_ADDR | \
                         VECTOR_ADDRESS_OFFSET_MODE16));
 }
-
-/*
- * Generic, controller-independent functions:
- */
-int show_interrupts(struct seq_file *p, void *v)
-{
-        int i = *(loff_t *)v, cpu;
-        struct irqaction *action;
-        unsigned long flags;
-
-        if (i == 0) {
-                seq_puts(p, "           ");
-                for_each_online_cpu(cpu)
-                        seq_printf(p, "CPU%d       ", cpu);
-                seq_putc(p, '\n');
-        }
-
-        if (i < NR_IRQS) {
-                spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
-                if (!action)
-                        goto unlock;
-
-                seq_printf(p, "%3d: ", i);
-                seq_printf(p, "%10u ", kstat_irqs(i));
-                seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-");
-                seq_printf(p, "  %s", action->name);
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-unlock:
-                spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        }
-
-        return 0;
-}
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index efba450a0518..93f5039099b7 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -388,12 +388,12 @@ static void __init init_mpr2_IRQ(void)
 {
         plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-5 */
 
-        set_irq_type(32, IRQ_TYPE_LEVEL_LOW);    /* IRQ0 CAN1 */
-        set_irq_type(33, IRQ_TYPE_LEVEL_LOW);    /* IRQ1 CAN2 */
-        set_irq_type(34, IRQ_TYPE_LEVEL_LOW);    /* IRQ2 CAN3 */
-        set_irq_type(35, IRQ_TYPE_LEVEL_LOW);    /* IRQ3 SMSC9115 */
-        set_irq_type(36, IRQ_TYPE_EDGE_RISING);  /* IRQ4 touchscreen */
-        set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
+        irq_set_irq_type(32, IRQ_TYPE_LEVEL_LOW);    /* IRQ0 CAN1 */
+        irq_set_irq_type(33, IRQ_TYPE_LEVEL_LOW);    /* IRQ1 CAN2 */
+        irq_set_irq_type(34, IRQ_TYPE_LEVEL_LOW);    /* IRQ2 CAN3 */
+        irq_set_irq_type(35, IRQ_TYPE_LEVEL_LOW);    /* IRQ3 SMSC9115 */
+        irq_set_irq_type(36, IRQ_TYPE_EDGE_RISING);  /* IRQ4 touchscreen */
+        irq_set_irq_type(37, IRQ_TYPE_EDGE_FALLING); /* IRQ5 touchscreen */
 
         intc_set_priority(32, 13);              /* IRQ0 CAN1 */
         intc_set_priority(33, 13);              /* IRQ0 CAN2 */
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 3e5fc3bbf3ed..636d8318a72a 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -14,8 +14,8 @@
 #include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/sh_flctl.h>
 #include <linux/delay.h>
@@ -423,7 +423,7 @@ static struct resource sdhi0_cn3_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -453,7 +453,7 @@ static struct resource sdhi1_cn7_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0x04cf0000,
-                .end    = 0x04cf01ff,
+                .end    = 0x04cf00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index d7ac5af9d102..311bcebdbd07 100644
--- a/arch/sh/boards/mach-cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -149,8 +149,8 @@ void init_cayman_irq(void)
         }
 
         for (i = 0; i < NR_EXT_IRQS; i++) {
-                set_irq_chip_and_handler(START_EXT_IRQS + i, &cayman_irq_type,
-                                         handle_level_irq);
+                irq_set_chip_and_handler(START_EXT_IRQS + i,
+                                         &cayman_irq_type, handle_level_irq);
         }
 
         /* Setup the SMSC interrupt */
diff --git a/arch/sh/boards/mach-dreamcast/irq.c b/arch/sh/boards/mach-dreamcast/irq.c
index 72e7ac9549da..78cf2ab89d7a 100644
--- a/arch/sh/boards/mach-dreamcast/irq.c
+++ b/arch/sh/boards/mach-dreamcast/irq.c
@@ -161,7 +161,6 @@ void systemasic_irq_init(void)
                         return;
                 }
 
-                set_irq_chip_and_handler(i, &systemasic_int,
-                                         handle_level_irq);
+                irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
         }
 }
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index e44480ce2ea8..fd4ff25f23b2 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -11,9 +11,9 @@
 #include <linux/init.h>
 #include <linux/device.h>
 #include <linux/platform_device.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mmc/host.h>
 #include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/gpio.h>
 #include <linux/interrupt.h>
@@ -464,7 +464,7 @@ static struct i2c_board_info ts_i2c_clients = {
         .irq            = IRQ0,
 };
 
-#ifdef CONFIG_MFD_SH_MOBILE_SDHI
+#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE)
 /* SDHI0 */
 static void sdhi0_set_pwr(struct platform_device *pdev, int state)
 {
@@ -482,7 +482,7 @@ static struct resource sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -522,7 +522,7 @@ static struct resource sdhi1_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0x04cf0000,
-                .end    = 0x04cf01ff,
+                .end    = 0x04cf00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -880,7 +880,7 @@ static struct platform_device *ecovec_devices[] __initdata = {
         &ceu0_device,
         &ceu1_device,
         &keysc_device,
-#ifdef CONFIG_MFD_SH_MOBILE_SDHI
+#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE)
         &sdhi0_device,
 #if !defined(CONFIG_MMC_SH_MMCIF)
         &sdhi1_device,
@@ -1102,7 +1102,7 @@ static int __init arch_setup(void)
 
                 /* enable TouchScreen */
                 i2c_register_board_info(0, &ts_i2c_clients, 1);
-                set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
+                irq_set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW);
         }
 
         /* enable CEU0 */
@@ -1162,7 +1162,7 @@ static int __init arch_setup(void)
         gpio_direction_input(GPIO_PTR5);
         gpio_direction_input(GPIO_PTR6);
 
-#ifdef CONFIG_MFD_SH_MOBILE_SDHI
+#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE)
         /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
         gpio_request(GPIO_FN_SDHI0CD,  NULL);
         gpio_request(GPIO_FN_SDHI0WP,  NULL);
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 7504daaa85da..8b4abbbd1477 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -10,8 +10,8 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/interrupt.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mfd/tmio.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/onenand.h>
@@ -354,7 +354,7 @@ static struct resource kfr2r09_sh_sdhi0_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index c35001fd9032..4fb00369f0e2 100644
--- a/arch/sh/boards/mach-microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
@@ -117,7 +117,7 @@ static struct irq_chip microdev_irq_type = {
 static void __init make_microdev_irq(unsigned int irq)
 {
         disable_irq_nosync(irq);
-        set_irq_chip_and_handler(irq, &microdev_irq_type, handle_level_irq);
+        irq_set_chip_and_handler(irq, &microdev_irq_type, handle_level_irq);
         disable_microdev_irq(irq_get_irq_data(irq));
 }
 
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 03a7ffe729d5..184fde169132 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -12,8 +12,8 @@
 #include <linux/interrupt.h>
 #include <linux/input.h>
 #include <linux/input/sh_keysc.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/mtd/nand.h>
 #include <linux/i2c.h>
@@ -399,7 +399,7 @@ static struct resource sdhi_cn9_resources[] = {
         [0] = {
                 .name   = "SDHI",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c
index 9070d7e60704..0db058e709e9 100644
--- a/arch/sh/boards/mach-se/7206/irq.c
+++ b/arch/sh/boards/mach-se/7206/irq.c
@@ -92,9 +92,8 @@ static void eoi_se7206_irq(struct irq_data *data)
 {
         unsigned short sts0,sts1;
         unsigned int irq = data->irq;
-        struct irq_desc *desc = irq_to_desc(irq);
 
-        if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
+        if (!irqd_irq_disabled(data) && !irqd_irq_inprogress(data))
                 enable_se7206_irq(data);
         /* FPGA isr clear */
         sts0 = __raw_readw(INTSTS0);
@@ -126,7 +125,7 @@ static struct irq_chip se7206_irq_chip __read_mostly = {
 static void make_se7206_irq(unsigned int irq)
 {
         disable_irq_nosync(irq);
-        set_irq_chip_and_handler_name(irq, &se7206_irq_chip,
+        irq_set_chip_and_handler_name(irq, &se7206_irq_chip,
                                       handle_level_irq, "level");
         disable_se7206_irq(irq_get_irq_data(irq));
 }
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
index 76255a19417f..fd45ffc48340 100644
--- a/arch/sh/boards/mach-se/7343/irq.c
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -67,19 +67,20 @@ void __init init_7343se_IRQ(void)
                         return;
                 se7343_fpga_irq[i] = irq;
 
-                set_irq_chip_and_handler_name(se7343_fpga_irq[i],
+                irq_set_chip_and_handler_name(se7343_fpga_irq[i],
                                               &se7343_irq_chip,
-                                              handle_level_irq, "level");
+                                              handle_level_irq,
+                                              "level");
 
-                set_irq_chip_data(se7343_fpga_irq[i], (void *)i);
+                irq_set_chip_data(se7343_fpga_irq[i], (void *)i);
         }
 
-        set_irq_chained_handler(IRQ0_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(IRQ1_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(IRQ4_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
-        set_irq_chained_handler(IRQ5_IRQ, se7343_irq_demux);
-        set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
+        irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index c013f95628ed..aac92f21ebd2 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -67,16 +67,17 @@ void __init init_se7722_IRQ(void)
                         return;
                 se7722_fpga_irq[i] = irq;
 
-                set_irq_chip_and_handler_name(se7722_fpga_irq[i],
+                irq_set_chip_and_handler_name(se7722_fpga_irq[i],
                                               &se7722_irq_chip,
-                                              handle_level_irq, "level");
+                                              handle_level_irq,
+                                              "level");
 
-                set_irq_chip_data(se7722_fpga_irq[i], (void *)i);
+                irq_set_chip_data(se7722_fpga_irq[i], (void *)i);
         }
 
-        set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux);
-        set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
+        irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
 
-        set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux);
-        set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
+        irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
index 5bd87c22b65b..c6342ce7768d 100644
--- a/arch/sh/boards/mach-se/7724/irq.c
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -140,17 +140,16 @@ void __init init_se7724_IRQ(void)
                         return;
                 }
 
-                set_irq_chip_and_handler_name(irq,
-                                              &se7724_irq_chip,
+                irq_set_chip_and_handler_name(irq, &se7724_irq_chip,
                                               handle_level_irq, "level");
         }
 
-        set_irq_chained_handler(IRQ0_IRQ, se7724_irq_demux);
-        set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ0_IRQ, se7724_irq_demux);
+        irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
 
-        set_irq_chained_handler(IRQ1_IRQ, se7724_irq_demux);
-        set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ1_IRQ, se7724_irq_demux);
+        irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
 
-        set_irq_chained_handler(IRQ2_IRQ, se7724_irq_demux);
-        set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(IRQ2_IRQ, se7724_irq_demux);
+        irq_set_irq_type(IRQ2_IRQ, IRQ_TYPE_LEVEL_LOW);
 }
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index c8bcf6a19b55..12357671023e 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -14,8 +14,8 @@
 #include <linux/device.h>
 #include <linux/interrupt.h>
 #include <linux/platform_device.h>
-#include <linux/mfd/sh_mobile_sdhi.h>
 #include <linux/mmc/host.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
 #include <linux/mtd/physmap.h>
 #include <linux/delay.h>
 #include <linux/smc91x.h>
@@ -456,7 +456,7 @@ static struct resource sdhi0_cn7_resources[] = {
         [0] = {
                 .name   = "SDHI0",
                 .start  = 0x04ce0000,
-                .end    = 0x04ce01ff,
+                .end    = 0x04ce00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -488,7 +488,7 @@ static struct resource sdhi1_cn8_resources[] = {
         [0] = {
                 .name   = "SDHI1",
                 .start  = 0x04cf0000,
-                .end    = 0x04cf01ff,
+                .end    = 0x04cf00ff,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/sh/boards/mach-x3proto/gpio.c b/arch/sh/boards/mach-x3proto/gpio.c
index 239e74066253..f33b2b57019c 100644
--- a/arch/sh/boards/mach-x3proto/gpio.c
+++ b/arch/sh/boards/mach-x3proto/gpio.c
@@ -102,8 +102,8 @@ int __init x3proto_gpio_setup(void)
 
                 spin_lock_irqsave(&x3proto_gpio_lock, flags);
                 x3proto_gpio_irq_map[i] = irq;
-                set_irq_chip_and_handler_name(irq, &dummy_irq_chip,
-                                        handle_simple_irq, "gpio");
+                irq_set_chip_and_handler_name(irq, &dummy_irq_chip,
+                                              handle_simple_irq, "gpio");
                 spin_unlock_irqrestore(&x3proto_gpio_lock, flags);
         }
 
@@ -113,8 +113,8 @@ int __init x3proto_gpio_setup(void)
                 x3proto_gpio_chip.base + x3proto_gpio_chip.ngpio,
                 ilsel);
 
-        set_irq_chained_handler(ilsel, x3proto_gpio_irq_handler);
-        set_irq_wake(ilsel, 1);
+        irq_set_chained_handler(ilsel, x3proto_gpio_irq_handler);
+        irq_set_irq_wake(ilsel, 1);
 
         return 0;
 
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index 177a10b25cad..eb4ea4d44d59 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -107,12 +107,12 @@ int __init setup_hd64461(void)
                         return -EINVAL;
                 }
 
-                set_irq_chip_and_handler(i, &hd64461_irq_chip,
+                irq_set_chip_and_handler(i, &hd64461_irq_chip,
                                          handle_level_irq);
         }
 
-        set_irq_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
-        set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
+        irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
+        irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);
 
 #ifdef CONFIG_HD64461_ENABLER
         printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
diff --git a/arch/sh/kernel/cpu/irq/imask.c b/arch/sh/kernel/cpu/irq/imask.c
index 32c825c9488e..39b6a24c159d 100644
--- a/arch/sh/kernel/cpu/irq/imask.c
+++ b/arch/sh/kernel/cpu/irq/imask.c
@@ -80,6 +80,6 @@ static struct irq_chip imask_irq_chip = {
 
 void make_imask_irq(unsigned int irq)
 {
-        set_irq_chip_and_handler_name(irq, &imask_irq_chip,
-                                      handle_level_irq, "level");
+        irq_set_chip_and_handler_name(irq, &imask_irq_chip, handle_level_irq,
+                                      "level");
 }
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 5af48f8357e5..9e056a3a0c73 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -135,7 +135,7 @@ void __init plat_irq_setup(void)
 
         /* Set default: per-line enable/disable, priority driven ack/eoi */
         for (i = 0; i < NR_INTC_IRQS; i++)
-                set_irq_chip_and_handler(i, &intc_irq_type, handle_level_irq);
+                irq_set_chip_and_handler(i, &intc_irq_type, handle_level_irq);
 
 
         /* Disable all interrupts and set all priorities to 0 to avoid trouble */
diff --git a/arch/sh/kernel/cpu/irq/ipr.c b/arch/sh/kernel/cpu/irq/ipr.c
index 7516c35ee514..5de6dff5c21b 100644
--- a/arch/sh/kernel/cpu/irq/ipr.c
+++ b/arch/sh/kernel/cpu/irq/ipr.c
@@ -74,9 +74,9 @@ void register_ipr_controller(struct ipr_desc *desc)
                 }
 
                 disable_irq_nosync(p->irq);
-                set_irq_chip_and_handler_name(p->irq, &desc->chip,
-                                      handle_level_irq, "level");
-                set_irq_chip_data(p->irq, p);
+                irq_set_chip_and_handler_name(p->irq, &desc->chip,
+                                              handle_level_irq, "level");
+                irq_set_chip_data(p->irq, p);
                 disable_ipr_irq(irq_get_irq_data(p->irq));
         }
 }
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index f766e6bf370e..14b234631f5f 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -52,6 +52,8 @@ config SPARC64
         select PERF_USE_VMALLOC
         select HAVE_GENERIC_HARDIRQS
         select GENERIC_HARDIRQS_NO_DEPRECATED
+        select GENERIC_IRQ_SHOW
+        select IRQ_PREFLOW_FASTEOI
 
 config ARCH_DEFCONFIG
         string
diff --git a/arch/sparc/kernel/irq_64.c b/arch/sparc/kernel/irq_64.c
index eb16e3b8a2dd..b1d275ce3435 100644
--- a/arch/sparc/kernel/irq_64.c
+++ b/arch/sparc/kernel/irq_64.c
@@ -162,47 +162,14 @@ void irq_free(unsigned int irq)
 /*
  * /proc/interrupts printing:
  */
-
-int show_interrupts(struct seq_file *p, void *v)
+int arch_show_interrupts(struct seq_file *p, int prec)
 {
-        int i = *(loff_t *) v, j;
-        struct irqaction * action;
-        unsigned long flags;
+        int j;
 
-        if (i == 0) {
-                seq_printf(p, "           ");
-                for_each_online_cpu(j)
-                        seq_printf(p, "CPU%d       ",j);
-                seq_putc(p, '\n');
-        }
-
-        if (i < NR_IRQS) {
-                raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
-                action = irq_desc[i].action;
-                if (!action)
-                        goto skip;
-                seq_printf(p, "%3d: ",i);
-#ifndef CONFIG_SMP
-                seq_printf(p, "%10u ", kstat_irqs(i));
-#else
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-#endif
-                seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name);
-                seq_printf(p, "  %s", action->name);
-
-                for (action=action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-skip:
-                raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
-        } else if (i == NR_IRQS) {
-                seq_printf(p, "NMI: ");
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
-                seq_printf(p, "     Non-maskable interrupts\n");
-        }
+        seq_printf(p, "NMI: ");
+        for_each_online_cpu(j)
+                seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
+        seq_printf(p, "     Non-maskable interrupts\n");
         return 0;
 }
 
@@ -344,10 +311,6 @@ static void sun4u_irq_disable(struct irq_data *data)
 static void sun4u_irq_eoi(struct irq_data *data)
 {
         struct irq_handler_data *handler_data = data->handler_data;
-        struct irq_desc *desc = irq_desc + data->irq;
-
-        if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-                return;
 
         if (likely(handler_data))
                 upa_writeq(ICLR_IDLE, handler_data->iclr);
@@ -402,12 +365,8 @@ static void sun4v_irq_disable(struct irq_data *data)
 static void sun4v_irq_eoi(struct irq_data *data)
 {
         unsigned int ino = irq_table[data->irq].dev_ino;
-        struct irq_desc *desc = irq_desc + data->irq;
         int err;
 
-        if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-                return;
-
         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
         if (err != HV_EOK)
                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
@@ -481,13 +440,9 @@ static void sun4v_virq_disable(struct irq_data *data)
 
 static void sun4v_virq_eoi(struct irq_data *data)
 {
-        struct irq_desc *desc = irq_desc + data->irq;
         unsigned long dev_handle, dev_ino;
         int err;
 
-        if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
-                return;
-
         dev_handle = irq_table[data->irq].dev_handle;
         dev_ino = irq_table[data->irq].dev_ino;
 
@@ -505,6 +460,7 @@ static struct irq_chip sun4u_irq = {
         .irq_disable            = sun4u_irq_disable,
         .irq_eoi                = sun4u_irq_eoi,
         .irq_set_affinity       = sun4u_set_affinity,
+        .flags                  = IRQCHIP_EOI_IF_HANDLED,
 };
 
 static struct irq_chip sun4v_irq = {
@@ -513,6 +469,7 @@ static struct irq_chip sun4v_irq = {
         .irq_disable            = sun4v_irq_disable,
         .irq_eoi                = sun4v_irq_eoi,
         .irq_set_affinity       = sun4v_set_affinity,
+        .flags                  = IRQCHIP_EOI_IF_HANDLED,
 };
 
 static struct irq_chip sun4v_virq = {
@@ -521,30 +478,28 @@ static struct irq_chip sun4v_virq = {
         .irq_disable            = sun4v_virq_disable,
         .irq_eoi                = sun4v_virq_eoi,
         .irq_set_affinity       = sun4v_virt_set_affinity,
+        .flags                  = IRQCHIP_EOI_IF_HANDLED,
 };
 
-static void pre_flow_handler(unsigned int irq, struct irq_desc *desc)
+static void pre_flow_handler(struct irq_data *d)
 {
-        struct irq_handler_data *handler_data = get_irq_data(irq);
-        unsigned int ino = irq_table[irq].dev_ino;
+        struct irq_handler_data *handler_data = irq_data_get_irq_handler_data(d);
+        unsigned int ino = irq_table[d->irq].dev_ino;
 
         handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2);
-
-        handle_fasteoi_irq(irq, desc);
 }
 
 void irq_install_pre_handler(int irq,
                              void (*func)(unsigned int, void *, void *),
                              void *arg1, void *arg2)
 {
-        struct irq_handler_data *handler_data = get_irq_data(irq);
-        struct irq_desc *desc = irq_desc + irq;
+        struct irq_handler_data *handler_data = irq_get_handler_data(irq);
 
         handler_data->pre_handler = func;
         handler_data->arg1 = arg1;
         handler_data->arg2 = arg2;
 
-        desc->handle_irq = pre_flow_handler;
+        __irq_set_preflow_handler(irq, pre_flow_handler);
 }
 
 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
@@ -562,13 +517,11 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
         if (!irq) {
                 irq = irq_alloc(0, ino);
                 bucket_set_irq(__pa(bucket), irq);
-                set_irq_chip_and_handler_name(irq,
-                                              &sun4u_irq,
-                                              handle_fasteoi_irq,
-                                              "IVEC");
+                irq_set_chip_and_handler_name(irq, &sun4u_irq,
+                                              handle_fasteoi_irq, "IVEC");
         }
 
-        handler_data = get_irq_data(irq);
+        handler_data = irq_get_handler_data(irq);
         if (unlikely(handler_data))
                 goto out;
 
@@ -577,7 +530,7 @@ unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
                 prom_halt();
         }
-        set_irq_data(irq, handler_data);
+        irq_set_handler_data(irq, handler_data);
 
         handler_data->imap  = imap;
         handler_data->iclr  = iclr;
@@ -600,12 +553,11 @@ static unsigned int sun4v_build_common(unsigned long sysino,
         if (!irq) {
                 irq = irq_alloc(0, sysino);
                 bucket_set_irq(__pa(bucket), irq);
-                set_irq_chip_and_handler_name(irq, chip,
-                                              handle_fasteoi_irq,
+                irq_set_chip_and_handler_name(irq, chip, handle_fasteoi_irq,
                                               "IVEC");
         }
 
-        handler_data = get_irq_data(irq);
+        handler_data = irq_get_handler_data(irq);
         if (unlikely(handler_data))
                 goto out;
 
@@ -614,7 +566,7 @@ static unsigned int sun4v_build_common(unsigned long sysino,
                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
                 prom_halt();
         }
-        set_irq_data(irq, handler_data);
+        irq_set_handler_data(irq, handler_data);
 
         /* Catch accidental accesses to these things.  IMAP/ICLR handling
          * is done by hypervisor calls on sun4v platforms, not by direct
@@ -639,7 +591,6 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
         struct irq_handler_data *handler_data;
         unsigned long hv_err, cookie;
         struct ino_bucket *bucket;
-        struct irq_desc *desc;
         unsigned int irq;
 
         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
@@ -660,8 +611,7 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
         irq = irq_alloc(devhandle, devino);
         bucket_set_irq(__pa(bucket), irq);
 
-        set_irq_chip_and_handler_name(irq, &sun4v_virq,
-                                      handle_fasteoi_irq,
+        irq_set_chip_and_handler_name(irq, &sun4v_virq, handle_fasteoi_irq,
                                       "IVEC");
 
         handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
@@ -672,10 +622,8 @@ unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
          * especially wrt. locking, we do not let request_irq() enable
          * the interrupt.
          */
-        desc = irq_desc + irq;
-        desc->status |= IRQ_NOAUTOEN;
-
-        set_irq_data(irq, handler_data);
+        irq_set_status_flags(irq, IRQ_NOAUTOEN);
+        irq_set_handler_data(irq, handler_data);
 
         /* Catch accidental accesses to these things.  IMAP/ICLR handling
          * is done by hypervisor calls on sun4v platforms, not by direct
@@ -734,7 +682,6 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs)
         orig_sp = set_hardirq_stack();
 
         while (bucket_pa) {
-                struct irq_desc *desc;
                 unsigned long next_pa;
                 unsigned int irq;
 
@@ -742,10 +689,7 @@ void __irq_entry handler_irq(int pil, struct pt_regs *regs)
                 irq = bucket_get_irq(bucket_pa);
                 bucket_clear_chain_pa(bucket_pa);
 
-                desc = irq_desc + irq;
-
-                if (!(desc->status & IRQ_DISABLED))
-                        desc->handle_irq(irq, desc);
+                generic_handle_irq(irq);
 
                 bucket_pa = next_pa;
         }
@@ -788,19 +732,18 @@ void fixup_irqs(void)
         unsigned int irq;
 
         for (irq = 0; irq < NR_IRQS; irq++) {
+                struct irq_desc *desc = irq_to_desc(irq);
+                struct irq_data *data = irq_desc_get_irq_data(desc);
                 unsigned long flags;
 
-                raw_spin_lock_irqsave(&irq_desc[irq].lock, flags);
-                if (irq_desc[irq].action &&
-                    !(irq_desc[irq].status & IRQ_PER_CPU)) {
-                        struct irq_data *data = irq_get_irq_data(irq);
-
+                raw_spin_lock_irqsave(&desc->lock, flags);
+                if (desc->action && !irqd_is_per_cpu(data)) {
                         if (data->chip->irq_set_affinity)
                                 data->chip->irq_set_affinity(data,
-                                                             data->affinity,
-                                                             false);
+                                                             data->affinity,
+                                                             false);
                 }
-                raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
+                raw_spin_unlock_irqrestore(&desc->lock, flags);
         }
 
         tick_ops->disable_irq();
@@ -1038,5 +981,5 @@ void __init init_IRQ(void)
                              : "i" (PSTATE_IE)
                              : "g1");
 
-        irq_desc[0].action = &timer_irq_action;
+        irq_to_desc(0)->action = &timer_irq_action;
 }
diff --git a/arch/sparc/kernel/pci.c b/arch/sparc/kernel/pci.c
index 44f41e312f73..713dc91020a6 100644
--- a/arch/sparc/kernel/pci.c
+++ b/arch/sparc/kernel/pci.c
@@ -1012,7 +1012,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
 
 void arch_teardown_msi_irq(unsigned int irq)
 {
-        struct msi_desc *entry = get_irq_msi(irq);
+        struct msi_desc *entry = irq_get_msi_desc(irq);
         struct pci_dev *pdev = entry->dev;
         struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
 
diff --git a/arch/sparc/kernel/pci_msi.c b/arch/sparc/kernel/pci_msi.c
index 550e937720e7..30982e9ab626 100644
--- a/arch/sparc/kernel/pci_msi.c
+++ b/arch/sparc/kernel/pci_msi.c
@@ -30,13 +30,10 @@ static irqreturn_t sparc64_msiq_interrupt(int irq, void *cookie)
 
                 err = ops->dequeue_msi(pbm, msiqid, &head, &msi);
                 if (likely(err > 0)) {
-                        struct irq_desc *desc;
                         unsigned int irq;
 
                         irq = pbm->msi_irq_table[msi - pbm->msi_first];
-                        desc = irq_desc + irq;
-
-                        desc->handle_irq(irq, desc);
+                        generic_handle_irq(irq);
                 }
 
                 if (unlikely(err < 0))
@@ -136,8 +133,8 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p,
         if (!*irq_p)
                 goto out_err;
 
-        set_irq_chip_and_handler_name(*irq_p, &msi_irq,
-                                      handle_simple_irq, "MSI");
+        irq_set_chip_and_handler_name(*irq_p, &msi_irq, handle_simple_irq,
+                                      "MSI");
 
         err = alloc_msi(pbm);
         if (unlikely(err < 0))
@@ -163,7 +160,7 @@ static int sparc64_setup_msi_irq(unsigned int *irq_p,
         }
         msg.data = msi;
 
-        set_irq_msi(*irq_p, entry);
+        irq_set_msi_desc(*irq_p, entry);
         write_msi_msg(*irq_p, &msg);
 
         return 0;
@@ -172,7 +169,7 @@ out_msi_free:
         free_msi(pbm, msi);
 
 out_irq_free:
-        set_irq_chip(*irq_p, NULL);
+        irq_set_chip(*irq_p, NULL);
         irq_free(*irq_p);
         *irq_p = 0;
 
@@ -211,7 +208,7 @@ static void sparc64_teardown_msi_irq(unsigned int irq,
 
         free_msi(pbm, msi_num);
 
-        set_irq_chip(irq, NULL);
+        irq_set_chip(irq, NULL);
         irq_free(irq);
 }
 
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index f3b78701c219..5e34a9fee9b3 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -12,6 +12,7 @@ config TILE
         select GENERIC_IRQ_PROBE
         select GENERIC_PENDING_IRQ if SMP
         select GENERIC_HARDIRQS_NO_DEPRECATED
+        select GENERIC_IRQ_SHOW
 
 # FIXME: investigate whether we need/want these options.
 #       select HAVE_IOREMAP_PROT
diff --git a/arch/tile/kernel/irq.c b/arch/tile/kernel/irq.c
index 0baa7580121f..aa0134db2dd6 100644
--- a/arch/tile/kernel/irq.c
+++ b/arch/tile/kernel/irq.c
@@ -241,14 +241,14 @@ void tile_irq_activate(unsigned int irq, int tile_irq_type)
         irq_flow_handler_t handle = handle_level_irq;
         if (tile_irq_type == TILE_IRQ_PERCPU)
                 handle = handle_percpu_irq;
-        set_irq_chip_and_handler(irq, &tile_irq_chip, handle);
+        irq_set_chip_and_handler(irq, &tile_irq_chip, handle);
 
         /*
          * Flag interrupts that are hardware-cleared so that ack()
          * won't clear them.
          */
         if (tile_irq_type == TILE_IRQ_HW_CLEAR)
-                set_irq_chip_data(irq, (void *)IS_HW_CLEARED);
+                irq_set_chip_data(irq, (void *)IS_HW_CLEARED);
 }
 EXPORT_SYMBOL(tile_irq_activate);
 
@@ -262,47 +262,6 @@ void ack_bad_irq(unsigned int irq)
  * Generic, controller-independent functions:
  */
 
-int show_interrupts(struct seq_file *p, void *v)
-{
-        int i = *(loff_t *) v, j;
-        struct irqaction *action;
-        unsigned long flags;
-
-        if (i == 0) {
-                seq_printf(p, "           ");
-                for (j = 0; j < NR_CPUS; j++)
-                        if (cpu_online(j))
-                                seq_printf(p, "CPU%-8d", j);
-                seq_putc(p, '\n');
-        }
-
-        if (i < NR_IRQS) {
-                struct irq_desc *desc = irq_to_desc(i);
-
-                raw_spin_lock_irqsave(&desc->lock, flags);
-                action = desc->action;
-                if (!action)
-                        goto skip;
-                seq_printf(p, "%3d: ", i);
-#ifndef CONFIG_SMP
-                seq_printf(p, "%10u ", kstat_irqs(i));
-#else
-                for_each_online_cpu(j)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
-#endif
-                seq_printf(p, " %14s", get_irq_desc_chip(desc)->name);
-                seq_printf(p, "  %s", action->name);
-
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-skip:
-                raw_spin_unlock_irqrestore(&desc->lock, flags);
-        }
-        return 0;
-}
-
 #if CHIP_HAS_IPI()
 int create_irq(void)
 {
diff --git a/arch/unicore32/Kconfig b/arch/unicore32/Kconfig
index 4a36db45fb3d..04e024919b2b 100644
--- a/arch/unicore32/Kconfig
+++ b/arch/unicore32/Kconfig
@@ -11,6 +11,7 @@ config UNICORE32
         select GENERIC_FIND_FIRST_BIT
         select GENERIC_IRQ_PROBE
         select GENERIC_HARDIRQS_NO_DEPRECATED
+        select GENERIC_IRQ_SHOW
         select ARCH_WANT_FRAME_POINTERS
         help
           UniCore-32 is 32-bit Instruction Set Architecture,
diff --git a/arch/unicore32/kernel/irq.c b/arch/unicore32/kernel/irq.c
index b23624cf3062..2aa30a364bbe 100644
--- a/arch/unicore32/kernel/irq.c
+++ b/arch/unicore32/kernel/irq.c
@@ -321,24 +321,24 @@ void __init init_IRQ(void)
         writel(1, INTC_ICCR);
 
         for (irq = 0; irq < IRQ_GPIOHIGH; irq++) {
-                set_irq_chip(irq, &puv3_low_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip(irq, &puv3_low_gpio_chip);
+                irq_set_handler(irq, handle_edge_irq);
                 irq_modify_status(irq,
                         IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
                         0);
         }
 
         for (irq = IRQ_GPIOHIGH + 1; irq < IRQ_GPIO0; irq++) {
-                set_irq_chip(irq, &puv3_normal_chip);
-                set_irq_handler(irq, handle_level_irq);
+                irq_set_chip(irq, &puv3_normal_chip);
+                irq_set_handler(irq, handle_level_irq);
                 irq_modify_status(irq,
                         IRQ_NOREQUEST | IRQ_NOAUTOEN,
                         IRQ_NOPROBE);
         }
 
         for (irq = IRQ_GPIO0; irq <= IRQ_GPIO27; irq++) {
-                set_irq_chip(irq, &puv3_high_gpio_chip);
-                set_irq_handler(irq, handle_edge_irq);
+                irq_set_chip(irq, &puv3_high_gpio_chip);
+                irq_set_handler(irq, handle_edge_irq);
                 irq_modify_status(irq,
                         IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN,
                         0);
@@ -347,56 +347,14 @@ void __init init_IRQ(void)
         /*
          * Install handler for GPIO 0-27 edge detect interrupts
          */
-        set_irq_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
-        set_irq_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
+        irq_set_chip(IRQ_GPIOHIGH, &puv3_normal_chip);
+        irq_set_chained_handler(IRQ_GPIOHIGH, puv3_gpio_handler);
 
 #ifdef CONFIG_PUV3_GPIO
         puv3_init_gpio();
 #endif
 }
 
-int show_interrupts(struct seq_file *p, void *v)
-{
-        int i = *(loff_t *) v, cpu;
-        struct irq_desc *desc;
-        struct irqaction *action;
-        unsigned long flags;
-
-        if (i == 0) {
-                char cpuname[12];
-
-                seq_printf(p, "    ");
-                for_each_present_cpu(cpu) {
-                        sprintf(cpuname, "CPU%d", cpu);
-                        seq_printf(p, " %10s", cpuname);
-                }
-                seq_putc(p, '\n');
-        }
-
-        if (i < nr_irqs) {
-                desc = irq_to_desc(i);
-                raw_spin_lock_irqsave(&desc->lock, flags);
-                action = desc->action;
-                if (!action)
-                        goto unlock;
-
-                seq_printf(p, "%3d: ", i);
-                for_each_present_cpu(cpu)
-                        seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
-                seq_printf(p, " %10s", desc->irq_data.chip->name ? : "-");
-                seq_printf(p, "  %s", action->name);
-                for (action = action->next; action; action = action->next)
-                        seq_printf(p, ", %s", action->name);
-
-                seq_putc(p, '\n');
-unlock:
-                raw_spin_unlock_irqrestore(&desc->lock, flags);
-        } else if (i == nr_irqs) {
-                seq_printf(p, "Error in interrupt!\n");
-        }
-        return 0;
-}
-
 /*
  * do_IRQ handles all hardware IRQ's.  Decoded IRQs should not
  * come via this function.  Instead, they should provide their
diff --git a/arch/x86/crypto/aesni-intel_asm.S b/arch/x86/crypto/aesni-intel_asm.S
index adcf794b22e2..be6d9e365a80 100644
--- a/arch/x86/crypto/aesni-intel_asm.S
+++ b/arch/x86/crypto/aesni-intel_asm.S
@@ -1612,6 +1612,7 @@ _zero_cipher_left_encrypt:
         movdqa SHUF_MASK(%rip), %xmm10
         PSHUFB_XMM %xmm10, %xmm0
 
+
         ENCRYPT_SINGLE_BLOCK    %xmm0, %xmm1        # Encrypt(K, Yn)
         sub $16, %r11
         add %r13, %r11
@@ -1634,7 +1635,9 @@ _zero_cipher_left_encrypt:
         # GHASH computation for the last <16 byte block
         sub     %r13, %r11
         add     $16, %r11
-        PSHUFB_XMM %xmm10, %xmm1
+
+        movdqa SHUF_MASK(%rip), %xmm10
+        PSHUFB_XMM %xmm10, %xmm0
 
         # shuffle xmm0 back to output as ciphertext
 
diff --git a/arch/x86/crypto/aesni-intel_glue.c b/arch/x86/crypto/aesni-intel_glue.c
index e0e6340c8dad..2577613fb32b 100644
--- a/arch/x86/crypto/aesni-intel_glue.c
+++ b/arch/x86/crypto/aesni-intel_glue.c
@@ -828,9 +828,15 @@ static int rfc4106_init(struct crypto_tfm *tfm)
         struct cryptd_aead *cryptd_tfm;
         struct aesni_rfc4106_gcm_ctx *ctx = (struct aesni_rfc4106_gcm_ctx *)
                 PTR_ALIGN((u8 *)crypto_tfm_ctx(tfm), AESNI_ALIGN);
+        struct crypto_aead *cryptd_child;
+        struct aesni_rfc4106_gcm_ctx *child_ctx;
         cryptd_tfm = cryptd_alloc_aead("__driver-gcm-aes-aesni", 0, 0);
         if (IS_ERR(cryptd_tfm))
                 return PTR_ERR(cryptd_tfm);
+
+        cryptd_child = cryptd_aead_child(cryptd_tfm);
+        child_ctx = aesni_rfc4106_gcm_ctx_get(cryptd_child);
+        memcpy(child_ctx, ctx, sizeof(*ctx));
         ctx->cryptd_tfm = cryptd_tfm;
         tfm->crt_aead.reqsize = sizeof(struct aead_request)
                 + crypto_aead_reqsize(&cryptd_tfm->base);
@@ -923,6 +929,9 @@ static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
         int ret = 0;
         struct crypto_tfm *tfm = crypto_aead_tfm(parent);
         struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(parent);
+        struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
+        struct aesni_rfc4106_gcm_ctx *child_ctx =
+                                 aesni_rfc4106_gcm_ctx_get(cryptd_child);
         u8 *new_key_mem = NULL;
 
         if (key_len < 4) {
@@ -966,6 +975,7 @@ static int rfc4106_set_key(struct crypto_aead *parent, const u8 *key,
                 goto exit;
         }
         ret = rfc4106_set_hash_subkey(ctx->hash_subkey, key, key_len);
+        memcpy(child_ctx, ctx, sizeof(*ctx));
 exit:
         kfree(new_key_mem);
         return ret;
@@ -997,7 +1007,6 @@ static int rfc4106_encrypt(struct aead_request *req)
         int ret;
         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
         struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
-        struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
 
         if (!irq_fpu_usable()) {
                 struct aead_request *cryptd_req =
@@ -1006,6 +1015,7 @@ static int rfc4106_encrypt(struct aead_request *req)
                 aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
                 return crypto_aead_encrypt(cryptd_req);
         } else {
+                struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
                 kernel_fpu_begin();
                 ret = cryptd_child->base.crt_aead.encrypt(req);
                 kernel_fpu_end();
@@ -1018,7 +1028,6 @@ static int rfc4106_decrypt(struct aead_request *req)
         int ret;
         struct crypto_aead *tfm = crypto_aead_reqtfm(req);
         struct aesni_rfc4106_gcm_ctx *ctx = aesni_rfc4106_gcm_ctx_get(tfm);
-        struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
 
         if (!irq_fpu_usable()) {
                 struct aead_request *cryptd_req =
@@ -1027,6 +1036,7 @@ static int rfc4106_decrypt(struct aead_request *req)
                 aead_request_set_tfm(cryptd_req, &ctx->cryptd_tfm->base);
                 return crypto_aead_decrypt(cryptd_req);
         } else {
+                struct crypto_aead *cryptd_child = cryptd_aead_child(ctx->cryptd_tfm);
                 kernel_fpu_begin();
                 ret = cryptd_child->base.crt_aead.decrypt(req);
                 kernel_fpu_end();
diff --git a/arch/x86/xen/p2m.c b/arch/x86/xen/p2m.c
index 215a3ce61068..141eb0de8b06 100644
--- a/arch/x86/xen/p2m.c
+++ b/arch/x86/xen/p2m.c
@@ -497,7 +497,7 @@ static bool alloc_p2m(unsigned long pfn)
         return true;
 }
 
-bool __early_alloc_p2m(unsigned long pfn)
+static bool __init __early_alloc_p2m(unsigned long pfn)
 {
         unsigned topidx, mididx, idx;
 
@@ -530,7 +530,7 @@ bool __early_alloc_p2m(unsigned long pfn)
         }
         return idx != 0;
 }
-unsigned long set_phys_range_identity(unsigned long pfn_s,
+unsigned long __init set_phys_range_identity(unsigned long pfn_s,
                                       unsigned long pfn_e)
 {
         unsigned long pfn;
@@ -671,7 +671,9 @@ int m2p_add_override(unsigned long mfn, struct page *page)
         page->private = mfn;
         page->index = pfn_to_mfn(pfn);
 
-        __set_phys_to_machine(pfn, FOREIGN_FRAME(mfn));
+        if (unlikely(!set_phys_to_machine(pfn, FOREIGN_FRAME(mfn))))
+                return -ENOMEM;
+
         if (!PageHighMem(page))
                 /* Just zap old mapping for now */
                 pte_clear(&init_mm, address, ptep);
@@ -709,7 +711,7 @@ int m2p_remove_override(struct page *page)
         spin_lock_irqsave(&m2p_override_lock, flags);
         list_del(&page->lru);
         spin_unlock_irqrestore(&m2p_override_lock, flags);
-        __set_phys_to_machine(pfn, page->index);
+        set_phys_to_machine(pfn, page->index);
 
         if (!PageHighMem(page))
                 set_pte_at(&init_mm, address, ptep,