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authorLinus Torvalds <torvalds@linux-foundation.org>2010-10-25 10:44:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2010-10-25 10:44:27 -0400
commit4b37ba90f49d4157ac5628f8d730d3505f176724 (patch)
treefdb3d04426f7b72ee86b1f06be746624494493c5 /arch
parent229aebb873e29726b91e076161649cf45154b0bf (diff)
parent55f411de484a0136a77d050e877578a60bc2e094 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (21 commits) m68knommu: convert to using tracehook_report_syscall_* m68knommu: some boards use fixed phy for FEC ethernet m68knommu: support the external GPIO based interrupts of the 5272 m68knommu: mask of vector bits in exception word properly m68knommu: change to new flag variables m68knommu: Fix MCFUART_TXFIFOSIZE for m548x. m68knommu: add basic mmu-less m548x support m68knommu: .gitignore vmlinux.lds m68knommu: stop using __do_IRQ m68knommu: rename PT_OFF_VECTOR to PT_OFF_FORMATVEC. m68knommu: add support for Coldfire 547x/548x interrupt controller m68k{nommu}: Remove unused DEFINE's from asm-offsets.c m68knommu: whitespace cleanup in 68328/entry.S m68knommu: Document supported chips in intc-2.c and intc-simr.c. m68knommu: fix strace support for 68328/68360 m68knommu: fix default starting date arch/m68knommu: Removing dead 68328_SERIAL_UART2 config option arch/m68knommu: Removing dead RAM_{16,32}_MB config option arch/m68knommu: Removing dead M68KFPU_EMU config option arch/m68knommu: Removing dead RELOCATE config option ...
Diffstat (limited to 'arch')
-rw-r--r--arch/m68k/include/asm/cacheflush_no.h2
-rw-r--r--arch/m68k/include/asm/coldfire.h4
-rw-r--r--arch/m68k/include/asm/gpio.h7
-rw-r--r--arch/m68k/include/asm/m548xgpt.h88
-rw-r--r--arch/m68k/include/asm/m548xsim.h55
-rw-r--r--arch/m68k/include/asm/mcfcache.h2
-rw-r--r--arch/m68k/include/asm/mcfsim.h2
-rw-r--r--arch/m68k/include/asm/mcfslt.h44
-rw-r--r--arch/m68k/include/asm/mcfuart.h9
-rw-r--r--arch/m68k/kernel/asm-offsets.c12
-rw-r--r--arch/m68knommu/Kconfig11
-rw-r--r--arch/m68knommu/Makefile3
-rw-r--r--arch/m68knommu/kernel/.gitignore1
-rw-r--r--arch/m68knommu/kernel/asm-offsets.c11
-rw-r--r--arch/m68knommu/kernel/ptrace.c47
-rw-r--r--arch/m68knommu/kernel/setup.c3
-rw-r--r--arch/m68knommu/kernel/time.c13
-rw-r--r--arch/m68knommu/kernel/traps.c26
-rw-r--r--arch/m68knommu/platform/5206/Makefile4
-rw-r--r--arch/m68knommu/platform/5206e/Makefile4
-rw-r--r--arch/m68knommu/platform/520x/Makefile4
-rw-r--r--arch/m68knommu/platform/523x/Makefile4
-rw-r--r--arch/m68knommu/platform/5249/Makefile4
-rw-r--r--arch/m68knommu/platform/5272/Makefile4
-rw-r--r--arch/m68knommu/platform/5272/config.c16
-rw-r--r--arch/m68knommu/platform/5272/intc.c60
-rw-r--r--arch/m68knommu/platform/527x/Makefile4
-rw-r--r--arch/m68knommu/platform/528x/Makefile4
-rw-r--r--arch/m68knommu/platform/5307/Makefile4
-rw-r--r--arch/m68knommu/platform/532x/Makefile4
-rw-r--r--arch/m68knommu/platform/5407/Makefile4
-rw-r--r--arch/m68knommu/platform/548x/Makefile18
-rw-r--r--arch/m68knommu/platform/548x/config.c115
-rw-r--r--arch/m68knommu/platform/68328/entry.S36
-rw-r--r--arch/m68knommu/platform/68328/head-de2.S6
-rw-r--r--arch/m68knommu/platform/68328/head-ram.S27
-rw-r--r--arch/m68knommu/platform/68328/ints.c6
-rw-r--r--arch/m68knommu/platform/68360/entry.S13
-rw-r--r--arch/m68knommu/platform/68360/ints.c6
-rw-r--r--arch/m68knommu/platform/68VZ328/config.c5
-rw-r--r--arch/m68knommu/platform/coldfire/Makefile5
-rw-r--r--arch/m68knommu/platform/coldfire/entry.S4
-rw-r--r--arch/m68knommu/platform/coldfire/intc-2.c53
-rw-r--r--arch/m68knommu/platform/coldfire/intc-simr.c10
-rw-r--r--arch/m68knommu/platform/coldfire/intc.c8
-rw-r--r--arch/m68knommu/platform/coldfire/sltimers.c145
46 files changed, 707 insertions, 210 deletions
diff --git a/arch/m68k/include/asm/cacheflush_no.h b/arch/m68k/include/asm/cacheflush_no.h
index 89f195656be7..7085bd51668b 100644
--- a/arch/m68k/include/asm/cacheflush_no.h
+++ b/arch/m68k/include/asm/cacheflush_no.h
@@ -29,7 +29,7 @@
29 29
30static inline void __flush_cache_all(void) 30static inline void __flush_cache_all(void)
31{ 31{
32#ifdef CONFIG_M5407 32#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
33 /* 33 /*
34 * Use cpushl to push and invalidate all cache lines. 34 * Use cpushl to push and invalidate all cache lines.
35 * Gas doesn't seem to know how to generate the ColdFire 35 * Gas doesn't seem to know how to generate the ColdFire
diff --git a/arch/m68k/include/asm/coldfire.h b/arch/m68k/include/asm/coldfire.h
index 83a9fa4e618a..3b0a34d0fe33 100644
--- a/arch/m68k/include/asm/coldfire.h
+++ b/arch/m68k/include/asm/coldfire.h
@@ -32,7 +32,9 @@
32 */ 32 */
33#define MCF_MBAR 0x10000000 33#define MCF_MBAR 0x10000000
34#define MCF_MBAR2 0x80000000 34#define MCF_MBAR2 0x80000000
35#if defined(CONFIG_M520x) 35#if defined(CONFIG_M548x)
36#define MCF_IPSBAR MCF_MBAR
37#elif defined(CONFIG_M520x)
36#define MCF_IPSBAR 0xFC000000 38#define MCF_IPSBAR 0xFC000000
37#else 39#else
38#define MCF_IPSBAR 0x40000000 40#define MCF_IPSBAR 0x40000000
diff --git a/arch/m68k/include/asm/gpio.h b/arch/m68k/include/asm/gpio.h
index 283214dc65a7..1b57adbafad5 100644
--- a/arch/m68k/include/asm/gpio.h
+++ b/arch/m68k/include/asm/gpio.h
@@ -36,7 +36,8 @@
36 */ 36 */
37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \ 37#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \ 38 defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || defined(CONFIG_M532x) 39 defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
40 defined(CONFIG_M532x) || defined(CONFIG_M548x)
40 41
41/* These parts have GPIO organized by 8 bit ports */ 42/* These parts have GPIO organized by 8 bit ports */
42 43
@@ -136,6 +137,8 @@ static inline u32 __mcf_gpio_ppdr(unsigned gpio)
136#endif 137#endif
137 else 138 else
138 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 139 return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
140#else
141 return 0;
139#endif 142#endif
140} 143}
141 144
@@ -173,6 +176,8 @@ static inline u32 __mcf_gpio_podr(unsigned gpio)
173#endif 176#endif
174 else 177 else
175 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START); 178 return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
179#else
180 return 0;
176#endif 181#endif
177} 182}
178 183
diff --git a/arch/m68k/include/asm/m548xgpt.h b/arch/m68k/include/asm/m548xgpt.h
new file mode 100644
index 000000000000..c8ef158a1c4e
--- /dev/null
+++ b/arch/m68k/include/asm/m548xgpt.h
@@ -0,0 +1,88 @@
1/*
2 * File: m548xgpt.h
3 * Purpose: Register and bit definitions for the MCF548X
4 *
5 * Notes:
6 *
7 */
8
9#ifndef m548xgpt_h
10#define m548xgpt_h
11
12/*********************************************************************
13*
14* General Purpose Timers (GPT)
15*
16*********************************************************************/
17
18/* Register read/write macros */
19#define MCF_GPT_GMS0 0x000800
20#define MCF_GPT_GCIR0 0x000804
21#define MCF_GPT_GPWM0 0x000808
22#define MCF_GPT_GSR0 0x00080C
23#define MCF_GPT_GMS1 0x000810
24#define MCF_GPT_GCIR1 0x000814
25#define MCF_GPT_GPWM1 0x000818
26#define MCF_GPT_GSR1 0x00081C
27#define MCF_GPT_GMS2 0x000820
28#define MCF_GPT_GCIR2 0x000824
29#define MCF_GPT_GPWM2 0x000828
30#define MCF_GPT_GSR2 0x00082C
31#define MCF_GPT_GMS3 0x000830
32#define MCF_GPT_GCIR3 0x000834
33#define MCF_GPT_GPWM3 0x000838
34#define MCF_GPT_GSR3 0x00083C
35#define MCF_GPT_GMS(x) (0x000800+((x)*0x010))
36#define MCF_GPT_GCIR(x) (0x000804+((x)*0x010))
37#define MCF_GPT_GPWM(x) (0x000808+((x)*0x010))
38#define MCF_GPT_GSR(x) (0x00080C+((x)*0x010))
39
40/* Bit definitions and macros for MCF_GPT_GMS */
41#define MCF_GPT_GMS_TMS(x) (((x)&0x00000007)<<0)
42#define MCF_GPT_GMS_GPIO(x) (((x)&0x00000003)<<4)
43#define MCF_GPT_GMS_IEN (0x00000100)
44#define MCF_GPT_GMS_OD (0x00000200)
45#define MCF_GPT_GMS_SC (0x00000400)
46#define MCF_GPT_GMS_CE (0x00001000)
47#define MCF_GPT_GMS_WDEN (0x00008000)
48#define MCF_GPT_GMS_ICT(x) (((x)&0x00000003)<<16)
49#define MCF_GPT_GMS_OCT(x) (((x)&0x00000003)<<20)
50#define MCF_GPT_GMS_OCPW(x) (((x)&0x000000FF)<<24)
51#define MCF_GPT_GMS_OCT_FRCLOW (0x00000000)
52#define MCF_GPT_GMS_OCT_PULSEHI (0x00100000)
53#define MCF_GPT_GMS_OCT_PULSELO (0x00200000)
54#define MCF_GPT_GMS_OCT_TOGGLE (0x00300000)
55#define MCF_GPT_GMS_ICT_ANY (0x00000000)
56#define MCF_GPT_GMS_ICT_RISE (0x00010000)
57#define MCF_GPT_GMS_ICT_FALL (0x00020000)
58#define MCF_GPT_GMS_ICT_PULSE (0x00030000)
59#define MCF_GPT_GMS_GPIO_INPUT (0x00000000)
60#define MCF_GPT_GMS_GPIO_OUTLO (0x00000020)
61#define MCF_GPT_GMS_GPIO_OUTHI (0x00000030)
62#define MCF_GPT_GMS_TMS_DISABLE (0x00000000)
63#define MCF_GPT_GMS_TMS_INCAPT (0x00000001)
64#define MCF_GPT_GMS_TMS_OUTCAPT (0x00000002)
65#define MCF_GPT_GMS_TMS_PWM (0x00000003)
66#define MCF_GPT_GMS_TMS_GPIO (0x00000004)
67
68/* Bit definitions and macros for MCF_GPT_GCIR */
69#define MCF_GPT_GCIR_CNT(x) (((x)&0x0000FFFF)<<0)
70#define MCF_GPT_GCIR_PRE(x) (((x)&0x0000FFFF)<<16)
71
72/* Bit definitions and macros for MCF_GPT_GPWM */
73#define MCF_GPT_GPWM_LOAD (0x00000001)
74#define MCF_GPT_GPWM_PWMOP (0x00000100)
75#define MCF_GPT_GPWM_WIDTH(x) (((x)&0x0000FFFF)<<16)
76
77/* Bit definitions and macros for MCF_GPT_GSR */
78#define MCF_GPT_GSR_CAPT (0x00000001)
79#define MCF_GPT_GSR_COMP (0x00000002)
80#define MCF_GPT_GSR_PWMP (0x00000004)
81#define MCF_GPT_GSR_TEXP (0x00000008)
82#define MCF_GPT_GSR_PIN (0x00000100)
83#define MCF_GPT_GSR_OVF(x) (((x)&0x00000007)<<12)
84#define MCF_GPT_GSR_CAPTURE(x) (((x)&0x0000FFFF)<<16)
85
86/********************************************************************/
87
88#endif /* m548xgpt_h */
diff --git a/arch/m68k/include/asm/m548xsim.h b/arch/m68k/include/asm/m548xsim.h
new file mode 100644
index 000000000000..149135ef30d2
--- /dev/null
+++ b/arch/m68k/include/asm/m548xsim.h
@@ -0,0 +1,55 @@
1/*
2 * m548xsim.h -- ColdFire 547x/548x System Integration Unit support.
3 */
4
5#ifndef m548xsim_h
6#define m548xsim_h
7
8#define MCFINT_VECBASE 64
9
10/*
11 * Interrupt Controller Registers
12 */
13#define MCFICM_INTC0 0x0700 /* Base for Interrupt Ctrl 0 */
14#define MCFINTC_IPRH 0x00 /* Interrupt pending 32-63 */
15#define MCFINTC_IPRL 0x04 /* Interrupt pending 1-31 */
16#define MCFINTC_IMRH 0x08 /* Interrupt mask 32-63 */
17#define MCFINTC_IMRL 0x0c /* Interrupt mask 1-31 */
18#define MCFINTC_INTFRCH 0x10 /* Interrupt force 32-63 */
19#define MCFINTC_INTFRCL 0x14 /* Interrupt force 1-31 */
20#define MCFINTC_IRLR 0x18 /* */
21#define MCFINTC_IACKL 0x19 /* */
22#define MCFINTC_ICR0 0x40 /* Base ICR register */
23
24/*
25 * Define system peripheral IRQ usage.
26 */
27#define MCF_IRQ_TIMER (64 + 54) /* Slice Timer 0 */
28#define MCF_IRQ_PROFILER (64 + 53) /* Slice Timer 1 */
29
30/*
31 * Generic GPIO support
32 */
33#define MCFGPIO_PIN_MAX 0 /* I am too lazy to count */
34#define MCFGPIO_IRQ_MAX -1
35#define MCFGPIO_IRQ_VECBASE -1
36
37/*
38 * Some PSC related definitions
39 */
40#define MCF_PAR_PSC(x) (0x000A4F-((x)&0x3))
41#define MCF_PAR_SDA (0x0008)
42#define MCF_PAR_SCL (0x0004)
43#define MCF_PAR_PSC_TXD (0x04)
44#define MCF_PAR_PSC_RXD (0x08)
45#define MCF_PAR_PSC_RTS(x) (((x)&0x03)<<4)
46#define MCF_PAR_PSC_CTS(x) (((x)&0x03)<<6)
47#define MCF_PAR_PSC_CTS_GPIO (0x00)
48#define MCF_PAR_PSC_CTS_BCLK (0x80)
49#define MCF_PAR_PSC_CTS_CTS (0xC0)
50#define MCF_PAR_PSC_RTS_GPIO (0x00)
51#define MCF_PAR_PSC_RTS_FSYNC (0x20)
52#define MCF_PAR_PSC_RTS_RTS (0x30)
53#define MCF_PAR_PSC_CANRX (0x40)
54
55#endif /* m548xsim_h */
diff --git a/arch/m68k/include/asm/mcfcache.h b/arch/m68k/include/asm/mcfcache.h
index c042634fadaa..f49dfc09f70a 100644
--- a/arch/m68k/include/asm/mcfcache.h
+++ b/arch/m68k/include/asm/mcfcache.h
@@ -107,7 +107,7 @@
107.endm 107.endm
108#endif /* CONFIG_M532x */ 108#endif /* CONFIG_M532x */
109 109
110#if defined(CONFIG_M5407) 110#if defined(CONFIG_M5407) || defined(CONFIG_M548x)
111/* 111/*
112 * Version 4 cores have a true harvard style separate instruction 112 * Version 4 cores have a true harvard style separate instruction
113 * and data cache. Invalidate and enable cache, also enable write 113 * and data cache. Invalidate and enable cache, also enable write
diff --git a/arch/m68k/include/asm/mcfsim.h b/arch/m68k/include/asm/mcfsim.h
index 9c70a67bf85f..6901fd68165b 100644
--- a/arch/m68k/include/asm/mcfsim.h
+++ b/arch/m68k/include/asm/mcfsim.h
@@ -41,6 +41,8 @@
41#elif defined(CONFIG_M5407) 41#elif defined(CONFIG_M5407)
42#include <asm/m5407sim.h> 42#include <asm/m5407sim.h>
43#include <asm/mcfintc.h> 43#include <asm/mcfintc.h>
44#elif defined(CONFIG_M548x)
45#include <asm/m548xsim.h>
44#endif 46#endif
45 47
46/****************************************************************************/ 48/****************************************************************************/
diff --git a/arch/m68k/include/asm/mcfslt.h b/arch/m68k/include/asm/mcfslt.h
new file mode 100644
index 000000000000..d0d0ecba5333
--- /dev/null
+++ b/arch/m68k/include/asm/mcfslt.h
@@ -0,0 +1,44 @@
1/****************************************************************************/
2
3/*
4 * mcfslt.h -- ColdFire internal Slice (SLT) timer support defines.
5 *
6 * (C) Copyright 2004, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2009, Philippe De Muyter (phdm@macqel.be)
8 */
9
10/****************************************************************************/
11#ifndef mcfslt_h
12#define mcfslt_h
13/****************************************************************************/
14
15/*
16 * Get address specific defines for the 547x.
17 */
18#define MCFSLT_TIMER0 0x900 /* Base address of TIMER0 */
19#define MCFSLT_TIMER1 0x910 /* Base address of TIMER1 */
20
21
22/*
23 * Define the SLT timer register set addresses.
24 */
25#define MCFSLT_STCNT 0x00 /* Terminal count */
26#define MCFSLT_SCR 0x04 /* Control */
27#define MCFSLT_SCNT 0x08 /* Current count */
28#define MCFSLT_SSR 0x0C /* Status */
29
30/*
31 * Bit definitions for the SCR control register.
32 */
33#define MCFSLT_SCR_RUN 0x04000000 /* Run mode (continuous) */
34#define MCFSLT_SCR_IEN 0x02000000 /* Interrupt enable */
35#define MCFSLT_SCR_TEN 0x01000000 /* Timer enable */
36
37/*
38 * Bit definitions for the SSR status register.
39 */
40#define MCFSLT_SSR_BE 0x02000000 /* Bus error condition */
41#define MCFSLT_SSR_TE 0x01000000 /* Timeout condition */
42
43/****************************************************************************/
44#endif /* mcfslt_h */
diff --git a/arch/m68k/include/asm/mcfuart.h b/arch/m68k/include/asm/mcfuart.h
index 01a8716c5fc5..db72e2b889ca 100644
--- a/arch/m68k/include/asm/mcfuart.h
+++ b/arch/m68k/include/asm/mcfuart.h
@@ -47,6 +47,11 @@
47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */ 47#define MCFUART_BASE1 0xfc060000 /* Base address of UART1 */
48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */ 48#define MCFUART_BASE2 0xfc064000 /* Base address of UART2 */
49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */ 49#define MCFUART_BASE3 0xfc068000 /* Base address of UART3 */
50#elif defined(CONFIG_M548x)
51#define MCFUART_BASE1 0x8600 /* on M548x */
52#define MCFUART_BASE2 0x8700 /* on M548x */
53#define MCFUART_BASE3 0x8800 /* on M548x */
54#define MCFUART_BASE4 0x8900 /* on M548x */
50#endif 55#endif
51 56
52 57
@@ -212,7 +217,9 @@ struct mcf_platform_uart {
212#define MCFUART_URF_RXS 0xc0 /* Receiver status */ 217#define MCFUART_URF_RXS 0xc0 /* Receiver status */
213#endif 218#endif
214 219
215#if defined(CONFIG_M5272) 220#if defined(CONFIG_M548x)
221#define MCFUART_TXFIFOSIZE 512
222#elif defined(CONFIG_M5272)
216#define MCFUART_TXFIFOSIZE 25 223#define MCFUART_TXFIFOSIZE 25
217#else 224#else
218#define MCFUART_TXFIFOSIZE 1 225#define MCFUART_TXFIFOSIZE 1
diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c
index 73e5e581245b..78e59b82ebc3 100644
--- a/arch/m68k/kernel/asm-offsets.c
+++ b/arch/m68k/kernel/asm-offsets.c
@@ -22,13 +22,9 @@
22int main(void) 22int main(void)
23{ 23{
24 /* offsets into the task struct */ 24 /* offsets into the task struct */
25 DEFINE(TASK_STATE, offsetof(struct task_struct, state));
26 DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
27 DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
28 DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); 25 DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
29 DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info)); 26 DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
30 DEFINE(TASK_MM, offsetof(struct task_struct, mm)); 27 DEFINE(TASK_MM, offsetof(struct task_struct, mm));
31 DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
32#ifdef CONFIG_MMU 28#ifdef CONFIG_MMU
33 DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info)); 29 DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
34#endif 30#endif
@@ -64,14 +60,6 @@ int main(void)
64 /* bitfields are a bit difficult */ 60 /* bitfields are a bit difficult */
65 DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4); 61 DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
66 62
67 /* offsets into the irq_handler struct */
68 DEFINE(IRQ_HANDLER, offsetof(struct irq_node, handler));
69 DEFINE(IRQ_DEVID, offsetof(struct irq_node, dev_id));
70 DEFINE(IRQ_NEXT, offsetof(struct irq_node, next));
71
72 /* offsets into the kernel_stat struct */
73 DEFINE(STAT_IRQ, offsetof(struct kernel_stat, irqs));
74
75 /* offsets into the irq_cpustat_t struct */ 63 /* offsets into the irq_cpustat_t struct */
76 DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); 64 DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
77 65
diff --git a/arch/m68knommu/Kconfig b/arch/m68knommu/Kconfig
index 2609c394e1df..9287150e5fb0 100644
--- a/arch/m68knommu/Kconfig
+++ b/arch/m68knommu/Kconfig
@@ -59,6 +59,10 @@ config GENERIC_HARDIRQS
59 bool 59 bool
60 default y 60 default y
61 61
62config GENERIC_HARDIRQS_NO__DO_IRQ
63 bool
64 default y
65
62config GENERIC_CALIBRATE_DELAY 66config GENERIC_CALIBRATE_DELAY
63 bool 67 bool
64 default y 68 default y
@@ -171,6 +175,11 @@ config M5407
171 help 175 help
172 Motorola ColdFire 5407 processor support. 176 Motorola ColdFire 5407 processor support.
173 177
178config M548x
179 bool "MCF548x"
180 help
181 Freescale ColdFire 5480/5481/5482/5483/5484/5485 processor support.
182
174endchoice 183endchoice
175 184
176config M527x 185config M527x
@@ -181,7 +190,7 @@ config M527x
181 190
182config COLDFIRE 191config COLDFIRE
183 bool 192 bool
184 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407) 193 depends on (M5206 || M5206e || M520x || M523x || M5249 || M527x || M5272 || M528x || M5307 || M532x || M5407 || M548x)
185 select GENERIC_GPIO 194 select GENERIC_GPIO
186 select ARCH_REQUIRE_GPIOLIB 195 select ARCH_REQUIRE_GPIOLIB
187 default y 196 default y
diff --git a/arch/m68knommu/Makefile b/arch/m68knommu/Makefile
index 14042574ac21..026ef16fa68e 100644
--- a/arch/m68knommu/Makefile
+++ b/arch/m68knommu/Makefile
@@ -25,6 +25,7 @@ platform-$(CONFIG_M528x) := 528x
25platform-$(CONFIG_M5307) := 5307 25platform-$(CONFIG_M5307) := 5307
26platform-$(CONFIG_M532x) := 532x 26platform-$(CONFIG_M532x) := 532x
27platform-$(CONFIG_M5407) := 5407 27platform-$(CONFIG_M5407) := 5407
28platform-$(CONFIG_M548x) := 548x
28PLATFORM := $(platform-y) 29PLATFORM := $(platform-y)
29 30
30board-$(CONFIG_PILOT) := pilot 31board-$(CONFIG_PILOT) := pilot
@@ -73,6 +74,7 @@ cpuclass-$(CONFIG_M528x) := coldfire
73cpuclass-$(CONFIG_M5307) := coldfire 74cpuclass-$(CONFIG_M5307) := coldfire
74cpuclass-$(CONFIG_M532x) := coldfire 75cpuclass-$(CONFIG_M532x) := coldfire
75cpuclass-$(CONFIG_M5407) := coldfire 76cpuclass-$(CONFIG_M5407) := coldfire
77cpuclass-$(CONFIG_M548x) := coldfire
76cpuclass-$(CONFIG_M68328) := 68328 78cpuclass-$(CONFIG_M68328) := 68328
77cpuclass-$(CONFIG_M68EZ328) := 68328 79cpuclass-$(CONFIG_M68EZ328) := 68328
78cpuclass-$(CONFIG_M68VZ328) := 68328 80cpuclass-$(CONFIG_M68VZ328) := 68328
@@ -100,6 +102,7 @@ cflags-$(CONFIG_M528x) := $(call cc-option,-m528x,-m5307)
100cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200) 102cflags-$(CONFIG_M5307) := $(call cc-option,-m5307,-m5200)
101cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307) 103cflags-$(CONFIG_M532x) := $(call cc-option,-mcpu=532x,-m5307)
102cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200) 104cflags-$(CONFIG_M5407) := $(call cc-option,-m5407,-m5200)
105cflags-$(CONFIG_M548x) := $(call cc-option,-m5407,-m5200)
103cflags-$(CONFIG_M68328) := -m68000 106cflags-$(CONFIG_M68328) := -m68000
104cflags-$(CONFIG_M68EZ328) := -m68000 107cflags-$(CONFIG_M68EZ328) := -m68000
105cflags-$(CONFIG_M68VZ328) := -m68000 108cflags-$(CONFIG_M68VZ328) := -m68000
diff --git a/arch/m68knommu/kernel/.gitignore b/arch/m68knommu/kernel/.gitignore
new file mode 100644
index 000000000000..c5f676c3c224
--- /dev/null
+++ b/arch/m68knommu/kernel/.gitignore
@@ -0,0 +1 @@
vmlinux.lds
diff --git a/arch/m68knommu/kernel/asm-offsets.c b/arch/m68knommu/kernel/asm-offsets.c
index 24335022fa2c..ffe02f41ad46 100644
--- a/arch/m68knommu/kernel/asm-offsets.c
+++ b/arch/m68knommu/kernel/asm-offsets.c
@@ -21,14 +21,8 @@
21int main(void) 21int main(void)
22{ 22{
23 /* offsets into the task struct */ 23 /* offsets into the task struct */
24 DEFINE(TASK_STATE, offsetof(struct task_struct, state));
25 DEFINE(TASK_FLAGS, offsetof(struct task_struct, flags));
26 DEFINE(TASK_PTRACE, offsetof(struct task_struct, ptrace));
27 DEFINE(TASK_BLOCKED, offsetof(struct task_struct, blocked));
28 DEFINE(TASK_THREAD, offsetof(struct task_struct, thread)); 24 DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
29 DEFINE(TASK_THREAD_INFO, offsetof(struct task_struct, stack));
30 DEFINE(TASK_MM, offsetof(struct task_struct, mm)); 25 DEFINE(TASK_MM, offsetof(struct task_struct, mm));
31 DEFINE(TASK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
32 26
33 /* offsets into the irq_cpustat_t struct */ 27 /* offsets into the irq_cpustat_t struct */
34 DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending)); 28 DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
@@ -63,7 +57,7 @@ int main(void)
63 DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2); 57 DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
64#else 58#else
65 /* bitfields are a bit difficult */ 59 /* bitfields are a bit difficult */
66 DEFINE(PT_OFF_VECTOR, offsetof(struct pt_regs, pc) + 4); 60 DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
67#endif 61#endif
68 62
69 /* signal defines */ 63 /* signal defines */
@@ -75,11 +69,8 @@ int main(void)
75 DEFINE(PT_PTRACED, PT_PTRACED); 69 DEFINE(PT_PTRACED, PT_PTRACED);
76 70
77 /* Offsets in thread_info structure */ 71 /* Offsets in thread_info structure */
78 DEFINE(TI_TASK, offsetof(struct thread_info, task));
79 DEFINE(TI_EXECDOMAIN, offsetof(struct thread_info, exec_domain));
80 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags)); 72 DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
81 DEFINE(TI_PREEMPTCOUNT, offsetof(struct thread_info, preempt_count)); 73 DEFINE(TI_PREEMPTCOUNT, offsetof(struct thread_info, preempt_count));
82 DEFINE(TI_CPU, offsetof(struct thread_info, cpu));
83 74
84 return 0; 75 return 0;
85} 76}
diff --git a/arch/m68knommu/kernel/ptrace.c b/arch/m68knommu/kernel/ptrace.c
index f6be1248d216..6fe7c38cd556 100644
--- a/arch/m68knommu/kernel/ptrace.c
+++ b/arch/m68knommu/kernel/ptrace.c
@@ -18,6 +18,7 @@
18#include <linux/ptrace.h> 18#include <linux/ptrace.h>
19#include <linux/user.h> 19#include <linux/user.h>
20#include <linux/signal.h> 20#include <linux/signal.h>
21#include <linux/tracehook.h>
21 22
22#include <asm/uaccess.h> 23#include <asm/uaccess.h>
23#include <asm/page.h> 24#include <asm/page.h>
@@ -134,14 +135,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
134 tmp >>= 16; 135 tmp >>= 16;
135 } else if (addr >= 21 && addr < 49) { 136 } else if (addr >= 21 && addr < 49) {
136 tmp = child->thread.fp[addr - 21]; 137 tmp = child->thread.fp[addr - 21];
137#ifdef CONFIG_M68KFPU_EMU
138 /* Convert internal fpu reg representation
139 * into long double format
140 */
141 if (FPU_IS_EMU && (addr < 45) && !(addr % 3))
142 tmp = ((tmp & 0xffff0000) << 15) |
143 ((tmp & 0x0000ffff) << 16);
144#endif
145 } else if (addr == 49) { 138 } else if (addr == 49) {
146 tmp = child->mm->start_code; 139 tmp = child->mm->start_code;
147 } else if (addr == 50) { 140 } else if (addr == 50) {
@@ -175,16 +168,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
175 } 168 }
176 if (addr >= 21 && addr < 48) 169 if (addr >= 21 && addr < 48)
177 { 170 {
178#ifdef CONFIG_M68KFPU_EMU
179 /* Convert long double format
180 * into internal fpu reg representation
181 */
182 if (FPU_IS_EMU && (addr < 45) && !(addr % 3)) {
183 data = (unsigned long)data << 15;
184 data = (data & 0xffff0000) |
185 ((data & 0x0000ffff) >> 1);
186 }
187#endif
188 child->thread.fp[addr - 21] = data; 171 child->thread.fp[addr - 21] = data;
189 ret = 0; 172 ret = 0;
190 } 173 }
@@ -259,21 +242,17 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
259 return ret; 242 return ret;
260} 243}
261 244
262asmlinkage void syscall_trace(void) 245asmlinkage int syscall_trace_enter(void)
263{ 246{
264 if (!test_thread_flag(TIF_SYSCALL_TRACE)) 247 int ret = 0;
265 return; 248
266 if (!(current->ptrace & PT_PTRACED)) 249 if (test_thread_flag(TIF_SYSCALL_TRACE))
267 return; 250 ret = tracehook_report_syscall_entry(task_pt_regs(current));
268 ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD) 251 return ret;
269 ? 0x80 : 0)); 252}
270 /* 253
271 * this isn't the same as continuing with a signal, but it will do 254asmlinkage void syscall_trace_leave(void)
272 * for normal use. strace only continues with a signal if the 255{
273 * stopping signal is not SIGTRAP. -brl 256 if (test_thread_flag(TIF_SYSCALL_TRACE))
274 */ 257 tracehook_report_syscall_exit(task_pt_regs(current), 0);
275 if (current->exit_code) {
276 send_sig(current->exit_code, current, 1);
277 current->exit_code = 0;
278 }
279} 258}
diff --git a/arch/m68knommu/kernel/setup.c b/arch/m68knommu/kernel/setup.c
index ba92b90d5fbc..c684adf5dc40 100644
--- a/arch/m68knommu/kernel/setup.c
+++ b/arch/m68knommu/kernel/setup.c
@@ -54,9 +54,6 @@ void (*mach_reset)(void);
54void (*mach_halt)(void); 54void (*mach_halt)(void);
55void (*mach_power_off)(void); 55void (*mach_power_off)(void);
56 56
57#ifdef CONFIG_M68000
58 #define CPU "MC68000"
59#endif
60#ifdef CONFIG_M68328 57#ifdef CONFIG_M68328
61 #define CPU "MC68328" 58 #define CPU "MC68328"
62#endif 59#endif
diff --git a/arch/m68knommu/kernel/time.c b/arch/m68knommu/kernel/time.c
index 7089dd9d843b..d6ac2a43453c 100644
--- a/arch/m68knommu/kernel/time.c
+++ b/arch/m68knommu/kernel/time.c
@@ -60,13 +60,16 @@ static unsigned long read_rtc_mmss(void)
60{ 60{
61 unsigned int year, mon, day, hour, min, sec; 61 unsigned int year, mon, day, hour, min, sec;
62 62
63 if (mach_gettod) 63 if (mach_gettod) {
64 mach_gettod(&year, &mon, &day, &hour, &min, &sec); 64 mach_gettod(&year, &mon, &day, &hour, &min, &sec);
65 else 65 if ((year += 1900) < 1970)
66 year = mon = day = hour = min = sec = 0; 66 year += 100;
67 } else {
68 year = 1970;
69 mon = day = 1;
70 hour = min = sec = 0;
71 }
67 72
68 if ((year += 1900) < 1970)
69 year += 100;
70 73
71 return mktime(year, mon, day, hour, min, sec); 74 return mktime(year, mon, day, hour, min, sec);
72} 75}
diff --git a/arch/m68knommu/kernel/traps.c b/arch/m68knommu/kernel/traps.c
index 3739c8f657d7..a768008dfd06 100644
--- a/arch/m68knommu/kernel/traps.c
+++ b/arch/m68knommu/kernel/traps.c
@@ -179,14 +179,16 @@ static void __show_stack(struct task_struct *task, unsigned long *stack)
179 179
180void bad_super_trap(struct frame *fp) 180void bad_super_trap(struct frame *fp)
181{ 181{
182 int vector = (fp->ptregs.vector >> 2) & 0xff;
183
182 console_verbose(); 184 console_verbose();
183 if (fp->ptregs.vector < 4 * ARRAY_SIZE(vec_names)) 185 if (vector < ARRAY_SIZE(vec_names))
184 printk (KERN_WARNING "*** %s *** FORMAT=%X\n", 186 printk (KERN_WARNING "*** %s *** FORMAT=%X\n",
185 vec_names[(fp->ptregs.vector) >> 2], 187 vec_names[vector],
186 fp->ptregs.format); 188 fp->ptregs.format);
187 else 189 else
188 printk (KERN_WARNING "*** Exception %d *** FORMAT=%X\n", 190 printk (KERN_WARNING "*** Exception %d *** FORMAT=%X\n",
189 (fp->ptregs.vector) >> 2, 191 vector,
190 fp->ptregs.format); 192 fp->ptregs.format);
191 printk (KERN_WARNING "Current process id is %d\n", current->pid); 193 printk (KERN_WARNING "Current process id is %d\n", current->pid);
192 die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0); 194 die_if_kernel("BAD KERNEL TRAP", &fp->ptregs, 0);
@@ -195,10 +197,11 @@ void bad_super_trap(struct frame *fp)
195asmlinkage void trap_c(struct frame *fp) 197asmlinkage void trap_c(struct frame *fp)
196{ 198{
197 int sig; 199 int sig;
200 int vector = (fp->ptregs.vector >> 2) & 0xff;
198 siginfo_t info; 201 siginfo_t info;
199 202
200 if (fp->ptregs.sr & PS_S) { 203 if (fp->ptregs.sr & PS_S) {
201 if ((fp->ptregs.vector >> 2) == VEC_TRACE) { 204 if (vector == VEC_TRACE) {
202 /* traced a trapping instruction */ 205 /* traced a trapping instruction */
203 } else 206 } else
204 bad_super_trap(fp); 207 bad_super_trap(fp);
@@ -206,7 +209,7 @@ asmlinkage void trap_c(struct frame *fp)
206 } 209 }
207 210
208 /* send the appropriate signal to the user program */ 211 /* send the appropriate signal to the user program */
209 switch ((fp->ptregs.vector) >> 2) { 212 switch (vector) {
210 case VEC_ADDRERR: 213 case VEC_ADDRERR:
211 info.si_code = BUS_ADRALN; 214 info.si_code = BUS_ADRALN;
212 sig = SIGBUS; 215 sig = SIGBUS;
@@ -360,16 +363,3 @@ void show_stack(struct task_struct *task, unsigned long *stack)
360 else 363 else
361 __show_stack(task, stack); 364 __show_stack(task, stack);
362} 365}
363
364#ifdef CONFIG_M68KFPU_EMU
365asmlinkage void fpemu_signal(int signal, int code, void *addr)
366{
367 siginfo_t info;
368
369 info.si_signo = signal;
370 info.si_errno = 0;
371 info.si_code = code;
372 info.si_addr = addr;
373 force_sig_info(signal, &info, current);
374}
375#endif
diff --git a/arch/m68knommu/platform/5206/Makefile b/arch/m68knommu/platform/5206/Makefile
index 113c33390064..b5db05625cfa 100644
--- a/arch/m68knommu/platform/5206/Makefile
+++ b/arch/m68knommu/platform/5206/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5206e/Makefile b/arch/m68knommu/platform/5206e/Makefile
index 113c33390064..b5db05625cfa 100644
--- a/arch/m68knommu/platform/5206e/Makefile
+++ b/arch/m68knommu/platform/5206e/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/520x/Makefile b/arch/m68knommu/platform/520x/Makefile
index 435ab3483dc1..ad3f4e5a57ce 100644
--- a/arch/m68knommu/platform/520x/Makefile
+++ b/arch/m68knommu/platform/520x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/523x/Makefile b/arch/m68knommu/platform/523x/Makefile
index b8f9b45440c2..c04b8f71c88c 100644
--- a/arch/m68knommu/platform/523x/Makefile
+++ b/arch/m68knommu/platform/523x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5249/Makefile b/arch/m68knommu/platform/5249/Makefile
index f56225d1582f..4bed30fd0073 100644
--- a/arch/m68knommu/platform/5249/Makefile
+++ b/arch/m68knommu/platform/5249/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5272/Makefile b/arch/m68knommu/platform/5272/Makefile
index 93673ef8e2c1..34110fc14301 100644
--- a/arch/m68knommu/platform/5272/Makefile
+++ b/arch/m68knommu/platform/5272/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5272/config.c b/arch/m68knommu/platform/5272/config.c
index 59278c0887d0..65bb582734e1 100644
--- a/arch/m68knommu/platform/5272/config.c
+++ b/arch/m68knommu/platform/5272/config.c
@@ -13,6 +13,8 @@
13#include <linux/param.h> 13#include <linux/param.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/phy.h>
17#include <linux/phy_fixed.h>
16#include <asm/machdep.h> 18#include <asm/machdep.h>
17#include <asm/coldfire.h> 19#include <asm/coldfire.h>
18#include <asm/mcfsim.h> 20#include <asm/mcfsim.h>
@@ -148,9 +150,23 @@ void __init config_BSP(char *commandp, int size)
148 150
149/***************************************************************************/ 151/***************************************************************************/
150 152
153/*
154 * Some 5272 based boards have the FEC ethernet diectly connected to
155 * an ethernet switch. In this case we need to use the fixed phy type,
156 * and we need to declare it early in boot.
157 */
158static struct fixed_phy_status nettel_fixed_phy_status __initdata = {
159 .link = 1,
160 .speed = 100,
161 .duplex = 0,
162};
163
164/***************************************************************************/
165
151static int __init init_BSP(void) 166static int __init init_BSP(void)
152{ 167{
153 m5272_uarts_init(); 168 m5272_uarts_init();
169 fixed_phy_add(PHY_POLL, 0, &nettel_fixed_phy_status);
154 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices)); 170 platform_add_devices(m5272_devices, ARRAY_SIZE(m5272_devices));
155 return 0; 171 return 0;
156} 172}
diff --git a/arch/m68knommu/platform/5272/intc.c b/arch/m68knommu/platform/5272/intc.c
index 7081e0a9720e..3cf681c177aa 100644
--- a/arch/m68knommu/platform/5272/intc.c
+++ b/arch/m68knommu/platform/5272/intc.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/interrupt.h> 14#include <linux/interrupt.h>
15#include <linux/kernel_stat.h>
15#include <linux/irq.h> 16#include <linux/irq.h>
16#include <linux/io.h> 17#include <linux/io.h>
17#include <asm/coldfire.h> 18#include <asm/coldfire.h>
@@ -29,6 +30,10 @@
29 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a 30 * via a set of 4 "Interrupt Controller Registers" (ICR). There is a
30 * loose mapping of vector number to register and internal bits, but 31 * loose mapping of vector number to register and internal bits, but
31 * a table is the easiest and quickest way to map them. 32 * a table is the easiest and quickest way to map them.
33 *
34 * Note that the external interrupts are edge triggered (unlike the
35 * internal interrupt sources which are level triggered). Which means
36 * they also need acknowledgeing via acknowledge bits.
32 */ 37 */
33struct irqmap { 38struct irqmap {
34 unsigned char icr; 39 unsigned char icr;
@@ -68,6 +73,11 @@ static struct irqmap intc_irqmap[MCFINT_VECMAX - MCFINT_VECBASE] = {
68 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, }, 73 /*MCF_IRQ_SWTO*/ { .icr = MCFSIM_ICR4, .index = 16, .ack = 0, },
69}; 74};
70 75
76/*
77 * The act of masking the interrupt also has a side effect of 'ack'ing
78 * an interrupt on this irq (for the external irqs). So this mask function
79 * is also an ack_mask function.
80 */
71static void intc_irq_mask(unsigned int irq) 81static void intc_irq_mask(unsigned int irq)
72{ 82{
73 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) { 83 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
@@ -95,7 +105,9 @@ static void intc_irq_ack(unsigned int irq)
95 irq -= MCFINT_VECBASE; 105 irq -= MCFINT_VECBASE;
96 if (intc_irqmap[irq].ack) { 106 if (intc_irqmap[irq].ack) {
97 u32 v; 107 u32 v;
98 v = 0xd << intc_irqmap[irq].index; 108 v = readl(MCF_MBAR + intc_irqmap[irq].icr);
109 v &= (0x7 << intc_irqmap[irq].index);
110 v |= (0x8 << intc_irqmap[irq].index);
99 writel(v, MCF_MBAR + intc_irqmap[irq].icr); 111 writel(v, MCF_MBAR + intc_irqmap[irq].icr);
100 } 112 }
101 } 113 }
@@ -103,21 +115,47 @@ static void intc_irq_ack(unsigned int irq)
103 115
104static int intc_irq_set_type(unsigned int irq, unsigned int type) 116static int intc_irq_set_type(unsigned int irq, unsigned int type)
105{ 117{
106 /* We can set the edge type here for external interrupts */ 118 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX)) {
119 irq -= MCFINT_VECBASE;
120 if (intc_irqmap[irq].ack) {
121 u32 v;
122 v = readl(MCF_MBAR + MCFSIM_PITR);
123 if (type == IRQ_TYPE_EDGE_FALLING)
124 v &= ~(0x1 << (32 - irq));
125 else
126 v |= (0x1 << (32 - irq));
127 writel(v, MCF_MBAR + MCFSIM_PITR);
128 }
129 }
107 return 0; 130 return 0;
108} 131}
109 132
133/*
134 * Simple flow handler to deal with the external edge triggered interrupts.
135 * We need to be careful with the masking/acking due to the side effects
136 * of masking an interrupt.
137 */
138static void intc_external_irq(unsigned int irq, struct irq_desc *desc)
139{
140 kstat_incr_irqs_this_cpu(irq, desc);
141 desc->status |= IRQ_INPROGRESS;
142 desc->chip->ack(irq);
143 handle_IRQ_event(irq, desc->action);
144 desc->status &= ~IRQ_INPROGRESS;
145}
146
110static struct irq_chip intc_irq_chip = { 147static struct irq_chip intc_irq_chip = {
111 .name = "CF-INTC", 148 .name = "CF-INTC",
112 .mask = intc_irq_mask, 149 .mask = intc_irq_mask,
113 .unmask = intc_irq_unmask, 150 .unmask = intc_irq_unmask,
151 .mask_ack = intc_irq_mask,
114 .ack = intc_irq_ack, 152 .ack = intc_irq_ack,
115 .set_type = intc_irq_set_type, 153 .set_type = intc_irq_set_type,
116}; 154};
117 155
118void __init init_IRQ(void) 156void __init init_IRQ(void)
119{ 157{
120 int irq; 158 int irq, edge;
121 159
122 init_vectors(); 160 init_vectors();
123 161
@@ -128,11 +166,17 @@ void __init init_IRQ(void)
128 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4); 166 writel(0x88888888, MCF_MBAR + MCFSIM_ICR4);
129 167
130 for (irq = 0; (irq < NR_IRQS); irq++) { 168 for (irq = 0; (irq < NR_IRQS); irq++) {
131 irq_desc[irq].status = IRQ_DISABLED; 169 set_irq_chip(irq, &intc_irq_chip);
132 irq_desc[irq].action = NULL; 170 edge = 0;
133 irq_desc[irq].depth = 1; 171 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECMAX))
134 irq_desc[irq].chip = &intc_irq_chip; 172 edge = intc_irqmap[irq - MCFINT_VECBASE].ack;
135 intc_irq_set_type(irq, 0); 173 if (edge) {
174 set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
175 set_irq_handler(irq, intc_external_irq);
176 } else {
177 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
178 set_irq_handler(irq, handle_level_irq);
179 }
136 } 180 }
137} 181}
138 182
diff --git a/arch/m68knommu/platform/527x/Makefile b/arch/m68knommu/platform/527x/Makefile
index 3d90e6d92459..6ac4b57370ea 100644
--- a/arch/m68knommu/platform/527x/Makefile
+++ b/arch/m68knommu/platform/527x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/528x/Makefile b/arch/m68knommu/platform/528x/Makefile
index 3d90e6d92459..6ac4b57370ea 100644
--- a/arch/m68knommu/platform/528x/Makefile
+++ b/arch/m68knommu/platform/528x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5307/Makefile b/arch/m68knommu/platform/5307/Makefile
index 6de526976828..d4293b791f2e 100644
--- a/arch/m68knommu/platform/5307/Makefile
+++ b/arch/m68knommu/platform/5307/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/532x/Makefile b/arch/m68knommu/platform/532x/Makefile
index 4cc23245bcd1..ce01669399c6 100644
--- a/arch/m68knommu/platform/532x/Makefile
+++ b/arch/m68knommu/platform/532x/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/5407/Makefile b/arch/m68knommu/platform/5407/Makefile
index dee62c5dbaa6..e83fe148eddc 100644
--- a/arch/m68knommu/platform/5407/Makefile
+++ b/arch/m68knommu/platform/5407/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
diff --git a/arch/m68knommu/platform/548x/Makefile b/arch/m68knommu/platform/548x/Makefile
new file mode 100644
index 000000000000..e6035e7a2d3f
--- /dev/null
+++ b/arch/m68knommu/platform/548x/Makefile
@@ -0,0 +1,18 @@
1#
2# Makefile for the m68knommu linux kernel.
3#
4
5#
6# If you want to play with the HW breakpoints then you will
7# need to add define this, which will give you a stack backtrace
8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt:
10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT
13#
14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
16
17obj-y := config.o
18
diff --git a/arch/m68knommu/platform/548x/config.c b/arch/m68knommu/platform/548x/config.c
new file mode 100644
index 000000000000..9888846bd1cf
--- /dev/null
+++ b/arch/m68knommu/platform/548x/config.c
@@ -0,0 +1,115 @@
1/***************************************************************************/
2
3/*
4 * linux/arch/m68knommu/platform/548x/config.c
5 *
6 * Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
7 */
8
9/***************************************************************************/
10
11#include <linux/kernel.h>
12#include <linux/param.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <asm/machdep.h>
17#include <asm/coldfire.h>
18#include <asm/m548xsim.h>
19#include <asm/mcfuart.h>
20#include <asm/m548xgpt.h>
21
22/***************************************************************************/
23
24static struct mcf_platform_uart m548x_uart_platform[] = {
25 {
26 .mapbase = MCF_MBAR + MCFUART_BASE1,
27 .irq = 64 + 35,
28 },
29 {
30 .mapbase = MCF_MBAR + MCFUART_BASE2,
31 .irq = 64 + 34,
32 },
33 {
34 .mapbase = MCF_MBAR + MCFUART_BASE3,
35 .irq = 64 + 33,
36 },
37 {
38 .mapbase = MCF_MBAR + MCFUART_BASE4,
39 .irq = 64 + 32,
40 },
41};
42
43static struct platform_device m548x_uart = {
44 .name = "mcfuart",
45 .id = 0,
46 .dev.platform_data = m548x_uart_platform,
47};
48
49static struct platform_device *m548x_devices[] __initdata = {
50 &m548x_uart,
51};
52
53
54/***************************************************************************/
55
56static void __init m548x_uart_init_line(int line, int irq)
57{
58 int rts_cts;
59
60 /* enable io pins */
61 switch (line) {
62 case 0:
63 rts_cts = 0; break;
64 case 1:
65 rts_cts = MCF_PAR_PSC_RTS_RTS; break;
66 case 2:
67 rts_cts = MCF_PAR_PSC_RTS_RTS | MCF_PAR_PSC_CTS_CTS; break;
68 case 3:
69 rts_cts = 0; break;
70 }
71 __raw_writeb(MCF_PAR_PSC_TXD | rts_cts | MCF_PAR_PSC_RXD,
72 MCF_MBAR + MCF_PAR_PSC(line));
73}
74
75static void __init m548x_uarts_init(void)
76{
77 const int nrlines = ARRAY_SIZE(m548x_uart_platform);
78 int line;
79
80 for (line = 0; (line < nrlines); line++)
81 m548x_uart_init_line(line, m548x_uart_platform[line].irq);
82}
83
84/***************************************************************************/
85
86static void mcf548x_reset(void)
87{
88 /* disable interrupts and enable the watchdog */
89 asm("movew #0x2700, %sr\n");
90 __raw_writel(0, MCF_MBAR + MCF_GPT_GMS0);
91 __raw_writel(MCF_GPT_GCIR_CNT(1), MCF_MBAR + MCF_GPT_GCIR0);
92 __raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
93 MCF_MBAR + MCF_GPT_GMS0);
94}
95
96/***************************************************************************/
97
98void __init config_BSP(char *commandp, int size)
99{
100 mach_reset = mcf548x_reset;
101 m548x_uarts_init();
102}
103
104/***************************************************************************/
105
106static int __init init_BSP(void)
107{
108
109 platform_add_devices(m548x_devices, ARRAY_SIZE(m548x_devices));
110 return 0;
111}
112
113arch_initcall(init_BSP);
114
115/***************************************************************************/
diff --git a/arch/m68knommu/platform/68328/entry.S b/arch/m68knommu/platform/68328/entry.S
index 9d80d2c42866..27241e16a526 100644
--- a/arch/m68knommu/platform/68328/entry.S
+++ b/arch/m68knommu/platform/68328/entry.S
@@ -43,10 +43,10 @@ badsys:
43 jra ret_from_exception 43 jra ret_from_exception
44 44
45do_trace: 45do_trace:
46 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ 46 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
47 subql #4,%sp 47 subql #4,%sp
48 SAVE_SWITCH_STACK 48 SAVE_SWITCH_STACK
49 jbsr syscall_trace 49 jbsr syscall_trace_enter
50 RESTORE_SWITCH_STACK 50 RESTORE_SWITCH_STACK
51 addql #4,%sp 51 addql #4,%sp
52 movel %sp@(PT_OFF_ORIG_D0),%d1 52 movel %sp@(PT_OFF_ORIG_D0),%d1
@@ -57,10 +57,10 @@ do_trace:
57 lea sys_call_table, %a0 57 lea sys_call_table, %a0
58 jbsr %a0@(%d1) 58 jbsr %a0@(%d1)
59 59
601: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 601: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
61 subql #4,%sp /* dummy return address */ 61 subql #4,%sp /* dummy return address */
62 SAVE_SWITCH_STACK 62 SAVE_SWITCH_STACK
63 jbsr syscall_trace 63 jbsr syscall_trace_leave
64 64
65ret_from_signal: 65ret_from_signal:
66 RESTORE_SWITCH_STACK 66 RESTORE_SWITCH_STACK
@@ -71,16 +71,16 @@ ENTRY(system_call)
71 SAVE_ALL 71 SAVE_ALL
72 72
73 /* save top of frame*/ 73 /* save top of frame*/
74 pea %sp@ 74 pea %sp@
75 jbsr set_esp0 75 jbsr set_esp0
76 addql #4,%sp 76 addql #4,%sp
77 77
78 movel %sp@(PT_OFF_ORIG_D0),%d0 78 movel %sp@(PT_OFF_ORIG_D0),%d0
79 79
80 movel %sp,%d1 /* get thread_info pointer */ 80 movel %sp,%d1 /* get thread_info pointer */
81 andl #-THREAD_SIZE,%d1 81 andl #-THREAD_SIZE,%d1
82 movel %d1,%a2 82 movel %d1,%a2
83 btst #TIF_SYSCALL_TRACE,%a2@(TI_FLAGS) 83 btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
84 jne do_trace 84 jne do_trace
85 cmpl #NR_syscalls,%d0 85 cmpl #NR_syscalls,%d0
86 jcc badsys 86 jcc badsys
@@ -88,10 +88,10 @@ ENTRY(system_call)
88 lea sys_call_table,%a0 88 lea sys_call_table,%a0
89 movel %a0@(%d0), %a0 89 movel %a0@(%d0), %a0
90 jbsr %a0@ 90 jbsr %a0@
91 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/ 91 movel %d0,%sp@(PT_OFF_D0) /* save the return value*/
92 92
93ret_from_exception: 93ret_from_exception:
94 btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/ 94 btst #5,%sp@(PT_OFF_SR) /* check if returning to kernel*/
95 jeq Luser_return /* if so, skip resched, signals*/ 95 jeq Luser_return /* if so, skip resched, signals*/
96 96
97Lkernel_return: 97Lkernel_return:
@@ -133,7 +133,7 @@ Lreturn:
133 */ 133 */
134inthandler1: 134inthandler1:
135 SAVE_ALL 135 SAVE_ALL
136 movew %sp@(PT_OFF_VECTOR), %d0 136 movew %sp@(PT_OFF_FORMATVEC), %d0
137 and #0x3ff, %d0 137 and #0x3ff, %d0
138 138
139 movel %sp,%sp@- 139 movel %sp,%sp@-
@@ -144,7 +144,7 @@ inthandler1:
144 144
145inthandler2: 145inthandler2:
146 SAVE_ALL 146 SAVE_ALL
147 movew %sp@(PT_OFF_VECTOR), %d0 147 movew %sp@(PT_OFF_FORMATVEC), %d0
148 and #0x3ff, %d0 148 and #0x3ff, %d0
149 149
150 movel %sp,%sp@- 150 movel %sp,%sp@-
@@ -155,7 +155,7 @@ inthandler2:
155 155
156inthandler3: 156inthandler3:
157 SAVE_ALL 157 SAVE_ALL
158 movew %sp@(PT_OFF_VECTOR), %d0 158 movew %sp@(PT_OFF_FORMATVEC), %d0
159 and #0x3ff, %d0 159 and #0x3ff, %d0
160 160
161 movel %sp,%sp@- 161 movel %sp,%sp@-
@@ -166,7 +166,7 @@ inthandler3:
166 166
167inthandler4: 167inthandler4:
168 SAVE_ALL 168 SAVE_ALL
169 movew %sp@(PT_OFF_VECTOR), %d0 169 movew %sp@(PT_OFF_FORMATVEC), %d0
170 and #0x3ff, %d0 170 and #0x3ff, %d0
171 171
172 movel %sp,%sp@- 172 movel %sp,%sp@-
@@ -177,7 +177,7 @@ inthandler4:
177 177
178inthandler5: 178inthandler5:
179 SAVE_ALL 179 SAVE_ALL
180 movew %sp@(PT_OFF_VECTOR), %d0 180 movew %sp@(PT_OFF_FORMATVEC), %d0
181 and #0x3ff, %d0 181 and #0x3ff, %d0
182 182
183 movel %sp,%sp@- 183 movel %sp,%sp@-
@@ -188,7 +188,7 @@ inthandler5:
188 188
189inthandler6: 189inthandler6:
190 SAVE_ALL 190 SAVE_ALL
191 movew %sp@(PT_OFF_VECTOR), %d0 191 movew %sp@(PT_OFF_FORMATVEC), %d0
192 and #0x3ff, %d0 192 and #0x3ff, %d0
193 193
194 movel %sp,%sp@- 194 movel %sp,%sp@-
@@ -199,7 +199,7 @@ inthandler6:
199 199
200inthandler7: 200inthandler7:
201 SAVE_ALL 201 SAVE_ALL
202 movew %sp@(PT_OFF_VECTOR), %d0 202 movew %sp@(PT_OFF_FORMATVEC), %d0
203 and #0x3ff, %d0 203 and #0x3ff, %d0
204 204
205 movel %sp,%sp@- 205 movel %sp,%sp@-
@@ -210,7 +210,7 @@ inthandler7:
210 210
211inthandler: 211inthandler:
212 SAVE_ALL 212 SAVE_ALL
213 movew %sp@(PT_OFF_VECTOR), %d0 213 movew %sp@(PT_OFF_FORMATVEC), %d0
214 and #0x3ff, %d0 214 and #0x3ff, %d0
215 215
216 movel %sp,%sp@- 216 movel %sp,%sp@-
diff --git a/arch/m68knommu/platform/68328/head-de2.S b/arch/m68knommu/platform/68328/head-de2.S
index 92d96456d363..f632fdcb93e9 100644
--- a/arch/m68knommu/platform/68328/head-de2.S
+++ b/arch/m68knommu/platform/68328/head-de2.S
@@ -1,11 +1,5 @@
1 1
2#if defined(CONFIG_RAM32MB)
3#define MEM_END 0x02000000 /* Memory size 32Mb */
4#elif defined(CONFIG_RAM16MB)
5#define MEM_END 0x01000000 /* Memory size 16Mb */
6#else
7#define MEM_END 0x00800000 /* Memory size 8Mb */ 2#define MEM_END 0x00800000 /* Memory size 8Mb */
8#endif
9 3
10#undef CRT_DEBUG 4#undef CRT_DEBUG
11 5
diff --git a/arch/m68knommu/platform/68328/head-ram.S b/arch/m68knommu/platform/68328/head-ram.S
index 252b80b02038..7f1aeeacb219 100644
--- a/arch/m68knommu/platform/68328/head-ram.S
+++ b/arch/m68knommu/platform/68328/head-ram.S
@@ -67,33 +67,6 @@ pclp1:
67 beq pclp1 67 beq pclp1
68#endif /* DEBUG */ 68#endif /* DEBUG */
69 69
70#ifdef CONFIG_RELOCATE
71 /* Copy me to RAM */
72 moveal #__rom_start, %a0
73 moveal #_stext, %a1
74 moveal #_edata, %a2
75
76 /* Copy %a0 to %a1 until %a1 == %a2 */
77LD1:
78 movel %a0@+, %d0
79 movel %d0, %a1@+
80 cmpal %a1, %a2
81 bhi LD1
82
83#ifdef DEBUG
84 moveq #74, %d7 /* 'J' */
85 moveb %d7,0xfffff907 /* No absolute addresses */
86pclp2:
87 movew 0xfffff906, %d7
88 andw #0x2000, %d7
89 beq pclp2
90#endif /* DEBUG */
91 /* jump into the RAM copy */
92 jmp ram_jump
93ram_jump:
94
95#endif /* CONFIG_RELOCATE */
96
97#ifdef DEBUG 70#ifdef DEBUG
98 moveq #82, %d7 /* 'R' */ 71 moveq #82, %d7 /* 'R' */
99 moveb %d7,0xfffff907 /* No absolute addresses */ 72 moveb %d7,0xfffff907 /* No absolute addresses */
diff --git a/arch/m68knommu/platform/68328/ints.c b/arch/m68knommu/platform/68328/ints.c
index b91ee85d4b5d..865852806a17 100644
--- a/arch/m68knommu/platform/68328/ints.c
+++ b/arch/m68knommu/platform/68328/ints.c
@@ -179,10 +179,8 @@ void __init init_IRQ(void)
179 IMR = ~0; 179 IMR = ~0;
180 180
181 for (i = 0; (i < NR_IRQS); i++) { 181 for (i = 0; (i < NR_IRQS); i++) {
182 irq_desc[i].status = IRQ_DISABLED; 182 set_irq_chip(irq, &intc_irq_chip);
183 irq_desc[i].action = NULL; 183 set_irq_handler(irq, handle_level_irq);
184 irq_desc[i].depth = 1;
185 irq_desc[i].chip = &intc_irq_chip;
186 } 184 }
187} 185}
188 186
diff --git a/arch/m68knommu/platform/68360/entry.S b/arch/m68knommu/platform/68360/entry.S
index 6d3460a39cac..c131c6e1d92d 100644
--- a/arch/m68knommu/platform/68360/entry.S
+++ b/arch/m68knommu/platform/68360/entry.S
@@ -42,7 +42,7 @@ do_trace:
42 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/ 42 movel #-ENOSYS,%sp@(PT_OFF_D0) /* needed for strace*/
43 subql #4,%sp 43 subql #4,%sp
44 SAVE_SWITCH_STACK 44 SAVE_SWITCH_STACK
45 jbsr syscall_trace 45 jbsr syscall_trace_enter
46 RESTORE_SWITCH_STACK 46 RESTORE_SWITCH_STACK
47 addql #4,%sp 47 addql #4,%sp
48 movel %sp@(PT_OFF_ORIG_D0),%d1 48 movel %sp@(PT_OFF_ORIG_D0),%d1
@@ -56,7 +56,7 @@ do_trace:
561: movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 561: movel %d0,%sp@(PT_OFF_D0) /* save the return value */
57 subql #4,%sp /* dummy return address */ 57 subql #4,%sp /* dummy return address */
58 SAVE_SWITCH_STACK 58 SAVE_SWITCH_STACK
59 jbsr syscall_trace 59 jbsr syscall_trace_leave
60 60
61ret_from_signal: 61ret_from_signal:
62 RESTORE_SWITCH_STACK 62 RESTORE_SWITCH_STACK
@@ -71,7 +71,12 @@ ENTRY(system_call)
71 jbsr set_esp0 71 jbsr set_esp0
72 addql #4,%sp 72 addql #4,%sp
73 73
74 btst #PF_TRACESYS_BIT,%a2@(TASK_FLAGS+PF_TRACESYS_OFF) 74 movel %sp@(PT_OFF_ORIG_D0),%d0
75
76 movel %sp,%d1 /* get thread_info pointer */
77 andl #-THREAD_SIZE,%d1
78 movel %d1,%a2
79 btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
75 jne do_trace 80 jne do_trace
76 cmpl #NR_syscalls,%d0 81 cmpl #NR_syscalls,%d0
77 jcc badsys 82 jcc badsys
@@ -124,7 +129,7 @@ Lreturn:
124 */ 129 */
125inthandler: 130inthandler:
126 SAVE_ALL 131 SAVE_ALL
127 movew %sp@(PT_OFF_VECTOR), %d0 132 movew %sp@(PT_OFF_FORMATVEC), %d0
128 and.l #0x3ff, %d0 133 and.l #0x3ff, %d0
129 lsr.l #0x02, %d0 134 lsr.l #0x02, %d0
130 135
diff --git a/arch/m68knommu/platform/68360/ints.c b/arch/m68knommu/platform/68360/ints.c
index 6f22970d8c20..ad96ab1051f0 100644
--- a/arch/m68knommu/platform/68360/ints.c
+++ b/arch/m68knommu/platform/68360/ints.c
@@ -132,10 +132,8 @@ void init_IRQ(void)
132 pquicc->intr_cimr = 0x00000000; 132 pquicc->intr_cimr = 0x00000000;
133 133
134 for (i = 0; (i < NR_IRQS); i++) { 134 for (i = 0; (i < NR_IRQS); i++) {
135 irq_desc[i].status = IRQ_DISABLED; 135 set_irq_chip(irq, &intc_irq_chip);
136 irq_desc[i].action = NULL; 136 set_irq_handler(irq, handle_level_irq);
137 irq_desc[i].depth = 1;
138 irq_desc[i].chip = &intc_irq_chip;
139 } 137 }
140} 138}
141 139
diff --git a/arch/m68knommu/platform/68VZ328/config.c b/arch/m68knommu/platform/68VZ328/config.c
index fc5c63054e98..eabaabe8af36 100644
--- a/arch/m68knommu/platform/68VZ328/config.c
+++ b/arch/m68knommu/platform/68VZ328/config.c
@@ -90,11 +90,6 @@ static void init_hardware(char *command, int size)
90 PDIQEG &= ~PD(1); 90 PDIQEG &= ~PD(1);
91 PDIRQEN |= PD(1); /* IRQ enabled */ 91 PDIRQEN |= PD(1); /* IRQ enabled */
92 92
93#ifdef CONFIG_68328_SERIAL_UART2
94 /* Enable RXD TXD port bits to enable UART2 */
95 PJSEL &= ~(PJ(5) | PJ(4));
96#endif
97
98#ifdef CONFIG_INIT_LCD 93#ifdef CONFIG_INIT_LCD
99 /* initialize LCD controller */ 94 /* initialize LCD controller */
100 LSSA = (long) screen_bits; 95 LSSA = (long) screen_bits;
diff --git a/arch/m68knommu/platform/coldfire/Makefile b/arch/m68knommu/platform/coldfire/Makefile
index f72a0e5d9996..45f501fa4525 100644
--- a/arch/m68knommu/platform/coldfire/Makefile
+++ b/arch/m68knommu/platform/coldfire/Makefile
@@ -8,8 +8,8 @@
8# on the console port whenever a DBG interrupt occurs. You have to 8# on the console port whenever a DBG interrupt occurs. You have to
9# set up you HW breakpoints to trigger a DBG interrupt: 9# set up you HW breakpoints to trigger a DBG interrupt:
10# 10#
11# EXTRA_CFLAGS += -DTRAP_DBG_INTERRUPT 11# ccflags-y := -DTRAP_DBG_INTERRUPT
12# EXTRA_AFLAGS += -DTRAP_DBG_INTERRUPT 12# asflags-y := -DTRAP_DBG_INTERRUPT
13# 13#
14 14
15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1 15asflags-$(CONFIG_FULLDEBUG) := -DDEBUGGER_COMPATIBLE_CACHE=1
@@ -26,6 +26,7 @@ obj-$(CONFIG_M528x) += pit.o intc-2.o
26obj-$(CONFIG_M5307) += timers.o intc.o 26obj-$(CONFIG_M5307) += timers.o intc.o
27obj-$(CONFIG_M532x) += timers.o intc-simr.o 27obj-$(CONFIG_M532x) += timers.o intc-simr.o
28obj-$(CONFIG_M5407) += timers.o intc.o 28obj-$(CONFIG_M5407) += timers.o intc.o
29obj-$(CONFIG_M548x) += sltimers.o intc-2.o
29 30
30obj-y += pinmux.o gpio.o 31obj-y += pinmux.o gpio.o
31extra-y := head.o 32extra-y := head.o
diff --git a/arch/m68knommu/platform/coldfire/entry.S b/arch/m68knommu/platform/coldfire/entry.S
index cd79d7e92ce6..5e92bed94b7e 100644
--- a/arch/m68knommu/platform/coldfire/entry.S
+++ b/arch/m68knommu/platform/coldfire/entry.S
@@ -88,7 +88,7 @@ ENTRY(system_call)
88 movel %d2,PT_OFF_D0(%sp) /* on syscall entry */ 88 movel %d2,PT_OFF_D0(%sp) /* on syscall entry */
89 subql #4,%sp 89 subql #4,%sp
90 SAVE_SWITCH_STACK 90 SAVE_SWITCH_STACK
91 jbsr syscall_trace 91 jbsr syscall_trace_enter
92 RESTORE_SWITCH_STACK 92 RESTORE_SWITCH_STACK
93 addql #4,%sp 93 addql #4,%sp
94 movel %d3,%a0 94 movel %d3,%a0
@@ -96,7 +96,7 @@ ENTRY(system_call)
96 movel %d0,%sp@(PT_OFF_D0) /* save the return value */ 96 movel %d0,%sp@(PT_OFF_D0) /* save the return value */
97 subql #4,%sp /* dummy return address */ 97 subql #4,%sp /* dummy return address */
98 SAVE_SWITCH_STACK 98 SAVE_SWITCH_STACK
99 jbsr syscall_trace 99 jbsr syscall_trace_leave
100 100
101ret_from_signal: 101ret_from_signal:
102 RESTORE_SWITCH_STACK 102 RESTORE_SWITCH_STACK
diff --git a/arch/m68knommu/platform/coldfire/intc-2.c b/arch/m68knommu/platform/coldfire/intc-2.c
index 5598c8b8661f..85daa2b3001a 100644
--- a/arch/m68knommu/platform/coldfire/intc-2.c
+++ b/arch/m68knommu/platform/coldfire/intc-2.c
@@ -1,5 +1,11 @@
1/* 1/*
2 * intc-1.c 2 * intc-2.c
3 *
4 * General interrupt controller code for the many ColdFire cores that use
5 * interrupt controllers with 63 interrupt sources, organized as 56 fully-
6 * programmable + 7 fixed-level interrupt sources. This includes the 523x
7 * family, the 5270, 5271, 5274, 5275, and the 528x family which have two such
8 * controllers, and the 547x and 548x families which have only one of them.
3 * 9 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> 10 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 * 11 *
@@ -19,21 +25,37 @@
19#include <asm/traps.h> 25#include <asm/traps.h>
20 26
21/* 27/*
22 * Each vector needs a unique priority and level asscoiated with it. 28 * Bit definitions for the ICR family of registers.
29 */
30#define MCFSIM_ICR_LEVEL(l) ((l)<<3) /* Level l intr */
31#define MCFSIM_ICR_PRI(p) (p) /* Priority p intr */
32
33/*
34 * Each vector needs a unique priority and level associated with it.
23 * We don't really care so much what they are, we don't rely on the 35 * We don't really care so much what they are, we don't rely on the
24 * tranditional priority interrupt scheme of the m68k/ColdFire. 36 * traditional priority interrupt scheme of the m68k/ColdFire.
25 */ 37 */
26static u8 intc_intpri = 0x36; 38static u8 intc_intpri = MCFSIM_ICR_LEVEL(6) | MCFSIM_ICR_PRI(6);
39
40#ifdef MCFICM_INTC1
41#define NR_VECS 128
42#else
43#define NR_VECS 64
44#endif
27 45
28static void intc_irq_mask(unsigned int irq) 46static void intc_irq_mask(unsigned int irq)
29{ 47{
30 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { 48 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
31 unsigned long imraddr; 49 unsigned long imraddr;
32 u32 val, imrbit; 50 u32 val, imrbit;
33 51
34 irq -= MCFINT_VECBASE; 52 irq -= MCFINT_VECBASE;
35 imraddr = MCF_IPSBAR; 53 imraddr = MCF_IPSBAR;
54#ifdef MCFICM_INTC1
36 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 55 imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
56#else
57 imraddr += MCFICM_INTC0;
58#endif
37 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; 59 imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL;
38 imrbit = 0x1 << (irq & 0x1f); 60 imrbit = 0x1 << (irq & 0x1f);
39 61
@@ -44,13 +66,17 @@ static void intc_irq_mask(unsigned int irq)
44 66
45static void intc_irq_unmask(unsigned int irq) 67static void intc_irq_unmask(unsigned int irq)
46{ 68{
47 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { 69 if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + NR_VECS)) {
48 unsigned long intaddr, imraddr, icraddr; 70 unsigned long intaddr, imraddr, icraddr;
49 u32 val, imrbit; 71 u32 val, imrbit;
50 72
51 irq -= MCFINT_VECBASE; 73 irq -= MCFINT_VECBASE;
52 intaddr = MCF_IPSBAR; 74 intaddr = MCF_IPSBAR;
75#ifdef MCFICM_INTC1
53 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; 76 intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0;
77#else
78 intaddr += MCFICM_INTC0;
79#endif
54 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); 80 imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL);
55 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); 81 icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f);
56 imrbit = 0x1 << (irq & 0x1f); 82 imrbit = 0x1 << (irq & 0x1f);
@@ -67,10 +93,16 @@ static void intc_irq_unmask(unsigned int irq)
67 } 93 }
68} 94}
69 95
96static int intc_irq_set_type(unsigned int irq, unsigned int type)
97{
98 return 0;
99}
100
70static struct irq_chip intc_irq_chip = { 101static struct irq_chip intc_irq_chip = {
71 .name = "CF-INTC", 102 .name = "CF-INTC",
72 .mask = intc_irq_mask, 103 .mask = intc_irq_mask,
73 .unmask = intc_irq_unmask, 104 .unmask = intc_irq_unmask,
105 .set_type = intc_irq_set_type,
74}; 106};
75 107
76void __init init_IRQ(void) 108void __init init_IRQ(void)
@@ -81,13 +113,14 @@ void __init init_IRQ(void)
81 113
82 /* Mask all interrupt sources */ 114 /* Mask all interrupt sources */
83 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); 115 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL);
116#ifdef MCFICM_INTC1
84 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); 117 __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL);
118#endif
85 119
86 for (irq = 0; (irq < NR_IRQS); irq++) { 120 for (irq = 0; (irq < NR_IRQS); irq++) {
87 irq_desc[irq].status = IRQ_DISABLED; 121 set_irq_chip(irq, &intc_irq_chip);
88 irq_desc[irq].action = NULL; 122 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
89 irq_desc[irq].depth = 1; 123 set_irq_handler(irq, handle_level_irq);
90 irq_desc[irq].chip = &intc_irq_chip;
91 } 124 }
92} 125}
93 126
diff --git a/arch/m68knommu/platform/coldfire/intc-simr.c b/arch/m68knommu/platform/coldfire/intc-simr.c
index 1b01e79c2f63..bb7048636140 100644
--- a/arch/m68knommu/platform/coldfire/intc-simr.c
+++ b/arch/m68knommu/platform/coldfire/intc-simr.c
@@ -1,6 +1,8 @@
1/* 1/*
2 * intc-simr.c 2 * intc-simr.c
3 * 3 *
4 * Interrupt controller code for the ColdFire 5208, 5207 & 532x parts.
5 *
4 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> 6 * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com>
5 * 7 *
6 * This file is subject to the terms and conditions of the GNU General Public 8 * This file is subject to the terms and conditions of the GNU General Public
@@ -68,11 +70,9 @@ void __init init_IRQ(void)
68 __raw_writeb(0xff, MCFINTC1_SIMR); 70 __raw_writeb(0xff, MCFINTC1_SIMR);
69 71
70 for (irq = 0; (irq < NR_IRQS); irq++) { 72 for (irq = 0; (irq < NR_IRQS); irq++) {
71 irq_desc[irq].status = IRQ_DISABLED; 73 set_irq_chip(irq, &intc_irq_chip);
72 irq_desc[irq].action = NULL; 74 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
73 irq_desc[irq].depth = 1; 75 set_irq_handler(irq, handle_level_irq);
74 irq_desc[irq].chip = &intc_irq_chip;
75 intc_irq_set_type(irq, 0);
76 } 76 }
77} 77}
78 78
diff --git a/arch/m68knommu/platform/coldfire/intc.c b/arch/m68knommu/platform/coldfire/intc.c
index a4560c86db71..60d2fcbe182b 100644
--- a/arch/m68knommu/platform/coldfire/intc.c
+++ b/arch/m68knommu/platform/coldfire/intc.c
@@ -143,11 +143,9 @@ void __init init_IRQ(void)
143 mcf_maskimr(0xffffffff); 143 mcf_maskimr(0xffffffff);
144 144
145 for (irq = 0; (irq < NR_IRQS); irq++) { 145 for (irq = 0; (irq < NR_IRQS); irq++) {
146 irq_desc[irq].status = IRQ_DISABLED; 146 set_irq_chip(irq, &intc_irq_chip);
147 irq_desc[irq].action = NULL; 147 set_irq_type(irq, IRQ_TYPE_LEVEL_HIGH);
148 irq_desc[irq].depth = 1; 148 set_irq_handler(irq, handle_level_irq);
149 irq_desc[irq].chip = &intc_irq_chip;
150 intc_irq_set_type(irq, 0);
151 } 149 }
152} 150}
153 151
diff --git a/arch/m68knommu/platform/coldfire/sltimers.c b/arch/m68knommu/platform/coldfire/sltimers.c
new file mode 100644
index 000000000000..0a1b937c3e18
--- /dev/null
+++ b/arch/m68knommu/platform/coldfire/sltimers.c
@@ -0,0 +1,145 @@
1/***************************************************************************/
2
3/*
4 * sltimers.c -- generic ColdFire slice timer support.
5 *
6 * Copyright (C) 2009-2010, Philippe De Muyter <phdm@macqel.be>
7 * based on
8 * timers.c -- generic ColdFire hardware timer support.
9 * Copyright (C) 1999-2008, Greg Ungerer <gerg@snapgear.com>
10 */
11
12/***************************************************************************/
13
14#include <linux/kernel.h>
15#include <linux/init.h>
16#include <linux/sched.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/profile.h>
20#include <linux/clocksource.h>
21#include <asm/io.h>
22#include <asm/traps.h>
23#include <asm/machdep.h>
24#include <asm/coldfire.h>
25#include <asm/mcfslt.h>
26#include <asm/mcfsim.h>
27
28/***************************************************************************/
29
30#ifdef CONFIG_HIGHPROFILE
31
32/*
33 * By default use Slice Timer 1 as the profiler clock timer.
34 */
35#define PA(a) (MCF_MBAR + MCFSLT_TIMER1 + (a))
36
37/*
38 * Choose a reasonably fast profile timer. Make it an odd value to
39 * try and get good coverage of kernel operations.
40 */
41#define PROFILEHZ 1013
42
43irqreturn_t mcfslt_profile_tick(int irq, void *dummy)
44{
45 /* Reset Slice Timer 1 */
46 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, PA(MCFSLT_SSR));
47 if (current->pid)
48 profile_tick(CPU_PROFILING);
49 return IRQ_HANDLED;
50}
51
52static struct irqaction mcfslt_profile_irq = {
53 .name = "profile timer",
54 .flags = IRQF_DISABLED | IRQF_TIMER,
55 .handler = mcfslt_profile_tick,
56};
57
58void mcfslt_profile_init(void)
59{
60 printk(KERN_INFO "PROFILE: lodging TIMER 1 @ %dHz as profile timer\n",
61 PROFILEHZ);
62
63 setup_irq(MCF_IRQ_PROFILER, &mcfslt_profile_irq);
64
65 /* Set up TIMER 2 as high speed profile clock */
66 __raw_writel(MCF_BUSCLK / PROFILEHZ - 1, PA(MCFSLT_STCNT));
67 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
68 PA(MCFSLT_SCR));
69
70}
71
72#endif /* CONFIG_HIGHPROFILE */
73
74/***************************************************************************/
75
76/*
77 * By default use Slice Timer 0 as the system clock timer.
78 */
79#define TA(a) (MCF_MBAR + MCFSLT_TIMER0 + (a))
80
81static u32 mcfslt_cycles_per_jiffy;
82static u32 mcfslt_cnt;
83
84static irqreturn_t mcfslt_tick(int irq, void *dummy)
85{
86 /* Reset Slice Timer 0 */
87 __raw_writel(MCFSLT_SSR_BE | MCFSLT_SSR_TE, TA(MCFSLT_SSR));
88 mcfslt_cnt += mcfslt_cycles_per_jiffy;
89 return arch_timer_interrupt(irq, dummy);
90}
91
92static struct irqaction mcfslt_timer_irq = {
93 .name = "timer",
94 .flags = IRQF_DISABLED | IRQF_TIMER,
95 .handler = mcfslt_tick,
96};
97
98static cycle_t mcfslt_read_clk(struct clocksource *cs)
99{
100 unsigned long flags;
101 u32 cycles;
102 u16 scnt;
103
104 local_irq_save(flags);
105 scnt = __raw_readl(TA(MCFSLT_SCNT));
106 cycles = mcfslt_cnt;
107 local_irq_restore(flags);
108
109 /* substract because slice timers count down */
110 return cycles - scnt;
111}
112
113static struct clocksource mcfslt_clk = {
114 .name = "slt",
115 .rating = 250,
116 .read = mcfslt_read_clk,
117 .shift = 20,
118 .mask = CLOCKSOURCE_MASK(32),
119 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
120};
121
122void hw_timer_init(void)
123{
124 mcfslt_cycles_per_jiffy = MCF_BUSCLK / HZ;
125 /*
126 * The coldfire slice timer (SLT) runs from STCNT to 0 included,
127 * then STCNT again and so on. It counts thus actually
128 * STCNT + 1 steps for 1 tick, not STCNT. So if you want
129 * n cycles, initialize STCNT with n - 1.
130 */
131 __raw_writel(mcfslt_cycles_per_jiffy - 1, TA(MCFSLT_STCNT));
132 __raw_writel(MCFSLT_SCR_RUN | MCFSLT_SCR_IEN | MCFSLT_SCR_TEN,
133 TA(MCFSLT_SCR));
134 /* initialize mcfslt_cnt knowing that slice timers count down */
135 mcfslt_cnt = mcfslt_cycles_per_jiffy;
136
137 setup_irq(MCF_IRQ_TIMER, &mcfslt_timer_irq);
138
139 mcfslt_clk.mult = clocksource_hz2mult(MCF_BUSCLK, mcfslt_clk.shift);
140 clocksource_register(&mcfslt_clk);
141
142#ifdef CONFIG_HIGHPROFILE
143 mcfslt_profile_init();
144#endif
145}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-11 00:20:19 -0500