diff options
| author | Will Simoneau <simoneau@ele.uri.edu> | 2011-07-16 13:45:12 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2011-07-16 13:45:12 -0400 |
| commit | 1ef48593bd6a508984d1270a1075532628bfd9c8 (patch) | |
| tree | 4cc0cdc07616becf7f60e5fa7438c916d30f6dbe /arch | |
| parent | 6d999da4d2610460fc5f5ce498f1483b40cc6679 (diff) | |
sparc: sun4m SMP: fix wrong shift instruction in IPI handler
This shift instruction appears to be shifting in the wrong direction.
Without this change, my SparcStation-20MP hangs just after bringing up
the second CPU:
Entering SMP Mode...
Starting CPU 2 at f02b4e90
Brought up 2 CPUs
Total of 2 processors activated (99.52 BogoMIPS).
*** stuck ***
Signed-off-by: Will Simoneau <simoneau@ele.uri.edu>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/sparc/kernel/entry.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/sparc/kernel/entry.S b/arch/sparc/kernel/entry.S index 9fe08a1ea6c6..f445e98463e6 100644 --- a/arch/sparc/kernel/entry.S +++ b/arch/sparc/kernel/entry.S | |||
| @@ -293,7 +293,7 @@ maybe_smp4m_msg: | |||
| 293 | WRITE_PAUSE | 293 | WRITE_PAUSE |
| 294 | wr %l4, PSR_ET, %psr | 294 | wr %l4, PSR_ET, %psr |
| 295 | WRITE_PAUSE | 295 | WRITE_PAUSE |
| 296 | sll %o3, 28, %o2 ! shift for simpler checks below | 296 | srl %o3, 28, %o2 ! shift for simpler checks below |
| 297 | maybe_smp4m_msg_check_single: | 297 | maybe_smp4m_msg_check_single: |
| 298 | andcc %o2, 0x1, %g0 | 298 | andcc %o2, 0x1, %g0 |
| 299 | beq,a maybe_smp4m_msg_check_mask | 299 | beq,a maybe_smp4m_msg_check_mask |