diff options
author | Peter Horton <phorton@bitbox.co.uk> | 2010-12-03 12:07:28 -0500 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2010-12-14 03:54:35 -0500 |
commit | f25972233fbe4b60dc4b514def4caf40aa1bb85a (patch) | |
tree | 1c1927bde94052d72f240acffd545439b75395d9 /arch | |
parent | 2c1f4672f0711e7f23ae49cbb7541088126fe576 (diff) |
mx51: add SSI3
Add SSI3 to MX51
Signed-off-by: Peter Horton <phorton@bitbox.co.uk>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx5/clock-mx51-mx53.c | 5 | ||||
-rw-r--r-- | arch/arm/plat-mxc/devices/platform-imx-ssi.c | 1 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx51.h | 12 |
3 files changed, 12 insertions, 6 deletions
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c index ed26de68a996..9fc65bbc9d77 100644 --- a/arch/arm/mach-mx5/clock-mx51-mx53.c +++ b/arch/arm/mach-mx5/clock-mx51-mx53.c | |||
@@ -1040,6 +1040,10 @@ DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET, | |||
1040 | NULL, NULL, &ipg_clk, NULL); | 1040 | NULL, NULL, &ipg_clk, NULL); |
1041 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, | 1041 | DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, |
1042 | NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); | 1042 | NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); |
1043 | DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET, | ||
1044 | NULL, NULL, &ipg_clk, NULL); | ||
1045 | DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET, | ||
1046 | NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk); | ||
1043 | 1047 | ||
1044 | /* eCSPI */ | 1048 | /* eCSPI */ |
1045 | DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, | 1049 | DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, |
@@ -1099,6 +1103,7 @@ static struct clk_lookup mx51_lookups[] = { | |||
1099 | _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) | 1103 | _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) |
1100 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) | 1104 | _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) |
1101 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) | 1105 | _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) |
1106 | _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk) | ||
1102 | _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) | 1107 | _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) |
1103 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) | 1108 | _REGISTER_CLOCK(NULL, "ckih", ckih_clk) |
1104 | _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) | 1109 | _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) |
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c index ac3d57239bed..2569c8d8a2ef 100644 --- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c +++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c | |||
@@ -72,6 +72,7 @@ const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { | |||
72 | imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) | 72 | imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) |
73 | imx51_imx_ssi_data_entry(0, 1), | 73 | imx51_imx_ssi_data_entry(0, 1), |
74 | imx51_imx_ssi_data_entry(1, 2), | 74 | imx51_imx_ssi_data_entry(1, 2), |
75 | imx51_imx_ssi_data_entry(2, 3), | ||
75 | }; | 76 | }; |
76 | #endif /* ifdef CONFIG_SOC_IMX51 */ | 77 | #endif /* ifdef CONFIG_SOC_IMX51 */ |
77 | 78 | ||
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h index 882f1f4e7f29..fa3a2a5d3e3e 100644 --- a/arch/arm/plat-mxc/include/mach/mx51.h +++ b/arch/arm/plat-mxc/include/mach/mx51.h | |||
@@ -109,7 +109,7 @@ | |||
109 | #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) | 109 | #define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) |
110 | #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) | 110 | #define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) |
111 | #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) | 111 | #define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) |
112 | #define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) | 112 | #define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) |
113 | #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) | 113 | #define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) |
114 | #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) | 114 | #define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) |
115 | #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) | 115 | #define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) |
@@ -223,9 +223,9 @@ | |||
223 | #define MX51_DMA_REQ_EMI_WR 32 | 223 | #define MX51_DMA_REQ_EMI_WR 32 |
224 | #define MX51_DMA_REQ_CTI2_1 33 | 224 | #define MX51_DMA_REQ_CTI2_1 33 |
225 | #define MX51_DMA_REQ_EPIT2 34 | 225 | #define MX51_DMA_REQ_EPIT2 34 |
226 | #define MX51_DMA_REQ_SSI3_RX2 35 | 226 | #define MX51_DMA_REQ_SSI3_RX1 35 |
227 | #define MX51_DMA_REQ_IPU 36 | 227 | #define MX51_DMA_REQ_IPU 36 |
228 | #define MX51_DMA_REQ_SSI3_TX2 37 | 228 | #define MX51_DMA_REQ_SSI3_TX1 37 |
229 | #define MX51_DMA_REQ_CSPI_RX 38 | 229 | #define MX51_DMA_REQ_CSPI_RX 38 |
230 | #define MX51_DMA_REQ_CSPI_TX 39 | 230 | #define MX51_DMA_REQ_CSPI_TX 39 |
231 | #define MX51_DMA_REQ_SDHC3 40 | 231 | #define MX51_DMA_REQ_SDHC3 40 |
@@ -234,8 +234,8 @@ | |||
234 | #define MX51_DMA_REQ_UART3_RX 43 | 234 | #define MX51_DMA_REQ_UART3_RX 43 |
235 | #define MX51_DMA_REQ_UART3_TX 44 | 235 | #define MX51_DMA_REQ_UART3_TX 44 |
236 | #define MX51_DMA_REQ_SPDIF 45 | 236 | #define MX51_DMA_REQ_SPDIF 45 |
237 | #define MX51_DMA_REQ_SSI3_RX1 46 | 237 | #define MX51_DMA_REQ_SSI3_RX0 46 |
238 | #define MX51_DMA_REQ_SSI3_TX1 47 | 238 | #define MX51_DMA_REQ_SSI3_TX0 47 |
239 | 239 | ||
240 | /* | 240 | /* |
241 | * Interrupt numbers | 241 | * Interrupt numbers |
@@ -337,7 +337,7 @@ | |||
337 | #define MX51_MXC_INT_FIRI 93 | 337 | #define MX51_MXC_INT_FIRI 93 |
338 | #define MX51_MXC_INT_PWM2 94 | 338 | #define MX51_MXC_INT_PWM2 94 |
339 | #define MX51_MXC_INT_SLIM_EXP 95 | 339 | #define MX51_MXC_INT_SLIM_EXP 95 |
340 | #define MX51_MXC_INT_SSI3 96 | 340 | #define MX51_INT_SSI3 96 |
341 | #define MX51_MXC_INT_EMI_BOOT 97 | 341 | #define MX51_MXC_INT_EMI_BOOT 97 |
342 | #define MX51_MXC_INT_CTI1_TG3 98 | 342 | #define MX51_MXC_INT_CTI1_TG3 98 |
343 | #define MX51_MXC_INT_SMC_RX 99 | 343 | #define MX51_MXC_INT_SMC_RX 99 |