diff options
author | David S. Miller <davem@sunset.davemloft.net> | 2007-03-09 01:46:02 -0500 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-04-26 04:55:15 -0400 |
commit | 8d3aee937596d2ca6676c2c27789751445bf0bc9 (patch) | |
tree | b22a333a9947ab94d8c35c13b4989cde53630ac9 /arch | |
parent | 0bae5f81b6f8130f5197e59b0e2ad6820c766b2b (diff) |
[SPARC64]: Kill pci_controller->base_address_update().
Implemented but never actually used.
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/sparc64/kernel/pci_psycho.c | 45 | ||||
-rw-r--r-- | arch/sparc64/kernel/pci_sabre.c | 46 | ||||
-rw-r--r-- | arch/sparc64/kernel/pci_schizo.c | 45 | ||||
-rw-r--r-- | arch/sparc64/kernel/pci_sun4v.c | 46 |
4 files changed, 0 insertions, 182 deletions
diff --git a/arch/sparc64/kernel/pci_psycho.c b/arch/sparc64/kernel/pci_psycho.c index c3f212725b04..64bd3579f1ca 100644 --- a/arch/sparc64/kernel/pci_psycho.c +++ b/arch/sparc64/kernel/pci_psycho.c | |||
@@ -894,50 +894,6 @@ static void psycho_register_error_handlers(struct pci_controller_info *p) | |||
894 | } | 894 | } |
895 | 895 | ||
896 | /* PSYCHO boot time probing and initialization. */ | 896 | /* PSYCHO boot time probing and initialization. */ |
897 | static void psycho_base_address_update(struct pci_dev *pdev, int resource) | ||
898 | { | ||
899 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | ||
900 | struct resource *res, *root; | ||
901 | u32 reg; | ||
902 | int where, size, is_64bit; | ||
903 | |||
904 | res = &pdev->resource[resource]; | ||
905 | if (resource < 6) { | ||
906 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | ||
907 | } else if (resource == PCI_ROM_RESOURCE) { | ||
908 | where = pdev->rom_base_reg; | ||
909 | } else { | ||
910 | /* Somebody might have asked allocation of a non-standard resource */ | ||
911 | return; | ||
912 | } | ||
913 | |||
914 | is_64bit = 0; | ||
915 | if (res->flags & IORESOURCE_IO) | ||
916 | root = &pbm->io_space; | ||
917 | else { | ||
918 | root = &pbm->mem_space; | ||
919 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | ||
920 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | ||
921 | is_64bit = 1; | ||
922 | } | ||
923 | |||
924 | size = res->end - res->start; | ||
925 | pci_read_config_dword(pdev, where, ®); | ||
926 | reg = ((reg & size) | | ||
927 | (((u32)(res->start - root->start)) & ~size)); | ||
928 | if (resource == PCI_ROM_RESOURCE) { | ||
929 | reg |= PCI_ROM_ADDRESS_ENABLE; | ||
930 | res->flags |= IORESOURCE_ROM_ENABLE; | ||
931 | } | ||
932 | pci_write_config_dword(pdev, where, reg); | ||
933 | |||
934 | /* This knows that the upper 32-bits of the address | ||
935 | * must be zero. Our PCI common layer enforces this. | ||
936 | */ | ||
937 | if (is_64bit) | ||
938 | pci_write_config_dword(pdev, where + 4, 0); | ||
939 | } | ||
940 | |||
941 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) | 897 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
942 | { | 898 | { |
943 | u8 *addr; | 899 | u8 *addr; |
@@ -1209,7 +1165,6 @@ void psycho_init(struct device_node *dp, char *model_name) | |||
1209 | p->index = pci_num_controllers++; | 1165 | p->index = pci_num_controllers++; |
1210 | p->pbms_same_domain = 0; | 1166 | p->pbms_same_domain = 0; |
1211 | p->scan_bus = psycho_scan_bus; | 1167 | p->scan_bus = psycho_scan_bus; |
1212 | p->base_address_update = psycho_base_address_update; | ||
1213 | p->pci_ops = &psycho_ops; | 1168 | p->pci_ops = &psycho_ops; |
1214 | 1169 | ||
1215 | prop = of_find_property(dp, "reg", NULL); | 1170 | prop = of_find_property(dp, "reg", NULL); |
diff --git a/arch/sparc64/kernel/pci_sabre.c b/arch/sparc64/kernel/pci_sabre.c index 64cdce81d86a..f3ec7bdacdc0 100644 --- a/arch/sparc64/kernel/pci_sabre.c +++ b/arch/sparc64/kernel/pci_sabre.c | |||
@@ -862,51 +862,6 @@ static void sabre_register_error_handlers(struct pci_controller_info *p) | |||
862 | sabre_write(base + SABRE_PCICTRL, tmp); | 862 | sabre_write(base + SABRE_PCICTRL, tmp); |
863 | } | 863 | } |
864 | 864 | ||
865 | static void sabre_base_address_update(struct pci_dev *pdev, int resource) | ||
866 | { | ||
867 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | ||
868 | struct resource *res; | ||
869 | unsigned long base; | ||
870 | u32 reg; | ||
871 | int where, size, is_64bit; | ||
872 | |||
873 | res = &pdev->resource[resource]; | ||
874 | if (resource < 6) { | ||
875 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | ||
876 | } else if (resource == PCI_ROM_RESOURCE) { | ||
877 | where = pdev->rom_base_reg; | ||
878 | } else { | ||
879 | /* Somebody might have asked allocation of a non-standard resource */ | ||
880 | return; | ||
881 | } | ||
882 | |||
883 | is_64bit = 0; | ||
884 | if (res->flags & IORESOURCE_IO) | ||
885 | base = pbm->controller_regs + SABRE_IOSPACE; | ||
886 | else { | ||
887 | base = pbm->controller_regs + SABRE_MEMSPACE; | ||
888 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | ||
889 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | ||
890 | is_64bit = 1; | ||
891 | } | ||
892 | |||
893 | size = res->end - res->start; | ||
894 | pci_read_config_dword(pdev, where, ®); | ||
895 | reg = ((reg & size) | | ||
896 | (((u32)(res->start - base)) & ~size)); | ||
897 | if (resource == PCI_ROM_RESOURCE) { | ||
898 | reg |= PCI_ROM_ADDRESS_ENABLE; | ||
899 | res->flags |= IORESOURCE_ROM_ENABLE; | ||
900 | } | ||
901 | pci_write_config_dword(pdev, where, reg); | ||
902 | |||
903 | /* This knows that the upper 32-bits of the address | ||
904 | * must be zero. Our PCI common layer enforces this. | ||
905 | */ | ||
906 | if (is_64bit) | ||
907 | pci_write_config_dword(pdev, where + 4, 0); | ||
908 | } | ||
909 | |||
910 | static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus) | 865 | static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus) |
911 | { | 866 | { |
912 | struct pci_dev *pdev; | 867 | struct pci_dev *pdev; |
@@ -1099,7 +1054,6 @@ void sabre_init(struct device_node *dp, char *model_name) | |||
1099 | p->index = pci_num_controllers++; | 1054 | p->index = pci_num_controllers++; |
1100 | p->pbms_same_domain = 1; | 1055 | p->pbms_same_domain = 1; |
1101 | p->scan_bus = sabre_scan_bus; | 1056 | p->scan_bus = sabre_scan_bus; |
1102 | p->base_address_update = sabre_base_address_update; | ||
1103 | p->pci_ops = &sabre_ops; | 1057 | p->pci_ops = &sabre_ops; |
1104 | 1058 | ||
1105 | /* | 1059 | /* |
diff --git a/arch/sparc64/kernel/pci_schizo.c b/arch/sparc64/kernel/pci_schizo.c index ba9206eb9516..99912db4e7e8 100644 --- a/arch/sparc64/kernel/pci_schizo.c +++ b/arch/sparc64/kernel/pci_schizo.c | |||
@@ -1251,50 +1251,6 @@ static void schizo_scan_bus(struct pci_controller_info *p) | |||
1251 | schizo_register_error_handlers(p); | 1251 | schizo_register_error_handlers(p); |
1252 | } | 1252 | } |
1253 | 1253 | ||
1254 | static void schizo_base_address_update(struct pci_dev *pdev, int resource) | ||
1255 | { | ||
1256 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | ||
1257 | struct resource *res, *root; | ||
1258 | u32 reg; | ||
1259 | int where, size, is_64bit; | ||
1260 | |||
1261 | res = &pdev->resource[resource]; | ||
1262 | if (resource < 6) { | ||
1263 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | ||
1264 | } else if (resource == PCI_ROM_RESOURCE) { | ||
1265 | where = pdev->rom_base_reg; | ||
1266 | } else { | ||
1267 | /* Somebody might have asked allocation of a non-standard resource */ | ||
1268 | return; | ||
1269 | } | ||
1270 | |||
1271 | is_64bit = 0; | ||
1272 | if (res->flags & IORESOURCE_IO) | ||
1273 | root = &pbm->io_space; | ||
1274 | else { | ||
1275 | root = &pbm->mem_space; | ||
1276 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | ||
1277 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | ||
1278 | is_64bit = 1; | ||
1279 | } | ||
1280 | |||
1281 | size = res->end - res->start; | ||
1282 | pci_read_config_dword(pdev, where, ®); | ||
1283 | reg = ((reg & size) | | ||
1284 | (((u32)(res->start - root->start)) & ~size)); | ||
1285 | if (resource == PCI_ROM_RESOURCE) { | ||
1286 | reg |= PCI_ROM_ADDRESS_ENABLE; | ||
1287 | res->flags |= IORESOURCE_ROM_ENABLE; | ||
1288 | } | ||
1289 | pci_write_config_dword(pdev, where, reg); | ||
1290 | |||
1291 | /* This knows that the upper 32-bits of the address | ||
1292 | * must be zero. Our PCI common layer enforces this. | ||
1293 | */ | ||
1294 | if (is_64bit) | ||
1295 | pci_write_config_dword(pdev, where + 4, 0); | ||
1296 | } | ||
1297 | |||
1298 | #define SCHIZO_STRBUF_CONTROL (0x02800UL) | 1254 | #define SCHIZO_STRBUF_CONTROL (0x02800UL) |
1299 | #define SCHIZO_STRBUF_FLUSH (0x02808UL) | 1255 | #define SCHIZO_STRBUF_FLUSH (0x02808UL) |
1300 | #define SCHIZO_STRBUF_FSYNC (0x02810UL) | 1256 | #define SCHIZO_STRBUF_FSYNC (0x02810UL) |
@@ -1661,7 +1617,6 @@ static void __schizo_init(struct device_node *dp, char *model_name, int chip_typ | |||
1661 | 1617 | ||
1662 | p->index = pci_num_controllers++; | 1618 | p->index = pci_num_controllers++; |
1663 | p->scan_bus = schizo_scan_bus; | 1619 | p->scan_bus = schizo_scan_bus; |
1664 | p->base_address_update = schizo_base_address_update; | ||
1665 | p->pci_ops = &schizo_ops; | 1620 | p->pci_ops = &schizo_ops; |
1666 | 1621 | ||
1667 | /* Like PSYCHO we have a 2GB aligned area for memory space. */ | 1622 | /* Like PSYCHO we have a 2GB aligned area for memory space. */ |
diff --git a/arch/sparc64/kernel/pci_sun4v.c b/arch/sparc64/kernel/pci_sun4v.c index ce0417e776a1..f9cd9f620d4e 100644 --- a/arch/sparc64/kernel/pci_sun4v.c +++ b/arch/sparc64/kernel/pci_sun4v.c | |||
@@ -698,51 +698,6 @@ static void pci_sun4v_scan_bus(struct pci_controller_info *p) | |||
698 | /* XXX register error interrupt handlers XXX */ | 698 | /* XXX register error interrupt handlers XXX */ |
699 | } | 699 | } |
700 | 700 | ||
701 | static void pci_sun4v_base_address_update(struct pci_dev *pdev, int resource) | ||
702 | { | ||
703 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; | ||
704 | struct resource *res, *root; | ||
705 | u32 reg; | ||
706 | int where, size, is_64bit; | ||
707 | |||
708 | res = &pdev->resource[resource]; | ||
709 | if (resource < 6) { | ||
710 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | ||
711 | } else if (resource == PCI_ROM_RESOURCE) { | ||
712 | where = pdev->rom_base_reg; | ||
713 | } else { | ||
714 | /* Somebody might have asked allocation of a non-standard resource */ | ||
715 | return; | ||
716 | } | ||
717 | |||
718 | /* XXX 64-bit MEM handling is not %100 correct... XXX */ | ||
719 | is_64bit = 0; | ||
720 | if (res->flags & IORESOURCE_IO) | ||
721 | root = &pbm->io_space; | ||
722 | else { | ||
723 | root = &pbm->mem_space; | ||
724 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | ||
725 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | ||
726 | is_64bit = 1; | ||
727 | } | ||
728 | |||
729 | size = res->end - res->start; | ||
730 | pci_read_config_dword(pdev, where, ®); | ||
731 | reg = ((reg & size) | | ||
732 | (((u32)(res->start - root->start)) & ~size)); | ||
733 | if (resource == PCI_ROM_RESOURCE) { | ||
734 | reg |= PCI_ROM_ADDRESS_ENABLE; | ||
735 | res->flags |= IORESOURCE_ROM_ENABLE; | ||
736 | } | ||
737 | pci_write_config_dword(pdev, where, reg); | ||
738 | |||
739 | /* This knows that the upper 32-bits of the address | ||
740 | * must be zero. Our PCI common layer enforces this. | ||
741 | */ | ||
742 | if (is_64bit) | ||
743 | pci_write_config_dword(pdev, where + 4, 0); | ||
744 | } | ||
745 | |||
746 | static unsigned long probe_existing_entries(struct pci_pbm_info *pbm, | 701 | static unsigned long probe_existing_entries(struct pci_pbm_info *pbm, |
747 | struct pci_iommu *iommu) | 702 | struct pci_iommu *iommu) |
748 | { | 703 | { |
@@ -1378,7 +1333,6 @@ void sun4v_pci_init(struct device_node *dp, char *model_name) | |||
1378 | p->pbms_same_domain = 0; | 1333 | p->pbms_same_domain = 0; |
1379 | 1334 | ||
1380 | p->scan_bus = pci_sun4v_scan_bus; | 1335 | p->scan_bus = pci_sun4v_scan_bus; |
1381 | p->base_address_update = pci_sun4v_base_address_update; | ||
1382 | #ifdef CONFIG_PCI_MSI | 1336 | #ifdef CONFIG_PCI_MSI |
1383 | p->setup_msi_irq = pci_sun4v_setup_msi_irq; | 1337 | p->setup_msi_irq = pci_sun4v_setup_msi_irq; |
1384 | p->teardown_msi_irq = pci_sun4v_teardown_msi_irq; | 1338 | p->teardown_msi_irq = pci_sun4v_teardown_msi_irq; |