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authorPaul Walmsley <paul@pwsan.com>2009-01-28 14:35:06 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2009-02-08 12:50:45 -0500
commitf11fda6a9173e8e6b152ba5cb26fa20095a4c60f (patch)
tree32130aefa922d5ca9519f0a07cea238ef5000db5 /arch
parent439764cc18beb20ef409991e75e29b460db71d33 (diff)
[ARM] OMAP2/3 clock: convert remaining MPU barriers into OCP barriers
Several parts of the OMAP2/3 clock code use wmb() to try to ensure that the hardware write completes before continuing. This approach is problematic: wmb() only ensures that the write leaves the ARM. It does not ensure that the write actually reaches the endpoint device. The endpoint device in this case - either the PRM, CM, or SCM - is three interconnects away from the ARM - and the final interconnect is low-speed. And the OCP interconnects will post the write, and who knows how long that will take to complete. So the wmb() is not what we want. Worse, the wmb() is indiscriminate; it causes the ARM to flush any other unrelated buffered writes and wait for the local interconnect to acknowledge them - potentially very expensive. Fix this by converting the wmb()s into readbacks of the same PRM/CM/SCM register. Since the PRM/CM/SCM devices use a single OCP thread, this will cause the MPU to block while waiting for posted writes to that device to complete. linux-omap source commit is 260f5487848681b4d8ea7430a709a601bbcb21d1. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap2/clock.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 7f12230fef73..666274a8b10d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -334,7 +334,7 @@ static int omap2_dflt_clk_enable(struct clk *clk)
334 else 334 else
335 v |= (1 << clk->enable_bit); 335 v |= (1 << clk->enable_bit);
336 __raw_writel(v, clk->enable_reg); 336 __raw_writel(v, clk->enable_reg);
337 wmb(); 337 v = __raw_readl(clk->enable_reg); /* OCP barrier */
338 338
339 return 0; 339 return 0;
340} 340}
@@ -703,7 +703,7 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
703 v &= ~clk->clksel_mask; 703 v &= ~clk->clksel_mask;
704 v |= field_val << __ffs(clk->clksel_mask); 704 v |= field_val << __ffs(clk->clksel_mask);
705 __raw_writel(v, clk->clksel_reg); 705 __raw_writel(v, clk->clksel_reg);
706 wmb(); 706 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
707 707
708 clk->rate = clk->parent->rate / new_div; 708 clk->rate = clk->parent->rate / new_div;
709 709
@@ -788,7 +788,7 @@ int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
788 v &= ~clk->clksel_mask; 788 v &= ~clk->clksel_mask;
789 v |= field_val << __ffs(clk->clksel_mask); 789 v |= field_val << __ffs(clk->clksel_mask);
790 __raw_writel(v, clk->clksel_reg); 790 __raw_writel(v, clk->clksel_reg);
791 wmb(); 791 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
792 792
793 _omap2xxx_clk_commit(clk); 793 _omap2xxx_clk_commit(clk);
794 794