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authorKuninori Morimoto <kuninori.morimoto.gx@renesas.com>2013-03-04 02:11:41 -0500
committerSimon Horman <horms+renesas@verge.net.au>2013-03-12 13:13:22 -0400
commitdbe95ad00b95a8baaedd87ce84996d95e5811055 (patch)
tree60bb8b337481d6f71313f276f643db634641a47b /arch
parentabe0e14b0b51b26bdf80ccaf4d7ee99a4b261af0 (diff)
ARM: shmobile: r8a7779: use gic_iid macro
"ARM: shmobile: add gic_iid macro for ICCIAR / interrupt ID" enabled to use gic_iid macro. This patch exchange current GIC interrupt setting from gic_spi() to gic_iid() Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> [ horms+renesas@verge.net.au: Updated git commit id in changelog ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c24
1 files changed, 12 insertions, 12 deletions
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 932285841b71..0068b9f85bc0 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -92,7 +92,7 @@ static struct plat_sci_port scif0_platform_data = {
92 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 92 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
93 .scbrr_algo_id = SCBRR_ALGO_2, 93 .scbrr_algo_id = SCBRR_ALGO_2,
94 .type = PORT_SCIF, 94 .type = PORT_SCIF,
95 .irqs = SCIx_IRQ_MUXED(gic_spi(88)), 95 .irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
96}; 96};
97 97
98static struct platform_device scif0_device = { 98static struct platform_device scif0_device = {
@@ -109,7 +109,7 @@ static struct plat_sci_port scif1_platform_data = {
109 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 109 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
110 .scbrr_algo_id = SCBRR_ALGO_2, 110 .scbrr_algo_id = SCBRR_ALGO_2,
111 .type = PORT_SCIF, 111 .type = PORT_SCIF,
112 .irqs = SCIx_IRQ_MUXED(gic_spi(89)), 112 .irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
113}; 113};
114 114
115static struct platform_device scif1_device = { 115static struct platform_device scif1_device = {
@@ -126,7 +126,7 @@ static struct plat_sci_port scif2_platform_data = {
126 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 126 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
127 .scbrr_algo_id = SCBRR_ALGO_2, 127 .scbrr_algo_id = SCBRR_ALGO_2,
128 .type = PORT_SCIF, 128 .type = PORT_SCIF,
129 .irqs = SCIx_IRQ_MUXED(gic_spi(90)), 129 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
130}; 130};
131 131
132static struct platform_device scif2_device = { 132static struct platform_device scif2_device = {
@@ -143,7 +143,7 @@ static struct plat_sci_port scif3_platform_data = {
143 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 143 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
144 .scbrr_algo_id = SCBRR_ALGO_2, 144 .scbrr_algo_id = SCBRR_ALGO_2,
145 .type = PORT_SCIF, 145 .type = PORT_SCIF,
146 .irqs = SCIx_IRQ_MUXED(gic_spi(91)), 146 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
147}; 147};
148 148
149static struct platform_device scif3_device = { 149static struct platform_device scif3_device = {
@@ -160,7 +160,7 @@ static struct plat_sci_port scif4_platform_data = {
160 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 160 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
161 .scbrr_algo_id = SCBRR_ALGO_2, 161 .scbrr_algo_id = SCBRR_ALGO_2,
162 .type = PORT_SCIF, 162 .type = PORT_SCIF,
163 .irqs = SCIx_IRQ_MUXED(gic_spi(92)), 163 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
164}; 164};
165 165
166static struct platform_device scif4_device = { 166static struct platform_device scif4_device = {
@@ -177,7 +177,7 @@ static struct plat_sci_port scif5_platform_data = {
177 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1, 177 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
178 .scbrr_algo_id = SCBRR_ALGO_2, 178 .scbrr_algo_id = SCBRR_ALGO_2,
179 .type = PORT_SCIF, 179 .type = PORT_SCIF,
180 .irqs = SCIx_IRQ_MUXED(gic_spi(93)), 180 .irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
181}; 181};
182 182
183static struct platform_device scif5_device = { 183static struct platform_device scif5_device = {
@@ -204,7 +204,7 @@ static struct resource tmu00_resources[] = {
204 .flags = IORESOURCE_MEM, 204 .flags = IORESOURCE_MEM,
205 }, 205 },
206 [1] = { 206 [1] = {
207 .start = gic_spi(32), 207 .start = gic_iid(0x40),
208 .flags = IORESOURCE_IRQ, 208 .flags = IORESOURCE_IRQ,
209 }, 209 },
210}; 210};
@@ -234,7 +234,7 @@ static struct resource tmu01_resources[] = {
234 .flags = IORESOURCE_MEM, 234 .flags = IORESOURCE_MEM,
235 }, 235 },
236 [1] = { 236 [1] = {
237 .start = gic_spi(33), 237 .start = gic_iid(0x41),
238 .flags = IORESOURCE_IRQ, 238 .flags = IORESOURCE_IRQ,
239 }, 239 },
240}; 240};
@@ -256,7 +256,7 @@ static struct resource rcar_i2c0_res[] = {
256 .end = 0xffc70fff, 256 .end = 0xffc70fff,
257 .flags = IORESOURCE_MEM, 257 .flags = IORESOURCE_MEM,
258 }, { 258 }, {
259 .start = gic_spi(79), 259 .start = gic_iid(0x6f),
260 .flags = IORESOURCE_IRQ, 260 .flags = IORESOURCE_IRQ,
261 }, 261 },
262}; 262};
@@ -274,7 +274,7 @@ static struct resource rcar_i2c1_res[] = {
274 .end = 0xffc71fff, 274 .end = 0xffc71fff,
275 .flags = IORESOURCE_MEM, 275 .flags = IORESOURCE_MEM,
276 }, { 276 }, {
277 .start = gic_spi(82), 277 .start = gic_iid(0x72),
278 .flags = IORESOURCE_IRQ, 278 .flags = IORESOURCE_IRQ,
279 }, 279 },
280}; 280};
@@ -292,7 +292,7 @@ static struct resource rcar_i2c2_res[] = {
292 .end = 0xffc72fff, 292 .end = 0xffc72fff,
293 .flags = IORESOURCE_MEM, 293 .flags = IORESOURCE_MEM,
294 }, { 294 }, {
295 .start = gic_spi(80), 295 .start = gic_iid(0x70),
296 .flags = IORESOURCE_IRQ, 296 .flags = IORESOURCE_IRQ,
297 }, 297 },
298}; 298};
@@ -310,7 +310,7 @@ static struct resource rcar_i2c3_res[] = {
310 .end = 0xffc73fff, 310 .end = 0xffc73fff,
311 .flags = IORESOURCE_MEM, 311 .flags = IORESOURCE_MEM,
312 }, { 312 }, {
313 .start = gic_spi(81), 313 .start = gic_iid(0x71),
314 .flags = IORESOURCE_IRQ, 314 .flags = IORESOURCE_IRQ,
315 }, 315 },
316}; 316};