diff options
author | Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2011-11-10 21:46:56 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2011-11-11 02:56:27 -0500 |
commit | b6b37e250558a8348ba9a22ba27376d22bca2c5c (patch) | |
tree | 92b7d6cb53a942503eb26910e8a3db75b6fa3897 /arch | |
parent | d55c9a97f80a7ad64f7c7eab5fb447a8d9a1532a (diff) |
ARM: mach-shmobile: bonito: Add dip-switch selector
devices enable/disable are controled by dip-switch on bonito board.
If bonito core board is connected to base board,
you can check the settings from FPGA.
This patch adds basic code and controls SCIFA5 settings
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-shmobile/board-bonito.c | 88 |
1 files changed, 71 insertions, 17 deletions
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c index 901d7457973a..efaa5feb39b8 100644 --- a/arch/arm/mach-shmobile/board-bonito.c +++ b/arch/arm/mach-shmobile/board-bonito.c | |||
@@ -56,8 +56,21 @@ | |||
56 | */ | 56 | */ |
57 | 57 | ||
58 | /* | 58 | /* |
59 | * SCIFA5 (CN42) | ||
60 | * | ||
61 | * S38.3 = ON | ||
62 | * S39.6 = ON | ||
63 | * S43.1 = ON | ||
64 | */ | ||
65 | |||
66 | /* | ||
59 | * FPGA | 67 | * FPGA |
60 | */ | 68 | */ |
69 | #define BUSSWMR1 0x0070 | ||
70 | #define BUSSWMR2 0x0072 | ||
71 | #define BUSSWMR3 0x0074 | ||
72 | #define BUSSWMR4 0x0076 | ||
73 | |||
61 | #define A1MDSR 0x10E0 | 74 | #define A1MDSR 0x10E0 |
62 | #define BVERR 0x1100 | 75 | #define BVERR 0x1100 |
63 | static u16 bonito_fpga_read(u32 offset) | 76 | static u16 bonito_fpga_read(u32 offset) |
@@ -71,9 +84,15 @@ static void bonito_fpga_write(u32 offset, u16 val) | |||
71 | } | 84 | } |
72 | 85 | ||
73 | /* | 86 | /* |
74 | * devices | 87 | * core board devices |
75 | */ | 88 | */ |
76 | static struct platform_device *bonito_devices[] __initdata = { | 89 | static struct platform_device *bonito_core_devices[] __initdata = { |
90 | }; | ||
91 | |||
92 | /* | ||
93 | * base board devices | ||
94 | */ | ||
95 | static struct platform_device *bonito_base_devices[] __initdata = { | ||
77 | }; | 96 | }; |
78 | 97 | ||
79 | /* | 98 | /* |
@@ -126,26 +145,18 @@ static void __init bonito_map_io(void) | |||
126 | /* | 145 | /* |
127 | * board init | 146 | * board init |
128 | */ | 147 | */ |
148 | #define BIT_ON(sw, bit) (sw & (1 << bit)) | ||
149 | #define BIT_OFF(sw, bit) (!(sw & (1 << bit))) | ||
150 | |||
129 | static void __init bonito_init(void) | 151 | static void __init bonito_init(void) |
130 | { | 152 | { |
131 | u16 val; | 153 | u16 val; |
132 | 154 | ||
133 | r8a7740_pinmux_init(); | 155 | r8a7740_pinmux_init(); |
134 | 156 | ||
135 | /* FPGA */ | 157 | /* |
136 | gpio_request(GPIO_FN_CS5B, NULL); | 158 | * core board settings |
137 | gpio_request(GPIO_FN_CS6A, NULL); | 159 | */ |
138 | gpio_request(GPIO_FN_CS5A_PORT105, NULL); | ||
139 | gpio_request(GPIO_FN_IRQ10, NULL); | ||
140 | |||
141 | val = bonito_fpga_read(BVERR); | ||
142 | pr_info("bonito version: cpu %02x, base %02x\n", | ||
143 | ((val >> 8) & 0xFF), | ||
144 | ((val >> 0) & 0xFF)); | ||
145 | |||
146 | /* SCIFA5 */ | ||
147 | gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL); | ||
148 | gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL); | ||
149 | 160 | ||
150 | #ifdef CONFIG_CACHE_L2X0 | 161 | #ifdef CONFIG_CACHE_L2X0 |
151 | /* Early BRESP enable, Shared attribute override enable, 32K*8way */ | 162 | /* Early BRESP enable, Shared attribute override enable, 32K*8way */ |
@@ -153,7 +164,50 @@ static void __init bonito_init(void) | |||
153 | #endif | 164 | #endif |
154 | 165 | ||
155 | r8a7740_add_standard_devices(); | 166 | r8a7740_add_standard_devices(); |
156 | platform_add_devices(bonito_devices, ARRAY_SIZE(bonito_devices)); | 167 | |
168 | platform_add_devices(bonito_core_devices, | ||
169 | ARRAY_SIZE(bonito_core_devices)); | ||
170 | |||
171 | /* | ||
172 | * base board settings | ||
173 | */ | ||
174 | gpio_request(GPIO_PORT176, NULL); | ||
175 | gpio_direction_input(GPIO_PORT176); | ||
176 | if (!gpio_get_value(GPIO_PORT176)) { | ||
177 | u16 bsw2; | ||
178 | u16 bsw3; | ||
179 | u16 bsw4; | ||
180 | |||
181 | /* | ||
182 | * FPGA | ||
183 | */ | ||
184 | gpio_request(GPIO_FN_CS5B, NULL); | ||
185 | gpio_request(GPIO_FN_CS6A, NULL); | ||
186 | gpio_request(GPIO_FN_CS5A_PORT105, NULL); | ||
187 | gpio_request(GPIO_FN_IRQ10, NULL); | ||
188 | |||
189 | val = bonito_fpga_read(BVERR); | ||
190 | pr_info("bonito version: cpu %02x, base %02x\n", | ||
191 | ((val >> 8) & 0xFF), | ||
192 | ((val >> 0) & 0xFF)); | ||
193 | |||
194 | bsw2 = bonito_fpga_read(BUSSWMR2); | ||
195 | bsw3 = bonito_fpga_read(BUSSWMR3); | ||
196 | bsw4 = bonito_fpga_read(BUSSWMR4); | ||
197 | |||
198 | /* | ||
199 | * SCIFA5 (CN42) | ||
200 | */ | ||
201 | if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */ | ||
202 | BIT_OFF(bsw3, 9) && /* S39.6 = ON */ | ||
203 | BIT_OFF(bsw4, 4)) { /* S43.1 = ON */ | ||
204 | gpio_request(GPIO_FN_SCIFA5_TXD_PORT91, NULL); | ||
205 | gpio_request(GPIO_FN_SCIFA5_RXD_PORT92, NULL); | ||
206 | } | ||
207 | |||
208 | platform_add_devices(bonito_base_devices, | ||
209 | ARRAY_SIZE(bonito_base_devices)); | ||
210 | } | ||
157 | } | 211 | } |
158 | 212 | ||
159 | static void __init bonito_timer_init(void) | 213 | static void __init bonito_timer_init(void) |