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authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2008-07-10 11:33:08 -0400
committerRalf Baechle <ralf@linux-mips.org>2008-07-15 13:44:35 -0400
commit89d63fe179520b11f54de1f26755b7444c79e73a (patch)
treefede06c5648335652c864fc35c951d991cbab183 /arch
parent22b1d707ffc99faebd86257ad19d5bb9fc624734 (diff)
[MIPS] TXx9: Reorganize PCI code
Split out PCIC dependent code and SoC dependent code from board dependent code. Now TX4927 PCIC code is independent from TX4927/TX4938 SoC code. Also fix some build problems on CONFIG_PCI=n. As a bonus, "FPCIB0 Backplane Support" is available for all TX39/TX49 boards and PCI66 support is available for all TX49 boards. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/Kconfig3
-rw-r--r--arch/mips/pci/Makefile8
-rw-r--r--arch/mips/pci/fixup-jmr3927.c25
-rw-r--r--arch/mips/pci/fixup-rbtx4927.c112
-rw-r--r--arch/mips/pci/fixup-rbtx4938.c52
-rw-r--r--arch/mips/pci/ops-tx3927.c87
-rw-r--r--arch/mips/pci/ops-tx4927.c514
-rw-r--r--arch/mips/pci/ops-tx4938.c214
-rw-r--r--arch/mips/pci/pci-jmr3927.c58
-rw-r--r--arch/mips/pci/pci-tx4927.c83
-rw-r--r--arch/mips/pci/pci-tx4938.c134
-rw-r--r--arch/mips/txx9/Kconfig11
-rw-r--r--arch/mips/txx9/generic/Makefile2
-rw-r--r--arch/mips/txx9/generic/pci.c377
-rw-r--r--arch/mips/txx9/generic/setup.c51
-rw-r--r--arch/mips/txx9/jmr3927/irq.c2
-rw-r--r--arch/mips/txx9/jmr3927/setup.c108
-rw-r--r--arch/mips/txx9/rbtx4927/irq.c20
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c499
-rw-r--r--arch/mips/txx9/rbtx4938/setup.c667
20 files changed, 1397 insertions, 1630 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 3202960f7597..2ea6fff88811 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -575,7 +575,7 @@ config TOSHIBA_RBTX4927
575 select HW_HAS_PCI 575 select HW_HAS_PCI
576 select IRQ_CPU 576 select IRQ_CPU
577 select IRQ_TXX9 577 select IRQ_TXX9
578 select I8259 if TOSHIBA_FPCIB0 578 select PCI_TX4927
579 select SWAP_IO_SPACE 579 select SWAP_IO_SPACE
580 select SYS_HAS_CPU_TX49XX 580 select SYS_HAS_CPU_TX49XX
581 select SYS_SUPPORTS_32BIT_KERNEL 581 select SYS_SUPPORTS_32BIT_KERNEL
@@ -598,6 +598,7 @@ config TOSHIBA_RBTX4938
598 select HW_HAS_PCI 598 select HW_HAS_PCI
599 select IRQ_CPU 599 select IRQ_CPU
600 select IRQ_TXX9 600 select IRQ_TXX9
601 select PCI_TX4927
601 select SWAP_IO_SPACE 602 select SWAP_IO_SPACE
602 select SYS_HAS_CPU_TX49XX 603 select SYS_HAS_CPU_TX49XX
603 select SYS_SUPPORTS_32BIT_KERNEL 604 select SYS_SUPPORTS_32BIT_KERNEL
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 4608e43de28c..908764878ac8 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -15,6 +15,8 @@ obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o 15obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
16obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o 16obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
17obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o 17obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o
18obj-$(CONFIG_PCI_TX3927) += ops-tx3927.o
19obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o
18 20
19# 21#
20# These are still pretty much in the old state, watch, go blind. 22# These are still pretty much in the old state, watch, go blind.
@@ -41,9 +43,9 @@ obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o
41obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o 43obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o
42obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o 44obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o
43obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o 45obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o
44obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o pci-jmr3927.o 46obj-$(CONFIG_TOSHIBA_JMR3927) += fixup-jmr3927.o
45obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o ops-tx4927.o 47obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o pci-tx4927.o pci-tx4938.o
46obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o ops-tx4938.o 48obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o pci-tx4938.o
47obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o 49obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
48obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o 50obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
49obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o 51obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c
index 41dcd6a3aae5..d5edaf21e088 100644
--- a/arch/mips/pci/fixup-jmr3927.c
+++ b/arch/mips/pci/fixup-jmr3927.c
@@ -28,36 +28,31 @@
28 * 675 Mass Ave, Cambridge, MA 02139, USA. 28 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 */ 29 */
30#include <linux/types.h> 30#include <linux/types.h>
31#include <linux/pci.h> 31#include <asm/txx9/pci.h>
32#include <linux/init.h>
33
34#include <asm/txx9/jmr3927.h> 32#include <asm/txx9/jmr3927.h>
35 33
36int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 34int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
37{ 35{
38 unsigned char irq = pin; 36 unsigned char irq = pin;
39 37
40 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
41 if (dev->vendor == PCI_VENDOR_ID_EFAR &&
42 dev->device == PCI_DEVICE_ID_EFAR_SLC90E66_1)
43 return irq;
44 /* IRQ rotation (PICMG) */ 38 /* IRQ rotation (PICMG) */
45 irq--; /* 0-3 */ 39 irq--; /* 0-3 */
46 if (dev->bus->parent == NULL && 40 if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
47 slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(23)) {
48 /* PCI CardSlot (IDSEL=A23, DevNu=12) */ 41 /* PCI CardSlot (IDSEL=A23, DevNu=12) */
49 /* PCIA => PCIC (IDSEL=A23) */ 42 /* PCIA => PCIC (IDSEL=A23) */
50 /* NOTE: JMR3927 JP1 must be set to OPEN */ 43 /* NOTE: JMR3927 JP1 must be set to OPEN */
51 irq = (irq + 2) % 4; 44 irq = (irq + 2) % 4;
52 } else if (dev->bus->parent == NULL && 45 } else if (slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
53 slot == TX3927_PCIC_IDSEL_AD_TO_SLOT(22)) {
54 /* PCI CardSlot (IDSEL=A22, DevNu=11) */ 46 /* PCI CardSlot (IDSEL=A22, DevNu=11) */
55 /* PCIA => PCIA (IDSEL=A22) */ 47 /* PCIA => PCIA (IDSEL=A22) */
56 /* NOTE: JMR3927 JP1 must be set to OPEN */ 48 /* NOTE: JMR3927 JP1 must be set to OPEN */
57 irq = (irq + 0) % 4; 49 irq = (irq + 0) % 4;
58 } else { 50 } else {
59 /* PCI Backplane */ 51 /* PCI Backplane */
60 irq = (irq + 3 + slot) % 4; 52 if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
53 irq = (irq + 33 - slot) % 4;
54 else
55 irq = (irq + 3 + slot) % 4;
61 } 56 }
62 irq++; /* 1-4 */ 57 irq++; /* 1-4 */
63 58
@@ -66,15 +61,13 @@ int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
66 irq = JMR3927_IRQ_IOC_PCIA; 61 irq = JMR3927_IRQ_IOC_PCIA;
67 break; 62 break;
68 case 2: 63 case 2:
69 // wrong for backplane irq = JMR3927_IRQ_IOC_PCIB; 64 irq = JMR3927_IRQ_IOC_PCIB;
70 irq = JMR3927_IRQ_IOC_PCID;
71 break; 65 break;
72 case 3: 66 case 3:
73 irq = JMR3927_IRQ_IOC_PCIC; 67 irq = JMR3927_IRQ_IOC_PCIC;
74 break; 68 break;
75 case 4: 69 case 4:
76 // wrong for backplane irq = JMR3927_IRQ_IOC_PCID; 70 irq = JMR3927_IRQ_IOC_PCID;
77 irq = JMR3927_IRQ_IOC_PCIB;
78 break; 71 break;
79 } 72 }
80 73
diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c
index 26013badfe1f..abab4852d158 100644
--- a/arch/mips/pci/fixup-rbtx4927.c
+++ b/arch/mips/pci/fixup-rbtx4927.c
@@ -33,102 +33,42 @@
33 * 675 Mass Ave, Cambridge, MA 02139, USA. 33 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 */ 34 */
35#include <linux/types.h> 35#include <linux/types.h>
36#include <linux/pci.h> 36#include <asm/txx9/pci.h>
37#include <linux/kernel.h> 37#include <asm/txx9/rbtx4927.h>
38#include <linux/init.h>
39 38
40#include <asm/txx9/tx4927.h> 39int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
41
42#undef DEBUG
43#ifdef DEBUG
44#define DBG(x...) printk(x)
45#else
46#define DBG(x...)
47#endif
48
49/* look up table for backplane pci irq for slots 17-20 by pin # */
50static unsigned char backplane_pci_irq[4][4] = {
51 /* PJ6 SLOT: 17, PIN: 1 */ {TX4927_IRQ_IOC_PCIA,
52 /* PJ6 SLOT: 17, PIN: 2 */
53 TX4927_IRQ_IOC_PCIB,
54 /* PJ6 SLOT: 17, PIN: 3 */
55 TX4927_IRQ_IOC_PCIC,
56 /* PJ6 SLOT: 17, PIN: 4 */
57 TX4927_IRQ_IOC_PCID},
58 /* SB SLOT: 18, PIN: 1 */ {TX4927_IRQ_IOC_PCIB,
59 /* SB SLOT: 18, PIN: 2 */
60 TX4927_IRQ_IOC_PCIC,
61 /* SB SLOT: 18, PIN: 3 */
62 TX4927_IRQ_IOC_PCID,
63 /* SB SLOT: 18, PIN: 4 */
64 TX4927_IRQ_IOC_PCIA},
65 /* PJ5 SLOT: 19, PIN: 1 */ {TX4927_IRQ_IOC_PCIC,
66 /* PJ5 SLOT: 19, PIN: 2 */
67 TX4927_IRQ_IOC_PCID,
68 /* PJ5 SLOT: 19, PIN: 3 */
69 TX4927_IRQ_IOC_PCIA,
70 /* PJ5 SLOT: 19, PIN: 4 */
71 TX4927_IRQ_IOC_PCIB},
72 /* PJ4 SLOT: 20, PIN: 1 */ {TX4927_IRQ_IOC_PCID,
73 /* PJ4 SLOT: 20, PIN: 2 */
74 TX4927_IRQ_IOC_PCIA,
75 /* PJ4 SLOT: 20, PIN: 3 */
76 TX4927_IRQ_IOC_PCIB,
77 /* PJ4 SLOT: 20, PIN: 4 */
78 TX4927_IRQ_IOC_PCIC}
79};
80
81static int pci_get_irq(const struct pci_dev *dev, int pin)
82{ 40{
83 unsigned char irq = pin; 41 unsigned char irq = pin;
84 42
85 DBG("pci_get_irq: pin is %d\n", pin);
86 /* IRQ rotation */ 43 /* IRQ rotation */
87 irq--; /* 0-3 */ 44 irq--; /* 0-3 */
88 if (dev->bus->parent == NULL && 45 if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
89 PCI_SLOT(dev->devfn) == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) { 46 /* PCI CardSlot (IDSEL=A23) */
90 printk("Onboard PCI_SLOT(dev->devfn) is %d\n", 47 /* PCIA => PCIA */
91 PCI_SLOT(dev->devfn)); 48 irq = (irq + 0 + slot) % 4;
92 /* IDSEL=A23 is tx4927 onboard pci slot */
93 irq = (irq + PCI_SLOT(dev->devfn)) % 4;
94 irq++; /* 1-4 */
95 DBG("irq is now %d\n", irq);
96
97 switch (irq) {
98 case 1:
99 irq = TX4927_IRQ_IOC_PCIA;
100 break;
101 case 2:
102 irq = TX4927_IRQ_IOC_PCIB;
103 break;
104 case 3:
105 irq = TX4927_IRQ_IOC_PCIC;
106 break;
107 case 4:
108 irq = TX4927_IRQ_IOC_PCID;
109 break;
110 }
111 } else { 49 } else {
112 /* PCI Backplane */ 50 /* PCI Backplane */
113 DBG("PCI Backplane PCI_SLOT(dev->devfn) is %d\n", 51 if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
114 PCI_SLOT(dev->devfn)); 52 irq = (irq + 33 - slot) % 4;
115 irq = backplane_pci_irq[PCI_SLOT(dev->devfn) - 17][irq]; 53 else
54 irq = (irq + 3 + slot) % 4;
116 } 55 }
117 DBG("assigned irq %d\n", irq); 56 irq++; /* 1-4 */
118 return irq;
119}
120
121int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
122{
123 unsigned char irq;
124
125 printk("PCI Setup for pin %d \n", pin);
126
127 if (dev->device == 0x9130) /* IDE */
128 irq = 14;
129 else
130 irq = pci_get_irq(dev, pin);
131 57
58 switch (irq) {
59 case 1:
60 irq = RBTX4927_IRQ_IOC_PCIA;
61 break;
62 case 2:
63 irq = RBTX4927_IRQ_IOC_PCIB;
64 break;
65 case 3:
66 irq = RBTX4927_IRQ_IOC_PCIC;
67 break;
68 case 4:
69 irq = RBTX4927_IRQ_IOC_PCID;
70 break;
71 }
132 return irq; 72 return irq;
133} 73}
134 74
diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c
index 64d4510c0265..39c995830384 100644
--- a/arch/mips/pci/fixup-rbtx4938.c
+++ b/arch/mips/pci/fixup-rbtx4938.c
@@ -10,45 +10,28 @@
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com) 10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */ 11 */
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/pci.h> 13#include <asm/txx9/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/txx9/rbtx4938.h> 14#include <asm/txx9/rbtx4938.h>
18 15
19extern struct pci_controller tx4938_pci_controller[]; 16int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
20
21static int pci_get_irq(const struct pci_dev *dev, int pin)
22{ 17{
23 int irq = pin; 18 int irq = tx4938_pcic1_map_irq(dev, slot);
24 u8 slot = PCI_SLOT(dev->devfn);
25 struct pci_controller *controller = (struct pci_controller *)dev->sysdata;
26
27 if (controller == &tx4938_pci_controller[1]) {
28 /* TX4938 PCIC1 */
29 switch (slot) {
30 case TX4938_PCIC_IDSEL_AD_TO_SLOT(31):
31 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH0_SEL)
32 return RBTX4938_IRQ_IRC + TX4938_IR_ETH0;
33 break;
34 case TX4938_PCIC_IDSEL_AD_TO_SLOT(30):
35 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_ETH1_SEL)
36 return RBTX4938_IRQ_IRC + TX4938_IR_ETH1;
37 break;
38 }
39 return 0;
40 }
41 19
20 if (irq >= 0)
21 return irq;
22 irq = pin;
42 /* IRQ rotation */ 23 /* IRQ rotation */
43 irq--; /* 0-3 */ 24 irq--; /* 0-3 */
44 if (dev->bus->parent == NULL && 25 if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
45 (slot == TX4938_PCIC_IDSEL_AD_TO_SLOT(23))) {
46 /* PCI CardSlot (IDSEL=A23) */ 26 /* PCI CardSlot (IDSEL=A23) */
47 /* PCIA => PCIA (IDSEL=A23) */ 27 /* PCIA => PCIA (IDSEL=A23) */
48 irq = (irq + 0 + slot) % 4; 28 irq = (irq + 0 + slot) % 4;
49 } else { 29 } else {
50 /* PCI Backplane */ 30 /* PCI Backplane */
51 irq = (irq + 33 - slot) % 4; 31 if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
32 irq = (irq + 33 - slot) % 4;
33 else
34 irq = (irq + 3 + slot) % 4;
52 } 35 }
53 irq++; /* 1-4 */ 36 irq++; /* 1-4 */
54 37
@@ -69,19 +52,6 @@ static int pci_get_irq(const struct pci_dev *dev, int pin)
69 return irq; 52 return irq;
70} 53}
71 54
72int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
73{
74 unsigned char irq = 0;
75
76 irq = pci_get_irq(dev, pin);
77
78 printk(KERN_INFO "PCI: 0x%02x:0x%02x(0x%02x,0x%02x) IRQ=%d\n",
79 dev->bus->number, dev->devfn, PCI_SLOT(dev->devfn),
80 PCI_FUNC(dev->devfn), irq);
81
82 return irq;
83}
84
85/* 55/*
86 * Do platform specific device initialization at pci_enable_device() time 56 * Do platform specific device initialization at pci_enable_device() time
87 */ 57 */
diff --git a/arch/mips/pci/ops-tx3927.c b/arch/mips/pci/ops-tx3927.c
index 5d398f694682..8a17a39e5bf2 100644
--- a/arch/mips/pci/ops-tx3927.c
+++ b/arch/mips/pci/ops-tx3927.c
@@ -8,7 +8,7 @@
8 * 8 *
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c 9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c
10 * 10 *
11 * Define the pci_ops for JMR3927. 11 * Define the pci_ops for TX3927.
12 * 12 *
13 * Much of the code is derived from the original DDB5074 port by 13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com> 14 * Geert Uytterhoeven <geert@sonycom.com>
@@ -39,7 +39,7 @@
39#include <linux/init.h> 39#include <linux/init.h>
40 40
41#include <asm/addrspace.h> 41#include <asm/addrspace.h>
42#include <asm/txx9/jmr3927.h> 42#include <asm/txx9/tx3927.h>
43 43
44static inline int mkaddr(unsigned char bus, unsigned char dev_fn, 44static inline int mkaddr(unsigned char bus, unsigned char dev_fn,
45 unsigned char where) 45 unsigned char where)
@@ -68,7 +68,7 @@ static inline int check_abort(void)
68 return PCIBIOS_SUCCESSFUL; 68 return PCIBIOS_SUCCESSFUL;
69} 69}
70 70
71static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn, 71static int tx3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
72 int where, int size, u32 * val) 72 int where, int size, u32 * val)
73{ 73{
74 int ret; 74 int ret;
@@ -94,7 +94,7 @@ static int jmr3927_pci_read_config(struct pci_bus *bus, unsigned int devfn,
94 return check_abort(); 94 return check_abort();
95} 95}
96 96
97static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn, 97static int tx3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
98 int where, int size, u32 val) 98 int where, int size, u32 val)
99{ 99{
100 int ret; 100 int ret;
@@ -125,7 +125,80 @@ static int jmr3927_pci_write_config(struct pci_bus *bus, unsigned int devfn,
125 return check_abort(); 125 return check_abort();
126} 126}
127 127
128struct pci_ops jmr3927_pci_ops = { 128static struct pci_ops tx3927_pci_ops = {
129 jmr3927_pci_read_config, 129 .read = tx3927_pci_read_config,
130 jmr3927_pci_write_config, 130 .write = tx3927_pci_write_config,
131}; 131};
132
133void __init tx3927_pcic_setup(struct pci_controller *channel,
134 unsigned long sdram_size, int extarb)
135{
136 unsigned long flags;
137 unsigned long io_base =
138 channel->io_resource->start + mips_io_port_base - IO_BASE;
139 unsigned long io_size =
140 channel->io_resource->end - channel->io_resource->start;
141 unsigned long io_pciaddr =
142 channel->io_resource->start - channel->io_offset;
143 unsigned long mem_base =
144 channel->mem_resource->start;
145 unsigned long mem_size =
146 channel->mem_resource->end - channel->mem_resource->start;
147 unsigned long mem_pciaddr =
148 channel->mem_resource->start - channel->mem_offset;
149
150 printk(KERN_INFO "TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s",
151 tx3927_pcicptr->did, tx3927_pcicptr->vid,
152 tx3927_pcicptr->rid,
153 extarb ? "External" : "Internal");
154 channel->pci_ops = &tx3927_pci_ops;
155
156 local_irq_save(flags);
157 /* Disable External PCI Config. Access */
158 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
159#ifdef __BIG_ENDIAN
160 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
161 TX3927_PCIC_LBC_TIBSE |
162 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
163#endif
164 /* LB->PCI mappings */
165 tx3927_pcicptr->iomas = ~(io_size - 1);
166 tx3927_pcicptr->ilbioma = io_base;
167 tx3927_pcicptr->ipbioma = io_pciaddr;
168 tx3927_pcicptr->mmas = ~(mem_size - 1);
169 tx3927_pcicptr->ilbmma = mem_base;
170 tx3927_pcicptr->ipbmma = mem_pciaddr;
171 /* PCI->LB mappings */
172 tx3927_pcicptr->iobas = 0xffffffff;
173 tx3927_pcicptr->ioba = 0;
174 tx3927_pcicptr->tlbioma = 0;
175 tx3927_pcicptr->mbas = ~(sdram_size - 1);
176 tx3927_pcicptr->mba = 0;
177 tx3927_pcicptr->tlbmma = 0;
178 /* Enable Direct mapping Address Space Decoder */
179 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
180
181 /* Clear All Local Bus Status */
182 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
183 /* Enable All Local Bus Interrupts */
184 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
185 /* Clear All PCI Status Error */
186 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
187 /* Enable All PCI Status Error Interrupts */
188 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
189
190 /* PCIC Int => IRC IRQ10 */
191 tx3927_pcicptr->il = TX3927_IR_PCI;
192 /* Target Control (per errata) */
193 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
194
195 /* Enable Bus Arbiter */
196 if (!extarb)
197 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
198
199 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
200 PCI_COMMAND_MEMORY |
201 PCI_COMMAND_IO |
202 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
203 local_irq_restore(flags);
204}
diff --git a/arch/mips/pci/ops-tx4927.c b/arch/mips/pci/ops-tx4927.c
index 54730eee451b..c6b49bccd274 100644
--- a/arch/mips/pci/ops-tx4927.c
+++ b/arch/mips/pci/ops-tx4927.c
@@ -1,206 +1,408 @@
1/* 1/*
2 * Copyright 2001 MontaVista Software Inc. 2 * Define the pci_ops for the PCIC on Toshiba TX4927, TX4938, etc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 * 3 *
6 * Copyright (C) 2000-2001 Toshiba Corporation 4 * Based on linux/arch/mips/pci/ops-tx4938.c,
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) 5 * linux/arch/mips/pci/fixup-rbtx4938.c,
8 * 6 * linux/arch/mips/txx9/rbtx4938/setup.c,
9 * Based on arch/mips/ddb5xxx/ddb5477/pci_ops.c 7 * and RBTX49xx patch from CELF patch archive.
10 *
11 * Define the pci_ops for the Toshiba rbtx4927
12 *
13 * Much of the code is derived from the original DDB5074 port by
14 * Geert Uytterhoeven <geert@sonycom.com>
15 *
16 * Copyright 2004 MontaVista Software Inc.
17 * Author: Manish Lachwani (mlachwani@mvista.com)
18 *
19 * This program is free software; you can redistribute it and/or modify it
20 * under the terms of the GNU General Public License as published by the
21 * Free Software Foundation; either version 2 of the License, or (at your
22 * option) any later version.
23 * 8 *
24 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 9 * 2003-2005 (c) MontaVista Software, Inc.
25 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 10 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
26 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 11 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
27 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
28 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
30 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
33 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * 12 *
35 * You should have received a copy of the GNU General Public License along 13 * This program is free software; you can redistribute it and/or modify it
36 * with this program; if not, write to the Free Software Foundation, Inc., 14 * under the terms of the GNU General Public License as published by the
37 * 675 Mass Ave, Cambridge, MA 02139, USA. 15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
38 */ 17 */
39#include <linux/types.h>
40#include <linux/pci.h>
41#include <linux/kernel.h> 18#include <linux/kernel.h>
42#include <linux/init.h> 19#include <asm/txx9/tx4927pcic.h>
43#include <asm/txx9/tx4927.h>
44
45/* initialize in setup */
46struct resource pci_io_resource = {
47 .name = "TX4927 PCI IO SPACE",
48 .start = 0x1000,
49 .end = (0x1000 + (TX4927_PCIIO_SIZE)) - 1,
50 .flags = IORESOURCE_IO
51};
52 20
53/* initialize in setup */ 21static struct {
54struct resource pci_mem_resource = { 22 struct pci_controller *channel;
55 .name = "TX4927 PCI MEM SPACE", 23 struct tx4927_pcic_reg __iomem *pcicptr;
56 .start = TX4927_PCIMEM, 24} pcicptrs[2]; /* TX4938 has 2 pcic */
57 .end = TX4927_PCIMEM + TX4927_PCIMEM_SIZE - 1, 25
58 .flags = IORESOURCE_MEM 26static void __init set_tx4927_pcicptr(struct pci_controller *channel,
59}; 27 struct tx4927_pcic_reg __iomem *pcicptr)
28{
29 int i;
30
31 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
32 if (pcicptrs[i].channel == channel) {
33 pcicptrs[i].pcicptr = pcicptr;
34 return;
35 }
36 }
37 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
38 if (!pcicptrs[i].channel) {
39 pcicptrs[i].channel = channel;
40 pcicptrs[i].pcicptr = pcicptr;
41 return;
42 }
43 }
44 BUG();
45}
60 46
61static int mkaddr(int bus, int dev_fn, int where, int *flagsp) 47struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
48 struct pci_controller *channel)
62{ 49{
63 if (bus > 0) { 50 int i;
64 /* Type 1 configuration */
65 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
66 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
67 } else {
68 if (dev_fn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
69 return -1;
70 51
71 /* Type 0 configuration */ 52 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
72 tx4927_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | 53 if (pcicptrs[i].channel == channel)
73 ((dev_fn & 0xff) << 0x08) | (where & 0xfc); 54 return pcicptrs[i].pcicptr;
74 } 55 }
56 return NULL;
57}
58
59static int mkaddr(struct pci_bus *bus, unsigned int devfn, int where,
60 struct tx4927_pcic_reg __iomem *pcicptr)
61{
62 if (bus->parent == NULL &&
63 devfn >= PCI_DEVFN(TX4927_PCIC_MAX_DEVNU, 0))
64 return -1;
65 __raw_writel(((bus->number & 0xff) << 0x10)
66 | ((devfn & 0xff) << 0x08) | (where & 0xfc)
67 | (bus->parent ? 1 : 0),
68 &pcicptr->g2pcfgadrs);
75 /* clear M_ABORT and Disable M_ABORT Int. */ 69 /* clear M_ABORT and Disable M_ABORT Int. */
76 tx4927_pcicptr->pcistatus = 70 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
77 (tx4927_pcicptr->pcistatus & 0x0000ffff) | 71 | (PCI_STATUS_REC_MASTER_ABORT << 16),
78 (PCI_STATUS_REC_MASTER_ABORT << 16); 72 &pcicptr->pcistatus);
79 tx4927_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
80 return 0; 73 return 0;
81} 74}
82 75
83static int check_abort(int flags) 76static int check_abort(struct tx4927_pcic_reg __iomem *pcicptr)
84{ 77{
85 int code = PCIBIOS_SUCCESSFUL; 78 int code = PCIBIOS_SUCCESSFUL;
86 if (tx4927_pcicptr-> 79
87 pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { 80 /* wait write cycle completion before checking error status */
88 tx4927_pcicptr->pcistatus = 81 while (__raw_readl(&pcicptr->pcicstatus) & TX4927_PCIC_PCICSTATUS_IWB)
89 (tx4927_pcicptr-> 82 ;
90 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT 83 if (__raw_readl(&pcicptr->pcistatus)
91 << 16); 84 & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
92 tx4927_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; 85 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
86 | (PCI_STATUS_REC_MASTER_ABORT << 16),
87 &pcicptr->pcistatus);
93 code = PCIBIOS_DEVICE_NOT_FOUND; 88 code = PCIBIOS_DEVICE_NOT_FOUND;
94 } 89 }
95 return code; 90 return code;
96} 91}
97 92
98static int tx4927_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, 93static u8 icd_readb(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
99 int size, u32 * val) 94{
95#ifdef __BIG_ENDIAN
96 offset ^= 3;
97#endif
98 return __raw_readb((void __iomem *)&pcicptr->g2pcfgdata + offset);
99}
100static u16 icd_readw(int offset, struct tx4927_pcic_reg __iomem *pcicptr)
101{
102#ifdef __BIG_ENDIAN
103 offset ^= 2;
104#endif
105 return __raw_readw((void __iomem *)&pcicptr->g2pcfgdata + offset);
106}
107static u32 icd_readl(struct tx4927_pcic_reg __iomem *pcicptr)
108{
109 return __raw_readl(&pcicptr->g2pcfgdata);
110}
111static void icd_writeb(u8 val, int offset,
112 struct tx4927_pcic_reg __iomem *pcicptr)
113{
114#ifdef __BIG_ENDIAN
115 offset ^= 3;
116#endif
117 __raw_writeb(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
118}
119static void icd_writew(u16 val, int offset,
120 struct tx4927_pcic_reg __iomem *pcicptr)
121{
122#ifdef __BIG_ENDIAN
123 offset ^= 2;
124#endif
125 __raw_writew(val, (void __iomem *)&pcicptr->g2pcfgdata + offset);
126}
127static void icd_writel(u32 val, struct tx4927_pcic_reg __iomem *pcicptr)
100{ 128{
101 int flags, retval, dev, busno, func; 129 __raw_writel(val, &pcicptr->g2pcfgdata);
130}
102 131
103 busno = bus->number; 132static struct tx4927_pcic_reg __iomem *pci_bus_to_pcicptr(struct pci_bus *bus)
104 dev = PCI_SLOT(devfn); 133{
105 func = PCI_FUNC(devfn); 134 struct pci_controller *channel = bus->sysdata;
135 return get_tx4927_pcicptr(channel);
136}
106 137
107 /* check if the bus is top-level */ 138static int tx4927_pci_config_read(struct pci_bus *bus, unsigned int devfn,
108 if (bus->parent != NULL) { 139 int where, int size, u32 *val)
109 busno = bus->number; 140{
110 } else { 141 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
111 busno = 0;
112 }
113 142
114 if (mkaddr(busno, devfn, where, &flags)) 143 if (mkaddr(bus, devfn, where, pcicptr)) {
144 *val = 0xffffffff;
115 return -1; 145 return -1;
116 146 }
117 switch (size) { 147 switch (size) {
118 case 1: 148 case 1:
119 *val = *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> 149 *val = icd_readb(where & 3, pcicptr);
120 g2pcfgdata |
121#ifdef __LITTLE_ENDIAN
122 (where & 3));
123#else
124 ((where & 0x3) ^ 0x3));
125#endif
126 break; 150 break;
127 case 2: 151 case 2:
128 *val = *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> 152 *val = icd_readw(where & 3, pcicptr);
129 g2pcfgdata |
130#ifdef __LITTLE_ENDIAN
131 (where & 3));
132#else
133 ((where & 0x3) ^ 0x2));
134#endif
135 break;
136 case 4:
137 *val = tx4927_pcicptr->g2pcfgdata;
138 break; 153 break;
154 default:
155 *val = icd_readl(pcicptr);
139 } 156 }
157 return check_abort(pcicptr);
158}
140 159
141 retval = check_abort(flags); 160static int tx4927_pci_config_write(struct pci_bus *bus, unsigned int devfn,
142 if (retval == PCIBIOS_DEVICE_NOT_FOUND) 161 int where, int size, u32 val)
143 *val = 0xffffffff; 162{
163 struct tx4927_pcic_reg __iomem *pcicptr = pci_bus_to_pcicptr(bus);
144 164
145 return retval; 165 if (mkaddr(bus, devfn, where, pcicptr))
166 return -1;
167 switch (size) {
168 case 1:
169 icd_writeb(val, where & 3, pcicptr);
170 break;
171 case 2:
172 icd_writew(val, where & 3, pcicptr);
173 break;
174 default:
175 icd_writel(val, pcicptr);
176 }
177 return check_abort(pcicptr);
146} 178}
147 179
148static int tx4927_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, 180static struct pci_ops tx4927_pci_ops = {
149 int size, u32 val) 181 .read = tx4927_pci_config_read,
182 .write = tx4927_pci_config_write,
183};
184
185static struct {
186 u8 trdyto;
187 u8 retryto;
188 u16 gbwc;
189} tx4927_pci_opts __devinitdata = {
190 .trdyto = 0,
191 .retryto = 0,
192 .gbwc = 0xfe0, /* 4064 GBUSCLK for CCFG.GTOT=0b11 */
193};
194
195void __init tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
196 struct pci_controller *channel, int extarb)
150{ 197{
151 int flags, dev, busno, func; 198 int i;
152 busno = bus->number; 199 unsigned long flags;
153 dev = PCI_SLOT(devfn);
154 func = PCI_FUNC(devfn);
155 200
156 /* check if the bus is top-level */ 201 set_tx4927_pcicptr(channel, pcicptr);
157 if (bus->parent != NULL) {
158 busno = bus->number;
159 } else {
160 busno = 0;
161 }
162 202
163 if (mkaddr(busno, devfn, where, &flags)) 203 if (!channel->pci_ops)
164 return -1; 204 printk(KERN_INFO
205 "PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
206 __raw_readl(&pcicptr->pciid) >> 16,
207 __raw_readl(&pcicptr->pciid) & 0xffff,
208 __raw_readl(&pcicptr->pciccrev) & 0xff,
209 extarb ? "External" : "Internal");
210 channel->pci_ops = &tx4927_pci_ops;
165 211
166 switch (size) { 212 local_irq_save(flags);
167 case 1: 213
168 *(volatile u8 *) ((unsigned long) & tx4927_pcicptr-> 214 /* Disable All Initiator Space */
169 g2pcfgdata | 215 __raw_writel(__raw_readl(&pcicptr->pciccfg)
170#ifdef __LITTLE_ENDIAN 216 & ~(TX4927_PCIC_PCICCFG_G2PMEN(0)
171 (where & 3)) = val; 217 | TX4927_PCIC_PCICCFG_G2PMEN(1)
218 | TX4927_PCIC_PCICCFG_G2PMEN(2)
219 | TX4927_PCIC_PCICCFG_G2PIOEN),
220 &pcicptr->pciccfg);
221
222 /* GB->PCI mappings */
223 __raw_writel((channel->io_resource->end - channel->io_resource->start)
224 >> 4,
225 &pcicptr->g2piomask);
226 ____raw_writeq((channel->io_resource->start +
227 channel->io_map_base - IO_BASE) |
228#ifdef __BIG_ENDIAN
229 TX4927_PCIC_G2PIOGBASE_ECHG
172#else 230#else
173 ((where & 0x3) ^ 0x3)) = val; 231 TX4927_PCIC_G2PIOGBASE_BSDIS
174#endif 232#endif
175 break; 233 , &pcicptr->g2piogbase);
176 234 ____raw_writeq(channel->io_resource->start - channel->io_offset,
177 case 2: 235 &pcicptr->g2piopbase);
178 *(volatile u16 *) ((unsigned long) & tx4927_pcicptr-> 236 for (i = 0; i < 3; i++) {
179 g2pcfgdata | 237 __raw_writel(0, &pcicptr->g2pmmask[i]);
180#ifdef __LITTLE_ENDIAN 238 ____raw_writeq(0, &pcicptr->g2pmgbase[i]);
181 (where & 3)) = val; 239 ____raw_writeq(0, &pcicptr->g2pmpbase[i]);
240 }
241 if (channel->mem_resource->end) {
242 __raw_writel((channel->mem_resource->end
243 - channel->mem_resource->start) >> 4,
244 &pcicptr->g2pmmask[0]);
245 ____raw_writeq(channel->mem_resource->start |
246#ifdef __BIG_ENDIAN
247 TX4927_PCIC_G2PMnGBASE_ECHG
182#else 248#else
183 ((where & 0x3) ^ 0x2)) = val; 249 TX4927_PCIC_G2PMnGBASE_BSDIS
184#endif 250#endif
185 break; 251 , &pcicptr->g2pmgbase[0]);
186 case 4: 252 ____raw_writeq(channel->mem_resource->start -
187 tx4927_pcicptr->g2pcfgdata = val; 253 channel->mem_offset,
188 break; 254 &pcicptr->g2pmpbase[0]);
255 }
256 /* PCI->GB mappings (I/O 256B) */
257 __raw_writel(0, &pcicptr->p2giopbase); /* 256B */
258 ____raw_writeq(0, &pcicptr->p2giogbase);
259 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
260 __raw_writel(0, &pcicptr->p2gm0plbase);
261 __raw_writel(0, &pcicptr->p2gm0pubase);
262 ____raw_writeq(TX4927_PCIC_P2GMnGBASE_TMEMEN |
263#ifdef __BIG_ENDIAN
264 TX4927_PCIC_P2GMnGBASE_TECHG
265#else
266 TX4927_PCIC_P2GMnGBASE_TBSDIS
267#endif
268 , &pcicptr->p2gmgbase[0]);
269 /* PCI->GB mappings (MEM 16MB) */
270 __raw_writel(0xffffffff, &pcicptr->p2gm1plbase);
271 __raw_writel(0xffffffff, &pcicptr->p2gm1pubase);
272 ____raw_writeq(0, &pcicptr->p2gmgbase[1]);
273 /* PCI->GB mappings (MEM 1MB) */
274 __raw_writel(0xffffffff, &pcicptr->p2gm2pbase); /* 1MB */
275 ____raw_writeq(0, &pcicptr->p2gmgbase[2]);
276
277 /* Clear all (including IRBER) except for GBWC */
278 __raw_writel((tx4927_pci_opts.gbwc << 16)
279 & TX4927_PCIC_PCICCFG_GBWC_MASK,
280 &pcicptr->pciccfg);
281 /* Enable Initiator Memory Space */
282 if (channel->mem_resource->end)
283 __raw_writel(__raw_readl(&pcicptr->pciccfg)
284 | TX4927_PCIC_PCICCFG_G2PMEN(0),
285 &pcicptr->pciccfg);
286 /* Enable Initiator I/O Space */
287 if (channel->io_resource->end)
288 __raw_writel(__raw_readl(&pcicptr->pciccfg)
289 | TX4927_PCIC_PCICCFG_G2PIOEN,
290 &pcicptr->pciccfg);
291 /* Enable Initiator Config */
292 __raw_writel(__raw_readl(&pcicptr->pciccfg)
293 | TX4927_PCIC_PCICCFG_ICAEN | TX4927_PCIC_PCICCFG_TCAR,
294 &pcicptr->pciccfg);
295
296 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
297 __raw_writel(0, &pcicptr->pcicfg1);
298
299 __raw_writel((__raw_readl(&pcicptr->g2ptocnt) & ~0xffff)
300 | (tx4927_pci_opts.trdyto & 0xff)
301 | ((tx4927_pci_opts.retryto & 0xff) << 8),
302 &pcicptr->g2ptocnt);
303
304 /* Clear All Local Bus Status */
305 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicstatus);
306 /* Enable All Local Bus Interrupts */
307 __raw_writel(TX4927_PCIC_PCICSTATUS_ALL, &pcicptr->pcicmask);
308 /* Clear All Initiator Status */
309 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pstatus);
310 /* Enable All Initiator Interrupts */
311 __raw_writel(TX4927_PCIC_G2PSTATUS_ALL, &pcicptr->g2pmask);
312 /* Clear All PCI Status Error */
313 __raw_writel((__raw_readl(&pcicptr->pcistatus) & 0x0000ffff)
314 | (TX4927_PCIC_PCISTATUS_ALL << 16),
315 &pcicptr->pcistatus);
316 /* Enable All PCI Status Error Interrupts */
317 __raw_writel(TX4927_PCIC_PCISTATUS_ALL, &pcicptr->pcimask);
318
319 if (!extarb) {
320 /* Reset Bus Arbiter */
321 __raw_writel(TX4927_PCIC_PBACFG_RPBA, &pcicptr->pbacfg);
322 __raw_writel(0, &pcicptr->pbabm);
323 /* Enable Bus Arbiter */
324 __raw_writel(TX4927_PCIC_PBACFG_PBAEN, &pcicptr->pbacfg);
189 } 325 }
190 326
191 return check_abort(flags); 327 __raw_writel(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
328 | PCI_COMMAND_PARITY | PCI_COMMAND_SERR,
329 &pcicptr->pcistatus);
330 local_irq_restore(flags);
331
332 printk(KERN_DEBUG
333 "PCI: COMMAND=%04x,PCIMASK=%04x,"
334 "TRDYTO=%02x,RETRYTO=%02x,GBWC=%03x\n",
335 __raw_readl(&pcicptr->pcistatus) & 0xffff,
336 __raw_readl(&pcicptr->pcimask) & 0xffff,
337 __raw_readl(&pcicptr->g2ptocnt) & 0xff,
338 (__raw_readl(&pcicptr->g2ptocnt) & 0xff00) >> 8,
339 (__raw_readl(&pcicptr->pciccfg) >> 16) & 0xfff);
192} 340}
193 341
194struct pci_ops tx4927_pci_ops = { 342static void tx4927_report_pcic_status1(struct tx4927_pcic_reg __iomem *pcicptr)
195 tx4927_pcibios_read_config, 343{
196 tx4927_pcibios_write_config 344 __u16 pcistatus = (__u16)(__raw_readl(&pcicptr->pcistatus) >> 16);
197}; 345 __u32 g2pstatus = __raw_readl(&pcicptr->g2pstatus);
346 __u32 pcicstatus = __raw_readl(&pcicptr->pcicstatus);
347 static struct {
348 __u32 flag;
349 const char *str;
350 } pcistat_tbl[] = {
351 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
352 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
353 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
354 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
355 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
356 { PCI_STATUS_PARITY, "MasterParityError" },
357 }, g2pstat_tbl[] = {
358 { TX4927_PCIC_G2PSTATUS_TTOE, "TIOE" },
359 { TX4927_PCIC_G2PSTATUS_RTOE, "RTOE" },
360 }, pcicstat_tbl[] = {
361 { TX4927_PCIC_PCICSTATUS_PME, "PME" },
362 { TX4927_PCIC_PCICSTATUS_TLB, "TLB" },
363 { TX4927_PCIC_PCICSTATUS_NIB, "NIB" },
364 { TX4927_PCIC_PCICSTATUS_ZIB, "ZIB" },
365 { TX4927_PCIC_PCICSTATUS_PERR, "PERR" },
366 { TX4927_PCIC_PCICSTATUS_SERR, "SERR" },
367 { TX4927_PCIC_PCICSTATUS_GBE, "GBE" },
368 { TX4927_PCIC_PCICSTATUS_IWB, "IWB" },
369 };
370 int i, cont;
198 371
199/* 372 printk(KERN_ERR "");
200 * h/w only supports devices 0x00 to 0x14 373 if (pcistatus & TX4927_PCIC_PCISTATUS_ALL) {
201 */ 374 printk(KERN_CONT "pcistat:%04x(", pcistatus);
202struct pci_controller tx4927_controller = { 375 for (i = 0, cont = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
203 .pci_ops = &tx4927_pci_ops, 376 if (pcistatus & pcistat_tbl[i].flag)
204 .io_resource = &pci_io_resource, 377 printk(KERN_CONT "%s%s",
205 .mem_resource = &pci_mem_resource, 378 cont++ ? " " : "", pcistat_tbl[i].str);
206}; 379 printk(KERN_CONT ") ");
380 }
381 if (g2pstatus & TX4927_PCIC_G2PSTATUS_ALL) {
382 printk(KERN_CONT "g2pstatus:%08x(", g2pstatus);
383 for (i = 0, cont = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
384 if (g2pstatus & g2pstat_tbl[i].flag)
385 printk(KERN_CONT "%s%s",
386 cont++ ? " " : "", g2pstat_tbl[i].str);
387 printk(KERN_CONT ") ");
388 }
389 if (pcicstatus & TX4927_PCIC_PCICSTATUS_ALL) {
390 printk(KERN_CONT "pcicstatus:%08x(", pcicstatus);
391 for (i = 0, cont = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
392 if (pcicstatus & pcicstat_tbl[i].flag)
393 printk(KERN_CONT "%s%s",
394 cont++ ? " " : "", pcicstat_tbl[i].str);
395 printk(KERN_CONT ")");
396 }
397 printk(KERN_CONT "\n");
398}
399
400void tx4927_report_pcic_status(void)
401{
402 int i;
403
404 for (i = 0; i < ARRAY_SIZE(pcicptrs); i++) {
405 if (pcicptrs[i].pcicptr)
406 tx4927_report_pcic_status1(pcicptrs[i].pcicptr);
407 }
408}
diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c
deleted file mode 100644
index 34494b82cb22..000000000000
--- a/arch/mips/pci/ops-tx4938.c
+++ /dev/null
@@ -1,214 +0,0 @@
1/*
2 * Define the pci_ops for the Toshiba rbtx4938
3 * Copyright (C) 2000-2001 Toshiba Corporation
4 *
5 * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
6 * terms of the GNU General Public License version 2. This program is
7 * licensed "as is" without any warranty of any kind, whether express
8 * or implied.
9 *
10 * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
11 */
12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/kernel.h>
15#include <linux/init.h>
16
17#include <asm/addrspace.h>
18#include <asm/txx9/rbtx4938.h>
19
20/* initialize in setup */
21struct resource pci_io_resource = {
22 .name = "pci IO space",
23 .start = 0,
24 .end = 0,
25 .flags = IORESOURCE_IO
26};
27
28/* initialize in setup */
29struct resource pci_mem_resource = {
30 .name = "pci memory space",
31 .start = 0,
32 .end = 0,
33 .flags = IORESOURCE_MEM
34};
35
36struct resource tx4938_pcic1_pci_io_resource = {
37 .name = "PCI1 IO",
38 .start = 0,
39 .end = 0,
40 .flags = IORESOURCE_IO
41};
42struct resource tx4938_pcic1_pci_mem_resource = {
43 .name = "PCI1 mem",
44 .start = 0,
45 .end = 0,
46 .flags = IORESOURCE_MEM
47};
48
49static int mkaddr(int bus, int dev_fn, int where,
50 struct tx4938_pcic_reg *pcicptr)
51{
52 if (bus > 0) {
53 /* Type 1 configuration */
54 pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
55 ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1;
56 } else {
57 if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0))
58 return -1;
59
60 /* Type 0 configuration */
61 pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) |
62 ((dev_fn & 0xff) << 0x08) | (where & 0xfc);
63 }
64 /* clear M_ABORT and Disable M_ABORT Int. */
65 pcicptr->pcistatus =
66 (pcicptr->pcistatus & 0x0000ffff) |
67 (PCI_STATUS_REC_MASTER_ABORT << 16);
68 pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT;
69
70 return 0;
71}
72
73static int check_abort(struct tx4938_pcic_reg *pcicptr)
74{
75 int code = PCIBIOS_SUCCESSFUL;
76 /* wait write cycle completion before checking error status */
77 while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB)
78 ;
79 if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) {
80 pcicptr->pcistatus =
81 (pcicptr->
82 pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT
83 << 16);
84 pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT;
85 code = PCIBIOS_DEVICE_NOT_FOUND;
86 }
87 return code;
88}
89
90extern struct pci_controller tx4938_pci_controller[];
91extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch);
92
93static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus)
94{
95 struct pci_controller *channel = bus->sysdata;
96 return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]);
97}
98
99static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn,
100 int where, int size, u32 * val)
101{
102 int retval, dev, busno, func;
103 struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
104 void __iomem *cfgdata =
105 (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
106
107 dev = PCI_SLOT(devfn);
108 func = PCI_FUNC(devfn);
109
110 /* check if the bus is top-level */
111 if (bus->parent != NULL)
112 busno = bus->number;
113 else {
114 busno = 0;
115 }
116
117 if (mkaddr(busno, devfn, where, pcicptr))
118 return -1;
119
120 switch (size) {
121 case 1:
122#ifdef __BIG_ENDIAN
123 cfgdata += (where & 3) ^ 3;
124#else
125 cfgdata += where & 3;
126#endif
127 *val = __raw_readb(cfgdata);
128 break;
129 case 2:
130#ifdef __BIG_ENDIAN
131 cfgdata += (where & 2) ^ 2;
132#else
133 cfgdata += where & 2;
134#endif
135 *val = __raw_readw(cfgdata);
136 break;
137 case 4:
138 *val = __raw_readl(cfgdata);
139 break;
140 }
141
142 retval = check_abort(pcicptr);
143 if (retval == PCIBIOS_DEVICE_NOT_FOUND)
144 *val = 0xffffffff;
145
146 return retval;
147}
148
149static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where,
150 int size, u32 val)
151{
152 int dev, busno, func;
153 struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus);
154 void __iomem *cfgdata =
155 (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata;
156
157 busno = bus->number;
158 dev = PCI_SLOT(devfn);
159 func = PCI_FUNC(devfn);
160
161 /* check if the bus is top-level */
162 if (bus->parent != NULL) {
163 busno = bus->number;
164 } else {
165 busno = 0;
166 }
167
168 if (mkaddr(busno, devfn, where, pcicptr))
169 return -1;
170
171 switch (size) {
172 case 1:
173#ifdef __BIG_ENDIAN
174 cfgdata += (where & 3) ^ 3;
175#else
176 cfgdata += where & 3;
177#endif
178 __raw_writeb(val, cfgdata);
179 break;
180 case 2:
181#ifdef __BIG_ENDIAN
182 cfgdata += (where & 2) ^ 2;
183#else
184 cfgdata += where & 2;
185#endif
186 __raw_writew(val, cfgdata);
187 break;
188 case 4:
189 __raw_writel(val, cfgdata);
190 break;
191 }
192
193 return check_abort(pcicptr);
194}
195
196struct pci_ops tx4938_pci_ops = {
197 tx4938_pcibios_read_config,
198 tx4938_pcibios_write_config
199};
200
201struct pci_controller tx4938_pci_controller[] = {
202 /* h/w only supports devices 0x00 to 0x14 */
203 {
204 .pci_ops = &tx4938_pci_ops,
205 .io_resource = &pci_io_resource,
206 .mem_resource = &pci_mem_resource,
207 },
208 /* h/w only supports devices 0x00 to 0x14 */
209 {
210 .pci_ops = &tx4938_pci_ops,
211 .io_resource = &tx4938_pcic1_pci_io_resource,
212 .mem_resource = &tx4938_pcic1_pci_mem_resource,
213 }
214};
diff --git a/arch/mips/pci/pci-jmr3927.c b/arch/mips/pci/pci-jmr3927.c
deleted file mode 100644
index 7fb6bd71901a..000000000000
--- a/arch/mips/pci/pci-jmr3927.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * Copyright 2001 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc.
4 * ahennessy@mvista.com
5 *
6 * Copyright (C) 2000-2001 Toshiba Corporation
7 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29#include <linux/types.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/init.h>
33
34#include <asm/txx9/jmr3927.h>
35#include <asm/debug.h>
36
37struct resource pci_io_resource = {
38 .name = "IO MEM",
39 .start = 0x1000, /* reserve regacy I/O space */
40 .end = 0x1000 + JMR3927_PCIIO_SIZE - 1,
41 .flags = IORESOURCE_IO
42};
43
44struct resource pci_mem_resource = {
45 .name = "PCI MEM",
46 .start = JMR3927_PCIMEM,
47 .end = JMR3927_PCIMEM + JMR3927_PCIMEM_SIZE - 1,
48 .flags = IORESOURCE_MEM
49};
50
51extern struct pci_ops jmr3927_pci_ops;
52
53struct pci_controller jmr3927_controller = {
54 .pci_ops = &jmr3927_pci_ops,
55 .io_resource = &pci_io_resource,
56 .mem_resource = &pci_mem_resource,
57 .mem_offset = JMR3927_PCIMEM
58};
diff --git a/arch/mips/pci/pci-tx4927.c b/arch/mips/pci/pci-tx4927.c
new file mode 100644
index 000000000000..27e86a09dd41
--- /dev/null
+++ b/arch/mips/pci/pci-tx4927.c
@@ -0,0 +1,83 @@
1/*
2 * linux/arch/mips/pci/pci-tx4927.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * Copyright 2001, 2003-2005 MontaVista Software Inc.
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/kernel.h>
18#include <asm/txx9/generic.h>
19#include <asm/txx9/tx4927.h>
20
21int __init tx4927_report_pciclk(void)
22{
23 int pciclk = 0;
24
25 printk(KERN_INFO "PCIC --%s PCICLK:",
26 (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66) ?
27 " PCI66" : "");
28 if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
29 u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
30 switch ((unsigned long)ccfg &
31 TX4927_CCFG_PCIDIVMODE_MASK) {
32 case TX4927_CCFG_PCIDIVMODE_2_5:
33 pciclk = txx9_cpu_clock * 2 / 5; break;
34 case TX4927_CCFG_PCIDIVMODE_3:
35 pciclk = txx9_cpu_clock / 3; break;
36 case TX4927_CCFG_PCIDIVMODE_5:
37 pciclk = txx9_cpu_clock / 5; break;
38 case TX4927_CCFG_PCIDIVMODE_6:
39 pciclk = txx9_cpu_clock / 6; break;
40 }
41 printk("Internal(%u.%uMHz)",
42 (pciclk + 50000) / 1000000,
43 ((pciclk + 50000) / 100000) % 10);
44 } else {
45 printk("External");
46 pciclk = -1;
47 }
48 printk("\n");
49 return pciclk;
50}
51
52int __init tx4927_pciclk66_setup(void)
53{
54 int pciclk;
55
56 /* Assert M66EN */
57 tx4927_ccfg_set(TX4927_CCFG_PCI66);
58 /* Double PCICLK (if possible) */
59 if (__raw_readq(&tx4927_ccfgptr->pcfg) & TX4927_PCFG_PCICLKEN_ALL) {
60 unsigned int pcidivmode = 0;
61 u64 ccfg = __raw_readq(&tx4927_ccfgptr->ccfg);
62 pcidivmode = (unsigned long)ccfg &
63 TX4927_CCFG_PCIDIVMODE_MASK;
64 switch (pcidivmode) {
65 case TX4927_CCFG_PCIDIVMODE_5:
66 case TX4927_CCFG_PCIDIVMODE_2_5:
67 pcidivmode = TX4927_CCFG_PCIDIVMODE_2_5;
68 pciclk = txx9_cpu_clock * 2 / 5;
69 break;
70 case TX4927_CCFG_PCIDIVMODE_6:
71 case TX4927_CCFG_PCIDIVMODE_3:
72 default:
73 pcidivmode = TX4927_CCFG_PCIDIVMODE_3;
74 pciclk = txx9_cpu_clock / 3;
75 }
76 tx4927_ccfg_change(TX4927_CCFG_PCIDIVMODE_MASK,
77 pcidivmode);
78 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
79 (unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg));
80 } else
81 pciclk = -1;
82 return pciclk;
83}
diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c
new file mode 100644
index 000000000000..e5375511c2b7
--- /dev/null
+++ b/arch/mips/pci/pci-tx4938.c
@@ -0,0 +1,134 @@
1/*
2 * linux/arch/mips/pci/pci-tx4938.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * Copyright 2001, 2003-2005 MontaVista Software Inc.
8 * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
9 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15#include <linux/init.h>
16#include <linux/pci.h>
17#include <linux/kernel.h>
18#include <asm/txx9/generic.h>
19#include <asm/txx9/tx4938.h>
20
21int __init tx4938_report_pciclk(void)
22{
23 int pciclk = 0;
24
25 printk(KERN_INFO "PCIC --%s PCICLK:",
26 (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66) ?
27 " PCI66" : "");
28 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
29 u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
30 switch ((unsigned long)ccfg &
31 TX4938_CCFG_PCIDIVMODE_MASK) {
32 case TX4938_CCFG_PCIDIVMODE_4:
33 pciclk = txx9_cpu_clock / 4; break;
34 case TX4938_CCFG_PCIDIVMODE_4_5:
35 pciclk = txx9_cpu_clock * 2 / 9; break;
36 case TX4938_CCFG_PCIDIVMODE_5:
37 pciclk = txx9_cpu_clock / 5; break;
38 case TX4938_CCFG_PCIDIVMODE_5_5:
39 pciclk = txx9_cpu_clock * 2 / 11; break;
40 case TX4938_CCFG_PCIDIVMODE_8:
41 pciclk = txx9_cpu_clock / 8; break;
42 case TX4938_CCFG_PCIDIVMODE_9:
43 pciclk = txx9_cpu_clock / 9; break;
44 case TX4938_CCFG_PCIDIVMODE_10:
45 pciclk = txx9_cpu_clock / 10; break;
46 case TX4938_CCFG_PCIDIVMODE_11:
47 pciclk = txx9_cpu_clock / 11; break;
48 }
49 printk("Internal(%u.%uMHz)",
50 (pciclk + 50000) / 1000000,
51 ((pciclk + 50000) / 100000) % 10);
52 } else {
53 printk("External");
54 pciclk = -1;
55 }
56 printk("\n");
57 return pciclk;
58}
59
60void __init tx4938_report_pci1clk(void)
61{
62 __u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
63 unsigned int pciclk =
64 txx9_gbus_clock / ((ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2);
65
66 printk(KERN_INFO "PCIC1 -- %sPCICLK:%u.%uMHz\n",
67 (ccfg & TX4938_CCFG_PCI1_66) ? "PCI66 " : "",
68 (pciclk + 50000) / 1000000,
69 ((pciclk + 50000) / 100000) % 10);
70}
71
72int __init tx4938_pciclk66_setup(void)
73{
74 int pciclk;
75
76 /* Assert M66EN */
77 tx4938_ccfg_set(TX4938_CCFG_PCI66);
78 /* Double PCICLK (if possible) */
79 if (__raw_readq(&tx4938_ccfgptr->pcfg) & TX4938_PCFG_PCICLKEN_ALL) {
80 unsigned int pcidivmode = 0;
81 u64 ccfg = __raw_readq(&tx4938_ccfgptr->ccfg);
82 pcidivmode = (unsigned long)ccfg &
83 TX4938_CCFG_PCIDIVMODE_MASK;
84 switch (pcidivmode) {
85 case TX4938_CCFG_PCIDIVMODE_8:
86 case TX4938_CCFG_PCIDIVMODE_4:
87 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
88 pciclk = txx9_cpu_clock / 4;
89 break;
90 case TX4938_CCFG_PCIDIVMODE_9:
91 case TX4938_CCFG_PCIDIVMODE_4_5:
92 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
93 pciclk = txx9_cpu_clock * 2 / 9;
94 break;
95 case TX4938_CCFG_PCIDIVMODE_10:
96 case TX4938_CCFG_PCIDIVMODE_5:
97 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
98 pciclk = txx9_cpu_clock / 5;
99 break;
100 case TX4938_CCFG_PCIDIVMODE_11:
101 case TX4938_CCFG_PCIDIVMODE_5_5:
102 default:
103 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
104 pciclk = txx9_cpu_clock * 2 / 11;
105 break;
106 }
107 tx4938_ccfg_change(TX4938_CCFG_PCIDIVMODE_MASK,
108 pcidivmode);
109 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
110 (unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg));
111 } else
112 pciclk = -1;
113 return pciclk;
114}
115
116int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
117{
118 if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) {
119 switch (slot) {
120 case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
121 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
122 TX4938_PCFG_ETH0_SEL)
123 return TXX9_IRQ_BASE + TX4938_IR_ETH0;
124 break;
125 case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
126 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
127 TX4938_PCFG_ETH1_SEL)
128 return TXX9_IRQ_BASE + TX4938_IR_ETH1;
129 break;
130 }
131 return 0;
132 }
133 return -1;
134}
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 98d103402b10..b8cdb192543a 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -1,6 +1,12 @@
1config TOSHIBA_FPCIB0 1config TOSHIBA_FPCIB0
2 bool "FPCIB0 Backplane Support" 2 bool "FPCIB0 Backplane Support"
3 depends on TOSHIBA_RBTX4927 3 depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX)
4 select I8259
5
6config PICMG_PCI_BACKPLANE_DEFAULT
7 bool "Support for PICMG PCI Backplane"
8 depends on PCI && (SYS_HAS_CPU_TX49XX || SYS_HAS_CPU_TX39XX)
9 default y if !TOSHIBA_FPCIB0
4 10
5if TOSHIBA_RBTX4938 11if TOSHIBA_RBTX4938
6 12
@@ -26,3 +32,6 @@ config TX4938_NAND_BOOT
26 Select this option if you need to use NAND boot. 32 Select this option if you need to use NAND boot.
27 33
28endif 34endif
35
36config PCI_TX4927
37 bool
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 8cb4a7e81473..b80b6e072284 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -2,6 +2,8 @@
2# Makefile for common code for TXx9 based systems 2# Makefile for common code for TXx9 based systems
3# 3#
4 4
5obj-y += setup.o
6obj-$(CONFIG_PCI) += pci.o
5obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o 7obj-$(CONFIG_TOSHIBA_RBTX4927) += mem_tx4927.o irq_tx4927.o
6obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o 8obj-$(CONFIG_TOSHIBA_RBTX4938) += mem_tx4938.o irq_tx4938.o
7obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o 9obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c
new file mode 100644
index 000000000000..8173faab99bb
--- /dev/null
+++ b/arch/mips/txx9/generic/pci.c
@@ -0,0 +1,377 @@
1/*
2 * linux/arch/mips/txx9/pci.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4927/setup.c,
5 * linux/arch/mips/txx9/rbtx4938/setup.c,
6 * and RBTX49xx patch from CELF patch archive.
7 *
8 * Copyright 2001-2005 MontaVista Software Inc.
9 * Copyright (C) 1996, 97, 2001, 04 Ralf Baechle (ralf@linux-mips.org)
10 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file "COPYING" in the main directory of this archive
14 * for more details.
15 */
16#include <linux/delay.h>
17#include <linux/jiffies.h>
18#include <linux/io.h>
19#include <asm/txx9/pci.h>
20#ifdef CONFIG_TOSHIBA_FPCIB0
21#include <linux/interrupt.h>
22#include <asm/i8259.h>
23#include <asm/txx9/smsc_fdc37m81x.h>
24#endif
25
26static int __init
27early_read_config_word(struct pci_controller *hose,
28 int top_bus, int bus, int devfn, int offset, u16 *value)
29{
30 struct pci_dev fake_dev;
31 struct pci_bus fake_bus;
32
33 fake_dev.bus = &fake_bus;
34 fake_dev.sysdata = hose;
35 fake_dev.devfn = devfn;
36 fake_bus.number = bus;
37 fake_bus.sysdata = hose;
38 fake_bus.ops = hose->pci_ops;
39
40 if (bus != top_bus)
41 /* Fake a parent bus structure. */
42 fake_bus.parent = &fake_bus;
43 else
44 fake_bus.parent = NULL;
45
46 return pci_read_config_word(&fake_dev, offset, value);
47}
48
49int __init txx9_pci66_check(struct pci_controller *hose, int top_bus,
50 int current_bus)
51{
52 u32 pci_devfn;
53 unsigned short vid;
54 int cap66 = -1;
55 u16 stat;
56
57 /* It seems SLC90E66 needs some time after PCI reset... */
58 mdelay(80);
59
60 printk(KERN_INFO "PCI: Checking 66MHz capabilities...\n");
61
62 for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
63 if (PCI_FUNC(pci_devfn))
64 continue;
65 if (early_read_config_word(hose, top_bus, current_bus,
66 pci_devfn, PCI_VENDOR_ID, &vid) !=
67 PCIBIOS_SUCCESSFUL)
68 continue;
69 if (vid == 0xffff)
70 continue;
71
72 /* check 66MHz capability */
73 if (cap66 < 0)
74 cap66 = 1;
75 if (cap66) {
76 early_read_config_word(hose, top_bus, current_bus,
77 pci_devfn, PCI_STATUS, &stat);
78 if (!(stat & PCI_STATUS_66MHZ)) {
79 printk(KERN_DEBUG
80 "PCI: %02x:%02x not 66MHz capable.\n",
81 current_bus, pci_devfn);
82 cap66 = 0;
83 break;
84 }
85 }
86 }
87 return cap66 > 0;
88}
89
90static struct resource primary_pci_mem_res[2] = {
91 { .name = "PCI MEM" },
92 { .name = "PCI MMIO" },
93};
94static struct resource primary_pci_io_res = { .name = "PCI IO" };
95struct pci_controller txx9_primary_pcic = {
96 .mem_resource = &primary_pci_mem_res[0],
97 .io_resource = &primary_pci_io_res,
98};
99
100#ifdef CONFIG_64BIT
101int txx9_pci_mem_high __initdata = 1;
102#else
103int txx9_pci_mem_high __initdata;
104#endif
105
106/*
107 * allocate pci_controller and resources.
108 * mem_base, io_base: physical addresss. 0 for auto assignment.
109 * mem_size and io_size means max size on auto assignment.
110 * pcic must be &txx9_primary_pcic or NULL.
111 */
112struct pci_controller *__init
113txx9_alloc_pci_controller(struct pci_controller *pcic,
114 unsigned long mem_base, unsigned long mem_size,
115 unsigned long io_base, unsigned long io_size)
116{
117 struct pcic {
118 struct pci_controller c;
119 struct resource r_mem[2];
120 struct resource r_io;
121 } *new = NULL;
122 int min_size = 0x10000;
123
124 if (!pcic) {
125 new = kzalloc(sizeof(*new), GFP_KERNEL);
126 if (!new)
127 return NULL;
128 new->r_mem[0].name = "PCI mem";
129 new->r_mem[1].name = "PCI mmio";
130 new->r_io.name = "PCI io";
131 new->c.mem_resource = new->r_mem;
132 new->c.io_resource = &new->r_io;
133 pcic = &new->c;
134 } else
135 BUG_ON(pcic != &txx9_primary_pcic);
136 pcic->io_resource->flags = IORESOURCE_IO;
137
138 /*
139 * for auto assignment, first search a (big) region for PCI
140 * MEM, then search a region for PCI IO.
141 */
142 if (mem_base) {
143 pcic->mem_resource[0].start = mem_base;
144 pcic->mem_resource[0].end = mem_base + mem_size - 1;
145 if (request_resource(&iomem_resource, &pcic->mem_resource[0]))
146 goto free_and_exit;
147 } else {
148 unsigned long min = 0, max = 0x20000000; /* low 512MB */
149 if (!mem_size) {
150 /* default size for auto assignment */
151 if (txx9_pci_mem_high)
152 mem_size = 0x20000000; /* mem:512M(max) */
153 else
154 mem_size = 0x08000000; /* mem:128M(max) */
155 }
156 if (txx9_pci_mem_high) {
157 min = 0x20000000;
158 max = 0xe0000000;
159 }
160 /* search free region for PCI MEM */
161 for (; mem_size >= min_size; mem_size /= 2) {
162 if (allocate_resource(&iomem_resource,
163 &pcic->mem_resource[0],
164 mem_size, min, max,
165 mem_size, NULL, NULL) == 0)
166 break;
167 }
168 if (mem_size < min_size)
169 goto free_and_exit;
170 }
171
172 pcic->mem_resource[1].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
173 if (io_base) {
174 pcic->mem_resource[1].start = io_base;
175 pcic->mem_resource[1].end = io_base + io_size - 1;
176 if (request_resource(&iomem_resource, &pcic->mem_resource[1]))
177 goto release_and_exit;
178 } else {
179 if (!io_size)
180 /* default size for auto assignment */
181 io_size = 0x01000000; /* io:16M(max) */
182 /* search free region for PCI IO in low 512MB */
183 for (; io_size >= min_size; io_size /= 2) {
184 if (allocate_resource(&iomem_resource,
185 &pcic->mem_resource[1],
186 io_size, 0, 0x20000000,
187 io_size, NULL, NULL) == 0)
188 break;
189 }
190 if (io_size < min_size)
191 goto release_and_exit;
192 io_base = pcic->mem_resource[1].start;
193 }
194
195 pcic->mem_resource[0].flags = IORESOURCE_MEM;
196 if (pcic == &txx9_primary_pcic &&
197 mips_io_port_base == (unsigned long)-1) {
198 /* map ioport 0 to PCI I/O space address 0 */
199 set_io_port_base(IO_BASE + pcic->mem_resource[1].start);
200 pcic->io_resource->start = 0;
201 pcic->io_offset = 0; /* busaddr == ioaddr */
202 pcic->io_map_base = IO_BASE + pcic->mem_resource[1].start;
203 } else {
204 /* physaddr to ioaddr */
205 pcic->io_resource->start =
206 io_base - (mips_io_port_base - IO_BASE);
207 pcic->io_offset = io_base - (mips_io_port_base - IO_BASE);
208 pcic->io_map_base = mips_io_port_base;
209 }
210 pcic->io_resource->end = pcic->io_resource->start + io_size - 1;
211
212 pcic->mem_offset = 0; /* busaddr == physaddr */
213
214 printk(KERN_INFO "PCI: IO 0x%08llx-0x%08llx MEM 0x%08llx-0x%08llx\n",
215 (unsigned long long)pcic->mem_resource[1].start,
216 (unsigned long long)pcic->mem_resource[1].end,
217 (unsigned long long)pcic->mem_resource[0].start,
218 (unsigned long long)pcic->mem_resource[0].end);
219
220 /* register_pci_controller() will request MEM resource */
221 release_resource(&pcic->mem_resource[0]);
222 return pcic;
223 release_and_exit:
224 release_resource(&pcic->mem_resource[0]);
225 free_and_exit:
226 kfree(new);
227 printk(KERN_ERR "PCI: Failed to allocate resources.\n");
228 return NULL;
229}
230
231static int __init
232txx9_arch_pci_init(void)
233{
234 PCIBIOS_MIN_IO = 0x8000; /* reseve legacy I/O space */
235 return 0;
236}
237arch_initcall(txx9_arch_pci_init);
238
239/* IRQ/IDSEL mapping */
240int txx9_pci_option =
241#ifdef CONFIG_PICMG_PCI_BACKPLANE_DEFAULT
242 TXX9_PCI_OPT_PICMG |
243#endif
244 TXX9_PCI_OPT_CLK_AUTO;
245
246enum txx9_pci_err_action txx9_pci_err_action = TXX9_PCI_ERR_REPORT;
247
248#ifdef CONFIG_TOSHIBA_FPCIB0
249static irqreturn_t i8259_interrupt(int irq, void *dev_id)
250{
251 int isairq;
252
253 isairq = i8259_irq();
254 if (unlikely(isairq <= I8259A_IRQ_BASE))
255 return IRQ_NONE;
256 generic_handle_irq(isairq);
257 return IRQ_HANDLED;
258}
259
260static int __init
261txx9_i8259_irq_setup(int irq)
262{
263 int err;
264
265 init_i8259_irqs();
266 err = request_irq(irq, &i8259_interrupt, IRQF_DISABLED|IRQF_SHARED,
267 "cascade(i8259)", (void *)(long)irq);
268 if (!err)
269 printk(KERN_INFO "PCI-ISA bridge PIC (irq %d)\n", irq);
270 return err;
271}
272
273static void __init quirk_slc90e66_bridge(struct pci_dev *dev)
274{
275 int irq; /* PCI/ISA Bridge interrupt */
276 u8 reg_64;
277 u32 reg_b0;
278 u8 reg_e1;
279 irq = pcibios_map_irq(dev, PCI_SLOT(dev->devfn), 1); /* INTA */
280 if (!irq)
281 return;
282 txx9_i8259_irq_setup(irq);
283 pci_read_config_byte(dev, 0x64, &reg_64);
284 pci_read_config_dword(dev, 0xb0, &reg_b0);
285 pci_read_config_byte(dev, 0xe1, &reg_e1);
286 /* serial irq control */
287 reg_64 = 0xd0;
288 /* serial irq pin */
289 reg_b0 |= 0x00010000;
290 /* ide irq on isa14 */
291 reg_e1 &= 0xf0;
292 reg_e1 |= 0x0d;
293 pci_write_config_byte(dev, 0x64, reg_64);
294 pci_write_config_dword(dev, 0xb0, reg_b0);
295 pci_write_config_byte(dev, 0xe1, reg_e1);
296
297 smsc_fdc37m81x_init(0x3f0);
298 smsc_fdc37m81x_config_beg();
299 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
300 SMSC_FDC37M81X_KBD);
301 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
302 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
303 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
304 1);
305 smsc_fdc37m81x_config_end();
306}
307
308static void quirk_slc90e66_ide(struct pci_dev *dev)
309{
310 unsigned char dat;
311 int regs[2] = {0x41, 0x43};
312 int i;
313
314 /* SMSC SLC90E66 IDE uses irq 14, 15 (default) */
315 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 14);
316 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &dat);
317 printk(KERN_INFO "PCI: %s: IRQ %02x", pci_name(dev), dat);
318 /* enable SMSC SLC90E66 IDE */
319 for (i = 0; i < ARRAY_SIZE(regs); i++) {
320 pci_read_config_byte(dev, regs[i], &dat);
321 pci_write_config_byte(dev, regs[i], dat | 0x80);
322 pci_read_config_byte(dev, regs[i], &dat);
323 printk(KERN_CONT " IDETIM%d %02x", i, dat);
324 }
325 pci_read_config_byte(dev, 0x5c, &dat);
326 /*
327 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
328 *
329 * This line of code is intended to provide the user with a work
330 * around solution to the anomalies cited in SMSC's anomaly sheet
331 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
332 *
333 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
334 */
335 dat |= 0x01;
336 pci_write_config_byte(dev, regs[i], dat);
337 pci_read_config_byte(dev, 0x5c, &dat);
338 printk(KERN_CONT " REG5C %02x", dat);
339 printk(KERN_CONT "\n");
340}
341#endif /* CONFIG_TOSHIBA_FPCIB0 */
342
343static void final_fixup(struct pci_dev *dev)
344{
345 unsigned char bist;
346
347 /* Do build-in self test */
348 if (pci_read_config_byte(dev, PCI_BIST, &bist) == PCIBIOS_SUCCESSFUL &&
349 (bist & PCI_BIST_CAPABLE)) {
350 unsigned long timeout;
351 pci_set_power_state(dev, PCI_D0);
352 printk(KERN_INFO "PCI: %s BIST...", pci_name(dev));
353 pci_write_config_byte(dev, PCI_BIST, PCI_BIST_START);
354 timeout = jiffies + HZ * 2; /* timeout after 2 sec */
355 do {
356 pci_read_config_byte(dev, PCI_BIST, &bist);
357 if (time_after(jiffies, timeout))
358 break;
359 } while (bist & PCI_BIST_START);
360 if (bist & (PCI_BIST_CODE_MASK | PCI_BIST_START))
361 printk(KERN_CONT "failed. (0x%x)\n", bist);
362 else
363 printk(KERN_CONT "OK.\n");
364 }
365}
366
367#ifdef CONFIG_TOSHIBA_FPCIB0
368#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
369DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_0,
370 quirk_slc90e66_bridge);
371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
372 quirk_slc90e66_ide);
373DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_1,
374 quirk_slc90e66_ide);
375#endif
376DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
377DECLARE_PCI_FIXUP_RESUME(PCI_ANY_ID, PCI_ANY_ID, final_fixup);
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
new file mode 100644
index 000000000000..46a631177757
--- /dev/null
+++ b/arch/mips/txx9/generic/setup.c
@@ -0,0 +1,51 @@
1/*
2 * linux/arch/mips/txx9/generic/setup.c
3 *
4 * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
5 * and RBTX49xx patch from CELF patch archive.
6 *
7 * 2003-2005 (c) MontaVista Software, Inc.
8 * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file "COPYING" in the main directory of this archive
12 * for more details.
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <asm/txx9/generic.h>
18
19/* EBUSC settings of TX4927, etc. */
20struct resource txx9_ce_res[8];
21static char txx9_ce_res_name[8][4]; /* "CEn" */
22
23/* pcode, internal register */
24char txx9_pcode_str[8];
25static struct resource txx9_reg_res = {
26 .name = txx9_pcode_str,
27 .flags = IORESOURCE_MEM,
28};
29void __init
30txx9_reg_res_init(unsigned int pcode, unsigned long base, unsigned long size)
31{
32 int i;
33
34 for (i = 0; i < ARRAY_SIZE(txx9_ce_res); i++) {
35 sprintf(txx9_ce_res_name[i], "CE%d", i);
36 txx9_ce_res[i].flags = IORESOURCE_MEM;
37 txx9_ce_res[i].name = txx9_ce_res_name[i];
38 }
39
40 sprintf(txx9_pcode_str, "TX%x", pcode);
41 if (base) {
42 txx9_reg_res.start = base & 0xfffffffffULL;
43 txx9_reg_res.end = (base & 0xfffffffffULL) + (size - 1);
44 request_resource(&iomem_resource, &txx9_reg_res);
45 }
46}
47
48/* clocks */
49unsigned int txx9_master_clock;
50unsigned int txx9_cpu_clock;
51unsigned int txx9_gbus_clock;
diff --git a/arch/mips/txx9/jmr3927/irq.c b/arch/mips/txx9/jmr3927/irq.c
index 85e1daf15c7b..b97d22e15da6 100644
--- a/arch/mips/txx9/jmr3927/irq.c
+++ b/arch/mips/txx9/jmr3927/irq.c
@@ -109,6 +109,7 @@ static struct irqaction ioc_action = {
109 .name = "IOC", 109 .name = "IOC",
110}; 110};
111 111
112#ifdef CONFIG_PCI
112static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id) 113static irqreturn_t jmr3927_pcierr_interrupt(int irq, void *dev_id)
113{ 114{
114 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq); 115 printk(KERN_WARNING "PCI error interrupt (irq 0x%x).\n", irq);
@@ -122,6 +123,7 @@ static struct irqaction pcierr_action = {
122 .mask = CPU_MASK_NONE, 123 .mask = CPU_MASK_NONE,
123 .name = "PCI error", 124 .name = "PCI error",
124}; 125};
126#endif
125 127
126static void __init jmr3927_irq_init(void); 128static void __init jmr3927_irq_init(void);
127 129
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 41e0f3b3af2c..baa8c8db9a94 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -30,7 +30,6 @@
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32#include <linux/types.h> 32#include <linux/types.h>
33#include <linux/pci.h>
34#include <linux/ioport.h> 33#include <linux/ioport.h>
35#include <linux/delay.h> 34#include <linux/delay.h>
36#include <linux/pm.h> 35#include <linux/pm.h>
@@ -44,6 +43,7 @@
44#include <asm/txx9tmr.h> 43#include <asm/txx9tmr.h>
45#include <asm/txx9pio.h> 44#include <asm/txx9pio.h>
46#include <asm/reboot.h> 45#include <asm/reboot.h>
46#include <asm/txx9/pci.h>
47#include <asm/txx9/jmr3927.h> 47#include <asm/txx9/jmr3927.h>
48#include <asm/mipsregs.h> 48#include <asm/mipsregs.h>
49 49
@@ -96,8 +96,6 @@ void __init plat_time_init(void)
96 96
97extern char * __init prom_getcmdline(void); 97extern char * __init prom_getcmdline(void);
98static void jmr3927_board_init(void); 98static void jmr3927_board_init(void);
99extern struct resource pci_io_resource;
100extern struct resource pci_mem_resource;
101 99
102void __init plat_mem_setup(void) 100void __init plat_mem_setup(void)
103{ 101{
@@ -112,8 +110,8 @@ void __init plat_mem_setup(void)
112 /* 110 /*
113 * IO/MEM resources. 111 * IO/MEM resources.
114 */ 112 */
115 ioport_resource.start = pci_io_resource.start; 113 ioport_resource.start = 0;
116 ioport_resource.end = pci_io_resource.end; 114 ioport_resource.end = 0xffffffff;
117 iomem_resource.start = 0; 115 iomem_resource.start = 0;
118 iomem_resource.end = 0xffffffff; 116 iomem_resource.end = 0xffffffff;
119 117
@@ -191,9 +189,33 @@ void __init plat_mem_setup(void)
191 189
192static void tx3927_setup(void); 190static void tx3927_setup(void);
193 191
192static void __init jmr3927_pci_setup(void)
193{
194#ifdef CONFIG_PCI
195 int extarb = !(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB);
196 struct pci_controller *c;
197
198 c = txx9_alloc_pci_controller(&txx9_primary_pcic,
199 JMR3927_PCIMEM, JMR3927_PCIMEM_SIZE,
200 JMR3927_PCIIO, JMR3927_PCIIO_SIZE);
201 register_pci_controller(c);
202 if (!extarb) {
203 /* Reset PCI Bus */
204 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
205 udelay(100);
206 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
207 JMR3927_IOC_RESET_ADDR);
208 udelay(100);
209 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
210 }
211 tx3927_pcic_setup(c, JMR3927_SDRAM_SIZE, extarb);
212#endif /* CONFIG_PCI */
213}
214
194static void __init jmr3927_board_init(void) 215static void __init jmr3927_board_init(void)
195{ 216{
196 tx3927_setup(); 217 tx3927_setup();
218 jmr3927_pci_setup();
197 219
198 /* SIO0 DTR on */ 220 /* SIO0 DTR on */
199 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR); 221 jmr3927_ioc_reg_out(0, JMR3927_IOC_DTR_ADDR);
@@ -210,14 +232,6 @@ static void __init jmr3927_board_init(void)
210static void __init tx3927_setup(void) 232static void __init tx3927_setup(void)
211{ 233{
212 int i; 234 int i;
213#ifdef CONFIG_PCI
214 unsigned long mips_pci_io_base = JMR3927_PCIIO;
215 unsigned long mips_pci_io_size = JMR3927_PCIIO_SIZE;
216 unsigned long mips_pci_mem_base = JMR3927_PCIMEM;
217 unsigned long mips_pci_mem_size = JMR3927_PCIMEM_SIZE;
218 /* for legacy I/O, PCI I/O PCI Bus address must be 0 */
219 unsigned long mips_pci_io_pciaddr = 0;
220#endif
221 235
222 /* SDRAMC are configured by PROM */ 236 /* SDRAMC are configured by PROM */
223 237
@@ -272,74 +286,6 @@ static void __init tx3927_setup(void)
272 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE; 286 tx3927_dmaptr->mcr = TX3927_DMA_MCR_MSTEN | TX3927_DMA_MCR_LE;
273#endif 287#endif
274 288
275#ifdef CONFIG_PCI
276 /* PCIC */
277 printk("TX3927 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:",
278 tx3927_pcicptr->did, tx3927_pcicptr->vid,
279 tx3927_pcicptr->rid);
280 if (!(tx3927_ccfgptr->ccfg & TX3927_CCFG_PCIXARB)) {
281 printk("External\n");
282 /* XXX */
283 } else {
284 printk("Internal\n");
285
286 /* Reset PCI Bus */
287 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
288 udelay(100);
289 jmr3927_ioc_reg_out(JMR3927_IOC_RESET_PCI,
290 JMR3927_IOC_RESET_ADDR);
291 udelay(100);
292 jmr3927_ioc_reg_out(0, JMR3927_IOC_RESET_ADDR);
293
294
295 /* Disable External PCI Config. Access */
296 tx3927_pcicptr->lbc = TX3927_PCIC_LBC_EPCAD;
297#ifdef __BIG_ENDIAN
298 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_IBSE |
299 TX3927_PCIC_LBC_TIBSE |
300 TX3927_PCIC_LBC_TMFBSE | TX3927_PCIC_LBC_MSDSE;
301#endif
302 /* LB->PCI mappings */
303 tx3927_pcicptr->iomas = ~(mips_pci_io_size - 1);
304 tx3927_pcicptr->ilbioma = mips_pci_io_base;
305 tx3927_pcicptr->ipbioma = mips_pci_io_pciaddr;
306 tx3927_pcicptr->mmas = ~(mips_pci_mem_size - 1);
307 tx3927_pcicptr->ilbmma = mips_pci_mem_base;
308 tx3927_pcicptr->ipbmma = mips_pci_mem_base;
309 /* PCI->LB mappings */
310 tx3927_pcicptr->iobas = 0xffffffff;
311 tx3927_pcicptr->ioba = 0;
312 tx3927_pcicptr->tlbioma = 0;
313 tx3927_pcicptr->mbas = ~(mips_pci_mem_size - 1);
314 tx3927_pcicptr->mba = 0;
315 tx3927_pcicptr->tlbmma = 0;
316 /* Enable Direct mapping Address Space Decoder */
317 tx3927_pcicptr->lbc |= TX3927_PCIC_LBC_ILMDE | TX3927_PCIC_LBC_ILIDE;
318
319 /* Clear All Local Bus Status */
320 tx3927_pcicptr->lbstat = TX3927_PCIC_LBIM_ALL;
321 /* Enable All Local Bus Interrupts */
322 tx3927_pcicptr->lbim = TX3927_PCIC_LBIM_ALL;
323 /* Clear All PCI Status Error */
324 tx3927_pcicptr->pcistat = TX3927_PCIC_PCISTATIM_ALL;
325 /* Enable All PCI Status Error Interrupts */
326 tx3927_pcicptr->pcistatim = TX3927_PCIC_PCISTATIM_ALL;
327
328 /* PCIC Int => IRC IRQ10 */
329 tx3927_pcicptr->il = TX3927_IR_PCI;
330 /* Target Control (per errata) */
331 tx3927_pcicptr->tc = TX3927_PCIC_TC_OF8E | TX3927_PCIC_TC_IF8E;
332
333 /* Enable Bus Arbiter */
334 tx3927_pcicptr->pbapmc = TX3927_PCIC_PBAPMC_PBAEN;
335
336 tx3927_pcicptr->pcicmd = PCI_COMMAND_MASTER |
337 PCI_COMMAND_MEMORY |
338 PCI_COMMAND_IO |
339 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
340 }
341#endif /* CONFIG_PCI */
342
343 /* PIO */ 289 /* PIO */
344 /* PIO[15:12] connected to LEDs */ 290 /* PIO[15:12] connected to LEDs */
345 __raw_writel(0x0000f000, &tx3927_pioptr->dir); 291 __raw_writel(0x0000f000, &tx3927_pioptr->dir);
diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 936e50e91d95..bef1447aeed2 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -111,9 +111,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
111#include <linux/types.h> 111#include <linux/types.h>
112#include <linux/interrupt.h> 112#include <linux/interrupt.h>
113#include <asm/io.h> 113#include <asm/io.h>
114#ifdef CONFIG_TOSHIBA_FPCIB0
115#include <asm/i8259.h>
116#endif
117#include <asm/txx9/rbtx4927.h> 114#include <asm/txx9/rbtx4927.h>
118 115
119#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0 116#define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG 0
@@ -125,8 +122,6 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
125#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC 122#define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
126#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2) 123#define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
127 124
128extern int tx4927_using_backplane;
129
130static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 125static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
131static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 126static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
132 127
@@ -146,17 +141,8 @@ int toshiba_rbtx4927_irq_nested(int sw_irq)
146 u8 level3; 141 u8 level3;
147 142
148 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f; 143 level3 = readb(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
149 if (level3) { 144 if (level3)
150 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1; 145 sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + fls(level3) - 1;
151#ifdef CONFIG_TOSHIBA_FPCIB0
152 if (sw_irq == TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC &&
153 tx4927_using_backplane) {
154 int irq = i8259_irq();
155 if (irq >= 0)
156 sw_irq = irq;
157 }
158#endif
159 }
160 return (sw_irq); 146 return (sw_irq);
161} 147}
162 148
@@ -205,10 +191,6 @@ void __init arch_init_irq(void)
205 191
206 tx4927_irq_init(); 192 tx4927_irq_init();
207 toshiba_rbtx4927_irq_ioc_init(); 193 toshiba_rbtx4927_irq_ioc_init();
208#ifdef CONFIG_TOSHIBA_FPCIB0
209 if (tx4927_using_backplane)
210 init_i8259_irqs();
211#endif
212 /* Onboard 10M Ether: High Active */ 194 /* Onboard 10M Ether: High Active */
213 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH); 195 set_irq_type(RBTX4927_RTL_8019_IRQ, IRQF_TRIGGER_HIGH);
214} 196}
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index df1b6e99b666..86b870abc319 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -47,10 +47,10 @@
47#include <linux/types.h> 47#include <linux/types.h>
48#include <linux/ioport.h> 48#include <linux/ioport.h>
49#include <linux/interrupt.h> 49#include <linux/interrupt.h>
50#include <linux/pci.h>
51#include <linux/pm.h> 50#include <linux/pm.h>
52#include <linux/platform_device.h> 51#include <linux/platform_device.h>
53#include <linux/clk.h> 52#include <linux/clk.h>
53#include <linux/delay.h>
54 54
55#include <asm/bootinfo.h> 55#include <asm/bootinfo.h>
56#include <asm/io.h> 56#include <asm/io.h>
@@ -58,10 +58,10 @@
58#include <asm/reboot.h> 58#include <asm/reboot.h>
59#include <asm/time.h> 59#include <asm/time.h>
60#include <asm/txx9tmr.h> 60#include <asm/txx9tmr.h>
61#ifdef CONFIG_TOSHIBA_FPCIB0 61#include <asm/txx9/generic.h>
62#include <asm/txx9/smsc_fdc37m81x.h> 62#include <asm/txx9/pci.h>
63#endif
64#include <asm/txx9/rbtx4927.h> 63#include <asm/txx9/rbtx4927.h>
64#include <asm/txx9/tx4938.h> /* for TX4937 */
65#ifdef CONFIG_SERIAL_TXX9 65#ifdef CONFIG_SERIAL_TXX9
66#include <linux/serial_core.h> 66#include <linux/serial_core.h>
67#endif 67#endif
@@ -70,356 +70,116 @@
70extern void toshiba_rbtx4927_restart(char *command); 70extern void toshiba_rbtx4927_restart(char *command);
71extern void toshiba_rbtx4927_halt(void); 71extern void toshiba_rbtx4927_halt(void);
72extern void toshiba_rbtx4927_power_off(void); 72extern void toshiba_rbtx4927_power_off(void);
73
74int tx4927_using_backplane = 0;
75
76extern void toshiba_rbtx4927_irq_setup(void); 73extern void toshiba_rbtx4927_irq_setup(void);
77 74
78char *prom_getcmdline(void); 75char *prom_getcmdline(void);
79 76
80#ifdef CONFIG_PCI
81#undef TX4927_SUPPORT_COMMAND_IO
82#undef TX4927_SUPPORT_PCI_66
83int tx4927_cpu_clock = 100000000; /* 100MHz */
84unsigned long mips_pci_io_base;
85unsigned long mips_pci_io_size;
86unsigned long mips_pci_mem_base;
87unsigned long mips_pci_mem_size;
88/* for legacy I/O, PCI I/O PCI Bus address must be 0 */
89unsigned long mips_pci_io_pciaddr = 0;
90unsigned long mips_memory_upper;
91static int tx4927_ccfg_toeon = 1; 77static int tx4927_ccfg_toeon = 1;
92static int tx4927_pcic_trdyto = 0; /* default: disabled */
93unsigned long tx4927_ce_base[8];
94int tx4927_pci66 = 0; /* 0:auto */
95#endif
96 78
97char *toshiba_name = ""; 79char *toshiba_name = "";
98 80
99#ifdef CONFIG_PCI 81#ifdef CONFIG_PCI
100extern struct pci_controller tx4927_controller; 82static void __init tx4927_pci_setup(void)
101
102static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
103 int top_bus, int busnr, int devfn)
104{ 83{
105 static struct pci_dev dev; 84 int extarb = !(__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCIARB);
106 static struct pci_bus bus; 85 struct pci_controller *c = &txx9_primary_pcic;
107 86
108 dev.sysdata = (void *)hose; 87 register_pci_controller(c);
109 dev.devfn = devfn; 88
110 bus.number = busnr; 89 if (__raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_PCI66)
111 bus.ops = hose->pci_ops; 90 txx9_pci_option =
112 bus.parent = NULL; 91 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
113 dev.bus = &bus; 92 TXX9_PCI_OPT_CLK_66; /* already configured */
114 93
115 return &dev; 94 /* Reset PCI Bus */
116} 95 writeb(1, rbtx4927_pcireset_addr);
117 96 /* Reset PCIC */
118#define EARLY_PCI_OP(rw, size, type) \ 97 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
119static int early_##rw##_config_##size(struct pci_controller *hose, \ 98 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
120 int top_bus, int bus, int devfn, int offset, type value) \ 99 TXX9_PCI_OPT_CLK_66)
121{ \ 100 tx4927_pciclk66_setup();
122 return pci_##rw##_config_##size( \ 101 mdelay(10);
123 fake_pci_dev(hose, top_bus, bus, devfn), \ 102 /* clear PCIC reset */
124 offset, value); \ 103 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
104 writeb(0, rbtx4927_pcireset_addr);
105 iob();
106
107 tx4927_report_pciclk();
108 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
109 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
110 TXX9_PCI_OPT_CLK_AUTO &&
111 txx9_pci66_check(c, 0, 0)) {
112 /* Reset PCI Bus */
113 writeb(1, rbtx4927_pcireset_addr);
114 /* Reset PCIC */
115 txx9_set64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
116 tx4927_pciclk66_setup();
117 mdelay(10);
118 /* clear PCIC reset */
119 txx9_clear64(&tx4927_ccfgptr->clkctr, TX4927_CLKCTR_PCIRST);
120 writeb(0, rbtx4927_pcireset_addr);
121 iob();
122 /* Reinitialize PCIC */
123 tx4927_report_pciclk();
124 tx4927_pcic_setup(tx4927_pcicptr, c, extarb);
125 }
125} 126}
126 127
127EARLY_PCI_OP(read, byte, u8 *) 128static void __init tx4937_pci_setup(void)
128EARLY_PCI_OP(read, dword, u32 *)
129EARLY_PCI_OP(write, byte, u8)
130EARLY_PCI_OP(write, dword, u32)
131
132static int __init tx4927_pcibios_init(void)
133{ 129{
134 unsigned int id; 130 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
135 u32 pci_devfn; 131 struct pci_controller *c = &txx9_primary_pcic;
136 int devfn_start = 0; 132
137 int devfn_stop = 0xff; 133 register_pci_controller(c);
138 int busno = 0; /* One bus on the Toshiba */ 134
139 struct pci_controller *hose = &tx4927_controller; 135 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
140 136 txx9_pci_option =
141 for (pci_devfn = devfn_start; pci_devfn < devfn_stop; pci_devfn++) { 137 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
142 early_read_config_dword(hose, busno, busno, pci_devfn, 138 TXX9_PCI_OPT_CLK_66; /* already configured */
143 PCI_VENDOR_ID, &id); 139
144 140 /* Reset PCI Bus */
145 if (id == 0xffffffff) { 141 writeb(1, rbtx4927_pcireset_addr);
146 continue; 142 /* Reset PCIC */
147 } 143 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
148 144 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
149 if (id == 0x94601055) { 145 TXX9_PCI_OPT_CLK_66)
150 u8 v08_64; 146 tx4938_pciclk66_setup();
151 u32 v32_b0; 147 mdelay(10);
152 u8 v08_e1; 148 /* clear PCIC reset */
153 149 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
154 early_read_config_byte(hose, busno, busno, 150 writeb(0, rbtx4927_pcireset_addr);
155 pci_devfn, 0x64, &v08_64); 151 iob();
156 early_read_config_dword(hose, busno, busno, 152
157 pci_devfn, 0xb0, &v32_b0); 153 tx4938_report_pciclk();
158 early_read_config_byte(hose, busno, busno, 154 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
159 pci_devfn, 0xe1, &v08_e1); 155 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
160 156 TXX9_PCI_OPT_CLK_AUTO &&
161 /* serial irq control */ 157 txx9_pci66_check(c, 0, 0)) {
162 v08_64 = 0xd0; 158 /* Reset PCI Bus */
163 159 writeb(1, rbtx4927_pcireset_addr);
164 /* serial irq pin */ 160 /* Reset PCIC */
165 v32_b0 |= 0x00010000; 161 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
166 162 tx4938_pciclk66_setup();
167 /* ide irq on isa14 */ 163 mdelay(10);
168 v08_e1 &= 0xf0; 164 /* clear PCIC reset */
169 v08_e1 |= 0x0d; 165 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
170 166 writeb(0, rbtx4927_pcireset_addr);
171 early_write_config_byte(hose, busno, busno, 167 iob();
172 pci_devfn, 0x64, v08_64); 168 /* Reinitialize PCIC */
173 early_write_config_dword(hose, busno, busno, 169 tx4938_report_pciclk();
174 pci_devfn, 0xb0, v32_b0); 170 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
175 early_write_config_byte(hose, busno, busno,
176 pci_devfn, 0xe1, v08_e1);
177 }
178
179 if (id == 0x91301055) {
180 u8 v08_04;
181 u8 v08_09;
182 u8 v08_41;
183 u8 v08_43;
184 u8 v08_5c;
185
186 early_read_config_byte(hose, busno, busno,
187 pci_devfn, 0x04, &v08_04);
188 early_read_config_byte(hose, busno, busno,
189 pci_devfn, 0x09, &v08_09);
190 early_read_config_byte(hose, busno, busno,
191 pci_devfn, 0x41, &v08_41);
192 early_read_config_byte(hose, busno, busno,
193 pci_devfn, 0x43, &v08_43);
194 early_read_config_byte(hose, busno, busno,
195 pci_devfn, 0x5c, &v08_5c);
196
197 /* enable ide master/io */
198 v08_04 |= (PCI_COMMAND_MASTER | PCI_COMMAND_IO);
199
200 /* enable ide native mode */
201 v08_09 |= 0x05;
202
203 /* enable primary ide */
204 v08_41 |= 0x80;
205
206 /* enable secondary ide */
207 v08_43 |= 0x80;
208
209 /*
210 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
211 *
212 * This line of code is intended to provide the user with a work
213 * around solution to the anomalies cited in SMSC's anomaly sheet
214 * entitled, "SLC90E66 Functional Rev.J_0.1 Anomalies"".
215 *
216 * !!! DO NOT REMOVE THIS COMMENT IT IS REQUIRED BY SMSC !!!
217 */
218 v08_5c |= 0x01;
219
220 early_write_config_byte(hose, busno, busno,
221 pci_devfn, 0x5c, v08_5c);
222 early_write_config_byte(hose, busno, busno,
223 pci_devfn, 0x04, v08_04);
224 early_write_config_byte(hose, busno, busno,
225 pci_devfn, 0x09, v08_09);
226 early_write_config_byte(hose, busno, busno,
227 pci_devfn, 0x41, v08_41);
228 early_write_config_byte(hose, busno, busno,
229 pci_devfn, 0x43, v08_43);
230 }
231
232 } 171 }
233
234 register_pci_controller(&tx4927_controller);
235 return 0;
236} 172}
237 173
238arch_initcall(tx4927_pcibios_init); 174static int __init rbtx4927_arch_init(void)
239
240extern struct resource pci_io_resource;
241extern struct resource pci_mem_resource;
242
243void __init tx4927_pci_setup(void)
244{ 175{
245 static int called = 0; 176 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
246 extern unsigned int tx4927_get_mem_size(void); 177 tx4937_pci_setup();
247 178 else
248 mips_memory_upper = tx4927_get_mem_size() << 20; 179 tx4927_pci_setup();
249 mips_memory_upper += KSEG0; 180 return 0;
250 mips_pci_io_base = TX4927_PCIIO;
251 mips_pci_io_size = TX4927_PCIIO_SIZE;
252 mips_pci_mem_base = TX4927_PCIMEM;
253 mips_pci_mem_size = TX4927_PCIMEM_SIZE;
254
255 if (!called) {
256 printk
257 ("%s PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
258 toshiba_name,
259 (unsigned short) (tx4927_pcicptr->pciid >> 16),
260 (unsigned short) (tx4927_pcicptr->pciid & 0xffff),
261 (unsigned short) (tx4927_pcicptr->pciccrev & 0xff),
262 (!(tx4927_ccfgptr->
263 ccfg & TX4927_CCFG_PCIXARB)) ? "External" :
264 "Internal");
265 called = 1;
266 }
267 printk("%s PCIC --%s PCICLK:", toshiba_name,
268 (tx4927_ccfgptr->ccfg & TX4927_CCFG_PCI66) ? " PCI66" : "");
269 if (tx4927_ccfgptr->pcfg & TX4927_PCFG_PCICLKEN_ALL) {
270 int pciclk = 0;
271 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
272 switch ((unsigned long) tx4927_ccfgptr->
273 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) {
274 case TX4937_CCFG_PCIDIVMODE_4:
275 pciclk = tx4927_cpu_clock / 4;
276 break;
277 case TX4937_CCFG_PCIDIVMODE_4_5:
278 pciclk = tx4927_cpu_clock * 2 / 9;
279 break;
280 case TX4937_CCFG_PCIDIVMODE_5:
281 pciclk = tx4927_cpu_clock / 5;
282 break;
283 case TX4937_CCFG_PCIDIVMODE_5_5:
284 pciclk = tx4927_cpu_clock * 2 / 11;
285 break;
286 case TX4937_CCFG_PCIDIVMODE_8:
287 pciclk = tx4927_cpu_clock / 8;
288 break;
289 case TX4937_CCFG_PCIDIVMODE_9:
290 pciclk = tx4927_cpu_clock / 9;
291 break;
292 case TX4937_CCFG_PCIDIVMODE_10:
293 pciclk = tx4927_cpu_clock / 10;
294 break;
295 case TX4937_CCFG_PCIDIVMODE_11:
296 pciclk = tx4927_cpu_clock / 11;
297 break;
298 }
299
300 else
301 switch ((unsigned long) tx4927_ccfgptr->
302 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) {
303 case TX4927_CCFG_PCIDIVMODE_2_5:
304 pciclk = tx4927_cpu_clock * 2 / 5;
305 break;
306 case TX4927_CCFG_PCIDIVMODE_3:
307 pciclk = tx4927_cpu_clock / 3;
308 break;
309 case TX4927_CCFG_PCIDIVMODE_5:
310 pciclk = tx4927_cpu_clock / 5;
311 break;
312 case TX4927_CCFG_PCIDIVMODE_6:
313 pciclk = tx4927_cpu_clock / 6;
314 break;
315 }
316
317 printk("Internal(%dMHz)", pciclk / 1000000);
318 } else
319 printk("External");
320 printk("\n");
321
322 /* GB->PCI mappings */
323 tx4927_pcicptr->g2piomask = (mips_pci_io_size - 1) >> 4;
324 tx4927_pcicptr->g2piogbase = mips_pci_io_base |
325#ifdef __BIG_ENDIAN
326 TX4927_PCIC_G2PIOGBASE_ECHG
327#else
328 TX4927_PCIC_G2PIOGBASE_BSDIS
329#endif
330 ;
331
332 tx4927_pcicptr->g2piopbase = 0;
333
334 tx4927_pcicptr->g2pmmask[0] = (mips_pci_mem_size - 1) >> 4;
335 tx4927_pcicptr->g2pmgbase[0] = mips_pci_mem_base |
336#ifdef __BIG_ENDIAN
337 TX4927_PCIC_G2PMnGBASE_ECHG
338#else
339 TX4927_PCIC_G2PMnGBASE_BSDIS
340#endif
341 ;
342 tx4927_pcicptr->g2pmpbase[0] = mips_pci_mem_base;
343
344 tx4927_pcicptr->g2pmmask[1] = 0;
345 tx4927_pcicptr->g2pmgbase[1] = 0;
346 tx4927_pcicptr->g2pmpbase[1] = 0;
347 tx4927_pcicptr->g2pmmask[2] = 0;
348 tx4927_pcicptr->g2pmgbase[2] = 0;
349 tx4927_pcicptr->g2pmpbase[2] = 0;
350
351
352 /* PCI->GB mappings (I/O 256B) */
353 tx4927_pcicptr->p2giopbase = 0; /* 256B */
354
355 /* PCI->GB mappings (MEM 512MB) M0 gets all of memory */
356 tx4927_pcicptr->p2gm0plbase = 0;
357 tx4927_pcicptr->p2gm0pubase = 0;
358 tx4927_pcicptr->p2gmgbase[0] = 0 | TX4927_PCIC_P2GMnGBASE_TMEMEN |
359#ifdef __BIG_ENDIAN
360 TX4927_PCIC_P2GMnGBASE_TECHG
361#else
362 TX4927_PCIC_P2GMnGBASE_TBSDIS
363#endif
364 ;
365
366 /* PCI->GB mappings (MEM 16MB) -not used */
367 tx4927_pcicptr->p2gm1plbase = 0xffffffff;
368 tx4927_pcicptr->p2gm1pubase = 0xffffffff;
369 tx4927_pcicptr->p2gmgbase[1] = 0;
370
371 /* PCI->GB mappings (MEM 1MB) -not used */
372 tx4927_pcicptr->p2gm2pbase = 0xffffffff;
373 tx4927_pcicptr->p2gmgbase[2] = 0;
374
375
376 /* Enable Initiator Memory 0 Space, I/O Space, Config */
377 tx4927_pcicptr->pciccfg &= TX4927_PCIC_PCICCFG_LBWC_MASK;
378 tx4927_pcicptr->pciccfg |=
379 TX4927_PCIC_PCICCFG_IMSE0 | TX4927_PCIC_PCICCFG_IISE |
380 TX4927_PCIC_PCICCFG_ICAE | TX4927_PCIC_PCICCFG_ATR;
381
382
383 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
384 tx4927_pcicptr->pcicfg1 = 0;
385
386 if (tx4927_pcic_trdyto >= 0) {
387 tx4927_pcicptr->g2ptocnt &= ~0xff;
388 tx4927_pcicptr->g2ptocnt |= (tx4927_pcic_trdyto & 0xff);
389 }
390
391 /* Clear All Local Bus Status */
392 tx4927_pcicptr->pcicstatus = TX4927_PCIC_PCICSTATUS_ALL;
393 /* Enable All Local Bus Interrupts */
394 tx4927_pcicptr->pcicmask = TX4927_PCIC_PCICSTATUS_ALL;
395 /* Clear All Initiator Status */
396 tx4927_pcicptr->g2pstatus = TX4927_PCIC_G2PSTATUS_ALL;
397 /* Enable All Initiator Interrupts */
398 tx4927_pcicptr->g2pmask = TX4927_PCIC_G2PSTATUS_ALL;
399 /* Clear All PCI Status Error */
400 tx4927_pcicptr->pcistatus =
401 (tx4927_pcicptr->pcistatus & 0x0000ffff) |
402 (TX4927_PCIC_PCISTATUS_ALL << 16);
403 /* Enable All PCI Status Error Interrupts */
404 tx4927_pcicptr->pcimask = TX4927_PCIC_PCISTATUS_ALL;
405
406 /* PCIC Int => IRC IRQ16 */
407 tx4927_pcicptr->pcicfg2 =
408 (tx4927_pcicptr->pcicfg2 & 0xffffff00) | TX4927_IR_PCIC;
409
410 if (!(tx4927_ccfgptr->ccfg & TX4927_CCFG_PCIXARB)) {
411 /* XXX */
412 } else {
413 /* Reset Bus Arbiter */
414 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_RPBA;
415 /* Enable Bus Arbiter */
416 tx4927_pcicptr->pbacfg = TX4927_PCIC_PBACFG_PBAEN;
417 }
418
419 tx4927_pcicptr->pcistatus = PCI_COMMAND_MASTER |
420 PCI_COMMAND_MEMORY |
421 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
422} 181}
182arch_initcall(rbtx4927_arch_init);
423#endif /* CONFIG_PCI */ 183#endif /* CONFIG_PCI */
424 184
425static void __noreturn wait_forever(void) 185static void __noreturn wait_forever(void)
@@ -479,8 +239,6 @@ void __init plat_mem_setup(void)
479 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); 239 cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC);
480 write_c0_config(cp0_config); 240 write_c0_config(cp0_config);
481 241
482 set_io_port_base(KSEG1 + TBTX4927_ISA_IO_OFFSET);
483
484 ioport_resource.end = 0xffffffff; 242 ioport_resource.end = 0xffffffff;
485 iomem_resource.end = 0xffffffff; 243 iomem_resource.end = 0xffffffff;
486 244
@@ -492,8 +250,13 @@ void __init plat_mem_setup(void)
492 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL); 250 txx9_tmr_init(TX4927_TMR_REG(0) & 0xfffffffffULL);
493 251
494#ifdef CONFIG_PCI 252#ifdef CONFIG_PCI
253 txx9_alloc_pci_controller(&txx9_primary_pcic,
254 RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE,
255 RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE);
256#else
257 set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET);
258#endif
495 259
496 /* PCIC */
497 /* 260 /*
498 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz. 261 * ASSUMPTION: PCIDIVMODE is configured for PCI 33MHz or 66MHz.
499 * 262 *
@@ -517,58 +280,38 @@ void __init plat_mem_setup(void)
517 * 280 *
518 */ 281 */
519 if (mips_machtype == MACH_TOSHIBA_RBTX4937) 282 if (mips_machtype == MACH_TOSHIBA_RBTX4937)
520 switch ((unsigned long)tx4927_ccfgptr-> 283 switch ((unsigned long)__raw_readq(&tx4938_ccfgptr->ccfg) &
521 ccfg & TX4937_CCFG_PCIDIVMODE_MASK) { 284 TX4938_CCFG_PCIDIVMODE_MASK) {
522 case TX4937_CCFG_PCIDIVMODE_8: 285 case TX4938_CCFG_PCIDIVMODE_8:
523 case TX4937_CCFG_PCIDIVMODE_4: 286 case TX4938_CCFG_PCIDIVMODE_4:
524 tx4927_cpu_clock = 266666666; /* 266MHz */ 287 txx9_cpu_clock = 266666666; /* 266MHz */
525 break; 288 break;
526 case TX4937_CCFG_PCIDIVMODE_9: 289 case TX4938_CCFG_PCIDIVMODE_9:
527 case TX4937_CCFG_PCIDIVMODE_4_5: 290 case TX4938_CCFG_PCIDIVMODE_4_5:
528 tx4927_cpu_clock = 300000000; /* 300MHz */ 291 txx9_cpu_clock = 300000000; /* 300MHz */
529 break; 292 break;
530 default: 293 default:
531 tx4927_cpu_clock = 333333333; /* 333MHz */ 294 txx9_cpu_clock = 333333333; /* 333MHz */
532 } 295 }
533 else 296 else
534 switch ((unsigned long)tx4927_ccfgptr-> 297 switch ((unsigned long)__raw_readq(&tx4927_ccfgptr->ccfg) &
535 ccfg & TX4927_CCFG_PCIDIVMODE_MASK) { 298 TX4927_CCFG_PCIDIVMODE_MASK) {
536 case TX4927_CCFG_PCIDIVMODE_2_5: 299 case TX4927_CCFG_PCIDIVMODE_2_5:
537 case TX4927_CCFG_PCIDIVMODE_5: 300 case TX4927_CCFG_PCIDIVMODE_5:
538 tx4927_cpu_clock = 166666666; /* 166MHz */ 301 txx9_cpu_clock = 166666666; /* 166MHz */
539 break; 302 break;
540 default: 303 default:
541 tx4927_cpu_clock = 200000000; /* 200MHz */ 304 txx9_cpu_clock = 200000000; /* 200MHz */
542 } 305 }
306 /* change default value to udelay/mdelay take reasonable time */
307 loops_per_jiffy = txx9_cpu_clock / HZ / 2;
543 308
544 /* CCFG */ 309 /* CCFG */
545 /* do reset on watchdog */ 310 /* do reset on watchdog */
546 tx4927_ccfgptr->ccfg |= TX4927_CCFG_WR; 311 tx4927_ccfg_set(TX4927_CCFG_WR);
547 /* enable Timeout BusError */ 312 /* enable Timeout BusError */
548 if (tx4927_ccfg_toeon) 313 if (tx4927_ccfg_toeon)
549 tx4927_ccfgptr->ccfg |= TX4927_CCFG_TOE; 314 tx4927_ccfg_set(TX4927_CCFG_TOE);
550
551 tx4927_pci_setup();
552 if (tx4927_using_backplane == 1)
553 printk("backplane board IS installed\n");
554 else
555 printk("No Backplane \n");
556
557 /* this is on ISA bus behind PCI bus, so need PCI up first */
558#ifdef CONFIG_TOSHIBA_FPCIB0
559 if (tx4927_using_backplane) {
560 smsc_fdc37m81x_init(0x3f0);
561 smsc_fdc37m81x_config_beg();
562 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_DNUM,
563 SMSC_FDC37M81X_KBD);
564 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT, 1);
565 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_INT2, 12);
566 smsc_fdc37m81x_config_set(SMSC_FDC37M81X_ACTIVE,
567 1);
568 smsc_fdc37m81x_config_end();
569 }
570#endif
571#endif /* CONFIG_PCI */
572 315
573#ifdef CONFIG_SERIAL_TXX9 316#ifdef CONFIG_SERIAL_TXX9
574 { 317 {
@@ -611,8 +354,8 @@ void __init plat_mem_setup(void)
611 354
612void __init plat_time_init(void) 355void __init plat_time_init(void)
613{ 356{
614 mips_hpt_frequency = tx4927_cpu_clock / 2; 357 mips_hpt_frequency = txx9_cpu_clock / 2;
615 if (tx4927_ccfgptr->ccfg & TX4927_CCFG_TINTDIS) 358 if (____raw_readq(&tx4927_ccfgptr->ccfg) & TX4927_CCFG_TINTDIS)
616 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL, 359 txx9_clockevent_init(TX4927_TMR_REG(0) & 0xfffffffffULL,
617 TXX9_IRQ_BASE + 17, 360 TXX9_IRQ_BASE + 17,
618 50000000); 361 50000000);
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index bbd572c9675b..144d2cada820 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -15,7 +15,6 @@
15#include <linux/delay.h> 15#include <linux/delay.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/console.h> 17#include <linux/console.h>
18#include <linux/pci.h>
19#include <linux/pm.h> 18#include <linux/pm.h>
20#include <linux/platform_device.h> 19#include <linux/platform_device.h>
21#include <linux/clk.h> 20#include <linux/clk.h>
@@ -26,6 +25,8 @@
26#include <asm/txx9tmr.h> 25#include <asm/txx9tmr.h>
27#include <asm/io.h> 26#include <asm/io.h>
28#include <asm/bootinfo.h> 27#include <asm/bootinfo.h>
28#include <asm/txx9/generic.h>
29#include <asm/txx9/pci.h>
29#include <asm/txx9/rbtx4938.h> 30#include <asm/txx9/rbtx4938.h>
30#ifdef CONFIG_SERIAL_TXX9 31#ifdef CONFIG_SERIAL_TXX9
31#include <linux/serial_core.h> 32#include <linux/serial_core.h>
@@ -35,37 +36,13 @@
35#include <asm/txx9pio.h> 36#include <asm/txx9pio.h>
36 37
37extern char * __init prom_getcmdline(void); 38extern char * __init prom_getcmdline(void);
38static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
39
40/* These functions are used for rebooting or halting the machine*/ 39/* These functions are used for rebooting or halting the machine*/
41extern void rbtx4938_machine_restart(char *command); 40extern void rbtx4938_machine_restart(char *command);
42extern void rbtx4938_machine_halt(void); 41extern void rbtx4938_machine_halt(void);
43extern void rbtx4938_machine_power_off(void); 42extern void rbtx4938_machine_power_off(void);
44 43
45/* clocks */
46unsigned int txx9_master_clock;
47unsigned int txx9_cpu_clock;
48unsigned int txx9_gbus_clock;
49
50unsigned long rbtx4938_ce_base[8];
51unsigned long rbtx4938_ce_size[8];
52int txboard_pci66_mode;
53static int tx4938_pcic_trdyto; /* default: disabled */
54static int tx4938_pcic_retryto; /* default: disabled */
55static int tx4938_ccfg_toeon = 1; 44static int tx4938_ccfg_toeon = 1;
56 45
57struct tx4938_pcic_reg *pcicptrs[4] = {
58 tx4938_pcicptr /* default setting for TX4938 */
59};
60
61static struct {
62 unsigned long base;
63 unsigned long size;
64} phys_regions[16] __initdata;
65static int num_phys_regions __initdata;
66
67#define PHYS_REGION_MINSIZE 0x10000
68
69void rbtx4938_machine_halt(void) 46void rbtx4938_machine_halt(void)
70{ 47{
71 printk(KERN_NOTICE "System Halted\n"); 48 printk(KERN_NOTICE "System Halted\n");
@@ -95,473 +72,72 @@ void rbtx4938_machine_restart(char *command)
95 ; 72 ;
96} 73}
97 74
98void __init 75static void __init rbtx4938_pci_setup(void)
99txboard_add_phys_region(unsigned long base, unsigned long size)
100{
101 if (num_phys_regions >= ARRAY_SIZE(phys_regions)) {
102 printk("phys_region overflow\n");
103 return;
104 }
105 phys_regions[num_phys_regions].base = base;
106 phys_regions[num_phys_regions].size = size;
107 num_phys_regions++;
108}
109unsigned long __init
110txboard_find_free_phys_region(unsigned long begin, unsigned long end,
111 unsigned long size)
112{
113 unsigned long base;
114 int i;
115
116 for (base = begin / size * size; base < end; base += size) {
117 for (i = 0; i < num_phys_regions; i++) {
118 if (phys_regions[i].size &&
119 base <= phys_regions[i].base + (phys_regions[i].size - 1) &&
120 base + (size - 1) >= phys_regions[i].base)
121 break;
122 }
123 if (i == num_phys_regions)
124 return base;
125 }
126 return 0;
127}
128unsigned long __init
129txboard_find_free_phys_region_shrink(unsigned long begin, unsigned long end,
130 unsigned long *size)
131{
132 unsigned long sz, base;
133 for (sz = *size; sz >= PHYS_REGION_MINSIZE; sz /= 2) {
134 base = txboard_find_free_phys_region(begin, end, sz);
135 if (base) {
136 *size = sz;
137 return base;
138 }
139 }
140 return 0;
141}
142unsigned long __init
143txboard_request_phys_region_range(unsigned long begin, unsigned long end,
144 unsigned long size)
145{
146 unsigned long base;
147 base = txboard_find_free_phys_region(begin, end, size);
148 if (base)
149 txboard_add_phys_region(base, size);
150 return base;
151}
152unsigned long __init
153txboard_request_phys_region(unsigned long size)
154{ 76{
155 unsigned long base;
156 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
157 base = txboard_find_free_phys_region(begin, end, size);
158 if (base)
159 txboard_add_phys_region(base, size);
160 return base;
161}
162unsigned long __init
163txboard_request_phys_region_shrink(unsigned long *size)
164{
165 unsigned long base;
166 unsigned long begin = 0, end = 0x20000000; /* search low 512MB */
167 base = txboard_find_free_phys_region_shrink(begin, end, size);
168 if (base)
169 txboard_add_phys_region(base, *size);
170 return base;
171}
172
173#ifdef CONFIG_PCI 77#ifdef CONFIG_PCI
174void __init 78 int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
175tx4938_pcic_setup(struct tx4938_pcic_reg *pcicptr, 79 struct pci_controller *c = &txx9_primary_pcic;
176 struct pci_controller *channel,
177 unsigned long pci_io_base,
178 int extarb)
179{
180 int i;
181 80
182 /* Disable All Initiator Space */ 81 register_pci_controller(c);
183 pcicptr->pciccfg &= ~(TX4938_PCIC_PCICCFG_G2PMEN(0)|
184 TX4938_PCIC_PCICCFG_G2PMEN(1)|
185 TX4938_PCIC_PCICCFG_G2PMEN(2)|
186 TX4938_PCIC_PCICCFG_G2PIOEN);
187
188 /* GB->PCI mappings */
189 pcicptr->g2piomask = (channel->io_resource->end - channel->io_resource->start) >> 4;
190 pcicptr->g2piogbase = pci_io_base |
191#ifdef __BIG_ENDIAN
192 TX4938_PCIC_G2PIOGBASE_ECHG
193#else
194 TX4938_PCIC_G2PIOGBASE_BSDIS
195#endif
196 ;
197 pcicptr->g2piopbase = 0;
198 for (i = 0; i < 3; i++) {
199 pcicptr->g2pmmask[i] = 0;
200 pcicptr->g2pmgbase[i] = 0;
201 pcicptr->g2pmpbase[i] = 0;
202 }
203 if (channel->mem_resource->end) {
204 pcicptr->g2pmmask[0] = (channel->mem_resource->end - channel->mem_resource->start) >> 4;
205 pcicptr->g2pmgbase[0] = channel->mem_resource->start |
206#ifdef __BIG_ENDIAN
207 TX4938_PCIC_G2PMnGBASE_ECHG
208#else
209 TX4938_PCIC_G2PMnGBASE_BSDIS
210#endif
211 ;
212 pcicptr->g2pmpbase[0] = channel->mem_resource->start;
213 }
214 /* PCI->GB mappings (I/O 256B) */
215 pcicptr->p2giopbase = 0; /* 256B */
216 pcicptr->p2giogbase = 0;
217 /* PCI->GB mappings (MEM 512MB (64MB on R1.x)) */
218 pcicptr->p2gm0plbase = 0;
219 pcicptr->p2gm0pubase = 0;
220 pcicptr->p2gmgbase[0] = 0 |
221 TX4938_PCIC_P2GMnGBASE_TMEMEN |
222#ifdef __BIG_ENDIAN
223 TX4938_PCIC_P2GMnGBASE_TECHG
224#else
225 TX4938_PCIC_P2GMnGBASE_TBSDIS
226#endif
227 ;
228 /* PCI->GB mappings (MEM 16MB) */
229 pcicptr->p2gm1plbase = 0xffffffff;
230 pcicptr->p2gm1pubase = 0xffffffff;
231 pcicptr->p2gmgbase[1] = 0;
232 /* PCI->GB mappings (MEM 1MB) */
233 pcicptr->p2gm2pbase = 0xffffffff; /* 1MB */
234 pcicptr->p2gmgbase[2] = 0;
235
236 pcicptr->pciccfg &= TX4938_PCIC_PCICCFG_GBWC_MASK;
237 /* Enable Initiator Memory Space */
238 if (channel->mem_resource->end)
239 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PMEN(0);
240 /* Enable Initiator I/O Space */
241 if (channel->io_resource->end)
242 pcicptr->pciccfg |= TX4938_PCIC_PCICCFG_G2PIOEN;
243 /* Enable Initiator Config */
244 pcicptr->pciccfg |=
245 TX4938_PCIC_PCICCFG_ICAEN |
246 TX4938_PCIC_PCICCFG_TCAR;
247
248 /* Do not use MEMMUL, MEMINF: YMFPCI card causes M_ABORT. */
249 pcicptr->pcicfg1 = 0;
250
251 pcicptr->g2ptocnt &= ~0xffff;
252
253 if (tx4938_pcic_trdyto >= 0) {
254 pcicptr->g2ptocnt &= ~0xff;
255 pcicptr->g2ptocnt |= (tx4938_pcic_trdyto & 0xff);
256 }
257
258 if (tx4938_pcic_retryto >= 0) {
259 pcicptr->g2ptocnt &= ~0xff00;
260 pcicptr->g2ptocnt |= ((tx4938_pcic_retryto<<8) & 0xff00);
261 }
262
263 /* Clear All Local Bus Status */
264 pcicptr->pcicstatus = TX4938_PCIC_PCICSTATUS_ALL;
265 /* Enable All Local Bus Interrupts */
266 pcicptr->pcicmask = TX4938_PCIC_PCICSTATUS_ALL;
267 /* Clear All Initiator Status */
268 pcicptr->g2pstatus = TX4938_PCIC_G2PSTATUS_ALL;
269 /* Enable All Initiator Interrupts */
270 pcicptr->g2pmask = TX4938_PCIC_G2PSTATUS_ALL;
271 /* Clear All PCI Status Error */
272 pcicptr->pcistatus =
273 (pcicptr->pcistatus & 0x0000ffff) |
274 (TX4938_PCIC_PCISTATUS_ALL << 16);
275 /* Enable All PCI Status Error Interrupts */
276 pcicptr->pcimask = TX4938_PCIC_PCISTATUS_ALL;
277
278 if (!extarb) {
279 /* Reset Bus Arbiter */
280 pcicptr->pbacfg = TX4938_PCIC_PBACFG_RPBA;
281 pcicptr->pbabm = 0;
282 /* Enable Bus Arbiter */
283 pcicptr->pbacfg = TX4938_PCIC_PBACFG_PBAEN;
284 }
285
286 /* PCIC Int => IRC IRQ16 */
287 pcicptr->pcicfg2 =
288 (pcicptr->pcicfg2 & 0xffffff00) | TX4938_IR_PCIC;
289
290 pcicptr->pcistatus = PCI_COMMAND_MASTER |
291 PCI_COMMAND_MEMORY |
292 PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
293}
294
295int __init
296tx4938_report_pciclk(void)
297{
298 unsigned long pcode = TX4938_REV_PCODE();
299 int pciclk = 0;
300 printk("TX%lx PCIC --%s PCICLK:",
301 pcode,
302 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) ? " PCI66" : "");
303 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
304
305 switch ((unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK) {
306 case TX4938_CCFG_PCIDIVMODE_4:
307 pciclk = txx9_cpu_clock / 4; break;
308 case TX4938_CCFG_PCIDIVMODE_4_5:
309 pciclk = txx9_cpu_clock * 2 / 9; break;
310 case TX4938_CCFG_PCIDIVMODE_5:
311 pciclk = txx9_cpu_clock / 5; break;
312 case TX4938_CCFG_PCIDIVMODE_5_5:
313 pciclk = txx9_cpu_clock * 2 / 11; break;
314 case TX4938_CCFG_PCIDIVMODE_8:
315 pciclk = txx9_cpu_clock / 8; break;
316 case TX4938_CCFG_PCIDIVMODE_9:
317 pciclk = txx9_cpu_clock / 9; break;
318 case TX4938_CCFG_PCIDIVMODE_10:
319 pciclk = txx9_cpu_clock / 10; break;
320 case TX4938_CCFG_PCIDIVMODE_11:
321 pciclk = txx9_cpu_clock / 11; break;
322 }
323 printk("Internal(%dMHz)", pciclk / 1000000);
324 } else {
325 printk("External");
326 pciclk = -1;
327 }
328 printk("\n");
329 return pciclk;
330}
331
332void __init set_tx4938_pcicptr(int ch, struct tx4938_pcic_reg *pcicptr)
333{
334 pcicptrs[ch] = pcicptr;
335}
336
337struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch)
338{
339 return pcicptrs[ch];
340}
341
342static struct pci_dev *fake_pci_dev(struct pci_controller *hose,
343 int top_bus, int busnr, int devfn)
344{
345 static struct pci_dev dev;
346 static struct pci_bus bus;
347 82
348 dev.sysdata = bus.sysdata = hose; 83 if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
349 dev.devfn = devfn; 84 txx9_pci_option =
350 bus.number = busnr; 85 (txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
351 bus.ops = hose->pci_ops; 86 TXX9_PCI_OPT_CLK_66; /* already configured */
352 bus.parent = NULL;
353 dev.bus = &bus;
354
355 return &dev;
356}
357
358#define EARLY_PCI_OP(rw, size, type) \
359static int early_##rw##_config_##size(struct pci_controller *hose, \
360 int top_bus, int bus, int devfn, int offset, type value) \
361{ \
362 return pci_##rw##_config_##size( \
363 fake_pci_dev(hose, top_bus, bus, devfn), \
364 offset, value); \
365}
366
367EARLY_PCI_OP(read, word, u16 *)
368
369int txboard_pci66_check(struct pci_controller *hose, int top_bus, int current_bus)
370{
371 u32 pci_devfn;
372 unsigned short vid;
373 int devfn_start = 0;
374 int devfn_stop = 0xff;
375 int cap66 = -1;
376 u16 stat;
377
378 printk("PCI: Checking 66MHz capabilities...\n");
379
380 for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
381 if (early_read_config_word(hose, top_bus, current_bus,
382 pci_devfn, PCI_VENDOR_ID,
383 &vid) != PCIBIOS_SUCCESSFUL)
384 continue;
385
386 if (vid == 0xffff) continue;
387
388 /* check 66MHz capability */
389 if (cap66 < 0)
390 cap66 = 1;
391 if (cap66) {
392 early_read_config_word(hose, top_bus, current_bus, pci_devfn,
393 PCI_STATUS, &stat);
394 if (!(stat & PCI_STATUS_66MHZ)) {
395 printk(KERN_DEBUG "PCI: %02x:%02x not 66MHz capable.\n",
396 current_bus, pci_devfn);
397 cap66 = 0;
398 break;
399 }
400 }
401 }
402 return cap66 > 0;
403}
404
405int __init
406tx4938_pciclk66_setup(void)
407{
408 int pciclk;
409
410 /* Assert M66EN */
411 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI66;
412 /* Double PCICLK (if possible) */
413 if (tx4938_ccfgptr->pcfg & TX4938_PCFG_PCICLKEN_ALL) {
414 unsigned int pcidivmode =
415 tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIDIVMODE_MASK;
416 switch (pcidivmode) {
417 case TX4938_CCFG_PCIDIVMODE_8:
418 case TX4938_CCFG_PCIDIVMODE_4:
419 pcidivmode = TX4938_CCFG_PCIDIVMODE_4;
420 pciclk = txx9_cpu_clock / 4;
421 break;
422 case TX4938_CCFG_PCIDIVMODE_9:
423 case TX4938_CCFG_PCIDIVMODE_4_5:
424 pcidivmode = TX4938_CCFG_PCIDIVMODE_4_5;
425 pciclk = txx9_cpu_clock * 2 / 9;
426 break;
427 case TX4938_CCFG_PCIDIVMODE_10:
428 case TX4938_CCFG_PCIDIVMODE_5:
429 pcidivmode = TX4938_CCFG_PCIDIVMODE_5;
430 pciclk = txx9_cpu_clock / 5;
431 break;
432 case TX4938_CCFG_PCIDIVMODE_11:
433 case TX4938_CCFG_PCIDIVMODE_5_5:
434 default:
435 pcidivmode = TX4938_CCFG_PCIDIVMODE_5_5;
436 pciclk = txx9_cpu_clock * 2 / 11;
437 break;
438 }
439 tx4938_ccfgptr->ccfg =
440 (tx4938_ccfgptr->ccfg & ~TX4938_CCFG_PCIDIVMODE_MASK)
441 | pcidivmode;
442 printk(KERN_DEBUG "PCICLK: ccfg:%08lx\n",
443 (unsigned long)tx4938_ccfgptr->ccfg);
444 } else {
445 pciclk = -1;
446 }
447 return pciclk;
448}
449
450extern struct pci_controller tx4938_pci_controller[];
451static int __init tx4938_pcibios_init(void)
452{
453 unsigned long mem_base[2];
454 unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
455 unsigned long io_base[2];
456 unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
457 /* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
458 int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
459
460 PCIBIOS_MIN_IO = 0x00001000UL;
461
462 mem_base[0] = txboard_request_phys_region_shrink(&mem_size[0]);
463 io_base[0] = txboard_request_phys_region_shrink(&io_size[0]);
464
465 printk("TX4938 PCIC -- DID:%04x VID:%04x RID:%02x Arbiter:%s\n",
466 (unsigned short)(tx4938_pcicptr->pciid >> 16),
467 (unsigned short)(tx4938_pcicptr->pciid & 0xffff),
468 (unsigned short)(tx4938_pcicptr->pciccrev & 0xff),
469 extarb ? "External" : "Internal");
470
471 /* setup PCI area */
472 tx4938_pci_controller[0].io_resource->start = io_base[0];
473 tx4938_pci_controller[0].io_resource->end = (io_base[0] + io_size[0]) - 1;
474 tx4938_pci_controller[0].mem_resource->start = mem_base[0];
475 tx4938_pci_controller[0].mem_resource->end = mem_base[0] + mem_size[0] - 1;
476
477 set_tx4938_pcicptr(0, tx4938_pcicptr);
478
479 register_pci_controller(&tx4938_pci_controller[0]);
480
481 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI66) {
482 printk("TX4938_CCFG_PCI66 already configured\n");
483 txboard_pci66_mode = -1; /* already configured */
484 }
485 87
486 /* Reset PCI Bus */ 88 /* Reset PCI Bus */
487 writeb(0, rbtx4938_pcireset_addr); 89 writeb(0, rbtx4938_pcireset_addr);
488 /* Reset PCIC */ 90 /* Reset PCIC */
489 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 91 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
490 if (txboard_pci66_mode > 0) 92 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
93 TXX9_PCI_OPT_CLK_66)
491 tx4938_pciclk66_setup(); 94 tx4938_pciclk66_setup();
492 mdelay(10); 95 mdelay(10);
493 /* clear PCIC reset */ 96 /* clear PCIC reset */
494 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 97 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
495 writeb(1, rbtx4938_pcireset_addr); 98 writeb(1, rbtx4938_pcireset_addr);
496 mmiowb(); 99 iob();
497 tx4938_report_pcic_status1(tx4938_pcicptr);
498 100
499 tx4938_report_pciclk(); 101 tx4938_report_pciclk();
500 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); 102 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
501 if (txboard_pci66_mode == 0 && 103 if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
502 txboard_pci66_check(&tx4938_pci_controller[0], 0, 0)) { 104 TXX9_PCI_OPT_CLK_AUTO &&
105 txx9_pci66_check(c, 0, 0)) {
503 /* Reset PCI Bus */ 106 /* Reset PCI Bus */
504 writeb(0, rbtx4938_pcireset_addr); 107 writeb(0, rbtx4938_pcireset_addr);
505 /* Reset PCIC */ 108 /* Reset PCIC */
506 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIRST; 109 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
507 tx4938_pciclk66_setup(); 110 tx4938_pciclk66_setup();
508 mdelay(10); 111 mdelay(10);
509 /* clear PCIC reset */ 112 /* clear PCIC reset */
510 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIRST; 113 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
511 writeb(1, rbtx4938_pcireset_addr); 114 writeb(1, rbtx4938_pcireset_addr);
512 mmiowb(); 115 iob();
513 /* Reinitialize PCIC */ 116 /* Reinitialize PCIC */
514 tx4938_report_pciclk(); 117 tx4938_report_pciclk();
515 tx4938_pcic_setup(tx4938_pcicptr, &tx4938_pci_controller[0], io_base[0], extarb); 118 tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
516 } 119 }
517 120
518 mem_base[1] = txboard_request_phys_region_shrink(&mem_size[1]); 121 if (__raw_readq(&tx4938_ccfgptr->pcfg) &
519 io_base[1] = txboard_request_phys_region_shrink(&io_size[1]); 122 (TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
520 /* Reset PCIC1 */ 123 /* Reset PCIC1 */
521 tx4938_ccfgptr->clkctr |= TX4938_CLKCTR_PCIC1RST; 124 txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
522 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */ 125 /* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
523 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD)) 126 if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
524 tx4938_ccfgptr->ccfg |= TX4938_CCFG_PCI1_66; 127 & TX4938_CCFG_PCI1DMD))
525 else 128 tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
526 tx4938_ccfgptr->ccfg &= ~TX4938_CCFG_PCI1_66; 129 mdelay(10);
527 mdelay(10); 130 /* clear PCIC1 reset */
528 /* clear PCIC1 reset */ 131 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
529 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST; 132 tx4938_report_pci1clk();
530 tx4938_report_pcic_status1(tx4938_pcic1ptr); 133
531 134 /* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
532 printk("TX4938 PCIC1 -- DID:%04x VID:%04x RID:%02x", 135 c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
533 (unsigned short)(tx4938_pcic1ptr->pciid >> 16), 136 register_pci_controller(c);
534 (unsigned short)(tx4938_pcic1ptr->pciid & 0xffff), 137 tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
535 (unsigned short)(tx4938_pcic1ptr->pciccrev & 0xff)); 138 }
536 printk("%s PCICLK:%dMHz\n",
537 (tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1_66) ? " PCI66" : "",
538 txx9_gbus_clock /
539 ((tx4938_ccfgptr->ccfg & TX4938_CCFG_PCI1DMD) ? 4 : 2) /
540 1000000);
541
542 /* assumption: CPHYSADDR(mips_io_port_base) == io_base[0] */
543 tx4938_pci_controller[1].io_resource->start =
544 io_base[1] - io_base[0];
545 tx4938_pci_controller[1].io_resource->end =
546 io_base[1] - io_base[0] + io_size[1] - 1;
547 tx4938_pci_controller[1].mem_resource->start = mem_base[1];
548 tx4938_pci_controller[1].mem_resource->end =
549 mem_base[1] + mem_size[1] - 1;
550 set_tx4938_pcicptr(1, tx4938_pcic1ptr);
551
552 register_pci_controller(&tx4938_pci_controller[1]);
553
554 tx4938_pcic_setup(tx4938_pcic1ptr, &tx4938_pci_controller[1], io_base[1], extarb);
555
556 /* map ioport 0 to PCI I/O space address 0 */
557 set_io_port_base(KSEG1 + io_base[0]);
558
559 return 0;
560}
561
562arch_initcall(tx4938_pcibios_init);
563
564#endif /* CONFIG_PCI */ 139#endif /* CONFIG_PCI */
140}
565 141
566/* SPI support */ 142/* SPI support */
567 143
@@ -594,7 +170,7 @@ static int __init rbtx4938_ethaddr_init(void)
594 unsigned int id = 170 unsigned int id =
595 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0); 171 TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
596 struct platform_device *pdev; 172 struct platform_device *pdev;
597 if (!(tx4938_ccfgptr->pcfg & 173 if (!(__raw_readq(&tx4938_ccfgptr->pcfg) &
598 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL))) 174 (i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
599 continue; 175 continue;
600 pdev = platform_device_alloc("tc35815-mac", id); 176 pdev = platform_device_alloc("tc35815-mac", id);
@@ -611,18 +187,12 @@ device_initcall(rbtx4938_ethaddr_init);
611static void __init rbtx4938_spi_setup(void) 187static void __init rbtx4938_spi_setup(void)
612{ 188{
613 /* set SPI_SEL */ 189 /* set SPI_SEL */
614 tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL; 190 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
615} 191}
616 192
617static struct resource rbtx4938_fpga_resource; 193static struct resource rbtx4938_fpga_resource;
618 194static struct resource tx4938_sdram_resource[4];
619static char pcode_str[8]; 195static struct resource tx4938_sram_resource;
620static struct resource tx4938_reg_resource = {
621 .start = TX4938_REG_BASE,
622 .end = TX4938_REG_BASE + TX4938_REG_SIZE,
623 .name = pcode_str,
624 .flags = IORESOURCE_MEM
625};
626 196
627void __init tx4938_board_setup(void) 197void __init tx4938_board_setup(void)
628{ 198{
@@ -631,24 +201,28 @@ void __init tx4938_board_setup(void)
631 int cpuclk = 0; 201 int cpuclk = 0;
632 unsigned long pcode = TX4938_REV_PCODE(); 202 unsigned long pcode = TX4938_REV_PCODE();
633 203
634 ioport_resource.start = 0x1000; 204 ioport_resource.start = 0;
635 ioport_resource.end = 0xffffffff; 205 ioport_resource.end = 0xffffffff;
636 iomem_resource.start = 0x1000; 206 iomem_resource.start = 0;
637 iomem_resource.end = 0xffffffff; /* expand to 4GB */ 207 iomem_resource.end = 0xffffffff; /* expand to 4GB */
638 208
639 sprintf(pcode_str, "TX%lx", pcode); 209 txx9_reg_res_init(pcode, TX4938_REG_BASE,
210 TX4938_REG_SIZE);
640 /* SDRAMC,EBUSC are configured by PROM */ 211 /* SDRAMC,EBUSC are configured by PROM */
641 for (i = 0; i < 8; i++) { 212 for (i = 0; i < 8; i++) {
642 if (!(tx4938_ebuscptr->cr[i] & 0x8)) 213 if (!(TX4938_EBUSC_CR(i) & 0x8))
643 continue; /* disabled */ 214 continue; /* disabled */
644 rbtx4938_ce_base[i] = (unsigned long)TX4938_EBUSC_BA(i); 215 txx9_ce_res[i].start = (unsigned long)TX4938_EBUSC_BA(i);
645 txboard_add_phys_region(rbtx4938_ce_base[i], TX4938_EBUSC_SIZE(i)); 216 txx9_ce_res[i].end =
217 txx9_ce_res[i].start + TX4938_EBUSC_SIZE(i) - 1;
218 request_resource(&iomem_resource, &txx9_ce_res[i]);
646 } 219 }
647 220
648 /* clocks */ 221 /* clocks */
649 if (txx9_master_clock) { 222 if (txx9_master_clock) {
223 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
650 /* calculate gbus_clock and cpu_clock_freq from master_clock */ 224 /* calculate gbus_clock and cpu_clock_freq from master_clock */
651 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; 225 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
652 switch (divmode) { 226 switch (divmode) {
653 case TX4938_CCFG_DIVMODE_8: 227 case TX4938_CCFG_DIVMODE_8:
654 case TX4938_CCFG_DIVMODE_10: 228 case TX4938_CCFG_DIVMODE_10:
@@ -678,12 +252,13 @@ void __init tx4938_board_setup(void)
678 } 252 }
679 txx9_cpu_clock = cpuclk; 253 txx9_cpu_clock = cpuclk;
680 } else { 254 } else {
255 u64 ccfg = ____raw_readq(&tx4938_ccfgptr->ccfg);
681 if (txx9_cpu_clock == 0) { 256 if (txx9_cpu_clock == 0) {
682 txx9_cpu_clock = 300000000; /* 300MHz */ 257 txx9_cpu_clock = 300000000; /* 300MHz */
683 } 258 }
684 /* calculate gbus_clock and master_clock from cpu_clock_freq */ 259 /* calculate gbus_clock and master_clock from cpu_clock_freq */
685 cpuclk = txx9_cpu_clock; 260 cpuclk = txx9_cpu_clock;
686 divmode = (unsigned long)tx4938_ccfgptr->ccfg & TX4938_CCFG_DIVMODE_MASK; 261 divmode = (__u32)ccfg & TX4938_CCFG_DIVMODE_MASK;
687 switch (divmode) { 262 switch (divmode) {
688 case TX4938_CCFG_DIVMODE_2: 263 case TX4938_CCFG_DIVMODE_2:
689 case TX4938_CCFG_DIVMODE_8: 264 case TX4938_CCFG_DIVMODE_8:
@@ -717,32 +292,32 @@ void __init tx4938_board_setup(void)
717 292
718 /* CCFG */ 293 /* CCFG */
719 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */ 294 /* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
720 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW; 295 tx4938_ccfg_set(TX4938_CCFG_WDRST | TX4938_CCFG_BEOW);
721 /* do reset on watchdog */ 296 /* do reset on watchdog */
722 tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR; 297 tx4938_ccfg_set(TX4938_CCFG_WR);
723 /* clear PCIC1 reset */ 298 /* clear PCIC1 reset */
724 if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST) 299 txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
725 tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
726 300
727 /* enable Timeout BusError */ 301 /* enable Timeout BusError */
728 if (tx4938_ccfg_toeon) 302 if (tx4938_ccfg_toeon)
729 tx4938_ccfgptr->ccfg |= TX4938_CCFG_TOE; 303 tx4938_ccfg_set(TX4938_CCFG_TOE);
730 304
731 /* DMA selection */ 305 /* DMA selection */
732 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_DMASEL_ALL; 306 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_DMASEL_ALL);
733 307
734 /* Use external clock for external arbiter */ 308 /* Use external clock for external arbiter */
735 if (!(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB)) 309 if (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB))
736 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_PCICLKEN_ALL; 310 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_PCICLKEN_ALL);
737 311
738 printk("%s -- %dMHz(M%dMHz) CRIR:%08lx CCFG:%Lx PCFG:%Lx\n", 312 printk(KERN_INFO "%s -- %dMHz(M%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
739 pcode_str, 313 txx9_pcode_str,
740 cpuclk / 1000000, txx9_master_clock / 1000000, 314 (cpuclk + 500000) / 1000000,
741 (unsigned long)tx4938_ccfgptr->crir, 315 (txx9_master_clock + 500000) / 1000000,
742 tx4938_ccfgptr->ccfg, 316 (__u32)____raw_readq(&tx4938_ccfgptr->crir),
743 tx4938_ccfgptr->pcfg); 317 (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
744 318 (unsigned long long)____raw_readq(&tx4938_ccfgptr->pcfg));
745 printk("%s SDRAMC --", pcode_str); 319
320 printk(KERN_INFO "%s SDRAMC --", txx9_pcode_str);
746 for (i = 0; i < 4; i++) { 321 for (i = 0; i < 4; i++) {
747 unsigned long long cr = tx4938_sdramcptr->cr[i]; 322 unsigned long long cr = tx4938_sdramcptr->cr[i];
748 unsigned long ram_base, ram_size; 323 unsigned long ram_base, ram_size;
@@ -753,16 +328,24 @@ void __init tx4938_board_setup(void)
753 if (ram_base >= 0x20000000) 328 if (ram_base >= 0x20000000)
754 continue; /* high memory (ignore) */ 329 continue; /* high memory (ignore) */
755 printk(" CR%d:%016Lx", i, cr); 330 printk(" CR%d:%016Lx", i, cr);
756 txboard_add_phys_region(ram_base, ram_size); 331 tx4938_sdram_resource[i].name = "SDRAM";
332 tx4938_sdram_resource[i].start = ram_base;
333 tx4938_sdram_resource[i].end = ram_base + ram_size - 1;
334 tx4938_sdram_resource[i].flags = IORESOURCE_MEM;
335 request_resource(&iomem_resource, &tx4938_sdram_resource[i]);
757 } 336 }
758 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr); 337 printk(" TR:%09Lx\n", tx4938_sdramcptr->tr);
759 338
760 /* SRAM */ 339 /* SRAM */
761 if (pcode == 0x4938 && tx4938_sramcptr->cr & 1) { 340 if (tx4938_sramcptr->cr & 1) {
762 unsigned int size = 0x800; 341 unsigned int size = 0x800;
763 unsigned long base = 342 unsigned long base =
764 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1); 343 (tx4938_sramcptr->cr >> (39-11)) & ~(size - 1);
765 txboard_add_phys_region(base, size); 344 tx4938_sram_resource.name = "SRAM";
345 tx4938_sram_resource.start = base;
346 tx4938_sram_resource.end = base + size - 1;
347 tx4938_sram_resource.flags = IORESOURCE_MEM;
348 request_resource(&iomem_resource, &tx4938_sram_resource);
766 } 349 }
767 350
768 /* TMR */ 351 /* TMR */
@@ -778,71 +361,15 @@ void __init tx4938_board_setup(void)
778 __raw_writel(0, &tx4938_pioptr->maskcpu); 361 __raw_writel(0, &tx4938_pioptr->maskcpu);
779 __raw_writel(0, &tx4938_pioptr->maskext); 362 __raw_writel(0, &tx4938_pioptr->maskext);
780 363
781 /* TX4938 internal registers */
782 if (request_resource(&iomem_resource, &tx4938_reg_resource))
783 printk("request resource for internal registers failed\n");
784}
785
786#ifdef CONFIG_PCI 364#ifdef CONFIG_PCI
787static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr) 365 txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
788{ 366#endif
789 unsigned short pcistatus = (unsigned short)(pcicptr->pcistatus >> 16);
790 unsigned long g2pstatus = pcicptr->g2pstatus;
791 unsigned long pcicstatus = pcicptr->pcicstatus;
792 static struct {
793 unsigned long flag;
794 const char *str;
795 } pcistat_tbl[] = {
796 { PCI_STATUS_DETECTED_PARITY, "DetectedParityError" },
797 { PCI_STATUS_SIG_SYSTEM_ERROR, "SignaledSystemError" },
798 { PCI_STATUS_REC_MASTER_ABORT, "ReceivedMasterAbort" },
799 { PCI_STATUS_REC_TARGET_ABORT, "ReceivedTargetAbort" },
800 { PCI_STATUS_SIG_TARGET_ABORT, "SignaledTargetAbort" },
801 { PCI_STATUS_PARITY, "MasterParityError" },
802 }, g2pstat_tbl[] = {
803 { TX4938_PCIC_G2PSTATUS_TTOE, "TIOE" },
804 { TX4938_PCIC_G2PSTATUS_RTOE, "RTOE" },
805 }, pcicstat_tbl[] = {
806 { TX4938_PCIC_PCICSTATUS_PME, "PME" },
807 { TX4938_PCIC_PCICSTATUS_TLB, "TLB" },
808 { TX4938_PCIC_PCICSTATUS_NIB, "NIB" },
809 { TX4938_PCIC_PCICSTATUS_ZIB, "ZIB" },
810 { TX4938_PCIC_PCICSTATUS_PERR, "PERR" },
811 { TX4938_PCIC_PCICSTATUS_SERR, "SERR" },
812 { TX4938_PCIC_PCICSTATUS_GBE, "GBE" },
813 { TX4938_PCIC_PCICSTATUS_IWB, "IWB" },
814 };
815 int i;
816
817 printk("pcistat:%04x(", pcistatus);
818 for (i = 0; i < ARRAY_SIZE(pcistat_tbl); i++)
819 if (pcistatus & pcistat_tbl[i].flag)
820 printk("%s ", pcistat_tbl[i].str);
821 printk("), g2pstatus:%08lx(", g2pstatus);
822 for (i = 0; i < ARRAY_SIZE(g2pstat_tbl); i++)
823 if (g2pstatus & g2pstat_tbl[i].flag)
824 printk("%s ", g2pstat_tbl[i].str);
825 printk("), pcicstatus:%08lx(", pcicstatus);
826 for (i = 0; i < ARRAY_SIZE(pcicstat_tbl); i++)
827 if (pcicstatus & pcicstat_tbl[i].flag)
828 printk("%s ", pcicstat_tbl[i].str);
829 printk(")\n");
830}
831
832void tx4938_report_pcic_status(void)
833{
834 int i;
835 struct tx4938_pcic_reg *pcicptr;
836 for (i = 0; (pcicptr = get_tx4938_pcicptr(i)) != NULL; i++)
837 tx4938_report_pcic_status1(pcicptr);
838} 367}
839 368
840#endif /* CONFIG_PCI */
841
842void __init plat_time_init(void) 369void __init plat_time_init(void)
843{ 370{
844 mips_hpt_frequency = txx9_cpu_clock / 2; 371 mips_hpt_frequency = txx9_cpu_clock / 2;
845 if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS) 372 if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_TINTDIS)
846 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL, 373 txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
847 TXX9_IRQ_BASE + TX4938_IR_TMR(0), 374 TXX9_IRQ_BASE + TX4938_IR_TMR(0),
848 txx9_gbus_clock / 2); 375 txx9_gbus_clock / 2);
@@ -890,19 +417,20 @@ void __init plat_mem_setup(void)
890#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 417#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
891 printk("PIOSEL: disabling both ata and nand selection\n"); 418 printk("PIOSEL: disabling both ata and nand selection\n");
892 local_irq_disable(); 419 local_irq_disable();
893 tx4938_ccfgptr->pcfg &= ~(TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); 420 txx9_clear64(&tx4938_ccfgptr->pcfg,
421 TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
894#endif 422#endif
895 423
896#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND 424#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
897 printk("PIOSEL: enabling nand selection\n"); 425 printk("PIOSEL: enabling nand selection\n");
898 tx4938_ccfgptr->pcfg |= TX4938_PCFG_NDF_SEL; 426 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
899 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_ATA_SEL; 427 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
900#endif 428#endif
901 429
902#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA 430#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
903 printk("PIOSEL: enabling ata selection\n"); 431 printk("PIOSEL: enabling ata selection\n");
904 tx4938_ccfgptr->pcfg |= TX4938_PCFG_ATA_SEL; 432 txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
905 tx4938_ccfgptr->pcfg &= ~TX4938_PCFG_NDF_SEL; 433 txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
906#endif 434#endif
907 435
908#ifdef CONFIG_IP_PNP 436#ifdef CONFIG_IP_PNP
@@ -920,7 +448,7 @@ void __init plat_mem_setup(void)
920#endif 448#endif
921 449
922 rbtx4938_spi_setup(); 450 rbtx4938_spi_setup();
923 pcfg = tx4938_ccfgptr->pcfg; /* updated */ 451 pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
924 /* fixup piosel */ 452 /* fixup piosel */
925 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == 453 if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
926 TX4938_PCFG_ATA_SEL) 454 TX4938_PCFG_ATA_SEL)
@@ -1063,6 +591,7 @@ static int __init rbtx4938_arch_init(void)
1063{ 591{
1064 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16); 592 txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
1065 gpiochip_add(&rbtx4938_spi_gpio_chip); 593 gpiochip_add(&rbtx4938_spi_gpio_chip);
594 rbtx4938_pci_setup();
1066 return rbtx4938_spi_init(); 595 return rbtx4938_spi_init();
1067} 596}
1068arch_initcall(rbtx4938_arch_init); 597arch_initcall(rbtx4938_arch_init);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-27 17:12:19 -0500