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authorWill Deacon <will.deacon@arm.com>2012-08-10 14:13:36 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2012-08-11 04:16:00 -0400
commit730a8128cd8978467eb1cf546b11014acb57d433 (patch)
tree010d027425130eb77c868c69365d6b0eb1c5a604 /arch
parentf5f2025ef3e2cdb593707cbf87378761f17befbe (diff)
ARM: 7489/1: errata: fix workaround for erratum #720789 on UP systems
Commit 5a783cbc4836 ("ARM: 7478/1: errata: extend workaround for erratum #720789") added workarounds for erratum #720789 to the range TLB invalidation functions with the observation that the erratum only affects SMP platforms. However, when running an SMP_ON_UP kernel on a uniprocessor platform we must take care to preserve the ASID as the workaround is not required. This patch ensures that we don't set the ASID to 0 when flushing the TLB on such a system, preserving the original behaviour with the workaround disabled. Cc: <stable@vger.kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mm/tlb-v7.S6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mm/tlb-v7.S b/arch/arm/mm/tlb-v7.S
index c2021139cb56..ea94765acf9a 100644
--- a/arch/arm/mm/tlb-v7.S
+++ b/arch/arm/mm/tlb-v7.S
@@ -38,10 +38,10 @@ ENTRY(v7wbi_flush_user_tlb_range)
38 dsb 38 dsb
39 mov r0, r0, lsr #PAGE_SHIFT @ align address 39 mov r0, r0, lsr #PAGE_SHIFT @ align address
40 mov r1, r1, lsr #PAGE_SHIFT 40 mov r1, r1, lsr #PAGE_SHIFT
41#ifdef CONFIG_ARM_ERRATA_720789
42 mov r3, #0
43#else
44 asid r3, r3 @ mask ASID 41 asid r3, r3 @ mask ASID
42#ifdef CONFIG_ARM_ERRATA_720789
43 ALT_SMP(W(mov) r3, #0 )
44 ALT_UP(W(nop) )
45#endif 45#endif
46 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA 46 orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
47 mov r1, r1, lsl #PAGE_SHIFT 47 mov r1, r1, lsl #PAGE_SHIFT