Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc

Pull sparc fixes from David Miller:
 "Just some minor fixups, a sunsu console setup panic cure, and
  recognition of a Fujitsu sun4v cpu."

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc:
  sparc: remove unused "config BITS"
  sparc: delete "if !ULTRA_HAS_POPULATION_COUNT"
  sparc64: correctly recognize SPARC64-X chips
  sparc,leon: fix GRPCI2 device0 PCI config space access
  sunsu: Fix panic in case of nonexistent port at "console=ttySY" cmdline option

5 files changed, 57 insertions, 24 deletions

diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index 289127d5241c..3d361f236308 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -84,12 +84,6 @@ config ARCH_DEFCONFIG
         default "arch/sparc/configs/sparc32_defconfig" if SPARC32
         default "arch/sparc/configs/sparc64_defconfig" if SPARC64
 
-# CONFIG_BITS can be used at source level to get 32/64 bits
-config BITS
-        int
-        default 32 if SPARC32
-        default 64 if SPARC64
-
 config IOMMU_HELPER
         bool
         default y if SPARC64
@@ -197,7 +191,7 @@ config RWSEM_XCHGADD_ALGORITHM
 
 config GENERIC_HWEIGHT
         bool
-        default y if !ULTRA_HAS_POPULATION_COUNT
+        default y
 
 config GENERIC_CALIBRATE_DELAY
         bool
diff --git a/arch/sparc/include/asm/spitfire.h b/arch/sparc/include/asm/spitfire.h
index d06a26601753..6b67e50fb9b4 100644
--- a/arch/sparc/include/asm/spitfire.h
+++ b/arch/sparc/include/asm/spitfire.h
@@ -45,6 +45,7 @@
 #define SUN4V_CHIP_NIAGARA3     0x03
 #define SUN4V_CHIP_NIAGARA4     0x04
 #define SUN4V_CHIP_NIAGARA5     0x05
+#define SUN4V_CHIP_SPARC64X     0x8a
 #define SUN4V_CHIP_UNKNOWN      0xff
 
 #ifndef __ASSEMBLY__
diff --git a/arch/sparc/kernel/cpu.c b/arch/sparc/kernel/cpu.c
index a6c94a2bf9d4..5c5125895db8 100644
--- a/arch/sparc/kernel/cpu.c
+++ b/arch/sparc/kernel/cpu.c
@@ -493,6 +493,12 @@ static void __init sun4v_cpu_probe(void)
                 sparc_pmu_type = "niagara5";
                 break;
 
+        case SUN4V_CHIP_SPARC64X:
+                sparc_cpu_type = "SPARC64-X";
+                sparc_fpu_type = "SPARC64-X integrated FPU";
+                sparc_pmu_type = "sparc64-x";
+                break;
+
         default:
                 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
                        prom_cpu_compatible);
diff --git a/arch/sparc/kernel/head_64.S b/arch/sparc/kernel/head_64.S
index 2feb15c35d9e..26b706a1867d 100644
--- a/arch/sparc/kernel/head_64.S
+++ b/arch/sparc/kernel/head_64.S
@@ -134,6 +134,8 @@ prom_niagara_prefix:
         .asciz  "SUNW,UltraSPARC-T"
 prom_sparc_prefix:
         .asciz  "SPARC-"
+prom_sparc64x_prefix:
+        .asciz  "SPARC64-X"
         .align  4
 prom_root_compatible:
         .skip   64
@@ -412,7 +414,7 @@ sun4v_chip_type:
         cmp     %g2, 'T'
         be,pt   %xcc, 70f
          cmp    %g2, 'M'
-        bne,pn  %xcc, 4f
+        bne,pn  %xcc, 49f
          nop
 
 70:     ldub    [%g1 + 7], %g2
@@ -425,7 +427,7 @@ sun4v_chip_type:
         cmp     %g2, '5'
         be,pt   %xcc, 5f
          mov    SUN4V_CHIP_NIAGARA5, %g4
-        ba,pt   %xcc, 4f
+        ba,pt   %xcc, 49f
          nop
 
 91:     sethi   %hi(prom_cpu_compatible), %g1
@@ -439,6 +441,25 @@ sun4v_chip_type:
          mov    SUN4V_CHIP_NIAGARA2, %g4
         
 4:
+        /* Athena */
+        sethi   %hi(prom_cpu_compatible), %g1
+        or      %g1, %lo(prom_cpu_compatible), %g1
+        sethi   %hi(prom_sparc64x_prefix), %g7
+        or      %g7, %lo(prom_sparc64x_prefix), %g7
+        mov     9, %g3
+41:     ldub    [%g7], %g2
+        ldub    [%g1], %g4
+        cmp     %g2, %g4
+        bne,pn  %icc, 49f
+        add     %g7, 1, %g7
+        subcc   %g3, 1, %g3
+        bne,pt  %xcc, 41b
+        add     %g1, 1, %g1
+        mov     SUN4V_CHIP_SPARC64X, %g4
+        ba,pt   %xcc, 5f
+        nop
+
+49:
         mov     SUN4V_CHIP_UNKNOWN, %g4
 5:      sethi   %hi(sun4v_chip_type), %g2
         or      %g2, %lo(sun4v_chip_type), %g2
diff --git a/arch/sparc/kernel/leon_pci_grpci2.c b/arch/sparc/kernel/leon_pci_grpci2.c
index fc4320886a3a..4d1487138d26 100644
--- a/arch/sparc/kernel/leon_pci_grpci2.c
+++ b/arch/sparc/kernel/leon_pci_grpci2.c
@@ -186,6 +186,8 @@ struct grpci2_cap_first {
 #define CAP9_IOMAP_OFS 0x20
 #define CAP9_BARSIZE_OFS 0x24
 
+#define TGT 256
+
 struct grpci2_priv {
         struct leon_pci_info    info; /* must be on top of this structure */
         struct grpci2_regs      *regs;
@@ -237,8 +239,12 @@ static int grpci2_cfg_r32(struct grpci2_priv *priv, unsigned int bus,
         if (where & 0x3)
                 return -EINVAL;
 
-        if (bus == 0 && PCI_SLOT(devfn) != 0)
-                devfn += (0x8 * 6);
+        if (bus == 0) {
+                devfn += (0x8 * 6); /* start at AD16=Device0 */
+        } else if (bus == TGT) {
+                bus = 0;
+                devfn = 0; /* special case: bridge controller itself */
+        }
 
         /* Select bus */
         spin_lock_irqsave(&grpci2_dev_lock, flags);
@@ -303,8 +309,12 @@ static int grpci2_cfg_w32(struct grpci2_priv *priv, unsigned int bus,
         if (where & 0x3)
                 return -EINVAL;
 
-        if (bus == 0 && PCI_SLOT(devfn) != 0)
-                devfn += (0x8 * 6);
+        if (bus == 0) {
+                devfn += (0x8 * 6); /* start at AD16=Device0 */
+        } else if (bus == TGT) {
+                bus = 0;
+                devfn = 0; /* special case: bridge controller itself */
+        }
 
         /* Select bus */
         spin_lock_irqsave(&grpci2_dev_lock, flags);
@@ -368,7 +378,7 @@ static int grpci2_read_config(struct pci_bus *bus, unsigned int devfn,
         unsigned int busno = bus->number;
         int ret;
 
-        if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0)) {
+        if (PCI_SLOT(devfn) > 15 || busno > 255) {
                 *val = ~0;
                 return 0;
         }
@@ -406,7 +416,7 @@ static int grpci2_write_config(struct pci_bus *bus, unsigned int devfn,
         struct grpci2_priv *priv = grpci2priv;
         unsigned int busno = bus->number;
 
-        if (PCI_SLOT(devfn) > 15 || (PCI_SLOT(devfn) == 0 && busno == 0))
+        if (PCI_SLOT(devfn) > 15 || busno > 255)
                 return 0;
 
 #ifdef GRPCI2_DEBUG_CFGACCESS
@@ -578,15 +588,15 @@ void grpci2_hw_init(struct grpci2_priv *priv)
                 REGSTORE(regs->ahbmst_map[i], priv->pci_area);
 
         /* Get the GRPCI2 Host PCI ID */
-        grpci2_cfg_r32(priv, 0, 0, PCI_VENDOR_ID, &priv->pciid);
+        grpci2_cfg_r32(priv, TGT, 0, PCI_VENDOR_ID, &priv->pciid);
 
         /* Get address to first (always defined) capability structure */
-        grpci2_cfg_r8(priv, 0, 0, PCI_CAPABILITY_LIST, &capptr);
+        grpci2_cfg_r8(priv, TGT, 0, PCI_CAPABILITY_LIST, &capptr);
 
         /* Enable/Disable Byte twisting */
-        grpci2_cfg_r32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, &io_map);
+        grpci2_cfg_r32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, &io_map);
         io_map = (io_map & ~0x1) | (priv->bt_enabled ? 1 : 0);
-        grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_IOMAP_OFS, io_map);
+        grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_IOMAP_OFS, io_map);
 
         /* Setup the Host's PCI Target BARs for other peripherals to access,
          * and do DMA to the host's memory. The target BARs can be sized and
@@ -617,17 +627,18 @@ void grpci2_hw_init(struct grpci2_priv *priv)
                                 pciadr = 0;
                         }
                 }
-                grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BARSIZE_OFS+i*4, bar_sz);
-                grpci2_cfg_w32(priv, 0, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
-                grpci2_cfg_w32(priv, 0, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
+                grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BARSIZE_OFS+i*4,
+                                bar_sz);
+                grpci2_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0+i*4, pciadr);
+                grpci2_cfg_w32(priv, TGT, 0, capptr+CAP9_BAR_OFS+i*4, ahbadr);
                 printk(KERN_INFO "        TGT BAR[%d]: 0x%08x (PCI)-> 0x%08x\n",
                         i, pciadr, ahbadr);
         }
 
         /* set as bus master and enable pci memory responses */
-        grpci2_cfg_r32(priv, 0, 0, PCI_COMMAND, &data);
+        grpci2_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
         data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-        grpci2_cfg_w32(priv, 0, 0, PCI_COMMAND, data);
+        grpci2_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
 
         /* Enable Error respone (CPU-TRAP) on illegal memory access. */
         REGSTORE(regs->ctrl, CTRL_ER | CTRL_PE);