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authorAl Viro <viro@ftp.linux.org.uk>2007-02-09 11:39:50 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-02-09 12:14:08 -0500
commitf1fda89522c5aaa1bd4ef69605e85e6ee9c85faf (patch)
treec70d3c771ee533ba294cfcf17e6ccf021a496f21 /arch
parent95389b86fd07660970a3e6498405d53037c035e9 (diff)
[PATCH] powerpc: celleb trivial endianness and iomem annotations
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/powerpc/platforms/celleb/pci.c12
-rw-r--r--arch/powerpc/platforms/celleb/scc_epci.c56
2 files changed, 34 insertions, 34 deletions
diff --git a/arch/powerpc/platforms/celleb/pci.c b/arch/powerpc/platforms/celleb/pci.c
index 867f83a7d0c9..98de836dfed3 100644
--- a/arch/powerpc/platforms/celleb/pci.c
+++ b/arch/powerpc/platforms/celleb/pci.c
@@ -65,13 +65,13 @@ static inline u8 celleb_fake_config_readb(void *addr)
65 65
66static inline u16 celleb_fake_config_readw(void *addr) 66static inline u16 celleb_fake_config_readw(void *addr)
67{ 67{
68 u16 *p = addr; 68 __le16 *p = addr;
69 return le16_to_cpu(*p); 69 return le16_to_cpu(*p);
70} 70}
71 71
72static inline u32 celleb_fake_config_readl(void *addr) 72static inline u32 celleb_fake_config_readl(void *addr)
73{ 73{
74 u32 *p = addr; 74 __le32 *p = addr;
75 return le32_to_cpu(*p); 75 return le32_to_cpu(*p);
76} 76}
77 77
@@ -83,16 +83,16 @@ static inline void celleb_fake_config_writeb(u32 val, void *addr)
83 83
84static inline void celleb_fake_config_writew(u32 val, void *addr) 84static inline void celleb_fake_config_writew(u32 val, void *addr)
85{ 85{
86 u16 val16; 86 __le16 val16;
87 u16 *p = addr; 87 __le16 *p = addr;
88 val16 = cpu_to_le16(val); 88 val16 = cpu_to_le16(val);
89 *p = val16; 89 *p = val16;
90} 90}
91 91
92static inline void celleb_fake_config_writel(u32 val, void *addr) 92static inline void celleb_fake_config_writel(u32 val, void *addr)
93{ 93{
94 u32 val32; 94 __le32 val32;
95 u32 *p = addr; 95 __le32 *p = addr;
96 val32 = cpu_to_le32(val); 96 val32 = cpu_to_le32(val);
97 *p = val32; 97 *p = val32;
98} 98}
diff --git a/arch/powerpc/platforms/celleb/scc_epci.c b/arch/powerpc/platforms/celleb/scc_epci.c
index 0edbc0c4f338..c11b39c3776a 100644
--- a/arch/powerpc/platforms/celleb/scc_epci.c
+++ b/arch/powerpc/platforms/celleb/scc_epci.c
@@ -47,7 +47,7 @@
47#if 0 /* test code for epci dummy read */ 47#if 0 /* test code for epci dummy read */
48static void celleb_epci_dummy_read(struct pci_dev *dev) 48static void celleb_epci_dummy_read(struct pci_dev *dev)
49{ 49{
50 void *epci_base; 50 void __iomem *epci_base;
51 struct device_node *node; 51 struct device_node *node;
52 struct pci_controller *hose; 52 struct pci_controller *hose;
53 u32 val; 53 u32 val;
@@ -58,7 +58,7 @@ static void celleb_epci_dummy_read(struct pci_dev *dev)
58 if (!hose) 58 if (!hose)
59 return; 59 return;
60 60
61 epci_base = (void *)hose->cfg_addr; 61 epci_base = hose->cfg_addr;
62 62
63 val = in_be32(epci_base + SCC_EPCI_WATRP); 63 val = in_be32(epci_base + SCC_EPCI_WATRP);
64 iosync(); 64 iosync();
@@ -71,18 +71,18 @@ static inline void clear_and_disable_master_abort_interrupt(
71 struct pci_controller *hose) 71 struct pci_controller *hose)
72{ 72{
73 void __iomem *addr; 73 void __iomem *addr;
74 addr = (void *)hose->cfg_addr + PCI_COMMAND; 74 addr = hose->cfg_addr + PCI_COMMAND;
75 out_be32(addr, in_be32(addr) | (PCI_STATUS_REC_MASTER_ABORT << 16)); 75 out_be32(addr, in_be32(addr) | (PCI_STATUS_REC_MASTER_ABORT << 16));
76} 76}
77 77
78static int celleb_epci_check_abort(struct pci_controller *hose, 78static int celleb_epci_check_abort(struct pci_controller *hose,
79 unsigned long addr) 79 void __iomem *addr)
80{ 80{
81 void __iomem *reg, *epci_base; 81 void __iomem *reg, *epci_base;
82 u32 val; 82 u32 val;
83 83
84 iob(); 84 iob();
85 epci_base = (void *)hose->cfg_addr; 85 epci_base = hose->cfg_addr;
86 86
87 reg = epci_base + PCI_COMMAND; 87 reg = epci_base + PCI_COMMAND;
88 val = in_be32(reg); 88 val = in_be32(reg);
@@ -108,23 +108,23 @@ static int celleb_epci_check_abort(struct pci_controller *hose,
108 return PCIBIOS_SUCCESSFUL; 108 return PCIBIOS_SUCCESSFUL;
109} 109}
110 110
111static unsigned long celleb_epci_make_config_addr(struct pci_controller *hose, 111static void __iomem *celleb_epci_make_config_addr(struct pci_controller *hose,
112 unsigned int devfn, int where) 112 unsigned int devfn, int where)
113{ 113{
114 unsigned long addr; 114 void __iomem *addr;
115 struct pci_bus *bus = hose->bus; 115 struct pci_bus *bus = hose->bus;
116 116
117 if (bus->self) 117 if (bus->self)
118 addr = (unsigned long)hose->cfg_data + 118 addr = hose->cfg_data +
119 (((bus->number & 0xff) << 16) 119 (((bus->number & 0xff) << 16)
120 | ((devfn & 0xff) << 8) 120 | ((devfn & 0xff) << 8)
121 | (where & 0xff) 121 | (where & 0xff)
122 | 0x01000000); 122 | 0x01000000);
123 else 123 else
124 addr = (unsigned long)hose->cfg_data + 124 addr = hose->cfg_data +
125 (((devfn & 0xff) << 8) | (where & 0xff)); 125 (((devfn & 0xff) << 8) | (where & 0xff));
126 126
127 pr_debug("EPCI: config_addr = 0x%016lx\n", addr); 127 pr_debug("EPCI: config_addr = 0x%p\n", addr);
128 128
129 return addr; 129 return addr;
130} 130}
@@ -132,7 +132,7 @@ static unsigned long celleb_epci_make_config_addr(struct pci_controller *hose,
132static int celleb_epci_read_config(struct pci_bus *bus, 132static int celleb_epci_read_config(struct pci_bus *bus,
133 unsigned int devfn, int where, int size, u32 * val) 133 unsigned int devfn, int where, int size, u32 * val)
134{ 134{
135 unsigned long addr; 135 void __iomem *addr;
136 struct device_node *node; 136 struct device_node *node;
137 struct pci_controller *hose; 137 struct pci_controller *hose;
138 138
@@ -148,17 +148,17 @@ static int celleb_epci_read_config(struct pci_bus *bus,
148 if (bus->number == hose->first_busno && devfn == 0) { 148 if (bus->number == hose->first_busno && devfn == 0) {
149 /* EPCI controller self */ 149 /* EPCI controller self */
150 150
151 addr = (unsigned long)hose->cfg_addr + where; 151 addr = hose->cfg_addr + where;
152 152
153 switch (size) { 153 switch (size) {
154 case 1: 154 case 1:
155 *val = in_8((u8 *)addr); 155 *val = in_8(addr);
156 break; 156 break;
157 case 2: 157 case 2:
158 *val = in_be16((u16 *)addr); 158 *val = in_be16(addr);
159 break; 159 break;
160 case 4: 160 case 4:
161 *val = in_be32((u32 *)addr); 161 *val = in_be32(addr);
162 break; 162 break;
163 default: 163 default:
164 return PCIBIOS_DEVICE_NOT_FOUND; 164 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -171,13 +171,13 @@ static int celleb_epci_read_config(struct pci_bus *bus,
171 171
172 switch (size) { 172 switch (size) {
173 case 1: 173 case 1:
174 *val = in_8((u8 *)addr); 174 *val = in_8(addr);
175 break; 175 break;
176 case 2: 176 case 2:
177 *val = in_le16((u16 *)addr); 177 *val = in_le16(addr);
178 break; 178 break;
179 case 4: 179 case 4:
180 *val = in_le32((u32 *)addr); 180 *val = in_le32(addr);
181 break; 181 break;
182 default: 182 default:
183 return PCIBIOS_DEVICE_NOT_FOUND; 183 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -188,13 +188,13 @@ static int celleb_epci_read_config(struct pci_bus *bus,
188 "addr=0x%lx, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n", 188 "addr=0x%lx, devfn=0x%x, where=0x%x, size=0x%x, val=0x%x\n",
189 addr, devfn, where, size, *val); 189 addr, devfn, where, size, *val);
190 190
191 return celleb_epci_check_abort(hose, 0); 191 return celleb_epci_check_abort(hose, NULL);
192} 192}
193 193
194static int celleb_epci_write_config(struct pci_bus *bus, 194static int celleb_epci_write_config(struct pci_bus *bus,
195 unsigned int devfn, int where, int size, u32 val) 195 unsigned int devfn, int where, int size, u32 val)
196{ 196{
197 unsigned long addr; 197 void __iomem *addr;
198 struct device_node *node; 198 struct device_node *node;
199 struct pci_controller *hose; 199 struct pci_controller *hose;
200 200
@@ -210,17 +210,17 @@ static int celleb_epci_write_config(struct pci_bus *bus,
210 if (bus->number == hose->first_busno && devfn == 0) { 210 if (bus->number == hose->first_busno && devfn == 0) {
211 /* EPCI controller self */ 211 /* EPCI controller self */
212 212
213 addr = (unsigned long)hose->cfg_addr + where; 213 addr = hose->cfg_addr + where;
214 214
215 switch (size) { 215 switch (size) {
216 case 1: 216 case 1:
217 out_8((u8 *)addr, val); 217 out_8(addr, val);
218 break; 218 break;
219 case 2: 219 case 2:
220 out_be16((u16 *)addr, val); 220 out_be16(addr, val);
221 break; 221 break;
222 case 4: 222 case 4:
223 out_be32((u32 *)addr, val); 223 out_be32(addr, val);
224 break; 224 break;
225 default: 225 default:
226 return PCIBIOS_DEVICE_NOT_FOUND; 226 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -233,13 +233,13 @@ static int celleb_epci_write_config(struct pci_bus *bus,
233 233
234 switch (size) { 234 switch (size) {
235 case 1: 235 case 1:
236 out_8((u8 *)addr, val); 236 out_8(addr, val);
237 break; 237 break;
238 case 2: 238 case 2:
239 out_le16((u16 *)addr, val); 239 out_le16(addr, val);
240 break; 240 break;
241 case 4: 241 case 4:
242 out_le32((u32 *)addr, val); 242 out_le32(addr, val);
243 break; 243 break;
244 default: 244 default:
245 return PCIBIOS_DEVICE_NOT_FOUND; 245 return PCIBIOS_DEVICE_NOT_FOUND;
@@ -261,7 +261,7 @@ static int __devinit celleb_epci_init(struct pci_controller *hose)
261 void __iomem *reg, *epci_base; 261 void __iomem *reg, *epci_base;
262 int hwres = 0; 262 int hwres = 0;
263 263
264 epci_base = (void *)hose->cfg_addr; 264 epci_base = hose->cfg_addr;
265 265
266 /* PCI core reset(Internal bus and PCI clock) */ 266 /* PCI core reset(Internal bus and PCI clock) */
267 reg = epci_base + SCC_EPCI_CKCTRL; 267 reg = epci_base + SCC_EPCI_CKCTRL;