diff options
author | Ben Dooks <ben-linux@fluff.org> | 2008-12-11 19:24:19 -0500 |
---|---|---|
committer | Ben Dooks <ben-linux@fluff.org> | 2009-03-08 08:37:05 -0400 |
commit | ef30e14420df546bc6576b00f9caf3379b6699d1 (patch) | |
tree | 8037b6f610fee43c8b71088dd0a6d65d7d6df937 /arch | |
parent | 4e59c25dcbc1f033d043f1009a7f6aaa1f2aef26 (diff) |
[ARM] S3C: Rename sleep.S functions to be non-cpu specific
Rename s3c2410_cpu_resume to s3c_cpu_resume and s3c2410_cpu_save to
s3c_cpu_save to remove the CPU specific naming of these functions
which are now in the generic PM code.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-s3c2410/pm.c | 2 | ||||
-rw-r--r-- | arch/arm/mach-s3c2412/mach-jive.c | 2 | ||||
-rw-r--r-- | arch/arm/plat-s3c/include/plat/pm.h | 5 | ||||
-rw-r--r-- | arch/arm/plat-s3c/pm.c | 3 | ||||
-rw-r--r-- | arch/arm/plat-s3c24xx/sleep.S | 10 |
5 files changed, 12 insertions, 10 deletions
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c index 72f96869aa94..87fc481d92d4 100644 --- a/arch/arm/mach-s3c2410/pm.c +++ b/arch/arm/mach-s3c2410/pm.c | |||
@@ -41,7 +41,7 @@ static void s3c2410_pm_prepare(void) | |||
41 | { | 41 | { |
42 | /* ensure at least GSTATUS3 has the resume address */ | 42 | /* ensure at least GSTATUS3 has the resume address */ |
43 | 43 | ||
44 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2410_GSTATUS3); | 44 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2410_GSTATUS3); |
45 | 45 | ||
46 | S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); | 46 | S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3)); |
47 | S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); | 47 | S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4)); |
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c index 50d8054292c2..72c266aee141 100644 --- a/arch/arm/mach-s3c2412/mach-jive.c +++ b/arch/arm/mach-s3c2412/mach-jive.c | |||
@@ -494,7 +494,7 @@ static int jive_pm_suspend(struct sys_device *sd, pm_message_t state) | |||
494 | * correct address to resume from. */ | 494 | * correct address to resume from. */ |
495 | 495 | ||
496 | __raw_writel(0x2BED, S3C2412_INFORM0); | 496 | __raw_writel(0x2BED, S3C2412_INFORM0); |
497 | __raw_writel(virt_to_phys(s3c2410_cpu_resume), S3C2412_INFORM1); | 497 | __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1); |
498 | 498 | ||
499 | return 0; | 499 | return 0; |
500 | } | 500 | } |
diff --git a/arch/arm/plat-s3c/include/plat/pm.h b/arch/arm/plat-s3c/include/plat/pm.h index a6104c8055ff..f121a5ac7420 100644 --- a/arch/arm/plat-s3c/include/plat/pm.h +++ b/arch/arm/plat-s3c/include/plat/pm.h | |||
@@ -46,9 +46,10 @@ extern unsigned long s3c_pm_flags; | |||
46 | 46 | ||
47 | /* from sleep.S */ | 47 | /* from sleep.S */ |
48 | 48 | ||
49 | extern int s3c2410_cpu_save(unsigned long *saveblk); | 49 | extern int s3c_cpu_save(unsigned long *saveblk); |
50 | extern void s3c_cpu_resume(void); | ||
51 | |||
50 | extern void s3c2410_cpu_suspend(void); | 52 | extern void s3c2410_cpu_suspend(void); |
51 | extern void s3c2410_cpu_resume(void); | ||
52 | 53 | ||
53 | extern unsigned long s3c_sleep_save_phys; | 54 | extern unsigned long s3c_sleep_save_phys; |
54 | 55 | ||
diff --git a/arch/arm/plat-s3c/pm.c b/arch/arm/plat-s3c/pm.c index e82ec628ced1..e320b0ff3852 100644 --- a/arch/arm/plat-s3c/pm.c +++ b/arch/arm/plat-s3c/pm.c | |||
@@ -280,8 +280,9 @@ static int s3c_pm_enter(suspend_state_t state) | |||
280 | * we resume as it saves its own register state, so use the return | 280 | * we resume as it saves its own register state, so use the return |
281 | * code to differentiate return from save and return from sleep */ | 281 | * code to differentiate return from save and return from sleep */ |
282 | 282 | ||
283 | if (s3c2410_cpu_save(regs_save) == 0) { | 283 | if (s3c_cpu_save(regs_save) == 0) { |
284 | flush_cache_all(); | 284 | flush_cache_all(); |
285 | S3C_PMDBG("preparing to sleep\n"); | ||
285 | pm_cpu_sleep(); | 286 | pm_cpu_sleep(); |
286 | } | 287 | } |
287 | 288 | ||
diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S index 7c1955ff3171..ecb830be67d6 100644 --- a/arch/arm/plat-s3c24xx/sleep.S +++ b/arch/arm/plat-s3c24xx/sleep.S | |||
@@ -41,7 +41,7 @@ | |||
41 | 41 | ||
42 | .text | 42 | .text |
43 | 43 | ||
44 | /* s3c2410_cpu_save | 44 | /* s3c_cpu_save |
45 | * | 45 | * |
46 | * save enough of the CPU state to allow us to re-start | 46 | * save enough of the CPU state to allow us to re-start |
47 | * pm.c code. as we store items like the sp/lr, we will | 47 | * pm.c code. as we store items like the sp/lr, we will |
@@ -59,7 +59,7 @@ | |||
59 | * 1 => resumed from sleep | 59 | * 1 => resumed from sleep |
60 | */ | 60 | */ |
61 | 61 | ||
62 | ENTRY(s3c2410_cpu_save) | 62 | ENTRY(s3c_cpu_save) |
63 | stmfd sp!, { r4 - r12, lr } | 63 | stmfd sp!, { r4 - r12, lr } |
64 | 64 | ||
65 | @@ store co-processor registers | 65 | @@ store co-processor registers |
@@ -99,12 +99,12 @@ s3c_sleep_save_phys: | |||
99 | 99 | ||
100 | /* sleep magic, to allow the bootloader to check for an valid | 100 | /* sleep magic, to allow the bootloader to check for an valid |
101 | * image to resume to. Must be the first word before the | 101 | * image to resume to. Must be the first word before the |
102 | * s3c2410_cpu_resume entry. | 102 | * s3c_cpu_resume entry. |
103 | */ | 103 | */ |
104 | 104 | ||
105 | .word 0x2bedf00d | 105 | .word 0x2bedf00d |
106 | 106 | ||
107 | /* s3c2410_cpu_resume | 107 | /* s3c_cpu_resume |
108 | * | 108 | * |
109 | * resume code entry for bootloader to call | 109 | * resume code entry for bootloader to call |
110 | * | 110 | * |
@@ -113,7 +113,7 @@ s3c_sleep_save_phys: | |||
113 | * must not write to the code segment (code is read-only) | 113 | * must not write to the code segment (code is read-only) |
114 | */ | 114 | */ |
115 | 115 | ||
116 | ENTRY(s3c2410_cpu_resume) | 116 | ENTRY(s3c_cpu_resume) |
117 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE | 117 | mov r0, #PSR_I_BIT | PSR_F_BIT | SVC_MODE |
118 | msr cpsr_c, r0 | 118 | msr cpsr_c, r0 |
119 | 119 | ||