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authorRalf Baechle <ralf@linux-mips.org>2007-10-30 11:43:44 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-11-26 12:26:13 -0500
commit98ce472181e760a552314850c238b14bbf3f04ec (patch)
treee2868580151a44e5853f1383b728984a6984ccf0 /arch
parent526a6770692477ff258621b1b8838cce9304f8e4 (diff)
[MIPS] IP32: More interrupt renumbering fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c24
1 files changed, 14 insertions, 10 deletions
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index aab17ddd2f30..cab7cc22ab67 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -209,18 +209,18 @@ static unsigned long macepci_mask;
209 209
210static void enable_macepci_irq(unsigned int irq) 210static void enable_macepci_irq(unsigned int irq)
211{ 211{
212 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); 212 macepci_mask |= MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
213 mace->pci.control = macepci_mask; 213 mace->pci.control = macepci_mask;
214 crime_mask |= 1 << (irq - 1); 214 crime_mask |= 1 << (irq - CRIME_IRQ_BASE);
215 crime->imask = crime_mask; 215 crime->imask = crime_mask;
216} 216}
217 217
218static void disable_macepci_irq(unsigned int irq) 218static void disable_macepci_irq(unsigned int irq)
219{ 219{
220 crime_mask &= ~(1 << (irq - 1)); 220 crime_mask &= ~(1 << (irq - CRIME_IRQ_BASE));
221 crime->imask = crime_mask; 221 crime->imask = crime_mask;
222 flush_crime_bus(); 222 flush_crime_bus();
223 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); 223 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - MACEPCI_SCSI0_IRQ);
224 mace->pci.control = macepci_mask; 224 mace->pci.control = macepci_mask;
225 flush_mace_bus(); 225 flush_mace_bus();
226} 226}
@@ -299,7 +299,7 @@ static void enable_maceisa_irq(unsigned int irq)
299 pr_debug("crime_int %08x enabled\n", crime_int); 299 pr_debug("crime_int %08x enabled\n", crime_int);
300 crime_mask |= crime_int; 300 crime_mask |= crime_int;
301 crime->imask = crime_mask; 301 crime->imask = crime_mask;
302 maceisa_mask |= 1 << (irq - 33); 302 maceisa_mask |= 1 << (irq - MACEISA_AUDIO_SW_IRQ);
303 mace->perif.ctrl.imask = maceisa_mask; 303 mace->perif.ctrl.imask = maceisa_mask;
304} 304}
305 305
@@ -307,7 +307,7 @@ static void disable_maceisa_irq(unsigned int irq)
307{ 307{
308 unsigned int crime_int = 0; 308 unsigned int crime_int = 0;
309 309
310 maceisa_mask &= ~(1 << (irq - 33)); 310 maceisa_mask &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
311 if (!(maceisa_mask & MACEISA_AUDIO_INT)) 311 if (!(maceisa_mask & MACEISA_AUDIO_INT))
312 crime_int |= MACE_AUDIO_INT; 312 crime_int |= MACE_AUDIO_INT;
313 if (!(maceisa_mask & MACEISA_MISC_INT)) 313 if (!(maceisa_mask & MACEISA_MISC_INT))
@@ -331,7 +331,7 @@ static void mask_and_ack_maceisa_irq(unsigned int irq)
331 case MACEISA_SERIAL2_TDMAPR_IRQ: 331 case MACEISA_SERIAL2_TDMAPR_IRQ:
332 /* edge triggered */ 332 /* edge triggered */
333 mace_int = mace->perif.ctrl.istat; 333 mace_int = mace->perif.ctrl.istat;
334 mace_int &= ~(1 << (irq - 33)); 334 mace_int &= ~(1 << (irq - MACEISA_AUDIO_SW_IRQ));
335 mace->perif.ctrl.istat = mace_int; 335 mace->perif.ctrl.istat = mace_int;
336 break; 336 break;
337 } 337 }
@@ -359,13 +359,17 @@ static struct irq_chip ip32_maceisa_interrupt = {
359 359
360static void enable_mace_irq(unsigned int irq) 360static void enable_mace_irq(unsigned int irq)
361{ 361{
362 crime_mask |= 1 << (irq - 1); 362 unsigned int bit = irq - CRIME_IRQ_BASE;
363
364 crime_mask |= (1 << bit);
363 crime->imask = crime_mask; 365 crime->imask = crime_mask;
364} 366}
365 367
366static void disable_mace_irq(unsigned int irq) 368static void disable_mace_irq(unsigned int irq)
367{ 369{
368 crime_mask &= ~(1 << (irq - 1)); 370 unsigned int bit = irq - CRIME_IRQ_BASE;
371
372 crime_mask &= ~(1 << bit);
369 crime->imask = crime_mask; 373 crime->imask = crime_mask;
370 flush_crime_bus(); 374 flush_crime_bus();
371} 375}
@@ -489,7 +493,7 @@ void __init arch_init_irq(void)
489 mace->perif.ctrl.imask = 0; 493 mace->perif.ctrl.imask = 0;
490 494
491 mips_cpu_irq_init(); 495 mips_cpu_irq_init();
492 for (irq = MIPS_CPU_IRQ_BASE + 8; irq <= IP32_IRQ_MAX; irq++) { 496 for (irq = CRIME_IRQ_BASE; irq <= IP32_IRQ_MAX; irq++) {
493 switch (irq) { 497 switch (irq) {
494 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ: 498 case MACE_VID_IN1_IRQ ... MACE_PCI_BRIDGE_IRQ:
495 set_irq_chip(irq, &ip32_mace_interrupt); 499 set_irq_chip(irq, &ip32_mace_interrupt);