diff options
| author | Kumar Gala <galak@freescale.com> | 2005-06-26 10:14:01 -0400 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-06-26 11:43:19 -0400 |
| commit | 7d681b23d6cc14a8c026ea6756242cb522cbbcae (patch) | |
| tree | 18b731dbb25c014133cbb25842e9fd00ae9ed4ec /arch | |
| parent | 340ea3972ffc6c9f90b3ac38b70eade1c8efbf5b (diff) | |
[PATCH] ppc32: Fix MPC83xx IPIC external interrupt pending register offset
The pending registers for IRQ1-IRQ7 were pointing to the interrupt pending
register instead of the external one.
Signed-off-by: Tony Li <Tony.Li@freescale.com>
Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/ppc/syslib/ipic.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/ppc/syslib/ipic.c b/arch/ppc/syslib/ipic.c index 580ed658e872..8f01e0f1d847 100644 --- a/arch/ppc/syslib/ipic.c +++ b/arch/ppc/syslib/ipic.c | |||
| @@ -79,7 +79,7 @@ static struct ipic_info ipic_info[] = { | |||
| 79 | .prio_mask = 7, | 79 | .prio_mask = 7, |
| 80 | }, | 80 | }, |
| 81 | [17] = { | 81 | [17] = { |
| 82 | .pend = IPIC_SIPNR_H, | 82 | .pend = IPIC_SEPNR, |
| 83 | .mask = IPIC_SEMSR, | 83 | .mask = IPIC_SEMSR, |
| 84 | .prio = IPIC_SMPRR_A, | 84 | .prio = IPIC_SMPRR_A, |
| 85 | .force = IPIC_SEFCR, | 85 | .force = IPIC_SEFCR, |
| @@ -87,7 +87,7 @@ static struct ipic_info ipic_info[] = { | |||
| 87 | .prio_mask = 5, | 87 | .prio_mask = 5, |
| 88 | }, | 88 | }, |
| 89 | [18] = { | 89 | [18] = { |
| 90 | .pend = IPIC_SIPNR_H, | 90 | .pend = IPIC_SEPNR, |
| 91 | .mask = IPIC_SEMSR, | 91 | .mask = IPIC_SEMSR, |
| 92 | .prio = IPIC_SMPRR_A, | 92 | .prio = IPIC_SMPRR_A, |
| 93 | .force = IPIC_SEFCR, | 93 | .force = IPIC_SEFCR, |
| @@ -95,7 +95,7 @@ static struct ipic_info ipic_info[] = { | |||
| 95 | .prio_mask = 6, | 95 | .prio_mask = 6, |
| 96 | }, | 96 | }, |
| 97 | [19] = { | 97 | [19] = { |
| 98 | .pend = IPIC_SIPNR_H, | 98 | .pend = IPIC_SEPNR, |
| 99 | .mask = IPIC_SEMSR, | 99 | .mask = IPIC_SEMSR, |
| 100 | .prio = IPIC_SMPRR_A, | 100 | .prio = IPIC_SMPRR_A, |
| 101 | .force = IPIC_SEFCR, | 101 | .force = IPIC_SEFCR, |
| @@ -103,7 +103,7 @@ static struct ipic_info ipic_info[] = { | |||
| 103 | .prio_mask = 7, | 103 | .prio_mask = 7, |
| 104 | }, | 104 | }, |
| 105 | [20] = { | 105 | [20] = { |
| 106 | .pend = IPIC_SIPNR_H, | 106 | .pend = IPIC_SEPNR, |
| 107 | .mask = IPIC_SEMSR, | 107 | .mask = IPIC_SEMSR, |
| 108 | .prio = IPIC_SMPRR_B, | 108 | .prio = IPIC_SMPRR_B, |
| 109 | .force = IPIC_SEFCR, | 109 | .force = IPIC_SEFCR, |
| @@ -111,7 +111,7 @@ static struct ipic_info ipic_info[] = { | |||
| 111 | .prio_mask = 4, | 111 | .prio_mask = 4, |
| 112 | }, | 112 | }, |
| 113 | [21] = { | 113 | [21] = { |
| 114 | .pend = IPIC_SIPNR_H, | 114 | .pend = IPIC_SEPNR, |
| 115 | .mask = IPIC_SEMSR, | 115 | .mask = IPIC_SEMSR, |
| 116 | .prio = IPIC_SMPRR_B, | 116 | .prio = IPIC_SMPRR_B, |
| 117 | .force = IPIC_SEFCR, | 117 | .force = IPIC_SEFCR, |
| @@ -119,7 +119,7 @@ static struct ipic_info ipic_info[] = { | |||
| 119 | .prio_mask = 5, | 119 | .prio_mask = 5, |
| 120 | }, | 120 | }, |
| 121 | [22] = { | 121 | [22] = { |
| 122 | .pend = IPIC_SIPNR_H, | 122 | .pend = IPIC_SEPNR, |
| 123 | .mask = IPIC_SEMSR, | 123 | .mask = IPIC_SEMSR, |
| 124 | .prio = IPIC_SMPRR_B, | 124 | .prio = IPIC_SMPRR_B, |
| 125 | .force = IPIC_SEFCR, | 125 | .force = IPIC_SEFCR, |
| @@ -127,7 +127,7 @@ static struct ipic_info ipic_info[] = { | |||
| 127 | .prio_mask = 6, | 127 | .prio_mask = 6, |
| 128 | }, | 128 | }, |
| 129 | [23] = { | 129 | [23] = { |
| 130 | .pend = IPIC_SIPNR_H, | 130 | .pend = IPIC_SEPNR, |
| 131 | .mask = IPIC_SEMSR, | 131 | .mask = IPIC_SEMSR, |
| 132 | .prio = IPIC_SMPRR_B, | 132 | .prio = IPIC_SMPRR_B, |
| 133 | .force = IPIC_SEFCR, | 133 | .force = IPIC_SEFCR, |