diff options
author | Paul Mundt <lethal@linux-sh.org> | 2006-09-27 01:55:41 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2006-09-27 01:55:41 -0400 |
commit | 749cf486920bf53f16e6a6889d9635a91ffb6c82 (patch) | |
tree | ff288990effd0fe5bf980d6c27af5dc9ad11bc3d /arch | |
parent | 94c0fa520cc169ccf661e9c03b5b95f74d1520b8 (diff) |
sh: Add flag for MMU PTEA capability.
Add CPU_HAS_PTEA, refactor some of the cpu flag settings.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/sh/kernel/cpu/sh4/probe.c | 34 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4/sq.c | 6 | ||||
-rw-r--r-- | arch/sh/mm/tlb-sh4.c | 12 |
3 files changed, 31 insertions, 21 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c index 85ff48c1533a..2a7707a81d8f 100644 --- a/arch/sh/kernel/cpu/sh4/probe.c +++ b/arch/sh/kernel/cpu/sh4/probe.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * CPU Subtype Probing for SH-4. | 4 | * CPU Subtype Probing for SH-4. |
5 | * | 5 | * |
6 | * Copyright (C) 2001, 2002, 2003, 2004 Paul Mundt | 6 | * Copyright (C) 2001 - 2005 Paul Mundt |
7 | * Copyright (C) 2003 Richard Curnow | 7 | * Copyright (C) 2003 Richard Curnow |
8 | * | 8 | * |
9 | * This file is subject to the terms and conditions of the GNU General Public | 9 | * This file is subject to the terms and conditions of the GNU General Public |
@@ -53,9 +53,6 @@ int __init detect_cpu_and_cache_system(void) | |||
53 | cpu_data->dcache.ways = 1; | 53 | cpu_data->dcache.ways = 1; |
54 | cpu_data->dcache.linesz = L1_CACHE_BYTES; | 54 | cpu_data->dcache.linesz = L1_CACHE_BYTES; |
55 | 55 | ||
56 | /* Set the FPU flag, virtually all SH-4's have one */ | ||
57 | cpu_data->flags |= CPU_HAS_FPU; | ||
58 | |||
59 | /* | 56 | /* |
60 | * Probe the underlying processor version/revision and | 57 | * Probe the underlying processor version/revision and |
61 | * adjust cpu_data setup accordingly. | 58 | * adjust cpu_data setup accordingly. |
@@ -63,26 +60,37 @@ int __init detect_cpu_and_cache_system(void) | |||
63 | switch (pvr) { | 60 | switch (pvr) { |
64 | case 0x205: | 61 | case 0x205: |
65 | cpu_data->type = CPU_SH7750; | 62 | cpu_data->type = CPU_SH7750; |
66 | cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER; | 63 | cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | |
64 | CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA; | ||
67 | break; | 65 | break; |
68 | case 0x206: | 66 | case 0x206: |
69 | cpu_data->type = CPU_SH7750S; | 67 | cpu_data->type = CPU_SH7750S; |
70 | cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_PERF_COUNTER; | 68 | cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG | CPU_HAS_FPU | |
69 | CPU_HAS_PERF_COUNTER | CPU_HAS_PTEA; | ||
71 | break; | 70 | break; |
72 | case 0x1100: | 71 | case 0x1100: |
73 | cpu_data->type = CPU_SH7751; | 72 | cpu_data->type = CPU_SH7751; |
73 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA; | ||
74 | break; | 74 | break; |
75 | case 0x2000: | 75 | case 0x2000: |
76 | cpu_data->type = CPU_SH73180; | 76 | cpu_data->type = CPU_SH73180; |
77 | cpu_data->icache.ways = 4; | 77 | cpu_data->icache.ways = 4; |
78 | cpu_data->dcache.ways = 4; | 78 | cpu_data->dcache.ways = 4; |
79 | cpu_data->flags &= ~CPU_HAS_FPU; | 79 | |
80 | /* | ||
81 | * XXX: Double check this, none of the SH-4A/SH-4AL processors | ||
82 | * should have this, as it's essentially a legacy thing. | ||
83 | */ | ||
84 | cpu_data->flags |= CPU_HAS_PTEA; | ||
80 | break; | 85 | break; |
81 | case 0x2001: | 86 | case 0x2001: |
82 | case 0x2004: | 87 | case 0x2004: |
83 | cpu_data->type = CPU_SH7770; | 88 | cpu_data->type = CPU_SH7770; |
84 | cpu_data->icache.ways = 4; | 89 | cpu_data->icache.ways = 4; |
85 | cpu_data->dcache.ways = 4; | 90 | cpu_data->dcache.ways = 4; |
91 | |||
92 | /* Same note as above applies here for PTEA */ | ||
93 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA; | ||
86 | break; | 94 | break; |
87 | case 0x2006: | 95 | case 0x2006: |
88 | case 0x200A: | 96 | case 0x200A: |
@@ -90,27 +98,31 @@ int __init detect_cpu_and_cache_system(void) | |||
90 | cpu_data->type = CPU_SH7781; | 98 | cpu_data->type = CPU_SH7781; |
91 | else | 99 | else |
92 | cpu_data->type = CPU_SH7780; | 100 | cpu_data->type = CPU_SH7780; |
101 | |||
93 | cpu_data->icache.ways = 4; | 102 | cpu_data->icache.ways = 4; |
94 | cpu_data->dcache.ways = 4; | 103 | cpu_data->dcache.ways = 4; |
104 | |||
105 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER; | ||
95 | break; | 106 | break; |
96 | case 0x8000: | 107 | case 0x8000: |
97 | cpu_data->type = CPU_ST40RA; | 108 | cpu_data->type = CPU_ST40RA; |
109 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA; | ||
98 | break; | 110 | break; |
99 | case 0x8100: | 111 | case 0x8100: |
100 | cpu_data->type = CPU_ST40GX1; | 112 | cpu_data->type = CPU_ST40GX1; |
113 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA; | ||
101 | break; | 114 | break; |
102 | case 0x700: | 115 | case 0x700: |
103 | cpu_data->type = CPU_SH4_501; | 116 | cpu_data->type = CPU_SH4_501; |
104 | cpu_data->icache.ways = 2; | 117 | cpu_data->icache.ways = 2; |
105 | cpu_data->dcache.ways = 2; | 118 | cpu_data->dcache.ways = 2; |
106 | 119 | cpu_data->flags |= CPU_HAS_PTEA; | |
107 | /* No FPU on the SH4-500 series.. */ | ||
108 | cpu_data->flags &= ~CPU_HAS_FPU; | ||
109 | break; | 120 | break; |
110 | case 0x600: | 121 | case 0x600: |
111 | cpu_data->type = CPU_SH4_202; | 122 | cpu_data->type = CPU_SH4_202; |
112 | cpu_data->icache.ways = 2; | 123 | cpu_data->icache.ways = 2; |
113 | cpu_data->dcache.ways = 2; | 124 | cpu_data->dcache.ways = 2; |
125 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA; | ||
114 | break; | 126 | break; |
115 | case 0x500 ... 0x501: | 127 | case 0x500 ... 0x501: |
116 | switch (prr) { | 128 | switch (prr) { |
@@ -128,6 +140,8 @@ int __init detect_cpu_and_cache_system(void) | |||
128 | cpu_data->icache.ways = 2; | 140 | cpu_data->icache.ways = 2; |
129 | cpu_data->dcache.ways = 2; | 141 | cpu_data->dcache.ways = 2; |
130 | 142 | ||
143 | cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA; | ||
144 | |||
131 | break; | 145 | break; |
132 | default: | 146 | default: |
133 | cpu_data->type = CPU_SH_NONE; | 147 | cpu_data->type = CPU_SH_NONE; |
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c index 32c93b781b51..b148966dd7c7 100644 --- a/arch/sh/kernel/cpu/sh4/sq.c +++ b/arch/sh/kernel/cpu/sh4/sq.c | |||
@@ -166,9 +166,9 @@ static struct sq_mapping *__sq_remap(struct sq_mapping *map) | |||
166 | ctrl_outl((pteh & MMU_VPN_MASK) | get_asid(), MMU_PTEH); | 166 | ctrl_outl((pteh & MMU_VPN_MASK) | get_asid(), MMU_PTEH); |
167 | 167 | ||
168 | ptel = map->addr & PAGE_MASK; | 168 | ptel = map->addr & PAGE_MASK; |
169 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 | 169 | |
170 | ctrl_outl(((ptel >> 28) & 0xe) | (ptel & 0x1), MMU_PTEA); | 170 | if (cpu_data->flags & CPU_HAS_PTEA) |
171 | #endif | 171 | ctrl_outl(((ptel >> 28) & 0xe) | (ptel & 0x1), MMU_PTEA); |
172 | 172 | ||
173 | pgprot = pgprot_noncached(PAGE_KERNEL); | 173 | pgprot = pgprot_noncached(PAGE_KERNEL); |
174 | 174 | ||
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c index 96e5fb0ac4fa..812b2d567de2 100644 --- a/arch/sh/mm/tlb-sh4.c +++ b/arch/sh/mm/tlb-sh4.c | |||
@@ -36,9 +36,6 @@ void update_mmu_cache(struct vm_area_struct * vma, | |||
36 | unsigned long vpn; | 36 | unsigned long vpn; |
37 | struct page *page; | 37 | struct page *page; |
38 | unsigned long pfn; | 38 | unsigned long pfn; |
39 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 | ||
40 | unsigned long ptea; | ||
41 | #endif | ||
42 | 39 | ||
43 | /* Ptrace may call this routine. */ | 40 | /* Ptrace may call this routine. */ |
44 | if (vma && current->active_mm != vma->vm_mm) | 41 | if (vma && current->active_mm != vma->vm_mm) |
@@ -61,12 +58,11 @@ void update_mmu_cache(struct vm_area_struct * vma, | |||
61 | ctrl_outl(vpn, MMU_PTEH); | 58 | ctrl_outl(vpn, MMU_PTEH); |
62 | 59 | ||
63 | pteval = pte_val(pte); | 60 | pteval = pte_val(pte); |
64 | #ifndef CONFIG_CPU_SUBTYPE_SH7780 | 61 | |
65 | /* Set PTEA register */ | 62 | /* Set PTEA register */ |
66 | /* TODO: make this look less hacky */ | 63 | if (cpu_data->flags & CPU_HAS_PTEA) |
67 | ptea = ((pteval >> 28) & 0xe) | (pteval & 0x1); | 64 | /* TODO: make this look less hacky */ |
68 | ctrl_outl(ptea, MMU_PTEA); | 65 | ctrl_outl(((pteval >> 28) & 0xe) | (pteval & 0x1), MMU_PTEA); |
69 | #endif | ||
70 | 66 | ||
71 | /* Set PTEL register */ | 67 | /* Set PTEL register */ |
72 | pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ | 68 | pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ |