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authorMagnus Damm <damm@igel.co.jp>2007-08-12 02:26:12 -0400
committerPaul Mundt <lethal@linux-sh.org>2007-09-20 22:57:50 -0400
commit73505b445dbb8ad12df468404c4dd5cde9c40c65 (patch)
treec248710475090f01dc874e2c878efc769b24d2af /arch
parent6ef5fb2cfcedaab4a43493c8f2305a67c0ce1af6 (diff)
sh: intc - rework core code
This patch reworks the intc core, implementing the following features: - Support dual priority registers - one set and one clear register - All 8/16/32 bit register combinations are now supported - Both single mask and single enable bitmap register are supported - Add code to set interrupt priority - Speedup sense and priority configuration code - Allocate data using bootmem, allows intc data structures to be __initdata - Save memory - allocated memory footprint is smaller than intc structures Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch')
-rw-r--r--arch/sh/cchips/voyagergx/irq.c2
-rw-r--r--arch/sh/kernel/cpu/irq/intc.c538
2 files changed, 328 insertions, 212 deletions
diff --git a/arch/sh/cchips/voyagergx/irq.c b/arch/sh/cchips/voyagergx/irq.c
index 0ca405a46a5b..2d3620cc92be 100644
--- a/arch/sh/cchips/voyagergx/irq.c
+++ b/arch/sh/cchips/voyagergx/irq.c
@@ -50,7 +50,7 @@ static struct intc_vect vectors[] = {
50}; 50};
51 51
52static struct intc_mask_reg mask_registers[] = { 52static struct intc_mask_reg mask_registers[] = {
53 { VOYAGER_INT_MASK, 1, 32, /* "Interrupt Mask", MMIO_base + 0x30 */ 53 { VOYAGER_INT_MASK, 0, 32, /* "Interrupt Mask", MMIO_base + 0x30 */
54 { UP, G54, G53, G52, G51, G50, G49, G48, 54 { UP, G54, G53, G52, G51, G50, G49, G48,
55 I2C, PW, 0, DMA, PCI, I2S, AC, US, 55 I2C, PW, 0, DMA, PCI, I2S, AC, US,
56 0, 0, U1, U0, CV, MC, S1, S0, 56 0, 0, U1, U0, CV, MC, S1, S0,
diff --git a/arch/sh/kernel/cpu/irq/intc.c b/arch/sh/kernel/cpu/irq/intc.c
index 24a8d554799e..d609a8ccd456 100644
--- a/arch/sh/kernel/cpu/irq/intc.c
+++ b/arch/sh/kernel/cpu/irq/intc.c
@@ -20,176 +20,227 @@
20#include <linux/module.h> 20#include <linux/module.h>
21#include <linux/io.h> 21#include <linux/io.h>
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/bootmem.h>
24
25#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
26 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
27 ((addr_e) << 16) | ((addr_d << 24)))
28
29#define _INTC_SHIFT(h) (h & 0x1f)
30#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
31#define _INTC_FN(h) ((h >> 9) & 0xf)
32#define _INTC_MODE(h) ((h >> 13) & 0x7)
33#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
34#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
35
36struct intc_handle_int {
37 unsigned int irq;
38 unsigned long handle;
39};
23 40
24#define _INTC_MK(fn, idx, bit, value) \ 41struct intc_desc_int {
25 ((fn) << 24 | ((value) << 16) | ((idx) << 8) | (bit)) 42 unsigned long *reg;
26#define _INTC_FN(h) (h >> 24) 43 unsigned int nr_reg;
27#define _INTC_VALUE(h) ((h >> 16) & 0xff) 44 struct intc_handle_int *prio;
28#define _INTC_IDX(h) ((h >> 8) & 0xff) 45 unsigned int nr_prio;
29#define _INTC_BIT(h) (h & 0xff) 46 struct intc_handle_int *sense;
47 unsigned int nr_sense;
48 struct irq_chip chip;
49};
30 50
31#define _INTC_PTR(desc, member, data) \ 51static unsigned int intc_prio_level[NR_IRQS]; /* for now */
32 (desc->member + _INTC_IDX(data))
33 52
34static inline struct intc_desc *get_intc_desc(unsigned int irq) 53static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
35{ 54{
36 struct irq_chip *chip = get_irq_chip(irq); 55 struct irq_chip *chip = get_irq_chip(irq);
37 return (void *)((char *)chip - offsetof(struct intc_desc, chip)); 56 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
38} 57}
39 58
40static inline unsigned int set_field(unsigned int value, 59static inline unsigned int set_field(unsigned int value,
41 unsigned int field_value, 60 unsigned int field_value,
42 unsigned int width, 61 unsigned int handle)
43 unsigned int shift)
44{ 62{
63 unsigned int width = _INTC_WIDTH(handle);
64 unsigned int shift = _INTC_SHIFT(handle);
65
45 value &= ~(((1 << width) - 1) << shift); 66 value &= ~(((1 << width) - 1) << shift);
46 value |= field_value << shift; 67 value |= field_value << shift;
47 return value; 68 return value;
48} 69}
49 70
50static inline unsigned int set_prio_field(struct intc_desc *desc, 71static void write_8(unsigned long addr, unsigned long h, unsigned long data)
51 unsigned int value,
52 unsigned int priority,
53 unsigned int data)
54{ 72{
55 unsigned int width = _INTC_PTR(desc, prio_regs, data)->field_width; 73 ctrl_outb(set_field(0, data, h), addr);
56
57 return set_field(value, priority, width, _INTC_BIT(data));
58} 74}
59 75
60static void disable_prio_16(struct intc_desc *desc, unsigned int data) 76static void write_16(unsigned long addr, unsigned long h, unsigned long data)
61{ 77{
62 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg; 78 ctrl_outw(set_field(0, data, h), addr);
63
64 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), 0, data), addr);
65} 79}
66 80
67static void enable_prio_16(struct intc_desc *desc, unsigned int data) 81static void write_32(unsigned long addr, unsigned long h, unsigned long data)
68{ 82{
69 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg; 83 ctrl_outl(set_field(0, data, h), addr);
70 unsigned int prio = _INTC_VALUE(data);
71
72 ctrl_outw(set_prio_field(desc, ctrl_inw(addr), prio, data), addr);
73} 84}
74 85
75static void disable_prio_32(struct intc_desc *desc, unsigned int data) 86static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
76{ 87{
77 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg; 88 ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
78
79 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), 0, data), addr);
80} 89}
81 90
82static void enable_prio_32(struct intc_desc *desc, unsigned int data) 91static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
83{ 92{
84 unsigned long addr = _INTC_PTR(desc, prio_regs, data)->set_reg; 93 ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
85 unsigned int prio = _INTC_VALUE(data);
86
87 ctrl_outl(set_prio_field(desc, ctrl_inl(addr), prio, data), addr);
88} 94}
89 95
90static void write_set_reg_8(struct intc_desc *desc, unsigned int data) 96static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
91{ 97{
92 ctrl_outb(1 << _INTC_BIT(data), 98 ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
93 _INTC_PTR(desc, mask_regs, data)->set_reg);
94} 99}
95 100
96static void write_clr_reg_8(struct intc_desc *desc, unsigned int data) 101enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
97{ 102
98 ctrl_outb(1 << _INTC_BIT(data), 103static void (*intc_reg_fns[])(unsigned long addr,
99 _INTC_PTR(desc, mask_regs, data)->clr_reg); 104 unsigned long h,
100} 105 unsigned long data) = {
106 [REG_FN_WRITE_BASE + 0] = write_8,
107 [REG_FN_WRITE_BASE + 1] = write_16,
108 [REG_FN_WRITE_BASE + 3] = write_32,
109 [REG_FN_MODIFY_BASE + 0] = modify_8,
110 [REG_FN_MODIFY_BASE + 1] = modify_16,
111 [REG_FN_MODIFY_BASE + 3] = modify_32,
112};
101 113
102static void write_set_reg_32(struct intc_desc *desc, unsigned int data) 114enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
103{ 115 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
104 ctrl_outl(1 << _INTC_BIT(data), 116 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
105 _INTC_PTR(desc, mask_regs, data)->set_reg); 117 MODE_PRIO_REG, /* Priority value written to enable interrupt */
106} 118 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
119};
107 120
108static void write_clr_reg_32(struct intc_desc *desc, unsigned int data) 121static void intc_mode_field(unsigned long addr,
122 unsigned long handle,
123 void (*fn)(unsigned long,
124 unsigned long,
125 unsigned long),
126 unsigned int irq)
109{ 127{
110 ctrl_outl(1 << _INTC_BIT(data), 128 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
111 _INTC_PTR(desc, mask_regs, data)->clr_reg);
112} 129}
113 130
114static void or_set_reg_16(struct intc_desc *desc, unsigned int data) 131static void intc_mode_zero(unsigned long addr,
132 unsigned long handle,
133 void (*fn)(unsigned long,
134 unsigned long,
135 unsigned long),
136 unsigned int irq)
115{ 137{
116 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg; 138 fn(addr, handle, 0);
117
118 ctrl_outw(ctrl_inw(addr) | 1 << _INTC_BIT(data), addr);
119} 139}
120 140
121static void and_set_reg_16(struct intc_desc *desc, unsigned int data) 141static void intc_mode_prio(unsigned long addr,
142 unsigned long handle,
143 void (*fn)(unsigned long,
144 unsigned long,
145 unsigned long),
146 unsigned int irq)
122{ 147{
123 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg; 148 fn(addr, handle, intc_prio_level[irq]);
124
125 ctrl_outw(ctrl_inw(addr) & ~(1 << _INTC_BIT(data)), addr);
126} 149}
127 150
128static void or_set_reg_32(struct intc_desc *desc, unsigned int data) 151static void (*intc_enable_fns[])(unsigned long addr,
129{ 152 unsigned long handle,
130 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg; 153 void (*fn)(unsigned long,
154 unsigned long,
155 unsigned long),
156 unsigned int irq) = {
157 [MODE_ENABLE_REG] = intc_mode_field,
158 [MODE_MASK_REG] = intc_mode_zero,
159 [MODE_DUAL_REG] = intc_mode_field,
160 [MODE_PRIO_REG] = intc_mode_prio,
161 [MODE_PCLR_REG] = intc_mode_prio,
162};
131 163
132 ctrl_outl(ctrl_inl(addr) | 1 << _INTC_BIT(data), addr); 164static void (*intc_disable_fns[])(unsigned long addr,
133} 165 unsigned long handle,
166 void (*fn)(unsigned long,
167 unsigned long,
168 unsigned long),
169 unsigned int irq) = {
170 [MODE_ENABLE_REG] = intc_mode_zero,
171 [MODE_MASK_REG] = intc_mode_field,
172 [MODE_DUAL_REG] = intc_mode_field,
173 [MODE_PRIO_REG] = intc_mode_zero,
174 [MODE_PCLR_REG] = intc_mode_field,
175};
134 176
135static void and_set_reg_32(struct intc_desc *desc, unsigned int data) 177static inline void _intc_enable(unsigned int irq, unsigned long handle)
136{ 178{
137 unsigned long addr = _INTC_PTR(desc, mask_regs, data)->set_reg; 179 struct intc_desc_int *d = get_intc_desc(irq);
180 unsigned long addr = d->reg[_INTC_ADDR_E(handle)];
138 181
139 ctrl_outl(ctrl_inl(addr) & ~(1 << _INTC_BIT(data)), addr); 182 intc_enable_fns[_INTC_MODE(handle)](addr, handle,
183 intc_reg_fns[_INTC_FN(handle)],
184 irq);
140} 185}
141 186
142enum { REG_FN_ERROR=0,
143 REG_FN_DUAL_8, REG_FN_DUAL_32,
144 REG_FN_ENA_16, REG_FN_ENA_32,
145 REG_FN_PRIO_16, REG_FN_PRIO_32 };
146
147static struct {
148 void (*enable)(struct intc_desc *, unsigned int);
149 void (*disable)(struct intc_desc *, unsigned int);
150} intc_reg_fns[] = {
151 [REG_FN_DUAL_8] = { write_clr_reg_8, write_set_reg_8 },
152 [REG_FN_DUAL_32] = { write_clr_reg_32, write_set_reg_32 },
153 [REG_FN_ENA_16] = { or_set_reg_16, and_set_reg_16 },
154 [REG_FN_ENA_32] = { or_set_reg_32, and_set_reg_32 },
155 [REG_FN_PRIO_16] = { enable_prio_16, disable_prio_16 },
156 [REG_FN_PRIO_32] = { enable_prio_32, disable_prio_32 },
157};
158
159static void intc_enable(unsigned int irq) 187static void intc_enable(unsigned int irq)
160{ 188{
161 struct intc_desc *desc = get_intc_desc(irq); 189 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
162 unsigned int data = (unsigned int) get_irq_chip_data(irq);
163
164 intc_reg_fns[_INTC_FN(data)].enable(desc, data);
165} 190}
166 191
167static void intc_disable(unsigned int irq) 192static void intc_disable(unsigned int irq)
168{ 193{
169 struct intc_desc *desc = get_intc_desc(irq); 194 struct intc_desc_int *desc = get_intc_desc(irq);
170 unsigned int data = (unsigned int) get_irq_chip_data(irq); 195 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
196 unsigned long addr = desc->reg[_INTC_ADDR_D(handle)];
171 197
172 intc_reg_fns[_INTC_FN(data)].disable(desc, data); 198 intc_disable_fns[_INTC_MODE(handle)](addr, handle,
199 intc_reg_fns[_INTC_FN(handle)],
200 irq);
173} 201}
174 202
175static void set_sense_16(struct intc_desc *desc, unsigned int data) 203static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
204 unsigned int nr_hp,
205 unsigned int irq)
176{ 206{
177 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg; 207 int i;
178 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width; 208
179 unsigned int bit = _INTC_BIT(data); 209 for (i = 0; i < nr_hp; i++) {
180 unsigned int value = _INTC_VALUE(data); 210 if ((hp + i)->irq != irq)
211 continue;
212
213 return hp + i;
214 }
181 215
182 ctrl_outw(set_field(ctrl_inw(addr), value, width, bit), addr); 216 return NULL;
183} 217}
184 218
185static void set_sense_32(struct intc_desc *desc, unsigned int data) 219int intc_set_priority(unsigned int irq, unsigned int prio)
186{ 220{
187 unsigned long addr = _INTC_PTR(desc, sense_regs, data)->reg; 221 struct intc_desc_int *d = get_intc_desc(irq);
188 unsigned int width = _INTC_PTR(desc, sense_regs, data)->field_width; 222 struct intc_handle_int *ihp;
189 unsigned int bit = _INTC_BIT(data); 223
190 unsigned int value = _INTC_VALUE(data); 224 if (!intc_prio_level[irq] || prio <= 1)
225 return -EINVAL;
226
227 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
228 if (ihp) {
229 if (prio >= ((1 << _INTC_WIDTH(ihp->handle)) - 1))
230 return -EINVAL;
191 231
192 ctrl_outl(set_field(ctrl_inl(addr), value, width, bit), addr); 232 intc_prio_level[irq] = prio;
233
234 /*
235 * only set secondary masking method directly
236 * primary masking method is using intc_prio_level[irq]
237 * priority level will be set during next enable()
238 */
239
240 if (ihp->handle)
241 _intc_enable(irq, ihp->handle);
242 }
243 return 0;
193} 244}
194 245
195#define VALID(x) (x | 0x80) 246#define VALID(x) (x | 0x80)
@@ -203,92 +254,38 @@ static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
203 254
204static int intc_set_sense(unsigned int irq, unsigned int type) 255static int intc_set_sense(unsigned int irq, unsigned int type)
205{ 256{
206 struct intc_desc *desc = get_intc_desc(irq); 257 struct intc_desc_int *d = get_intc_desc(irq);
207 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK]; 258 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
208 unsigned int i, j, data, bit; 259 struct intc_handle_int *ihp;
209 intc_enum enum_id = 0; 260 unsigned long addr;
210
211 for (i = 0; i < desc->nr_vectors; i++) {
212 struct intc_vect *vect = desc->vectors + i;
213
214 if (evt2irq(vect->vect) != irq)
215 continue;
216 261
217 enum_id = vect->enum_id; 262 if (!value)
218 break;
219 }
220
221 if (!enum_id || !value || !desc->sense_regs)
222 return -EINVAL; 263 return -EINVAL;
223 264
224 value ^= VALID(0); 265 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
225 266 if (ihp) {
226 for (i = 0; i < desc->nr_sense_regs; i++) { 267 addr = d->reg[_INTC_ADDR_E(ihp->handle)];
227 struct intc_sense_reg *sr = desc->sense_regs + i; 268 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
228
229 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
230 if (sr->enum_ids[j] != enum_id)
231 continue;
232
233 bit = sr->reg_width - ((j + 1) * sr->field_width);
234 data = _INTC_MK(0, i, bit, value);
235
236 switch(sr->reg_width) {
237 case 16:
238 set_sense_16(desc, data);
239 break;
240 case 32:
241 set_sense_32(desc, data);
242 break;
243 }
244
245 return 0;
246 }
247 }
248
249 return -EINVAL;
250}
251
252static unsigned int __init intc_find_dual_handler(unsigned int width)
253{
254 switch (width) {
255 case 8:
256 return REG_FN_DUAL_8;
257 case 32:
258 return REG_FN_DUAL_32;
259 } 269 }
260 270 return 0;
261 BUG();
262 return REG_FN_ERROR;
263} 271}
264 272
265static unsigned int __init intc_find_prio_handler(unsigned int width) 273static unsigned int __init intc_get_reg(struct intc_desc_int *d,
274 unsigned long address)
266{ 275{
267 switch (width) { 276 unsigned int k;
268 case 16:
269 return REG_FN_PRIO_16;
270 case 32:
271 return REG_FN_PRIO_32;
272 }
273
274 BUG();
275 return REG_FN_ERROR;
276}
277 277
278static unsigned int __init intc_find_ena_handler(unsigned int width) 278 for (k = 0; k < d->nr_reg; k++) {
279{ 279 if (d->reg[k] == address)
280 switch (width) { 280 return k;
281 case 16:
282 return REG_FN_ENA_16;
283 case 32:
284 return REG_FN_ENA_32;
285 } 281 }
286 282
287 BUG(); 283 BUG();
288 return REG_FN_ERROR; 284 return 0;
289} 285}
290 286
291static intc_enum __init intc_grp_id(struct intc_desc *desc, intc_enum enum_id) 287static intc_enum __init intc_grp_id(struct intc_desc *desc,
288 intc_enum enum_id)
292{ 289{
293 struct intc_group *g = desc->groups; 290 struct intc_group *g = desc->groups;
294 unsigned int i, j; 291 unsigned int i, j;
@@ -333,10 +330,12 @@ static unsigned int __init intc_prio_value(struct intc_desc *desc,
333} 330}
334 331
335static unsigned int __init intc_mask_data(struct intc_desc *desc, 332static unsigned int __init intc_mask_data(struct intc_desc *desc,
333 struct intc_desc_int *d,
336 intc_enum enum_id, int do_grps) 334 intc_enum enum_id, int do_grps)
337{ 335{
338 struct intc_mask_reg *mr = desc->mask_regs; 336 struct intc_mask_reg *mr = desc->mask_regs;
339 unsigned int i, j, fn; 337 unsigned int i, j, fn, mode;
338 unsigned long reg_e, reg_d;
340 339
341 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) { 340 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
342 mr = desc->mask_regs + i; 341 mr = desc->mask_regs + i;
@@ -345,32 +344,46 @@ static unsigned int __init intc_mask_data(struct intc_desc *desc,
345 if (mr->enum_ids[j] != enum_id) 344 if (mr->enum_ids[j] != enum_id)
346 continue; 345 continue;
347 346
348 switch (mr->clr_reg) { 347 if (mr->set_reg && mr->clr_reg) {
349 case 1: /* 1 = enabled interrupt - "enable" register */ 348 fn = REG_FN_WRITE_BASE;
350 fn = intc_find_ena_handler(mr->reg_width); 349 mode = MODE_DUAL_REG;
351 break; 350 reg_e = mr->clr_reg;
352 default: 351 reg_d = mr->set_reg;
353 fn = intc_find_dual_handler(mr->reg_width); 352 } else {
353 fn = REG_FN_MODIFY_BASE;
354 if (mr->set_reg) {
355 mode = MODE_ENABLE_REG;
356 reg_e = mr->set_reg;
357 reg_d = mr->set_reg;
358 } else {
359 mode = MODE_MASK_REG;
360 reg_e = mr->clr_reg;
361 reg_d = mr->clr_reg;
362 }
354 } 363 }
355 364
356 if (fn == REG_FN_ERROR) 365 fn += (mr->reg_width >> 3) - 1;
357 return 0; 366 return _INTC_MK(fn, mode,
358 367 intc_get_reg(d, reg_e),
359 return _INTC_MK(fn, i, (mr->reg_width - 1) - j, 0); 368 intc_get_reg(d, reg_d),
369 1,
370 (mr->reg_width - 1) - j);
360 } 371 }
361 } 372 }
362 373
363 if (do_grps) 374 if (do_grps)
364 return intc_mask_data(desc, intc_grp_id(desc, enum_id), 0); 375 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
365 376
366 return 0; 377 return 0;
367} 378}
368 379
369static unsigned int __init intc_prio_data(struct intc_desc *desc, 380static unsigned int __init intc_prio_data(struct intc_desc *desc,
381 struct intc_desc_int *d,
370 intc_enum enum_id, int do_grps) 382 intc_enum enum_id, int do_grps)
371{ 383{
372 struct intc_prio_reg *pr = desc->prio_regs; 384 struct intc_prio_reg *pr = desc->prio_regs;
373 unsigned int i, j, fn, bit, prio; 385 unsigned int i, j, fn, mode, bit;
386 unsigned long reg_e, reg_d;
374 387
375 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) { 388 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
376 pr = desc->prio_regs + i; 389 pr = desc->prio_regs + i;
@@ -379,26 +392,69 @@ static unsigned int __init intc_prio_data(struct intc_desc *desc,
379 if (pr->enum_ids[j] != enum_id) 392 if (pr->enum_ids[j] != enum_id)
380 continue; 393 continue;
381 394
382 fn = intc_find_prio_handler(pr->reg_width); 395 if (pr->set_reg && pr->clr_reg) {
383 if (fn == REG_FN_ERROR) 396 fn = REG_FN_WRITE_BASE;
384 return 0; 397 mode = MODE_PCLR_REG;
398 reg_e = pr->set_reg;
399 reg_d = pr->clr_reg;
400 } else {
401 fn = REG_FN_MODIFY_BASE;
402 mode = MODE_PRIO_REG;
403 if (!pr->set_reg)
404 BUG();
405 reg_e = pr->set_reg;
406 reg_d = pr->set_reg;
407 }
385 408
386 prio = intc_prio_value(desc, enum_id, 1); 409 fn += (pr->reg_width >> 3) - 1;
387 bit = pr->reg_width - ((j + 1) * pr->field_width); 410 bit = pr->reg_width - ((j + 1) * pr->field_width);
388 411
389 BUG_ON(bit < 0); 412 BUG_ON(bit < 0);
390 413
391 return _INTC_MK(fn, i, bit, prio); 414 return _INTC_MK(fn, mode,
415 intc_get_reg(d, reg_e),
416 intc_get_reg(d, reg_d),
417 pr->field_width, bit);
392 } 418 }
393 } 419 }
394 420
395 if (do_grps) 421 if (do_grps)
396 return intc_prio_data(desc, intc_grp_id(desc, enum_id), 0); 422 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
423
424 return 0;
425}
426
427static unsigned int __init intc_sense_data(struct intc_desc *desc,
428 struct intc_desc_int *d,
429 intc_enum enum_id)
430{
431 struct intc_sense_reg *sr = desc->sense_regs;
432 unsigned int i, j, fn, bit;
433
434 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
435 sr = desc->sense_regs + i;
436
437 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
438 if (sr->enum_ids[j] != enum_id)
439 continue;
440
441 fn = REG_FN_MODIFY_BASE;
442 fn += (sr->reg_width >> 3) - 1;
443 bit = sr->reg_width - ((j + 1) * sr->field_width);
444
445 BUG_ON(bit < 0);
446
447 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
448 0, sr->field_width, bit);
449 }
450 }
397 451
398 return 0; 452 return 0;
399} 453}
400 454
401static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id, 455static void __init intc_register_irq(struct intc_desc *desc,
456 struct intc_desc_int *d,
457 intc_enum enum_id,
402 unsigned int irq) 458 unsigned int irq)
403{ 459{
404 unsigned int data[2], primary; 460 unsigned int data[2], primary;
@@ -410,15 +466,15 @@ static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
410 * 4. priority, multiple interrupt sources (groups) 466 * 4. priority, multiple interrupt sources (groups)
411 */ 467 */
412 468
413 data[0] = intc_mask_data(desc, enum_id, 0); 469 data[0] = intc_mask_data(desc, d, enum_id, 0);
414 data[1] = intc_prio_data(desc, enum_id, 0); 470 data[1] = intc_prio_data(desc, d, enum_id, 0);
415 471
416 primary = 0; 472 primary = 0;
417 if (!data[0] && data[1]) 473 if (!data[0] && data[1])
418 primary = 1; 474 primary = 1;
419 475
420 data[0] = data[0] ? data[0] : intc_mask_data(desc, enum_id, 1); 476 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
421 data[1] = data[1] ? data[1] : intc_prio_data(desc, enum_id, 1); 477 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
422 478
423 if (!data[primary]) 479 if (!data[primary])
424 primary ^= 1; 480 primary ^= 1;
@@ -426,31 +482,91 @@ static void __init intc_register_irq(struct intc_desc *desc, intc_enum enum_id,
426 BUG_ON(!data[primary]); /* must have primary masking method */ 482 BUG_ON(!data[primary]); /* must have primary masking method */
427 483
428 disable_irq_nosync(irq); 484 disable_irq_nosync(irq);
429 set_irq_chip_and_handler_name(irq, &desc->chip, 485 set_irq_chip_and_handler_name(irq, &d->chip,
430 handle_level_irq, "level"); 486 handle_level_irq, "level");
431 set_irq_chip_data(irq, (void *)data[primary]); 487 set_irq_chip_data(irq, (void *)data[primary]);
432 488
489 /* record the desired priority level */
490 intc_prio_level[irq] = intc_prio_value(desc, enum_id, 1);
491
433 /* enable secondary masking method if present */ 492 /* enable secondary masking method if present */
434 if (data[!primary]) 493 if (data[!primary])
435 intc_reg_fns[_INTC_FN(data[!primary])].enable(desc, 494 _intc_enable(irq, data[!primary]);
436 data[!primary]); 495
496 /* add irq to d->prio list if priority is available */
497 if (data[1]) {
498 (d->prio + d->nr_prio)->irq = irq;
499 if (!primary) /* only secondary priority can access regs */
500 (d->prio + d->nr_prio)->handle = data[1];
501 d->nr_prio++;
502 }
503
504 /* add irq to d->sense list if sense is available */
505 data[0] = intc_sense_data(desc, d, enum_id);
506 if (data[0]) {
507 (d->sense + d->nr_sense)->irq = irq;
508 (d->sense + d->nr_sense)->handle = data[0];
509 d->nr_sense++;
510 }
437 511
438 /* irq should be disabled by default */ 512 /* irq should be disabled by default */
439 desc->chip.mask(irq); 513 d->chip.mask(irq);
440} 514}
441 515
442void __init register_intc_controller(struct intc_desc *desc) 516void __init register_intc_controller(struct intc_desc *desc)
443{ 517{
444 unsigned int i; 518 unsigned int i, k;
519 struct intc_desc_int *d;
520
521 d = alloc_bootmem(sizeof(*d));
522
523 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
524 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
525 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
526
527 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
528 k = 0;
529
530 if (desc->mask_regs) {
531 for (i = 0; i < desc->nr_mask_regs; i++) {
532 if (desc->mask_regs[i].set_reg)
533 d->reg[k++] = desc->mask_regs[i].set_reg;
534 if (desc->mask_regs[i].clr_reg)
535 d->reg[k++] = desc->mask_regs[i].clr_reg;
536 }
537 }
538
539 if (desc->prio_regs) {
540 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
541
542 for (i = 0; i < desc->nr_prio_regs; i++) {
543 if (desc->prio_regs[i].set_reg)
544 d->reg[k++] = desc->prio_regs[i].set_reg;
545 if (desc->prio_regs[i].clr_reg)
546 d->reg[k++] = desc->prio_regs[i].clr_reg;
547 }
548 }
549
550 if (desc->sense_regs) {
551 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
552
553 for (i = 0; i < desc->nr_sense_regs; i++) {
554 if (desc->sense_regs[i].reg)
555 d->reg[k++] = desc->sense_regs[i].reg;
556 }
557 }
558
559 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
445 560
446 desc->chip.mask = intc_disable; 561 d->chip.name = desc->name;
447 desc->chip.unmask = intc_enable; 562 d->chip.mask = intc_disable;
448 desc->chip.mask_ack = intc_disable; 563 d->chip.unmask = intc_enable;
449 desc->chip.set_type = intc_set_sense; 564 d->chip.mask_ack = intc_disable;
565 d->chip.set_type = intc_set_sense;
450 566
451 for (i = 0; i < desc->nr_vectors; i++) { 567 for (i = 0; i < desc->nr_vectors; i++) {
452 struct intc_vect *vect = desc->vectors + i; 568 struct intc_vect *vect = desc->vectors + i;
453 569
454 intc_register_irq(desc, vect->enum_id, evt2irq(vect->vect)); 570 intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
455 } 571 }
456} 572}
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-05 19:44:35 -0500